4 * Copyright (c) 2005-2007 CodeSourcery
5 * Written by Paul Brook
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
27 #include "qemu/qemu-print.h"
28 #include "exec/cpu_ldst.h"
29 #include "exec/translator.h"
31 #include "exec/helper-proto.h"
32 #include "exec/helper-gen.h"
34 #include "trace-tcg.h"
36 #include "fpu/softfloat.h"
39 //#define DEBUG_DISPATCH 1
41 #define DEFO32(name, offset) static TCGv QREG_##name;
42 #define DEFO64(name, offset) static TCGv_i64 QREG_##name;
47 static TCGv_i32 cpu_halted
;
48 static TCGv_i32 cpu_exception_index
;
50 static char cpu_reg_names
[2 * 8 * 3 + 5 * 4];
51 static TCGv cpu_dregs
[8];
52 static TCGv cpu_aregs
[8];
53 static TCGv_i64 cpu_macc
[4];
55 #define REG(insn, pos) (((insn) >> (pos)) & 7)
56 #define DREG(insn, pos) cpu_dregs[REG(insn, pos)]
57 #define AREG(insn, pos) get_areg(s, REG(insn, pos))
58 #define MACREG(acc) cpu_macc[acc]
59 #define QREG_SP get_areg(s, 7)
61 static TCGv NULL_QREG
;
62 #define IS_NULL_QREG(t) (t == NULL_QREG)
63 /* Used to distinguish stores from bad addressing modes. */
64 static TCGv store_dummy
;
66 #include "exec/gen-icount.h"
68 void m68k_tcg_init(void)
73 #define DEFO32(name, offset) \
74 QREG_##name = tcg_global_mem_new_i32(cpu_env, \
75 offsetof(CPUM68KState, offset), #name);
76 #define DEFO64(name, offset) \
77 QREG_##name = tcg_global_mem_new_i64(cpu_env, \
78 offsetof(CPUM68KState, offset), #name);
83 cpu_halted
= tcg_global_mem_new_i32(cpu_env
,
84 -offsetof(M68kCPU
, env
) +
85 offsetof(CPUState
, halted
), "HALTED");
86 cpu_exception_index
= tcg_global_mem_new_i32(cpu_env
,
87 -offsetof(M68kCPU
, env
) +
88 offsetof(CPUState
, exception_index
),
92 for (i
= 0; i
< 8; i
++) {
94 cpu_dregs
[i
] = tcg_global_mem_new(cpu_env
,
95 offsetof(CPUM68KState
, dregs
[i
]), p
);
98 cpu_aregs
[i
] = tcg_global_mem_new(cpu_env
,
99 offsetof(CPUM68KState
, aregs
[i
]), p
);
102 for (i
= 0; i
< 4; i
++) {
103 sprintf(p
, "ACC%d", i
);
104 cpu_macc
[i
] = tcg_global_mem_new_i64(cpu_env
,
105 offsetof(CPUM68KState
, macc
[i
]), p
);
109 NULL_QREG
= tcg_global_mem_new(cpu_env
, -4, "NULL");
110 store_dummy
= tcg_global_mem_new(cpu_env
, -8, "NULL");
113 /* internal defines */
114 typedef struct DisasContext
{
115 DisasContextBase base
;
118 CCOp cc_op
; /* Current CC operation */
124 #define MAX_TO_RELEASE 8
126 TCGv release
[MAX_TO_RELEASE
];
129 static void init_release_array(DisasContext
*s
)
131 #ifdef CONFIG_DEBUG_TCG
132 memset(s
->release
, 0, sizeof(s
->release
));
134 s
->release_count
= 0;
137 static void do_release(DisasContext
*s
)
140 for (i
= 0; i
< s
->release_count
; i
++) {
141 tcg_temp_free(s
->release
[i
]);
143 init_release_array(s
);
146 static TCGv
mark_to_release(DisasContext
*s
, TCGv tmp
)
148 g_assert(s
->release_count
< MAX_TO_RELEASE
);
149 return s
->release
[s
->release_count
++] = tmp
;
152 static TCGv
get_areg(DisasContext
*s
, unsigned regno
)
154 if (s
->writeback_mask
& (1 << regno
)) {
155 return s
->writeback
[regno
];
157 return cpu_aregs
[regno
];
161 static void delay_set_areg(DisasContext
*s
, unsigned regno
,
162 TCGv val
, bool give_temp
)
164 if (s
->writeback_mask
& (1 << regno
)) {
166 tcg_temp_free(s
->writeback
[regno
]);
167 s
->writeback
[regno
] = val
;
169 tcg_gen_mov_i32(s
->writeback
[regno
], val
);
172 s
->writeback_mask
|= 1 << regno
;
174 s
->writeback
[regno
] = val
;
176 TCGv tmp
= tcg_temp_new();
177 s
->writeback
[regno
] = tmp
;
178 tcg_gen_mov_i32(tmp
, val
);
183 static void do_writebacks(DisasContext
*s
)
185 unsigned mask
= s
->writeback_mask
;
187 s
->writeback_mask
= 0;
189 unsigned regno
= ctz32(mask
);
190 tcg_gen_mov_i32(cpu_aregs
[regno
], s
->writeback
[regno
]);
191 tcg_temp_free(s
->writeback
[regno
]);
197 /* is_jmp field values */
198 #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
199 #define DISAS_EXIT DISAS_TARGET_1 /* cpu state was modified dynamically */
201 #if defined(CONFIG_USER_ONLY)
204 #define IS_USER(s) (!(s->base.tb->flags & TB_FLAGS_MSR_S))
205 #define SFC_INDEX(s) ((s->base.tb->flags & TB_FLAGS_SFC_S) ? \
206 MMU_KERNEL_IDX : MMU_USER_IDX)
207 #define DFC_INDEX(s) ((s->base.tb->flags & TB_FLAGS_DFC_S) ? \
208 MMU_KERNEL_IDX : MMU_USER_IDX)
211 typedef void (*disas_proc
)(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
);
213 #ifdef DEBUG_DISPATCH
214 #define DISAS_INSN(name) \
215 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
217 static void disas_##name(CPUM68KState *env, DisasContext *s, \
220 qemu_log("Dispatch " #name "\n"); \
221 real_disas_##name(env, s, insn); \
223 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
226 #define DISAS_INSN(name) \
227 static void disas_##name(CPUM68KState *env, DisasContext *s, \
231 static const uint8_t cc_op_live
[CC_OP_NB
] = {
232 [CC_OP_DYNAMIC
] = CCF_C
| CCF_V
| CCF_Z
| CCF_N
| CCF_X
,
233 [CC_OP_FLAGS
] = CCF_C
| CCF_V
| CCF_Z
| CCF_N
| CCF_X
,
234 [CC_OP_ADDB
... CC_OP_ADDL
] = CCF_X
| CCF_N
| CCF_V
,
235 [CC_OP_SUBB
... CC_OP_SUBL
] = CCF_X
| CCF_N
| CCF_V
,
236 [CC_OP_CMPB
... CC_OP_CMPL
] = CCF_X
| CCF_N
| CCF_V
,
237 [CC_OP_LOGIC
] = CCF_X
| CCF_N
240 static void set_cc_op(DisasContext
*s
, CCOp op
)
242 CCOp old_op
= s
->cc_op
;
252 * Discard CC computation that will no longer be used.
253 * Note that X and N are never dead.
255 dead
= cc_op_live
[old_op
] & ~cc_op_live
[op
];
257 tcg_gen_discard_i32(QREG_CC_C
);
260 tcg_gen_discard_i32(QREG_CC_Z
);
263 tcg_gen_discard_i32(QREG_CC_V
);
267 /* Update the CPU env CC_OP state. */
268 static void update_cc_op(DisasContext
*s
)
270 if (!s
->cc_op_synced
) {
272 tcg_gen_movi_i32(QREG_CC_OP
, s
->cc_op
);
276 /* Generate a jump to an immediate address. */
277 static void gen_jmp_im(DisasContext
*s
, uint32_t dest
)
280 tcg_gen_movi_i32(QREG_PC
, dest
);
281 s
->base
.is_jmp
= DISAS_JUMP
;
284 /* Generate a jump to the address in qreg DEST. */
285 static void gen_jmp(DisasContext
*s
, TCGv dest
)
288 tcg_gen_mov_i32(QREG_PC
, dest
);
289 s
->base
.is_jmp
= DISAS_JUMP
;
292 static void gen_exception(DisasContext
*s
, uint32_t dest
, int nr
)
297 tcg_gen_movi_i32(QREG_PC
, dest
);
299 tmp
= tcg_const_i32(nr
);
300 gen_helper_raise_exception(cpu_env
, tmp
);
301 tcg_temp_free_i32(tmp
);
303 s
->base
.is_jmp
= DISAS_NORETURN
;
306 static inline void gen_addr_fault(DisasContext
*s
)
308 gen_exception(s
, s
->base
.pc_next
, EXCP_ADDRESS
);
312 * Generate a load from the specified address. Narrow values are
313 * sign extended to full register width.
315 static inline TCGv
gen_load(DisasContext
*s
, int opsize
, TCGv addr
,
319 tmp
= tcg_temp_new_i32();
323 tcg_gen_qemu_ld8s(tmp
, addr
, index
);
325 tcg_gen_qemu_ld8u(tmp
, addr
, index
);
329 tcg_gen_qemu_ld16s(tmp
, addr
, index
);
331 tcg_gen_qemu_ld16u(tmp
, addr
, index
);
334 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
337 g_assert_not_reached();
342 /* Generate a store. */
343 static inline void gen_store(DisasContext
*s
, int opsize
, TCGv addr
, TCGv val
,
348 tcg_gen_qemu_st8(val
, addr
, index
);
351 tcg_gen_qemu_st16(val
, addr
, index
);
354 tcg_gen_qemu_st32(val
, addr
, index
);
357 g_assert_not_reached();
368 * Generate an unsigned load if VAL is 0 a signed load if val is -1,
369 * otherwise generate a store.
371 static TCGv
gen_ldst(DisasContext
*s
, int opsize
, TCGv addr
, TCGv val
,
372 ea_what what
, int index
)
374 if (what
== EA_STORE
) {
375 gen_store(s
, opsize
, addr
, val
, index
);
378 return mark_to_release(s
, gen_load(s
, opsize
, addr
,
379 what
== EA_LOADS
, index
));
383 /* Read a 16-bit immediate constant */
384 static inline uint16_t read_im16(CPUM68KState
*env
, DisasContext
*s
)
387 im
= translator_lduw(env
, s
->pc
);
392 /* Read an 8-bit immediate constant */
393 static inline uint8_t read_im8(CPUM68KState
*env
, DisasContext
*s
)
395 return read_im16(env
, s
);
398 /* Read a 32-bit immediate constant. */
399 static inline uint32_t read_im32(CPUM68KState
*env
, DisasContext
*s
)
402 im
= read_im16(env
, s
) << 16;
403 im
|= 0xffff & read_im16(env
, s
);
407 /* Read a 64-bit immediate constant. */
408 static inline uint64_t read_im64(CPUM68KState
*env
, DisasContext
*s
)
411 im
= (uint64_t)read_im32(env
, s
) << 32;
412 im
|= (uint64_t)read_im32(env
, s
);
416 /* Calculate and address index. */
417 static TCGv
gen_addr_index(DisasContext
*s
, uint16_t ext
, TCGv tmp
)
422 add
= (ext
& 0x8000) ? AREG(ext
, 12) : DREG(ext
, 12);
423 if ((ext
& 0x800) == 0) {
424 tcg_gen_ext16s_i32(tmp
, add
);
427 scale
= (ext
>> 9) & 3;
429 tcg_gen_shli_i32(tmp
, add
, scale
);
436 * Handle a base + index + displacement effective addresss.
437 * A NULL_QREG base means pc-relative.
439 static TCGv
gen_lea_indexed(CPUM68KState
*env
, DisasContext
*s
, TCGv base
)
448 ext
= read_im16(env
, s
);
450 if ((ext
& 0x800) == 0 && !m68k_feature(s
->env
, M68K_FEATURE_WORD_INDEX
))
453 if (m68k_feature(s
->env
, M68K_FEATURE_M68000
) &&
454 !m68k_feature(s
->env
, M68K_FEATURE_SCALED_INDEX
)) {
459 /* full extension word format */
460 if (!m68k_feature(s
->env
, M68K_FEATURE_EXT_FULL
))
463 if ((ext
& 0x30) > 0x10) {
464 /* base displacement */
465 if ((ext
& 0x30) == 0x20) {
466 bd
= (int16_t)read_im16(env
, s
);
468 bd
= read_im32(env
, s
);
473 tmp
= mark_to_release(s
, tcg_temp_new());
474 if ((ext
& 0x44) == 0) {
476 add
= gen_addr_index(s
, ext
, tmp
);
480 if ((ext
& 0x80) == 0) {
481 /* base not suppressed */
482 if (IS_NULL_QREG(base
)) {
483 base
= mark_to_release(s
, tcg_const_i32(offset
+ bd
));
486 if (!IS_NULL_QREG(add
)) {
487 tcg_gen_add_i32(tmp
, add
, base
);
493 if (!IS_NULL_QREG(add
)) {
495 tcg_gen_addi_i32(tmp
, add
, bd
);
499 add
= mark_to_release(s
, tcg_const_i32(bd
));
501 if ((ext
& 3) != 0) {
502 /* memory indirect */
503 base
= mark_to_release(s
, gen_load(s
, OS_LONG
, add
, 0, IS_USER(s
)));
504 if ((ext
& 0x44) == 4) {
505 add
= gen_addr_index(s
, ext
, tmp
);
506 tcg_gen_add_i32(tmp
, add
, base
);
512 /* outer displacement */
513 if ((ext
& 3) == 2) {
514 od
= (int16_t)read_im16(env
, s
);
516 od
= read_im32(env
, s
);
522 tcg_gen_addi_i32(tmp
, add
, od
);
527 /* brief extension word format */
528 tmp
= mark_to_release(s
, tcg_temp_new());
529 add
= gen_addr_index(s
, ext
, tmp
);
530 if (!IS_NULL_QREG(base
)) {
531 tcg_gen_add_i32(tmp
, add
, base
);
533 tcg_gen_addi_i32(tmp
, tmp
, (int8_t)ext
);
535 tcg_gen_addi_i32(tmp
, add
, offset
+ (int8_t)ext
);
542 /* Sign or zero extend a value. */
544 static inline void gen_ext(TCGv res
, TCGv val
, int opsize
, int sign
)
549 tcg_gen_ext8s_i32(res
, val
);
551 tcg_gen_ext8u_i32(res
, val
);
556 tcg_gen_ext16s_i32(res
, val
);
558 tcg_gen_ext16u_i32(res
, val
);
562 tcg_gen_mov_i32(res
, val
);
565 g_assert_not_reached();
569 /* Evaluate all the CC flags. */
571 static void gen_flush_flags(DisasContext
*s
)
582 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
583 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
584 /* Compute signed overflow for addition. */
587 tcg_gen_sub_i32(t0
, QREG_CC_N
, QREG_CC_V
);
588 gen_ext(t0
, t0
, s
->cc_op
- CC_OP_ADDB
, 1);
589 tcg_gen_xor_i32(t1
, QREG_CC_N
, QREG_CC_V
);
590 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_V
, t0
);
592 tcg_gen_andc_i32(QREG_CC_V
, t1
, QREG_CC_V
);
599 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
600 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
601 /* Compute signed overflow for subtraction. */
604 tcg_gen_add_i32(t0
, QREG_CC_N
, QREG_CC_V
);
605 gen_ext(t0
, t0
, s
->cc_op
- CC_OP_SUBB
, 1);
606 tcg_gen_xor_i32(t1
, QREG_CC_N
, t0
);
607 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_V
, t0
);
609 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_V
, t1
);
616 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_C
, QREG_CC_N
, QREG_CC_V
);
617 tcg_gen_sub_i32(QREG_CC_Z
, QREG_CC_N
, QREG_CC_V
);
618 gen_ext(QREG_CC_Z
, QREG_CC_Z
, s
->cc_op
- CC_OP_CMPB
, 1);
619 /* Compute signed overflow for subtraction. */
621 tcg_gen_xor_i32(t0
, QREG_CC_Z
, QREG_CC_N
);
622 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_V
, QREG_CC_N
);
623 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_V
, t0
);
625 tcg_gen_mov_i32(QREG_CC_N
, QREG_CC_Z
);
629 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
630 tcg_gen_movi_i32(QREG_CC_C
, 0);
631 tcg_gen_movi_i32(QREG_CC_V
, 0);
635 gen_helper_flush_flags(cpu_env
, QREG_CC_OP
);
640 t0
= tcg_const_i32(s
->cc_op
);
641 gen_helper_flush_flags(cpu_env
, t0
);
647 /* Note that flush_flags also assigned to env->cc_op. */
648 s
->cc_op
= CC_OP_FLAGS
;
651 static inline TCGv
gen_extend(DisasContext
*s
, TCGv val
, int opsize
, int sign
)
655 if (opsize
== OS_LONG
) {
658 tmp
= mark_to_release(s
, tcg_temp_new());
659 gen_ext(tmp
, val
, opsize
, sign
);
665 static void gen_logic_cc(DisasContext
*s
, TCGv val
, int opsize
)
667 gen_ext(QREG_CC_N
, val
, opsize
, 1);
668 set_cc_op(s
, CC_OP_LOGIC
);
671 static void gen_update_cc_cmp(DisasContext
*s
, TCGv dest
, TCGv src
, int opsize
)
673 tcg_gen_mov_i32(QREG_CC_N
, dest
);
674 tcg_gen_mov_i32(QREG_CC_V
, src
);
675 set_cc_op(s
, CC_OP_CMPB
+ opsize
);
678 static void gen_update_cc_add(TCGv dest
, TCGv src
, int opsize
)
680 gen_ext(QREG_CC_N
, dest
, opsize
, 1);
681 tcg_gen_mov_i32(QREG_CC_V
, src
);
684 static inline int opsize_bytes(int opsize
)
687 case OS_BYTE
: return 1;
688 case OS_WORD
: return 2;
689 case OS_LONG
: return 4;
690 case OS_SINGLE
: return 4;
691 case OS_DOUBLE
: return 8;
692 case OS_EXTENDED
: return 12;
693 case OS_PACKED
: return 12;
695 g_assert_not_reached();
699 static inline int insn_opsize(int insn
)
701 switch ((insn
>> 6) & 3) {
702 case 0: return OS_BYTE
;
703 case 1: return OS_WORD
;
704 case 2: return OS_LONG
;
706 g_assert_not_reached();
710 static inline int ext_opsize(int ext
, int pos
)
712 switch ((ext
>> pos
) & 7) {
713 case 0: return OS_LONG
;
714 case 1: return OS_SINGLE
;
715 case 2: return OS_EXTENDED
;
716 case 3: return OS_PACKED
;
717 case 4: return OS_WORD
;
718 case 5: return OS_DOUBLE
;
719 case 6: return OS_BYTE
;
721 g_assert_not_reached();
726 * Assign value to a register. If the width is less than the register width
727 * only the low part of the register is set.
729 static void gen_partset_reg(int opsize
, TCGv reg
, TCGv val
)
734 tcg_gen_andi_i32(reg
, reg
, 0xffffff00);
735 tmp
= tcg_temp_new();
736 tcg_gen_ext8u_i32(tmp
, val
);
737 tcg_gen_or_i32(reg
, reg
, tmp
);
741 tcg_gen_andi_i32(reg
, reg
, 0xffff0000);
742 tmp
= tcg_temp_new();
743 tcg_gen_ext16u_i32(tmp
, val
);
744 tcg_gen_or_i32(reg
, reg
, tmp
);
749 tcg_gen_mov_i32(reg
, val
);
752 g_assert_not_reached();
757 * Generate code for an "effective address". Does not adjust the base
758 * register for autoincrement addressing modes.
760 static TCGv
gen_lea_mode(CPUM68KState
*env
, DisasContext
*s
,
761 int mode
, int reg0
, int opsize
)
769 case 0: /* Data register direct. */
770 case 1: /* Address register direct. */
772 case 3: /* Indirect postincrement. */
773 if (opsize
== OS_UNSIZED
) {
777 case 2: /* Indirect register */
778 return get_areg(s
, reg0
);
779 case 4: /* Indirect predecrememnt. */
780 if (opsize
== OS_UNSIZED
) {
783 reg
= get_areg(s
, reg0
);
784 tmp
= mark_to_release(s
, tcg_temp_new());
785 if (reg0
== 7 && opsize
== OS_BYTE
&&
786 m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
787 tcg_gen_subi_i32(tmp
, reg
, 2);
789 tcg_gen_subi_i32(tmp
, reg
, opsize_bytes(opsize
));
792 case 5: /* Indirect displacement. */
793 reg
= get_areg(s
, reg0
);
794 tmp
= mark_to_release(s
, tcg_temp_new());
795 ext
= read_im16(env
, s
);
796 tcg_gen_addi_i32(tmp
, reg
, (int16_t)ext
);
798 case 6: /* Indirect index + displacement. */
799 reg
= get_areg(s
, reg0
);
800 return gen_lea_indexed(env
, s
, reg
);
803 case 0: /* Absolute short. */
804 offset
= (int16_t)read_im16(env
, s
);
805 return mark_to_release(s
, tcg_const_i32(offset
));
806 case 1: /* Absolute long. */
807 offset
= read_im32(env
, s
);
808 return mark_to_release(s
, tcg_const_i32(offset
));
809 case 2: /* pc displacement */
811 offset
+= (int16_t)read_im16(env
, s
);
812 return mark_to_release(s
, tcg_const_i32(offset
));
813 case 3: /* pc index+displacement. */
814 return gen_lea_indexed(env
, s
, NULL_QREG
);
815 case 4: /* Immediate. */
820 /* Should never happen. */
824 static TCGv
gen_lea(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
827 int mode
= extract32(insn
, 3, 3);
828 int reg0
= REG(insn
, 0);
829 return gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
833 * Generate code to load/store a value from/into an EA. If WHAT > 0 this is
834 * a write otherwise it is a read (0 == sign extend, -1 == zero extend).
835 * ADDRP is non-null for readwrite operands.
837 static TCGv
gen_ea_mode(CPUM68KState
*env
, DisasContext
*s
, int mode
, int reg0
,
838 int opsize
, TCGv val
, TCGv
*addrp
, ea_what what
,
841 TCGv reg
, tmp
, result
;
845 case 0: /* Data register direct. */
846 reg
= cpu_dregs
[reg0
];
847 if (what
== EA_STORE
) {
848 gen_partset_reg(opsize
, reg
, val
);
851 return gen_extend(s
, reg
, opsize
, what
== EA_LOADS
);
853 case 1: /* Address register direct. */
854 reg
= get_areg(s
, reg0
);
855 if (what
== EA_STORE
) {
856 tcg_gen_mov_i32(reg
, val
);
859 return gen_extend(s
, reg
, opsize
, what
== EA_LOADS
);
861 case 2: /* Indirect register */
862 reg
= get_areg(s
, reg0
);
863 return gen_ldst(s
, opsize
, reg
, val
, what
, index
);
864 case 3: /* Indirect postincrement. */
865 reg
= get_areg(s
, reg0
);
866 result
= gen_ldst(s
, opsize
, reg
, val
, what
, index
);
867 if (what
== EA_STORE
|| !addrp
) {
868 TCGv tmp
= tcg_temp_new();
869 if (reg0
== 7 && opsize
== OS_BYTE
&&
870 m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
871 tcg_gen_addi_i32(tmp
, reg
, 2);
873 tcg_gen_addi_i32(tmp
, reg
, opsize_bytes(opsize
));
875 delay_set_areg(s
, reg0
, tmp
, true);
878 case 4: /* Indirect predecrememnt. */
879 if (addrp
&& what
== EA_STORE
) {
882 tmp
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
883 if (IS_NULL_QREG(tmp
)) {
890 result
= gen_ldst(s
, opsize
, tmp
, val
, what
, index
);
891 if (what
== EA_STORE
|| !addrp
) {
892 delay_set_areg(s
, reg0
, tmp
, false);
895 case 5: /* Indirect displacement. */
896 case 6: /* Indirect index + displacement. */
898 if (addrp
&& what
== EA_STORE
) {
901 tmp
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
902 if (IS_NULL_QREG(tmp
)) {
909 return gen_ldst(s
, opsize
, tmp
, val
, what
, index
);
912 case 0: /* Absolute short. */
913 case 1: /* Absolute long. */
914 case 2: /* pc displacement */
915 case 3: /* pc index+displacement. */
917 case 4: /* Immediate. */
918 /* Sign extend values for consistency. */
921 if (what
== EA_LOADS
) {
922 offset
= (int8_t)read_im8(env
, s
);
924 offset
= read_im8(env
, s
);
928 if (what
== EA_LOADS
) {
929 offset
= (int16_t)read_im16(env
, s
);
931 offset
= read_im16(env
, s
);
935 offset
= read_im32(env
, s
);
938 g_assert_not_reached();
940 return mark_to_release(s
, tcg_const_i32(offset
));
945 /* Should never happen. */
949 static TCGv
gen_ea(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
950 int opsize
, TCGv val
, TCGv
*addrp
, ea_what what
, int index
)
952 int mode
= extract32(insn
, 3, 3);
953 int reg0
= REG(insn
, 0);
954 return gen_ea_mode(env
, s
, mode
, reg0
, opsize
, val
, addrp
, what
, index
);
957 static TCGv_ptr
gen_fp_ptr(int freg
)
959 TCGv_ptr fp
= tcg_temp_new_ptr();
960 tcg_gen_addi_ptr(fp
, cpu_env
, offsetof(CPUM68KState
, fregs
[freg
]));
964 static TCGv_ptr
gen_fp_result_ptr(void)
966 TCGv_ptr fp
= tcg_temp_new_ptr();
967 tcg_gen_addi_ptr(fp
, cpu_env
, offsetof(CPUM68KState
, fp_result
));
971 static void gen_fp_move(TCGv_ptr dest
, TCGv_ptr src
)
976 t32
= tcg_temp_new();
977 tcg_gen_ld16u_i32(t32
, src
, offsetof(FPReg
, l
.upper
));
978 tcg_gen_st16_i32(t32
, dest
, offsetof(FPReg
, l
.upper
));
981 t64
= tcg_temp_new_i64();
982 tcg_gen_ld_i64(t64
, src
, offsetof(FPReg
, l
.lower
));
983 tcg_gen_st_i64(t64
, dest
, offsetof(FPReg
, l
.lower
));
984 tcg_temp_free_i64(t64
);
987 static void gen_load_fp(DisasContext
*s
, int opsize
, TCGv addr
, TCGv_ptr fp
,
993 t64
= tcg_temp_new_i64();
994 tmp
= tcg_temp_new();
997 tcg_gen_qemu_ld8s(tmp
, addr
, index
);
998 gen_helper_exts32(cpu_env
, fp
, tmp
);
1001 tcg_gen_qemu_ld16s(tmp
, addr
, index
);
1002 gen_helper_exts32(cpu_env
, fp
, tmp
);
1005 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
1006 gen_helper_exts32(cpu_env
, fp
, tmp
);
1009 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
1010 gen_helper_extf32(cpu_env
, fp
, tmp
);
1013 tcg_gen_qemu_ld64(t64
, addr
, index
);
1014 gen_helper_extf64(cpu_env
, fp
, t64
);
1017 if (m68k_feature(s
->env
, M68K_FEATURE_CF_FPU
)) {
1018 gen_exception(s
, s
->base
.pc_next
, EXCP_FP_UNIMP
);
1021 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
1022 tcg_gen_shri_i32(tmp
, tmp
, 16);
1023 tcg_gen_st16_i32(tmp
, fp
, offsetof(FPReg
, l
.upper
));
1024 tcg_gen_addi_i32(tmp
, addr
, 4);
1025 tcg_gen_qemu_ld64(t64
, tmp
, index
);
1026 tcg_gen_st_i64(t64
, fp
, offsetof(FPReg
, l
.lower
));
1030 * unimplemented data type on 68040/ColdFire
1031 * FIXME if needed for another FPU
1033 gen_exception(s
, s
->base
.pc_next
, EXCP_FP_UNIMP
);
1036 g_assert_not_reached();
1039 tcg_temp_free_i64(t64
);
1042 static void gen_store_fp(DisasContext
*s
, int opsize
, TCGv addr
, TCGv_ptr fp
,
1048 t64
= tcg_temp_new_i64();
1049 tmp
= tcg_temp_new();
1052 gen_helper_reds32(tmp
, cpu_env
, fp
);
1053 tcg_gen_qemu_st8(tmp
, addr
, index
);
1056 gen_helper_reds32(tmp
, cpu_env
, fp
);
1057 tcg_gen_qemu_st16(tmp
, addr
, index
);
1060 gen_helper_reds32(tmp
, cpu_env
, fp
);
1061 tcg_gen_qemu_st32(tmp
, addr
, index
);
1064 gen_helper_redf32(tmp
, cpu_env
, fp
);
1065 tcg_gen_qemu_st32(tmp
, addr
, index
);
1068 gen_helper_redf64(t64
, cpu_env
, fp
);
1069 tcg_gen_qemu_st64(t64
, addr
, index
);
1072 if (m68k_feature(s
->env
, M68K_FEATURE_CF_FPU
)) {
1073 gen_exception(s
, s
->base
.pc_next
, EXCP_FP_UNIMP
);
1076 tcg_gen_ld16u_i32(tmp
, fp
, offsetof(FPReg
, l
.upper
));
1077 tcg_gen_shli_i32(tmp
, tmp
, 16);
1078 tcg_gen_qemu_st32(tmp
, addr
, index
);
1079 tcg_gen_addi_i32(tmp
, addr
, 4);
1080 tcg_gen_ld_i64(t64
, fp
, offsetof(FPReg
, l
.lower
));
1081 tcg_gen_qemu_st64(t64
, tmp
, index
);
1085 * unimplemented data type on 68040/ColdFire
1086 * FIXME if needed for another FPU
1088 gen_exception(s
, s
->base
.pc_next
, EXCP_FP_UNIMP
);
1091 g_assert_not_reached();
1094 tcg_temp_free_i64(t64
);
1097 static void gen_ldst_fp(DisasContext
*s
, int opsize
, TCGv addr
,
1098 TCGv_ptr fp
, ea_what what
, int index
)
1100 if (what
== EA_STORE
) {
1101 gen_store_fp(s
, opsize
, addr
, fp
, index
);
1103 gen_load_fp(s
, opsize
, addr
, fp
, index
);
1107 static int gen_ea_mode_fp(CPUM68KState
*env
, DisasContext
*s
, int mode
,
1108 int reg0
, int opsize
, TCGv_ptr fp
, ea_what what
,
1111 TCGv reg
, addr
, tmp
;
1115 case 0: /* Data register direct. */
1116 reg
= cpu_dregs
[reg0
];
1117 if (what
== EA_STORE
) {
1122 gen_helper_reds32(reg
, cpu_env
, fp
);
1125 gen_helper_redf32(reg
, cpu_env
, fp
);
1128 g_assert_not_reached();
1131 tmp
= tcg_temp_new();
1134 tcg_gen_ext8s_i32(tmp
, reg
);
1135 gen_helper_exts32(cpu_env
, fp
, tmp
);
1138 tcg_gen_ext16s_i32(tmp
, reg
);
1139 gen_helper_exts32(cpu_env
, fp
, tmp
);
1142 gen_helper_exts32(cpu_env
, fp
, reg
);
1145 gen_helper_extf32(cpu_env
, fp
, reg
);
1148 g_assert_not_reached();
1153 case 1: /* Address register direct. */
1155 case 2: /* Indirect register */
1156 addr
= get_areg(s
, reg0
);
1157 gen_ldst_fp(s
, opsize
, addr
, fp
, what
, index
);
1159 case 3: /* Indirect postincrement. */
1160 addr
= cpu_aregs
[reg0
];
1161 gen_ldst_fp(s
, opsize
, addr
, fp
, what
, index
);
1162 tcg_gen_addi_i32(addr
, addr
, opsize_bytes(opsize
));
1164 case 4: /* Indirect predecrememnt. */
1165 addr
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
1166 if (IS_NULL_QREG(addr
)) {
1169 gen_ldst_fp(s
, opsize
, addr
, fp
, what
, index
);
1170 tcg_gen_mov_i32(cpu_aregs
[reg0
], addr
);
1172 case 5: /* Indirect displacement. */
1173 case 6: /* Indirect index + displacement. */
1175 addr
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
1176 if (IS_NULL_QREG(addr
)) {
1179 gen_ldst_fp(s
, opsize
, addr
, fp
, what
, index
);
1183 case 0: /* Absolute short. */
1184 case 1: /* Absolute long. */
1185 case 2: /* pc displacement */
1186 case 3: /* pc index+displacement. */
1188 case 4: /* Immediate. */
1189 if (what
== EA_STORE
) {
1194 tmp
= tcg_const_i32((int8_t)read_im8(env
, s
));
1195 gen_helper_exts32(cpu_env
, fp
, tmp
);
1199 tmp
= tcg_const_i32((int16_t)read_im16(env
, s
));
1200 gen_helper_exts32(cpu_env
, fp
, tmp
);
1204 tmp
= tcg_const_i32(read_im32(env
, s
));
1205 gen_helper_exts32(cpu_env
, fp
, tmp
);
1209 tmp
= tcg_const_i32(read_im32(env
, s
));
1210 gen_helper_extf32(cpu_env
, fp
, tmp
);
1214 t64
= tcg_const_i64(read_im64(env
, s
));
1215 gen_helper_extf64(cpu_env
, fp
, t64
);
1216 tcg_temp_free_i64(t64
);
1219 if (m68k_feature(s
->env
, M68K_FEATURE_CF_FPU
)) {
1220 gen_exception(s
, s
->base
.pc_next
, EXCP_FP_UNIMP
);
1223 tmp
= tcg_const_i32(read_im32(env
, s
) >> 16);
1224 tcg_gen_st16_i32(tmp
, fp
, offsetof(FPReg
, l
.upper
));
1226 t64
= tcg_const_i64(read_im64(env
, s
));
1227 tcg_gen_st_i64(t64
, fp
, offsetof(FPReg
, l
.lower
));
1228 tcg_temp_free_i64(t64
);
1232 * unimplemented data type on 68040/ColdFire
1233 * FIXME if needed for another FPU
1235 gen_exception(s
, s
->base
.pc_next
, EXCP_FP_UNIMP
);
1238 g_assert_not_reached();
1248 static int gen_ea_fp(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
1249 int opsize
, TCGv_ptr fp
, ea_what what
, int index
)
1251 int mode
= extract32(insn
, 3, 3);
1252 int reg0
= REG(insn
, 0);
1253 return gen_ea_mode_fp(env
, s
, mode
, reg0
, opsize
, fp
, what
, index
);
1264 static void gen_cc_cond(DisasCompare
*c
, DisasContext
*s
, int cond
)
1270 /* The CC_OP_CMP form can handle most normal comparisons directly. */
1271 if (op
== CC_OP_CMPB
|| op
== CC_OP_CMPW
|| op
== CC_OP_CMPL
) {
1278 tcond
= TCG_COND_LEU
;
1282 tcond
= TCG_COND_LTU
;
1286 tcond
= TCG_COND_EQ
;
1291 c
->v2
= tcg_const_i32(0);
1292 c
->v1
= tmp
= tcg_temp_new();
1293 tcg_gen_sub_i32(tmp
, QREG_CC_N
, QREG_CC_V
);
1294 gen_ext(tmp
, tmp
, op
- CC_OP_CMPB
, 1);
1298 tcond
= TCG_COND_LT
;
1302 tcond
= TCG_COND_LE
;
1309 c
->v2
= tcg_const_i32(0);
1315 tcond
= TCG_COND_NEVER
;
1317 case 14: /* GT (!(Z || (N ^ V))) */
1318 case 15: /* LE (Z || (N ^ V)) */
1320 * Logic operations clear V, which simplifies LE to (Z || N),
1321 * and since Z and N are co-located, this becomes a normal
1324 if (op
== CC_OP_LOGIC
) {
1326 tcond
= TCG_COND_LE
;
1330 case 12: /* GE (!(N ^ V)) */
1331 case 13: /* LT (N ^ V) */
1332 /* Logic operations clear V, which simplifies this to N. */
1333 if (op
!= CC_OP_LOGIC
) {
1337 case 10: /* PL (!N) */
1338 case 11: /* MI (N) */
1339 /* Several cases represent N normally. */
1340 if (op
== CC_OP_ADDB
|| op
== CC_OP_ADDW
|| op
== CC_OP_ADDL
||
1341 op
== CC_OP_SUBB
|| op
== CC_OP_SUBW
|| op
== CC_OP_SUBL
||
1342 op
== CC_OP_LOGIC
) {
1344 tcond
= TCG_COND_LT
;
1348 case 6: /* NE (!Z) */
1349 case 7: /* EQ (Z) */
1350 /* Some cases fold Z into N. */
1351 if (op
== CC_OP_ADDB
|| op
== CC_OP_ADDW
|| op
== CC_OP_ADDL
||
1352 op
== CC_OP_SUBB
|| op
== CC_OP_SUBW
|| op
== CC_OP_SUBL
||
1353 op
== CC_OP_LOGIC
) {
1354 tcond
= TCG_COND_EQ
;
1359 case 4: /* CC (!C) */
1360 case 5: /* CS (C) */
1361 /* Some cases fold C into X. */
1362 if (op
== CC_OP_ADDB
|| op
== CC_OP_ADDW
|| op
== CC_OP_ADDL
||
1363 op
== CC_OP_SUBB
|| op
== CC_OP_SUBW
|| op
== CC_OP_SUBL
) {
1364 tcond
= TCG_COND_NE
;
1369 case 8: /* VC (!V) */
1370 case 9: /* VS (V) */
1371 /* Logic operations clear V and C. */
1372 if (op
== CC_OP_LOGIC
) {
1373 tcond
= TCG_COND_NEVER
;
1380 /* Otherwise, flush flag state to CC_OP_FLAGS. */
1387 /* Invalid, or handled above. */
1389 case 2: /* HI (!C && !Z) -> !(C || Z)*/
1390 case 3: /* LS (C || Z) */
1391 c
->v1
= tmp
= tcg_temp_new();
1393 tcg_gen_setcond_i32(TCG_COND_EQ
, tmp
, QREG_CC_Z
, c
->v2
);
1394 tcg_gen_or_i32(tmp
, tmp
, QREG_CC_C
);
1395 tcond
= TCG_COND_NE
;
1397 case 4: /* CC (!C) */
1398 case 5: /* CS (C) */
1400 tcond
= TCG_COND_NE
;
1402 case 6: /* NE (!Z) */
1403 case 7: /* EQ (Z) */
1405 tcond
= TCG_COND_EQ
;
1407 case 8: /* VC (!V) */
1408 case 9: /* VS (V) */
1410 tcond
= TCG_COND_LT
;
1412 case 10: /* PL (!N) */
1413 case 11: /* MI (N) */
1415 tcond
= TCG_COND_LT
;
1417 case 12: /* GE (!(N ^ V)) */
1418 case 13: /* LT (N ^ V) */
1419 c
->v1
= tmp
= tcg_temp_new();
1421 tcg_gen_xor_i32(tmp
, QREG_CC_N
, QREG_CC_V
);
1422 tcond
= TCG_COND_LT
;
1424 case 14: /* GT (!(Z || (N ^ V))) */
1425 case 15: /* LE (Z || (N ^ V)) */
1426 c
->v1
= tmp
= tcg_temp_new();
1428 tcg_gen_setcond_i32(TCG_COND_EQ
, tmp
, QREG_CC_Z
, c
->v2
);
1429 tcg_gen_neg_i32(tmp
, tmp
);
1430 tmp2
= tcg_temp_new();
1431 tcg_gen_xor_i32(tmp2
, QREG_CC_N
, QREG_CC_V
);
1432 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
1433 tcg_temp_free(tmp2
);
1434 tcond
= TCG_COND_LT
;
1439 if ((cond
& 1) == 0) {
1440 tcond
= tcg_invert_cond(tcond
);
1445 static void free_cond(DisasCompare
*c
)
1448 tcg_temp_free(c
->v1
);
1451 tcg_temp_free(c
->v2
);
1455 static void gen_jmpcc(DisasContext
*s
, int cond
, TCGLabel
*l1
)
1459 gen_cc_cond(&c
, s
, cond
);
1461 tcg_gen_brcond_i32(c
.tcond
, c
.v1
, c
.v2
, l1
);
1465 /* Force a TB lookup after an instruction that changes the CPU state. */
1466 static void gen_exit_tb(DisasContext
*s
)
1469 tcg_gen_movi_i32(QREG_PC
, s
->pc
);
1470 s
->base
.is_jmp
= DISAS_EXIT
;
1473 #define SRC_EA(env, result, opsize, op_sign, addrp) do { \
1474 result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \
1475 op_sign ? EA_LOADS : EA_LOADU, IS_USER(s)); \
1476 if (IS_NULL_QREG(result)) { \
1477 gen_addr_fault(s); \
1482 #define DEST_EA(env, insn, opsize, val, addrp) do { \
1483 TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, \
1484 EA_STORE, IS_USER(s)); \
1485 if (IS_NULL_QREG(ea_result)) { \
1486 gen_addr_fault(s); \
1491 static inline bool use_goto_tb(DisasContext
*s
, uint32_t dest
)
1493 #ifndef CONFIG_USER_ONLY
1494 return (s
->base
.pc_first
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)
1495 || (s
->base
.pc_next
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
1501 /* Generate a jump to an immediate address. */
1502 static void gen_jmp_tb(DisasContext
*s
, int n
, uint32_t dest
)
1504 if (unlikely(s
->base
.singlestep_enabled
)) {
1505 gen_exception(s
, dest
, EXCP_DEBUG
);
1506 } else if (use_goto_tb(s
, dest
)) {
1508 tcg_gen_movi_i32(QREG_PC
, dest
);
1509 tcg_gen_exit_tb(s
->base
.tb
, n
);
1511 gen_jmp_im(s
, dest
);
1512 tcg_gen_exit_tb(NULL
, 0);
1514 s
->base
.is_jmp
= DISAS_NORETURN
;
1523 cond
= (insn
>> 8) & 0xf;
1524 gen_cc_cond(&c
, s
, cond
);
1526 tmp
= tcg_temp_new();
1527 tcg_gen_setcond_i32(c
.tcond
, tmp
, c
.v1
, c
.v2
);
1530 tcg_gen_neg_i32(tmp
, tmp
);
1531 DEST_EA(env
, insn
, OS_BYTE
, tmp
, NULL
);
1543 reg
= DREG(insn
, 0);
1545 offset
= (int16_t)read_im16(env
, s
);
1546 l1
= gen_new_label();
1547 gen_jmpcc(s
, (insn
>> 8) & 0xf, l1
);
1549 tmp
= tcg_temp_new();
1550 tcg_gen_ext16s_i32(tmp
, reg
);
1551 tcg_gen_addi_i32(tmp
, tmp
, -1);
1552 gen_partset_reg(OS_WORD
, reg
, tmp
);
1553 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, -1, l1
);
1554 gen_jmp_tb(s
, 1, base
+ offset
);
1556 gen_jmp_tb(s
, 0, s
->pc
);
1559 DISAS_INSN(undef_mac
)
1561 gen_exception(s
, s
->base
.pc_next
, EXCP_LINEA
);
1564 DISAS_INSN(undef_fpu
)
1566 gen_exception(s
, s
->base
.pc_next
, EXCP_LINEF
);
1572 * ??? This is both instructions that are as yet unimplemented
1573 * for the 680x0 series, as well as those that are implemented
1574 * but actually illegal for CPU32 or pre-68020.
1576 qemu_log_mask(LOG_UNIMP
, "Illegal instruction: %04x @ %08x\n",
1577 insn
, s
->base
.pc_next
);
1578 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
1588 sign
= (insn
& 0x100) != 0;
1589 reg
= DREG(insn
, 9);
1590 tmp
= tcg_temp_new();
1592 tcg_gen_ext16s_i32(tmp
, reg
);
1594 tcg_gen_ext16u_i32(tmp
, reg
);
1595 SRC_EA(env
, src
, OS_WORD
, sign
, NULL
);
1596 tcg_gen_mul_i32(tmp
, tmp
, src
);
1597 tcg_gen_mov_i32(reg
, tmp
);
1598 gen_logic_cc(s
, tmp
, OS_LONG
);
1608 /* divX.w <EA>,Dn 32/16 -> 16r:16q */
1610 sign
= (insn
& 0x100) != 0;
1612 /* dest.l / src.w */
1614 SRC_EA(env
, src
, OS_WORD
, sign
, NULL
);
1615 destr
= tcg_const_i32(REG(insn
, 9));
1617 gen_helper_divsw(cpu_env
, destr
, src
);
1619 gen_helper_divuw(cpu_env
, destr
, src
);
1621 tcg_temp_free(destr
);
1623 set_cc_op(s
, CC_OP_FLAGS
);
1632 ext
= read_im16(env
, s
);
1634 sign
= (ext
& 0x0800) != 0;
1637 if (!m68k_feature(s
->env
, M68K_FEATURE_QUAD_MULDIV
)) {
1638 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
1642 /* divX.l <EA>, Dr:Dq 64/32 -> 32r:32q */
1644 SRC_EA(env
, den
, OS_LONG
, 0, NULL
);
1645 num
= tcg_const_i32(REG(ext
, 12));
1646 reg
= tcg_const_i32(REG(ext
, 0));
1648 gen_helper_divsll(cpu_env
, num
, reg
, den
);
1650 gen_helper_divull(cpu_env
, num
, reg
, den
);
1654 set_cc_op(s
, CC_OP_FLAGS
);
1658 /* divX.l <EA>, Dq 32/32 -> 32q */
1659 /* divXl.l <EA>, Dr:Dq 32/32 -> 32r:32q */
1661 SRC_EA(env
, den
, OS_LONG
, 0, NULL
);
1662 num
= tcg_const_i32(REG(ext
, 12));
1663 reg
= tcg_const_i32(REG(ext
, 0));
1665 gen_helper_divsl(cpu_env
, num
, reg
, den
);
1667 gen_helper_divul(cpu_env
, num
, reg
, den
);
1672 set_cc_op(s
, CC_OP_FLAGS
);
1675 static void bcd_add(TCGv dest
, TCGv src
)
1680 * dest10 = dest10 + src10 + X
1684 * t3 = t2 + dest + X
1688 * t7 = (t6 >> 2) | (t6 >> 3)
1693 * t1 = (src + 0x066) + dest + X
1694 * = result with some possible exceding 0x6
1697 t0
= tcg_const_i32(0x066);
1698 tcg_gen_add_i32(t0
, t0
, src
);
1700 t1
= tcg_temp_new();
1701 tcg_gen_add_i32(t1
, t0
, dest
);
1702 tcg_gen_add_i32(t1
, t1
, QREG_CC_X
);
1704 /* we will remove exceding 0x6 where there is no carry */
1707 * t0 = (src + 0x0066) ^ dest
1708 * = t1 without carries
1711 tcg_gen_xor_i32(t0
, t0
, dest
);
1714 * extract the carries
1716 * = only the carries
1719 tcg_gen_xor_i32(t0
, t0
, t1
);
1722 * generate 0x1 where there is no carry
1723 * and for each 0x10, generate a 0x6
1726 tcg_gen_shri_i32(t0
, t0
, 3);
1727 tcg_gen_not_i32(t0
, t0
);
1728 tcg_gen_andi_i32(t0
, t0
, 0x22);
1729 tcg_gen_add_i32(dest
, t0
, t0
);
1730 tcg_gen_add_i32(dest
, dest
, t0
);
1734 * remove the exceding 0x6
1735 * for digits that have not generated a carry
1738 tcg_gen_sub_i32(dest
, t1
, dest
);
1742 static void bcd_sub(TCGv dest
, TCGv src
)
1747 * dest10 = dest10 - src10 - X
1748 * = bcd_add(dest + 1 - X, 0x199 - src)
1751 /* t0 = 0x066 + (0x199 - src) */
1753 t0
= tcg_temp_new();
1754 tcg_gen_subfi_i32(t0
, 0x1ff, src
);
1756 /* t1 = t0 + dest + 1 - X*/
1758 t1
= tcg_temp_new();
1759 tcg_gen_add_i32(t1
, t0
, dest
);
1760 tcg_gen_addi_i32(t1
, t1
, 1);
1761 tcg_gen_sub_i32(t1
, t1
, QREG_CC_X
);
1763 /* t2 = t0 ^ dest */
1765 t2
= tcg_temp_new();
1766 tcg_gen_xor_i32(t2
, t0
, dest
);
1770 tcg_gen_xor_i32(t0
, t1
, t2
);
1774 * t0 = (t2 >> 2) | (t2 >> 3)
1776 * to fit on 8bit operands, changed in:
1778 * t2 = ~(t0 >> 3) & 0x22
1783 tcg_gen_shri_i32(t2
, t0
, 3);
1784 tcg_gen_not_i32(t2
, t2
);
1785 tcg_gen_andi_i32(t2
, t2
, 0x22);
1786 tcg_gen_add_i32(t0
, t2
, t2
);
1787 tcg_gen_add_i32(t0
, t0
, t2
);
1790 /* return t1 - t0 */
1792 tcg_gen_sub_i32(dest
, t1
, t0
);
1797 static void bcd_flags(TCGv val
)
1799 tcg_gen_andi_i32(QREG_CC_C
, val
, 0x0ff);
1800 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_C
);
1802 tcg_gen_extract_i32(QREG_CC_C
, val
, 8, 1);
1804 tcg_gen_mov_i32(QREG_CC_X
, QREG_CC_C
);
1807 DISAS_INSN(abcd_reg
)
1812 gen_flush_flags(s
); /* !Z is sticky */
1814 src
= gen_extend(s
, DREG(insn
, 0), OS_BYTE
, 0);
1815 dest
= gen_extend(s
, DREG(insn
, 9), OS_BYTE
, 0);
1817 gen_partset_reg(OS_BYTE
, DREG(insn
, 9), dest
);
1822 DISAS_INSN(abcd_mem
)
1824 TCGv src
, dest
, addr
;
1826 gen_flush_flags(s
); /* !Z is sticky */
1828 /* Indirect pre-decrement load (mode 4) */
1830 src
= gen_ea_mode(env
, s
, 4, REG(insn
, 0), OS_BYTE
,
1831 NULL_QREG
, NULL
, EA_LOADU
, IS_USER(s
));
1832 dest
= gen_ea_mode(env
, s
, 4, REG(insn
, 9), OS_BYTE
,
1833 NULL_QREG
, &addr
, EA_LOADU
, IS_USER(s
));
1837 gen_ea_mode(env
, s
, 4, REG(insn
, 9), OS_BYTE
, dest
, &addr
,
1838 EA_STORE
, IS_USER(s
));
1843 DISAS_INSN(sbcd_reg
)
1847 gen_flush_flags(s
); /* !Z is sticky */
1849 src
= gen_extend(s
, DREG(insn
, 0), OS_BYTE
, 0);
1850 dest
= gen_extend(s
, DREG(insn
, 9), OS_BYTE
, 0);
1854 gen_partset_reg(OS_BYTE
, DREG(insn
, 9), dest
);
1859 DISAS_INSN(sbcd_mem
)
1861 TCGv src
, dest
, addr
;
1863 gen_flush_flags(s
); /* !Z is sticky */
1865 /* Indirect pre-decrement load (mode 4) */
1867 src
= gen_ea_mode(env
, s
, 4, REG(insn
, 0), OS_BYTE
,
1868 NULL_QREG
, NULL
, EA_LOADU
, IS_USER(s
));
1869 dest
= gen_ea_mode(env
, s
, 4, REG(insn
, 9), OS_BYTE
,
1870 NULL_QREG
, &addr
, EA_LOADU
, IS_USER(s
));
1874 gen_ea_mode(env
, s
, 4, REG(insn
, 9), OS_BYTE
, dest
, &addr
,
1875 EA_STORE
, IS_USER(s
));
1885 gen_flush_flags(s
); /* !Z is sticky */
1887 SRC_EA(env
, src
, OS_BYTE
, 0, &addr
);
1889 dest
= tcg_const_i32(0);
1892 DEST_EA(env
, insn
, OS_BYTE
, dest
, &addr
);
1896 tcg_temp_free(dest
);
1909 add
= (insn
& 0x4000) != 0;
1910 opsize
= insn_opsize(insn
);
1911 reg
= gen_extend(s
, DREG(insn
, 9), opsize
, 1);
1912 dest
= tcg_temp_new();
1914 SRC_EA(env
, tmp
, opsize
, 1, &addr
);
1918 SRC_EA(env
, src
, opsize
, 1, NULL
);
1921 tcg_gen_add_i32(dest
, tmp
, src
);
1922 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, src
);
1923 set_cc_op(s
, CC_OP_ADDB
+ opsize
);
1925 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, tmp
, src
);
1926 tcg_gen_sub_i32(dest
, tmp
, src
);
1927 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
1929 gen_update_cc_add(dest
, src
, opsize
);
1931 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
1933 gen_partset_reg(opsize
, DREG(insn
, 9), dest
);
1935 tcg_temp_free(dest
);
1938 /* Reverse the order of the bits in REG. */
1942 reg
= DREG(insn
, 0);
1943 gen_helper_bitrev(reg
, reg
);
1946 DISAS_INSN(bitop_reg
)
1956 if ((insn
& 0x38) != 0)
1960 op
= (insn
>> 6) & 3;
1961 SRC_EA(env
, src1
, opsize
, 0, op
? &addr
: NULL
);
1964 src2
= tcg_temp_new();
1965 if (opsize
== OS_BYTE
)
1966 tcg_gen_andi_i32(src2
, DREG(insn
, 9), 7);
1968 tcg_gen_andi_i32(src2
, DREG(insn
, 9), 31);
1970 tmp
= tcg_const_i32(1);
1971 tcg_gen_shl_i32(tmp
, tmp
, src2
);
1972 tcg_temp_free(src2
);
1974 tcg_gen_and_i32(QREG_CC_Z
, src1
, tmp
);
1976 dest
= tcg_temp_new();
1979 tcg_gen_xor_i32(dest
, src1
, tmp
);
1982 tcg_gen_andc_i32(dest
, src1
, tmp
);
1985 tcg_gen_or_i32(dest
, src1
, tmp
);
1992 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
1994 tcg_temp_free(dest
);
2000 reg
= DREG(insn
, 0);
2002 gen_helper_sats(reg
, reg
, QREG_CC_V
);
2003 gen_logic_cc(s
, reg
, OS_LONG
);
2006 static void gen_push(DisasContext
*s
, TCGv val
)
2010 tmp
= tcg_temp_new();
2011 tcg_gen_subi_i32(tmp
, QREG_SP
, 4);
2012 gen_store(s
, OS_LONG
, tmp
, val
, IS_USER(s
));
2013 tcg_gen_mov_i32(QREG_SP
, tmp
);
2017 static TCGv
mreg(int reg
)
2021 return cpu_dregs
[reg
];
2024 return cpu_aregs
[reg
& 7];
2029 TCGv addr
, incr
, tmp
, r
[16];
2030 int is_load
= (insn
& 0x0400) != 0;
2031 int opsize
= (insn
& 0x40) != 0 ? OS_LONG
: OS_WORD
;
2032 uint16_t mask
= read_im16(env
, s
);
2033 int mode
= extract32(insn
, 3, 3);
2034 int reg0
= REG(insn
, 0);
2037 tmp
= cpu_aregs
[reg0
];
2040 case 0: /* data register direct */
2041 case 1: /* addr register direct */
2046 case 2: /* indirect */
2049 case 3: /* indirect post-increment */
2051 /* post-increment is not allowed */
2056 case 4: /* indirect pre-decrement */
2058 /* pre-decrement is not allowed */
2062 * We want a bare copy of the address reg, without any pre-decrement
2063 * adjustment, as gen_lea would provide.
2068 tmp
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
2069 if (IS_NULL_QREG(tmp
)) {
2075 addr
= tcg_temp_new();
2076 tcg_gen_mov_i32(addr
, tmp
);
2077 incr
= tcg_const_i32(opsize_bytes(opsize
));
2080 /* memory to register */
2081 for (i
= 0; i
< 16; i
++) {
2082 if (mask
& (1 << i
)) {
2083 r
[i
] = gen_load(s
, opsize
, addr
, 1, IS_USER(s
));
2084 tcg_gen_add_i32(addr
, addr
, incr
);
2087 for (i
= 0; i
< 16; i
++) {
2088 if (mask
& (1 << i
)) {
2089 tcg_gen_mov_i32(mreg(i
), r
[i
]);
2090 tcg_temp_free(r
[i
]);
2094 /* post-increment: movem (An)+,X */
2095 tcg_gen_mov_i32(cpu_aregs
[reg0
], addr
);
2098 /* register to memory */
2100 /* pre-decrement: movem X,-(An) */
2101 for (i
= 15; i
>= 0; i
--) {
2102 if ((mask
<< i
) & 0x8000) {
2103 tcg_gen_sub_i32(addr
, addr
, incr
);
2104 if (reg0
+ 8 == i
&&
2105 m68k_feature(s
->env
, M68K_FEATURE_EXT_FULL
)) {
2107 * M68020+: if the addressing register is the
2108 * register moved to memory, the value written
2109 * is the initial value decremented by the size of
2110 * the operation, regardless of how many actual
2111 * stores have been performed until this point.
2112 * M68000/M68010: the value is the initial value.
2114 tmp
= tcg_temp_new();
2115 tcg_gen_sub_i32(tmp
, cpu_aregs
[reg0
], incr
);
2116 gen_store(s
, opsize
, addr
, tmp
, IS_USER(s
));
2119 gen_store(s
, opsize
, addr
, mreg(i
), IS_USER(s
));
2123 tcg_gen_mov_i32(cpu_aregs
[reg0
], addr
);
2125 for (i
= 0; i
< 16; i
++) {
2126 if (mask
& (1 << i
)) {
2127 gen_store(s
, opsize
, addr
, mreg(i
), IS_USER(s
));
2128 tcg_gen_add_i32(addr
, addr
, incr
);
2134 tcg_temp_free(incr
);
2135 tcg_temp_free(addr
);
2147 displ
= read_im16(env
, s
);
2149 addr
= AREG(insn
, 0);
2150 reg
= DREG(insn
, 9);
2152 abuf
= tcg_temp_new();
2153 tcg_gen_addi_i32(abuf
, addr
, displ
);
2154 dbuf
= tcg_temp_new();
2163 for ( ; i
> 0 ; i
--) {
2164 tcg_gen_shri_i32(dbuf
, reg
, (i
- 1) * 8);
2165 tcg_gen_qemu_st8(dbuf
, abuf
, IS_USER(s
));
2167 tcg_gen_addi_i32(abuf
, abuf
, 2);
2171 for ( ; i
> 0 ; i
--) {
2172 tcg_gen_qemu_ld8u(dbuf
, abuf
, IS_USER(s
));
2173 tcg_gen_deposit_i32(reg
, reg
, dbuf
, (i
- 1) * 8, 8);
2175 tcg_gen_addi_i32(abuf
, abuf
, 2);
2179 tcg_temp_free(abuf
);
2180 tcg_temp_free(dbuf
);
2183 DISAS_INSN(bitop_im
)
2193 if ((insn
& 0x38) != 0)
2197 op
= (insn
>> 6) & 3;
2199 bitnum
= read_im16(env
, s
);
2200 if (m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
2201 if (bitnum
& 0xfe00) {
2202 disas_undef(env
, s
, insn
);
2206 if (bitnum
& 0xff00) {
2207 disas_undef(env
, s
, insn
);
2212 SRC_EA(env
, src1
, opsize
, 0, op
? &addr
: NULL
);
2215 if (opsize
== OS_BYTE
)
2221 tcg_gen_andi_i32(QREG_CC_Z
, src1
, mask
);
2224 tmp
= tcg_temp_new();
2227 tcg_gen_xori_i32(tmp
, src1
, mask
);
2230 tcg_gen_andi_i32(tmp
, src1
, ~mask
);
2233 tcg_gen_ori_i32(tmp
, src1
, mask
);
2238 DEST_EA(env
, insn
, opsize
, tmp
, &addr
);
2243 static TCGv
gen_get_ccr(DisasContext
*s
)
2248 dest
= tcg_temp_new();
2249 gen_helper_get_ccr(dest
, cpu_env
);
2253 static TCGv
gen_get_sr(DisasContext
*s
)
2258 ccr
= gen_get_ccr(s
);
2259 sr
= tcg_temp_new();
2260 tcg_gen_andi_i32(sr
, QREG_SR
, 0xffe0);
2261 tcg_gen_or_i32(sr
, sr
, ccr
);
2266 static void gen_set_sr_im(DisasContext
*s
, uint16_t val
, int ccr_only
)
2269 tcg_gen_movi_i32(QREG_CC_C
, val
& CCF_C
? 1 : 0);
2270 tcg_gen_movi_i32(QREG_CC_V
, val
& CCF_V
? -1 : 0);
2271 tcg_gen_movi_i32(QREG_CC_Z
, val
& CCF_Z
? 0 : 1);
2272 tcg_gen_movi_i32(QREG_CC_N
, val
& CCF_N
? -1 : 0);
2273 tcg_gen_movi_i32(QREG_CC_X
, val
& CCF_X
? 1 : 0);
2275 TCGv sr
= tcg_const_i32(val
);
2276 gen_helper_set_sr(cpu_env
, sr
);
2279 set_cc_op(s
, CC_OP_FLAGS
);
2282 static void gen_set_sr(DisasContext
*s
, TCGv val
, int ccr_only
)
2285 gen_helper_set_ccr(cpu_env
, val
);
2287 gen_helper_set_sr(cpu_env
, val
);
2289 set_cc_op(s
, CC_OP_FLAGS
);
2292 static void gen_move_to_sr(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
2295 if ((insn
& 0x3f) == 0x3c) {
2297 val
= read_im16(env
, s
);
2298 gen_set_sr_im(s
, val
, ccr_only
);
2301 SRC_EA(env
, src
, OS_WORD
, 0, NULL
);
2302 gen_set_sr(s
, src
, ccr_only
);
2306 DISAS_INSN(arith_im
)
2314 bool with_SR
= ((insn
& 0x3f) == 0x3c);
2316 op
= (insn
>> 9) & 7;
2317 opsize
= insn_opsize(insn
);
2320 im
= tcg_const_i32((int8_t)read_im8(env
, s
));
2323 im
= tcg_const_i32((int16_t)read_im16(env
, s
));
2326 im
= tcg_const_i32(read_im32(env
, s
));
2329 g_assert_not_reached();
2333 /* SR/CCR can only be used with andi/eori/ori */
2334 if (op
== 2 || op
== 3 || op
== 6) {
2335 disas_undef(env
, s
, insn
);
2340 src1
= gen_get_ccr(s
);
2344 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
2347 src1
= gen_get_sr(s
);
2350 /* OS_LONG; others already g_assert_not_reached. */
2351 disas_undef(env
, s
, insn
);
2355 SRC_EA(env
, src1
, opsize
, 1, (op
== 6) ? NULL
: &addr
);
2357 dest
= tcg_temp_new();
2360 tcg_gen_or_i32(dest
, src1
, im
);
2362 gen_set_sr(s
, dest
, opsize
== OS_BYTE
);
2364 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2365 gen_logic_cc(s
, dest
, opsize
);
2369 tcg_gen_and_i32(dest
, src1
, im
);
2371 gen_set_sr(s
, dest
, opsize
== OS_BYTE
);
2373 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2374 gen_logic_cc(s
, dest
, opsize
);
2378 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, src1
, im
);
2379 tcg_gen_sub_i32(dest
, src1
, im
);
2380 gen_update_cc_add(dest
, im
, opsize
);
2381 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
2382 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2385 tcg_gen_add_i32(dest
, src1
, im
);
2386 gen_update_cc_add(dest
, im
, opsize
);
2387 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, im
);
2388 set_cc_op(s
, CC_OP_ADDB
+ opsize
);
2389 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2392 tcg_gen_xor_i32(dest
, src1
, im
);
2394 gen_set_sr(s
, dest
, opsize
== OS_BYTE
);
2396 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2397 gen_logic_cc(s
, dest
, opsize
);
2401 gen_update_cc_cmp(s
, src1
, im
, opsize
);
2407 tcg_temp_free(dest
);
2419 switch ((insn
>> 9) & 3) {
2433 g_assert_not_reached();
2436 ext
= read_im16(env
, s
);
2438 /* cas Dc,Du,<EA> */
2440 addr
= gen_lea(env
, s
, insn
, opsize
);
2441 if (IS_NULL_QREG(addr
)) {
2446 cmp
= gen_extend(s
, DREG(ext
, 0), opsize
, 1);
2449 * if <EA> == Dc then
2451 * Dc = <EA> (because <EA> == Dc)
2456 load
= tcg_temp_new();
2457 tcg_gen_atomic_cmpxchg_i32(load
, addr
, cmp
, DREG(ext
, 6),
2459 /* update flags before setting cmp to load */
2460 gen_update_cc_cmp(s
, load
, cmp
, opsize
);
2461 gen_partset_reg(opsize
, DREG(ext
, 0), load
);
2463 tcg_temp_free(load
);
2465 switch (extract32(insn
, 3, 3)) {
2466 case 3: /* Indirect postincrement. */
2467 tcg_gen_addi_i32(AREG(insn
, 0), addr
, opsize_bytes(opsize
));
2469 case 4: /* Indirect predecrememnt. */
2470 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
2477 uint16_t ext1
, ext2
;
2481 /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
2483 ext1
= read_im16(env
, s
);
2485 if (ext1
& 0x8000) {
2486 /* Address Register */
2487 addr1
= AREG(ext1
, 12);
2490 addr1
= DREG(ext1
, 12);
2493 ext2
= read_im16(env
, s
);
2494 if (ext2
& 0x8000) {
2495 /* Address Register */
2496 addr2
= AREG(ext2
, 12);
2499 addr2
= DREG(ext2
, 12);
2503 * if (R1) == Dc1 && (R2) == Dc2 then
2511 regs
= tcg_const_i32(REG(ext2
, 6) |
2512 (REG(ext1
, 6) << 3) |
2513 (REG(ext2
, 0) << 6) |
2514 (REG(ext1
, 0) << 9));
2515 if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2516 gen_helper_exit_atomic(cpu_env
);
2518 gen_helper_cas2w(cpu_env
, regs
, addr1
, addr2
);
2520 tcg_temp_free(regs
);
2522 /* Note that cas2w also assigned to env->cc_op. */
2523 s
->cc_op
= CC_OP_CMPW
;
2524 s
->cc_op_synced
= 1;
2529 uint16_t ext1
, ext2
;
2530 TCGv addr1
, addr2
, regs
;
2532 /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
2534 ext1
= read_im16(env
, s
);
2536 if (ext1
& 0x8000) {
2537 /* Address Register */
2538 addr1
= AREG(ext1
, 12);
2541 addr1
= DREG(ext1
, 12);
2544 ext2
= read_im16(env
, s
);
2545 if (ext2
& 0x8000) {
2546 /* Address Register */
2547 addr2
= AREG(ext2
, 12);
2550 addr2
= DREG(ext2
, 12);
2554 * if (R1) == Dc1 && (R2) == Dc2 then
2562 regs
= tcg_const_i32(REG(ext2
, 6) |
2563 (REG(ext1
, 6) << 3) |
2564 (REG(ext2
, 0) << 6) |
2565 (REG(ext1
, 0) << 9));
2566 if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2567 gen_helper_cas2l_parallel(cpu_env
, regs
, addr1
, addr2
);
2569 gen_helper_cas2l(cpu_env
, regs
, addr1
, addr2
);
2571 tcg_temp_free(regs
);
2573 /* Note that cas2l also assigned to env->cc_op. */
2574 s
->cc_op
= CC_OP_CMPL
;
2575 s
->cc_op_synced
= 1;
2582 reg
= DREG(insn
, 0);
2583 tcg_gen_bswap32_i32(reg
, reg
);
2593 switch (insn
>> 12) {
2594 case 1: /* move.b */
2597 case 2: /* move.l */
2600 case 3: /* move.w */
2606 SRC_EA(env
, src
, opsize
, 1, NULL
);
2607 op
= (insn
>> 6) & 7;
2610 /* The value will already have been sign extended. */
2611 dest
= AREG(insn
, 9);
2612 tcg_gen_mov_i32(dest
, src
);
2616 dest_ea
= ((insn
>> 9) & 7) | (op
<< 3);
2617 DEST_EA(env
, dest_ea
, opsize
, src
, NULL
);
2618 /* This will be correct because loads sign extend. */
2619 gen_logic_cc(s
, src
, opsize
);
2630 opsize
= insn_opsize(insn
);
2631 SRC_EA(env
, src
, opsize
, 1, &addr
);
2633 gen_flush_flags(s
); /* compute old Z */
2636 * Perform substract with borrow.
2637 * (X, N) = -(src + X);
2640 z
= tcg_const_i32(0);
2641 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, src
, z
, QREG_CC_X
, z
);
2642 tcg_gen_sub2_i32(QREG_CC_N
, QREG_CC_X
, z
, z
, QREG_CC_N
, QREG_CC_X
);
2644 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
2646 tcg_gen_andi_i32(QREG_CC_X
, QREG_CC_X
, 1);
2649 * Compute signed-overflow for negation. The normal formula for
2650 * subtraction is (res ^ src) & (src ^ dest), but with dest==0
2651 * this simplies to res & src.
2654 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_N
, src
);
2656 /* Copy the rest of the results into place. */
2657 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
); /* !Z is sticky */
2658 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
2660 set_cc_op(s
, CC_OP_FLAGS
);
2662 /* result is in QREG_CC_N */
2664 DEST_EA(env
, insn
, opsize
, QREG_CC_N
, &addr
);
2672 reg
= AREG(insn
, 9);
2673 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
2674 if (IS_NULL_QREG(tmp
)) {
2678 tcg_gen_mov_i32(reg
, tmp
);
2686 zero
= tcg_const_i32(0);
2688 opsize
= insn_opsize(insn
);
2689 DEST_EA(env
, insn
, opsize
, zero
, NULL
);
2690 gen_logic_cc(s
, zero
, opsize
);
2691 tcg_temp_free(zero
);
2694 DISAS_INSN(move_from_ccr
)
2698 ccr
= gen_get_ccr(s
);
2699 DEST_EA(env
, insn
, OS_WORD
, ccr
, NULL
);
2709 opsize
= insn_opsize(insn
);
2710 SRC_EA(env
, src1
, opsize
, 1, &addr
);
2711 dest
= tcg_temp_new();
2712 tcg_gen_neg_i32(dest
, src1
);
2713 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
2714 gen_update_cc_add(dest
, src1
, opsize
);
2715 tcg_gen_setcondi_i32(TCG_COND_NE
, QREG_CC_X
, dest
, 0);
2716 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2717 tcg_temp_free(dest
);
2720 DISAS_INSN(move_to_ccr
)
2722 gen_move_to_sr(env
, s
, insn
, true);
2732 opsize
= insn_opsize(insn
);
2733 SRC_EA(env
, src1
, opsize
, 1, &addr
);
2734 dest
= tcg_temp_new();
2735 tcg_gen_not_i32(dest
, src1
);
2736 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2737 gen_logic_cc(s
, dest
, opsize
);
2746 src1
= tcg_temp_new();
2747 src2
= tcg_temp_new();
2748 reg
= DREG(insn
, 0);
2749 tcg_gen_shli_i32(src1
, reg
, 16);
2750 tcg_gen_shri_i32(src2
, reg
, 16);
2751 tcg_gen_or_i32(reg
, src1
, src2
);
2752 tcg_temp_free(src2
);
2753 tcg_temp_free(src1
);
2754 gen_logic_cc(s
, reg
, OS_LONG
);
2759 gen_exception(s
, s
->base
.pc_next
, EXCP_DEBUG
);
2766 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
2767 if (IS_NULL_QREG(tmp
)) {
2780 reg
= DREG(insn
, 0);
2781 op
= (insn
>> 6) & 7;
2782 tmp
= tcg_temp_new();
2784 tcg_gen_ext16s_i32(tmp
, reg
);
2786 tcg_gen_ext8s_i32(tmp
, reg
);
2788 gen_partset_reg(OS_WORD
, reg
, tmp
);
2790 tcg_gen_mov_i32(reg
, tmp
);
2791 gen_logic_cc(s
, tmp
, OS_LONG
);
2800 opsize
= insn_opsize(insn
);
2801 SRC_EA(env
, tmp
, opsize
, 1, NULL
);
2802 gen_logic_cc(s
, tmp
, opsize
);
2807 /* Implemented as a NOP. */
2812 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
2815 /* ??? This should be atomic. */
2822 dest
= tcg_temp_new();
2823 SRC_EA(env
, src1
, OS_BYTE
, 1, &addr
);
2824 gen_logic_cc(s
, src1
, OS_BYTE
);
2825 tcg_gen_ori_i32(dest
, src1
, 0x80);
2826 DEST_EA(env
, insn
, OS_BYTE
, dest
, &addr
);
2827 tcg_temp_free(dest
);
2836 ext
= read_im16(env
, s
);
2841 if (!m68k_feature(s
->env
, M68K_FEATURE_QUAD_MULDIV
)) {
2842 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
2846 SRC_EA(env
, src1
, OS_LONG
, 0, NULL
);
2849 tcg_gen_muls2_i32(QREG_CC_Z
, QREG_CC_N
, src1
, DREG(ext
, 12));
2851 tcg_gen_mulu2_i32(QREG_CC_Z
, QREG_CC_N
, src1
, DREG(ext
, 12));
2853 /* if Dl == Dh, 68040 returns low word */
2854 tcg_gen_mov_i32(DREG(ext
, 0), QREG_CC_N
);
2855 tcg_gen_mov_i32(DREG(ext
, 12), QREG_CC_Z
);
2856 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
);
2858 tcg_gen_movi_i32(QREG_CC_V
, 0);
2859 tcg_gen_movi_i32(QREG_CC_C
, 0);
2861 set_cc_op(s
, CC_OP_FLAGS
);
2864 SRC_EA(env
, src1
, OS_LONG
, 0, NULL
);
2865 if (m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
2866 tcg_gen_movi_i32(QREG_CC_C
, 0);
2868 tcg_gen_muls2_i32(QREG_CC_N
, QREG_CC_V
, src1
, DREG(ext
, 12));
2869 /* QREG_CC_V is -(QREG_CC_V != (QREG_CC_N >> 31)) */
2870 tcg_gen_sari_i32(QREG_CC_Z
, QREG_CC_N
, 31);
2871 tcg_gen_setcond_i32(TCG_COND_NE
, QREG_CC_V
, QREG_CC_V
, QREG_CC_Z
);
2873 tcg_gen_mulu2_i32(QREG_CC_N
, QREG_CC_V
, src1
, DREG(ext
, 12));
2874 /* QREG_CC_V is -(QREG_CC_V != 0), use QREG_CC_C as 0 */
2875 tcg_gen_setcond_i32(TCG_COND_NE
, QREG_CC_V
, QREG_CC_V
, QREG_CC_C
);
2877 tcg_gen_neg_i32(QREG_CC_V
, QREG_CC_V
);
2878 tcg_gen_mov_i32(DREG(ext
, 12), QREG_CC_N
);
2880 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
2882 set_cc_op(s
, CC_OP_FLAGS
);
2885 * The upper 32 bits of the product are discarded, so
2886 * muls.l and mulu.l are functionally equivalent.
2888 tcg_gen_mul_i32(DREG(ext
, 12), src1
, DREG(ext
, 12));
2889 gen_logic_cc(s
, DREG(ext
, 12), OS_LONG
);
2893 static void gen_link(DisasContext
*s
, uint16_t insn
, int32_t offset
)
2898 reg
= AREG(insn
, 0);
2899 tmp
= tcg_temp_new();
2900 tcg_gen_subi_i32(tmp
, QREG_SP
, 4);
2901 gen_store(s
, OS_LONG
, tmp
, reg
, IS_USER(s
));
2902 if ((insn
& 7) != 7) {
2903 tcg_gen_mov_i32(reg
, tmp
);
2905 tcg_gen_addi_i32(QREG_SP
, tmp
, offset
);
2913 offset
= read_im16(env
, s
);
2914 gen_link(s
, insn
, offset
);
2921 offset
= read_im32(env
, s
);
2922 gen_link(s
, insn
, offset
);
2931 src
= tcg_temp_new();
2932 reg
= AREG(insn
, 0);
2933 tcg_gen_mov_i32(src
, reg
);
2934 tmp
= gen_load(s
, OS_LONG
, src
, 0, IS_USER(s
));
2935 tcg_gen_mov_i32(reg
, tmp
);
2936 tcg_gen_addi_i32(QREG_SP
, src
, 4);
2941 #if defined(CONFIG_SOFTMMU)
2945 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
2949 gen_helper_reset(cpu_env
);
2960 int16_t offset
= read_im16(env
, s
);
2962 tmp
= gen_load(s
, OS_LONG
, QREG_SP
, 0, IS_USER(s
));
2963 tcg_gen_addi_i32(QREG_SP
, QREG_SP
, offset
+ 4);
2971 tmp
= gen_load(s
, OS_LONG
, QREG_SP
, 0, IS_USER(s
));
2972 tcg_gen_addi_i32(QREG_SP
, QREG_SP
, 4);
2981 * Load the target address first to ensure correct exception
2984 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
2985 if (IS_NULL_QREG(tmp
)) {
2989 if ((insn
& 0x40) == 0) {
2991 gen_push(s
, tcg_const_i32(s
->pc
));
3005 if ((insn
& 070) == 010) {
3006 /* Operation on address register is always long. */
3009 opsize
= insn_opsize(insn
);
3011 SRC_EA(env
, src
, opsize
, 1, &addr
);
3012 imm
= (insn
>> 9) & 7;
3016 val
= tcg_const_i32(imm
);
3017 dest
= tcg_temp_new();
3018 tcg_gen_mov_i32(dest
, src
);
3019 if ((insn
& 0x38) == 0x08) {
3021 * Don't update condition codes if the destination is an
3024 if (insn
& 0x0100) {
3025 tcg_gen_sub_i32(dest
, dest
, val
);
3027 tcg_gen_add_i32(dest
, dest
, val
);
3030 if (insn
& 0x0100) {
3031 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, val
);
3032 tcg_gen_sub_i32(dest
, dest
, val
);
3033 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
3035 tcg_gen_add_i32(dest
, dest
, val
);
3036 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, val
);
3037 set_cc_op(s
, CC_OP_ADDB
+ opsize
);
3039 gen_update_cc_add(dest
, val
, opsize
);
3042 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
3043 tcg_temp_free(dest
);
3049 case 2: /* One extension word. */
3052 case 3: /* Two extension words. */
3055 case 4: /* No extension words. */
3058 disas_undef(env
, s
, insn
);
3069 op
= (insn
>> 8) & 0xf;
3070 offset
= (int8_t)insn
;
3072 offset
= (int16_t)read_im16(env
, s
);
3073 } else if (offset
== -1) {
3074 offset
= read_im32(env
, s
);
3078 gen_push(s
, tcg_const_i32(s
->pc
));
3082 TCGLabel
*l1
= gen_new_label();
3083 gen_jmpcc(s
, ((insn
>> 8) & 0xf) ^ 1, l1
);
3084 gen_jmp_tb(s
, 1, base
+ offset
);
3086 gen_jmp_tb(s
, 0, s
->pc
);
3088 /* Unconditional branch. */
3090 gen_jmp_tb(s
, 0, base
+ offset
);
3096 tcg_gen_movi_i32(DREG(insn
, 9), (int8_t)insn
);
3097 gen_logic_cc(s
, DREG(insn
, 9), OS_LONG
);
3110 SRC_EA(env
, src
, opsize
, (insn
& 0x80) == 0, NULL
);
3111 reg
= DREG(insn
, 9);
3112 tcg_gen_mov_i32(reg
, src
);
3113 gen_logic_cc(s
, src
, opsize
);
3124 opsize
= insn_opsize(insn
);
3125 reg
= gen_extend(s
, DREG(insn
, 9), opsize
, 0);
3126 dest
= tcg_temp_new();
3128 SRC_EA(env
, src
, opsize
, 0, &addr
);
3129 tcg_gen_or_i32(dest
, src
, reg
);
3130 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
3132 SRC_EA(env
, src
, opsize
, 0, NULL
);
3133 tcg_gen_or_i32(dest
, src
, reg
);
3134 gen_partset_reg(opsize
, DREG(insn
, 9), dest
);
3136 gen_logic_cc(s
, dest
, opsize
);
3137 tcg_temp_free(dest
);
3145 SRC_EA(env
, src
, (insn
& 0x100) ? OS_LONG
: OS_WORD
, 1, NULL
);
3146 reg
= AREG(insn
, 9);
3147 tcg_gen_sub_i32(reg
, reg
, src
);
3150 static inline void gen_subx(DisasContext
*s
, TCGv src
, TCGv dest
, int opsize
)
3154 gen_flush_flags(s
); /* compute old Z */
3157 * Perform substract with borrow.
3158 * (X, N) = dest - (src + X);
3161 tmp
= tcg_const_i32(0);
3162 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, src
, tmp
, QREG_CC_X
, tmp
);
3163 tcg_gen_sub2_i32(QREG_CC_N
, QREG_CC_X
, dest
, tmp
, QREG_CC_N
, QREG_CC_X
);
3164 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
3165 tcg_gen_andi_i32(QREG_CC_X
, QREG_CC_X
, 1);
3167 /* Compute signed-overflow for substract. */
3169 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_N
, dest
);
3170 tcg_gen_xor_i32(tmp
, dest
, src
);
3171 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_V
, tmp
);
3174 /* Copy the rest of the results into place. */
3175 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
); /* !Z is sticky */
3176 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
3178 set_cc_op(s
, CC_OP_FLAGS
);
3180 /* result is in QREG_CC_N */
3183 DISAS_INSN(subx_reg
)
3189 opsize
= insn_opsize(insn
);
3191 src
= gen_extend(s
, DREG(insn
, 0), opsize
, 1);
3192 dest
= gen_extend(s
, DREG(insn
, 9), opsize
, 1);
3194 gen_subx(s
, src
, dest
, opsize
);
3196 gen_partset_reg(opsize
, DREG(insn
, 9), QREG_CC_N
);
3199 DISAS_INSN(subx_mem
)
3207 opsize
= insn_opsize(insn
);
3209 addr_src
= AREG(insn
, 0);
3210 tcg_gen_subi_i32(addr_src
, addr_src
, opsize_bytes(opsize
));
3211 src
= gen_load(s
, opsize
, addr_src
, 1, IS_USER(s
));
3213 addr_dest
= AREG(insn
, 9);
3214 tcg_gen_subi_i32(addr_dest
, addr_dest
, opsize_bytes(opsize
));
3215 dest
= gen_load(s
, opsize
, addr_dest
, 1, IS_USER(s
));
3217 gen_subx(s
, src
, dest
, opsize
);
3219 gen_store(s
, opsize
, addr_dest
, QREG_CC_N
, IS_USER(s
));
3221 tcg_temp_free(dest
);
3230 val
= (insn
>> 9) & 7;
3233 src
= tcg_const_i32(val
);
3234 gen_logic_cc(s
, src
, OS_LONG
);
3235 DEST_EA(env
, insn
, OS_LONG
, src
, NULL
);
3245 opsize
= insn_opsize(insn
);
3246 SRC_EA(env
, src
, opsize
, 1, NULL
);
3247 reg
= gen_extend(s
, DREG(insn
, 9), opsize
, 1);
3248 gen_update_cc_cmp(s
, reg
, src
, opsize
);
3262 SRC_EA(env
, src
, opsize
, 1, NULL
);
3263 reg
= AREG(insn
, 9);
3264 gen_update_cc_cmp(s
, reg
, src
, OS_LONG
);
3269 int opsize
= insn_opsize(insn
);
3272 /* Post-increment load (mode 3) from Ay. */
3273 src
= gen_ea_mode(env
, s
, 3, REG(insn
, 0), opsize
,
3274 NULL_QREG
, NULL
, EA_LOADS
, IS_USER(s
));
3275 /* Post-increment load (mode 3) from Ax. */
3276 dst
= gen_ea_mode(env
, s
, 3, REG(insn
, 9), opsize
,
3277 NULL_QREG
, NULL
, EA_LOADS
, IS_USER(s
));
3279 gen_update_cc_cmp(s
, dst
, src
, opsize
);
3289 opsize
= insn_opsize(insn
);
3291 SRC_EA(env
, src
, opsize
, 0, &addr
);
3292 dest
= tcg_temp_new();
3293 tcg_gen_xor_i32(dest
, src
, DREG(insn
, 9));
3294 gen_logic_cc(s
, dest
, opsize
);
3295 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
3296 tcg_temp_free(dest
);
3299 static void do_exg(TCGv reg1
, TCGv reg2
)
3301 TCGv temp
= tcg_temp_new();
3302 tcg_gen_mov_i32(temp
, reg1
);
3303 tcg_gen_mov_i32(reg1
, reg2
);
3304 tcg_gen_mov_i32(reg2
, temp
);
3305 tcg_temp_free(temp
);
3310 /* exchange Dx and Dy */
3311 do_exg(DREG(insn
, 9), DREG(insn
, 0));
3316 /* exchange Ax and Ay */
3317 do_exg(AREG(insn
, 9), AREG(insn
, 0));
3322 /* exchange Dx and Ay */
3323 do_exg(DREG(insn
, 9), AREG(insn
, 0));
3334 dest
= tcg_temp_new();
3336 opsize
= insn_opsize(insn
);
3337 reg
= DREG(insn
, 9);
3339 SRC_EA(env
, src
, opsize
, 0, &addr
);
3340 tcg_gen_and_i32(dest
, src
, reg
);
3341 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
3343 SRC_EA(env
, src
, opsize
, 0, NULL
);
3344 tcg_gen_and_i32(dest
, src
, reg
);
3345 gen_partset_reg(opsize
, reg
, dest
);
3347 gen_logic_cc(s
, dest
, opsize
);
3348 tcg_temp_free(dest
);
3356 SRC_EA(env
, src
, (insn
& 0x100) ? OS_LONG
: OS_WORD
, 1, NULL
);
3357 reg
= AREG(insn
, 9);
3358 tcg_gen_add_i32(reg
, reg
, src
);
3361 static inline void gen_addx(DisasContext
*s
, TCGv src
, TCGv dest
, int opsize
)
3365 gen_flush_flags(s
); /* compute old Z */
3368 * Perform addition with carry.
3369 * (X, N) = src + dest + X;
3372 tmp
= tcg_const_i32(0);
3373 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, QREG_CC_X
, tmp
, dest
, tmp
);
3374 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, QREG_CC_N
, QREG_CC_X
, src
, tmp
);
3375 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
3377 /* Compute signed-overflow for addition. */
3379 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_N
, src
);
3380 tcg_gen_xor_i32(tmp
, dest
, src
);
3381 tcg_gen_andc_i32(QREG_CC_V
, QREG_CC_V
, tmp
);
3384 /* Copy the rest of the results into place. */
3385 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
); /* !Z is sticky */
3386 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
3388 set_cc_op(s
, CC_OP_FLAGS
);
3390 /* result is in QREG_CC_N */
3393 DISAS_INSN(addx_reg
)
3399 opsize
= insn_opsize(insn
);
3401 dest
= gen_extend(s
, DREG(insn
, 9), opsize
, 1);
3402 src
= gen_extend(s
, DREG(insn
, 0), opsize
, 1);
3404 gen_addx(s
, src
, dest
, opsize
);
3406 gen_partset_reg(opsize
, DREG(insn
, 9), QREG_CC_N
);
3409 DISAS_INSN(addx_mem
)
3417 opsize
= insn_opsize(insn
);
3419 addr_src
= AREG(insn
, 0);
3420 tcg_gen_subi_i32(addr_src
, addr_src
, opsize_bytes(opsize
));
3421 src
= gen_load(s
, opsize
, addr_src
, 1, IS_USER(s
));
3423 addr_dest
= AREG(insn
, 9);
3424 tcg_gen_subi_i32(addr_dest
, addr_dest
, opsize_bytes(opsize
));
3425 dest
= gen_load(s
, opsize
, addr_dest
, 1, IS_USER(s
));
3427 gen_addx(s
, src
, dest
, opsize
);
3429 gen_store(s
, opsize
, addr_dest
, QREG_CC_N
, IS_USER(s
));
3431 tcg_temp_free(dest
);
3435 static inline void shift_im(DisasContext
*s
, uint16_t insn
, int opsize
)
3437 int count
= (insn
>> 9) & 7;
3438 int logical
= insn
& 8;
3439 int left
= insn
& 0x100;
3440 int bits
= opsize_bytes(opsize
) * 8;
3441 TCGv reg
= gen_extend(s
, DREG(insn
, 0), opsize
, !logical
);
3447 tcg_gen_movi_i32(QREG_CC_V
, 0);
3449 tcg_gen_shri_i32(QREG_CC_C
, reg
, bits
- count
);
3450 tcg_gen_shli_i32(QREG_CC_N
, reg
, count
);
3453 * Note that ColdFire always clears V (done above),
3454 * while M68000 sets if the most significant bit is changed at
3455 * any time during the shift operation.
3457 if (!logical
&& m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
3458 /* if shift count >= bits, V is (reg != 0) */
3459 if (count
>= bits
) {
3460 tcg_gen_setcond_i32(TCG_COND_NE
, QREG_CC_V
, reg
, QREG_CC_V
);
3462 TCGv t0
= tcg_temp_new();
3463 tcg_gen_sari_i32(QREG_CC_V
, reg
, bits
- 1);
3464 tcg_gen_sari_i32(t0
, reg
, bits
- count
- 1);
3465 tcg_gen_setcond_i32(TCG_COND_NE
, QREG_CC_V
, QREG_CC_V
, t0
);
3468 tcg_gen_neg_i32(QREG_CC_V
, QREG_CC_V
);
3471 tcg_gen_shri_i32(QREG_CC_C
, reg
, count
- 1);
3473 tcg_gen_shri_i32(QREG_CC_N
, reg
, count
);
3475 tcg_gen_sari_i32(QREG_CC_N
, reg
, count
);
3479 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
3480 tcg_gen_andi_i32(QREG_CC_C
, QREG_CC_C
, 1);
3481 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
3482 tcg_gen_mov_i32(QREG_CC_X
, QREG_CC_C
);
3484 gen_partset_reg(opsize
, DREG(insn
, 0), QREG_CC_N
);
3485 set_cc_op(s
, CC_OP_FLAGS
);
3488 static inline void shift_reg(DisasContext
*s
, uint16_t insn
, int opsize
)
3490 int logical
= insn
& 8;
3491 int left
= insn
& 0x100;
3492 int bits
= opsize_bytes(opsize
) * 8;
3493 TCGv reg
= gen_extend(s
, DREG(insn
, 0), opsize
, !logical
);
3497 t64
= tcg_temp_new_i64();
3498 s64
= tcg_temp_new_i64();
3499 s32
= tcg_temp_new();
3502 * Note that m68k truncates the shift count modulo 64, not 32.
3503 * In addition, a 64-bit shift makes it easy to find "the last
3504 * bit shifted out", for the carry flag.
3506 tcg_gen_andi_i32(s32
, DREG(insn
, 9), 63);
3507 tcg_gen_extu_i32_i64(s64
, s32
);
3508 tcg_gen_extu_i32_i64(t64
, reg
);
3510 /* Optimistically set V=0. Also used as a zero source below. */
3511 tcg_gen_movi_i32(QREG_CC_V
, 0);
3513 tcg_gen_shl_i64(t64
, t64
, s64
);
3515 if (opsize
== OS_LONG
) {
3516 tcg_gen_extr_i64_i32(QREG_CC_N
, QREG_CC_C
, t64
);
3517 /* Note that C=0 if shift count is 0, and we get that for free. */
3519 TCGv zero
= tcg_const_i32(0);
3520 tcg_gen_extrl_i64_i32(QREG_CC_N
, t64
);
3521 tcg_gen_shri_i32(QREG_CC_C
, QREG_CC_N
, bits
);
3522 tcg_gen_movcond_i32(TCG_COND_EQ
, QREG_CC_C
,
3523 s32
, zero
, zero
, QREG_CC_C
);
3524 tcg_temp_free(zero
);
3526 tcg_gen_andi_i32(QREG_CC_C
, QREG_CC_C
, 1);
3528 /* X = C, but only if the shift count was non-zero. */
3529 tcg_gen_movcond_i32(TCG_COND_NE
, QREG_CC_X
, s32
, QREG_CC_V
,
3530 QREG_CC_C
, QREG_CC_X
);
3533 * M68000 sets V if the most significant bit is changed at
3534 * any time during the shift operation. Do this via creating
3535 * an extension of the sign bit, comparing, and discarding
3536 * the bits below the sign bit. I.e.
3537 * int64_t s = (intN_t)reg;
3538 * int64_t t = (int64_t)(intN_t)reg << count;
3539 * V = ((s ^ t) & (-1 << (bits - 1))) != 0
3541 if (!logical
&& m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
3542 TCGv_i64 tt
= tcg_const_i64(32);
3543 /* if shift is greater than 32, use 32 */
3544 tcg_gen_movcond_i64(TCG_COND_GT
, s64
, s64
, tt
, tt
, s64
);
3545 tcg_temp_free_i64(tt
);
3546 /* Sign extend the input to 64 bits; re-do the shift. */
3547 tcg_gen_ext_i32_i64(t64
, reg
);
3548 tcg_gen_shl_i64(s64
, t64
, s64
);
3549 /* Clear all bits that are unchanged. */
3550 tcg_gen_xor_i64(t64
, t64
, s64
);
3551 /* Ignore the bits below the sign bit. */
3552 tcg_gen_andi_i64(t64
, t64
, -1ULL << (bits
- 1));
3553 /* If any bits remain set, we have overflow. */
3554 tcg_gen_setcondi_i64(TCG_COND_NE
, t64
, t64
, 0);
3555 tcg_gen_extrl_i64_i32(QREG_CC_V
, t64
);
3556 tcg_gen_neg_i32(QREG_CC_V
, QREG_CC_V
);
3559 tcg_gen_shli_i64(t64
, t64
, 32);
3561 tcg_gen_shr_i64(t64
, t64
, s64
);
3563 tcg_gen_sar_i64(t64
, t64
, s64
);
3565 tcg_gen_extr_i64_i32(QREG_CC_C
, QREG_CC_N
, t64
);
3567 /* Note that C=0 if shift count is 0, and we get that for free. */
3568 tcg_gen_shri_i32(QREG_CC_C
, QREG_CC_C
, 31);
3570 /* X = C, but only if the shift count was non-zero. */
3571 tcg_gen_movcond_i32(TCG_COND_NE
, QREG_CC_X
, s32
, QREG_CC_V
,
3572 QREG_CC_C
, QREG_CC_X
);
3574 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
3575 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
3578 tcg_temp_free_i64(s64
);
3579 tcg_temp_free_i64(t64
);
3581 /* Write back the result. */
3582 gen_partset_reg(opsize
, DREG(insn
, 0), QREG_CC_N
);
3583 set_cc_op(s
, CC_OP_FLAGS
);
3586 DISAS_INSN(shift8_im
)
3588 shift_im(s
, insn
, OS_BYTE
);
3591 DISAS_INSN(shift16_im
)
3593 shift_im(s
, insn
, OS_WORD
);
3596 DISAS_INSN(shift_im
)
3598 shift_im(s
, insn
, OS_LONG
);
3601 DISAS_INSN(shift8_reg
)
3603 shift_reg(s
, insn
, OS_BYTE
);
3606 DISAS_INSN(shift16_reg
)
3608 shift_reg(s
, insn
, OS_WORD
);
3611 DISAS_INSN(shift_reg
)
3613 shift_reg(s
, insn
, OS_LONG
);
3616 DISAS_INSN(shift_mem
)
3618 int logical
= insn
& 8;
3619 int left
= insn
& 0x100;
3623 SRC_EA(env
, src
, OS_WORD
, !logical
, &addr
);
3624 tcg_gen_movi_i32(QREG_CC_V
, 0);
3626 tcg_gen_shri_i32(QREG_CC_C
, src
, 15);
3627 tcg_gen_shli_i32(QREG_CC_N
, src
, 1);
3630 * Note that ColdFire always clears V,
3631 * while M68000 sets if the most significant bit is changed at
3632 * any time during the shift operation
3634 if (!logical
&& m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
3635 src
= gen_extend(s
, src
, OS_WORD
, 1);
3636 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_N
, src
);
3639 tcg_gen_mov_i32(QREG_CC_C
, src
);
3641 tcg_gen_shri_i32(QREG_CC_N
, src
, 1);
3643 tcg_gen_sari_i32(QREG_CC_N
, src
, 1);
3647 gen_ext(QREG_CC_N
, QREG_CC_N
, OS_WORD
, 1);
3648 tcg_gen_andi_i32(QREG_CC_C
, QREG_CC_C
, 1);
3649 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
3650 tcg_gen_mov_i32(QREG_CC_X
, QREG_CC_C
);
3652 DEST_EA(env
, insn
, OS_WORD
, QREG_CC_N
, &addr
);
3653 set_cc_op(s
, CC_OP_FLAGS
);
3656 static void rotate(TCGv reg
, TCGv shift
, int left
, int size
)
3660 /* Replicate the 8-bit input so that a 32-bit rotate works. */
3661 tcg_gen_ext8u_i32(reg
, reg
);
3662 tcg_gen_muli_i32(reg
, reg
, 0x01010101);
3665 /* Replicate the 16-bit input so that a 32-bit rotate works. */
3666 tcg_gen_deposit_i32(reg
, reg
, reg
, 16, 16);
3671 tcg_gen_rotl_i32(reg
, reg
, shift
);
3673 tcg_gen_rotr_i32(reg
, reg
, shift
);
3681 tcg_gen_ext8s_i32(reg
, reg
);
3684 tcg_gen_ext16s_i32(reg
, reg
);
3690 /* QREG_CC_X is not affected */
3692 tcg_gen_mov_i32(QREG_CC_N
, reg
);
3693 tcg_gen_mov_i32(QREG_CC_Z
, reg
);
3696 tcg_gen_andi_i32(QREG_CC_C
, reg
, 1);
3698 tcg_gen_shri_i32(QREG_CC_C
, reg
, 31);
3701 tcg_gen_movi_i32(QREG_CC_V
, 0); /* always cleared */
3704 static void rotate_x_flags(TCGv reg
, TCGv X
, int size
)
3708 tcg_gen_ext8s_i32(reg
, reg
);
3711 tcg_gen_ext16s_i32(reg
, reg
);
3716 tcg_gen_mov_i32(QREG_CC_N
, reg
);
3717 tcg_gen_mov_i32(QREG_CC_Z
, reg
);
3718 tcg_gen_mov_i32(QREG_CC_X
, X
);
3719 tcg_gen_mov_i32(QREG_CC_C
, X
);
3720 tcg_gen_movi_i32(QREG_CC_V
, 0);
3723 /* Result of rotate_x() is valid if 0 <= shift <= size */
3724 static TCGv
rotate_x(TCGv reg
, TCGv shift
, int left
, int size
)
3726 TCGv X
, shl
, shr
, shx
, sz
, zero
;
3728 sz
= tcg_const_i32(size
);
3730 shr
= tcg_temp_new();
3731 shl
= tcg_temp_new();
3732 shx
= tcg_temp_new();
3734 tcg_gen_mov_i32(shl
, shift
); /* shl = shift */
3735 tcg_gen_movi_i32(shr
, size
+ 1);
3736 tcg_gen_sub_i32(shr
, shr
, shift
); /* shr = size + 1 - shift */
3737 tcg_gen_subi_i32(shx
, shift
, 1); /* shx = shift - 1 */
3738 /* shx = shx < 0 ? size : shx; */
3739 zero
= tcg_const_i32(0);
3740 tcg_gen_movcond_i32(TCG_COND_LT
, shx
, shx
, zero
, sz
, shx
);
3741 tcg_temp_free(zero
);
3743 tcg_gen_mov_i32(shr
, shift
); /* shr = shift */
3744 tcg_gen_movi_i32(shl
, size
+ 1);
3745 tcg_gen_sub_i32(shl
, shl
, shift
); /* shl = size + 1 - shift */
3746 tcg_gen_sub_i32(shx
, sz
, shift
); /* shx = size - shift */
3748 tcg_temp_free_i32(sz
);
3750 /* reg = (reg << shl) | (reg >> shr) | (x << shx); */
3752 tcg_gen_shl_i32(shl
, reg
, shl
);
3753 tcg_gen_shr_i32(shr
, reg
, shr
);
3754 tcg_gen_or_i32(reg
, shl
, shr
);
3757 tcg_gen_shl_i32(shx
, QREG_CC_X
, shx
);
3758 tcg_gen_or_i32(reg
, reg
, shx
);
3761 /* X = (reg >> size) & 1 */
3764 tcg_gen_extract_i32(X
, reg
, size
, 1);
3769 /* Result of rotate32_x() is valid if 0 <= shift < 33 */
3770 static TCGv
rotate32_x(TCGv reg
, TCGv shift
, int left
)
3772 TCGv_i64 t0
, shift64
;
3773 TCGv X
, lo
, hi
, zero
;
3775 shift64
= tcg_temp_new_i64();
3776 tcg_gen_extu_i32_i64(shift64
, shift
);
3778 t0
= tcg_temp_new_i64();
3781 lo
= tcg_temp_new();
3782 hi
= tcg_temp_new();
3785 /* create [reg:X:..] */
3787 tcg_gen_shli_i32(lo
, QREG_CC_X
, 31);
3788 tcg_gen_concat_i32_i64(t0
, lo
, reg
);
3792 tcg_gen_rotl_i64(t0
, t0
, shift64
);
3793 tcg_temp_free_i64(shift64
);
3795 /* result is [reg:..:reg:X] */
3797 tcg_gen_extr_i64_i32(lo
, hi
, t0
);
3798 tcg_gen_andi_i32(X
, lo
, 1);
3800 tcg_gen_shri_i32(lo
, lo
, 1);
3802 /* create [..:X:reg] */
3804 tcg_gen_concat_i32_i64(t0
, reg
, QREG_CC_X
);
3806 tcg_gen_rotr_i64(t0
, t0
, shift64
);
3807 tcg_temp_free_i64(shift64
);
3809 /* result is value: [X:reg:..:reg] */
3811 tcg_gen_extr_i64_i32(lo
, hi
, t0
);
3815 tcg_gen_shri_i32(X
, hi
, 31);
3817 /* extract result */
3819 tcg_gen_shli_i32(hi
, hi
, 1);
3821 tcg_temp_free_i64(t0
);
3822 tcg_gen_or_i32(lo
, lo
, hi
);
3825 /* if shift == 0, register and X are not affected */
3827 zero
= tcg_const_i32(0);
3828 tcg_gen_movcond_i32(TCG_COND_EQ
, X
, shift
, zero
, QREG_CC_X
, X
);
3829 tcg_gen_movcond_i32(TCG_COND_EQ
, reg
, shift
, zero
, reg
, lo
);
3830 tcg_temp_free(zero
);
3836 DISAS_INSN(rotate_im
)
3840 int left
= (insn
& 0x100);
3842 tmp
= (insn
>> 9) & 7;
3847 shift
= tcg_const_i32(tmp
);
3849 rotate(DREG(insn
, 0), shift
, left
, 32);
3851 TCGv X
= rotate32_x(DREG(insn
, 0), shift
, left
);
3852 rotate_x_flags(DREG(insn
, 0), X
, 32);
3855 tcg_temp_free(shift
);
3857 set_cc_op(s
, CC_OP_FLAGS
);
3860 DISAS_INSN(rotate8_im
)
3862 int left
= (insn
& 0x100);
3867 reg
= gen_extend(s
, DREG(insn
, 0), OS_BYTE
, 0);
3869 tmp
= (insn
>> 9) & 7;
3874 shift
= tcg_const_i32(tmp
);
3876 rotate(reg
, shift
, left
, 8);
3878 TCGv X
= rotate_x(reg
, shift
, left
, 8);
3879 rotate_x_flags(reg
, X
, 8);
3882 tcg_temp_free(shift
);
3883 gen_partset_reg(OS_BYTE
, DREG(insn
, 0), reg
);
3884 set_cc_op(s
, CC_OP_FLAGS
);
3887 DISAS_INSN(rotate16_im
)
3889 int left
= (insn
& 0x100);
3894 reg
= gen_extend(s
, DREG(insn
, 0), OS_WORD
, 0);
3895 tmp
= (insn
>> 9) & 7;
3900 shift
= tcg_const_i32(tmp
);
3902 rotate(reg
, shift
, left
, 16);
3904 TCGv X
= rotate_x(reg
, shift
, left
, 16);
3905 rotate_x_flags(reg
, X
, 16);
3908 tcg_temp_free(shift
);
3909 gen_partset_reg(OS_WORD
, DREG(insn
, 0), reg
);
3910 set_cc_op(s
, CC_OP_FLAGS
);
3913 DISAS_INSN(rotate_reg
)
3918 int left
= (insn
& 0x100);
3920 reg
= DREG(insn
, 0);
3921 src
= DREG(insn
, 9);
3922 /* shift in [0..63] */
3923 t0
= tcg_temp_new();
3924 tcg_gen_andi_i32(t0
, src
, 63);
3925 t1
= tcg_temp_new_i32();
3927 tcg_gen_andi_i32(t1
, src
, 31);
3928 rotate(reg
, t1
, left
, 32);
3929 /* if shift == 0, clear C */
3930 tcg_gen_movcond_i32(TCG_COND_EQ
, QREG_CC_C
,
3931 t0
, QREG_CC_V
/* 0 */,
3932 QREG_CC_V
/* 0 */, QREG_CC_C
);
3936 tcg_gen_movi_i32(t1
, 33);
3937 tcg_gen_remu_i32(t1
, t0
, t1
);
3938 X
= rotate32_x(DREG(insn
, 0), t1
, left
);
3939 rotate_x_flags(DREG(insn
, 0), X
, 32);
3944 set_cc_op(s
, CC_OP_FLAGS
);
3947 DISAS_INSN(rotate8_reg
)
3952 int left
= (insn
& 0x100);
3954 reg
= gen_extend(s
, DREG(insn
, 0), OS_BYTE
, 0);
3955 src
= DREG(insn
, 9);
3956 /* shift in [0..63] */
3957 t0
= tcg_temp_new_i32();
3958 tcg_gen_andi_i32(t0
, src
, 63);
3959 t1
= tcg_temp_new_i32();
3961 tcg_gen_andi_i32(t1
, src
, 7);
3962 rotate(reg
, t1
, left
, 8);
3963 /* if shift == 0, clear C */
3964 tcg_gen_movcond_i32(TCG_COND_EQ
, QREG_CC_C
,
3965 t0
, QREG_CC_V
/* 0 */,
3966 QREG_CC_V
/* 0 */, QREG_CC_C
);
3970 tcg_gen_movi_i32(t1
, 9);
3971 tcg_gen_remu_i32(t1
, t0
, t1
);
3972 X
= rotate_x(reg
, t1
, left
, 8);
3973 rotate_x_flags(reg
, X
, 8);
3978 gen_partset_reg(OS_BYTE
, DREG(insn
, 0), reg
);
3979 set_cc_op(s
, CC_OP_FLAGS
);
3982 DISAS_INSN(rotate16_reg
)
3987 int left
= (insn
& 0x100);
3989 reg
= gen_extend(s
, DREG(insn
, 0), OS_WORD
, 0);
3990 src
= DREG(insn
, 9);
3991 /* shift in [0..63] */
3992 t0
= tcg_temp_new_i32();
3993 tcg_gen_andi_i32(t0
, src
, 63);
3994 t1
= tcg_temp_new_i32();
3996 tcg_gen_andi_i32(t1
, src
, 15);
3997 rotate(reg
, t1
, left
, 16);
3998 /* if shift == 0, clear C */
3999 tcg_gen_movcond_i32(TCG_COND_EQ
, QREG_CC_C
,
4000 t0
, QREG_CC_V
/* 0 */,
4001 QREG_CC_V
/* 0 */, QREG_CC_C
);
4005 tcg_gen_movi_i32(t1
, 17);
4006 tcg_gen_remu_i32(t1
, t0
, t1
);
4007 X
= rotate_x(reg
, t1
, left
, 16);
4008 rotate_x_flags(reg
, X
, 16);
4013 gen_partset_reg(OS_WORD
, DREG(insn
, 0), reg
);
4014 set_cc_op(s
, CC_OP_FLAGS
);
4017 DISAS_INSN(rotate_mem
)
4022 int left
= (insn
& 0x100);
4024 SRC_EA(env
, src
, OS_WORD
, 0, &addr
);
4026 shift
= tcg_const_i32(1);
4027 if (insn
& 0x0200) {
4028 rotate(src
, shift
, left
, 16);
4030 TCGv X
= rotate_x(src
, shift
, left
, 16);
4031 rotate_x_flags(src
, X
, 16);
4034 tcg_temp_free(shift
);
4035 DEST_EA(env
, insn
, OS_WORD
, src
, &addr
);
4036 set_cc_op(s
, CC_OP_FLAGS
);
4039 DISAS_INSN(bfext_reg
)
4041 int ext
= read_im16(env
, s
);
4042 int is_sign
= insn
& 0x200;
4043 TCGv src
= DREG(insn
, 0);
4044 TCGv dst
= DREG(ext
, 12);
4045 int len
= ((extract32(ext
, 0, 5) - 1) & 31) + 1;
4046 int ofs
= extract32(ext
, 6, 5); /* big bit-endian */
4047 int pos
= 32 - ofs
- len
; /* little bit-endian */
4048 TCGv tmp
= tcg_temp_new();
4052 * In general, we're going to rotate the field so that it's at the
4053 * top of the word and then right-shift by the complement of the
4054 * width to extend the field.
4057 /* Variable width. */
4059 /* Variable offset. */
4060 tcg_gen_andi_i32(tmp
, DREG(ext
, 6), 31);
4061 tcg_gen_rotl_i32(tmp
, src
, tmp
);
4063 tcg_gen_rotli_i32(tmp
, src
, ofs
);
4066 shift
= tcg_temp_new();
4067 tcg_gen_neg_i32(shift
, DREG(ext
, 0));
4068 tcg_gen_andi_i32(shift
, shift
, 31);
4069 tcg_gen_sar_i32(QREG_CC_N
, tmp
, shift
);
4071 tcg_gen_mov_i32(dst
, QREG_CC_N
);
4073 tcg_gen_shr_i32(dst
, tmp
, shift
);
4075 tcg_temp_free(shift
);
4077 /* Immediate width. */
4079 /* Variable offset */
4080 tcg_gen_andi_i32(tmp
, DREG(ext
, 6), 31);
4081 tcg_gen_rotl_i32(tmp
, src
, tmp
);
4086 * Immediate offset. If the field doesn't wrap around the
4087 * end of the word, rely on (s)extract completely.
4090 tcg_gen_rotli_i32(tmp
, src
, ofs
);
4096 tcg_gen_sextract_i32(QREG_CC_N
, src
, pos
, len
);
4098 tcg_gen_mov_i32(dst
, QREG_CC_N
);
4100 tcg_gen_extract_i32(dst
, src
, pos
, len
);
4105 set_cc_op(s
, CC_OP_LOGIC
);
4108 DISAS_INSN(bfext_mem
)
4110 int ext
= read_im16(env
, s
);
4111 int is_sign
= insn
& 0x200;
4112 TCGv dest
= DREG(ext
, 12);
4113 TCGv addr
, len
, ofs
;
4115 addr
= gen_lea(env
, s
, insn
, OS_UNSIZED
);
4116 if (IS_NULL_QREG(addr
)) {
4124 len
= tcg_const_i32(extract32(ext
, 0, 5));
4129 ofs
= tcg_const_i32(extract32(ext
, 6, 5));
4133 gen_helper_bfexts_mem(dest
, cpu_env
, addr
, ofs
, len
);
4134 tcg_gen_mov_i32(QREG_CC_N
, dest
);
4136 TCGv_i64 tmp
= tcg_temp_new_i64();
4137 gen_helper_bfextu_mem(tmp
, cpu_env
, addr
, ofs
, len
);
4138 tcg_gen_extr_i64_i32(dest
, QREG_CC_N
, tmp
);
4139 tcg_temp_free_i64(tmp
);
4141 set_cc_op(s
, CC_OP_LOGIC
);
4143 if (!(ext
& 0x20)) {
4146 if (!(ext
& 0x800)) {
4151 DISAS_INSN(bfop_reg
)
4153 int ext
= read_im16(env
, s
);
4154 TCGv src
= DREG(insn
, 0);
4155 int len
= ((extract32(ext
, 0, 5) - 1) & 31) + 1;
4156 int ofs
= extract32(ext
, 6, 5); /* big bit-endian */
4157 TCGv mask
, tofs
, tlen
;
4161 if ((insn
& 0x0f00) == 0x0d00) { /* bfffo */
4162 tofs
= tcg_temp_new();
4163 tlen
= tcg_temp_new();
4166 if ((ext
& 0x820) == 0) {
4167 /* Immediate width and offset. */
4168 uint32_t maski
= 0x7fffffffu
>> (len
- 1);
4169 if (ofs
+ len
<= 32) {
4170 tcg_gen_shli_i32(QREG_CC_N
, src
, ofs
);
4172 tcg_gen_rotli_i32(QREG_CC_N
, src
, ofs
);
4174 tcg_gen_andi_i32(QREG_CC_N
, QREG_CC_N
, ~maski
);
4175 mask
= tcg_const_i32(ror32(maski
, ofs
));
4177 tcg_gen_movi_i32(tofs
, ofs
);
4178 tcg_gen_movi_i32(tlen
, len
);
4181 TCGv tmp
= tcg_temp_new();
4183 /* Variable width */
4184 tcg_gen_subi_i32(tmp
, DREG(ext
, 0), 1);
4185 tcg_gen_andi_i32(tmp
, tmp
, 31);
4186 mask
= tcg_const_i32(0x7fffffffu
);
4187 tcg_gen_shr_i32(mask
, mask
, tmp
);
4189 tcg_gen_addi_i32(tlen
, tmp
, 1);
4192 /* Immediate width */
4193 mask
= tcg_const_i32(0x7fffffffu
>> (len
- 1));
4195 tcg_gen_movi_i32(tlen
, len
);
4199 /* Variable offset */
4200 tcg_gen_andi_i32(tmp
, DREG(ext
, 6), 31);
4201 tcg_gen_rotl_i32(QREG_CC_N
, src
, tmp
);
4202 tcg_gen_andc_i32(QREG_CC_N
, QREG_CC_N
, mask
);
4203 tcg_gen_rotr_i32(mask
, mask
, tmp
);
4205 tcg_gen_mov_i32(tofs
, tmp
);
4208 /* Immediate offset (and variable width) */
4209 tcg_gen_rotli_i32(QREG_CC_N
, src
, ofs
);
4210 tcg_gen_andc_i32(QREG_CC_N
, QREG_CC_N
, mask
);
4211 tcg_gen_rotri_i32(mask
, mask
, ofs
);
4213 tcg_gen_movi_i32(tofs
, ofs
);
4218 set_cc_op(s
, CC_OP_LOGIC
);
4220 switch (insn
& 0x0f00) {
4221 case 0x0a00: /* bfchg */
4222 tcg_gen_eqv_i32(src
, src
, mask
);
4224 case 0x0c00: /* bfclr */
4225 tcg_gen_and_i32(src
, src
, mask
);
4227 case 0x0d00: /* bfffo */
4228 gen_helper_bfffo_reg(DREG(ext
, 12), QREG_CC_N
, tofs
, tlen
);
4229 tcg_temp_free(tlen
);
4230 tcg_temp_free(tofs
);
4232 case 0x0e00: /* bfset */
4233 tcg_gen_orc_i32(src
, src
, mask
);
4235 case 0x0800: /* bftst */
4236 /* flags already set; no other work to do. */
4239 g_assert_not_reached();
4241 tcg_temp_free(mask
);
4244 DISAS_INSN(bfop_mem
)
4246 int ext
= read_im16(env
, s
);
4247 TCGv addr
, len
, ofs
;
4250 addr
= gen_lea(env
, s
, insn
, OS_UNSIZED
);
4251 if (IS_NULL_QREG(addr
)) {
4259 len
= tcg_const_i32(extract32(ext
, 0, 5));
4264 ofs
= tcg_const_i32(extract32(ext
, 6, 5));
4267 switch (insn
& 0x0f00) {
4268 case 0x0a00: /* bfchg */
4269 gen_helper_bfchg_mem(QREG_CC_N
, cpu_env
, addr
, ofs
, len
);
4271 case 0x0c00: /* bfclr */
4272 gen_helper_bfclr_mem(QREG_CC_N
, cpu_env
, addr
, ofs
, len
);
4274 case 0x0d00: /* bfffo */
4275 t64
= tcg_temp_new_i64();
4276 gen_helper_bfffo_mem(t64
, cpu_env
, addr
, ofs
, len
);
4277 tcg_gen_extr_i64_i32(DREG(ext
, 12), QREG_CC_N
, t64
);
4278 tcg_temp_free_i64(t64
);
4280 case 0x0e00: /* bfset */
4281 gen_helper_bfset_mem(QREG_CC_N
, cpu_env
, addr
, ofs
, len
);
4283 case 0x0800: /* bftst */
4284 gen_helper_bfexts_mem(QREG_CC_N
, cpu_env
, addr
, ofs
, len
);
4287 g_assert_not_reached();
4289 set_cc_op(s
, CC_OP_LOGIC
);
4291 if (!(ext
& 0x20)) {
4294 if (!(ext
& 0x800)) {
4299 DISAS_INSN(bfins_reg
)
4301 int ext
= read_im16(env
, s
);
4302 TCGv dst
= DREG(insn
, 0);
4303 TCGv src
= DREG(ext
, 12);
4304 int len
= ((extract32(ext
, 0, 5) - 1) & 31) + 1;
4305 int ofs
= extract32(ext
, 6, 5); /* big bit-endian */
4306 int pos
= 32 - ofs
- len
; /* little bit-endian */
4309 tmp
= tcg_temp_new();
4312 /* Variable width */
4313 tcg_gen_neg_i32(tmp
, DREG(ext
, 0));
4314 tcg_gen_andi_i32(tmp
, tmp
, 31);
4315 tcg_gen_shl_i32(QREG_CC_N
, src
, tmp
);
4317 /* Immediate width */
4318 tcg_gen_shli_i32(QREG_CC_N
, src
, 32 - len
);
4320 set_cc_op(s
, CC_OP_LOGIC
);
4322 /* Immediate width and offset */
4323 if ((ext
& 0x820) == 0) {
4324 /* Check for suitability for deposit. */
4326 tcg_gen_deposit_i32(dst
, dst
, src
, pos
, len
);
4328 uint32_t maski
= -2U << (len
- 1);
4329 uint32_t roti
= (ofs
+ len
) & 31;
4330 tcg_gen_andi_i32(tmp
, src
, ~maski
);
4331 tcg_gen_rotri_i32(tmp
, tmp
, roti
);
4332 tcg_gen_andi_i32(dst
, dst
, ror32(maski
, roti
));
4333 tcg_gen_or_i32(dst
, dst
, tmp
);
4336 TCGv mask
= tcg_temp_new();
4337 TCGv rot
= tcg_temp_new();
4340 /* Variable width */
4341 tcg_gen_subi_i32(rot
, DREG(ext
, 0), 1);
4342 tcg_gen_andi_i32(rot
, rot
, 31);
4343 tcg_gen_movi_i32(mask
, -2);
4344 tcg_gen_shl_i32(mask
, mask
, rot
);
4345 tcg_gen_mov_i32(rot
, DREG(ext
, 0));
4346 tcg_gen_andc_i32(tmp
, src
, mask
);
4348 /* Immediate width (variable offset) */
4349 uint32_t maski
= -2U << (len
- 1);
4350 tcg_gen_andi_i32(tmp
, src
, ~maski
);
4351 tcg_gen_movi_i32(mask
, maski
);
4352 tcg_gen_movi_i32(rot
, len
& 31);
4355 /* Variable offset */
4356 tcg_gen_add_i32(rot
, rot
, DREG(ext
, 6));
4358 /* Immediate offset (variable width) */
4359 tcg_gen_addi_i32(rot
, rot
, ofs
);
4361 tcg_gen_andi_i32(rot
, rot
, 31);
4362 tcg_gen_rotr_i32(mask
, mask
, rot
);
4363 tcg_gen_rotr_i32(tmp
, tmp
, rot
);
4364 tcg_gen_and_i32(dst
, dst
, mask
);
4365 tcg_gen_or_i32(dst
, dst
, tmp
);
4368 tcg_temp_free(mask
);
4373 DISAS_INSN(bfins_mem
)
4375 int ext
= read_im16(env
, s
);
4376 TCGv src
= DREG(ext
, 12);
4377 TCGv addr
, len
, ofs
;
4379 addr
= gen_lea(env
, s
, insn
, OS_UNSIZED
);
4380 if (IS_NULL_QREG(addr
)) {
4388 len
= tcg_const_i32(extract32(ext
, 0, 5));
4393 ofs
= tcg_const_i32(extract32(ext
, 6, 5));
4396 gen_helper_bfins_mem(QREG_CC_N
, cpu_env
, addr
, src
, ofs
, len
);
4397 set_cc_op(s
, CC_OP_LOGIC
);
4399 if (!(ext
& 0x20)) {
4402 if (!(ext
& 0x800)) {
4410 reg
= DREG(insn
, 0);
4411 gen_logic_cc(s
, reg
, OS_LONG
);
4412 gen_helper_ff1(reg
, reg
);
4420 switch ((insn
>> 7) & 3) {
4425 if (m68k_feature(env
, M68K_FEATURE_CHK2
)) {
4431 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
4434 SRC_EA(env
, src
, opsize
, 1, NULL
);
4435 reg
= gen_extend(s
, DREG(insn
, 9), opsize
, 1);
4438 gen_helper_chk(cpu_env
, reg
, src
);
4444 TCGv addr1
, addr2
, bound1
, bound2
, reg
;
4447 switch ((insn
>> 9) & 3) {
4458 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
4462 ext
= read_im16(env
, s
);
4463 if ((ext
& 0x0800) == 0) {
4464 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
4468 addr1
= gen_lea(env
, s
, insn
, OS_UNSIZED
);
4469 addr2
= tcg_temp_new();
4470 tcg_gen_addi_i32(addr2
, addr1
, opsize_bytes(opsize
));
4472 bound1
= gen_load(s
, opsize
, addr1
, 1, IS_USER(s
));
4473 tcg_temp_free(addr1
);
4474 bound2
= gen_load(s
, opsize
, addr2
, 1, IS_USER(s
));
4475 tcg_temp_free(addr2
);
4477 reg
= tcg_temp_new();
4479 tcg_gen_mov_i32(reg
, AREG(ext
, 12));
4481 gen_ext(reg
, DREG(ext
, 12), opsize
, 1);
4485 gen_helper_chk2(cpu_env
, reg
, bound1
, bound2
);
4487 tcg_temp_free(bound1
);
4488 tcg_temp_free(bound2
);
4491 static void m68k_copy_line(TCGv dst
, TCGv src
, int index
)
4496 addr
= tcg_temp_new();
4498 t0
= tcg_temp_new_i64();
4499 t1
= tcg_temp_new_i64();
4501 tcg_gen_andi_i32(addr
, src
, ~15);
4502 tcg_gen_qemu_ld64(t0
, addr
, index
);
4503 tcg_gen_addi_i32(addr
, addr
, 8);
4504 tcg_gen_qemu_ld64(t1
, addr
, index
);
4506 tcg_gen_andi_i32(addr
, dst
, ~15);
4507 tcg_gen_qemu_st64(t0
, addr
, index
);
4508 tcg_gen_addi_i32(addr
, addr
, 8);
4509 tcg_gen_qemu_st64(t1
, addr
, index
);
4511 tcg_temp_free_i64(t0
);
4512 tcg_temp_free_i64(t1
);
4513 tcg_temp_free(addr
);
4516 DISAS_INSN(move16_reg
)
4518 int index
= IS_USER(s
);
4522 ext
= read_im16(env
, s
);
4523 if ((ext
& (1 << 15)) == 0) {
4524 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
4527 m68k_copy_line(AREG(ext
, 12), AREG(insn
, 0), index
);
4529 /* Ax can be Ay, so save Ay before incrementing Ax */
4530 tmp
= tcg_temp_new();
4531 tcg_gen_mov_i32(tmp
, AREG(ext
, 12));
4532 tcg_gen_addi_i32(AREG(insn
, 0), AREG(insn
, 0), 16);
4533 tcg_gen_addi_i32(AREG(ext
, 12), tmp
, 16);
4537 DISAS_INSN(move16_mem
)
4539 int index
= IS_USER(s
);
4542 reg
= AREG(insn
, 0);
4543 addr
= tcg_const_i32(read_im32(env
, s
));
4545 if ((insn
>> 3) & 1) {
4546 /* MOVE16 (xxx).L, (Ay) */
4547 m68k_copy_line(reg
, addr
, index
);
4549 /* MOVE16 (Ay), (xxx).L */
4550 m68k_copy_line(addr
, reg
, index
);
4553 tcg_temp_free(addr
);
4555 if (((insn
>> 3) & 2) == 0) {
4557 tcg_gen_addi_i32(reg
, reg
, 16);
4567 ext
= read_im16(env
, s
);
4568 if (ext
!= 0x46FC) {
4569 gen_exception(s
, addr
, EXCP_ILLEGAL
);
4572 ext
= read_im16(env
, s
);
4573 if (IS_USER(s
) || (ext
& SR_S
) == 0) {
4574 gen_exception(s
, addr
, EXCP_PRIVILEGE
);
4577 gen_push(s
, gen_get_sr(s
));
4578 gen_set_sr_im(s
, ext
, 0);
4581 DISAS_INSN(move_from_sr
)
4585 if (IS_USER(s
) && !m68k_feature(env
, M68K_FEATURE_M68000
)) {
4586 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4590 DEST_EA(env
, insn
, OS_WORD
, sr
, NULL
);
4593 #if defined(CONFIG_SOFTMMU)
4603 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4607 ext
= read_im16(env
, s
);
4609 opsize
= insn_opsize(insn
);
4612 /* address register */
4613 reg
= AREG(ext
, 12);
4617 reg
= DREG(ext
, 12);
4621 addr
= gen_lea(env
, s
, insn
, opsize
);
4622 if (IS_NULL_QREG(addr
)) {
4628 /* from reg to ea */
4629 gen_store(s
, opsize
, addr
, reg
, DFC_INDEX(s
));
4631 /* from ea to reg */
4632 TCGv tmp
= gen_load(s
, opsize
, addr
, 0, SFC_INDEX(s
));
4634 gen_ext(reg
, tmp
, opsize
, 1);
4636 gen_partset_reg(opsize
, reg
, tmp
);
4640 switch (extract32(insn
, 3, 3)) {
4641 case 3: /* Indirect postincrement. */
4642 tcg_gen_addi_i32(AREG(insn
, 0), addr
,
4643 REG(insn
, 0) == 7 && opsize
== OS_BYTE
4645 : opsize_bytes(opsize
));
4647 case 4: /* Indirect predecrememnt. */
4648 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
4653 DISAS_INSN(move_to_sr
)
4656 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4659 gen_move_to_sr(env
, s
, insn
, false);
4663 DISAS_INSN(move_from_usp
)
4666 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4669 tcg_gen_ld_i32(AREG(insn
, 0), cpu_env
,
4670 offsetof(CPUM68KState
, sp
[M68K_USP
]));
4673 DISAS_INSN(move_to_usp
)
4676 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4679 tcg_gen_st_i32(AREG(insn
, 0), cpu_env
,
4680 offsetof(CPUM68KState
, sp
[M68K_USP
]));
4686 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4690 gen_exception(s
, s
->pc
, EXCP_HALT_INSN
);
4698 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4702 ext
= read_im16(env
, s
);
4704 gen_set_sr_im(s
, ext
, 0);
4705 tcg_gen_movi_i32(cpu_halted
, 1);
4706 gen_exception(s
, s
->pc
, EXCP_HLT
);
4712 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4715 gen_exception(s
, s
->base
.pc_next
, EXCP_RTE
);
4718 DISAS_INSN(cf_movec
)
4724 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4728 ext
= read_im16(env
, s
);
4731 reg
= AREG(ext
, 12);
4733 reg
= DREG(ext
, 12);
4735 gen_helper_cf_movec_to(cpu_env
, tcg_const_i32(ext
& 0xfff), reg
);
4739 DISAS_INSN(m68k_movec
)
4745 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4749 ext
= read_im16(env
, s
);
4752 reg
= AREG(ext
, 12);
4754 reg
= DREG(ext
, 12);
4757 gen_helper_m68k_movec_to(cpu_env
, tcg_const_i32(ext
& 0xfff), reg
);
4759 gen_helper_m68k_movec_from(reg
, cpu_env
, tcg_const_i32(ext
& 0xfff));
4767 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4770 /* ICache fetch. Implement as no-op. */
4776 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4779 /* Cache push/invalidate. Implement as no-op. */
4785 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4788 /* Cache push/invalidate. Implement as no-op. */
4794 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4797 /* Invalidate cache line. Implement as no-op. */
4800 #if defined(CONFIG_SOFTMMU)
4806 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4810 opmode
= tcg_const_i32((insn
>> 3) & 3);
4811 gen_helper_pflush(cpu_env
, AREG(insn
, 0), opmode
);
4812 tcg_temp_free(opmode
);
4820 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4823 is_read
= tcg_const_i32((insn
>> 5) & 1);
4824 gen_helper_ptest(cpu_env
, AREG(insn
, 0), is_read
);
4825 tcg_temp_free(is_read
);
4831 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4837 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
4840 /* TODO: Implement wdebug. */
4841 cpu_abort(env_cpu(env
), "WDEBUG not implemented");
4847 gen_exception(s
, s
->base
.pc_next
, EXCP_TRAP0
+ (insn
& 0xf));
4850 static void gen_load_fcr(DisasContext
*s
, TCGv res
, int reg
)
4854 tcg_gen_movi_i32(res
, 0);
4857 tcg_gen_ld_i32(res
, cpu_env
, offsetof(CPUM68KState
, fpsr
));
4860 tcg_gen_ld_i32(res
, cpu_env
, offsetof(CPUM68KState
, fpcr
));
4865 static void gen_store_fcr(DisasContext
*s
, TCGv val
, int reg
)
4871 tcg_gen_st_i32(val
, cpu_env
, offsetof(CPUM68KState
, fpsr
));
4874 gen_helper_set_fpcr(cpu_env
, val
);
4879 static void gen_qemu_store_fcr(DisasContext
*s
, TCGv addr
, int reg
)
4881 int index
= IS_USER(s
);
4884 tmp
= tcg_temp_new();
4885 gen_load_fcr(s
, tmp
, reg
);
4886 tcg_gen_qemu_st32(tmp
, addr
, index
);
4890 static void gen_qemu_load_fcr(DisasContext
*s
, TCGv addr
, int reg
)
4892 int index
= IS_USER(s
);
4895 tmp
= tcg_temp_new();
4896 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
4897 gen_store_fcr(s
, tmp
, reg
);
4902 static void gen_op_fmove_fcr(CPUM68KState
*env
, DisasContext
*s
,
4903 uint32_t insn
, uint32_t ext
)
4905 int mask
= (ext
>> 10) & 7;
4906 int is_write
= (ext
>> 13) & 1;
4907 int mode
= extract32(insn
, 3, 3);
4913 if (mask
!= M68K_FPIAR
&& mask
!= M68K_FPSR
&& mask
!= M68K_FPCR
) {
4914 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
4918 gen_load_fcr(s
, DREG(insn
, 0), mask
);
4920 gen_store_fcr(s
, DREG(insn
, 0), mask
);
4923 case 1: /* An, only with FPIAR */
4924 if (mask
!= M68K_FPIAR
) {
4925 gen_exception(s
, s
->base
.pc_next
, EXCP_ILLEGAL
);
4929 gen_load_fcr(s
, AREG(insn
, 0), mask
);
4931 gen_store_fcr(s
, AREG(insn
, 0), mask
);
4938 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
4939 if (IS_NULL_QREG(tmp
)) {
4944 addr
= tcg_temp_new();
4945 tcg_gen_mov_i32(addr
, tmp
);
4950 * 0b100 Floating-Point Control Register
4951 * 0b010 Floating-Point Status Register
4952 * 0b001 Floating-Point Instruction Address Register
4956 if (is_write
&& mode
== 4) {
4957 for (i
= 2; i
>= 0; i
--, mask
>>= 1) {
4959 gen_qemu_store_fcr(s
, addr
, 1 << i
);
4961 tcg_gen_subi_i32(addr
, addr
, opsize_bytes(OS_LONG
));
4965 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
4967 for (i
= 0; i
< 3; i
++, mask
>>= 1) {
4970 gen_qemu_store_fcr(s
, addr
, 1 << i
);
4972 gen_qemu_load_fcr(s
, addr
, 1 << i
);
4974 if (mask
!= 1 || mode
== 3) {
4975 tcg_gen_addi_i32(addr
, addr
, opsize_bytes(OS_LONG
));
4980 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
4983 tcg_temp_free_i32(addr
);
4986 static void gen_op_fmovem(CPUM68KState
*env
, DisasContext
*s
,
4987 uint32_t insn
, uint32_t ext
)
4991 int mode
= (ext
>> 11) & 0x3;
4992 int is_load
= ((ext
& 0x2000) == 0);
4994 if (m68k_feature(s
->env
, M68K_FEATURE_FPU
)) {
4995 opsize
= OS_EXTENDED
;
4997 opsize
= OS_DOUBLE
; /* FIXME */
5000 addr
= gen_lea(env
, s
, insn
, opsize
);
5001 if (IS_NULL_QREG(addr
)) {
5006 tmp
= tcg_temp_new();
5008 /* Dynamic register list */
5009 tcg_gen_ext8u_i32(tmp
, DREG(ext
, 4));
5011 /* Static register list */
5012 tcg_gen_movi_i32(tmp
, ext
& 0xff);
5015 if (!is_load
&& (mode
& 2) == 0) {
5017 * predecrement addressing mode
5018 * only available to store register to memory
5020 if (opsize
== OS_EXTENDED
) {
5021 gen_helper_fmovemx_st_predec(tmp
, cpu_env
, addr
, tmp
);
5023 gen_helper_fmovemd_st_predec(tmp
, cpu_env
, addr
, tmp
);
5026 /* postincrement addressing mode */
5027 if (opsize
== OS_EXTENDED
) {
5029 gen_helper_fmovemx_ld_postinc(tmp
, cpu_env
, addr
, tmp
);
5031 gen_helper_fmovemx_st_postinc(tmp
, cpu_env
, addr
, tmp
);
5035 gen_helper_fmovemd_ld_postinc(tmp
, cpu_env
, addr
, tmp
);
5037 gen_helper_fmovemd_st_postinc(tmp
, cpu_env
, addr
, tmp
);
5041 if ((insn
& 070) == 030 || (insn
& 070) == 040) {
5042 tcg_gen_mov_i32(AREG(insn
, 0), tmp
);
5048 * ??? FP exceptions are not implemented. Most exceptions are deferred until
5049 * immediately before the next FP instruction is executed.
5056 TCGv_ptr cpu_src
, cpu_dest
;
5058 ext
= read_im16(env
, s
);
5059 opmode
= ext
& 0x7f;
5060 switch ((ext
>> 13) & 7) {
5066 if (insn
== 0xf200 && (ext
& 0xfc00) == 0x5c00) {
5068 TCGv rom_offset
= tcg_const_i32(opmode
);
5069 cpu_dest
= gen_fp_ptr(REG(ext
, 7));
5070 gen_helper_fconst(cpu_env
, cpu_dest
, rom_offset
);
5071 tcg_temp_free_ptr(cpu_dest
);
5072 tcg_temp_free(rom_offset
);
5076 case 3: /* fmove out */
5077 cpu_src
= gen_fp_ptr(REG(ext
, 7));
5078 opsize
= ext_opsize(ext
, 10);
5079 if (gen_ea_fp(env
, s
, insn
, opsize
, cpu_src
,
5080 EA_STORE
, IS_USER(s
)) == -1) {
5083 gen_helper_ftst(cpu_env
, cpu_src
);
5084 tcg_temp_free_ptr(cpu_src
);
5086 case 4: /* fmove to control register. */
5087 case 5: /* fmove from control register. */
5088 gen_op_fmove_fcr(env
, s
, insn
, ext
);
5090 case 6: /* fmovem */
5092 if ((ext
& 0x1000) == 0 && !m68k_feature(s
->env
, M68K_FEATURE_FPU
)) {
5095 gen_op_fmovem(env
, s
, insn
, ext
);
5098 if (ext
& (1 << 14)) {
5099 /* Source effective address. */
5100 opsize
= ext_opsize(ext
, 10);
5101 cpu_src
= gen_fp_result_ptr();
5102 if (gen_ea_fp(env
, s
, insn
, opsize
, cpu_src
,
5103 EA_LOADS
, IS_USER(s
)) == -1) {
5108 /* Source register. */
5109 opsize
= OS_EXTENDED
;
5110 cpu_src
= gen_fp_ptr(REG(ext
, 10));
5112 cpu_dest
= gen_fp_ptr(REG(ext
, 7));
5115 gen_fp_move(cpu_dest
, cpu_src
);
5117 case 0x40: /* fsmove */
5118 gen_helper_fsround(cpu_env
, cpu_dest
, cpu_src
);
5120 case 0x44: /* fdmove */
5121 gen_helper_fdround(cpu_env
, cpu_dest
, cpu_src
);
5124 gen_helper_firound(cpu_env
, cpu_dest
, cpu_src
);
5127 gen_helper_fsinh(cpu_env
, cpu_dest
, cpu_src
);
5129 case 3: /* fintrz */
5130 gen_helper_fitrunc(cpu_env
, cpu_dest
, cpu_src
);
5133 gen_helper_fsqrt(cpu_env
, cpu_dest
, cpu_src
);
5135 case 0x41: /* fssqrt */
5136 gen_helper_fssqrt(cpu_env
, cpu_dest
, cpu_src
);
5138 case 0x45: /* fdsqrt */
5139 gen_helper_fdsqrt(cpu_env
, cpu_dest
, cpu_src
);
5141 case 0x06: /* flognp1 */
5142 gen_helper_flognp1(cpu_env
, cpu_dest
, cpu_src
);
5144 case 0x09: /* ftanh */
5145 gen_helper_ftanh(cpu_env
, cpu_dest
, cpu_src
);
5147 case 0x0a: /* fatan */
5148 gen_helper_fatan(cpu_env
, cpu_dest
, cpu_src
);
5150 case 0x0c: /* fasin */
5151 gen_helper_fasin(cpu_env
, cpu_dest
, cpu_src
);
5153 case 0x0d: /* fatanh */
5154 gen_helper_fatanh(cpu_env
, cpu_dest
, cpu_src
);
5156 case 0x0e: /* fsin */
5157 gen_helper_fsin(cpu_env
, cpu_dest
, cpu_src
);
5159 case 0x0f: /* ftan */
5160 gen_helper_ftan(cpu_env
, cpu_dest
, cpu_src
);
5162 case 0x10: /* fetox */
5163 gen_helper_fetox(cpu_env
, cpu_dest
, cpu_src
);
5165 case 0x11: /* ftwotox */
5166 gen_helper_ftwotox(cpu_env
, cpu_dest
, cpu_src
);
5168 case 0x12: /* ftentox */
5169 gen_helper_ftentox(cpu_env
, cpu_dest
, cpu_src
);
5171 case 0x14: /* flogn */
5172 gen_helper_flogn(cpu_env
, cpu_dest
, cpu_src
);
5174 case 0x15: /* flog10 */
5175 gen_helper_flog10(cpu_env
, cpu_dest
, cpu_src
);
5177 case 0x16: /* flog2 */
5178 gen_helper_flog2(cpu_env
, cpu_dest
, cpu_src
);
5180 case 0x18: /* fabs */
5181 gen_helper_fabs(cpu_env
, cpu_dest
, cpu_src
);
5183 case 0x58: /* fsabs */
5184 gen_helper_fsabs(cpu_env
, cpu_dest
, cpu_src
);
5186 case 0x5c: /* fdabs */
5187 gen_helper_fdabs(cpu_env
, cpu_dest
, cpu_src
);
5189 case 0x19: /* fcosh */
5190 gen_helper_fcosh(cpu_env
, cpu_dest
, cpu_src
);
5192 case 0x1a: /* fneg */
5193 gen_helper_fneg(cpu_env
, cpu_dest
, cpu_src
);
5195 case 0x5a: /* fsneg */
5196 gen_helper_fsneg(cpu_env
, cpu_dest
, cpu_src
);
5198 case 0x5e: /* fdneg */
5199 gen_helper_fdneg(cpu_env
, cpu_dest
, cpu_src
);
5201 case 0x1c: /* facos */
5202 gen_helper_facos(cpu_env
, cpu_dest
, cpu_src
);
5204 case 0x1d: /* fcos */
5205 gen_helper_fcos(cpu_env
, cpu_dest
, cpu_src
);
5207 case 0x1e: /* fgetexp */
5208 gen_helper_fgetexp(cpu_env
, cpu_dest
, cpu_src
);
5210 case 0x1f: /* fgetman */
5211 gen_helper_fgetman(cpu_env
, cpu_dest
, cpu_src
);
5213 case 0x20: /* fdiv */
5214 gen_helper_fdiv(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5216 case 0x60: /* fsdiv */
5217 gen_helper_fsdiv(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5219 case 0x64: /* fddiv */
5220 gen_helper_fddiv(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5222 case 0x21: /* fmod */
5223 gen_helper_fmod(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5225 case 0x22: /* fadd */
5226 gen_helper_fadd(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5228 case 0x62: /* fsadd */
5229 gen_helper_fsadd(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5231 case 0x66: /* fdadd */
5232 gen_helper_fdadd(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5234 case 0x23: /* fmul */
5235 gen_helper_fmul(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5237 case 0x63: /* fsmul */
5238 gen_helper_fsmul(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5240 case 0x67: /* fdmul */
5241 gen_helper_fdmul(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5243 case 0x24: /* fsgldiv */
5244 gen_helper_fsgldiv(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5246 case 0x25: /* frem */
5247 gen_helper_frem(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5249 case 0x26: /* fscale */
5250 gen_helper_fscale(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5252 case 0x27: /* fsglmul */
5253 gen_helper_fsglmul(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5255 case 0x28: /* fsub */
5256 gen_helper_fsub(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5258 case 0x68: /* fssub */
5259 gen_helper_fssub(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5261 case 0x6c: /* fdsub */
5262 gen_helper_fdsub(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
5264 case 0x30: case 0x31: case 0x32:
5265 case 0x33: case 0x34: case 0x35:
5266 case 0x36: case 0x37: {
5267 TCGv_ptr cpu_dest2
= gen_fp_ptr(REG(ext
, 0));
5268 gen_helper_fsincos(cpu_env
, cpu_dest
, cpu_dest2
, cpu_src
);
5269 tcg_temp_free_ptr(cpu_dest2
);
5272 case 0x38: /* fcmp */
5273 gen_helper_fcmp(cpu_env
, cpu_src
, cpu_dest
);
5275 case 0x3a: /* ftst */
5276 gen_helper_ftst(cpu_env
, cpu_src
);
5281 tcg_temp_free_ptr(cpu_src
);
5282 gen_helper_ftst(cpu_env
, cpu_dest
);
5283 tcg_temp_free_ptr(cpu_dest
);
5286 /* FIXME: Is this right for offset addressing modes? */
5288 disas_undef_fpu(env
, s
, insn
);
5291 static void gen_fcc_cond(DisasCompare
*c
, DisasContext
*s
, int cond
)
5296 c
->v2
= tcg_const_i32(0);
5298 /* TODO: Raise BSUN exception. */
5299 fpsr
= tcg_temp_new();
5300 gen_load_fcr(s
, fpsr
, M68K_FPSR
);
5303 case 16: /* Signaling False */
5305 c
->tcond
= TCG_COND_NEVER
;
5307 case 1: /* EQual Z */
5308 case 17: /* Signaling EQual Z */
5309 c
->v1
= tcg_temp_new();
5311 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_Z
);
5312 c
->tcond
= TCG_COND_NE
;
5314 case 2: /* Ordered Greater Than !(A || Z || N) */
5315 case 18: /* Greater Than !(A || Z || N) */
5316 c
->v1
= tcg_temp_new();
5318 tcg_gen_andi_i32(c
->v1
, fpsr
,
5319 FPSR_CC_A
| FPSR_CC_Z
| FPSR_CC_N
);
5320 c
->tcond
= TCG_COND_EQ
;
5322 case 3: /* Ordered Greater than or Equal Z || !(A || N) */
5323 case 19: /* Greater than or Equal Z || !(A || N) */
5324 c
->v1
= tcg_temp_new();
5326 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
);
5327 tcg_gen_shli_i32(c
->v1
, c
->v1
, ctz32(FPSR_CC_N
) - ctz32(FPSR_CC_A
));
5328 tcg_gen_andi_i32(fpsr
, fpsr
, FPSR_CC_Z
| FPSR_CC_N
);
5329 tcg_gen_or_i32(c
->v1
, c
->v1
, fpsr
);
5330 tcg_gen_xori_i32(c
->v1
, c
->v1
, FPSR_CC_N
);
5331 c
->tcond
= TCG_COND_NE
;
5333 case 4: /* Ordered Less Than !(!N || A || Z); */
5334 case 20: /* Less Than !(!N || A || Z); */
5335 c
->v1
= tcg_temp_new();
5337 tcg_gen_xori_i32(c
->v1
, fpsr
, FPSR_CC_N
);
5338 tcg_gen_andi_i32(c
->v1
, c
->v1
, FPSR_CC_N
| FPSR_CC_A
| FPSR_CC_Z
);
5339 c
->tcond
= TCG_COND_EQ
;
5341 case 5: /* Ordered Less than or Equal Z || (N && !A) */
5342 case 21: /* Less than or Equal Z || (N && !A) */
5343 c
->v1
= tcg_temp_new();
5345 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
);
5346 tcg_gen_shli_i32(c
->v1
, c
->v1
, ctz32(FPSR_CC_N
) - ctz32(FPSR_CC_A
));
5347 tcg_gen_andc_i32(c
->v1
, fpsr
, c
->v1
);
5348 tcg_gen_andi_i32(c
->v1
, c
->v1
, FPSR_CC_Z
| FPSR_CC_N
);
5349 c
->tcond
= TCG_COND_NE
;
5351 case 6: /* Ordered Greater or Less than !(A || Z) */
5352 case 22: /* Greater or Less than !(A || Z) */
5353 c
->v1
= tcg_temp_new();
5355 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
| FPSR_CC_Z
);
5356 c
->tcond
= TCG_COND_EQ
;
5358 case 7: /* Ordered !A */
5359 case 23: /* Greater, Less or Equal !A */
5360 c
->v1
= tcg_temp_new();
5362 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
);
5363 c
->tcond
= TCG_COND_EQ
;
5365 case 8: /* Unordered A */
5366 case 24: /* Not Greater, Less or Equal A */
5367 c
->v1
= tcg_temp_new();
5369 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
);
5370 c
->tcond
= TCG_COND_NE
;
5372 case 9: /* Unordered or Equal A || Z */
5373 case 25: /* Not Greater or Less then A || Z */
5374 c
->v1
= tcg_temp_new();
5376 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
| FPSR_CC_Z
);
5377 c
->tcond
= TCG_COND_NE
;
5379 case 10: /* Unordered or Greater Than A || !(N || Z)) */
5380 case 26: /* Not Less or Equal A || !(N || Z)) */
5381 c
->v1
= tcg_temp_new();
5383 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_Z
);
5384 tcg_gen_shli_i32(c
->v1
, c
->v1
, ctz32(FPSR_CC_N
) - ctz32(FPSR_CC_Z
));
5385 tcg_gen_andi_i32(fpsr
, fpsr
, FPSR_CC_A
| FPSR_CC_N
);
5386 tcg_gen_or_i32(c
->v1
, c
->v1
, fpsr
);
5387 tcg_gen_xori_i32(c
->v1
, c
->v1
, FPSR_CC_N
);
5388 c
->tcond
= TCG_COND_NE
;
5390 case 11: /* Unordered or Greater or Equal A || Z || !N */
5391 case 27: /* Not Less Than A || Z || !N */
5392 c
->v1
= tcg_temp_new();
5394 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
| FPSR_CC_Z
| FPSR_CC_N
);
5395 tcg_gen_xori_i32(c
->v1
, c
->v1
, FPSR_CC_N
);
5396 c
->tcond
= TCG_COND_NE
;
5398 case 12: /* Unordered or Less Than A || (N && !Z) */
5399 case 28: /* Not Greater than or Equal A || (N && !Z) */
5400 c
->v1
= tcg_temp_new();
5402 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_Z
);
5403 tcg_gen_shli_i32(c
->v1
, c
->v1
, ctz32(FPSR_CC_N
) - ctz32(FPSR_CC_Z
));
5404 tcg_gen_andc_i32(c
->v1
, fpsr
, c
->v1
);
5405 tcg_gen_andi_i32(c
->v1
, c
->v1
, FPSR_CC_A
| FPSR_CC_N
);
5406 c
->tcond
= TCG_COND_NE
;
5408 case 13: /* Unordered or Less or Equal A || Z || N */
5409 case 29: /* Not Greater Than A || Z || N */
5410 c
->v1
= tcg_temp_new();
5412 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
| FPSR_CC_Z
| FPSR_CC_N
);
5413 c
->tcond
= TCG_COND_NE
;
5415 case 14: /* Not Equal !Z */
5416 case 30: /* Signaling Not Equal !Z */
5417 c
->v1
= tcg_temp_new();
5419 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_Z
);
5420 c
->tcond
= TCG_COND_EQ
;
5423 case 31: /* Signaling True */
5425 c
->tcond
= TCG_COND_ALWAYS
;
5428 tcg_temp_free(fpsr
);
5431 static void gen_fjmpcc(DisasContext
*s
, int cond
, TCGLabel
*l1
)
5435 gen_fcc_cond(&c
, s
, cond
);
5437 tcg_gen_brcond_i32(c
.tcond
, c
.v1
, c
.v2
, l1
);
5448 offset
= (int16_t)read_im16(env
, s
);
5449 if (insn
& (1 << 6)) {
5450 offset
= (offset
<< 16) | read_im16(env
, s
);
5453 l1
= gen_new_label();
5455 gen_fjmpcc(s
, insn
& 0x3f, l1
);
5456 gen_jmp_tb(s
, 0, s
->pc
);
5458 gen_jmp_tb(s
, 1, base
+ offset
);
5468 ext
= read_im16(env
, s
);
5470 gen_fcc_cond(&c
, s
, cond
);
5472 tmp
= tcg_temp_new();
5473 tcg_gen_setcond_i32(c
.tcond
, tmp
, c
.v1
, c
.v2
);
5476 tcg_gen_neg_i32(tmp
, tmp
);
5477 DEST_EA(env
, insn
, OS_BYTE
, tmp
, NULL
);
5481 #if defined(CONFIG_SOFTMMU)
5482 DISAS_INSN(frestore
)
5487 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
5490 if (m68k_feature(s
->env
, M68K_FEATURE_M68040
)) {
5491 SRC_EA(env
, addr
, OS_LONG
, 0, NULL
);
5492 /* FIXME: check the state frame */
5494 disas_undef(env
, s
, insn
);
5501 gen_exception(s
, s
->base
.pc_next
, EXCP_PRIVILEGE
);
5505 if (m68k_feature(s
->env
, M68K_FEATURE_M68040
)) {
5506 /* always write IDLE */
5507 TCGv idle
= tcg_const_i32(0x41000000);
5508 DEST_EA(env
, insn
, OS_LONG
, idle
, NULL
);
5509 tcg_temp_free(idle
);
5511 disas_undef(env
, s
, insn
);
5516 static inline TCGv
gen_mac_extract_word(DisasContext
*s
, TCGv val
, int upper
)
5518 TCGv tmp
= tcg_temp_new();
5519 if (s
->env
->macsr
& MACSR_FI
) {
5521 tcg_gen_andi_i32(tmp
, val
, 0xffff0000);
5523 tcg_gen_shli_i32(tmp
, val
, 16);
5524 } else if (s
->env
->macsr
& MACSR_SU
) {
5526 tcg_gen_sari_i32(tmp
, val
, 16);
5528 tcg_gen_ext16s_i32(tmp
, val
);
5531 tcg_gen_shri_i32(tmp
, val
, 16);
5533 tcg_gen_ext16u_i32(tmp
, val
);
5538 static void gen_mac_clear_flags(void)
5540 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
,
5541 ~(MACSR_V
| MACSR_Z
| MACSR_N
| MACSR_EV
));
5557 s
->mactmp
= tcg_temp_new_i64();
5561 ext
= read_im16(env
, s
);
5563 acc
= ((insn
>> 7) & 1) | ((ext
>> 3) & 2);
5564 dual
= ((insn
& 0x30) != 0 && (ext
& 3) != 0);
5565 if (dual
&& !m68k_feature(s
->env
, M68K_FEATURE_CF_EMAC_B
)) {
5566 disas_undef(env
, s
, insn
);
5570 /* MAC with load. */
5571 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
5572 addr
= tcg_temp_new();
5573 tcg_gen_and_i32(addr
, tmp
, QREG_MAC_MASK
);
5575 * Load the value now to ensure correct exception behavior.
5576 * Perform writeback after reading the MAC inputs.
5578 loadval
= gen_load(s
, OS_LONG
, addr
, 0, IS_USER(s
));
5581 rx
= (ext
& 0x8000) ? AREG(ext
, 12) : DREG(insn
, 12);
5582 ry
= (ext
& 8) ? AREG(ext
, 0) : DREG(ext
, 0);
5584 loadval
= addr
= NULL_QREG
;
5585 rx
= (insn
& 0x40) ? AREG(insn
, 9) : DREG(insn
, 9);
5586 ry
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5589 gen_mac_clear_flags();
5592 /* Disabled because conditional branches clobber temporary vars. */
5593 if ((s
->env
->macsr
& MACSR_OMC
) != 0 && !dual
) {
5594 /* Skip the multiply if we know we will ignore it. */
5595 l1
= gen_new_label();
5596 tmp
= tcg_temp_new();
5597 tcg_gen_andi_i32(tmp
, QREG_MACSR
, 1 << (acc
+ 8));
5598 gen_op_jmp_nz32(tmp
, l1
);
5602 if ((ext
& 0x0800) == 0) {
5604 rx
= gen_mac_extract_word(s
, rx
, (ext
& 0x80) != 0);
5605 ry
= gen_mac_extract_word(s
, ry
, (ext
& 0x40) != 0);
5607 if (s
->env
->macsr
& MACSR_FI
) {
5608 gen_helper_macmulf(s
->mactmp
, cpu_env
, rx
, ry
);
5610 if (s
->env
->macsr
& MACSR_SU
)
5611 gen_helper_macmuls(s
->mactmp
, cpu_env
, rx
, ry
);
5613 gen_helper_macmulu(s
->mactmp
, cpu_env
, rx
, ry
);
5614 switch ((ext
>> 9) & 3) {
5616 tcg_gen_shli_i64(s
->mactmp
, s
->mactmp
, 1);
5619 tcg_gen_shri_i64(s
->mactmp
, s
->mactmp
, 1);
5625 /* Save the overflow flag from the multiply. */
5626 saved_flags
= tcg_temp_new();
5627 tcg_gen_mov_i32(saved_flags
, QREG_MACSR
);
5629 saved_flags
= NULL_QREG
;
5633 /* Disabled because conditional branches clobber temporary vars. */
5634 if ((s
->env
->macsr
& MACSR_OMC
) != 0 && dual
) {
5635 /* Skip the accumulate if the value is already saturated. */
5636 l1
= gen_new_label();
5637 tmp
= tcg_temp_new();
5638 gen_op_and32(tmp
, QREG_MACSR
, tcg_const_i32(MACSR_PAV0
<< acc
));
5639 gen_op_jmp_nz32(tmp
, l1
);
5644 tcg_gen_sub_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
5646 tcg_gen_add_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
5648 if (s
->env
->macsr
& MACSR_FI
)
5649 gen_helper_macsatf(cpu_env
, tcg_const_i32(acc
));
5650 else if (s
->env
->macsr
& MACSR_SU
)
5651 gen_helper_macsats(cpu_env
, tcg_const_i32(acc
));
5653 gen_helper_macsatu(cpu_env
, tcg_const_i32(acc
));
5656 /* Disabled because conditional branches clobber temporary vars. */
5662 /* Dual accumulate variant. */
5663 acc
= (ext
>> 2) & 3;
5664 /* Restore the overflow flag from the multiplier. */
5665 tcg_gen_mov_i32(QREG_MACSR
, saved_flags
);
5667 /* Disabled because conditional branches clobber temporary vars. */
5668 if ((s
->env
->macsr
& MACSR_OMC
) != 0) {
5669 /* Skip the accumulate if the value is already saturated. */
5670 l1
= gen_new_label();
5671 tmp
= tcg_temp_new();
5672 gen_op_and32(tmp
, QREG_MACSR
, tcg_const_i32(MACSR_PAV0
<< acc
));
5673 gen_op_jmp_nz32(tmp
, l1
);
5677 tcg_gen_sub_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
5679 tcg_gen_add_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
5680 if (s
->env
->macsr
& MACSR_FI
)
5681 gen_helper_macsatf(cpu_env
, tcg_const_i32(acc
));
5682 else if (s
->env
->macsr
& MACSR_SU
)
5683 gen_helper_macsats(cpu_env
, tcg_const_i32(acc
));
5685 gen_helper_macsatu(cpu_env
, tcg_const_i32(acc
));
5687 /* Disabled because conditional branches clobber temporary vars. */
5692 gen_helper_mac_set_flags(cpu_env
, tcg_const_i32(acc
));
5696 rw
= (insn
& 0x40) ? AREG(insn
, 9) : DREG(insn
, 9);
5697 tcg_gen_mov_i32(rw
, loadval
);
5699 * FIXME: Should address writeback happen with the masked or
5702 switch ((insn
>> 3) & 7) {
5703 case 3: /* Post-increment. */
5704 tcg_gen_addi_i32(AREG(insn
, 0), addr
, 4);
5706 case 4: /* Pre-decrement. */
5707 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
5709 tcg_temp_free(loadval
);
5713 DISAS_INSN(from_mac
)
5719 rx
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5720 accnum
= (insn
>> 9) & 3;
5721 acc
= MACREG(accnum
);
5722 if (s
->env
->macsr
& MACSR_FI
) {
5723 gen_helper_get_macf(rx
, cpu_env
, acc
);
5724 } else if ((s
->env
->macsr
& MACSR_OMC
) == 0) {
5725 tcg_gen_extrl_i64_i32(rx
, acc
);
5726 } else if (s
->env
->macsr
& MACSR_SU
) {
5727 gen_helper_get_macs(rx
, acc
);
5729 gen_helper_get_macu(rx
, acc
);
5732 tcg_gen_movi_i64(acc
, 0);
5733 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
, ~(MACSR_PAV0
<< accnum
));
5737 DISAS_INSN(move_mac
)
5739 /* FIXME: This can be done without a helper. */
5743 dest
= tcg_const_i32((insn
>> 9) & 3);
5744 gen_helper_mac_move(cpu_env
, dest
, tcg_const_i32(src
));
5745 gen_mac_clear_flags();
5746 gen_helper_mac_set_flags(cpu_env
, dest
);
5749 DISAS_INSN(from_macsr
)
5753 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5754 tcg_gen_mov_i32(reg
, QREG_MACSR
);
5757 DISAS_INSN(from_mask
)
5760 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5761 tcg_gen_mov_i32(reg
, QREG_MAC_MASK
);
5764 DISAS_INSN(from_mext
)
5768 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5769 acc
= tcg_const_i32((insn
& 0x400) ? 2 : 0);
5770 if (s
->env
->macsr
& MACSR_FI
)
5771 gen_helper_get_mac_extf(reg
, cpu_env
, acc
);
5773 gen_helper_get_mac_exti(reg
, cpu_env
, acc
);
5776 DISAS_INSN(macsr_to_ccr
)
5778 TCGv tmp
= tcg_temp_new();
5779 tcg_gen_andi_i32(tmp
, QREG_MACSR
, 0xf);
5780 gen_helper_set_sr(cpu_env
, tmp
);
5782 set_cc_op(s
, CC_OP_FLAGS
);
5790 accnum
= (insn
>> 9) & 3;
5791 acc
= MACREG(accnum
);
5792 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
5793 if (s
->env
->macsr
& MACSR_FI
) {
5794 tcg_gen_ext_i32_i64(acc
, val
);
5795 tcg_gen_shli_i64(acc
, acc
, 8);
5796 } else if (s
->env
->macsr
& MACSR_SU
) {
5797 tcg_gen_ext_i32_i64(acc
, val
);
5799 tcg_gen_extu_i32_i64(acc
, val
);
5801 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
, ~(MACSR_PAV0
<< accnum
));
5802 gen_mac_clear_flags();
5803 gen_helper_mac_set_flags(cpu_env
, tcg_const_i32(accnum
));
5806 DISAS_INSN(to_macsr
)
5809 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
5810 gen_helper_set_macsr(cpu_env
, val
);
5817 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
5818 tcg_gen_ori_i32(QREG_MAC_MASK
, val
, 0xffff0000);
5825 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
5826 acc
= tcg_const_i32((insn
& 0x400) ? 2 : 0);
5827 if (s
->env
->macsr
& MACSR_FI
)
5828 gen_helper_set_mac_extf(cpu_env
, val
, acc
);
5829 else if (s
->env
->macsr
& MACSR_SU
)
5830 gen_helper_set_mac_exts(cpu_env
, val
, acc
);
5832 gen_helper_set_mac_extu(cpu_env
, val
, acc
);
5835 static disas_proc opcode_table
[65536];
5838 register_opcode (disas_proc proc
, uint16_t opcode
, uint16_t mask
)
5844 /* Sanity check. All set bits must be included in the mask. */
5845 if (opcode
& ~mask
) {
5847 "qemu internal error: bogus opcode definition %04x/%04x\n",
5852 * This could probably be cleverer. For now just optimize the case where
5853 * the top bits are known.
5855 /* Find the first zero bit in the mask. */
5857 while ((i
& mask
) != 0)
5859 /* Iterate over all combinations of this and lower bits. */
5864 from
= opcode
& ~(i
- 1);
5866 for (i
= from
; i
< to
; i
++) {
5867 if ((i
& mask
) == opcode
)
5868 opcode_table
[i
] = proc
;
5873 * Register m68k opcode handlers. Order is important.
5874 * Later insn override earlier ones.
5876 void register_m68k_insns (CPUM68KState
*env
)
5879 * Build the opcode table only once to avoid
5880 * multithreading issues.
5882 if (opcode_table
[0] != NULL
) {
5887 * use BASE() for instruction available
5888 * for CF_ISA_A and M68000.
5890 #define BASE(name, opcode, mask) \
5891 register_opcode(disas_##name, 0x##opcode, 0x##mask)
5892 #define INSN(name, opcode, mask, feature) do { \
5893 if (m68k_feature(env, M68K_FEATURE_##feature)) \
5894 BASE(name, opcode, mask); \
5896 BASE(undef
, 0000, 0000);
5897 INSN(arith_im
, 0080, fff8
, CF_ISA_A
);
5898 INSN(arith_im
, 0000, ff00
, M68000
);
5899 INSN(chk2
, 00c0
, f9c0
, CHK2
);
5900 INSN(bitrev
, 00c0
, fff8
, CF_ISA_APLUSC
);
5901 BASE(bitop_reg
, 0100, f1c0
);
5902 BASE(bitop_reg
, 0140, f1c0
);
5903 BASE(bitop_reg
, 0180, f1c0
);
5904 BASE(bitop_reg
, 01c0
, f1c0
);
5905 INSN(movep
, 0108, f138
, MOVEP
);
5906 INSN(arith_im
, 0280, fff8
, CF_ISA_A
);
5907 INSN(arith_im
, 0200, ff00
, M68000
);
5908 INSN(undef
, 02c0
, ffc0
, M68000
);
5909 INSN(byterev
, 02c0
, fff8
, CF_ISA_APLUSC
);
5910 INSN(arith_im
, 0480, fff8
, CF_ISA_A
);
5911 INSN(arith_im
, 0400, ff00
, M68000
);
5912 INSN(undef
, 04c0
, ffc0
, M68000
);
5913 INSN(arith_im
, 0600, ff00
, M68000
);
5914 INSN(undef
, 06c0
, ffc0
, M68000
);
5915 INSN(ff1
, 04c0
, fff8
, CF_ISA_APLUSC
);
5916 INSN(arith_im
, 0680, fff8
, CF_ISA_A
);
5917 INSN(arith_im
, 0c00
, ff38
, CF_ISA_A
);
5918 INSN(arith_im
, 0c00
, ff00
, M68000
);
5919 BASE(bitop_im
, 0800, ffc0
);
5920 BASE(bitop_im
, 0840, ffc0
);
5921 BASE(bitop_im
, 0880, ffc0
);
5922 BASE(bitop_im
, 08c0
, ffc0
);
5923 INSN(arith_im
, 0a80
, fff8
, CF_ISA_A
);
5924 INSN(arith_im
, 0a00
, ff00
, M68000
);
5925 #if defined(CONFIG_SOFTMMU)
5926 INSN(moves
, 0e00
, ff00
, M68000
);
5928 INSN(cas
, 0ac0
, ffc0
, CAS
);
5929 INSN(cas
, 0cc0
, ffc0
, CAS
);
5930 INSN(cas
, 0ec0
, ffc0
, CAS
);
5931 INSN(cas2w
, 0cfc
, ffff
, CAS
);
5932 INSN(cas2l
, 0efc
, ffff
, CAS
);
5933 BASE(move
, 1000, f000
);
5934 BASE(move
, 2000, f000
);
5935 BASE(move
, 3000, f000
);
5936 INSN(chk
, 4000, f040
, M68000
);
5937 INSN(strldsr
, 40e7
, ffff
, CF_ISA_APLUSC
);
5938 INSN(negx
, 4080, fff8
, CF_ISA_A
);
5939 INSN(negx
, 4000, ff00
, M68000
);
5940 INSN(undef
, 40c0
, ffc0
, M68000
);
5941 INSN(move_from_sr
, 40c0
, fff8
, CF_ISA_A
);
5942 INSN(move_from_sr
, 40c0
, ffc0
, M68000
);
5943 BASE(lea
, 41c0
, f1c0
);
5944 BASE(clr
, 4200, ff00
);
5945 BASE(undef
, 42c0
, ffc0
);
5946 INSN(move_from_ccr
, 42c0
, fff8
, CF_ISA_A
);
5947 INSN(move_from_ccr
, 42c0
, ffc0
, M68000
);
5948 INSN(neg
, 4480, fff8
, CF_ISA_A
);
5949 INSN(neg
, 4400, ff00
, M68000
);
5950 INSN(undef
, 44c0
, ffc0
, M68000
);
5951 BASE(move_to_ccr
, 44c0
, ffc0
);
5952 INSN(not, 4680, fff8
, CF_ISA_A
);
5953 INSN(not, 4600, ff00
, M68000
);
5954 #if defined(CONFIG_SOFTMMU)
5955 BASE(move_to_sr
, 46c0
, ffc0
);
5957 INSN(nbcd
, 4800, ffc0
, M68000
);
5958 INSN(linkl
, 4808, fff8
, M68000
);
5959 BASE(pea
, 4840, ffc0
);
5960 BASE(swap
, 4840, fff8
);
5961 INSN(bkpt
, 4848, fff8
, BKPT
);
5962 INSN(movem
, 48d0
, fbf8
, CF_ISA_A
);
5963 INSN(movem
, 48e8
, fbf8
, CF_ISA_A
);
5964 INSN(movem
, 4880, fb80
, M68000
);
5965 BASE(ext
, 4880, fff8
);
5966 BASE(ext
, 48c0
, fff8
);
5967 BASE(ext
, 49c0
, fff8
);
5968 BASE(tst
, 4a00
, ff00
);
5969 INSN(tas
, 4ac0
, ffc0
, CF_ISA_B
);
5970 INSN(tas
, 4ac0
, ffc0
, M68000
);
5971 #if defined(CONFIG_SOFTMMU)
5972 INSN(halt
, 4ac8
, ffff
, CF_ISA_A
);
5974 INSN(pulse
, 4acc
, ffff
, CF_ISA_A
);
5975 BASE(illegal
, 4afc
, ffff
);
5976 INSN(mull
, 4c00
, ffc0
, CF_ISA_A
);
5977 INSN(mull
, 4c00
, ffc0
, LONG_MULDIV
);
5978 INSN(divl
, 4c40
, ffc0
, CF_ISA_A
);
5979 INSN(divl
, 4c40
, ffc0
, LONG_MULDIV
);
5980 INSN(sats
, 4c80
, fff8
, CF_ISA_B
);
5981 BASE(trap
, 4e40
, fff0
);
5982 BASE(link
, 4e50
, fff8
);
5983 BASE(unlk
, 4e58
, fff8
);
5984 #if defined(CONFIG_SOFTMMU)
5985 INSN(move_to_usp
, 4e60
, fff8
, USP
);
5986 INSN(move_from_usp
, 4e68
, fff8
, USP
);
5987 INSN(reset
, 4e70
, ffff
, M68000
);
5988 BASE(stop
, 4e72
, ffff
);
5989 BASE(rte
, 4e73
, ffff
);
5990 INSN(cf_movec
, 4e7b
, ffff
, CF_ISA_A
);
5991 INSN(m68k_movec
, 4e7a
, fffe
, M68000
);
5993 BASE(nop
, 4e71
, ffff
);
5994 INSN(rtd
, 4e74
, ffff
, RTD
);
5995 BASE(rts
, 4e75
, ffff
);
5996 BASE(jump
, 4e80
, ffc0
);
5997 BASE(jump
, 4ec0
, ffc0
);
5998 INSN(addsubq
, 5000, f080
, M68000
);
5999 BASE(addsubq
, 5080, f0c0
);
6000 INSN(scc
, 50c0
, f0f8
, CF_ISA_A
); /* Scc.B Dx */
6001 INSN(scc
, 50c0
, f0c0
, M68000
); /* Scc.B <EA> */
6002 INSN(dbcc
, 50c8
, f0f8
, M68000
);
6003 INSN(tpf
, 51f8
, fff8
, CF_ISA_A
);
6005 /* Branch instructions. */
6006 BASE(branch
, 6000, f000
);
6007 /* Disable long branch instructions, then add back the ones we want. */
6008 BASE(undef
, 60ff
, f0ff
); /* All long branches. */
6009 INSN(branch
, 60ff
, f0ff
, CF_ISA_B
);
6010 INSN(undef
, 60ff
, ffff
, CF_ISA_B
); /* bra.l */
6011 INSN(branch
, 60ff
, ffff
, BRAL
);
6012 INSN(branch
, 60ff
, f0ff
, BCCL
);
6014 BASE(moveq
, 7000, f100
);
6015 INSN(mvzs
, 7100, f100
, CF_ISA_B
);
6016 BASE(or, 8000, f000
);
6017 BASE(divw
, 80c0
, f0c0
);
6018 INSN(sbcd_reg
, 8100, f1f8
, M68000
);
6019 INSN(sbcd_mem
, 8108, f1f8
, M68000
);
6020 BASE(addsub
, 9000, f000
);
6021 INSN(undef
, 90c0
, f0c0
, CF_ISA_A
);
6022 INSN(subx_reg
, 9180, f1f8
, CF_ISA_A
);
6023 INSN(subx_reg
, 9100, f138
, M68000
);
6024 INSN(subx_mem
, 9108, f138
, M68000
);
6025 INSN(suba
, 91c0
, f1c0
, CF_ISA_A
);
6026 INSN(suba
, 90c0
, f0c0
, M68000
);
6028 BASE(undef_mac
, a000
, f000
);
6029 INSN(mac
, a000
, f100
, CF_EMAC
);
6030 INSN(from_mac
, a180
, f9b0
, CF_EMAC
);
6031 INSN(move_mac
, a110
, f9fc
, CF_EMAC
);
6032 INSN(from_macsr
,a980
, f9f0
, CF_EMAC
);
6033 INSN(from_mask
, ad80
, fff0
, CF_EMAC
);
6034 INSN(from_mext
, ab80
, fbf0
, CF_EMAC
);
6035 INSN(macsr_to_ccr
, a9c0
, ffff
, CF_EMAC
);
6036 INSN(to_mac
, a100
, f9c0
, CF_EMAC
);
6037 INSN(to_macsr
, a900
, ffc0
, CF_EMAC
);
6038 INSN(to_mext
, ab00
, fbc0
, CF_EMAC
);
6039 INSN(to_mask
, ad00
, ffc0
, CF_EMAC
);
6041 INSN(mov3q
, a140
, f1c0
, CF_ISA_B
);
6042 INSN(cmp
, b000
, f1c0
, CF_ISA_B
); /* cmp.b */
6043 INSN(cmp
, b040
, f1c0
, CF_ISA_B
); /* cmp.w */
6044 INSN(cmpa
, b0c0
, f1c0
, CF_ISA_B
); /* cmpa.w */
6045 INSN(cmp
, b080
, f1c0
, CF_ISA_A
);
6046 INSN(cmpa
, b1c0
, f1c0
, CF_ISA_A
);
6047 INSN(cmp
, b000
, f100
, M68000
);
6048 INSN(eor
, b100
, f100
, M68000
);
6049 INSN(cmpm
, b108
, f138
, M68000
);
6050 INSN(cmpa
, b0c0
, f0c0
, M68000
);
6051 INSN(eor
, b180
, f1c0
, CF_ISA_A
);
6052 BASE(and, c000
, f000
);
6053 INSN(exg_dd
, c140
, f1f8
, M68000
);
6054 INSN(exg_aa
, c148
, f1f8
, M68000
);
6055 INSN(exg_da
, c188
, f1f8
, M68000
);
6056 BASE(mulw
, c0c0
, f0c0
);
6057 INSN(abcd_reg
, c100
, f1f8
, M68000
);
6058 INSN(abcd_mem
, c108
, f1f8
, M68000
);
6059 BASE(addsub
, d000
, f000
);
6060 INSN(undef
, d0c0
, f0c0
, CF_ISA_A
);
6061 INSN(addx_reg
, d180
, f1f8
, CF_ISA_A
);
6062 INSN(addx_reg
, d100
, f138
, M68000
);
6063 INSN(addx_mem
, d108
, f138
, M68000
);
6064 INSN(adda
, d1c0
, f1c0
, CF_ISA_A
);
6065 INSN(adda
, d0c0
, f0c0
, M68000
);
6066 INSN(shift_im
, e080
, f0f0
, CF_ISA_A
);
6067 INSN(shift_reg
, e0a0
, f0f0
, CF_ISA_A
);
6068 INSN(shift8_im
, e000
, f0f0
, M68000
);
6069 INSN(shift16_im
, e040
, f0f0
, M68000
);
6070 INSN(shift_im
, e080
, f0f0
, M68000
);
6071 INSN(shift8_reg
, e020
, f0f0
, M68000
);
6072 INSN(shift16_reg
, e060
, f0f0
, M68000
);
6073 INSN(shift_reg
, e0a0
, f0f0
, M68000
);
6074 INSN(shift_mem
, e0c0
, fcc0
, M68000
);
6075 INSN(rotate_im
, e090
, f0f0
, M68000
);
6076 INSN(rotate8_im
, e010
, f0f0
, M68000
);
6077 INSN(rotate16_im
, e050
, f0f0
, M68000
);
6078 INSN(rotate_reg
, e0b0
, f0f0
, M68000
);
6079 INSN(rotate8_reg
, e030
, f0f0
, M68000
);
6080 INSN(rotate16_reg
, e070
, f0f0
, M68000
);
6081 INSN(rotate_mem
, e4c0
, fcc0
, M68000
);
6082 INSN(bfext_mem
, e9c0
, fdc0
, BITFIELD
); /* bfextu & bfexts */
6083 INSN(bfext_reg
, e9c0
, fdf8
, BITFIELD
);
6084 INSN(bfins_mem
, efc0
, ffc0
, BITFIELD
);
6085 INSN(bfins_reg
, efc0
, fff8
, BITFIELD
);
6086 INSN(bfop_mem
, eac0
, ffc0
, BITFIELD
); /* bfchg */
6087 INSN(bfop_reg
, eac0
, fff8
, BITFIELD
); /* bfchg */
6088 INSN(bfop_mem
, ecc0
, ffc0
, BITFIELD
); /* bfclr */
6089 INSN(bfop_reg
, ecc0
, fff8
, BITFIELD
); /* bfclr */
6090 INSN(bfop_mem
, edc0
, ffc0
, BITFIELD
); /* bfffo */
6091 INSN(bfop_reg
, edc0
, fff8
, BITFIELD
); /* bfffo */
6092 INSN(bfop_mem
, eec0
, ffc0
, BITFIELD
); /* bfset */
6093 INSN(bfop_reg
, eec0
, fff8
, BITFIELD
); /* bfset */
6094 INSN(bfop_mem
, e8c0
, ffc0
, BITFIELD
); /* bftst */
6095 INSN(bfop_reg
, e8c0
, fff8
, BITFIELD
); /* bftst */
6096 BASE(undef_fpu
, f000
, f000
);
6097 INSN(fpu
, f200
, ffc0
, CF_FPU
);
6098 INSN(fbcc
, f280
, ffc0
, CF_FPU
);
6099 INSN(fpu
, f200
, ffc0
, FPU
);
6100 INSN(fscc
, f240
, ffc0
, FPU
);
6101 INSN(fbcc
, f280
, ff80
, FPU
);
6102 #if defined(CONFIG_SOFTMMU)
6103 INSN(frestore
, f340
, ffc0
, CF_FPU
);
6104 INSN(fsave
, f300
, ffc0
, CF_FPU
);
6105 INSN(frestore
, f340
, ffc0
, FPU
);
6106 INSN(fsave
, f300
, ffc0
, FPU
);
6107 INSN(intouch
, f340
, ffc0
, CF_ISA_A
);
6108 INSN(cpushl
, f428
, ff38
, CF_ISA_A
);
6109 INSN(cpush
, f420
, ff20
, M68040
);
6110 INSN(cinv
, f400
, ff20
, M68040
);
6111 INSN(pflush
, f500
, ffe0
, M68040
);
6112 INSN(ptest
, f548
, ffd8
, M68040
);
6113 INSN(wddata
, fb00
, ff00
, CF_ISA_A
);
6114 INSN(wdebug
, fbc0
, ffc0
, CF_ISA_A
);
6116 INSN(move16_mem
, f600
, ffe0
, M68040
);
6117 INSN(move16_reg
, f620
, fff8
, M68040
);
6121 static void m68k_tr_init_disas_context(DisasContextBase
*dcbase
, CPUState
*cpu
)
6123 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
6124 CPUM68KState
*env
= cpu
->env_ptr
;
6127 dc
->pc
= dc
->base
.pc_first
;
6128 dc
->cc_op
= CC_OP_DYNAMIC
;
6129 dc
->cc_op_synced
= 1;
6131 dc
->writeback_mask
= 0;
6132 init_release_array(dc
);
6135 static void m68k_tr_tb_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
6139 static void m68k_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
6141 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
6142 tcg_gen_insn_start(dc
->base
.pc_next
, dc
->cc_op
);
6145 static bool m68k_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
6146 const CPUBreakpoint
*bp
)
6148 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
6150 gen_exception(dc
, dc
->base
.pc_next
, EXCP_DEBUG
);
6152 * The address covered by the breakpoint must be included in
6153 * [tb->pc, tb->pc + tb->size) in order to for it to be
6154 * properly cleared -- thus we increment the PC here so that
6155 * the logic setting tb->size below does the right thing.
6157 dc
->base
.pc_next
+= 2;
6162 static void m68k_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
6164 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
6165 CPUM68KState
*env
= cpu
->env_ptr
;
6166 uint16_t insn
= read_im16(env
, dc
);
6168 opcode_table
[insn
](env
, dc
, insn
);
6172 dc
->base
.pc_next
= dc
->pc
;
6174 if (dc
->base
.is_jmp
== DISAS_NEXT
) {
6176 * Stop translation when the next insn might touch a new page.
6177 * This ensures that prefetch aborts at the right place.
6179 * We cannot determine the size of the next insn without
6180 * completely decoding it. However, the maximum insn size
6181 * is 32 bytes, so end if we do not have that much remaining.
6182 * This may produce several small TBs at the end of each page,
6183 * but they will all be linked with goto_tb.
6185 * ??? ColdFire maximum is 4 bytes; MC68000's maximum is also
6186 * smaller than MC68020's.
6188 target_ulong start_page_offset
6189 = dc
->pc
- (dc
->base
.pc_first
& TARGET_PAGE_MASK
);
6191 if (start_page_offset
>= TARGET_PAGE_SIZE
- 32) {
6192 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
6197 static void m68k_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
6199 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
6201 if (dc
->base
.is_jmp
== DISAS_NORETURN
) {
6204 if (dc
->base
.singlestep_enabled
) {
6205 gen_helper_raise_exception(cpu_env
, tcg_const_i32(EXCP_DEBUG
));
6209 switch (dc
->base
.is_jmp
) {
6210 case DISAS_TOO_MANY
:
6212 gen_jmp_tb(dc
, 0, dc
->pc
);
6215 /* We updated CC_OP and PC in gen_jmp/gen_jmp_im. */
6216 tcg_gen_lookup_and_goto_ptr();
6220 * We updated CC_OP and PC in gen_exit_tb, but also modified
6221 * other state that may require returning to the main loop.
6223 tcg_gen_exit_tb(NULL
, 0);
6226 g_assert_not_reached();
6230 static void m68k_tr_disas_log(const DisasContextBase
*dcbase
, CPUState
*cpu
)
6232 qemu_log("IN: %s\n", lookup_symbol(dcbase
->pc_first
));
6233 log_target_disas(cpu
, dcbase
->pc_first
, dcbase
->tb
->size
);
6236 static const TranslatorOps m68k_tr_ops
= {
6237 .init_disas_context
= m68k_tr_init_disas_context
,
6238 .tb_start
= m68k_tr_tb_start
,
6239 .insn_start
= m68k_tr_insn_start
,
6240 .breakpoint_check
= m68k_tr_breakpoint_check
,
6241 .translate_insn
= m68k_tr_translate_insn
,
6242 .tb_stop
= m68k_tr_tb_stop
,
6243 .disas_log
= m68k_tr_disas_log
,
6246 void gen_intermediate_code(CPUState
*cpu
, TranslationBlock
*tb
, int max_insns
)
6249 translator_loop(&m68k_tr_ops
, &dc
.base
, cpu
, tb
, max_insns
);
6252 static double floatx80_to_double(CPUM68KState
*env
, uint16_t high
, uint64_t low
)
6254 floatx80 a
= { .high
= high
, .low
= low
};
6260 u
.f64
= floatx80_to_float64(a
, &env
->fp_status
);
6264 void m68k_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
6266 M68kCPU
*cpu
= M68K_CPU(cs
);
6267 CPUM68KState
*env
= &cpu
->env
;
6270 for (i
= 0; i
< 8; i
++) {
6271 qemu_fprintf(f
, "D%d = %08x A%d = %08x "
6272 "F%d = %04x %016"PRIx64
" (%12g)\n",
6273 i
, env
->dregs
[i
], i
, env
->aregs
[i
],
6274 i
, env
->fregs
[i
].l
.upper
, env
->fregs
[i
].l
.lower
,
6275 floatx80_to_double(env
, env
->fregs
[i
].l
.upper
,
6276 env
->fregs
[i
].l
.lower
));
6278 qemu_fprintf(f
, "PC = %08x ", env
->pc
);
6279 sr
= env
->sr
| cpu_m68k_get_ccr(env
);
6280 qemu_fprintf(f
, "SR = %04x T:%x I:%x %c%c %c%c%c%c%c\n",
6281 sr
, (sr
& SR_T
) >> SR_T_SHIFT
, (sr
& SR_I
) >> SR_I_SHIFT
,
6282 (sr
& SR_S
) ? 'S' : 'U', (sr
& SR_M
) ? '%' : 'I',
6283 (sr
& CCF_X
) ? 'X' : '-', (sr
& CCF_N
) ? 'N' : '-',
6284 (sr
& CCF_Z
) ? 'Z' : '-', (sr
& CCF_V
) ? 'V' : '-',
6285 (sr
& CCF_C
) ? 'C' : '-');
6286 qemu_fprintf(f
, "FPSR = %08x %c%c%c%c ", env
->fpsr
,
6287 (env
->fpsr
& FPSR_CC_A
) ? 'A' : '-',
6288 (env
->fpsr
& FPSR_CC_I
) ? 'I' : '-',
6289 (env
->fpsr
& FPSR_CC_Z
) ? 'Z' : '-',
6290 (env
->fpsr
& FPSR_CC_N
) ? 'N' : '-');
6291 qemu_fprintf(f
, "\n "
6292 "FPCR = %04x ", env
->fpcr
);
6293 switch (env
->fpcr
& FPCR_PREC_MASK
) {
6295 qemu_fprintf(f
, "X ");
6298 qemu_fprintf(f
, "S ");
6301 qemu_fprintf(f
, "D ");
6304 switch (env
->fpcr
& FPCR_RND_MASK
) {
6306 qemu_fprintf(f
, "RN ");
6309 qemu_fprintf(f
, "RZ ");
6312 qemu_fprintf(f
, "RM ");
6315 qemu_fprintf(f
, "RP ");
6318 qemu_fprintf(f
, "\n");
6319 #ifdef CONFIG_SOFTMMU
6320 qemu_fprintf(f
, "%sA7(MSP) = %08x %sA7(USP) = %08x %sA7(ISP) = %08x\n",
6321 env
->current_sp
== M68K_SSP
? "->" : " ", env
->sp
[M68K_SSP
],
6322 env
->current_sp
== M68K_USP
? "->" : " ", env
->sp
[M68K_USP
],
6323 env
->current_sp
== M68K_ISP
? "->" : " ", env
->sp
[M68K_ISP
]);
6324 qemu_fprintf(f
, "VBR = 0x%08x\n", env
->vbr
);
6325 qemu_fprintf(f
, "SFC = %x DFC %x\n", env
->sfc
, env
->dfc
);
6326 qemu_fprintf(f
, "SSW %08x TCR %08x URP %08x SRP %08x\n",
6327 env
->mmu
.ssw
, env
->mmu
.tcr
, env
->mmu
.urp
, env
->mmu
.srp
);
6328 qemu_fprintf(f
, "DTTR0/1: %08x/%08x ITTR0/1: %08x/%08x\n",
6329 env
->mmu
.ttr
[M68K_DTTR0
], env
->mmu
.ttr
[M68K_DTTR1
],
6330 env
->mmu
.ttr
[M68K_ITTR0
], env
->mmu
.ttr
[M68K_ITTR1
]);
6331 qemu_fprintf(f
, "MMUSR %08x, fault at %08x\n",
6332 env
->mmu
.mmusr
, env
->mmu
.ar
);
6336 void restore_state_to_opc(CPUM68KState
*env
, TranslationBlock
*tb
,
6339 int cc_op
= data
[1];
6341 if (cc_op
!= CC_OP_DYNAMIC
) {