1 #include "qemu/osdep.h"
4 #include "exec/gdbstub.h"
5 #include "exec/helper-proto.h"
6 #include "qemu/host-utils.h"
7 #include "sysemu/arch_init.h"
8 #include "sysemu/sysemu.h"
9 #include "qemu/bitops.h"
10 #include "qemu/crc32c.h"
11 #include "exec/cpu_ldst.h"
13 #include <zlib.h> /* For crc32 */
14 #include "exec/semihost.h"
16 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
18 #ifndef CONFIG_USER_ONLY
19 static bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
20 int access_type
, ARMMMUIdx mmu_idx
,
21 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
22 target_ulong
*page_size
, uint32_t *fsr
,
25 static bool get_phys_addr_lpae(CPUARMState
*env
, target_ulong address
,
26 int access_type
, ARMMMUIdx mmu_idx
,
27 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
28 target_ulong
*page_size_ptr
, uint32_t *fsr
,
31 /* Definitions for the PMCCNTR and PMCR registers */
37 static int vfp_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
41 /* VFP data registers are always little-endian. */
42 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
44 stfq_le_p(buf
, env
->vfp
.regs
[reg
]);
47 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
48 /* Aliases for Q regs. */
51 stfq_le_p(buf
, env
->vfp
.regs
[(reg
- 32) * 2]);
52 stfq_le_p(buf
+ 8, env
->vfp
.regs
[(reg
- 32) * 2 + 1]);
56 switch (reg
- nregs
) {
57 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
58 case 1: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSCR
]); return 4;
59 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
64 static int vfp_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
68 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
70 env
->vfp
.regs
[reg
] = ldfq_le_p(buf
);
73 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
76 env
->vfp
.regs
[(reg
- 32) * 2] = ldfq_le_p(buf
);
77 env
->vfp
.regs
[(reg
- 32) * 2 + 1] = ldfq_le_p(buf
+ 8);
81 switch (reg
- nregs
) {
82 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
83 case 1: env
->vfp
.xregs
[ARM_VFP_FPSCR
] = ldl_p(buf
); return 4;
84 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
89 static int aarch64_fpu_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
93 /* 128 bit FP register */
94 stfq_le_p(buf
, env
->vfp
.regs
[reg
* 2]);
95 stfq_le_p(buf
+ 8, env
->vfp
.regs
[reg
* 2 + 1]);
99 stl_p(buf
, vfp_get_fpsr(env
));
103 stl_p(buf
, vfp_get_fpcr(env
));
110 static int aarch64_fpu_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
114 /* 128 bit FP register */
115 env
->vfp
.regs
[reg
* 2] = ldfq_le_p(buf
);
116 env
->vfp
.regs
[reg
* 2 + 1] = ldfq_le_p(buf
+ 8);
120 vfp_set_fpsr(env
, ldl_p(buf
));
124 vfp_set_fpcr(env
, ldl_p(buf
));
131 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
133 assert(ri
->fieldoffset
);
134 if (cpreg_field_is_64bit(ri
)) {
135 return CPREG_FIELD64(env
, ri
);
137 return CPREG_FIELD32(env
, ri
);
141 static void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
144 assert(ri
->fieldoffset
);
145 if (cpreg_field_is_64bit(ri
)) {
146 CPREG_FIELD64(env
, ri
) = value
;
148 CPREG_FIELD32(env
, ri
) = value
;
152 static void *raw_ptr(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
154 return (char *)env
+ ri
->fieldoffset
;
157 uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
159 /* Raw read of a coprocessor register (as needed for migration, etc). */
160 if (ri
->type
& ARM_CP_CONST
) {
161 return ri
->resetvalue
;
162 } else if (ri
->raw_readfn
) {
163 return ri
->raw_readfn(env
, ri
);
164 } else if (ri
->readfn
) {
165 return ri
->readfn(env
, ri
);
167 return raw_read(env
, ri
);
171 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
174 /* Raw write of a coprocessor register (as needed for migration, etc).
175 * Note that constant registers are treated as write-ignored; the
176 * caller should check for success by whether a readback gives the
179 if (ri
->type
& ARM_CP_CONST
) {
181 } else if (ri
->raw_writefn
) {
182 ri
->raw_writefn(env
, ri
, v
);
183 } else if (ri
->writefn
) {
184 ri
->writefn(env
, ri
, v
);
186 raw_write(env
, ri
, v
);
190 static bool raw_accessors_invalid(const ARMCPRegInfo
*ri
)
192 /* Return true if the regdef would cause an assertion if you called
193 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
194 * program bug for it not to have the NO_RAW flag).
195 * NB that returning false here doesn't necessarily mean that calling
196 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
197 * read/write access functions which are safe for raw use" from "has
198 * read/write access functions which have side effects but has forgotten
199 * to provide raw access functions".
200 * The tests here line up with the conditions in read/write_raw_cp_reg()
201 * and assertions in raw_read()/raw_write().
203 if ((ri
->type
& ARM_CP_CONST
) ||
205 ((ri
->raw_writefn
|| ri
->writefn
) && (ri
->raw_readfn
|| ri
->readfn
))) {
211 bool write_cpustate_to_list(ARMCPU
*cpu
)
213 /* Write the coprocessor state from cpu->env to the (index,value) list. */
217 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
218 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
219 const ARMCPRegInfo
*ri
;
221 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
226 if (ri
->type
& ARM_CP_NO_RAW
) {
229 cpu
->cpreg_values
[i
] = read_raw_cp_reg(&cpu
->env
, ri
);
234 bool write_list_to_cpustate(ARMCPU
*cpu
)
239 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
240 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
241 uint64_t v
= cpu
->cpreg_values
[i
];
242 const ARMCPRegInfo
*ri
;
244 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
249 if (ri
->type
& ARM_CP_NO_RAW
) {
252 /* Write value and confirm it reads back as written
253 * (to catch read-only registers and partially read-only
254 * registers where the incoming migration value doesn't match)
256 write_raw_cp_reg(&cpu
->env
, ri
, v
);
257 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
264 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
266 ARMCPU
*cpu
= opaque
;
268 const ARMCPRegInfo
*ri
;
270 regidx
= *(uint32_t *)key
;
271 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
273 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
274 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
275 /* The value array need not be initialized at this point */
276 cpu
->cpreg_array_len
++;
280 static void count_cpreg(gpointer key
, gpointer opaque
)
282 ARMCPU
*cpu
= opaque
;
284 const ARMCPRegInfo
*ri
;
286 regidx
= *(uint32_t *)key
;
287 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
289 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
290 cpu
->cpreg_array_len
++;
294 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
296 uint64_t aidx
= cpreg_to_kvm_id(*(uint32_t *)a
);
297 uint64_t bidx
= cpreg_to_kvm_id(*(uint32_t *)b
);
308 void init_cpreg_list(ARMCPU
*cpu
)
310 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
311 * Note that we require cpreg_tuples[] to be sorted by key ID.
316 keys
= g_hash_table_get_keys(cpu
->cp_regs
);
317 keys
= g_list_sort(keys
, cpreg_key_compare
);
319 cpu
->cpreg_array_len
= 0;
321 g_list_foreach(keys
, count_cpreg
, cpu
);
323 arraylen
= cpu
->cpreg_array_len
;
324 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
325 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
326 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
327 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
328 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
329 cpu
->cpreg_array_len
= 0;
331 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
333 assert(cpu
->cpreg_array_len
== arraylen
);
339 * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
340 * they are accessible when EL3 is using AArch64 regardless of EL3.NS.
342 * access_el3_aa32ns: Used to check AArch32 register views.
343 * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views.
345 static CPAccessResult
access_el3_aa32ns(CPUARMState
*env
,
346 const ARMCPRegInfo
*ri
)
348 bool secure
= arm_is_secure_below_el3(env
);
350 assert(!arm_el_is_aa64(env
, 3));
352 return CP_ACCESS_TRAP_UNCATEGORIZED
;
357 static CPAccessResult
access_el3_aa32ns_aa64any(CPUARMState
*env
,
358 const ARMCPRegInfo
*ri
)
360 if (!arm_el_is_aa64(env
, 3)) {
361 return access_el3_aa32ns(env
, ri
);
366 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
368 ARMCPU
*cpu
= arm_env_get_cpu(env
);
370 raw_write(env
, ri
, value
);
371 tlb_flush(CPU(cpu
), 1); /* Flush TLB as domain not tracked in TLB */
374 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
376 ARMCPU
*cpu
= arm_env_get_cpu(env
);
378 if (raw_read(env
, ri
) != value
) {
379 /* Unlike real hardware the qemu TLB uses virtual addresses,
380 * not modified virtual addresses, so this causes a TLB flush.
382 tlb_flush(CPU(cpu
), 1);
383 raw_write(env
, ri
, value
);
387 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
390 ARMCPU
*cpu
= arm_env_get_cpu(env
);
392 if (raw_read(env
, ri
) != value
&& !arm_feature(env
, ARM_FEATURE_MPU
)
393 && !extended_addresses_enabled(env
)) {
394 /* For VMSA (when not using the LPAE long descriptor page table
395 * format) this register includes the ASID, so do a TLB flush.
396 * For PMSA it is purely a process ID and no action is needed.
398 tlb_flush(CPU(cpu
), 1);
400 raw_write(env
, ri
, value
);
403 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
406 /* Invalidate all (TLBIALL) */
407 ARMCPU
*cpu
= arm_env_get_cpu(env
);
409 tlb_flush(CPU(cpu
), 1);
412 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
415 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
416 ARMCPU
*cpu
= arm_env_get_cpu(env
);
418 tlb_flush_page(CPU(cpu
), value
& TARGET_PAGE_MASK
);
421 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
424 /* Invalidate by ASID (TLBIASID) */
425 ARMCPU
*cpu
= arm_env_get_cpu(env
);
427 tlb_flush(CPU(cpu
), value
== 0);
430 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
433 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
434 ARMCPU
*cpu
= arm_env_get_cpu(env
);
436 tlb_flush_page(CPU(cpu
), value
& TARGET_PAGE_MASK
);
439 /* IS variants of TLB operations must affect all cores */
440 static void tlbiall_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
445 CPU_FOREACH(other_cs
) {
446 tlb_flush(other_cs
, 1);
450 static void tlbiasid_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
455 CPU_FOREACH(other_cs
) {
456 tlb_flush(other_cs
, value
== 0);
460 static void tlbimva_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
465 CPU_FOREACH(other_cs
) {
466 tlb_flush_page(other_cs
, value
& TARGET_PAGE_MASK
);
470 static void tlbimvaa_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
475 CPU_FOREACH(other_cs
) {
476 tlb_flush_page(other_cs
, value
& TARGET_PAGE_MASK
);
480 static const ARMCPRegInfo cp_reginfo
[] = {
481 /* Define the secure and non-secure FCSE identifier CP registers
482 * separately because there is no secure bank in V8 (no _EL3). This allows
483 * the secure register to be properly reset and migrated. There is also no
484 * v8 EL1 version of the register so the non-secure instance stands alone.
486 { .name
= "FCSEIDR(NS)",
487 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
488 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
489 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_ns
),
490 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
491 { .name
= "FCSEIDR(S)",
492 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
493 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
494 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_s
),
495 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
496 /* Define the secure and non-secure context identifier CP registers
497 * separately because there is no secure bank in V8 (no _EL3). This allows
498 * the secure register to be properly reset and migrated. In the
499 * non-secure case, the 32-bit register will have reset and migration
500 * disabled during registration as it is handled by the 64-bit instance.
502 { .name
= "CONTEXTIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
503 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
504 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
505 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[1]),
506 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
507 { .name
= "CONTEXTIDR(S)", .state
= ARM_CP_STATE_AA32
,
508 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
509 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
510 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_s
),
511 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
515 static const ARMCPRegInfo not_v8_cp_reginfo
[] = {
516 /* NB: Some of these registers exist in v8 but with more precise
517 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
519 /* MMU Domain access control / MPU write buffer control */
521 .cp
= 15, .opc1
= CP_ANY
, .crn
= 3, .crm
= CP_ANY
, .opc2
= CP_ANY
,
522 .access
= PL1_RW
, .resetvalue
= 0,
523 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
524 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
525 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
526 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
527 * For v6 and v5, these mappings are overly broad.
529 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 0,
530 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
531 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 1,
532 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
533 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 4,
534 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
535 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 8,
536 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
537 /* Cache maintenance ops; some of this space may be overridden later. */
538 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
539 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
540 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
544 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
545 /* Not all pre-v6 cores implemented this WFI, so this is slightly
548 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
549 .access
= PL1_W
, .type
= ARM_CP_WFI
},
553 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
554 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
555 * is UNPREDICTABLE; we choose to NOP as most implementations do).
557 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
558 .access
= PL1_W
, .type
= ARM_CP_WFI
},
559 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
560 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
561 * OMAPCP will override this space.
563 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
564 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
566 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
567 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
569 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
570 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
571 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
573 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
574 * implementing it as RAZ means the "debug architecture version" bits
575 * will read as a reserved value, which should cause Linux to not try
576 * to use the debug hardware.
578 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
579 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
580 /* MMU TLB control. Note that the wildcarding means we cover not just
581 * the unified TLB ops but also the dside/iside/inner-shareable variants.
583 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
584 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
585 .type
= ARM_CP_NO_RAW
},
586 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
587 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
588 .type
= ARM_CP_NO_RAW
},
589 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
590 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
591 .type
= ARM_CP_NO_RAW
},
592 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
593 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
594 .type
= ARM_CP_NO_RAW
},
595 { .name
= "PRRR", .cp
= 15, .crn
= 10, .crm
= 2,
596 .opc1
= 0, .opc2
= 0, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
597 { .name
= "NMRR", .cp
= 15, .crn
= 10, .crm
= 2,
598 .opc1
= 0, .opc2
= 1, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
602 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
607 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
608 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
609 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
610 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
611 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
613 if (arm_feature(env
, ARM_FEATURE_VFP
)) {
614 /* VFP coprocessor: cp10 & cp11 [23:20] */
615 mask
|= (1 << 31) | (1 << 30) | (0xf << 20);
617 if (!arm_feature(env
, ARM_FEATURE_NEON
)) {
618 /* ASEDIS [31] bit is RAO/WI */
622 /* VFPv3 and upwards with NEON implement 32 double precision
623 * registers (D0-D31).
625 if (!arm_feature(env
, ARM_FEATURE_NEON
) ||
626 !arm_feature(env
, ARM_FEATURE_VFP3
)) {
627 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
633 env
->cp15
.cpacr_el1
= value
;
636 static CPAccessResult
cpacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
638 if (arm_feature(env
, ARM_FEATURE_V8
)) {
639 /* Check if CPACR accesses are to be trapped to EL2 */
640 if (arm_current_el(env
) == 1 &&
641 (env
->cp15
.cptr_el
[2] & CPTR_TCPAC
) && !arm_is_secure(env
)) {
642 return CP_ACCESS_TRAP_EL2
;
643 /* Check if CPACR accesses are to be trapped to EL3 */
644 } else if (arm_current_el(env
) < 3 &&
645 (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
646 return CP_ACCESS_TRAP_EL3
;
653 static CPAccessResult
cptr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
655 /* Check if CPTR accesses are set to trap to EL3 */
656 if (arm_current_el(env
) == 2 && (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
657 return CP_ACCESS_TRAP_EL3
;
663 static const ARMCPRegInfo v6_cp_reginfo
[] = {
664 /* prefetch by MVA in v6, NOP in v7 */
665 { .name
= "MVA_prefetch",
666 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
667 .access
= PL1_W
, .type
= ARM_CP_NOP
},
668 /* We need to break the TB after ISB to execute self-modifying code
669 * correctly and also to take any pending interrupts immediately.
670 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
672 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
673 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
, .writefn
= arm_cp_write_ignore
},
674 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
675 .access
= PL0_W
, .type
= ARM_CP_NOP
},
676 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
677 .access
= PL0_W
, .type
= ARM_CP_NOP
},
678 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
680 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ifar_s
),
681 offsetof(CPUARMState
, cp15
.ifar_ns
) },
683 /* Watchpoint Fault Address Register : should actually only be present
684 * for 1136, 1176, 11MPCore.
686 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
687 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
688 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
689 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2, .accessfn
= cpacr_access
,
690 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.cpacr_el1
),
691 .resetvalue
= 0, .writefn
= cpacr_write
},
695 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
697 /* Performance monitor registers user accessibility is controlled
700 if (arm_current_el(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
701 return CP_ACCESS_TRAP
;
706 #ifndef CONFIG_USER_ONLY
708 static inline bool arm_ccnt_enabled(CPUARMState
*env
)
710 /* This does not support checking PMCCFILTR_EL0 register */
712 if (!(env
->cp15
.c9_pmcr
& PMCRE
)) {
719 void pmccntr_sync(CPUARMState
*env
)
723 temp_ticks
= muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
724 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
726 if (env
->cp15
.c9_pmcr
& PMCRD
) {
727 /* Increment once every 64 processor clock cycles */
731 if (arm_ccnt_enabled(env
)) {
732 env
->cp15
.c15_ccnt
= temp_ticks
- env
->cp15
.c15_ccnt
;
736 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
742 /* The counter has been reset */
743 env
->cp15
.c15_ccnt
= 0;
746 /* only the DP, X, D and E bits are writable */
747 env
->cp15
.c9_pmcr
&= ~0x39;
748 env
->cp15
.c9_pmcr
|= (value
& 0x39);
753 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
755 uint64_t total_ticks
;
757 if (!arm_ccnt_enabled(env
)) {
758 /* Counter is disabled, do not change value */
759 return env
->cp15
.c15_ccnt
;
762 total_ticks
= muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
763 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
765 if (env
->cp15
.c9_pmcr
& PMCRD
) {
766 /* Increment once every 64 processor clock cycles */
769 return total_ticks
- env
->cp15
.c15_ccnt
;
772 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
775 uint64_t total_ticks
;
777 if (!arm_ccnt_enabled(env
)) {
778 /* Counter is disabled, set the absolute value */
779 env
->cp15
.c15_ccnt
= value
;
783 total_ticks
= muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
784 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
786 if (env
->cp15
.c9_pmcr
& PMCRD
) {
787 /* Increment once every 64 processor clock cycles */
790 env
->cp15
.c15_ccnt
= total_ticks
- value
;
793 static void pmccntr_write32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
796 uint64_t cur_val
= pmccntr_read(env
, NULL
);
798 pmccntr_write(env
, ri
, deposit64(cur_val
, 0, 32, value
));
801 #else /* CONFIG_USER_ONLY */
803 void pmccntr_sync(CPUARMState
*env
)
809 static void pmccfiltr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
813 env
->cp15
.pmccfiltr_el0
= value
& 0x7E000000;
817 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
821 env
->cp15
.c9_pmcnten
|= value
;
824 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
828 env
->cp15
.c9_pmcnten
&= ~value
;
831 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
834 env
->cp15
.c9_pmovsr
&= ~value
;
837 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
840 env
->cp15
.c9_pmxevtyper
= value
& 0xff;
843 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
846 env
->cp15
.c9_pmuserenr
= value
& 1;
849 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
852 /* We have no event counters so only the C bit can be changed */
854 env
->cp15
.c9_pminten
|= value
;
857 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
861 env
->cp15
.c9_pminten
&= ~value
;
864 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
867 /* Note that even though the AArch64 view of this register has bits
868 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
869 * architectural requirements for bits which are RES0 only in some
870 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
871 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
873 raw_write(env
, ri
, value
& ~0x1FULL
);
876 static void scr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
878 /* We only mask off bits that are RES0 both for AArch64 and AArch32.
879 * For bits that vary between AArch32/64, code needs to check the
880 * current execution mode before directly using the feature bit.
882 uint32_t valid_mask
= SCR_AARCH64_MASK
| SCR_AARCH32_MASK
;
884 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
885 valid_mask
&= ~SCR_HCE
;
887 /* On ARMv7, SMD (or SCD as it is called in v7) is only
888 * supported if EL2 exists. The bit is UNK/SBZP when
889 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
890 * when EL2 is unavailable.
891 * On ARMv8, this bit is always available.
893 if (arm_feature(env
, ARM_FEATURE_V7
) &&
894 !arm_feature(env
, ARM_FEATURE_V8
)) {
895 valid_mask
&= ~SCR_SMD
;
899 /* Clear all-context RES0 bits. */
901 raw_write(env
, ri
, value
);
904 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
906 ARMCPU
*cpu
= arm_env_get_cpu(env
);
908 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
911 uint32_t index
= A32_BANKED_REG_GET(env
, csselr
,
912 ri
->secure
& ARM_CP_SECSTATE_S
);
914 return cpu
->ccsidr
[index
];
917 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
920 raw_write(env
, ri
, value
& 0xf);
923 static uint64_t isr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
925 CPUState
*cs
= ENV_GET_CPU(env
);
928 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
931 if (cs
->interrupt_request
& CPU_INTERRUPT_FIQ
) {
934 /* External aborts are not possible in QEMU so A bit is always clear */
938 static const ARMCPRegInfo v7_cp_reginfo
[] = {
939 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
940 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
941 .access
= PL1_W
, .type
= ARM_CP_NOP
},
942 /* Performance monitors are implementation defined in v7,
943 * but with an ARM recommended set of registers, which we
944 * follow (although we don't actually implement any counters)
946 * Performance registers fall into three categories:
947 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
948 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
949 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
950 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
951 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
953 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
954 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
955 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
956 .writefn
= pmcntenset_write
,
957 .accessfn
= pmreg_access
,
958 .raw_writefn
= raw_write
},
959 { .name
= "PMCNTENSET_EL0", .state
= ARM_CP_STATE_AA64
,
960 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 1,
961 .access
= PL0_RW
, .accessfn
= pmreg_access
,
962 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
), .resetvalue
= 0,
963 .writefn
= pmcntenset_write
, .raw_writefn
= raw_write
},
964 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
966 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
967 .accessfn
= pmreg_access
,
968 .writefn
= pmcntenclr_write
,
969 .type
= ARM_CP_ALIAS
},
970 { .name
= "PMCNTENCLR_EL0", .state
= ARM_CP_STATE_AA64
,
971 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 2,
972 .access
= PL0_RW
, .accessfn
= pmreg_access
,
973 .type
= ARM_CP_ALIAS
,
974 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
975 .writefn
= pmcntenclr_write
},
976 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
977 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
978 .accessfn
= pmreg_access
,
979 .writefn
= pmovsr_write
,
980 .raw_writefn
= raw_write
},
981 /* Unimplemented so WI. */
982 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
983 .access
= PL0_W
, .accessfn
= pmreg_access
, .type
= ARM_CP_NOP
},
984 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
985 * We choose to RAZ/WI.
987 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
988 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0,
989 .accessfn
= pmreg_access
},
990 #ifndef CONFIG_USER_ONLY
991 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
992 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_IO
,
993 .readfn
= pmccntr_read
, .writefn
= pmccntr_write32
,
994 .accessfn
= pmreg_access
},
995 { .name
= "PMCCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
996 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 0,
997 .access
= PL0_RW
, .accessfn
= pmreg_access
,
999 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
, },
1001 { .name
= "PMCCFILTR_EL0", .state
= ARM_CP_STATE_AA64
,
1002 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 15, .opc2
= 7,
1003 .writefn
= pmccfiltr_write
,
1004 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1006 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmccfiltr_el0
),
1008 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
1010 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmxevtyper
),
1011 .accessfn
= pmreg_access
, .writefn
= pmxevtyper_write
,
1012 .raw_writefn
= raw_write
},
1013 /* Unimplemented, RAZ/WI. */
1014 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
1015 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0,
1016 .accessfn
= pmreg_access
},
1017 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
1018 .access
= PL0_R
| PL1_RW
,
1019 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
1021 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
1022 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
1024 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
1026 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
1027 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
1028 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
1029 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
1030 .writefn
= pmintenclr_write
, },
1031 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
1032 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
1033 .access
= PL1_RW
, .writefn
= vbar_write
,
1034 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.vbar_s
),
1035 offsetof(CPUARMState
, cp15
.vbar_ns
) },
1037 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
1038 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
1039 .access
= PL1_R
, .readfn
= ccsidr_read
, .type
= ARM_CP_NO_RAW
},
1040 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
1041 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
1042 .access
= PL1_RW
, .writefn
= csselr_write
, .resetvalue
= 0,
1043 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.csselr_s
),
1044 offsetof(CPUARMState
, cp15
.csselr_ns
) } },
1045 /* Auxiliary ID register: this actually has an IMPDEF value but for now
1046 * just RAZ for all cores:
1048 { .name
= "AIDR", .state
= ARM_CP_STATE_BOTH
,
1049 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 7,
1050 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1051 /* Auxiliary fault status registers: these also are IMPDEF, and we
1052 * choose to RAZ/WI for all cores.
1054 { .name
= "AFSR0_EL1", .state
= ARM_CP_STATE_BOTH
,
1055 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 0,
1056 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1057 { .name
= "AFSR1_EL1", .state
= ARM_CP_STATE_BOTH
,
1058 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 1,
1059 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1060 /* MAIR can just read-as-written because we don't implement caches
1061 * and so don't need to care about memory attributes.
1063 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
1064 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
1065 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[1]),
1067 { .name
= "MAIR_EL3", .state
= ARM_CP_STATE_AA64
,
1068 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 2, .opc2
= 0,
1069 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[3]),
1071 /* For non-long-descriptor page tables these are PRRR and NMRR;
1072 * regardless they still act as reads-as-written for QEMU.
1074 /* MAIR0/1 are defined separately from their 64-bit counterpart which
1075 * allows them to assign the correct fieldoffset based on the endianness
1076 * handled in the field definitions.
1078 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
,
1079 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0, .access
= PL1_RW
,
1080 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair0_s
),
1081 offsetof(CPUARMState
, cp15
.mair0_ns
) },
1082 .resetfn
= arm_cp_reset_ignore
},
1083 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
,
1084 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1, .access
= PL1_RW
,
1085 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair1_s
),
1086 offsetof(CPUARMState
, cp15
.mair1_ns
) },
1087 .resetfn
= arm_cp_reset_ignore
},
1088 { .name
= "ISR_EL1", .state
= ARM_CP_STATE_BOTH
,
1089 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 0,
1090 .type
= ARM_CP_NO_RAW
, .access
= PL1_R
, .readfn
= isr_read
},
1091 /* 32 bit ITLB invalidates */
1092 { .name
= "ITLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 0,
1093 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
1094 { .name
= "ITLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
1095 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
1096 { .name
= "ITLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 2,
1097 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
1098 /* 32 bit DTLB invalidates */
1099 { .name
= "DTLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 0,
1100 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
1101 { .name
= "DTLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
1102 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
1103 { .name
= "DTLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 2,
1104 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
1105 /* 32 bit TLB invalidates */
1106 { .name
= "TLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
1107 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
1108 { .name
= "TLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
1109 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
1110 { .name
= "TLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
1111 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
1112 { .name
= "TLBIMVAA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
1113 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimvaa_write
},
1117 static const ARMCPRegInfo v7mp_cp_reginfo
[] = {
1118 /* 32 bit TLB invalidates, Inner Shareable */
1119 { .name
= "TLBIALLIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
1120 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_is_write
},
1121 { .name
= "TLBIMVAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
1122 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_is_write
},
1123 { .name
= "TLBIASIDIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
1124 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
1125 .writefn
= tlbiasid_is_write
},
1126 { .name
= "TLBIMVAAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
1127 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
1128 .writefn
= tlbimvaa_is_write
},
1132 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1139 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1141 if (arm_current_el(env
) == 0 && (env
->teecr
& 1)) {
1142 return CP_ACCESS_TRAP
;
1144 return CP_ACCESS_OK
;
1147 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
1148 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
1149 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
1151 .writefn
= teecr_write
},
1152 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
1153 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
1154 .accessfn
= teehbr_access
, .resetvalue
= 0 },
1158 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
1159 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
1160 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
1162 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[0]), .resetvalue
= 0 },
1163 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
1165 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrurw_s
),
1166 offsetoflow32(CPUARMState
, cp15
.tpidrurw_ns
) },
1167 .resetfn
= arm_cp_reset_ignore
},
1168 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
1169 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
1170 .access
= PL0_R
|PL1_W
,
1171 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el
[0]),
1173 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
1174 .access
= PL0_R
|PL1_W
,
1175 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidruro_s
),
1176 offsetoflow32(CPUARMState
, cp15
.tpidruro_ns
) },
1177 .resetfn
= arm_cp_reset_ignore
},
1178 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_AA64
,
1179 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
1181 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[1]), .resetvalue
= 0 },
1182 { .name
= "TPIDRPRW", .opc1
= 0, .cp
= 15, .crn
= 13, .crm
= 0, .opc2
= 4,
1184 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrprw_s
),
1185 offsetoflow32(CPUARMState
, cp15
.tpidrprw_ns
) },
1190 #ifndef CONFIG_USER_ONLY
1192 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1194 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
1195 if (arm_current_el(env
) == 0 && !extract32(env
->cp15
.c14_cntkctl
, 0, 2)) {
1196 return CP_ACCESS_TRAP
;
1198 return CP_ACCESS_OK
;
1201 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
)
1203 unsigned int cur_el
= arm_current_el(env
);
1204 bool secure
= arm_is_secure(env
);
1206 /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
1208 !extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
1209 return CP_ACCESS_TRAP
;
1212 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
1213 timeridx
== GTIMER_PHYS
&& !secure
&& cur_el
< 2 &&
1214 !extract32(env
->cp15
.cnthctl_el2
, 0, 1)) {
1215 return CP_ACCESS_TRAP_EL2
;
1217 return CP_ACCESS_OK
;
1220 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
)
1222 unsigned int cur_el
= arm_current_el(env
);
1223 bool secure
= arm_is_secure(env
);
1225 /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
1226 * EL0[PV]TEN is zero.
1229 !extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
1230 return CP_ACCESS_TRAP
;
1233 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
1234 timeridx
== GTIMER_PHYS
&& !secure
&& cur_el
< 2 &&
1235 !extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
1236 return CP_ACCESS_TRAP_EL2
;
1238 return CP_ACCESS_OK
;
1241 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
1242 const ARMCPRegInfo
*ri
)
1244 return gt_counter_access(env
, GTIMER_PHYS
);
1247 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
1248 const ARMCPRegInfo
*ri
)
1250 return gt_counter_access(env
, GTIMER_VIRT
);
1253 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1255 return gt_timer_access(env
, GTIMER_PHYS
);
1258 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1260 return gt_timer_access(env
, GTIMER_VIRT
);
1263 static CPAccessResult
gt_stimer_access(CPUARMState
*env
,
1264 const ARMCPRegInfo
*ri
)
1266 /* The AArch64 register view of the secure physical timer is
1267 * always accessible from EL3, and configurably accessible from
1270 switch (arm_current_el(env
)) {
1272 if (!arm_is_secure(env
)) {
1273 return CP_ACCESS_TRAP
;
1275 if (!(env
->cp15
.scr_el3
& SCR_ST
)) {
1276 return CP_ACCESS_TRAP_EL3
;
1278 return CP_ACCESS_OK
;
1281 return CP_ACCESS_TRAP
;
1283 return CP_ACCESS_OK
;
1285 g_assert_not_reached();
1289 static uint64_t gt_get_countervalue(CPUARMState
*env
)
1291 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / GTIMER_SCALE
;
1294 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
1296 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
1299 /* Timer enabled: calculate and set current ISTATUS, irq, and
1300 * reset timer to when ISTATUS next has to change
1302 uint64_t offset
= timeridx
== GTIMER_VIRT
?
1303 cpu
->env
.cp15
.cntvoff_el2
: 0;
1304 uint64_t count
= gt_get_countervalue(&cpu
->env
);
1305 /* Note that this must be unsigned 64 bit arithmetic: */
1306 int istatus
= count
- offset
>= gt
->cval
;
1309 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
1310 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
],
1311 (istatus
&& !(gt
->ctl
& 2)));
1313 /* Next transition is when count rolls back over to zero */
1314 nexttick
= UINT64_MAX
;
1316 /* Next transition is when we hit cval */
1317 nexttick
= gt
->cval
+ offset
;
1319 /* Note that the desired next expiry time might be beyond the
1320 * signed-64-bit range of a QEMUTimer -- in this case we just
1321 * set the timer for as far in the future as possible. When the
1322 * timer expires we will reset the timer for any remaining period.
1324 if (nexttick
> INT64_MAX
/ GTIMER_SCALE
) {
1325 nexttick
= INT64_MAX
/ GTIMER_SCALE
;
1327 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
1329 /* Timer disabled: ISTATUS and timer output always clear */
1331 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], 0);
1332 timer_del(cpu
->gt_timer
[timeridx
]);
1336 static void gt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1339 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1341 timer_del(cpu
->gt_timer
[timeridx
]);
1344 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1346 return gt_get_countervalue(env
);
1349 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1351 return gt_get_countervalue(env
) - env
->cp15
.cntvoff_el2
;
1354 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1358 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
1359 gt_recalc_timer(arm_env_get_cpu(env
), timeridx
);
1362 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1365 uint64_t offset
= timeridx
== GTIMER_VIRT
? env
->cp15
.cntvoff_el2
: 0;
1367 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
1368 (gt_get_countervalue(env
) - offset
));
1371 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1375 uint64_t offset
= timeridx
== GTIMER_VIRT
? env
->cp15
.cntvoff_el2
: 0;
1377 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) - offset
+
1378 sextract64(value
, 0, 32);
1379 gt_recalc_timer(arm_env_get_cpu(env
), timeridx
);
1382 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1386 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1387 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
1389 env
->cp15
.c14_timer
[timeridx
].ctl
= deposit64(oldval
, 0, 2, value
);
1390 if ((oldval
^ value
) & 1) {
1391 /* Enable toggled */
1392 gt_recalc_timer(cpu
, timeridx
);
1393 } else if ((oldval
^ value
) & 2) {
1394 /* IMASK toggled: don't need to recalculate,
1395 * just set the interrupt line based on ISTATUS
1397 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
],
1398 (oldval
& 4) && !(value
& 2));
1402 static void gt_phys_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1404 gt_timer_reset(env
, ri
, GTIMER_PHYS
);
1407 static void gt_phys_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1410 gt_cval_write(env
, ri
, GTIMER_PHYS
, value
);
1413 static uint64_t gt_phys_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1415 return gt_tval_read(env
, ri
, GTIMER_PHYS
);
1418 static void gt_phys_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1421 gt_tval_write(env
, ri
, GTIMER_PHYS
, value
);
1424 static void gt_phys_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1427 gt_ctl_write(env
, ri
, GTIMER_PHYS
, value
);
1430 static void gt_virt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1432 gt_timer_reset(env
, ri
, GTIMER_VIRT
);
1435 static void gt_virt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1438 gt_cval_write(env
, ri
, GTIMER_VIRT
, value
);
1441 static uint64_t gt_virt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1443 return gt_tval_read(env
, ri
, GTIMER_VIRT
);
1446 static void gt_virt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1449 gt_tval_write(env
, ri
, GTIMER_VIRT
, value
);
1452 static void gt_virt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1455 gt_ctl_write(env
, ri
, GTIMER_VIRT
, value
);
1458 static void gt_cntvoff_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1461 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1463 raw_write(env
, ri
, value
);
1464 gt_recalc_timer(cpu
, GTIMER_VIRT
);
1467 static void gt_hyp_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1469 gt_timer_reset(env
, ri
, GTIMER_HYP
);
1472 static void gt_hyp_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1475 gt_cval_write(env
, ri
, GTIMER_HYP
, value
);
1478 static uint64_t gt_hyp_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1480 return gt_tval_read(env
, ri
, GTIMER_HYP
);
1483 static void gt_hyp_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1486 gt_tval_write(env
, ri
, GTIMER_HYP
, value
);
1489 static void gt_hyp_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1492 gt_ctl_write(env
, ri
, GTIMER_HYP
, value
);
1495 static void gt_sec_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1497 gt_timer_reset(env
, ri
, GTIMER_SEC
);
1500 static void gt_sec_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1503 gt_cval_write(env
, ri
, GTIMER_SEC
, value
);
1506 static uint64_t gt_sec_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1508 return gt_tval_read(env
, ri
, GTIMER_SEC
);
1511 static void gt_sec_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1514 gt_tval_write(env
, ri
, GTIMER_SEC
, value
);
1517 static void gt_sec_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1520 gt_ctl_write(env
, ri
, GTIMER_SEC
, value
);
1523 void arm_gt_ptimer_cb(void *opaque
)
1525 ARMCPU
*cpu
= opaque
;
1527 gt_recalc_timer(cpu
, GTIMER_PHYS
);
1530 void arm_gt_vtimer_cb(void *opaque
)
1532 ARMCPU
*cpu
= opaque
;
1534 gt_recalc_timer(cpu
, GTIMER_VIRT
);
1537 void arm_gt_htimer_cb(void *opaque
)
1539 ARMCPU
*cpu
= opaque
;
1541 gt_recalc_timer(cpu
, GTIMER_HYP
);
1544 void arm_gt_stimer_cb(void *opaque
)
1546 ARMCPU
*cpu
= opaque
;
1548 gt_recalc_timer(cpu
, GTIMER_SEC
);
1551 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
1552 /* Note that CNTFRQ is purely reads-as-written for the benefit
1553 * of software; writing it doesn't actually change the timer frequency.
1554 * Our reset value matches the fixed frequency we implement the timer at.
1556 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
1557 .type
= ARM_CP_ALIAS
,
1558 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
1559 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
1561 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
1562 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
1563 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
1564 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
1565 .resetvalue
= (1000 * 1000 * 1000) / GTIMER_SCALE
,
1567 /* overall control: mostly access permissions */
1568 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
1569 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
1571 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
1574 /* per-timer control */
1575 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
1576 .secure
= ARM_CP_SECSTATE_NS
,
1577 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL1_RW
| PL0_R
,
1578 .accessfn
= gt_ptimer_access
,
1579 .fieldoffset
= offsetoflow32(CPUARMState
,
1580 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
1581 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
,
1583 { .name
= "CNTP_CTL(S)",
1584 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
1585 .secure
= ARM_CP_SECSTATE_S
,
1586 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL1_RW
| PL0_R
,
1587 .accessfn
= gt_ptimer_access
,
1588 .fieldoffset
= offsetoflow32(CPUARMState
,
1589 cp15
.c14_timer
[GTIMER_SEC
].ctl
),
1590 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
1592 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
1593 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
1594 .type
= ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1595 .accessfn
= gt_ptimer_access
,
1596 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
1598 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
,
1600 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
1601 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL1_RW
| PL0_R
,
1602 .accessfn
= gt_vtimer_access
,
1603 .fieldoffset
= offsetoflow32(CPUARMState
,
1604 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
1605 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
,
1607 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
1608 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
1609 .type
= ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1610 .accessfn
= gt_vtimer_access
,
1611 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
1613 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
,
1615 /* TimerValue views: a 32 bit downcounting view of the underlying state */
1616 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
1617 .secure
= ARM_CP_SECSTATE_NS
,
1618 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1619 .accessfn
= gt_ptimer_access
,
1620 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
,
1622 { .name
= "CNTP_TVAL(S)",
1623 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
1624 .secure
= ARM_CP_SECSTATE_S
,
1625 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1626 .accessfn
= gt_ptimer_access
,
1627 .readfn
= gt_sec_tval_read
, .writefn
= gt_sec_tval_write
,
1629 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
1630 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
1631 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1632 .accessfn
= gt_ptimer_access
, .resetfn
= gt_phys_timer_reset
,
1633 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
,
1635 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
1636 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1637 .accessfn
= gt_vtimer_access
,
1638 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
,
1640 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
1641 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
1642 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1643 .accessfn
= gt_vtimer_access
, .resetfn
= gt_virt_timer_reset
,
1644 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
,
1646 /* The counter itself */
1647 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
1648 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
1649 .accessfn
= gt_pct_access
,
1650 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
1652 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
1653 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
1654 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
1655 .accessfn
= gt_pct_access
, .readfn
= gt_cnt_read
,
1657 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
1658 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
1659 .accessfn
= gt_vct_access
,
1660 .readfn
= gt_virt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
1662 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
1663 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
1664 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
1665 .accessfn
= gt_vct_access
, .readfn
= gt_virt_cnt_read
,
1667 /* Comparison value, indicating when the timer goes off */
1668 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
1669 .secure
= ARM_CP_SECSTATE_NS
,
1670 .access
= PL1_RW
| PL0_R
,
1671 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
1672 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
1673 .accessfn
= gt_ptimer_access
,
1674 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
,
1676 { .name
= "CNTP_CVAL(S)", .cp
= 15, .crm
= 14, .opc1
= 2,
1677 .secure
= ARM_CP_SECSTATE_S
,
1678 .access
= PL1_RW
| PL0_R
,
1679 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
1680 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
1681 .accessfn
= gt_ptimer_access
,
1682 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
1684 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
1685 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
1686 .access
= PL1_RW
| PL0_R
,
1688 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
1689 .resetvalue
= 0, .accessfn
= gt_ptimer_access
,
1690 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
,
1692 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
1693 .access
= PL1_RW
| PL0_R
,
1694 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
1695 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
1696 .accessfn
= gt_vtimer_access
,
1697 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
,
1699 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
1700 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
1701 .access
= PL1_RW
| PL0_R
,
1703 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
1704 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
1705 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
,
1707 /* Secure timer -- this is actually restricted to only EL3
1708 * and configurably Secure-EL1 via the accessfn.
1710 { .name
= "CNTPS_TVAL_EL1", .state
= ARM_CP_STATE_AA64
,
1711 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 0,
1712 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
,
1713 .accessfn
= gt_stimer_access
,
1714 .readfn
= gt_sec_tval_read
,
1715 .writefn
= gt_sec_tval_write
,
1716 .resetfn
= gt_sec_timer_reset
,
1718 { .name
= "CNTPS_CTL_EL1", .state
= ARM_CP_STATE_AA64
,
1719 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 1,
1720 .type
= ARM_CP_IO
, .access
= PL1_RW
,
1721 .accessfn
= gt_stimer_access
,
1722 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].ctl
),
1724 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
1726 { .name
= "CNTPS_CVAL_EL1", .state
= ARM_CP_STATE_AA64
,
1727 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 2,
1728 .type
= ARM_CP_IO
, .access
= PL1_RW
,
1729 .accessfn
= gt_stimer_access
,
1730 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
1731 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
1737 /* In user-mode none of the generic timer registers are accessible,
1738 * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1739 * so instead just don't register any of them.
1741 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
1747 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1749 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
1750 raw_write(env
, ri
, value
);
1751 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
1752 raw_write(env
, ri
, value
& 0xfffff6ff);
1754 raw_write(env
, ri
, value
& 0xfffff1ff);
1758 #ifndef CONFIG_USER_ONLY
1759 /* get_phys_addr() isn't present for user-mode-only targets */
1761 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1764 /* The ATS12NSO* operations must trap to EL3 if executed in
1765 * Secure EL1 (which can only happen if EL3 is AArch64).
1766 * They are simply UNDEF if executed from NS EL1.
1767 * They function normally from EL2 or EL3.
1769 if (arm_current_el(env
) == 1) {
1770 if (arm_is_secure_below_el3(env
)) {
1771 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3
;
1773 return CP_ACCESS_TRAP_UNCATEGORIZED
;
1776 return CP_ACCESS_OK
;
1779 static uint64_t do_ats_write(CPUARMState
*env
, uint64_t value
,
1780 int access_type
, ARMMMUIdx mmu_idx
)
1783 target_ulong page_size
;
1788 MemTxAttrs attrs
= {};
1789 ARMMMUFaultInfo fi
= {};
1791 ret
= get_phys_addr(env
, value
, access_type
, mmu_idx
,
1792 &phys_addr
, &attrs
, &prot
, &page_size
, &fsr
, &fi
);
1793 if (extended_addresses_enabled(env
)) {
1794 /* fsr is a DFSR/IFSR value for the long descriptor
1795 * translation table format, but with WnR always clear.
1796 * Convert it to a 64-bit PAR.
1798 par64
= (1 << 11); /* LPAE bit always set */
1800 par64
|= phys_addr
& ~0xfffULL
;
1801 if (!attrs
.secure
) {
1802 par64
|= (1 << 9); /* NS */
1804 /* We don't set the ATTR or SH fields in the PAR. */
1807 par64
|= (fsr
& 0x3f) << 1; /* FS */
1808 /* Note that S2WLK and FSTAGE are always zero, because we don't
1809 * implement virtualization and therefore there can't be a stage 2
1814 /* fsr is a DFSR/IFSR value for the short descriptor
1815 * translation table format (with WnR always clear).
1816 * Convert it to a 32-bit PAR.
1819 /* We do not set any attribute bits in the PAR */
1820 if (page_size
== (1 << 24)
1821 && arm_feature(env
, ARM_FEATURE_V7
)) {
1822 par64
= (phys_addr
& 0xff000000) | (1 << 1);
1824 par64
= phys_addr
& 0xfffff000;
1826 if (!attrs
.secure
) {
1827 par64
|= (1 << 9); /* NS */
1830 par64
= ((fsr
& (1 << 10)) >> 5) | ((fsr
& (1 << 12)) >> 6) |
1831 ((fsr
& 0xf) << 1) | 1;
1837 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1839 int access_type
= ri
->opc2
& 1;
1842 int el
= arm_current_el(env
);
1843 bool secure
= arm_is_secure_below_el3(env
);
1845 switch (ri
->opc2
& 6) {
1847 /* stage 1 current state PL1: ATS1CPR, ATS1CPW */
1850 mmu_idx
= ARMMMUIdx_S1E3
;
1853 mmu_idx
= ARMMMUIdx_S1NSE1
;
1856 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S1NSE1
;
1859 g_assert_not_reached();
1863 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
1866 mmu_idx
= ARMMMUIdx_S1SE0
;
1869 mmu_idx
= ARMMMUIdx_S1NSE0
;
1872 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S1NSE0
;
1875 g_assert_not_reached();
1879 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
1880 mmu_idx
= ARMMMUIdx_S12NSE1
;
1883 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
1884 mmu_idx
= ARMMMUIdx_S12NSE0
;
1887 g_assert_not_reached();
1890 par64
= do_ats_write(env
, value
, access_type
, mmu_idx
);
1892 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
1895 static void ats1h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1898 int access_type
= ri
->opc2
& 1;
1901 par64
= do_ats_write(env
, value
, access_type
, ARMMMUIdx_S2NS
);
1903 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
1906 static CPAccessResult
at_s1e2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1908 if (arm_current_el(env
) == 3 && !(env
->cp15
.scr_el3
& SCR_NS
)) {
1909 return CP_ACCESS_TRAP
;
1911 return CP_ACCESS_OK
;
1914 static void ats_write64(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1917 int access_type
= ri
->opc2
& 1;
1919 int secure
= arm_is_secure_below_el3(env
);
1921 switch (ri
->opc2
& 6) {
1924 case 0: /* AT S1E1R, AT S1E1W */
1925 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S1NSE1
;
1927 case 4: /* AT S1E2R, AT S1E2W */
1928 mmu_idx
= ARMMMUIdx_S1E2
;
1930 case 6: /* AT S1E3R, AT S1E3W */
1931 mmu_idx
= ARMMMUIdx_S1E3
;
1934 g_assert_not_reached();
1937 case 2: /* AT S1E0R, AT S1E0W */
1938 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S1NSE0
;
1940 case 4: /* AT S12E1R, AT S12E1W */
1941 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S12NSE1
;
1943 case 6: /* AT S12E0R, AT S12E0W */
1944 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S12NSE0
;
1947 g_assert_not_reached();
1950 env
->cp15
.par_el
[1] = do_ats_write(env
, value
, access_type
, mmu_idx
);
1954 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
1955 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
1956 .access
= PL1_RW
, .resetvalue
= 0,
1957 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.par_s
),
1958 offsetoflow32(CPUARMState
, cp15
.par_ns
) },
1959 .writefn
= par_write
},
1960 #ifndef CONFIG_USER_ONLY
1961 /* This underdecoding is safe because the reginfo is NO_RAW. */
1962 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
1963 .access
= PL1_W
, .accessfn
= ats_access
,
1964 .writefn
= ats_write
, .type
= ARM_CP_NO_RAW
},
1969 /* Return basic MPU access permission bits. */
1970 static uint32_t simple_mpu_ap_bits(uint32_t val
)
1977 for (i
= 0; i
< 16; i
+= 2) {
1978 ret
|= (val
>> i
) & mask
;
1984 /* Pad basic MPU access permission bits to extended format. */
1985 static uint32_t extended_mpu_ap_bits(uint32_t val
)
1992 for (i
= 0; i
< 16; i
+= 2) {
1993 ret
|= (val
& mask
) << i
;
1999 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2002 env
->cp15
.pmsav5_data_ap
= extended_mpu_ap_bits(value
);
2005 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2007 return simple_mpu_ap_bits(env
->cp15
.pmsav5_data_ap
);
2010 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2013 env
->cp15
.pmsav5_insn_ap
= extended_mpu_ap_bits(value
);
2016 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2018 return simple_mpu_ap_bits(env
->cp15
.pmsav5_insn_ap
);
2021 static uint64_t pmsav7_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2023 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
2029 u32p
+= env
->cp15
.c6_rgnr
;
2033 static void pmsav7_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2036 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2037 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
2043 u32p
+= env
->cp15
.c6_rgnr
;
2044 tlb_flush(CPU(cpu
), 1); /* Mappings may have changed - purge! */
2048 static void pmsav7_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2050 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2051 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
2057 memset(u32p
, 0, sizeof(*u32p
) * cpu
->pmsav7_dregion
);
2060 static void pmsav7_rgnr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2063 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2064 uint32_t nrgs
= cpu
->pmsav7_dregion
;
2066 if (value
>= nrgs
) {
2067 qemu_log_mask(LOG_GUEST_ERROR
,
2068 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
2069 " > %" PRIu32
"\n", (uint32_t)value
, nrgs
);
2073 raw_write(env
, ri
, value
);
2076 static const ARMCPRegInfo pmsav7_cp_reginfo
[] = {
2077 { .name
= "DRBAR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 0,
2078 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
2079 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drbar
),
2080 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
, .resetfn
= pmsav7_reset
},
2081 { .name
= "DRSR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 2,
2082 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
2083 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drsr
),
2084 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
, .resetfn
= pmsav7_reset
},
2085 { .name
= "DRACR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 4,
2086 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
2087 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.dracr
),
2088 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
, .resetfn
= pmsav7_reset
},
2089 { .name
= "RGNR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 2, .opc2
= 0,
2091 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_rgnr
),
2092 .writefn
= pmsav7_rgnr_write
},
2096 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
2097 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
2098 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
2099 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
2100 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
2101 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
2102 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
2103 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
2104 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
2105 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
2107 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
2109 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
2111 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
2113 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
2115 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
2116 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
2118 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
2119 /* Protection region base and size registers */
2120 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
2121 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2122 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
2123 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
2124 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2125 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
2126 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
2127 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2128 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
2129 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
2130 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2131 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
2132 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
2133 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2134 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
2135 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
2136 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2137 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
2138 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
2139 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2140 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
2141 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
2142 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2143 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
2147 static void vmsa_ttbcr_raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2150 TCR
*tcr
= raw_ptr(env
, ri
);
2151 int maskshift
= extract32(value
, 0, 3);
2153 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
2154 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& TTBCR_EAE
)) {
2155 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
2156 * using Long-desciptor translation table format */
2157 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
2158 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
2159 /* In an implementation that includes the Security Extensions
2160 * TTBCR has additional fields PD0 [4] and PD1 [5] for
2161 * Short-descriptor translation table format.
2163 value
&= TTBCR_PD1
| TTBCR_PD0
| TTBCR_N
;
2169 /* Update the masks corresponding to the TCR bank being written
2170 * Note that we always calculate mask and base_mask, but
2171 * they are only used for short-descriptor tables (ie if EAE is 0);
2172 * for long-descriptor tables the TCR fields are used differently
2173 * and the mask and base_mask values are meaningless.
2175 tcr
->raw_tcr
= value
;
2176 tcr
->mask
= ~(((uint32_t)0xffffffffu
) >> maskshift
);
2177 tcr
->base_mask
= ~((uint32_t)0x3fffu
>> maskshift
);
2180 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2183 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2185 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
2186 /* With LPAE the TTBCR could result in a change of ASID
2187 * via the TTBCR.A1 bit, so do a TLB flush.
2189 tlb_flush(CPU(cpu
), 1);
2191 vmsa_ttbcr_raw_write(env
, ri
, value
);
2194 static void vmsa_ttbcr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2196 TCR
*tcr
= raw_ptr(env
, ri
);
2198 /* Reset both the TCR as well as the masks corresponding to the bank of
2199 * the TCR being reset.
2203 tcr
->base_mask
= 0xffffc000u
;
2206 static void vmsa_tcr_el1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2209 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2210 TCR
*tcr
= raw_ptr(env
, ri
);
2212 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
2213 tlb_flush(CPU(cpu
), 1);
2214 tcr
->raw_tcr
= value
;
2217 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2220 /* 64 bit accesses to the TTBRs can change the ASID and so we
2221 * must flush the TLB.
2223 if (cpreg_field_is_64bit(ri
)) {
2224 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2226 tlb_flush(CPU(cpu
), 1);
2228 raw_write(env
, ri
, value
);
2231 static void vttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2234 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2235 CPUState
*cs
= CPU(cpu
);
2237 /* Accesses to VTTBR may change the VMID so we must flush the TLB. */
2238 if (raw_read(env
, ri
) != value
) {
2239 tlb_flush_by_mmuidx(cs
, ARMMMUIdx_S12NSE1
, ARMMMUIdx_S12NSE0
,
2240 ARMMMUIdx_S2NS
, -1);
2241 raw_write(env
, ri
, value
);
2245 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo
[] = {
2246 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
2247 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
2248 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dfsr_s
),
2249 offsetoflow32(CPUARMState
, cp15
.dfsr_ns
) }, },
2250 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
2251 .access
= PL1_RW
, .resetvalue
= 0,
2252 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.ifsr_s
),
2253 offsetoflow32(CPUARMState
, cp15
.ifsr_ns
) } },
2254 { .name
= "DFAR", .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 0, .opc2
= 0,
2255 .access
= PL1_RW
, .resetvalue
= 0,
2256 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.dfar_s
),
2257 offsetof(CPUARMState
, cp15
.dfar_ns
) } },
2258 { .name
= "FAR_EL1", .state
= ARM_CP_STATE_AA64
,
2259 .opc0
= 3, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
2260 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[1]),
2265 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
2266 { .name
= "ESR_EL1", .state
= ARM_CP_STATE_AA64
,
2267 .opc0
= 3, .crn
= 5, .crm
= 2, .opc1
= 0, .opc2
= 0,
2269 .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[1]), .resetvalue
= 0, },
2270 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
2271 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 0,
2272 .access
= PL1_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
2273 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
2274 offsetof(CPUARMState
, cp15
.ttbr0_ns
) } },
2275 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
2276 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 1,
2277 .access
= PL1_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
2278 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
2279 offsetof(CPUARMState
, cp15
.ttbr1_ns
) } },
2280 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
2281 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
2282 .access
= PL1_RW
, .writefn
= vmsa_tcr_el1_write
,
2283 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= raw_write
,
2284 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[1]) },
2285 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
2286 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
, .writefn
= vmsa_ttbcr_write
,
2287 .raw_writefn
= vmsa_ttbcr_raw_write
,
2288 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tcr_el
[3]),
2289 offsetoflow32(CPUARMState
, cp15
.tcr_el
[1])} },
2293 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2296 env
->cp15
.c15_ticonfig
= value
& 0xe7;
2297 /* The OS_TYPE bit in this register changes the reported CPUID! */
2298 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
2299 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
2302 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2305 env
->cp15
.c15_threadid
= value
& 0xffff;
2308 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2311 /* Wait-for-interrupt (deprecated) */
2312 cpu_interrupt(CPU(arm_env_get_cpu(env
)), CPU_INTERRUPT_HALT
);
2315 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2318 /* On OMAP there are registers indicating the max/min index of dcache lines
2319 * containing a dirty line; cache flush operations have to reset these.
2321 env
->cp15
.c15_i_max
= 0x000;
2322 env
->cp15
.c15_i_min
= 0xff0;
2325 static const ARMCPRegInfo omap_cp_reginfo
[] = {
2326 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
2327 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
2328 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el
[1]),
2330 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
2331 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
2332 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
2334 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
2335 .writefn
= omap_ticonfig_write
},
2336 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
2338 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
2339 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
2340 .access
= PL1_RW
, .resetvalue
= 0xff0,
2341 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
2342 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
2344 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
2345 .writefn
= omap_threadid_write
},
2346 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
2347 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
2348 .type
= ARM_CP_NO_RAW
,
2349 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
2350 /* TODO: Peripheral port remap register:
2351 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
2352 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
2355 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
2356 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
2357 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
,
2358 .writefn
= omap_cachemaint_write
},
2359 { .name
= "C9", .cp
= 15, .crn
= 9,
2360 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
2361 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
2365 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2368 env
->cp15
.c15_cpar
= value
& 0x3fff;
2371 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
2372 { .name
= "XSCALE_CPAR",
2373 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
2374 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
2375 .writefn
= xscale_cpar_write
, },
2376 { .name
= "XSCALE_AUXCR",
2377 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
2378 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
2380 /* XScale specific cache-lockdown: since we have no cache we NOP these
2381 * and hope the guest does not really rely on cache behaviour.
2383 { .name
= "XSCALE_LOCK_ICACHE_LINE",
2384 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
2385 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2386 { .name
= "XSCALE_UNLOCK_ICACHE",
2387 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
2388 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2389 { .name
= "XSCALE_DCACHE_LOCK",
2390 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 0,
2391 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
2392 { .name
= "XSCALE_UNLOCK_DCACHE",
2393 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 1,
2394 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2398 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
2399 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
2400 * implementation of this implementation-defined space.
2401 * Ideally this should eventually disappear in favour of actually
2402 * implementing the correct behaviour for all cores.
2404 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
2405 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
2407 .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
| ARM_CP_OVERRIDE
,
2412 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
2413 /* Cache status: RAZ because we have no cache so it's always clean */
2414 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
2415 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2420 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
2421 /* We never have a a block transfer operation in progress */
2422 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
2423 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2425 /* The cache ops themselves: these all NOP for QEMU */
2426 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
2427 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2428 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
2429 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2430 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
2431 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2432 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
2433 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2434 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
2435 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2436 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
2437 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2441 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
2442 /* The cache test-and-clean instructions always return (1 << 30)
2443 * to indicate that there are no dirty cache lines.
2445 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
2446 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2447 .resetvalue
= (1 << 30) },
2448 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
2449 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2450 .resetvalue
= (1 << 30) },
2454 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
2455 /* Ignore ReadBuffer accesses */
2456 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
2457 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
2458 .access
= PL1_RW
, .resetvalue
= 0,
2459 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
},
2463 static uint64_t midr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2465 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2466 unsigned int cur_el
= arm_current_el(env
);
2467 bool secure
= arm_is_secure(env
);
2469 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
) && !secure
&& cur_el
== 1) {
2470 return env
->cp15
.vpidr_el2
;
2472 return raw_read(env
, ri
);
2475 static uint64_t mpidr_read_val(CPUARMState
*env
)
2477 ARMCPU
*cpu
= ARM_CPU(arm_env_get_cpu(env
));
2478 uint64_t mpidr
= cpu
->mp_affinity
;
2480 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
2481 mpidr
|= (1U << 31);
2482 /* Cores which are uniprocessor (non-coherent)
2483 * but still implement the MP extensions set
2484 * bit 30. (For instance, Cortex-R5).
2486 if (cpu
->mp_is_up
) {
2487 mpidr
|= (1u << 30);
2493 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2495 unsigned int cur_el
= arm_current_el(env
);
2496 bool secure
= arm_is_secure(env
);
2498 if (arm_feature(env
, ARM_FEATURE_EL2
) && !secure
&& cur_el
== 1) {
2499 return env
->cp15
.vmpidr_el2
;
2501 return mpidr_read_val(env
);
2504 static const ARMCPRegInfo mpidr_cp_reginfo
[] = {
2505 { .name
= "MPIDR", .state
= ARM_CP_STATE_BOTH
,
2506 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
2507 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_RAW
},
2511 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
2513 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
2514 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
2515 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
2517 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
2518 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
2519 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
2521 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
2522 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .resetvalue
= 0,
2523 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.par_s
),
2524 offsetof(CPUARMState
, cp15
.par_ns
)} },
2525 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
2526 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
2527 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
2528 offsetof(CPUARMState
, cp15
.ttbr0_ns
) },
2529 .writefn
= vmsa_ttbr_write
, },
2530 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
2531 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
2532 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
2533 offsetof(CPUARMState
, cp15
.ttbr1_ns
) },
2534 .writefn
= vmsa_ttbr_write
, },
2538 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2540 return vfp_get_fpcr(env
);
2543 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2546 vfp_set_fpcr(env
, value
);
2549 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2551 return vfp_get_fpsr(env
);
2554 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2557 vfp_set_fpsr(env
, value
);
2560 static CPAccessResult
aa64_daif_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2562 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UMA
)) {
2563 return CP_ACCESS_TRAP
;
2565 return CP_ACCESS_OK
;
2568 static void aa64_daif_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2571 env
->daif
= value
& PSTATE_DAIF
;
2574 static CPAccessResult
aa64_cacheop_access(CPUARMState
*env
,
2575 const ARMCPRegInfo
*ri
)
2577 /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
2578 * SCTLR_EL1.UCI is set.
2580 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UCI
)) {
2581 return CP_ACCESS_TRAP
;
2583 return CP_ACCESS_OK
;
2586 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
2587 * Page D4-1736 (DDI0487A.b)
2590 static void tlbi_aa64_vmalle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2593 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2594 CPUState
*cs
= CPU(cpu
);
2596 if (arm_is_secure_below_el3(env
)) {
2597 tlb_flush_by_mmuidx(cs
, ARMMMUIdx_S1SE1
, ARMMMUIdx_S1SE0
, -1);
2599 tlb_flush_by_mmuidx(cs
, ARMMMUIdx_S12NSE1
, ARMMMUIdx_S12NSE0
, -1);
2603 static void tlbi_aa64_vmalle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2606 bool sec
= arm_is_secure_below_el3(env
);
2609 CPU_FOREACH(other_cs
) {
2611 tlb_flush_by_mmuidx(other_cs
, ARMMMUIdx_S1SE1
, ARMMMUIdx_S1SE0
, -1);
2613 tlb_flush_by_mmuidx(other_cs
, ARMMMUIdx_S12NSE1
,
2614 ARMMMUIdx_S12NSE0
, -1);
2619 static void tlbi_aa64_alle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2622 /* Note that the 'ALL' scope must invalidate both stage 1 and
2623 * stage 2 translations, whereas most other scopes only invalidate
2624 * stage 1 translations.
2626 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2627 CPUState
*cs
= CPU(cpu
);
2629 if (arm_is_secure_below_el3(env
)) {
2630 tlb_flush_by_mmuidx(cs
, ARMMMUIdx_S1SE1
, ARMMMUIdx_S1SE0
, -1);
2632 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
2633 tlb_flush_by_mmuidx(cs
, ARMMMUIdx_S12NSE1
, ARMMMUIdx_S12NSE0
,
2634 ARMMMUIdx_S2NS
, -1);
2636 tlb_flush_by_mmuidx(cs
, ARMMMUIdx_S12NSE1
, ARMMMUIdx_S12NSE0
, -1);
2641 static void tlbi_aa64_alle2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2644 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2645 CPUState
*cs
= CPU(cpu
);
2647 tlb_flush_by_mmuidx(cs
, ARMMMUIdx_S1E2
, -1);
2650 static void tlbi_aa64_alle3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2653 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2654 CPUState
*cs
= CPU(cpu
);
2656 tlb_flush_by_mmuidx(cs
, ARMMMUIdx_S1E3
, -1);
2659 static void tlbi_aa64_alle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2662 /* Note that the 'ALL' scope must invalidate both stage 1 and
2663 * stage 2 translations, whereas most other scopes only invalidate
2664 * stage 1 translations.
2666 bool sec
= arm_is_secure_below_el3(env
);
2667 bool has_el2
= arm_feature(env
, ARM_FEATURE_EL2
);
2670 CPU_FOREACH(other_cs
) {
2672 tlb_flush_by_mmuidx(other_cs
, ARMMMUIdx_S1SE1
, ARMMMUIdx_S1SE0
, -1);
2673 } else if (has_el2
) {
2674 tlb_flush_by_mmuidx(other_cs
, ARMMMUIdx_S12NSE1
,
2675 ARMMMUIdx_S12NSE0
, ARMMMUIdx_S2NS
, -1);
2677 tlb_flush_by_mmuidx(other_cs
, ARMMMUIdx_S12NSE1
,
2678 ARMMMUIdx_S12NSE0
, -1);
2683 static void tlbi_aa64_alle2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2688 CPU_FOREACH(other_cs
) {
2689 tlb_flush_by_mmuidx(other_cs
, ARMMMUIdx_S1E2
, -1);
2693 static void tlbi_aa64_alle3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2698 CPU_FOREACH(other_cs
) {
2699 tlb_flush_by_mmuidx(other_cs
, ARMMMUIdx_S1E3
, -1);
2703 static void tlbi_aa64_vae1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2706 /* Invalidate by VA, EL1&0 (AArch64 version).
2707 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
2708 * since we don't support flush-for-specific-ASID-only or
2709 * flush-last-level-only.
2711 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2712 CPUState
*cs
= CPU(cpu
);
2713 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
2715 if (arm_is_secure_below_el3(env
)) {
2716 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdx_S1SE1
,
2717 ARMMMUIdx_S1SE0
, -1);
2719 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdx_S12NSE1
,
2720 ARMMMUIdx_S12NSE0
, -1);
2724 static void tlbi_aa64_vae2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2727 /* Invalidate by VA, EL2
2728 * Currently handles both VAE2 and VALE2, since we don't support
2729 * flush-last-level-only.
2731 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2732 CPUState
*cs
= CPU(cpu
);
2733 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
2735 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdx_S1E2
, -1);
2738 static void tlbi_aa64_vae3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2741 /* Invalidate by VA, EL3
2742 * Currently handles both VAE3 and VALE3, since we don't support
2743 * flush-last-level-only.
2745 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2746 CPUState
*cs
= CPU(cpu
);
2747 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
2749 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdx_S1E3
, -1);
2752 static void tlbi_aa64_vae1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2755 bool sec
= arm_is_secure_below_el3(env
);
2757 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
2759 CPU_FOREACH(other_cs
) {
2761 tlb_flush_page_by_mmuidx(other_cs
, pageaddr
, ARMMMUIdx_S1SE1
,
2762 ARMMMUIdx_S1SE0
, -1);
2764 tlb_flush_page_by_mmuidx(other_cs
, pageaddr
, ARMMMUIdx_S12NSE1
,
2765 ARMMMUIdx_S12NSE0
, -1);
2770 static void tlbi_aa64_vae2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2774 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
2776 CPU_FOREACH(other_cs
) {
2777 tlb_flush_page_by_mmuidx(other_cs
, pageaddr
, ARMMMUIdx_S1E2
, -1);
2781 static void tlbi_aa64_vae3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2785 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
2787 CPU_FOREACH(other_cs
) {
2788 tlb_flush_page_by_mmuidx(other_cs
, pageaddr
, ARMMMUIdx_S1E3
, -1);
2792 static void tlbi_aa64_ipas2e1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2795 /* Invalidate by IPA. This has to invalidate any structures that
2796 * contain only stage 2 translation information, but does not need
2797 * to apply to structures that contain combined stage 1 and stage 2
2798 * translation information.
2799 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
2801 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2802 CPUState
*cs
= CPU(cpu
);
2805 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
2809 pageaddr
= sextract64(value
<< 12, 0, 48);
2811 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdx_S2NS
, -1);
2814 static void tlbi_aa64_ipas2e1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2820 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
2824 pageaddr
= sextract64(value
<< 12, 0, 48);
2826 CPU_FOREACH(other_cs
) {
2827 tlb_flush_page_by_mmuidx(other_cs
, pageaddr
, ARMMMUIdx_S2NS
, -1);
2831 static CPAccessResult
aa64_zva_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2833 /* We don't implement EL2, so the only control on DC ZVA is the
2834 * bit in the SCTLR which can prohibit access for EL0.
2836 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_DZE
)) {
2837 return CP_ACCESS_TRAP
;
2839 return CP_ACCESS_OK
;
2842 static uint64_t aa64_dczid_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2844 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2845 int dzp_bit
= 1 << 4;
2847 /* DZP indicates whether DC ZVA access is allowed */
2848 if (aa64_zva_access(env
, NULL
) == CP_ACCESS_OK
) {
2851 return cpu
->dcz_blocksize
| dzp_bit
;
2854 static CPAccessResult
sp_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2856 if (!(env
->pstate
& PSTATE_SP
)) {
2857 /* Access to SP_EL0 is undefined if it's being used as
2858 * the stack pointer.
2860 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2862 return CP_ACCESS_OK
;
2865 static uint64_t spsel_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2867 return env
->pstate
& PSTATE_SP
;
2870 static void spsel_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
2872 update_spsel(env
, val
);
2875 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2878 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2880 if (raw_read(env
, ri
) == value
) {
2881 /* Skip the TLB flush if nothing actually changed; Linux likes
2882 * to do a lot of pointless SCTLR writes.
2887 raw_write(env
, ri
, value
);
2888 /* ??? Lots of these bits are not implemented. */
2889 /* This may enable/disable the MMU, so do a TLB flush. */
2890 tlb_flush(CPU(cpu
), 1);
2893 static const ARMCPRegInfo v8_cp_reginfo
[] = {
2894 /* Minimal set of EL0-visible registers. This will need to be expanded
2895 * significantly for system emulation of AArch64 CPUs.
2897 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
2898 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
2899 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
2900 { .name
= "DAIF", .state
= ARM_CP_STATE_AA64
,
2901 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 2,
2902 .type
= ARM_CP_NO_RAW
,
2903 .access
= PL0_RW
, .accessfn
= aa64_daif_access
,
2904 .fieldoffset
= offsetof(CPUARMState
, daif
),
2905 .writefn
= aa64_daif_write
, .resetfn
= arm_cp_reset_ignore
},
2906 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
2907 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
2908 .access
= PL0_RW
, .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
2909 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
2910 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
2911 .access
= PL0_RW
, .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
2912 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
2913 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
2914 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
,
2915 .readfn
= aa64_dczid_read
},
2916 { .name
= "DC_ZVA", .state
= ARM_CP_STATE_AA64
,
2917 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 1,
2918 .access
= PL0_W
, .type
= ARM_CP_DC_ZVA
,
2919 #ifndef CONFIG_USER_ONLY
2920 /* Avoid overhead of an access check that always passes in user-mode */
2921 .accessfn
= aa64_zva_access
,
2924 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
2925 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
2926 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
2927 /* Cache ops: all NOPs since we don't emulate caches */
2928 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
2929 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
2930 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2931 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
2932 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
2933 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2934 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
2935 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
2936 .access
= PL0_W
, .type
= ARM_CP_NOP
,
2937 .accessfn
= aa64_cacheop_access
},
2938 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
2939 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
2940 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2941 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
2942 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
2943 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2944 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
2945 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
2946 .access
= PL0_W
, .type
= ARM_CP_NOP
,
2947 .accessfn
= aa64_cacheop_access
},
2948 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
2949 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
2950 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2951 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
2952 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
2953 .access
= PL0_W
, .type
= ARM_CP_NOP
,
2954 .accessfn
= aa64_cacheop_access
},
2955 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
2956 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
2957 .access
= PL0_W
, .type
= ARM_CP_NOP
,
2958 .accessfn
= aa64_cacheop_access
},
2959 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
2960 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
2961 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2962 /* TLBI operations */
2963 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
2964 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
2965 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2966 .writefn
= tlbi_aa64_vmalle1is_write
},
2967 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
2968 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
2969 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2970 .writefn
= tlbi_aa64_vae1is_write
},
2971 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
2972 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
2973 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2974 .writefn
= tlbi_aa64_vmalle1is_write
},
2975 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
2976 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
2977 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2978 .writefn
= tlbi_aa64_vae1is_write
},
2979 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
2980 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
2981 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2982 .writefn
= tlbi_aa64_vae1is_write
},
2983 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
2984 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
2985 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2986 .writefn
= tlbi_aa64_vae1is_write
},
2987 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
2988 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
2989 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2990 .writefn
= tlbi_aa64_vmalle1_write
},
2991 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
2992 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
2993 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2994 .writefn
= tlbi_aa64_vae1_write
},
2995 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
2996 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
2997 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
2998 .writefn
= tlbi_aa64_vmalle1_write
},
2999 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
3000 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
3001 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3002 .writefn
= tlbi_aa64_vae1_write
},
3003 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
3004 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
3005 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3006 .writefn
= tlbi_aa64_vae1_write
},
3007 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
3008 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
3009 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3010 .writefn
= tlbi_aa64_vae1_write
},
3011 { .name
= "TLBI_IPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
3012 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
3013 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3014 .writefn
= tlbi_aa64_ipas2e1is_write
},
3015 { .name
= "TLBI_IPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
3016 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
3017 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3018 .writefn
= tlbi_aa64_ipas2e1is_write
},
3019 { .name
= "TLBI_ALLE1IS", .state
= ARM_CP_STATE_AA64
,
3020 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
3021 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3022 .writefn
= tlbi_aa64_alle1is_write
},
3023 { .name
= "TLBI_VMALLS12E1IS", .state
= ARM_CP_STATE_AA64
,
3024 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 6,
3025 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3026 .writefn
= tlbi_aa64_alle1is_write
},
3027 { .name
= "TLBI_IPAS2E1", .state
= ARM_CP_STATE_AA64
,
3028 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
3029 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3030 .writefn
= tlbi_aa64_ipas2e1_write
},
3031 { .name
= "TLBI_IPAS2LE1", .state
= ARM_CP_STATE_AA64
,
3032 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
3033 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3034 .writefn
= tlbi_aa64_ipas2e1_write
},
3035 { .name
= "TLBI_ALLE1", .state
= ARM_CP_STATE_AA64
,
3036 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
3037 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3038 .writefn
= tlbi_aa64_alle1_write
},
3039 { .name
= "TLBI_VMALLS12E1", .state
= ARM_CP_STATE_AA64
,
3040 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 6,
3041 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3042 .writefn
= tlbi_aa64_alle1is_write
},
3043 #ifndef CONFIG_USER_ONLY
3044 /* 64 bit address translation operations */
3045 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
3046 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 0,
3047 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3048 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
3049 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 1,
3050 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3051 { .name
= "AT_S1E0R", .state
= ARM_CP_STATE_AA64
,
3052 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 2,
3053 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3054 { .name
= "AT_S1E0W", .state
= ARM_CP_STATE_AA64
,
3055 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 3,
3056 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3057 { .name
= "AT_S12E1R", .state
= ARM_CP_STATE_AA64
,
3058 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 4,
3059 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3060 { .name
= "AT_S12E1W", .state
= ARM_CP_STATE_AA64
,
3061 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 5,
3062 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3063 { .name
= "AT_S12E0R", .state
= ARM_CP_STATE_AA64
,
3064 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 6,
3065 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3066 { .name
= "AT_S12E0W", .state
= ARM_CP_STATE_AA64
,
3067 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 7,
3068 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3069 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
3070 { .name
= "AT_S1E3R", .state
= ARM_CP_STATE_AA64
,
3071 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 0,
3072 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3073 { .name
= "AT_S1E3W", .state
= ARM_CP_STATE_AA64
,
3074 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 1,
3075 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3076 { .name
= "PAR_EL1", .state
= ARM_CP_STATE_AA64
,
3077 .type
= ARM_CP_ALIAS
,
3078 .opc0
= 3, .opc1
= 0, .crn
= 7, .crm
= 4, .opc2
= 0,
3079 .access
= PL1_RW
, .resetvalue
= 0,
3080 .fieldoffset
= offsetof(CPUARMState
, cp15
.par_el
[1]),
3081 .writefn
= par_write
},
3083 /* TLB invalidate last level of translation table walk */
3084 { .name
= "TLBIMVALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
3085 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_is_write
},
3086 { .name
= "TLBIMVAALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
3087 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
3088 .writefn
= tlbimvaa_is_write
},
3089 { .name
= "TLBIMVAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
3090 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
3091 { .name
= "TLBIMVAAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
3092 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimvaa_write
},
3093 /* 32 bit cache operations */
3094 { .name
= "ICIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
3095 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3096 { .name
= "BPIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 6,
3097 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3098 { .name
= "ICIALLU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
3099 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3100 { .name
= "ICIMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 1,
3101 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3102 { .name
= "BPIALL", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 6,
3103 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3104 { .name
= "BPIMVA", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 7,
3105 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3106 { .name
= "DCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
3107 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3108 { .name
= "DCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
3109 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3110 { .name
= "DCCMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 1,
3111 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3112 { .name
= "DCCSW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
3113 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3114 { .name
= "DCCMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 11, .opc2
= 1,
3115 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3116 { .name
= "DCCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 1,
3117 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3118 { .name
= "DCCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
3119 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3120 /* MMU Domain access control / MPU write buffer control */
3121 { .name
= "DACR", .cp
= 15, .opc1
= 0, .crn
= 3, .crm
= 0, .opc2
= 0,
3122 .access
= PL1_RW
, .resetvalue
= 0,
3123 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
3124 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
3125 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
3126 { .name
= "ELR_EL1", .state
= ARM_CP_STATE_AA64
,
3127 .type
= ARM_CP_ALIAS
,
3128 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 1,
3130 .fieldoffset
= offsetof(CPUARMState
, elr_el
[1]) },
3131 { .name
= "SPSR_EL1", .state
= ARM_CP_STATE_AA64
,
3132 .type
= ARM_CP_ALIAS
,
3133 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 0,
3135 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_SVC
]) },
3136 /* We rely on the access checks not allowing the guest to write to the
3137 * state field when SPSel indicates that it's being used as the stack
3140 { .name
= "SP_EL0", .state
= ARM_CP_STATE_AA64
,
3141 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 1, .opc2
= 0,
3142 .access
= PL1_RW
, .accessfn
= sp_el0_access
,
3143 .type
= ARM_CP_ALIAS
,
3144 .fieldoffset
= offsetof(CPUARMState
, sp_el
[0]) },
3145 { .name
= "SP_EL1", .state
= ARM_CP_STATE_AA64
,
3146 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 1, .opc2
= 0,
3147 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
3148 .fieldoffset
= offsetof(CPUARMState
, sp_el
[1]) },
3149 { .name
= "SPSel", .state
= ARM_CP_STATE_AA64
,
3150 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 0,
3151 .type
= ARM_CP_NO_RAW
,
3152 .access
= PL1_RW
, .readfn
= spsel_read
, .writefn
= spsel_write
},
3156 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
3157 static const ARMCPRegInfo el3_no_el2_cp_reginfo
[] = {
3158 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_AA64
,
3159 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
3161 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
},
3162 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
3163 .type
= ARM_CP_NO_RAW
,
3164 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
3166 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
},
3167 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
3168 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
3169 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3170 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
3171 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
3172 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3174 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
3175 .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
3176 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3177 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
3178 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
3179 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3181 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
3182 .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
3183 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3185 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
3186 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
3187 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3189 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
3190 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
3191 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3193 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3194 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
3195 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3196 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3197 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
3198 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
3199 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3200 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
3201 .cp
= 15, .opc1
= 6, .crm
= 2,
3202 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
3203 .type
= ARM_CP_CONST
| ARM_CP_64BIT
, .resetvalue
= 0 },
3204 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
3205 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
3206 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3207 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
3208 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
3209 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3210 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
3211 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
3212 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3213 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
3214 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
3215 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3216 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
3217 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
3219 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
3220 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
3221 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3222 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
3223 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
3224 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3225 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
3226 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
3228 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
3229 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
3230 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3231 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
3232 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
3234 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
3235 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
3236 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3237 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
3238 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
3239 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3240 { .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3241 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
3242 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3243 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_BOTH
,
3244 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
3245 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
3246 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3250 static void hcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3252 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3253 uint64_t valid_mask
= HCR_MASK
;
3255 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
3256 valid_mask
&= ~HCR_HCD
;
3258 valid_mask
&= ~HCR_TSC
;
3261 /* Clear RES0 bits. */
3262 value
&= valid_mask
;
3264 /* These bits change the MMU setup:
3265 * HCR_VM enables stage 2 translation
3266 * HCR_PTW forbids certain page-table setups
3267 * HCR_DC Disables stage1 and enables stage2 translation
3269 if ((raw_read(env
, ri
) ^ value
) & (HCR_VM
| HCR_PTW
| HCR_DC
)) {
3270 tlb_flush(CPU(cpu
), 1);
3272 raw_write(env
, ri
, value
);
3275 static const ARMCPRegInfo el2_cp_reginfo
[] = {
3276 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
3277 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
3278 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
3279 .writefn
= hcr_write
},
3280 { .name
= "DACR32_EL2", .state
= ARM_CP_STATE_AA64
,
3281 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 0, .opc2
= 0,
3282 .access
= PL2_RW
, .resetvalue
= 0,
3283 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
3284 .fieldoffset
= offsetof(CPUARMState
, cp15
.dacr32_el2
) },
3285 { .name
= "ELR_EL2", .state
= ARM_CP_STATE_AA64
,
3286 .type
= ARM_CP_ALIAS
,
3287 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 1,
3289 .fieldoffset
= offsetof(CPUARMState
, elr_el
[2]) },
3290 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_AA64
,
3291 .type
= ARM_CP_ALIAS
,
3292 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
3293 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[2]) },
3294 { .name
= "IFSR32_EL2", .state
= ARM_CP_STATE_AA64
,
3295 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 0, .opc2
= 1,
3296 .access
= PL2_RW
, .resetvalue
= 0,
3297 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifsr32_el2
) },
3298 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_AA64
,
3299 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
3300 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[2]) },
3301 { .name
= "SPSR_EL2", .state
= ARM_CP_STATE_AA64
,
3302 .type
= ARM_CP_ALIAS
,
3303 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 0,
3305 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_HYP
]) },
3306 { .name
= "SPSR_IRQ", .state
= ARM_CP_STATE_AA64
,
3307 .type
= ARM_CP_ALIAS
,
3308 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 0,
3310 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_IRQ
]) },
3311 { .name
= "SPSR_ABT", .state
= ARM_CP_STATE_AA64
,
3312 .type
= ARM_CP_ALIAS
,
3313 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 1,
3315 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_ABT
]) },
3316 { .name
= "SPSR_UND", .state
= ARM_CP_STATE_AA64
,
3317 .type
= ARM_CP_ALIAS
,
3318 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 2,
3320 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_UND
]) },
3321 { .name
= "SPSR_FIQ", .state
= ARM_CP_STATE_AA64
,
3322 .type
= ARM_CP_ALIAS
,
3323 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 3,
3325 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_FIQ
]) },
3326 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_AA64
,
3327 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
3328 .access
= PL2_RW
, .writefn
= vbar_write
,
3329 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[2]),
3331 { .name
= "SP_EL2", .state
= ARM_CP_STATE_AA64
,
3332 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 1, .opc2
= 0,
3333 .access
= PL3_RW
, .type
= ARM_CP_ALIAS
,
3334 .fieldoffset
= offsetof(CPUARMState
, sp_el
[2]) },
3335 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
3336 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
3337 .access
= PL2_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
3338 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[2]) },
3339 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
3340 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
3341 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[2]),
3343 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
3344 .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
3345 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
3346 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el
[2]) },
3347 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
3348 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
3349 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3351 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
3352 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
3353 .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
3354 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3356 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
3357 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
3358 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3360 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
3361 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
3362 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3364 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3365 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
3366 .access
= PL2_RW
, .writefn
= vmsa_tcr_el1_write
,
3367 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= raw_write
,
3368 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[2]) },
3369 { .name
= "VTCR", .state
= ARM_CP_STATE_AA32
,
3370 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
3371 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
3372 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
3373 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_AA64
,
3374 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
3375 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
3376 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
3377 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
3378 .cp
= 15, .opc1
= 6, .crm
= 2,
3379 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
3380 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
3381 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
),
3382 .writefn
= vttbr_write
},
3383 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
3384 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
3385 .access
= PL2_RW
, .writefn
= vttbr_write
,
3386 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
) },
3387 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
3388 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
3389 .access
= PL2_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
3390 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[2]) },
3391 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
3392 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
3393 .access
= PL2_RW
, .resetvalue
= 0,
3394 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[2]) },
3395 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
3396 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
3397 .access
= PL2_RW
, .resetvalue
= 0,
3398 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
3399 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
3400 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
3401 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
3402 { .name
= "TLBI_ALLE2", .state
= ARM_CP_STATE_AA64
,
3403 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
3404 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3405 .writefn
= tlbi_aa64_alle2_write
},
3406 { .name
= "TLBI_VAE2", .state
= ARM_CP_STATE_AA64
,
3407 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
3408 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3409 .writefn
= tlbi_aa64_vae2_write
},
3410 { .name
= "TLBI_VALE2", .state
= ARM_CP_STATE_AA64
,
3411 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
3412 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3413 .writefn
= tlbi_aa64_vae2_write
},
3414 { .name
= "TLBI_ALLE2IS", .state
= ARM_CP_STATE_AA64
,
3415 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
3416 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3417 .writefn
= tlbi_aa64_alle2is_write
},
3418 { .name
= "TLBI_VAE2IS", .state
= ARM_CP_STATE_AA64
,
3419 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
3420 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3421 .writefn
= tlbi_aa64_vae2is_write
},
3422 { .name
= "TLBI_VALE2IS", .state
= ARM_CP_STATE_AA64
,
3423 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
3424 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3425 .writefn
= tlbi_aa64_vae2is_write
},
3426 #ifndef CONFIG_USER_ONLY
3427 /* Unlike the other EL2-related AT operations, these must
3428 * UNDEF from EL3 if EL2 is not implemented, which is why we
3429 * define them here rather than with the rest of the AT ops.
3431 { .name
= "AT_S1E2R", .state
= ARM_CP_STATE_AA64
,
3432 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
3433 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
3434 .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3435 { .name
= "AT_S1E2W", .state
= ARM_CP_STATE_AA64
,
3436 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
3437 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
3438 .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3439 /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
3440 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
3441 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
3442 * to behave as if SCR.NS was 1.
3444 { .name
= "ATS1HR", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
3446 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
},
3447 { .name
= "ATS1HW", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
3449 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
},
3450 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
3451 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
3452 /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
3453 * reset values as IMPDEF. We choose to reset to 3 to comply with
3454 * both ARMv7 and ARMv8.
3456 .access
= PL2_RW
, .resetvalue
= 3,
3457 .fieldoffset
= offsetof(CPUARMState
, cp15
.cnthctl_el2
) },
3458 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
3459 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
3460 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 0,
3461 .writefn
= gt_cntvoff_write
,
3462 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
3463 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
3464 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
| ARM_CP_IO
,
3465 .writefn
= gt_cntvoff_write
,
3466 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
3467 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
3468 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
3469 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
3470 .type
= ARM_CP_IO
, .access
= PL2_RW
,
3471 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
3472 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
3473 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
3474 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_IO
,
3475 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
3476 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
3477 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
3478 .type
= ARM_CP_IO
, .access
= PL2_RW
,
3479 .resetfn
= gt_hyp_timer_reset
,
3480 .readfn
= gt_hyp_tval_read
, .writefn
= gt_hyp_tval_write
},
3481 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
3483 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
3485 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].ctl
),
3487 .writefn
= gt_hyp_ctl_write
, .raw_writefn
= raw_write
},
3489 /* The only field of MDCR_EL2 that has a defined architectural reset value
3490 * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we
3491 * don't impelment any PMU event counters, so using zero as a reset
3492 * value for MDCR_EL2 is okay
3494 { .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3495 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
3496 .access
= PL2_RW
, .resetvalue
= 0,
3497 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el2
), },
3498 { .name
= "HPFAR", .state
= ARM_CP_STATE_AA32
,
3499 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
3500 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
3501 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
3502 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_AA64
,
3503 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
3505 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
3509 static const ARMCPRegInfo el3_cp_reginfo
[] = {
3510 { .name
= "SCR_EL3", .state
= ARM_CP_STATE_AA64
,
3511 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 0,
3512 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.scr_el3
),
3513 .resetvalue
= 0, .writefn
= scr_write
},
3514 { .name
= "SCR", .type
= ARM_CP_ALIAS
,
3515 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 0,
3516 .access
= PL3_RW
, .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.scr_el3
),
3517 .writefn
= scr_write
},
3518 { .name
= "SDER32_EL3", .state
= ARM_CP_STATE_AA64
,
3519 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 1,
3520 .access
= PL3_RW
, .resetvalue
= 0,
3521 .fieldoffset
= offsetof(CPUARMState
, cp15
.sder
) },
3523 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 1,
3524 .access
= PL3_RW
, .resetvalue
= 0,
3525 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.sder
) },
3526 /* TODO: Implement NSACR trapping of secure EL1 accesses to EL3 */
3527 { .name
= "NSACR", .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
3528 .access
= PL3_W
| PL1_R
, .resetvalue
= 0,
3529 .fieldoffset
= offsetof(CPUARMState
, cp15
.nsacr
) },
3530 { .name
= "MVBAR", .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
3531 .access
= PL3_RW
, .writefn
= vbar_write
, .resetvalue
= 0,
3532 .fieldoffset
= offsetof(CPUARMState
, cp15
.mvbar
) },
3533 { .name
= "SCTLR_EL3", .state
= ARM_CP_STATE_AA64
,
3534 .type
= ARM_CP_ALIAS
, /* reset handled by AArch32 view */
3535 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 0,
3536 .access
= PL3_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
3537 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[3]) },
3538 { .name
= "TTBR0_EL3", .state
= ARM_CP_STATE_AA64
,
3539 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 0,
3540 .access
= PL3_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
3541 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[3]) },
3542 { .name
= "TCR_EL3", .state
= ARM_CP_STATE_AA64
,
3543 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 2,
3544 .access
= PL3_RW
, .writefn
= vmsa_tcr_el1_write
,
3545 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= raw_write
,
3546 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[3]) },
3547 { .name
= "ELR_EL3", .state
= ARM_CP_STATE_AA64
,
3548 .type
= ARM_CP_ALIAS
,
3549 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 1,
3551 .fieldoffset
= offsetof(CPUARMState
, elr_el
[3]) },
3552 { .name
= "ESR_EL3", .state
= ARM_CP_STATE_AA64
,
3553 .type
= ARM_CP_ALIAS
,
3554 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 2, .opc2
= 0,
3555 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[3]) },
3556 { .name
= "FAR_EL3", .state
= ARM_CP_STATE_AA64
,
3557 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 0,
3558 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[3]) },
3559 { .name
= "SPSR_EL3", .state
= ARM_CP_STATE_AA64
,
3560 .type
= ARM_CP_ALIAS
,
3561 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 0,
3563 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_MON
]) },
3564 { .name
= "VBAR_EL3", .state
= ARM_CP_STATE_AA64
,
3565 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 0,
3566 .access
= PL3_RW
, .writefn
= vbar_write
,
3567 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[3]),
3569 { .name
= "CPTR_EL3", .state
= ARM_CP_STATE_AA64
,
3570 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 2,
3571 .access
= PL3_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
3572 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[3]) },
3573 { .name
= "TPIDR_EL3", .state
= ARM_CP_STATE_AA64
,
3574 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 2,
3575 .access
= PL3_RW
, .resetvalue
= 0,
3576 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[3]) },
3577 { .name
= "AMAIR_EL3", .state
= ARM_CP_STATE_AA64
,
3578 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 3, .opc2
= 0,
3579 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
3581 { .name
= "AFSR0_EL3", .state
= ARM_CP_STATE_BOTH
,
3582 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 0,
3583 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
3585 { .name
= "AFSR1_EL3", .state
= ARM_CP_STATE_BOTH
,
3586 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 1,
3587 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
3589 { .name
= "TLBI_ALLE3IS", .state
= ARM_CP_STATE_AA64
,
3590 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 0,
3591 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
3592 .writefn
= tlbi_aa64_alle3is_write
},
3593 { .name
= "TLBI_VAE3IS", .state
= ARM_CP_STATE_AA64
,
3594 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 1,
3595 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
3596 .writefn
= tlbi_aa64_vae3is_write
},
3597 { .name
= "TLBI_VALE3IS", .state
= ARM_CP_STATE_AA64
,
3598 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 5,
3599 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
3600 .writefn
= tlbi_aa64_vae3is_write
},
3601 { .name
= "TLBI_ALLE3", .state
= ARM_CP_STATE_AA64
,
3602 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 0,
3603 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
3604 .writefn
= tlbi_aa64_alle3_write
},
3605 { .name
= "TLBI_VAE3", .state
= ARM_CP_STATE_AA64
,
3606 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 1,
3607 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
3608 .writefn
= tlbi_aa64_vae3_write
},
3609 { .name
= "TLBI_VALE3", .state
= ARM_CP_STATE_AA64
,
3610 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 5,
3611 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
3612 .writefn
= tlbi_aa64_vae3_write
},
3616 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3618 /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
3619 * but the AArch32 CTR has its own reginfo struct)
3621 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UCT
)) {
3622 return CP_ACCESS_TRAP
;
3624 return CP_ACCESS_OK
;
3627 static void oslar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3630 /* Writes to OSLAR_EL1 may update the OS lock status, which can be
3631 * read via a bit in OSLSR_EL1.
3635 if (ri
->state
== ARM_CP_STATE_AA32
) {
3636 oslock
= (value
== 0xC5ACCE55);
3641 env
->cp15
.oslsr_el1
= deposit32(env
->cp15
.oslsr_el1
, 1, 1, oslock
);
3644 static const ARMCPRegInfo debug_cp_reginfo
[] = {
3645 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
3646 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
3647 * unlike DBGDRAR it is never accessible from EL0.
3648 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
3651 { .name
= "DBGDRAR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
3652 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3653 { .name
= "MDRAR_EL1", .state
= ARM_CP_STATE_AA64
,
3654 .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
3655 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3656 { .name
= "DBGDSAR", .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
3657 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3658 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
3659 { .name
= "MDSCR_EL1", .state
= ARM_CP_STATE_BOTH
,
3660 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
3662 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
),
3664 /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
3665 * We don't implement the configurable EL0 access.
3667 { .name
= "MDCCSR_EL0", .state
= ARM_CP_STATE_BOTH
,
3668 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
3669 .type
= ARM_CP_ALIAS
,
3671 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
), },
3672 { .name
= "OSLAR_EL1", .state
= ARM_CP_STATE_BOTH
,
3673 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 4,
3674 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3675 .writefn
= oslar_write
},
3676 { .name
= "OSLSR_EL1", .state
= ARM_CP_STATE_BOTH
,
3677 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 4,
3678 .access
= PL1_R
, .resetvalue
= 10,
3679 .fieldoffset
= offsetof(CPUARMState
, cp15
.oslsr_el1
) },
3680 /* Dummy OSDLR_EL1: 32-bit Linux will read this */
3681 { .name
= "OSDLR_EL1", .state
= ARM_CP_STATE_BOTH
,
3682 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 4,
3683 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
3684 /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
3685 * implement vector catch debug events yet.
3688 .cp
= 14, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
3689 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
3693 static const ARMCPRegInfo debug_lpae_cp_reginfo
[] = {
3694 /* 64 bit access versions of the (dummy) debug registers */
3695 { .name
= "DBGDRAR", .cp
= 14, .crm
= 1, .opc1
= 0,
3696 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
3697 { .name
= "DBGDSAR", .cp
= 14, .crm
= 2, .opc1
= 0,
3698 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
3702 void hw_watchpoint_update(ARMCPU
*cpu
, int n
)
3704 CPUARMState
*env
= &cpu
->env
;
3706 vaddr wvr
= env
->cp15
.dbgwvr
[n
];
3707 uint64_t wcr
= env
->cp15
.dbgwcr
[n
];
3709 int flags
= BP_CPU
| BP_STOP_BEFORE_ACCESS
;
3711 if (env
->cpu_watchpoint
[n
]) {
3712 cpu_watchpoint_remove_by_ref(CPU(cpu
), env
->cpu_watchpoint
[n
]);
3713 env
->cpu_watchpoint
[n
] = NULL
;
3716 if (!extract64(wcr
, 0, 1)) {
3717 /* E bit clear : watchpoint disabled */
3721 switch (extract64(wcr
, 3, 2)) {
3723 /* LSC 00 is reserved and must behave as if the wp is disabled */
3726 flags
|= BP_MEM_READ
;
3729 flags
|= BP_MEM_WRITE
;
3732 flags
|= BP_MEM_ACCESS
;
3736 /* Attempts to use both MASK and BAS fields simultaneously are
3737 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
3738 * thus generating a watchpoint for every byte in the masked region.
3740 mask
= extract64(wcr
, 24, 4);
3741 if (mask
== 1 || mask
== 2) {
3742 /* Reserved values of MASK; we must act as if the mask value was
3743 * some non-reserved value, or as if the watchpoint were disabled.
3744 * We choose the latter.
3748 /* Watchpoint covers an aligned area up to 2GB in size */
3750 /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
3751 * whether the watchpoint fires when the unmasked bits match; we opt
3752 * to generate the exceptions.
3756 /* Watchpoint covers bytes defined by the byte address select bits */
3757 int bas
= extract64(wcr
, 5, 8);
3761 /* This must act as if the watchpoint is disabled */
3765 if (extract64(wvr
, 2, 1)) {
3766 /* Deprecated case of an only 4-aligned address. BAS[7:4] are
3767 * ignored, and BAS[3:0] define which bytes to watch.
3771 /* The BAS bits are supposed to be programmed to indicate a contiguous
3772 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
3773 * we fire for each byte in the word/doubleword addressed by the WVR.
3774 * We choose to ignore any non-zero bits after the first range of 1s.
3776 basstart
= ctz32(bas
);
3777 len
= cto32(bas
>> basstart
);
3781 cpu_watchpoint_insert(CPU(cpu
), wvr
, len
, flags
,
3782 &env
->cpu_watchpoint
[n
]);
3785 void hw_watchpoint_update_all(ARMCPU
*cpu
)
3788 CPUARMState
*env
= &cpu
->env
;
3790 /* Completely clear out existing QEMU watchpoints and our array, to
3791 * avoid possible stale entries following migration load.
3793 cpu_watchpoint_remove_all(CPU(cpu
), BP_CPU
);
3794 memset(env
->cpu_watchpoint
, 0, sizeof(env
->cpu_watchpoint
));
3796 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_watchpoint
); i
++) {
3797 hw_watchpoint_update(cpu
, i
);
3801 static void dbgwvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3804 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3807 /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
3808 * register reads and behaves as if values written are sign extended.
3809 * Bits [1:0] are RES0.
3811 value
= sextract64(value
, 0, 49) & ~3ULL;
3813 raw_write(env
, ri
, value
);
3814 hw_watchpoint_update(cpu
, i
);
3817 static void dbgwcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3820 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3823 raw_write(env
, ri
, value
);
3824 hw_watchpoint_update(cpu
, i
);
3827 void hw_breakpoint_update(ARMCPU
*cpu
, int n
)
3829 CPUARMState
*env
= &cpu
->env
;
3830 uint64_t bvr
= env
->cp15
.dbgbvr
[n
];
3831 uint64_t bcr
= env
->cp15
.dbgbcr
[n
];
3836 if (env
->cpu_breakpoint
[n
]) {
3837 cpu_breakpoint_remove_by_ref(CPU(cpu
), env
->cpu_breakpoint
[n
]);
3838 env
->cpu_breakpoint
[n
] = NULL
;
3841 if (!extract64(bcr
, 0, 1)) {
3842 /* E bit clear : watchpoint disabled */
3846 bt
= extract64(bcr
, 20, 4);
3849 case 4: /* unlinked address mismatch (reserved if AArch64) */
3850 case 5: /* linked address mismatch (reserved if AArch64) */
3851 qemu_log_mask(LOG_UNIMP
,
3852 "arm: address mismatch breakpoint types not implemented");
3854 case 0: /* unlinked address match */
3855 case 1: /* linked address match */
3857 /* Bits [63:49] are hardwired to the value of bit [48]; that is,
3858 * we behave as if the register was sign extended. Bits [1:0] are
3859 * RES0. The BAS field is used to allow setting breakpoints on 16
3860 * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
3861 * a bp will fire if the addresses covered by the bp and the addresses
3862 * covered by the insn overlap but the insn doesn't start at the
3863 * start of the bp address range. We choose to require the insn and
3864 * the bp to have the same address. The constraints on writing to
3865 * BAS enforced in dbgbcr_write mean we have only four cases:
3866 * 0b0000 => no breakpoint
3867 * 0b0011 => breakpoint on addr
3868 * 0b1100 => breakpoint on addr + 2
3869 * 0b1111 => breakpoint on addr
3870 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
3872 int bas
= extract64(bcr
, 5, 4);
3873 addr
= sextract64(bvr
, 0, 49) & ~3ULL;
3882 case 2: /* unlinked context ID match */
3883 case 8: /* unlinked VMID match (reserved if no EL2) */
3884 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
3885 qemu_log_mask(LOG_UNIMP
,
3886 "arm: unlinked context breakpoint types not implemented");
3888 case 9: /* linked VMID match (reserved if no EL2) */
3889 case 11: /* linked context ID and VMID match (reserved if no EL2) */
3890 case 3: /* linked context ID match */
3892 /* We must generate no events for Linked context matches (unless
3893 * they are linked to by some other bp/wp, which is handled in
3894 * updates for the linking bp/wp). We choose to also generate no events
3895 * for reserved values.
3900 cpu_breakpoint_insert(CPU(cpu
), addr
, flags
, &env
->cpu_breakpoint
[n
]);
3903 void hw_breakpoint_update_all(ARMCPU
*cpu
)
3906 CPUARMState
*env
= &cpu
->env
;
3908 /* Completely clear out existing QEMU breakpoints and our array, to
3909 * avoid possible stale entries following migration load.
3911 cpu_breakpoint_remove_all(CPU(cpu
), BP_CPU
);
3912 memset(env
->cpu_breakpoint
, 0, sizeof(env
->cpu_breakpoint
));
3914 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_breakpoint
); i
++) {
3915 hw_breakpoint_update(cpu
, i
);
3919 static void dbgbvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3922 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3925 raw_write(env
, ri
, value
);
3926 hw_breakpoint_update(cpu
, i
);
3929 static void dbgbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3932 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3935 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
3938 value
= deposit64(value
, 6, 1, extract64(value
, 5, 1));
3939 value
= deposit64(value
, 8, 1, extract64(value
, 7, 1));
3941 raw_write(env
, ri
, value
);
3942 hw_breakpoint_update(cpu
, i
);
3945 static void define_debug_regs(ARMCPU
*cpu
)
3947 /* Define v7 and v8 architectural debug registers.
3948 * These are just dummy implementations for now.
3951 int wrps
, brps
, ctx_cmps
;
3952 ARMCPRegInfo dbgdidr
= {
3953 .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
3954 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->dbgdidr
,
3957 /* Note that all these register fields hold "number of Xs minus 1". */
3958 brps
= extract32(cpu
->dbgdidr
, 24, 4);
3959 wrps
= extract32(cpu
->dbgdidr
, 28, 4);
3960 ctx_cmps
= extract32(cpu
->dbgdidr
, 20, 4);
3962 assert(ctx_cmps
<= brps
);
3964 /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
3965 * of the debug registers such as number of breakpoints;
3966 * check that if they both exist then they agree.
3968 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
3969 assert(extract32(cpu
->id_aa64dfr0
, 12, 4) == brps
);
3970 assert(extract32(cpu
->id_aa64dfr0
, 20, 4) == wrps
);
3971 assert(extract32(cpu
->id_aa64dfr0
, 28, 4) == ctx_cmps
);
3974 define_one_arm_cp_reg(cpu
, &dbgdidr
);
3975 define_arm_cp_regs(cpu
, debug_cp_reginfo
);
3977 if (arm_feature(&cpu
->env
, ARM_FEATURE_LPAE
)) {
3978 define_arm_cp_regs(cpu
, debug_lpae_cp_reginfo
);
3981 for (i
= 0; i
< brps
+ 1; i
++) {
3982 ARMCPRegInfo dbgregs
[] = {
3983 { .name
= "DBGBVR", .state
= ARM_CP_STATE_BOTH
,
3984 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 4,
3986 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbvr
[i
]),
3987 .writefn
= dbgbvr_write
, .raw_writefn
= raw_write
3989 { .name
= "DBGBCR", .state
= ARM_CP_STATE_BOTH
,
3990 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 5,
3992 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbcr
[i
]),
3993 .writefn
= dbgbcr_write
, .raw_writefn
= raw_write
3997 define_arm_cp_regs(cpu
, dbgregs
);
4000 for (i
= 0; i
< wrps
+ 1; i
++) {
4001 ARMCPRegInfo dbgregs
[] = {
4002 { .name
= "DBGWVR", .state
= ARM_CP_STATE_BOTH
,
4003 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 6,
4005 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwvr
[i
]),
4006 .writefn
= dbgwvr_write
, .raw_writefn
= raw_write
4008 { .name
= "DBGWCR", .state
= ARM_CP_STATE_BOTH
,
4009 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 7,
4011 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwcr
[i
]),
4012 .writefn
= dbgwcr_write
, .raw_writefn
= raw_write
4016 define_arm_cp_regs(cpu
, dbgregs
);
4020 void register_cp_regs_for_features(ARMCPU
*cpu
)
4022 /* Register all the coprocessor registers based on feature bits */
4023 CPUARMState
*env
= &cpu
->env
;
4024 if (arm_feature(env
, ARM_FEATURE_M
)) {
4025 /* M profile has no coprocessor registers */
4029 define_arm_cp_regs(cpu
, cp_reginfo
);
4030 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
4031 /* Must go early as it is full of wildcards that may be
4032 * overridden by later definitions.
4034 define_arm_cp_regs(cpu
, not_v8_cp_reginfo
);
4037 if (arm_feature(env
, ARM_FEATURE_V6
)) {
4038 /* The ID registers all have impdef reset values */
4039 ARMCPRegInfo v6_idregs
[] = {
4040 { .name
= "ID_PFR0", .state
= ARM_CP_STATE_BOTH
,
4041 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
4042 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4043 .resetvalue
= cpu
->id_pfr0
},
4044 { .name
= "ID_PFR1", .state
= ARM_CP_STATE_BOTH
,
4045 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 1,
4046 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4047 .resetvalue
= cpu
->id_pfr1
},
4048 { .name
= "ID_DFR0", .state
= ARM_CP_STATE_BOTH
,
4049 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 2,
4050 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4051 .resetvalue
= cpu
->id_dfr0
},
4052 { .name
= "ID_AFR0", .state
= ARM_CP_STATE_BOTH
,
4053 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 3,
4054 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4055 .resetvalue
= cpu
->id_afr0
},
4056 { .name
= "ID_MMFR0", .state
= ARM_CP_STATE_BOTH
,
4057 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 4,
4058 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4059 .resetvalue
= cpu
->id_mmfr0
},
4060 { .name
= "ID_MMFR1", .state
= ARM_CP_STATE_BOTH
,
4061 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 5,
4062 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4063 .resetvalue
= cpu
->id_mmfr1
},
4064 { .name
= "ID_MMFR2", .state
= ARM_CP_STATE_BOTH
,
4065 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 6,
4066 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4067 .resetvalue
= cpu
->id_mmfr2
},
4068 { .name
= "ID_MMFR3", .state
= ARM_CP_STATE_BOTH
,
4069 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 7,
4070 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4071 .resetvalue
= cpu
->id_mmfr3
},
4072 { .name
= "ID_ISAR0", .state
= ARM_CP_STATE_BOTH
,
4073 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
4074 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4075 .resetvalue
= cpu
->id_isar0
},
4076 { .name
= "ID_ISAR1", .state
= ARM_CP_STATE_BOTH
,
4077 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 1,
4078 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4079 .resetvalue
= cpu
->id_isar1
},
4080 { .name
= "ID_ISAR2", .state
= ARM_CP_STATE_BOTH
,
4081 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
4082 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4083 .resetvalue
= cpu
->id_isar2
},
4084 { .name
= "ID_ISAR3", .state
= ARM_CP_STATE_BOTH
,
4085 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 3,
4086 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4087 .resetvalue
= cpu
->id_isar3
},
4088 { .name
= "ID_ISAR4", .state
= ARM_CP_STATE_BOTH
,
4089 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 4,
4090 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4091 .resetvalue
= cpu
->id_isar4
},
4092 { .name
= "ID_ISAR5", .state
= ARM_CP_STATE_BOTH
,
4093 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 5,
4094 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4095 .resetvalue
= cpu
->id_isar5
},
4096 /* 6..7 are as yet unallocated and must RAZ */
4097 { .name
= "ID_ISAR6", .cp
= 15, .crn
= 0, .crm
= 2,
4098 .opc1
= 0, .opc2
= 6, .access
= PL1_R
, .type
= ARM_CP_CONST
,
4100 { .name
= "ID_ISAR7", .cp
= 15, .crn
= 0, .crm
= 2,
4101 .opc1
= 0, .opc2
= 7, .access
= PL1_R
, .type
= ARM_CP_CONST
,
4105 define_arm_cp_regs(cpu
, v6_idregs
);
4106 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
4108 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
4110 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
4111 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
4113 if (arm_feature(env
, ARM_FEATURE_V7MP
) &&
4114 !arm_feature(env
, ARM_FEATURE_MPU
)) {
4115 define_arm_cp_regs(cpu
, v7mp_cp_reginfo
);
4117 if (arm_feature(env
, ARM_FEATURE_V7
)) {
4118 /* v7 performance monitor control register: same implementor
4119 * field as main ID register, and we implement only the cycle
4122 #ifndef CONFIG_USER_ONLY
4123 ARMCPRegInfo pmcr
= {
4124 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
4126 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
4127 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcr
),
4128 .accessfn
= pmreg_access
, .writefn
= pmcr_write
,
4129 .raw_writefn
= raw_write
,
4131 ARMCPRegInfo pmcr64
= {
4132 .name
= "PMCR_EL0", .state
= ARM_CP_STATE_AA64
,
4133 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 0,
4134 .access
= PL0_RW
, .accessfn
= pmreg_access
,
4136 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
4137 .resetvalue
= cpu
->midr
& 0xff000000,
4138 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
4140 define_one_arm_cp_reg(cpu
, &pmcr
);
4141 define_one_arm_cp_reg(cpu
, &pmcr64
);
4143 ARMCPRegInfo clidr
= {
4144 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
4145 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
4146 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->clidr
4148 define_one_arm_cp_reg(cpu
, &clidr
);
4149 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
4150 define_debug_regs(cpu
);
4152 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
4154 if (arm_feature(env
, ARM_FEATURE_V8
)) {
4155 /* AArch64 ID registers, which all have impdef reset values */
4156 ARMCPRegInfo v8_idregs
[] = {
4157 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
4158 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
4159 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4160 .resetvalue
= cpu
->id_aa64pfr0
},
4161 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
4162 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
4163 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4164 .resetvalue
= cpu
->id_aa64pfr1
},
4165 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
4166 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
4167 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4168 /* We mask out the PMUVer field, because we don't currently
4169 * implement the PMU. Not advertising it prevents the guest
4170 * from trying to use it and getting UNDEFs on registers we
4173 .resetvalue
= cpu
->id_aa64dfr0
& ~0xf00 },
4174 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
4175 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
4176 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4177 .resetvalue
= cpu
->id_aa64dfr1
},
4178 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
4179 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
4180 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4181 .resetvalue
= cpu
->id_aa64afr0
},
4182 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
4183 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
4184 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4185 .resetvalue
= cpu
->id_aa64afr1
},
4186 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
4187 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
4188 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4189 .resetvalue
= cpu
->id_aa64isar0
},
4190 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
4191 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
4192 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4193 .resetvalue
= cpu
->id_aa64isar1
},
4194 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
4195 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
4196 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4197 .resetvalue
= cpu
->id_aa64mmfr0
},
4198 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
4199 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
4200 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4201 .resetvalue
= cpu
->id_aa64mmfr1
},
4202 { .name
= "MVFR0_EL1", .state
= ARM_CP_STATE_AA64
,
4203 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
4204 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4205 .resetvalue
= cpu
->mvfr0
},
4206 { .name
= "MVFR1_EL1", .state
= ARM_CP_STATE_AA64
,
4207 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
4208 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4209 .resetvalue
= cpu
->mvfr1
},
4210 { .name
= "MVFR2_EL1", .state
= ARM_CP_STATE_AA64
,
4211 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
4212 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4213 .resetvalue
= cpu
->mvfr2
},
4216 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
4217 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
4218 !arm_feature(env
, ARM_FEATURE_EL2
)) {
4219 ARMCPRegInfo rvbar
= {
4220 .name
= "RVBAR_EL1", .state
= ARM_CP_STATE_AA64
,
4221 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
4222 .type
= ARM_CP_CONST
, .access
= PL1_R
, .resetvalue
= cpu
->rvbar
4224 define_one_arm_cp_reg(cpu
, &rvbar
);
4226 define_arm_cp_regs(cpu
, v8_idregs
);
4227 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
4229 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
4230 uint64_t vmpidr_def
= mpidr_read_val(env
);
4231 ARMCPRegInfo vpidr_regs
[] = {
4232 { .name
= "VPIDR", .state
= ARM_CP_STATE_AA32
,
4233 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
4234 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
4235 .resetvalue
= cpu
->midr
,
4236 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
4237 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
4238 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
4239 .access
= PL2_RW
, .resetvalue
= cpu
->midr
,
4240 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
4241 { .name
= "VMPIDR", .state
= ARM_CP_STATE_AA32
,
4242 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
4243 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
4244 .resetvalue
= vmpidr_def
,
4245 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
4246 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
4247 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
4249 .resetvalue
= vmpidr_def
,
4250 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
4253 define_arm_cp_regs(cpu
, vpidr_regs
);
4254 define_arm_cp_regs(cpu
, el2_cp_reginfo
);
4255 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
4256 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
4257 ARMCPRegInfo rvbar
= {
4258 .name
= "RVBAR_EL2", .state
= ARM_CP_STATE_AA64
,
4259 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 1,
4260 .type
= ARM_CP_CONST
, .access
= PL2_R
, .resetvalue
= cpu
->rvbar
4262 define_one_arm_cp_reg(cpu
, &rvbar
);
4265 /* If EL2 is missing but higher ELs are enabled, we need to
4266 * register the no_el2 reginfos.
4268 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
4269 /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
4270 * of MIDR_EL1 and MPIDR_EL1.
4272 ARMCPRegInfo vpidr_regs
[] = {
4273 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
4274 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
4275 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
4276 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->midr
,
4277 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
4278 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
4279 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
4280 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
4281 .type
= ARM_CP_NO_RAW
,
4282 .writefn
= arm_cp_write_ignore
, .readfn
= mpidr_read
},
4285 define_arm_cp_regs(cpu
, vpidr_regs
);
4286 define_arm_cp_regs(cpu
, el3_no_el2_cp_reginfo
);
4289 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
4290 define_arm_cp_regs(cpu
, el3_cp_reginfo
);
4291 ARMCPRegInfo rvbar
= {
4292 .name
= "RVBAR_EL3", .state
= ARM_CP_STATE_AA64
,
4293 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 1,
4294 .type
= ARM_CP_CONST
, .access
= PL3_R
, .resetvalue
= cpu
->rvbar
4296 define_one_arm_cp_reg(cpu
, &rvbar
);
4298 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
4299 if (arm_feature(env
, ARM_FEATURE_V6
)) {
4300 /* PMSAv6 not implemented */
4301 assert(arm_feature(env
, ARM_FEATURE_V7
));
4302 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
4303 define_arm_cp_regs(cpu
, pmsav7_cp_reginfo
);
4305 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
4308 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
4309 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
4311 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
4312 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
4314 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
4315 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
4317 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
4318 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
4320 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
4321 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
4323 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
4324 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
4326 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
4327 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
4329 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
4330 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
4332 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
4333 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
4335 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
4336 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
4338 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
4339 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
4341 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
4342 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
4344 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
4345 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
4346 * be read-only (ie write causes UNDEF exception).
4349 ARMCPRegInfo id_pre_v8_midr_cp_reginfo
[] = {
4350 /* Pre-v8 MIDR space.
4351 * Note that the MIDR isn't a simple constant register because
4352 * of the TI925 behaviour where writes to another register can
4353 * cause the MIDR value to change.
4355 * Unimplemented registers in the c15 0 0 0 space default to
4356 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
4357 * and friends override accordingly.
4360 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
4361 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
4362 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
4363 .readfn
= midr_read
,
4364 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
4365 .type
= ARM_CP_OVERRIDE
},
4366 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
4368 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
4369 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4371 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
4372 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4374 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
4375 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4377 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
4378 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4380 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
4381 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4384 ARMCPRegInfo id_v8_midr_cp_reginfo
[] = {
4385 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
4386 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 0,
4387 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
, .resetvalue
= cpu
->midr
,
4388 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
4389 .readfn
= midr_read
},
4390 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
4391 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
4392 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
4393 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
4394 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
4395 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 7,
4396 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
4397 { .name
= "REVIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
4398 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 6,
4399 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->revidr
},
4402 ARMCPRegInfo id_cp_reginfo
[] = {
4403 /* These are common to v8 and pre-v8 */
4405 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
4406 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
4407 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
4408 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
4409 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
4410 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
4411 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
4413 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
4414 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4417 /* TLBTR is specific to VMSA */
4418 ARMCPRegInfo id_tlbtr_reginfo
= {
4420 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
4421 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0,
4423 /* MPUIR is specific to PMSA V6+ */
4424 ARMCPRegInfo id_mpuir_reginfo
= {
4426 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
4427 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4428 .resetvalue
= cpu
->pmsav7_dregion
<< 8
4430 ARMCPRegInfo crn0_wi_reginfo
= {
4431 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
4432 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
4433 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
4435 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
4436 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
4438 /* Register the blanket "writes ignored" value first to cover the
4439 * whole space. Then update the specific ID registers to allow write
4440 * access, so that they ignore writes rather than causing them to
4443 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
4444 for (r
= id_pre_v8_midr_cp_reginfo
;
4445 r
->type
!= ARM_CP_SENTINEL
; r
++) {
4448 for (r
= id_cp_reginfo
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
4451 id_tlbtr_reginfo
.access
= PL1_RW
;
4452 id_tlbtr_reginfo
.access
= PL1_RW
;
4454 if (arm_feature(env
, ARM_FEATURE_V8
)) {
4455 define_arm_cp_regs(cpu
, id_v8_midr_cp_reginfo
);
4457 define_arm_cp_regs(cpu
, id_pre_v8_midr_cp_reginfo
);
4459 define_arm_cp_regs(cpu
, id_cp_reginfo
);
4460 if (!arm_feature(env
, ARM_FEATURE_MPU
)) {
4461 define_one_arm_cp_reg(cpu
, &id_tlbtr_reginfo
);
4462 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
4463 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
4467 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
4468 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
4471 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
4472 ARMCPRegInfo auxcr_reginfo
[] = {
4473 { .name
= "ACTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
4474 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 1,
4475 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
4476 .resetvalue
= cpu
->reset_auxcr
},
4477 { .name
= "ACTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
4478 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 1,
4479 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
4481 { .name
= "ACTLR_EL3", .state
= ARM_CP_STATE_AA64
,
4482 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 1,
4483 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
4487 define_arm_cp_regs(cpu
, auxcr_reginfo
);
4490 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
4491 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
4492 /* 32 bit view is [31:18] 0...0 [43:32]. */
4493 uint32_t cbar32
= (extract64(cpu
->reset_cbar
, 18, 14) << 18)
4494 | extract64(cpu
->reset_cbar
, 32, 12);
4495 ARMCPRegInfo cbar_reginfo
[] = {
4497 .type
= ARM_CP_CONST
,
4498 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
4499 .access
= PL1_R
, .resetvalue
= cpu
->reset_cbar
},
4500 { .name
= "CBAR_EL1", .state
= ARM_CP_STATE_AA64
,
4501 .type
= ARM_CP_CONST
,
4502 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 3, .opc2
= 0,
4503 .access
= PL1_R
, .resetvalue
= cbar32
},
4506 /* We don't implement a r/w 64 bit CBAR currently */
4507 assert(arm_feature(env
, ARM_FEATURE_CBAR_RO
));
4508 define_arm_cp_regs(cpu
, cbar_reginfo
);
4510 ARMCPRegInfo cbar
= {
4512 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
4513 .access
= PL1_R
|PL3_W
, .resetvalue
= cpu
->reset_cbar
,
4514 .fieldoffset
= offsetof(CPUARMState
,
4515 cp15
.c15_config_base_address
)
4517 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
4518 cbar
.access
= PL1_R
;
4519 cbar
.fieldoffset
= 0;
4520 cbar
.type
= ARM_CP_CONST
;
4522 define_one_arm_cp_reg(cpu
, &cbar
);
4526 /* Generic registers whose values depend on the implementation */
4528 ARMCPRegInfo sctlr
= {
4529 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
4530 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
4532 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.sctlr_s
),
4533 offsetof(CPUARMState
, cp15
.sctlr_ns
) },
4534 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
4535 .raw_writefn
= raw_write
,
4537 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
4538 /* Normally we would always end the TB on an SCTLR write, but Linux
4539 * arch/arm/mach-pxa/sleep.S expects two instructions following
4540 * an MMU enable to execute from cache. Imitate this behaviour.
4542 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
4544 define_one_arm_cp_reg(cpu
, &sctlr
);
4548 ARMCPU
*cpu_arm_init(const char *cpu_model
)
4550 return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU
, cpu_model
));
4553 void arm_cpu_register_gdb_regs_for_features(ARMCPU
*cpu
)
4555 CPUState
*cs
= CPU(cpu
);
4556 CPUARMState
*env
= &cpu
->env
;
4558 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
4559 gdb_register_coprocessor(cs
, aarch64_fpu_gdb_get_reg
,
4560 aarch64_fpu_gdb_set_reg
,
4561 34, "aarch64-fpu.xml", 0);
4562 } else if (arm_feature(env
, ARM_FEATURE_NEON
)) {
4563 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
4564 51, "arm-neon.xml", 0);
4565 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
4566 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
4567 35, "arm-vfp3.xml", 0);
4568 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
4569 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
4570 19, "arm-vfp.xml", 0);
4574 /* Sort alphabetically by type name, except for "any". */
4575 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
4577 ObjectClass
*class_a
= (ObjectClass
*)a
;
4578 ObjectClass
*class_b
= (ObjectClass
*)b
;
4579 const char *name_a
, *name_b
;
4581 name_a
= object_class_get_name(class_a
);
4582 name_b
= object_class_get_name(class_b
);
4583 if (strcmp(name_a
, "any-" TYPE_ARM_CPU
) == 0) {
4585 } else if (strcmp(name_b
, "any-" TYPE_ARM_CPU
) == 0) {
4588 return strcmp(name_a
, name_b
);
4592 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
4594 ObjectClass
*oc
= data
;
4595 CPUListState
*s
= user_data
;
4596 const char *typename
;
4599 typename
= object_class_get_name(oc
);
4600 name
= g_strndup(typename
, strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
4601 (*s
->cpu_fprintf
)(s
->file
, " %s\n",
4606 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
4610 .cpu_fprintf
= cpu_fprintf
,
4614 list
= object_class_get_list(TYPE_ARM_CPU
, false);
4615 list
= g_slist_sort(list
, arm_cpu_list_compare
);
4616 (*cpu_fprintf
)(f
, "Available CPUs:\n");
4617 g_slist_foreach(list
, arm_cpu_list_entry
, &s
);
4620 /* The 'host' CPU type is dynamically registered only if KVM is
4621 * enabled, so we have to special-case it here:
4623 (*cpu_fprintf
)(f
, " host (only available in KVM mode)\n");
4627 static void arm_cpu_add_definition(gpointer data
, gpointer user_data
)
4629 ObjectClass
*oc
= data
;
4630 CpuDefinitionInfoList
**cpu_list
= user_data
;
4631 CpuDefinitionInfoList
*entry
;
4632 CpuDefinitionInfo
*info
;
4633 const char *typename
;
4635 typename
= object_class_get_name(oc
);
4636 info
= g_malloc0(sizeof(*info
));
4637 info
->name
= g_strndup(typename
,
4638 strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
4640 entry
= g_malloc0(sizeof(*entry
));
4641 entry
->value
= info
;
4642 entry
->next
= *cpu_list
;
4646 CpuDefinitionInfoList
*arch_query_cpu_definitions(Error
**errp
)
4648 CpuDefinitionInfoList
*cpu_list
= NULL
;
4651 list
= object_class_get_list(TYPE_ARM_CPU
, false);
4652 g_slist_foreach(list
, arm_cpu_add_definition
, &cpu_list
);
4658 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
4659 void *opaque
, int state
, int secstate
,
4660 int crm
, int opc1
, int opc2
)
4662 /* Private utility function for define_one_arm_cp_reg_with_opaque():
4663 * add a single reginfo struct to the hash table.
4665 uint32_t *key
= g_new(uint32_t, 1);
4666 ARMCPRegInfo
*r2
= g_memdup(r
, sizeof(ARMCPRegInfo
));
4667 int is64
= (r
->type
& ARM_CP_64BIT
) ? 1 : 0;
4668 int ns
= (secstate
& ARM_CP_SECSTATE_NS
) ? 1 : 0;
4670 /* Reset the secure state to the specific incoming state. This is
4671 * necessary as the register may have been defined with both states.
4673 r2
->secure
= secstate
;
4675 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
4676 /* Register is banked (using both entries in array).
4677 * Overwriting fieldoffset as the array is only used to define
4678 * banked registers but later only fieldoffset is used.
4680 r2
->fieldoffset
= r
->bank_fieldoffsets
[ns
];
4683 if (state
== ARM_CP_STATE_AA32
) {
4684 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
4685 /* If the register is banked then we don't need to migrate or
4686 * reset the 32-bit instance in certain cases:
4688 * 1) If the register has both 32-bit and 64-bit instances then we
4689 * can count on the 64-bit instance taking care of the
4691 * 2) If ARMv8 is enabled then we can count on a 64-bit version
4692 * taking care of the secure bank. This requires that separate
4693 * 32 and 64-bit definitions are provided.
4695 if ((r
->state
== ARM_CP_STATE_BOTH
&& ns
) ||
4696 (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) && !ns
)) {
4697 r2
->type
|= ARM_CP_ALIAS
;
4699 } else if ((secstate
!= r
->secure
) && !ns
) {
4700 /* The register is not banked so we only want to allow migration of
4701 * the non-secure instance.
4703 r2
->type
|= ARM_CP_ALIAS
;
4706 if (r
->state
== ARM_CP_STATE_BOTH
) {
4707 /* We assume it is a cp15 register if the .cp field is left unset.
4713 #ifdef HOST_WORDS_BIGENDIAN
4714 if (r2
->fieldoffset
) {
4715 r2
->fieldoffset
+= sizeof(uint32_t);
4720 if (state
== ARM_CP_STATE_AA64
) {
4721 /* To allow abbreviation of ARMCPRegInfo
4722 * definitions, we treat cp == 0 as equivalent to
4723 * the value for "standard guest-visible sysreg".
4724 * STATE_BOTH definitions are also always "standard
4725 * sysreg" in their AArch64 view (the .cp value may
4726 * be non-zero for the benefit of the AArch32 view).
4728 if (r
->cp
== 0 || r
->state
== ARM_CP_STATE_BOTH
) {
4729 r2
->cp
= CP_REG_ARM64_SYSREG_CP
;
4731 *key
= ENCODE_AA64_CP_REG(r2
->cp
, r2
->crn
, crm
,
4732 r2
->opc0
, opc1
, opc2
);
4734 *key
= ENCODE_CP_REG(r2
->cp
, is64
, ns
, r2
->crn
, crm
, opc1
, opc2
);
4737 r2
->opaque
= opaque
;
4739 /* reginfo passed to helpers is correct for the actual access,
4740 * and is never ARM_CP_STATE_BOTH:
4743 /* Make sure reginfo passed to helpers for wildcarded regs
4744 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
4749 /* By convention, for wildcarded registers only the first
4750 * entry is used for migration; the others are marked as
4751 * ALIAS so we don't try to transfer the register
4752 * multiple times. Special registers (ie NOP/WFI) are
4753 * never migratable and not even raw-accessible.
4755 if ((r
->type
& ARM_CP_SPECIAL
)) {
4756 r2
->type
|= ARM_CP_NO_RAW
;
4758 if (((r
->crm
== CP_ANY
) && crm
!= 0) ||
4759 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
4760 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
4761 r2
->type
|= ARM_CP_ALIAS
;
4764 /* Check that raw accesses are either forbidden or handled. Note that
4765 * we can't assert this earlier because the setup of fieldoffset for
4766 * banked registers has to be done first.
4768 if (!(r2
->type
& ARM_CP_NO_RAW
)) {
4769 assert(!raw_accessors_invalid(r2
));
4772 /* Overriding of an existing definition must be explicitly
4775 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
4776 ARMCPRegInfo
*oldreg
;
4777 oldreg
= g_hash_table_lookup(cpu
->cp_regs
, key
);
4778 if (oldreg
&& !(oldreg
->type
& ARM_CP_OVERRIDE
)) {
4779 fprintf(stderr
, "Register redefined: cp=%d %d bit "
4780 "crn=%d crm=%d opc1=%d opc2=%d, "
4781 "was %s, now %s\n", r2
->cp
, 32 + 32 * is64
,
4782 r2
->crn
, r2
->crm
, r2
->opc1
, r2
->opc2
,
4783 oldreg
->name
, r2
->name
);
4784 g_assert_not_reached();
4787 g_hash_table_insert(cpu
->cp_regs
, key
, r2
);
4791 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
4792 const ARMCPRegInfo
*r
, void *opaque
)
4794 /* Define implementations of coprocessor registers.
4795 * We store these in a hashtable because typically
4796 * there are less than 150 registers in a space which
4797 * is 16*16*16*8*8 = 262144 in size.
4798 * Wildcarding is supported for the crm, opc1 and opc2 fields.
4799 * If a register is defined twice then the second definition is
4800 * used, so this can be used to define some generic registers and
4801 * then override them with implementation specific variations.
4802 * At least one of the original and the second definition should
4803 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
4804 * against accidental use.
4806 * The state field defines whether the register is to be
4807 * visible in the AArch32 or AArch64 execution state. If the
4808 * state is set to ARM_CP_STATE_BOTH then we synthesise a
4809 * reginfo structure for the AArch32 view, which sees the lower
4810 * 32 bits of the 64 bit register.
4812 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
4813 * be wildcarded. AArch64 registers are always considered to be 64
4814 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
4815 * the register, if any.
4817 int crm
, opc1
, opc2
, state
;
4818 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
4819 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
4820 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
4821 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
4822 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
4823 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
4824 /* 64 bit registers have only CRm and Opc1 fields */
4825 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
4826 /* op0 only exists in the AArch64 encodings */
4827 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
4828 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
4829 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
4830 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
4831 * encodes a minimum access level for the register. We roll this
4832 * runtime check into our general permission check code, so check
4833 * here that the reginfo's specified permissions are strict enough
4834 * to encompass the generic architectural permission check.
4836 if (r
->state
!= ARM_CP_STATE_AA32
) {
4839 case 0: case 1: case 2:
4852 /* unallocated encoding, so not possible */
4860 /* min_EL EL1, secure mode only (we don't check the latter) */
4864 /* broken reginfo with out-of-range opc1 */
4868 /* assert our permissions are not too lax (stricter is fine) */
4869 assert((r
->access
& ~mask
) == 0);
4872 /* Check that the register definition has enough info to handle
4873 * reads and writes if they are permitted.
4875 if (!(r
->type
& (ARM_CP_SPECIAL
|ARM_CP_CONST
))) {
4876 if (r
->access
& PL3_R
) {
4877 assert((r
->fieldoffset
||
4878 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
4881 if (r
->access
& PL3_W
) {
4882 assert((r
->fieldoffset
||
4883 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
4887 /* Bad type field probably means missing sentinel at end of reg list */
4888 assert(cptype_valid(r
->type
));
4889 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
4890 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
4891 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
4892 for (state
= ARM_CP_STATE_AA32
;
4893 state
<= ARM_CP_STATE_AA64
; state
++) {
4894 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
4897 if (state
== ARM_CP_STATE_AA32
) {
4898 /* Under AArch32 CP registers can be common
4899 * (same for secure and non-secure world) or banked.
4901 switch (r
->secure
) {
4902 case ARM_CP_SECSTATE_S
:
4903 case ARM_CP_SECSTATE_NS
:
4904 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
4905 r
->secure
, crm
, opc1
, opc2
);
4908 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
4911 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
4917 /* AArch64 registers get mapped to non-secure instance
4919 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
4929 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
4930 const ARMCPRegInfo
*regs
, void *opaque
)
4932 /* Define a whole list of registers */
4933 const ARMCPRegInfo
*r
;
4934 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
4935 define_one_arm_cp_reg_with_opaque(cpu
, r
, opaque
);
4939 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
4941 return g_hash_table_lookup(cpregs
, &encoded_cp
);
4944 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4947 /* Helper coprocessor write function for write-ignore registers */
4950 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4952 /* Helper coprocessor write function for read-as-zero registers */
4956 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
4958 /* Helper coprocessor reset function for do-nothing-on-reset registers */
4961 static int bad_mode_switch(CPUARMState
*env
, int mode
)
4963 /* Return true if it is not valid for us to switch to
4964 * this CPU mode (ie all the UNPREDICTABLE cases in
4965 * the ARM ARM CPSRWriteByInstr pseudocode).
4968 case ARM_CPU_MODE_USR
:
4969 case ARM_CPU_MODE_SYS
:
4970 case ARM_CPU_MODE_SVC
:
4971 case ARM_CPU_MODE_ABT
:
4972 case ARM_CPU_MODE_UND
:
4973 case ARM_CPU_MODE_IRQ
:
4974 case ARM_CPU_MODE_FIQ
:
4976 case ARM_CPU_MODE_MON
:
4977 return !arm_is_secure(env
);
4983 uint32_t cpsr_read(CPUARMState
*env
)
4986 ZF
= (env
->ZF
== 0);
4987 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
4988 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
4989 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
4990 | ((env
->condexec_bits
& 0xfc) << 8)
4991 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
4994 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
4996 uint32_t changed_daif
;
4998 if (mask
& CPSR_NZCV
) {
4999 env
->ZF
= (~val
) & CPSR_Z
;
5001 env
->CF
= (val
>> 29) & 1;
5002 env
->VF
= (val
<< 3) & 0x80000000;
5005 env
->QF
= ((val
& CPSR_Q
) != 0);
5007 env
->thumb
= ((val
& CPSR_T
) != 0);
5008 if (mask
& CPSR_IT_0_1
) {
5009 env
->condexec_bits
&= ~3;
5010 env
->condexec_bits
|= (val
>> 25) & 3;
5012 if (mask
& CPSR_IT_2_7
) {
5013 env
->condexec_bits
&= 3;
5014 env
->condexec_bits
|= (val
>> 8) & 0xfc;
5016 if (mask
& CPSR_GE
) {
5017 env
->GE
= (val
>> 16) & 0xf;
5020 /* In a V7 implementation that includes the security extensions but does
5021 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
5022 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
5023 * bits respectively.
5025 * In a V8 implementation, it is permitted for privileged software to
5026 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
5028 if (!arm_feature(env
, ARM_FEATURE_V8
) &&
5029 arm_feature(env
, ARM_FEATURE_EL3
) &&
5030 !arm_feature(env
, ARM_FEATURE_EL2
) &&
5031 !arm_is_secure(env
)) {
5033 changed_daif
= (env
->daif
^ val
) & mask
;
5035 if (changed_daif
& CPSR_A
) {
5036 /* Check to see if we are allowed to change the masking of async
5037 * abort exceptions from a non-secure state.
5039 if (!(env
->cp15
.scr_el3
& SCR_AW
)) {
5040 qemu_log_mask(LOG_GUEST_ERROR
,
5041 "Ignoring attempt to switch CPSR_A flag from "
5042 "non-secure world with SCR.AW bit clear\n");
5047 if (changed_daif
& CPSR_F
) {
5048 /* Check to see if we are allowed to change the masking of FIQ
5049 * exceptions from a non-secure state.
5051 if (!(env
->cp15
.scr_el3
& SCR_FW
)) {
5052 qemu_log_mask(LOG_GUEST_ERROR
,
5053 "Ignoring attempt to switch CPSR_F flag from "
5054 "non-secure world with SCR.FW bit clear\n");
5058 /* Check whether non-maskable FIQ (NMFI) support is enabled.
5059 * If this bit is set software is not allowed to mask
5060 * FIQs, but is allowed to set CPSR_F to 0.
5062 if ((A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_NMFI
) &&
5064 qemu_log_mask(LOG_GUEST_ERROR
,
5065 "Ignoring attempt to enable CPSR_F flag "
5066 "(non-maskable FIQ [NMFI] support enabled)\n");
5072 env
->daif
&= ~(CPSR_AIF
& mask
);
5073 env
->daif
|= val
& CPSR_AIF
& mask
;
5075 if ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
) {
5076 if (bad_mode_switch(env
, val
& CPSR_M
)) {
5077 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
5078 * We choose to ignore the attempt and leave the CPSR M field
5083 switch_mode(env
, val
& CPSR_M
);
5086 mask
&= ~CACHED_CPSR_BITS
;
5087 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
5090 /* Sign/zero extend */
5091 uint32_t HELPER(sxtb16
)(uint32_t x
)
5094 res
= (uint16_t)(int8_t)x
;
5095 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
5099 uint32_t HELPER(uxtb16
)(uint32_t x
)
5102 res
= (uint16_t)(uint8_t)x
;
5103 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
5107 uint32_t HELPER(clz
)(uint32_t x
)
5112 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
5116 if (num
== INT_MIN
&& den
== -1)
5121 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
5128 uint32_t HELPER(rbit
)(uint32_t x
)
5133 #if defined(CONFIG_USER_ONLY)
5135 /* These should probably raise undefined insn exceptions. */
5136 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
5138 ARMCPU
*cpu
= arm_env_get_cpu(env
);
5140 cpu_abort(CPU(cpu
), "v7m_msr %d\n", reg
);
5143 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
5145 ARMCPU
*cpu
= arm_env_get_cpu(env
);
5147 cpu_abort(CPU(cpu
), "v7m_mrs %d\n", reg
);
5151 void switch_mode(CPUARMState
*env
, int mode
)
5153 ARMCPU
*cpu
= arm_env_get_cpu(env
);
5155 if (mode
!= ARM_CPU_MODE_USR
) {
5156 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
5160 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
5162 ARMCPU
*cpu
= arm_env_get_cpu(env
);
5164 cpu_abort(CPU(cpu
), "banked r13 write\n");
5167 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
5169 ARMCPU
*cpu
= arm_env_get_cpu(env
);
5171 cpu_abort(CPU(cpu
), "banked r13 read\n");
5175 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
5176 uint32_t cur_el
, bool secure
)
5181 void aarch64_sync_64_to_32(CPUARMState
*env
)
5183 g_assert_not_reached();
5188 /* Map CPU modes onto saved register banks. */
5189 int bank_number(int mode
)
5192 case ARM_CPU_MODE_USR
:
5193 case ARM_CPU_MODE_SYS
:
5195 case ARM_CPU_MODE_SVC
:
5197 case ARM_CPU_MODE_ABT
:
5199 case ARM_CPU_MODE_UND
:
5201 case ARM_CPU_MODE_IRQ
:
5203 case ARM_CPU_MODE_FIQ
:
5205 case ARM_CPU_MODE_HYP
:
5207 case ARM_CPU_MODE_MON
:
5210 g_assert_not_reached();
5213 void switch_mode(CPUARMState
*env
, int mode
)
5218 old_mode
= env
->uncached_cpsr
& CPSR_M
;
5219 if (mode
== old_mode
)
5222 if (old_mode
== ARM_CPU_MODE_FIQ
) {
5223 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
5224 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
5225 } else if (mode
== ARM_CPU_MODE_FIQ
) {
5226 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
5227 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
5230 i
= bank_number(old_mode
);
5231 env
->banked_r13
[i
] = env
->regs
[13];
5232 env
->banked_r14
[i
] = env
->regs
[14];
5233 env
->banked_spsr
[i
] = env
->spsr
;
5235 i
= bank_number(mode
);
5236 env
->regs
[13] = env
->banked_r13
[i
];
5237 env
->regs
[14] = env
->banked_r14
[i
];
5238 env
->spsr
= env
->banked_spsr
[i
];
5241 /* Physical Interrupt Target EL Lookup Table
5243 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
5245 * The below multi-dimensional table is used for looking up the target
5246 * exception level given numerous condition criteria. Specifically, the
5247 * target EL is based on SCR and HCR routing controls as well as the
5248 * currently executing EL and secure state.
5251 * target_el_table[2][2][2][2][2][4]
5252 * | | | | | +--- Current EL
5253 * | | | | +------ Non-secure(0)/Secure(1)
5254 * | | | +--------- HCR mask override
5255 * | | +------------ SCR exec state control
5256 * | +--------------- SCR mask override
5257 * +------------------ 32-bit(0)/64-bit(1) EL3
5259 * The table values are as such:
5263 * The ARM ARM target EL table includes entries indicating that an "exception
5264 * is not taken". The two cases where this is applicable are:
5265 * 1) An exception is taken from EL3 but the SCR does not have the exception
5267 * 2) An exception is taken from EL2 but the HCR does not have the exception
5269 * In these two cases, the below table contain a target of EL1. This value is
5270 * returned as it is expected that the consumer of the table data will check
5271 * for "target EL >= current EL" to ensure the exception is not taken.
5275 * BIT IRQ IMO Non-secure Secure
5276 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
5278 static const int8_t target_el_table
[2][2][2][2][2][4] = {
5279 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
5280 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
5281 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
5282 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
5283 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
5284 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
5285 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
5286 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
5287 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
5288 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},
5289 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },},
5290 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},},
5291 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
5292 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
5293 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
5294 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},},
5298 * Determine the target EL for physical exceptions
5300 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
5301 uint32_t cur_el
, bool secure
)
5303 CPUARMState
*env
= cs
->env_ptr
;
5308 /* Is the highest EL AArch64? */
5309 int is64
= arm_feature(env
, ARM_FEATURE_AARCH64
);
5311 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5312 rw
= ((env
->cp15
.scr_el3
& SCR_RW
) == SCR_RW
);
5314 /* Either EL2 is the highest EL (and so the EL2 register width
5315 * is given by is64); or there is no EL2 or EL3, in which case
5316 * the value of 'rw' does not affect the table lookup anyway.
5323 scr
= ((env
->cp15
.scr_el3
& SCR_IRQ
) == SCR_IRQ
);
5324 hcr
= ((env
->cp15
.hcr_el2
& HCR_IMO
) == HCR_IMO
);
5327 scr
= ((env
->cp15
.scr_el3
& SCR_FIQ
) == SCR_FIQ
);
5328 hcr
= ((env
->cp15
.hcr_el2
& HCR_FMO
) == HCR_FMO
);
5331 scr
= ((env
->cp15
.scr_el3
& SCR_EA
) == SCR_EA
);
5332 hcr
= ((env
->cp15
.hcr_el2
& HCR_AMO
) == HCR_AMO
);
5336 /* If HCR.TGE is set then HCR is treated as being 1 */
5337 hcr
|= ((env
->cp15
.hcr_el2
& HCR_TGE
) == HCR_TGE
);
5339 /* Perform a table-lookup for the target EL given the current state */
5340 target_el
= target_el_table
[is64
][scr
][rw
][hcr
][secure
][cur_el
];
5342 assert(target_el
> 0);
5347 static void v7m_push(CPUARMState
*env
, uint32_t val
)
5349 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
5352 stl_phys(cs
->as
, env
->regs
[13], val
);
5355 static uint32_t v7m_pop(CPUARMState
*env
)
5357 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
5360 val
= ldl_phys(cs
->as
, env
->regs
[13]);
5365 /* Switch to V7M main or process stack pointer. */
5366 static void switch_v7m_sp(CPUARMState
*env
, int process
)
5369 if (env
->v7m
.current_sp
!= process
) {
5370 tmp
= env
->v7m
.other_sp
;
5371 env
->v7m
.other_sp
= env
->regs
[13];
5372 env
->regs
[13] = tmp
;
5373 env
->v7m
.current_sp
= process
;
5377 static void do_v7m_exception_exit(CPUARMState
*env
)
5382 type
= env
->regs
[15];
5383 if (env
->v7m
.exception
!= 0)
5384 armv7m_nvic_complete_irq(env
->nvic
, env
->v7m
.exception
);
5386 /* Switch to the target stack. */
5387 switch_v7m_sp(env
, (type
& 4) != 0);
5388 /* Pop registers. */
5389 env
->regs
[0] = v7m_pop(env
);
5390 env
->regs
[1] = v7m_pop(env
);
5391 env
->regs
[2] = v7m_pop(env
);
5392 env
->regs
[3] = v7m_pop(env
);
5393 env
->regs
[12] = v7m_pop(env
);
5394 env
->regs
[14] = v7m_pop(env
);
5395 env
->regs
[15] = v7m_pop(env
);
5396 if (env
->regs
[15] & 1) {
5397 qemu_log_mask(LOG_GUEST_ERROR
,
5398 "M profile return from interrupt with misaligned "
5399 "PC is UNPREDICTABLE\n");
5400 /* Actual hardware seems to ignore the lsbit, and there are several
5401 * RTOSes out there which incorrectly assume the r15 in the stack
5402 * frame should be a Thumb-style "lsbit indicates ARM/Thumb" value.
5404 env
->regs
[15] &= ~1U;
5406 xpsr
= v7m_pop(env
);
5407 xpsr_write(env
, xpsr
, 0xfffffdff);
5408 /* Undo stack alignment. */
5411 /* ??? The exception return type specifies Thread/Handler mode. However
5412 this is also implied by the xPSR value. Not sure what to do
5413 if there is a mismatch. */
5414 /* ??? Likewise for mismatches between the CONTROL register and the stack
5418 void arm_v7m_cpu_do_interrupt(CPUState
*cs
)
5420 ARMCPU
*cpu
= ARM_CPU(cs
);
5421 CPUARMState
*env
= &cpu
->env
;
5422 uint32_t xpsr
= xpsr_read(env
);
5426 arm_log_exception(cs
->exception_index
);
5429 if (env
->v7m
.current_sp
)
5431 if (env
->v7m
.exception
== 0)
5434 /* For exceptions we just mark as pending on the NVIC, and let that
5436 /* TODO: Need to escalate if the current priority is higher than the
5437 one we're raising. */
5438 switch (cs
->exception_index
) {
5440 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
);
5443 /* The PC already points to the next instruction. */
5444 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SVC
);
5446 case EXCP_PREFETCH_ABORT
:
5447 case EXCP_DATA_ABORT
:
5448 /* TODO: if we implemented the MPU registers, this is where we
5449 * should set the MMFAR, etc from exception.fsr and exception.vaddress.
5451 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
);
5454 if (semihosting_enabled()) {
5456 nr
= arm_lduw_code(env
, env
->regs
[15], env
->bswap_code
) & 0xff;
5459 qemu_log_mask(CPU_LOG_INT
,
5460 "...handling as semihosting call 0x%x\n",
5462 env
->regs
[0] = do_arm_semihosting(env
);
5466 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_DEBUG
);
5469 env
->v7m
.exception
= armv7m_nvic_acknowledge_irq(env
->nvic
);
5471 case EXCP_EXCEPTION_EXIT
:
5472 do_v7m_exception_exit(env
);
5475 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
5476 return; /* Never happens. Keep compiler happy. */
5479 /* Align stack pointer. */
5480 /* ??? Should only do this if Configuration Control Register
5481 STACKALIGN bit is set. */
5482 if (env
->regs
[13] & 4) {
5486 /* Switch to the handler mode. */
5487 v7m_push(env
, xpsr
);
5488 v7m_push(env
, env
->regs
[15]);
5489 v7m_push(env
, env
->regs
[14]);
5490 v7m_push(env
, env
->regs
[12]);
5491 v7m_push(env
, env
->regs
[3]);
5492 v7m_push(env
, env
->regs
[2]);
5493 v7m_push(env
, env
->regs
[1]);
5494 v7m_push(env
, env
->regs
[0]);
5495 switch_v7m_sp(env
, 0);
5497 env
->condexec_bits
= 0;
5499 addr
= ldl_phys(cs
->as
, env
->v7m
.vecbase
+ env
->v7m
.exception
* 4);
5500 env
->regs
[15] = addr
& 0xfffffffe;
5501 env
->thumb
= addr
& 1;
5504 /* Function used to synchronize QEMU's AArch64 register set with AArch32
5505 * register set. This is necessary when switching between AArch32 and AArch64
5508 void aarch64_sync_32_to_64(CPUARMState
*env
)
5511 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
5513 /* We can blanket copy R[0:7] to X[0:7] */
5514 for (i
= 0; i
< 8; i
++) {
5515 env
->xregs
[i
] = env
->regs
[i
];
5518 /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
5519 * Otherwise, they come from the banked user regs.
5521 if (mode
== ARM_CPU_MODE_FIQ
) {
5522 for (i
= 8; i
< 13; i
++) {
5523 env
->xregs
[i
] = env
->usr_regs
[i
- 8];
5526 for (i
= 8; i
< 13; i
++) {
5527 env
->xregs
[i
] = env
->regs
[i
];
5531 /* Registers x13-x23 are the various mode SP and FP registers. Registers
5532 * r13 and r14 are only copied if we are in that mode, otherwise we copy
5533 * from the mode banked register.
5535 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
5536 env
->xregs
[13] = env
->regs
[13];
5537 env
->xregs
[14] = env
->regs
[14];
5539 env
->xregs
[13] = env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)];
5540 /* HYP is an exception in that it is copied from r14 */
5541 if (mode
== ARM_CPU_MODE_HYP
) {
5542 env
->xregs
[14] = env
->regs
[14];
5544 env
->xregs
[14] = env
->banked_r14
[bank_number(ARM_CPU_MODE_USR
)];
5548 if (mode
== ARM_CPU_MODE_HYP
) {
5549 env
->xregs
[15] = env
->regs
[13];
5551 env
->xregs
[15] = env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)];
5554 if (mode
== ARM_CPU_MODE_IRQ
) {
5555 env
->xregs
[16] = env
->regs
[14];
5556 env
->xregs
[17] = env
->regs
[13];
5558 env
->xregs
[16] = env
->banked_r14
[bank_number(ARM_CPU_MODE_IRQ
)];
5559 env
->xregs
[17] = env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)];
5562 if (mode
== ARM_CPU_MODE_SVC
) {
5563 env
->xregs
[18] = env
->regs
[14];
5564 env
->xregs
[19] = env
->regs
[13];
5566 env
->xregs
[18] = env
->banked_r14
[bank_number(ARM_CPU_MODE_SVC
)];
5567 env
->xregs
[19] = env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)];
5570 if (mode
== ARM_CPU_MODE_ABT
) {
5571 env
->xregs
[20] = env
->regs
[14];
5572 env
->xregs
[21] = env
->regs
[13];
5574 env
->xregs
[20] = env
->banked_r14
[bank_number(ARM_CPU_MODE_ABT
)];
5575 env
->xregs
[21] = env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)];
5578 if (mode
== ARM_CPU_MODE_UND
) {
5579 env
->xregs
[22] = env
->regs
[14];
5580 env
->xregs
[23] = env
->regs
[13];
5582 env
->xregs
[22] = env
->banked_r14
[bank_number(ARM_CPU_MODE_UND
)];
5583 env
->xregs
[23] = env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)];
5586 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
5587 * mode, then we can copy from r8-r14. Otherwise, we copy from the
5588 * FIQ bank for r8-r14.
5590 if (mode
== ARM_CPU_MODE_FIQ
) {
5591 for (i
= 24; i
< 31; i
++) {
5592 env
->xregs
[i
] = env
->regs
[i
- 16]; /* X[24:30] <- R[8:14] */
5595 for (i
= 24; i
< 29; i
++) {
5596 env
->xregs
[i
] = env
->fiq_regs
[i
- 24];
5598 env
->xregs
[29] = env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)];
5599 env
->xregs
[30] = env
->banked_r14
[bank_number(ARM_CPU_MODE_FIQ
)];
5602 env
->pc
= env
->regs
[15];
5605 /* Function used to synchronize QEMU's AArch32 register set with AArch64
5606 * register set. This is necessary when switching between AArch32 and AArch64
5609 void aarch64_sync_64_to_32(CPUARMState
*env
)
5612 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
5614 /* We can blanket copy X[0:7] to R[0:7] */
5615 for (i
= 0; i
< 8; i
++) {
5616 env
->regs
[i
] = env
->xregs
[i
];
5619 /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
5620 * Otherwise, we copy x8-x12 into the banked user regs.
5622 if (mode
== ARM_CPU_MODE_FIQ
) {
5623 for (i
= 8; i
< 13; i
++) {
5624 env
->usr_regs
[i
- 8] = env
->xregs
[i
];
5627 for (i
= 8; i
< 13; i
++) {
5628 env
->regs
[i
] = env
->xregs
[i
];
5632 /* Registers r13 & r14 depend on the current mode.
5633 * If we are in a given mode, we copy the corresponding x registers to r13
5634 * and r14. Otherwise, we copy the x register to the banked r13 and r14
5637 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
5638 env
->regs
[13] = env
->xregs
[13];
5639 env
->regs
[14] = env
->xregs
[14];
5641 env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[13];
5643 /* HYP is an exception in that it does not have its own banked r14 but
5644 * shares the USR r14
5646 if (mode
== ARM_CPU_MODE_HYP
) {
5647 env
->regs
[14] = env
->xregs
[14];
5649 env
->banked_r14
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[14];
5653 if (mode
== ARM_CPU_MODE_HYP
) {
5654 env
->regs
[13] = env
->xregs
[15];
5656 env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)] = env
->xregs
[15];
5659 if (mode
== ARM_CPU_MODE_IRQ
) {
5660 env
->regs
[14] = env
->xregs
[16];
5661 env
->regs
[13] = env
->xregs
[17];
5663 env
->banked_r14
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[16];
5664 env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[17];
5667 if (mode
== ARM_CPU_MODE_SVC
) {
5668 env
->regs
[14] = env
->xregs
[18];
5669 env
->regs
[13] = env
->xregs
[19];
5671 env
->banked_r14
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[18];
5672 env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[19];
5675 if (mode
== ARM_CPU_MODE_ABT
) {
5676 env
->regs
[14] = env
->xregs
[20];
5677 env
->regs
[13] = env
->xregs
[21];
5679 env
->banked_r14
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[20];
5680 env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[21];
5683 if (mode
== ARM_CPU_MODE_UND
) {
5684 env
->regs
[14] = env
->xregs
[22];
5685 env
->regs
[13] = env
->xregs
[23];
5687 env
->banked_r14
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[22];
5688 env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[23];
5691 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
5692 * mode, then we can copy to r8-r14. Otherwise, we copy to the
5693 * FIQ bank for r8-r14.
5695 if (mode
== ARM_CPU_MODE_FIQ
) {
5696 for (i
= 24; i
< 31; i
++) {
5697 env
->regs
[i
- 16] = env
->xregs
[i
]; /* X[24:30] -> R[8:14] */
5700 for (i
= 24; i
< 29; i
++) {
5701 env
->fiq_regs
[i
- 24] = env
->xregs
[i
];
5703 env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[29];
5704 env
->banked_r14
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[30];
5707 env
->regs
[15] = env
->pc
;
5710 /* Handle a CPU exception. */
5711 void arm_cpu_do_interrupt(CPUState
*cs
)
5713 ARMCPU
*cpu
= ARM_CPU(cs
);
5714 CPUARMState
*env
= &cpu
->env
;
5723 arm_log_exception(cs
->exception_index
);
5725 if (arm_is_psci_call(cpu
, cs
->exception_index
)) {
5726 arm_handle_psci_call(cpu
);
5727 qemu_log_mask(CPU_LOG_INT
, "...handled as PSCI call\n");
5731 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
5732 switch (env
->exception
.syndrome
>> ARM_EL_EC_SHIFT
) {
5734 case EC_BREAKPOINT_SAME_EL
:
5738 case EC_WATCHPOINT_SAME_EL
:
5744 case EC_VECTORCATCH
:
5753 env
->cp15
.mdscr_el1
= deposit64(env
->cp15
.mdscr_el1
, 2, 4, moe
);
5756 /* TODO: Vectored interrupt controller. */
5757 switch (cs
->exception_index
) {
5759 new_mode
= ARM_CPU_MODE_UND
;
5768 if (semihosting_enabled()) {
5769 /* Check for semihosting interrupt. */
5771 mask
= arm_lduw_code(env
, env
->regs
[15] - 2, env
->bswap_code
)
5774 mask
= arm_ldl_code(env
, env
->regs
[15] - 4, env
->bswap_code
)
5777 /* Only intercept calls from privileged modes, to provide some
5778 semblance of security. */
5779 if (((mask
== 0x123456 && !env
->thumb
)
5780 || (mask
== 0xab && env
->thumb
))
5781 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
5782 qemu_log_mask(CPU_LOG_INT
,
5783 "...handling as semihosting call 0x%x\n",
5785 env
->regs
[0] = do_arm_semihosting(env
);
5789 new_mode
= ARM_CPU_MODE_SVC
;
5792 /* The PC already points to the next instruction. */
5796 /* See if this is a semihosting syscall. */
5797 if (env
->thumb
&& semihosting_enabled()) {
5798 mask
= arm_lduw_code(env
, env
->regs
[15], env
->bswap_code
) & 0xff;
5800 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
5802 qemu_log_mask(CPU_LOG_INT
,
5803 "...handling as semihosting call 0x%x\n",
5805 env
->regs
[0] = do_arm_semihosting(env
);
5809 env
->exception
.fsr
= 2;
5810 /* Fall through to prefetch abort. */
5811 case EXCP_PREFETCH_ABORT
:
5812 A32_BANKED_CURRENT_REG_SET(env
, ifsr
, env
->exception
.fsr
);
5813 A32_BANKED_CURRENT_REG_SET(env
, ifar
, env
->exception
.vaddress
);
5814 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
5815 env
->exception
.fsr
, (uint32_t)env
->exception
.vaddress
);
5816 new_mode
= ARM_CPU_MODE_ABT
;
5818 mask
= CPSR_A
| CPSR_I
;
5821 case EXCP_DATA_ABORT
:
5822 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
5823 A32_BANKED_CURRENT_REG_SET(env
, dfar
, env
->exception
.vaddress
);
5824 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
5826 (uint32_t)env
->exception
.vaddress
);
5827 new_mode
= ARM_CPU_MODE_ABT
;
5829 mask
= CPSR_A
| CPSR_I
;
5833 new_mode
= ARM_CPU_MODE_IRQ
;
5835 /* Disable IRQ and imprecise data aborts. */
5836 mask
= CPSR_A
| CPSR_I
;
5838 if (env
->cp15
.scr_el3
& SCR_IRQ
) {
5839 /* IRQ routed to monitor mode */
5840 new_mode
= ARM_CPU_MODE_MON
;
5845 new_mode
= ARM_CPU_MODE_FIQ
;
5847 /* Disable FIQ, IRQ and imprecise data aborts. */
5848 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
5849 if (env
->cp15
.scr_el3
& SCR_FIQ
) {
5850 /* FIQ routed to monitor mode */
5851 new_mode
= ARM_CPU_MODE_MON
;
5856 new_mode
= ARM_CPU_MODE_MON
;
5858 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
5862 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
5863 return; /* Never happens. Keep compiler happy. */
5866 if (new_mode
== ARM_CPU_MODE_MON
) {
5867 addr
+= env
->cp15
.mvbar
;
5868 } else if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
5869 /* High vectors. When enabled, base address cannot be remapped. */
5872 /* ARM v7 architectures provide a vector base address register to remap
5873 * the interrupt vector table.
5874 * This register is only followed in non-monitor mode, and is banked.
5875 * Note: only bits 31:5 are valid.
5877 addr
+= A32_BANKED_CURRENT_REG_GET(env
, vbar
);
5880 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
5881 env
->cp15
.scr_el3
&= ~SCR_NS
;
5884 switch_mode (env
, new_mode
);
5885 /* For exceptions taken to AArch32 we must clear the SS bit in both
5886 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
5888 env
->uncached_cpsr
&= ~PSTATE_SS
;
5889 env
->spsr
= cpsr_read(env
);
5890 /* Clear IT bits. */
5891 env
->condexec_bits
= 0;
5892 /* Switch to the new mode, and to the correct instruction set. */
5893 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
5895 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
5896 * and we should just guard the thumb mode on V4 */
5897 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
5898 env
->thumb
= (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_TE
) != 0;
5900 env
->regs
[14] = env
->regs
[15] + offset
;
5901 env
->regs
[15] = addr
;
5902 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
5906 /* Return the exception level which controls this address translation regime */
5907 static inline uint32_t regime_el(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
5910 case ARMMMUIdx_S2NS
:
5911 case ARMMMUIdx_S1E2
:
5913 case ARMMMUIdx_S1E3
:
5915 case ARMMMUIdx_S1SE0
:
5916 return arm_el_is_aa64(env
, 3) ? 1 : 3;
5917 case ARMMMUIdx_S1SE1
:
5918 case ARMMMUIdx_S1NSE0
:
5919 case ARMMMUIdx_S1NSE1
:
5922 g_assert_not_reached();
5926 /* Return true if this address translation regime is secure */
5927 static inline bool regime_is_secure(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
5930 case ARMMMUIdx_S12NSE0
:
5931 case ARMMMUIdx_S12NSE1
:
5932 case ARMMMUIdx_S1NSE0
:
5933 case ARMMMUIdx_S1NSE1
:
5934 case ARMMMUIdx_S1E2
:
5935 case ARMMMUIdx_S2NS
:
5937 case ARMMMUIdx_S1E3
:
5938 case ARMMMUIdx_S1SE0
:
5939 case ARMMMUIdx_S1SE1
:
5942 g_assert_not_reached();
5946 /* Return the SCTLR value which controls this address translation regime */
5947 static inline uint32_t regime_sctlr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
5949 return env
->cp15
.sctlr_el
[regime_el(env
, mmu_idx
)];
5952 /* Return true if the specified stage of address translation is disabled */
5953 static inline bool regime_translation_disabled(CPUARMState
*env
,
5956 if (mmu_idx
== ARMMMUIdx_S2NS
) {
5957 return (env
->cp15
.hcr_el2
& HCR_VM
) == 0;
5959 return (regime_sctlr(env
, mmu_idx
) & SCTLR_M
) == 0;
5962 /* Return the TCR controlling this translation regime */
5963 static inline TCR
*regime_tcr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
5965 if (mmu_idx
== ARMMMUIdx_S2NS
) {
5966 return &env
->cp15
.vtcr_el2
;
5968 return &env
->cp15
.tcr_el
[regime_el(env
, mmu_idx
)];
5971 /* Return the TTBR associated with this translation regime */
5972 static inline uint64_t regime_ttbr(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
5975 if (mmu_idx
== ARMMMUIdx_S2NS
) {
5976 return env
->cp15
.vttbr_el2
;
5979 return env
->cp15
.ttbr0_el
[regime_el(env
, mmu_idx
)];
5981 return env
->cp15
.ttbr1_el
[regime_el(env
, mmu_idx
)];
5985 /* Return true if the translation regime is using LPAE format page tables */
5986 static inline bool regime_using_lpae_format(CPUARMState
*env
,
5989 int el
= regime_el(env
, mmu_idx
);
5990 if (el
== 2 || arm_el_is_aa64(env
, el
)) {
5993 if (arm_feature(env
, ARM_FEATURE_LPAE
)
5994 && (regime_tcr(env
, mmu_idx
)->raw_tcr
& TTBCR_EAE
)) {
6000 /* Returns true if the stage 1 translation regime is using LPAE format page
6001 * tables. Used when raising alignment exceptions, whose FSR changes depending
6002 * on whether the long or short descriptor format is in use. */
6003 bool arm_s1_regime_using_lpae_format(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
6005 if (mmu_idx
== ARMMMUIdx_S12NSE0
|| mmu_idx
== ARMMMUIdx_S12NSE1
) {
6006 mmu_idx
+= ARMMMUIdx_S1NSE0
;
6009 return regime_using_lpae_format(env
, mmu_idx
);
6012 static inline bool regime_is_user(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
6015 case ARMMMUIdx_S1SE0
:
6016 case ARMMMUIdx_S1NSE0
:
6020 case ARMMMUIdx_S12NSE0
:
6021 case ARMMMUIdx_S12NSE1
:
6022 g_assert_not_reached();
6026 /* Translate section/page access permissions to page
6027 * R/W protection flags
6030 * @mmu_idx: MMU index indicating required translation regime
6031 * @ap: The 3-bit access permissions (AP[2:0])
6032 * @domain_prot: The 2-bit domain access permissions
6034 static inline int ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
6035 int ap
, int domain_prot
)
6037 bool is_user
= regime_is_user(env
, mmu_idx
);
6039 if (domain_prot
== 3) {
6040 return PAGE_READ
| PAGE_WRITE
;
6045 if (arm_feature(env
, ARM_FEATURE_V7
)) {
6048 switch (regime_sctlr(env
, mmu_idx
) & (SCTLR_S
| SCTLR_R
)) {
6050 return is_user
? 0 : PAGE_READ
;
6057 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
6062 return PAGE_READ
| PAGE_WRITE
;
6065 return PAGE_READ
| PAGE_WRITE
;
6066 case 4: /* Reserved. */
6069 return is_user
? 0 : PAGE_READ
;
6073 if (!arm_feature(env
, ARM_FEATURE_V6K
)) {
6078 g_assert_not_reached();
6082 /* Translate section/page access permissions to page
6083 * R/W protection flags.
6085 * @ap: The 2-bit simple AP (AP[2:1])
6086 * @is_user: TRUE if accessing from PL0
6088 static inline int simple_ap_to_rw_prot_is_user(int ap
, bool is_user
)
6092 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
6094 return PAGE_READ
| PAGE_WRITE
;
6096 return is_user
? 0 : PAGE_READ
;
6100 g_assert_not_reached();
6105 simple_ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, int ap
)
6107 return simple_ap_to_rw_prot_is_user(ap
, regime_is_user(env
, mmu_idx
));
6110 /* Translate S2 section/page access permissions to protection flags
6113 * @s2ap: The 2-bit stage2 access permissions (S2AP)
6114 * @xn: XN (execute-never) bit
6116 static int get_S2prot(CPUARMState
*env
, int s2ap
, int xn
)
6132 /* Translate section/page access permissions to protection flags
6135 * @mmu_idx: MMU index indicating required translation regime
6136 * @is_aa64: TRUE if AArch64
6137 * @ap: The 2-bit simple AP (AP[2:1])
6138 * @ns: NS (non-secure) bit
6139 * @xn: XN (execute-never) bit
6140 * @pxn: PXN (privileged execute-never) bit
6142 static int get_S1prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, bool is_aa64
,
6143 int ap
, int ns
, int xn
, int pxn
)
6145 bool is_user
= regime_is_user(env
, mmu_idx
);
6146 int prot_rw
, user_rw
;
6150 assert(mmu_idx
!= ARMMMUIdx_S2NS
);
6152 user_rw
= simple_ap_to_rw_prot_is_user(ap
, true);
6156 prot_rw
= simple_ap_to_rw_prot_is_user(ap
, false);
6159 if (ns
&& arm_is_secure(env
) && (env
->cp15
.scr_el3
& SCR_SIF
)) {
6163 /* TODO have_wxn should be replaced with
6164 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
6165 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
6166 * compatible processors have EL2, which is required for [U]WXN.
6168 have_wxn
= arm_feature(env
, ARM_FEATURE_LPAE
);
6171 wxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_WXN
;
6175 switch (regime_el(env
, mmu_idx
)) {
6178 xn
= pxn
|| (user_rw
& PAGE_WRITE
);
6185 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
6186 switch (regime_el(env
, mmu_idx
)) {
6190 xn
= xn
|| !(user_rw
& PAGE_READ
);
6194 uwxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_UWXN
;
6196 xn
= xn
|| !(prot_rw
& PAGE_READ
) || pxn
||
6197 (uwxn
&& (user_rw
& PAGE_WRITE
));
6207 if (xn
|| (wxn
&& (prot_rw
& PAGE_WRITE
))) {
6210 return prot_rw
| PAGE_EXEC
;
6213 static bool get_level1_table_address(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
6214 uint32_t *table
, uint32_t address
)
6216 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
6217 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
6219 if (address
& tcr
->mask
) {
6220 if (tcr
->raw_tcr
& TTBCR_PD1
) {
6221 /* Translation table walk disabled for TTBR1 */
6224 *table
= regime_ttbr(env
, mmu_idx
, 1) & 0xffffc000;
6226 if (tcr
->raw_tcr
& TTBCR_PD0
) {
6227 /* Translation table walk disabled for TTBR0 */
6230 *table
= regime_ttbr(env
, mmu_idx
, 0) & tcr
->base_mask
;
6232 *table
|= (address
>> 18) & 0x3ffc;
6236 /* Translate a S1 pagetable walk through S2 if needed. */
6237 static hwaddr
S1_ptw_translate(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
6238 hwaddr addr
, MemTxAttrs txattrs
,
6240 ARMMMUFaultInfo
*fi
)
6242 if ((mmu_idx
== ARMMMUIdx_S1NSE0
|| mmu_idx
== ARMMMUIdx_S1NSE1
) &&
6243 !regime_translation_disabled(env
, ARMMMUIdx_S2NS
)) {
6244 target_ulong s2size
;
6249 ret
= get_phys_addr_lpae(env
, addr
, 0, ARMMMUIdx_S2NS
, &s2pa
,
6250 &txattrs
, &s2prot
, &s2size
, fsr
, fi
);
6262 /* All loads done in the course of a page table walk go through here.
6263 * TODO: rather than ignoring errors from physical memory reads (which
6264 * are external aborts in ARM terminology) we should propagate this
6265 * error out so that we can turn it into a Data Abort if this walk
6266 * was being done for a CPU load/store or an address translation instruction
6267 * (but not if it was for a debug access).
6269 static uint32_t arm_ldl_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
,
6270 ARMMMUIdx mmu_idx
, uint32_t *fsr
,
6271 ARMMMUFaultInfo
*fi
)
6273 ARMCPU
*cpu
= ARM_CPU(cs
);
6274 CPUARMState
*env
= &cpu
->env
;
6275 MemTxAttrs attrs
= {};
6278 attrs
.secure
= is_secure
;
6279 as
= arm_addressspace(cs
, attrs
);
6280 addr
= S1_ptw_translate(env
, mmu_idx
, addr
, attrs
, fsr
, fi
);
6284 return address_space_ldl(as
, addr
, attrs
, NULL
);
6287 static uint64_t arm_ldq_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
,
6288 ARMMMUIdx mmu_idx
, uint32_t *fsr
,
6289 ARMMMUFaultInfo
*fi
)
6291 ARMCPU
*cpu
= ARM_CPU(cs
);
6292 CPUARMState
*env
= &cpu
->env
;
6293 MemTxAttrs attrs
= {};
6296 attrs
.secure
= is_secure
;
6297 as
= arm_addressspace(cs
, attrs
);
6298 addr
= S1_ptw_translate(env
, mmu_idx
, addr
, attrs
, fsr
, fi
);
6302 return address_space_ldq(as
, addr
, attrs
, NULL
);
6305 static bool get_phys_addr_v5(CPUARMState
*env
, uint32_t address
,
6306 int access_type
, ARMMMUIdx mmu_idx
,
6307 hwaddr
*phys_ptr
, int *prot
,
6308 target_ulong
*page_size
, uint32_t *fsr
,
6309 ARMMMUFaultInfo
*fi
)
6311 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
6322 /* Pagetable walk. */
6323 /* Lookup l1 descriptor. */
6324 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
6325 /* Section translation fault if page walk is disabled by PD0 or PD1 */
6329 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
6332 domain
= (desc
>> 5) & 0x0f;
6333 if (regime_el(env
, mmu_idx
) == 1) {
6334 dacr
= env
->cp15
.dacr_ns
;
6336 dacr
= env
->cp15
.dacr_s
;
6338 domain_prot
= (dacr
>> (domain
* 2)) & 3;
6340 /* Section translation fault. */
6344 if (domain_prot
== 0 || domain_prot
== 2) {
6346 code
= 9; /* Section domain fault. */
6348 code
= 11; /* Page domain fault. */
6353 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
6354 ap
= (desc
>> 10) & 3;
6356 *page_size
= 1024 * 1024;
6358 /* Lookup l2 entry. */
6360 /* Coarse pagetable. */
6361 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
6363 /* Fine pagetable. */
6364 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
6366 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
6369 case 0: /* Page translation fault. */
6372 case 1: /* 64k page. */
6373 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
6374 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
6375 *page_size
= 0x10000;
6377 case 2: /* 4k page. */
6378 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
6379 ap
= (desc
>> (4 + ((address
>> 9) & 6))) & 3;
6380 *page_size
= 0x1000;
6382 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
6384 /* ARMv6/XScale extended small page format */
6385 if (arm_feature(env
, ARM_FEATURE_XSCALE
)
6386 || arm_feature(env
, ARM_FEATURE_V6
)) {
6387 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
6388 *page_size
= 0x1000;
6390 /* UNPREDICTABLE in ARMv5; we choose to take a
6391 * page translation fault.
6397 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
6400 ap
= (desc
>> 4) & 3;
6403 /* Never happens, but compiler isn't smart enough to tell. */
6408 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
6409 *prot
|= *prot
? PAGE_EXEC
: 0;
6410 if (!(*prot
& (1 << access_type
))) {
6411 /* Access permission fault. */
6414 *phys_ptr
= phys_addr
;
6417 *fsr
= code
| (domain
<< 4);
6421 static bool get_phys_addr_v6(CPUARMState
*env
, uint32_t address
,
6422 int access_type
, ARMMMUIdx mmu_idx
,
6423 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
6424 target_ulong
*page_size
, uint32_t *fsr
,
6425 ARMMMUFaultInfo
*fi
)
6427 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
6441 /* Pagetable walk. */
6442 /* Lookup l1 descriptor. */
6443 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
6444 /* Section translation fault if page walk is disabled by PD0 or PD1 */
6448 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
6451 if (type
== 0 || (type
== 3 && !arm_feature(env
, ARM_FEATURE_PXN
))) {
6452 /* Section translation fault, or attempt to use the encoding
6453 * which is Reserved on implementations without PXN.
6458 if ((type
== 1) || !(desc
& (1 << 18))) {
6459 /* Page or Section. */
6460 domain
= (desc
>> 5) & 0x0f;
6462 if (regime_el(env
, mmu_idx
) == 1) {
6463 dacr
= env
->cp15
.dacr_ns
;
6465 dacr
= env
->cp15
.dacr_s
;
6467 domain_prot
= (dacr
>> (domain
* 2)) & 3;
6468 if (domain_prot
== 0 || domain_prot
== 2) {
6470 code
= 9; /* Section domain fault. */
6472 code
= 11; /* Page domain fault. */
6477 if (desc
& (1 << 18)) {
6479 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
6480 phys_addr
|= (uint64_t)extract32(desc
, 20, 4) << 32;
6481 phys_addr
|= (uint64_t)extract32(desc
, 5, 4) << 36;
6482 *page_size
= 0x1000000;
6485 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
6486 *page_size
= 0x100000;
6488 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
6489 xn
= desc
& (1 << 4);
6492 ns
= extract32(desc
, 19, 1);
6494 if (arm_feature(env
, ARM_FEATURE_PXN
)) {
6495 pxn
= (desc
>> 2) & 1;
6497 ns
= extract32(desc
, 3, 1);
6498 /* Lookup l2 entry. */
6499 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
6500 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
6502 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
6504 case 0: /* Page translation fault. */
6507 case 1: /* 64k page. */
6508 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
6509 xn
= desc
& (1 << 15);
6510 *page_size
= 0x10000;
6512 case 2: case 3: /* 4k page. */
6513 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
6515 *page_size
= 0x1000;
6518 /* Never happens, but compiler isn't smart enough to tell. */
6523 if (domain_prot
== 3) {
6524 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
6526 if (pxn
&& !regime_is_user(env
, mmu_idx
)) {
6529 if (xn
&& access_type
== 2)
6532 if (arm_feature(env
, ARM_FEATURE_V6K
) &&
6533 (regime_sctlr(env
, mmu_idx
) & SCTLR_AFE
)) {
6534 /* The simplified model uses AP[0] as an access control bit. */
6535 if ((ap
& 1) == 0) {
6536 /* Access flag fault. */
6537 code
= (code
== 15) ? 6 : 3;
6540 *prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
>> 1);
6542 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
6547 if (!(*prot
& (1 << access_type
))) {
6548 /* Access permission fault. */
6553 /* The NS bit will (as required by the architecture) have no effect if
6554 * the CPU doesn't support TZ or this is a non-secure translation
6555 * regime, because the attribute will already be non-secure.
6557 attrs
->secure
= false;
6559 *phys_ptr
= phys_addr
;
6562 *fsr
= code
| (domain
<< 4);
6566 /* Fault type for long-descriptor MMU fault reporting; this corresponds
6567 * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
6570 translation_fault
= 1,
6572 permission_fault
= 3,
6576 * check_s2_startlevel
6578 * @is_aa64: True if the translation regime is in AArch64 state
6579 * @startlevel: Suggested starting level
6580 * @inputsize: Bitsize of IPAs
6581 * @stride: Page-table stride (See the ARM ARM)
6583 * Returns true if the suggested starting level is OK and false otherwise.
6585 static bool check_s2_startlevel(ARMCPU
*cpu
, bool is_aa64
, int level
,
6586 int inputsize
, int stride
)
6588 /* Negative levels are never allowed. */
6594 unsigned int pamax
= arm_pamax(cpu
);
6597 case 13: /* 64KB Pages. */
6598 if (level
== 0 || (level
== 1 && pamax
<= 42)) {
6602 case 11: /* 16KB Pages. */
6603 if (level
== 0 || (level
== 1 && pamax
<= 40)) {
6607 case 9: /* 4KB Pages. */
6608 if (level
== 0 && pamax
<= 42) {
6613 g_assert_not_reached();
6616 const int grainsize
= stride
+ 3;
6619 /* AArch32 only supports 4KB pages. Assert on that. */
6620 assert(stride
== 9);
6626 startsizecheck
= inputsize
- ((3 - level
) * stride
+ grainsize
);
6627 if (startsizecheck
< 1 || startsizecheck
> stride
+ 4) {
6634 static bool get_phys_addr_lpae(CPUARMState
*env
, target_ulong address
,
6635 int access_type
, ARMMMUIdx mmu_idx
,
6636 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
6637 target_ulong
*page_size_ptr
, uint32_t *fsr
,
6638 ARMMMUFaultInfo
*fi
)
6640 ARMCPU
*cpu
= arm_env_get_cpu(env
);
6641 CPUState
*cs
= CPU(cpu
);
6642 /* Read an LPAE long-descriptor translation table. */
6643 MMUFaultType fault_type
= translation_fault
;
6650 hwaddr descaddr
, descmask
;
6651 uint32_t tableattrs
;
6652 target_ulong page_size
;
6655 int32_t va_size
= 32;
6658 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
6659 int ap
, ns
, xn
, pxn
;
6660 uint32_t el
= regime_el(env
, mmu_idx
);
6661 bool ttbr1_valid
= true;
6662 uint64_t descaddrmask
;
6665 * This code does not handle the different format TCR for VTCR_EL2.
6666 * This code also does not support shareability levels.
6667 * Attribute and permission bit handling should also be checked when adding
6668 * support for those page table walks.
6670 if (arm_el_is_aa64(env
, el
)) {
6673 if (mmu_idx
!= ARMMMUIdx_S2NS
) {
6674 tbi
= extract64(tcr
->raw_tcr
, 20, 1);
6677 if (extract64(address
, 55, 1)) {
6678 tbi
= extract64(tcr
->raw_tcr
, 38, 1);
6680 tbi
= extract64(tcr
->raw_tcr
, 37, 1);
6685 /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it
6689 ttbr1_valid
= false;
6692 /* There is no TTBR1 for EL2 */
6694 ttbr1_valid
= false;
6698 /* Determine whether this address is in the region controlled by
6699 * TTBR0 or TTBR1 (or if it is in neither region and should fault).
6700 * This is a Non-secure PL0/1 stage 1 translation, so controlled by
6701 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
6703 if (va_size
== 64) {
6704 /* AArch64 translation. */
6705 t0sz
= extract32(tcr
->raw_tcr
, 0, 6);
6706 t0sz
= MIN(t0sz
, 39);
6707 t0sz
= MAX(t0sz
, 16);
6708 } else if (mmu_idx
!= ARMMMUIdx_S2NS
) {
6709 /* AArch32 stage 1 translation. */
6710 t0sz
= extract32(tcr
->raw_tcr
, 0, 3);
6712 /* AArch32 stage 2 translation. */
6713 bool sext
= extract32(tcr
->raw_tcr
, 4, 1);
6714 bool sign
= extract32(tcr
->raw_tcr
, 3, 1);
6715 t0sz
= sextract32(tcr
->raw_tcr
, 0, 4);
6717 /* If the sign-extend bit is not the same as t0sz[3], the result
6718 * is unpredictable. Flag this as a guest error. */
6720 qemu_log_mask(LOG_GUEST_ERROR
,
6721 "AArch32: VTCR.S / VTCR.T0SZ[3] missmatch\n");
6724 t1sz
= extract32(tcr
->raw_tcr
, 16, 6);
6725 if (va_size
== 64) {
6726 t1sz
= MIN(t1sz
, 39);
6727 t1sz
= MAX(t1sz
, 16);
6729 if (t0sz
&& !extract64(address
, va_size
- t0sz
, t0sz
- tbi
)) {
6730 /* there is a ttbr0 region and we are in it (high bits all zero) */
6732 } else if (ttbr1_valid
&& t1sz
&&
6733 !extract64(~address
, va_size
- t1sz
, t1sz
- tbi
)) {
6734 /* there is a ttbr1 region and we are in it (high bits all one) */
6737 /* ttbr0 region is "everything not in the ttbr1 region" */
6739 } else if (!t1sz
&& ttbr1_valid
) {
6740 /* ttbr1 region is "everything not in the ttbr0 region" */
6743 /* in the gap between the two regions, this is a Translation fault */
6744 fault_type
= translation_fault
;
6748 /* Note that QEMU ignores shareability and cacheability attributes,
6749 * so we don't need to do anything with the SH, ORGN, IRGN fields
6750 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
6751 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
6752 * implement any ASID-like capability so we can ignore it (instead
6753 * we will always flush the TLB any time the ASID is changed).
6755 if (ttbr_select
== 0) {
6756 ttbr
= regime_ttbr(env
, mmu_idx
, 0);
6758 epd
= extract32(tcr
->raw_tcr
, 7, 1);
6760 inputsize
= va_size
- t0sz
;
6762 tg
= extract32(tcr
->raw_tcr
, 14, 2);
6763 if (tg
== 1) { /* 64KB pages */
6766 if (tg
== 2) { /* 16KB pages */
6770 /* We should only be here if TTBR1 is valid */
6771 assert(ttbr1_valid
);
6773 ttbr
= regime_ttbr(env
, mmu_idx
, 1);
6774 epd
= extract32(tcr
->raw_tcr
, 23, 1);
6775 inputsize
= va_size
- t1sz
;
6777 tg
= extract32(tcr
->raw_tcr
, 30, 2);
6778 if (tg
== 3) { /* 64KB pages */
6781 if (tg
== 1) { /* 16KB pages */
6786 /* Here we should have set up all the parameters for the translation:
6787 * va_size, inputsize, ttbr, epd, stride, tbi
6791 /* Translation table walk disabled => Translation fault on TLB miss
6792 * Note: This is always 0 on 64-bit EL2 and EL3.
6797 if (mmu_idx
!= ARMMMUIdx_S2NS
) {
6798 /* The starting level depends on the virtual address size (which can
6799 * be up to 48 bits) and the translation granule size. It indicates
6800 * the number of strides (stride bits at a time) needed to
6801 * consume the bits of the input address. In the pseudocode this is:
6802 * level = 4 - RoundUp((inputsize - grainsize) / stride)
6803 * where their 'inputsize' is our 'inputsize', 'grainsize' is
6804 * our 'stride + 3' and 'stride' is our 'stride'.
6805 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
6806 * = 4 - (inputsize - stride - 3 + stride - 1) / stride
6807 * = 4 - (inputsize - 4) / stride;
6809 level
= 4 - (inputsize
- 4) / stride
;
6811 /* For stage 2 translations the starting level is specified by the
6812 * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
6814 int startlevel
= extract32(tcr
->raw_tcr
, 6, 2);
6817 if (va_size
== 32 || stride
== 9) {
6818 /* AArch32 or 4KB pages */
6819 level
= 2 - startlevel
;
6821 /* 16KB or 64KB pages */
6822 level
= 3 - startlevel
;
6825 /* Check that the starting level is valid. */
6826 ok
= check_s2_startlevel(cpu
, va_size
== 64, level
,
6829 /* AArch64 reports these as level 0 faults.
6830 * AArch32 reports these as level 1 faults.
6832 level
= va_size
== 64 ? 0 : 1;
6833 fault_type
= translation_fault
;
6838 /* Clear the vaddr bits which aren't part of the within-region address,
6839 * so that we don't have to special case things when calculating the
6840 * first descriptor address.
6842 if (va_size
!= inputsize
) {
6843 address
&= (1ULL << inputsize
) - 1;
6846 descmask
= (1ULL << (stride
+ 3)) - 1;
6848 /* Now we can extract the actual base address from the TTBR */
6849 descaddr
= extract64(ttbr
, 0, 48);
6850 descaddr
&= ~((1ULL << (inputsize
- (stride
* (4 - level
)))) - 1);
6852 /* The address field in the descriptor goes up to bit 39 for ARMv7
6853 * but up to bit 47 for ARMv8.
6855 if (arm_feature(env
, ARM_FEATURE_V8
)) {
6856 descaddrmask
= 0xfffffffff000ULL
;
6858 descaddrmask
= 0xfffffff000ULL
;
6861 /* Secure accesses start with the page table in secure memory and
6862 * can be downgraded to non-secure at any step. Non-secure accesses
6863 * remain non-secure. We implement this by just ORing in the NSTable/NS
6864 * bits at each step.
6866 tableattrs
= regime_is_secure(env
, mmu_idx
) ? 0 : (1 << 4);
6868 uint64_t descriptor
;
6871 descaddr
|= (address
>> (stride
* (4 - level
))) & descmask
;
6873 nstable
= extract32(tableattrs
, 4, 1);
6874 descriptor
= arm_ldq_ptw(cs
, descaddr
, !nstable
, mmu_idx
, fsr
, fi
);
6879 if (!(descriptor
& 1) ||
6880 (!(descriptor
& 2) && (level
== 3))) {
6881 /* Invalid, or the Reserved level 3 encoding */
6884 descaddr
= descriptor
& descaddrmask
;
6886 if ((descriptor
& 2) && (level
< 3)) {
6887 /* Table entry. The top five bits are attributes which may
6888 * propagate down through lower levels of the table (and
6889 * which are all arranged so that 0 means "no effect", so
6890 * we can gather them up by ORing in the bits at each level).
6892 tableattrs
|= extract64(descriptor
, 59, 5);
6896 /* Block entry at level 1 or 2, or page entry at level 3.
6897 * These are basically the same thing, although the number
6898 * of bits we pull in from the vaddr varies.
6900 page_size
= (1ULL << ((stride
* (4 - level
)) + 3));
6901 descaddr
|= (address
& (page_size
- 1));
6902 /* Extract attributes from the descriptor */
6903 attrs
= extract64(descriptor
, 2, 10)
6904 | (extract64(descriptor
, 52, 12) << 10);
6906 if (mmu_idx
== ARMMMUIdx_S2NS
) {
6907 /* Stage 2 table descriptors do not include any attribute fields */
6910 /* Merge in attributes from table descriptors */
6911 attrs
|= extract32(tableattrs
, 0, 2) << 11; /* XN, PXN */
6912 attrs
|= extract32(tableattrs
, 3, 1) << 5; /* APTable[1] => AP[2] */
6913 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
6914 * means "force PL1 access only", which means forcing AP[1] to 0.
6916 if (extract32(tableattrs
, 2, 1)) {
6919 attrs
|= nstable
<< 3; /* NS */
6922 /* Here descaddr is the final physical address, and attributes
6925 fault_type
= access_fault
;
6926 if ((attrs
& (1 << 8)) == 0) {
6931 ap
= extract32(attrs
, 4, 2);
6932 xn
= extract32(attrs
, 12, 1);
6934 if (mmu_idx
== ARMMMUIdx_S2NS
) {
6936 *prot
= get_S2prot(env
, ap
, xn
);
6938 ns
= extract32(attrs
, 3, 1);
6939 pxn
= extract32(attrs
, 11, 1);
6940 *prot
= get_S1prot(env
, mmu_idx
, va_size
== 64, ap
, ns
, xn
, pxn
);
6943 fault_type
= permission_fault
;
6944 if (!(*prot
& (1 << access_type
))) {
6949 /* The NS bit will (as required by the architecture) have no effect if
6950 * the CPU doesn't support TZ or this is a non-secure translation
6951 * regime, because the attribute will already be non-secure.
6953 txattrs
->secure
= false;
6955 *phys_ptr
= descaddr
;
6956 *page_size_ptr
= page_size
;
6960 /* Long-descriptor format IFSR/DFSR value */
6961 *fsr
= (1 << 9) | (fault_type
<< 2) | level
;
6962 /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */
6963 fi
->stage2
= fi
->s1ptw
|| (mmu_idx
== ARMMMUIdx_S2NS
);
6967 static inline void get_phys_addr_pmsav7_default(CPUARMState
*env
,
6969 int32_t address
, int *prot
)
6971 *prot
= PAGE_READ
| PAGE_WRITE
;
6973 case 0xF0000000 ... 0xFFFFFFFF:
6974 if (regime_sctlr(env
, mmu_idx
) & SCTLR_V
) { /* hivecs execing is ok */
6978 case 0x00000000 ... 0x7FFFFFFF:
6985 static bool get_phys_addr_pmsav7(CPUARMState
*env
, uint32_t address
,
6986 int access_type
, ARMMMUIdx mmu_idx
,
6987 hwaddr
*phys_ptr
, int *prot
, uint32_t *fsr
)
6989 ARMCPU
*cpu
= arm_env_get_cpu(env
);
6991 bool is_user
= regime_is_user(env
, mmu_idx
);
6993 *phys_ptr
= address
;
6996 if (regime_translation_disabled(env
, mmu_idx
)) { /* MPU disabled */
6997 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
6998 } else { /* MPU enabled */
6999 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
7001 uint32_t base
= env
->pmsav7
.drbar
[n
];
7002 uint32_t rsize
= extract32(env
->pmsav7
.drsr
[n
], 1, 5);
7006 if (!(env
->pmsav7
.drsr
[n
] & 0x1)) {
7011 qemu_log_mask(LOG_GUEST_ERROR
, "DRSR.Rsize field can not be 0");
7015 rmask
= (1ull << rsize
) - 1;
7018 qemu_log_mask(LOG_GUEST_ERROR
, "DRBAR %" PRIx32
" misaligned "
7019 "to DRSR region size, mask = %" PRIx32
,
7024 if (address
< base
|| address
> base
+ rmask
) {
7028 /* Region matched */
7030 if (rsize
>= 8) { /* no subregions for regions < 256 bytes */
7032 uint32_t srdis_mask
;
7034 rsize
-= 3; /* sub region size (power of 2) */
7035 snd
= ((address
- base
) >> rsize
) & 0x7;
7036 srdis
= extract32(env
->pmsav7
.drsr
[n
], snd
+ 8, 1);
7038 srdis_mask
= srdis
? 0x3 : 0x0;
7039 for (i
= 2; i
<= 8 && rsize
< TARGET_PAGE_BITS
; i
*= 2) {
7040 /* This will check in groups of 2, 4 and then 8, whether
7041 * the subregion bits are consistent. rsize is incremented
7042 * back up to give the region size, considering consistent
7043 * adjacent subregions as one region. Stop testing if rsize
7044 * is already big enough for an entire QEMU page.
7046 int snd_rounded
= snd
& ~(i
- 1);
7047 uint32_t srdis_multi
= extract32(env
->pmsav7
.drsr
[n
],
7048 snd_rounded
+ 8, i
);
7049 if (srdis_mask
^ srdis_multi
) {
7052 srdis_mask
= (srdis_mask
<< i
) | srdis_mask
;
7056 if (rsize
< TARGET_PAGE_BITS
) {
7057 qemu_log_mask(LOG_UNIMP
, "No support for MPU (sub)region"
7058 "alignment of %" PRIu32
" bits. Minimum is %d\n",
7059 rsize
, TARGET_PAGE_BITS
);
7068 if (n
== -1) { /* no hits */
7069 if (cpu
->pmsav7_dregion
&&
7070 (is_user
|| !(regime_sctlr(env
, mmu_idx
) & SCTLR_BR
))) {
7071 /* background fault */
7075 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
7076 } else { /* a MPU hit! */
7077 uint32_t ap
= extract32(env
->pmsav7
.dracr
[n
], 8, 3);
7079 if (is_user
) { /* User mode AP bit decoding */
7084 break; /* no access */
7086 *prot
|= PAGE_WRITE
;
7090 *prot
|= PAGE_READ
| PAGE_EXEC
;
7093 qemu_log_mask(LOG_GUEST_ERROR
,
7094 "Bad value for AP bits in DRACR %"
7097 } else { /* Priv. mode AP bits decoding */
7100 break; /* no access */
7104 *prot
|= PAGE_WRITE
;
7108 *prot
|= PAGE_READ
| PAGE_EXEC
;
7111 qemu_log_mask(LOG_GUEST_ERROR
,
7112 "Bad value for AP bits in DRACR %"
7118 if (env
->pmsav7
.dracr
[n
] & (1 << 12)) {
7119 *prot
&= ~PAGE_EXEC
;
7124 *fsr
= 0x00d; /* Permission fault */
7125 return !(*prot
& (1 << access_type
));
7128 static bool get_phys_addr_pmsav5(CPUARMState
*env
, uint32_t address
,
7129 int access_type
, ARMMMUIdx mmu_idx
,
7130 hwaddr
*phys_ptr
, int *prot
, uint32_t *fsr
)
7135 bool is_user
= regime_is_user(env
, mmu_idx
);
7137 *phys_ptr
= address
;
7138 for (n
= 7; n
>= 0; n
--) {
7139 base
= env
->cp15
.c6_region
[n
];
7140 if ((base
& 1) == 0) {
7143 mask
= 1 << ((base
>> 1) & 0x1f);
7144 /* Keep this shift separate from the above to avoid an
7145 (undefined) << 32. */
7146 mask
= (mask
<< 1) - 1;
7147 if (((base
^ address
) & ~mask
) == 0) {
7156 if (access_type
== 2) {
7157 mask
= env
->cp15
.pmsav5_insn_ap
;
7159 mask
= env
->cp15
.pmsav5_data_ap
;
7161 mask
= (mask
>> (n
* 4)) & 0xf;
7171 *prot
= PAGE_READ
| PAGE_WRITE
;
7176 *prot
|= PAGE_WRITE
;
7180 *prot
= PAGE_READ
| PAGE_WRITE
;
7193 /* Bad permission. */
7201 /* get_phys_addr - get the physical address for this virtual address
7203 * Find the physical address corresponding to the given virtual address,
7204 * by doing a translation table walk on MMU based systems or using the
7205 * MPU state on MPU based systems.
7207 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
7208 * prot and page_size may not be filled in, and the populated fsr value provides
7209 * information on why the translation aborted, in the format of a
7210 * DFSR/IFSR fault register, with the following caveats:
7211 * * we honour the short vs long DFSR format differences.
7212 * * the WnR bit is never set (the caller must do this).
7213 * * for PSMAv5 based systems we don't bother to return a full FSR format
7217 * @address: virtual address to get physical address for
7218 * @access_type: 0 for read, 1 for write, 2 for execute
7219 * @mmu_idx: MMU index indicating required translation regime
7220 * @phys_ptr: set to the physical address corresponding to the virtual address
7221 * @attrs: set to the memory transaction attributes to use
7222 * @prot: set to the permissions for the page containing phys_ptr
7223 * @page_size: set to the size of the page containing phys_ptr
7224 * @fsr: set to the DFSR/IFSR value on failure
7226 static bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
7227 int access_type
, ARMMMUIdx mmu_idx
,
7228 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
7229 target_ulong
*page_size
, uint32_t *fsr
,
7230 ARMMMUFaultInfo
*fi
)
7232 if (mmu_idx
== ARMMMUIdx_S12NSE0
|| mmu_idx
== ARMMMUIdx_S12NSE1
) {
7233 /* Call ourselves recursively to do the stage 1 and then stage 2
7236 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
7241 ret
= get_phys_addr(env
, address
, access_type
,
7242 mmu_idx
+ ARMMMUIdx_S1NSE0
, &ipa
, attrs
,
7243 prot
, page_size
, fsr
, fi
);
7245 /* If S1 fails or S2 is disabled, return early. */
7246 if (ret
|| regime_translation_disabled(env
, ARMMMUIdx_S2NS
)) {
7251 /* S1 is done. Now do S2 translation. */
7252 ret
= get_phys_addr_lpae(env
, ipa
, access_type
, ARMMMUIdx_S2NS
,
7253 phys_ptr
, attrs
, &s2_prot
,
7254 page_size
, fsr
, fi
);
7256 /* Combine the S1 and S2 perms. */
7261 * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
7263 mmu_idx
+= ARMMMUIdx_S1NSE0
;
7267 /* The page table entries may downgrade secure to non-secure, but
7268 * cannot upgrade an non-secure translation regime's attributes
7271 attrs
->secure
= regime_is_secure(env
, mmu_idx
);
7272 attrs
->user
= regime_is_user(env
, mmu_idx
);
7274 /* Fast Context Switch Extension. This doesn't exist at all in v8.
7275 * In v7 and earlier it affects all stage 1 translations.
7277 if (address
< 0x02000000 && mmu_idx
!= ARMMMUIdx_S2NS
7278 && !arm_feature(env
, ARM_FEATURE_V8
)) {
7279 if (regime_el(env
, mmu_idx
) == 3) {
7280 address
+= env
->cp15
.fcseidr_s
;
7282 address
+= env
->cp15
.fcseidr_ns
;
7286 /* pmsav7 has special handling for when MPU is disabled so call it before
7287 * the common MMU/MPU disabled check below.
7289 if (arm_feature(env
, ARM_FEATURE_MPU
) &&
7290 arm_feature(env
, ARM_FEATURE_V7
)) {
7291 *page_size
= TARGET_PAGE_SIZE
;
7292 return get_phys_addr_pmsav7(env
, address
, access_type
, mmu_idx
,
7293 phys_ptr
, prot
, fsr
);
7296 if (regime_translation_disabled(env
, mmu_idx
)) {
7297 /* MMU/MPU disabled. */
7298 *phys_ptr
= address
;
7299 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
7300 *page_size
= TARGET_PAGE_SIZE
;
7304 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
7306 *page_size
= TARGET_PAGE_SIZE
;
7307 return get_phys_addr_pmsav5(env
, address
, access_type
, mmu_idx
,
7308 phys_ptr
, prot
, fsr
);
7311 if (regime_using_lpae_format(env
, mmu_idx
)) {
7312 return get_phys_addr_lpae(env
, address
, access_type
, mmu_idx
, phys_ptr
,
7313 attrs
, prot
, page_size
, fsr
, fi
);
7314 } else if (regime_sctlr(env
, mmu_idx
) & SCTLR_XP
) {
7315 return get_phys_addr_v6(env
, address
, access_type
, mmu_idx
, phys_ptr
,
7316 attrs
, prot
, page_size
, fsr
, fi
);
7318 return get_phys_addr_v5(env
, address
, access_type
, mmu_idx
, phys_ptr
,
7319 prot
, page_size
, fsr
, fi
);
7323 /* Walk the page table and (if the mapping exists) add the page
7324 * to the TLB. Return false on success, or true on failure. Populate
7325 * fsr with ARM DFSR/IFSR fault register format value on failure.
7327 bool arm_tlb_fill(CPUState
*cs
, vaddr address
,
7328 int access_type
, int mmu_idx
, uint32_t *fsr
,
7329 ARMMMUFaultInfo
*fi
)
7331 ARMCPU
*cpu
= ARM_CPU(cs
);
7332 CPUARMState
*env
= &cpu
->env
;
7334 target_ulong page_size
;
7337 MemTxAttrs attrs
= {};
7339 ret
= get_phys_addr(env
, address
, access_type
, mmu_idx
, &phys_addr
,
7340 &attrs
, &prot
, &page_size
, fsr
, fi
);
7342 /* Map a single [sub]page. */
7343 phys_addr
&= TARGET_PAGE_MASK
;
7344 address
&= TARGET_PAGE_MASK
;
7345 tlb_set_page_with_attrs(cs
, address
, phys_addr
, attrs
,
7346 prot
, mmu_idx
, page_size
);
7353 hwaddr
arm_cpu_get_phys_page_attrs_debug(CPUState
*cs
, vaddr addr
,
7356 ARMCPU
*cpu
= ARM_CPU(cs
);
7357 CPUARMState
*env
= &cpu
->env
;
7359 target_ulong page_size
;
7363 ARMMMUFaultInfo fi
= {};
7365 *attrs
= (MemTxAttrs
) {};
7367 ret
= get_phys_addr(env
, addr
, 0, cpu_mmu_index(env
, false), &phys_addr
,
7368 attrs
, &prot
, &page_size
, &fsr
, &fi
);
7376 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
7378 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
7379 env
->regs
[13] = val
;
7381 env
->banked_r13
[bank_number(mode
)] = val
;
7385 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
7387 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
7388 return env
->regs
[13];
7390 return env
->banked_r13
[bank_number(mode
)];
7394 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
7396 ARMCPU
*cpu
= arm_env_get_cpu(env
);
7400 return xpsr_read(env
) & 0xf8000000;
7402 return xpsr_read(env
) & 0xf80001ff;
7404 return xpsr_read(env
) & 0xff00fc00;
7406 return xpsr_read(env
) & 0xff00fdff;
7408 return xpsr_read(env
) & 0x000001ff;
7410 return xpsr_read(env
) & 0x0700fc00;
7412 return xpsr_read(env
) & 0x0700edff;
7414 return env
->v7m
.current_sp
? env
->v7m
.other_sp
: env
->regs
[13];
7416 return env
->v7m
.current_sp
? env
->regs
[13] : env
->v7m
.other_sp
;
7417 case 16: /* PRIMASK */
7418 return (env
->daif
& PSTATE_I
) != 0;
7419 case 17: /* BASEPRI */
7420 case 18: /* BASEPRI_MAX */
7421 return env
->v7m
.basepri
;
7422 case 19: /* FAULTMASK */
7423 return (env
->daif
& PSTATE_F
) != 0;
7424 case 20: /* CONTROL */
7425 return env
->v7m
.control
;
7427 /* ??? For debugging only. */
7428 cpu_abort(CPU(cpu
), "Unimplemented system register read (%d)\n", reg
);
7433 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
7435 ARMCPU
*cpu
= arm_env_get_cpu(env
);
7439 xpsr_write(env
, val
, 0xf8000000);
7442 xpsr_write(env
, val
, 0xf8000000);
7445 xpsr_write(env
, val
, 0xfe00fc00);
7448 xpsr_write(env
, val
, 0xfe00fc00);
7451 /* IPSR bits are readonly. */
7454 xpsr_write(env
, val
, 0x0600fc00);
7457 xpsr_write(env
, val
, 0x0600fc00);
7460 if (env
->v7m
.current_sp
)
7461 env
->v7m
.other_sp
= val
;
7463 env
->regs
[13] = val
;
7466 if (env
->v7m
.current_sp
)
7467 env
->regs
[13] = val
;
7469 env
->v7m
.other_sp
= val
;
7471 case 16: /* PRIMASK */
7473 env
->daif
|= PSTATE_I
;
7475 env
->daif
&= ~PSTATE_I
;
7478 case 17: /* BASEPRI */
7479 env
->v7m
.basepri
= val
& 0xff;
7481 case 18: /* BASEPRI_MAX */
7483 if (val
!= 0 && (val
< env
->v7m
.basepri
|| env
->v7m
.basepri
== 0))
7484 env
->v7m
.basepri
= val
;
7486 case 19: /* FAULTMASK */
7488 env
->daif
|= PSTATE_F
;
7490 env
->daif
&= ~PSTATE_F
;
7493 case 20: /* CONTROL */
7494 env
->v7m
.control
= val
& 3;
7495 switch_v7m_sp(env
, (val
& 2) != 0);
7498 /* ??? For debugging only. */
7499 cpu_abort(CPU(cpu
), "Unimplemented system register write (%d)\n", reg
);
7506 void HELPER(dc_zva
)(CPUARMState
*env
, uint64_t vaddr_in
)
7508 /* Implement DC ZVA, which zeroes a fixed-length block of memory.
7509 * Note that we do not implement the (architecturally mandated)
7510 * alignment fault for attempts to use this on Device memory
7511 * (which matches the usual QEMU behaviour of not implementing either
7512 * alignment faults or any memory attribute handling).
7515 ARMCPU
*cpu
= arm_env_get_cpu(env
);
7516 uint64_t blocklen
= 4 << cpu
->dcz_blocksize
;
7517 uint64_t vaddr
= vaddr_in
& ~(blocklen
- 1);
7519 #ifndef CONFIG_USER_ONLY
7521 /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
7522 * the block size so we might have to do more than one TLB lookup.
7523 * We know that in fact for any v8 CPU the page size is at least 4K
7524 * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
7525 * 1K as an artefact of legacy v5 subpage support being present in the
7526 * same QEMU executable.
7528 int maxidx
= DIV_ROUND_UP(blocklen
, TARGET_PAGE_SIZE
);
7529 void *hostaddr
[maxidx
];
7531 unsigned mmu_idx
= cpu_mmu_index(env
, false);
7532 TCGMemOpIdx oi
= make_memop_idx(MO_UB
, mmu_idx
);
7534 for (try = 0; try < 2; try++) {
7536 for (i
= 0; i
< maxidx
; i
++) {
7537 hostaddr
[i
] = tlb_vaddr_to_host(env
,
7538 vaddr
+ TARGET_PAGE_SIZE
* i
,
7545 /* If it's all in the TLB it's fair game for just writing to;
7546 * we know we don't need to update dirty status, etc.
7548 for (i
= 0; i
< maxidx
- 1; i
++) {
7549 memset(hostaddr
[i
], 0, TARGET_PAGE_SIZE
);
7551 memset(hostaddr
[i
], 0, blocklen
- (i
* TARGET_PAGE_SIZE
));
7554 /* OK, try a store and see if we can populate the tlb. This
7555 * might cause an exception if the memory isn't writable,
7556 * in which case we will longjmp out of here. We must for
7557 * this purpose use the actual register value passed to us
7558 * so that we get the fault address right.
7560 helper_ret_stb_mmu(env
, vaddr_in
, 0, oi
, GETRA());
7561 /* Now we can populate the other TLB entries, if any */
7562 for (i
= 0; i
< maxidx
; i
++) {
7563 uint64_t va
= vaddr
+ TARGET_PAGE_SIZE
* i
;
7564 if (va
!= (vaddr_in
& TARGET_PAGE_MASK
)) {
7565 helper_ret_stb_mmu(env
, va
, 0, oi
, GETRA());
7570 /* Slow path (probably attempt to do this to an I/O device or
7571 * similar, or clearing of a block of code we have translations
7572 * cached for). Just do a series of byte writes as the architecture
7573 * demands. It's not worth trying to use a cpu_physical_memory_map(),
7574 * memset(), unmap() sequence here because:
7575 * + we'd need to account for the blocksize being larger than a page
7576 * + the direct-RAM access case is almost always going to be dealt
7577 * with in the fastpath code above, so there's no speed benefit
7578 * + we would have to deal with the map returning NULL because the
7579 * bounce buffer was in use
7581 for (i
= 0; i
< blocklen
; i
++) {
7582 helper_ret_stb_mmu(env
, vaddr
+ i
, 0, oi
, GETRA());
7586 memset(g2h(vaddr
), 0, blocklen
);
7590 /* Note that signed overflow is undefined in C. The following routines are
7591 careful to use unsigned types where modulo arithmetic is required.
7592 Failure to do so _will_ break on newer gcc. */
7594 /* Signed saturating arithmetic. */
7596 /* Perform 16-bit signed saturating addition. */
7597 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
7602 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
7611 /* Perform 8-bit signed saturating addition. */
7612 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
7617 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
7626 /* Perform 16-bit signed saturating subtraction. */
7627 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
7632 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
7641 /* Perform 8-bit signed saturating subtraction. */
7642 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
7647 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
7656 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
7657 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
7658 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
7659 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
7662 #include "op_addsub.h"
7664 /* Unsigned saturating arithmetic. */
7665 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
7674 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
7682 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
7691 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
7699 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
7700 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
7701 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
7702 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
7705 #include "op_addsub.h"
7707 /* Signed modulo arithmetic. */
7708 #define SARITH16(a, b, n, op) do { \
7710 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
7711 RESULT(sum, n, 16); \
7713 ge |= 3 << (n * 2); \
7716 #define SARITH8(a, b, n, op) do { \
7718 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
7719 RESULT(sum, n, 8); \
7725 #define ADD16(a, b, n) SARITH16(a, b, n, +)
7726 #define SUB16(a, b, n) SARITH16(a, b, n, -)
7727 #define ADD8(a, b, n) SARITH8(a, b, n, +)
7728 #define SUB8(a, b, n) SARITH8(a, b, n, -)
7732 #include "op_addsub.h"
7734 /* Unsigned modulo arithmetic. */
7735 #define ADD16(a, b, n) do { \
7737 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
7738 RESULT(sum, n, 16); \
7739 if ((sum >> 16) == 1) \
7740 ge |= 3 << (n * 2); \
7743 #define ADD8(a, b, n) do { \
7745 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
7746 RESULT(sum, n, 8); \
7747 if ((sum >> 8) == 1) \
7751 #define SUB16(a, b, n) do { \
7753 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
7754 RESULT(sum, n, 16); \
7755 if ((sum >> 16) == 0) \
7756 ge |= 3 << (n * 2); \
7759 #define SUB8(a, b, n) do { \
7761 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
7762 RESULT(sum, n, 8); \
7763 if ((sum >> 8) == 0) \
7770 #include "op_addsub.h"
7772 /* Halved signed arithmetic. */
7773 #define ADD16(a, b, n) \
7774 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
7775 #define SUB16(a, b, n) \
7776 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
7777 #define ADD8(a, b, n) \
7778 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
7779 #define SUB8(a, b, n) \
7780 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
7783 #include "op_addsub.h"
7785 /* Halved unsigned arithmetic. */
7786 #define ADD16(a, b, n) \
7787 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
7788 #define SUB16(a, b, n) \
7789 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
7790 #define ADD8(a, b, n) \
7791 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
7792 #define SUB8(a, b, n) \
7793 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
7796 #include "op_addsub.h"
7798 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
7806 /* Unsigned sum of absolute byte differences. */
7807 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
7810 sum
= do_usad(a
, b
);
7811 sum
+= do_usad(a
>> 8, b
>> 8);
7812 sum
+= do_usad(a
>> 16, b
>>16);
7813 sum
+= do_usad(a
>> 24, b
>> 24);
7817 /* For ARMv6 SEL instruction. */
7818 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
7831 return (a
& mask
) | (b
& ~mask
);
7834 /* VFP support. We follow the convention used for VFP instructions:
7835 Single precision routines have a "s" suffix, double precision a
7838 /* Convert host exception flags to vfp form. */
7839 static inline int vfp_exceptbits_from_host(int host_bits
)
7841 int target_bits
= 0;
7843 if (host_bits
& float_flag_invalid
)
7845 if (host_bits
& float_flag_divbyzero
)
7847 if (host_bits
& float_flag_overflow
)
7849 if (host_bits
& (float_flag_underflow
| float_flag_output_denormal
))
7851 if (host_bits
& float_flag_inexact
)
7852 target_bits
|= 0x10;
7853 if (host_bits
& float_flag_input_denormal
)
7854 target_bits
|= 0x80;
7858 uint32_t HELPER(vfp_get_fpscr
)(CPUARMState
*env
)
7863 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
7864 | (env
->vfp
.vec_len
<< 16)
7865 | (env
->vfp
.vec_stride
<< 20);
7866 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
7867 i
|= get_float_exception_flags(&env
->vfp
.standard_fp_status
);
7868 fpscr
|= vfp_exceptbits_from_host(i
);
7872 uint32_t vfp_get_fpscr(CPUARMState
*env
)
7874 return HELPER(vfp_get_fpscr
)(env
);
7877 /* Convert vfp exception flags to target form. */
7878 static inline int vfp_exceptbits_to_host(int target_bits
)
7882 if (target_bits
& 1)
7883 host_bits
|= float_flag_invalid
;
7884 if (target_bits
& 2)
7885 host_bits
|= float_flag_divbyzero
;
7886 if (target_bits
& 4)
7887 host_bits
|= float_flag_overflow
;
7888 if (target_bits
& 8)
7889 host_bits
|= float_flag_underflow
;
7890 if (target_bits
& 0x10)
7891 host_bits
|= float_flag_inexact
;
7892 if (target_bits
& 0x80)
7893 host_bits
|= float_flag_input_denormal
;
7897 void HELPER(vfp_set_fpscr
)(CPUARMState
*env
, uint32_t val
)
7902 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
7903 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
7904 env
->vfp
.vec_len
= (val
>> 16) & 7;
7905 env
->vfp
.vec_stride
= (val
>> 20) & 3;
7908 if (changed
& (3 << 22)) {
7909 i
= (val
>> 22) & 3;
7911 case FPROUNDING_TIEEVEN
:
7912 i
= float_round_nearest_even
;
7914 case FPROUNDING_POSINF
:
7917 case FPROUNDING_NEGINF
:
7918 i
= float_round_down
;
7920 case FPROUNDING_ZERO
:
7921 i
= float_round_to_zero
;
7924 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
7926 if (changed
& (1 << 24)) {
7927 set_flush_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
7928 set_flush_inputs_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
7930 if (changed
& (1 << 25))
7931 set_default_nan_mode((val
& (1 << 25)) != 0, &env
->vfp
.fp_status
);
7933 i
= vfp_exceptbits_to_host(val
);
7934 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
7935 set_float_exception_flags(0, &env
->vfp
.standard_fp_status
);
7938 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
)
7940 HELPER(vfp_set_fpscr
)(env
, val
);
7943 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
7945 #define VFP_BINOP(name) \
7946 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
7948 float_status *fpst = fpstp; \
7949 return float32_ ## name(a, b, fpst); \
7951 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
7953 float_status *fpst = fpstp; \
7954 return float64_ ## name(a, b, fpst); \
7966 float32
VFP_HELPER(neg
, s
)(float32 a
)
7968 return float32_chs(a
);
7971 float64
VFP_HELPER(neg
, d
)(float64 a
)
7973 return float64_chs(a
);
7976 float32
VFP_HELPER(abs
, s
)(float32 a
)
7978 return float32_abs(a
);
7981 float64
VFP_HELPER(abs
, d
)(float64 a
)
7983 return float64_abs(a
);
7986 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUARMState
*env
)
7988 return float32_sqrt(a
, &env
->vfp
.fp_status
);
7991 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUARMState
*env
)
7993 return float64_sqrt(a
, &env
->vfp
.fp_status
);
7996 /* XXX: check quiet/signaling case */
7997 #define DO_VFP_cmp(p, type) \
7998 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
8001 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
8002 case 0: flags = 0x6; break; \
8003 case -1: flags = 0x8; break; \
8004 case 1: flags = 0x2; break; \
8005 default: case 2: flags = 0x3; break; \
8007 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
8008 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
8010 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
8013 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
8014 case 0: flags = 0x6; break; \
8015 case -1: flags = 0x8; break; \
8016 case 1: flags = 0x2; break; \
8017 default: case 2: flags = 0x3; break; \
8019 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
8020 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
8022 DO_VFP_cmp(s
, float32
)
8023 DO_VFP_cmp(d
, float64
)
8026 /* Integer to float and float to integer conversions */
8028 #define CONV_ITOF(name, fsz, sign) \
8029 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
8031 float_status *fpst = fpstp; \
8032 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
8035 #define CONV_FTOI(name, fsz, sign, round) \
8036 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
8038 float_status *fpst = fpstp; \
8039 if (float##fsz##_is_any_nan(x)) { \
8040 float_raise(float_flag_invalid, fpst); \
8043 return float##fsz##_to_##sign##int32##round(x, fpst); \
8046 #define FLOAT_CONVS(name, p, fsz, sign) \
8047 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
8048 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
8049 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
8051 FLOAT_CONVS(si
, s
, 32, )
8052 FLOAT_CONVS(si
, d
, 64, )
8053 FLOAT_CONVS(ui
, s
, 32, u
)
8054 FLOAT_CONVS(ui
, d
, 64, u
)
8060 /* floating point conversion */
8061 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUARMState
*env
)
8063 float64 r
= float32_to_float64(x
, &env
->vfp
.fp_status
);
8064 /* ARM requires that S<->D conversion of any kind of NaN generates
8065 * a quiet NaN by forcing the most significant frac bit to 1.
8067 return float64_maybe_silence_nan(r
);
8070 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUARMState
*env
)
8072 float32 r
= float64_to_float32(x
, &env
->vfp
.fp_status
);
8073 /* ARM requires that S<->D conversion of any kind of NaN generates
8074 * a quiet NaN by forcing the most significant frac bit to 1.
8076 return float32_maybe_silence_nan(r
);
8079 /* VFP3 fixed point conversion. */
8080 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
8081 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
8084 float_status *fpst = fpstp; \
8086 tmp = itype##_to_##float##fsz(x, fpst); \
8087 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
8090 /* Notice that we want only input-denormal exception flags from the
8091 * scalbn operation: the other possible flags (overflow+inexact if
8092 * we overflow to infinity, output-denormal) aren't correct for the
8093 * complete scale-and-convert operation.
8095 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
8096 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
8100 float_status *fpst = fpstp; \
8101 int old_exc_flags = get_float_exception_flags(fpst); \
8103 if (float##fsz##_is_any_nan(x)) { \
8104 float_raise(float_flag_invalid, fpst); \
8107 tmp = float##fsz##_scalbn(x, shift, fpst); \
8108 old_exc_flags |= get_float_exception_flags(fpst) \
8109 & float_flag_input_denormal; \
8110 set_float_exception_flags(old_exc_flags, fpst); \
8111 return float##fsz##_to_##itype##round(tmp, fpst); \
8114 #define VFP_CONV_FIX(name, p, fsz, isz, itype) \
8115 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
8116 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
8117 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
8119 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \
8120 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
8121 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
8123 VFP_CONV_FIX(sh
, d
, 64, 64, int16
)
8124 VFP_CONV_FIX(sl
, d
, 64, 64, int32
)
8125 VFP_CONV_FIX_A64(sq
, d
, 64, 64, int64
)
8126 VFP_CONV_FIX(uh
, d
, 64, 64, uint16
)
8127 VFP_CONV_FIX(ul
, d
, 64, 64, uint32
)
8128 VFP_CONV_FIX_A64(uq
, d
, 64, 64, uint64
)
8129 VFP_CONV_FIX(sh
, s
, 32, 32, int16
)
8130 VFP_CONV_FIX(sl
, s
, 32, 32, int32
)
8131 VFP_CONV_FIX_A64(sq
, s
, 32, 64, int64
)
8132 VFP_CONV_FIX(uh
, s
, 32, 32, uint16
)
8133 VFP_CONV_FIX(ul
, s
, 32, 32, uint32
)
8134 VFP_CONV_FIX_A64(uq
, s
, 32, 64, uint64
)
8136 #undef VFP_CONV_FIX_FLOAT
8137 #undef VFP_CONV_FLOAT_FIX_ROUND
8139 /* Set the current fp rounding mode and return the old one.
8140 * The argument is a softfloat float_round_ value.
8142 uint32_t HELPER(set_rmode
)(uint32_t rmode
, CPUARMState
*env
)
8144 float_status
*fp_status
= &env
->vfp
.fp_status
;
8146 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
8147 set_float_rounding_mode(rmode
, fp_status
);
8152 /* Set the current fp rounding mode in the standard fp status and return
8153 * the old one. This is for NEON instructions that need to change the
8154 * rounding mode but wish to use the standard FPSCR values for everything
8155 * else. Always set the rounding mode back to the correct value after
8157 * The argument is a softfloat float_round_ value.
8159 uint32_t HELPER(set_neon_rmode
)(uint32_t rmode
, CPUARMState
*env
)
8161 float_status
*fp_status
= &env
->vfp
.standard_fp_status
;
8163 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
8164 set_float_rounding_mode(rmode
, fp_status
);
8169 /* Half precision conversions. */
8170 static float32
do_fcvt_f16_to_f32(uint32_t a
, CPUARMState
*env
, float_status
*s
)
8172 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
8173 float32 r
= float16_to_float32(make_float16(a
), ieee
, s
);
8175 return float32_maybe_silence_nan(r
);
8180 static uint32_t do_fcvt_f32_to_f16(float32 a
, CPUARMState
*env
, float_status
*s
)
8182 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
8183 float16 r
= float32_to_float16(a
, ieee
, s
);
8185 r
= float16_maybe_silence_nan(r
);
8187 return float16_val(r
);
8190 float32
HELPER(neon_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
8192 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.standard_fp_status
);
8195 uint32_t HELPER(neon_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
8197 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.standard_fp_status
);
8200 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
8202 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.fp_status
);
8205 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
8207 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.fp_status
);
8210 float64
HELPER(vfp_fcvt_f16_to_f64
)(uint32_t a
, CPUARMState
*env
)
8212 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
8213 float64 r
= float16_to_float64(make_float16(a
), ieee
, &env
->vfp
.fp_status
);
8215 return float64_maybe_silence_nan(r
);
8220 uint32_t HELPER(vfp_fcvt_f64_to_f16
)(float64 a
, CPUARMState
*env
)
8222 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
8223 float16 r
= float64_to_float16(a
, ieee
, &env
->vfp
.fp_status
);
8225 r
= float16_maybe_silence_nan(r
);
8227 return float16_val(r
);
8230 #define float32_two make_float32(0x40000000)
8231 #define float32_three make_float32(0x40400000)
8232 #define float32_one_point_five make_float32(0x3fc00000)
8234 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
8236 float_status
*s
= &env
->vfp
.standard_fp_status
;
8237 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
8238 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
8239 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
8240 float_raise(float_flag_input_denormal
, s
);
8244 return float32_sub(float32_two
, float32_mul(a
, b
, s
), s
);
8247 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
8249 float_status
*s
= &env
->vfp
.standard_fp_status
;
8251 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
8252 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
8253 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
8254 float_raise(float_flag_input_denormal
, s
);
8256 return float32_one_point_five
;
8258 product
= float32_mul(a
, b
, s
);
8259 return float32_div(float32_sub(float32_three
, product
, s
), float32_two
, s
);
8264 /* Constants 256 and 512 are used in some helpers; we avoid relying on
8265 * int->float conversions at run-time. */
8266 #define float64_256 make_float64(0x4070000000000000LL)
8267 #define float64_512 make_float64(0x4080000000000000LL)
8268 #define float32_maxnorm make_float32(0x7f7fffff)
8269 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
8271 /* Reciprocal functions
8273 * The algorithm that must be used to calculate the estimate
8274 * is specified by the ARM ARM, see FPRecipEstimate()
8277 static float64
recip_estimate(float64 a
, float_status
*real_fp_status
)
8279 /* These calculations mustn't set any fp exception flags,
8280 * so we use a local copy of the fp_status.
8282 float_status dummy_status
= *real_fp_status
;
8283 float_status
*s
= &dummy_status
;
8284 /* q = (int)(a * 512.0) */
8285 float64 q
= float64_mul(float64_512
, a
, s
);
8286 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
8288 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
8289 q
= int64_to_float64(q_int
, s
);
8290 q
= float64_add(q
, float64_half
, s
);
8291 q
= float64_div(q
, float64_512
, s
);
8292 q
= float64_div(float64_one
, q
, s
);
8294 /* s = (int)(256.0 * r + 0.5) */
8295 q
= float64_mul(q
, float64_256
, s
);
8296 q
= float64_add(q
, float64_half
, s
);
8297 q_int
= float64_to_int64_round_to_zero(q
, s
);
8299 /* return (double)s / 256.0 */
8300 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
8303 /* Common wrapper to call recip_estimate */
8304 static float64
call_recip_estimate(float64 num
, int off
, float_status
*fpst
)
8306 uint64_t val64
= float64_val(num
);
8307 uint64_t frac
= extract64(val64
, 0, 52);
8308 int64_t exp
= extract64(val64
, 52, 11);
8310 float64 scaled
, estimate
;
8312 /* Generate the scaled number for the estimate function */
8314 if (extract64(frac
, 51, 1) == 0) {
8316 frac
= extract64(frac
, 0, 50) << 2;
8318 frac
= extract64(frac
, 0, 51) << 1;
8322 /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
8323 scaled
= make_float64((0x3feULL
<< 52)
8324 | extract64(frac
, 44, 8) << 44);
8326 estimate
= recip_estimate(scaled
, fpst
);
8328 /* Build new result */
8329 val64
= float64_val(estimate
);
8330 sbit
= 0x8000000000000000ULL
& val64
;
8332 frac
= extract64(val64
, 0, 52);
8335 frac
= 1ULL << 51 | extract64(frac
, 1, 51);
8336 } else if (exp
== -1) {
8337 frac
= 1ULL << 50 | extract64(frac
, 2, 50);
8341 return make_float64(sbit
| (exp
<< 52) | frac
);
8344 static bool round_to_inf(float_status
*fpst
, bool sign_bit
)
8346 switch (fpst
->float_rounding_mode
) {
8347 case float_round_nearest_even
: /* Round to Nearest */
8349 case float_round_up
: /* Round to +Inf */
8351 case float_round_down
: /* Round to -Inf */
8353 case float_round_to_zero
: /* Round to Zero */
8357 g_assert_not_reached();
8360 float32
HELPER(recpe_f32
)(float32 input
, void *fpstp
)
8362 float_status
*fpst
= fpstp
;
8363 float32 f32
= float32_squash_input_denormal(input
, fpst
);
8364 uint32_t f32_val
= float32_val(f32
);
8365 uint32_t f32_sbit
= 0x80000000ULL
& f32_val
;
8366 int32_t f32_exp
= extract32(f32_val
, 23, 8);
8367 uint32_t f32_frac
= extract32(f32_val
, 0, 23);
8373 if (float32_is_any_nan(f32
)) {
8375 if (float32_is_signaling_nan(f32
)) {
8376 float_raise(float_flag_invalid
, fpst
);
8377 nan
= float32_maybe_silence_nan(f32
);
8379 if (fpst
->default_nan_mode
) {
8380 nan
= float32_default_nan
;
8383 } else if (float32_is_infinity(f32
)) {
8384 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
8385 } else if (float32_is_zero(f32
)) {
8386 float_raise(float_flag_divbyzero
, fpst
);
8387 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
8388 } else if ((f32_val
& ~(1ULL << 31)) < (1ULL << 21)) {
8389 /* Abs(value) < 2.0^-128 */
8390 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
8391 if (round_to_inf(fpst
, f32_sbit
)) {
8392 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
8394 return float32_set_sign(float32_maxnorm
, float32_is_neg(f32
));
8396 } else if (f32_exp
>= 253 && fpst
->flush_to_zero
) {
8397 float_raise(float_flag_underflow
, fpst
);
8398 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
8402 f64
= make_float64(((int64_t)(f32_exp
) << 52) | (int64_t)(f32_frac
) << 29);
8403 r64
= call_recip_estimate(f64
, 253, fpst
);
8404 r64_val
= float64_val(r64
);
8405 r64_exp
= extract64(r64_val
, 52, 11);
8406 r64_frac
= extract64(r64_val
, 0, 52);
8408 /* result = sign : result_exp<7:0> : fraction<51:29>; */
8409 return make_float32(f32_sbit
|
8410 (r64_exp
& 0xff) << 23 |
8411 extract64(r64_frac
, 29, 24));
8414 float64
HELPER(recpe_f64
)(float64 input
, void *fpstp
)
8416 float_status
*fpst
= fpstp
;
8417 float64 f64
= float64_squash_input_denormal(input
, fpst
);
8418 uint64_t f64_val
= float64_val(f64
);
8419 uint64_t f64_sbit
= 0x8000000000000000ULL
& f64_val
;
8420 int64_t f64_exp
= extract64(f64_val
, 52, 11);
8426 /* Deal with any special cases */
8427 if (float64_is_any_nan(f64
)) {
8429 if (float64_is_signaling_nan(f64
)) {
8430 float_raise(float_flag_invalid
, fpst
);
8431 nan
= float64_maybe_silence_nan(f64
);
8433 if (fpst
->default_nan_mode
) {
8434 nan
= float64_default_nan
;
8437 } else if (float64_is_infinity(f64
)) {
8438 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
8439 } else if (float64_is_zero(f64
)) {
8440 float_raise(float_flag_divbyzero
, fpst
);
8441 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
8442 } else if ((f64_val
& ~(1ULL << 63)) < (1ULL << 50)) {
8443 /* Abs(value) < 2.0^-1024 */
8444 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
8445 if (round_to_inf(fpst
, f64_sbit
)) {
8446 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
8448 return float64_set_sign(float64_maxnorm
, float64_is_neg(f64
));
8450 } else if (f64_exp
>= 2045 && fpst
->flush_to_zero
) {
8451 float_raise(float_flag_underflow
, fpst
);
8452 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
8455 r64
= call_recip_estimate(f64
, 2045, fpst
);
8456 r64_val
= float64_val(r64
);
8457 r64_exp
= extract64(r64_val
, 52, 11);
8458 r64_frac
= extract64(r64_val
, 0, 52);
8460 /* result = sign : result_exp<10:0> : fraction<51:0> */
8461 return make_float64(f64_sbit
|
8462 ((r64_exp
& 0x7ff) << 52) |
8466 /* The algorithm that must be used to calculate the estimate
8467 * is specified by the ARM ARM.
8469 static float64
recip_sqrt_estimate(float64 a
, float_status
*real_fp_status
)
8471 /* These calculations mustn't set any fp exception flags,
8472 * so we use a local copy of the fp_status.
8474 float_status dummy_status
= *real_fp_status
;
8475 float_status
*s
= &dummy_status
;
8479 if (float64_lt(a
, float64_half
, s
)) {
8480 /* range 0.25 <= a < 0.5 */
8482 /* a in units of 1/512 rounded down */
8483 /* q0 = (int)(a * 512.0); */
8484 q
= float64_mul(float64_512
, a
, s
);
8485 q_int
= float64_to_int64_round_to_zero(q
, s
);
8487 /* reciprocal root r */
8488 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
8489 q
= int64_to_float64(q_int
, s
);
8490 q
= float64_add(q
, float64_half
, s
);
8491 q
= float64_div(q
, float64_512
, s
);
8492 q
= float64_sqrt(q
, s
);
8493 q
= float64_div(float64_one
, q
, s
);
8495 /* range 0.5 <= a < 1.0 */
8497 /* a in units of 1/256 rounded down */
8498 /* q1 = (int)(a * 256.0); */
8499 q
= float64_mul(float64_256
, a
, s
);
8500 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
8502 /* reciprocal root r */
8503 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
8504 q
= int64_to_float64(q_int
, s
);
8505 q
= float64_add(q
, float64_half
, s
);
8506 q
= float64_div(q
, float64_256
, s
);
8507 q
= float64_sqrt(q
, s
);
8508 q
= float64_div(float64_one
, q
, s
);
8510 /* r in units of 1/256 rounded to nearest */
8511 /* s = (int)(256.0 * r + 0.5); */
8513 q
= float64_mul(q
, float64_256
,s
);
8514 q
= float64_add(q
, float64_half
, s
);
8515 q_int
= float64_to_int64_round_to_zero(q
, s
);
8517 /* return (double)s / 256.0;*/
8518 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
8521 float32
HELPER(rsqrte_f32
)(float32 input
, void *fpstp
)
8523 float_status
*s
= fpstp
;
8524 float32 f32
= float32_squash_input_denormal(input
, s
);
8525 uint32_t val
= float32_val(f32
);
8526 uint32_t f32_sbit
= 0x80000000 & val
;
8527 int32_t f32_exp
= extract32(val
, 23, 8);
8528 uint32_t f32_frac
= extract32(val
, 0, 23);
8534 if (float32_is_any_nan(f32
)) {
8536 if (float32_is_signaling_nan(f32
)) {
8537 float_raise(float_flag_invalid
, s
);
8538 nan
= float32_maybe_silence_nan(f32
);
8540 if (s
->default_nan_mode
) {
8541 nan
= float32_default_nan
;
8544 } else if (float32_is_zero(f32
)) {
8545 float_raise(float_flag_divbyzero
, s
);
8546 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
8547 } else if (float32_is_neg(f32
)) {
8548 float_raise(float_flag_invalid
, s
);
8549 return float32_default_nan
;
8550 } else if (float32_is_infinity(f32
)) {
8551 return float32_zero
;
8554 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
8555 * preserving the parity of the exponent. */
8557 f64_frac
= ((uint64_t) f32_frac
) << 29;
8559 while (extract64(f64_frac
, 51, 1) == 0) {
8560 f64_frac
= f64_frac
<< 1;
8561 f32_exp
= f32_exp
-1;
8563 f64_frac
= extract64(f64_frac
, 0, 51) << 1;
8566 if (extract64(f32_exp
, 0, 1) == 0) {
8567 f64
= make_float64(((uint64_t) f32_sbit
) << 32
8571 f64
= make_float64(((uint64_t) f32_sbit
) << 32
8576 result_exp
= (380 - f32_exp
) / 2;
8578 f64
= recip_sqrt_estimate(f64
, s
);
8580 val64
= float64_val(f64
);
8582 val
= ((result_exp
& 0xff) << 23)
8583 | ((val64
>> 29) & 0x7fffff);
8584 return make_float32(val
);
8587 float64
HELPER(rsqrte_f64
)(float64 input
, void *fpstp
)
8589 float_status
*s
= fpstp
;
8590 float64 f64
= float64_squash_input_denormal(input
, s
);
8591 uint64_t val
= float64_val(f64
);
8592 uint64_t f64_sbit
= 0x8000000000000000ULL
& val
;
8593 int64_t f64_exp
= extract64(val
, 52, 11);
8594 uint64_t f64_frac
= extract64(val
, 0, 52);
8596 uint64_t result_frac
;
8598 if (float64_is_any_nan(f64
)) {
8600 if (float64_is_signaling_nan(f64
)) {
8601 float_raise(float_flag_invalid
, s
);
8602 nan
= float64_maybe_silence_nan(f64
);
8604 if (s
->default_nan_mode
) {
8605 nan
= float64_default_nan
;
8608 } else if (float64_is_zero(f64
)) {
8609 float_raise(float_flag_divbyzero
, s
);
8610 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
8611 } else if (float64_is_neg(f64
)) {
8612 float_raise(float_flag_invalid
, s
);
8613 return float64_default_nan
;
8614 } else if (float64_is_infinity(f64
)) {
8615 return float64_zero
;
8618 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
8619 * preserving the parity of the exponent. */
8622 while (extract64(f64_frac
, 51, 1) == 0) {
8623 f64_frac
= f64_frac
<< 1;
8624 f64_exp
= f64_exp
- 1;
8626 f64_frac
= extract64(f64_frac
, 0, 51) << 1;
8629 if (extract64(f64_exp
, 0, 1) == 0) {
8630 f64
= make_float64(f64_sbit
8634 f64
= make_float64(f64_sbit
8639 result_exp
= (3068 - f64_exp
) / 2;
8641 f64
= recip_sqrt_estimate(f64
, s
);
8643 result_frac
= extract64(float64_val(f64
), 0, 52);
8645 return make_float64(f64_sbit
|
8646 ((result_exp
& 0x7ff) << 52) |
8650 uint32_t HELPER(recpe_u32
)(uint32_t a
, void *fpstp
)
8652 float_status
*s
= fpstp
;
8655 if ((a
& 0x80000000) == 0) {
8659 f64
= make_float64((0x3feULL
<< 52)
8660 | ((int64_t)(a
& 0x7fffffff) << 21));
8662 f64
= recip_estimate(f64
, s
);
8664 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
8667 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, void *fpstp
)
8669 float_status
*fpst
= fpstp
;
8672 if ((a
& 0xc0000000) == 0) {
8676 if (a
& 0x80000000) {
8677 f64
= make_float64((0x3feULL
<< 52)
8678 | ((uint64_t)(a
& 0x7fffffff) << 21));
8679 } else { /* bits 31-30 == '01' */
8680 f64
= make_float64((0x3fdULL
<< 52)
8681 | ((uint64_t)(a
& 0x3fffffff) << 22));
8684 f64
= recip_sqrt_estimate(f64
, fpst
);
8686 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
8689 /* VFPv4 fused multiply-accumulate */
8690 float32
VFP_HELPER(muladd
, s
)(float32 a
, float32 b
, float32 c
, void *fpstp
)
8692 float_status
*fpst
= fpstp
;
8693 return float32_muladd(a
, b
, c
, 0, fpst
);
8696 float64
VFP_HELPER(muladd
, d
)(float64 a
, float64 b
, float64 c
, void *fpstp
)
8698 float_status
*fpst
= fpstp
;
8699 return float64_muladd(a
, b
, c
, 0, fpst
);
8702 /* ARMv8 round to integral */
8703 float32
HELPER(rints_exact
)(float32 x
, void *fp_status
)
8705 return float32_round_to_int(x
, fp_status
);
8708 float64
HELPER(rintd_exact
)(float64 x
, void *fp_status
)
8710 return float64_round_to_int(x
, fp_status
);
8713 float32
HELPER(rints
)(float32 x
, void *fp_status
)
8715 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
8718 ret
= float32_round_to_int(x
, fp_status
);
8720 /* Suppress any inexact exceptions the conversion produced */
8721 if (!(old_flags
& float_flag_inexact
)) {
8722 new_flags
= get_float_exception_flags(fp_status
);
8723 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
8729 float64
HELPER(rintd
)(float64 x
, void *fp_status
)
8731 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
8734 ret
= float64_round_to_int(x
, fp_status
);
8736 new_flags
= get_float_exception_flags(fp_status
);
8738 /* Suppress any inexact exceptions the conversion produced */
8739 if (!(old_flags
& float_flag_inexact
)) {
8740 new_flags
= get_float_exception_flags(fp_status
);
8741 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
8747 /* Convert ARM rounding mode to softfloat */
8748 int arm_rmode_to_sf(int rmode
)
8751 case FPROUNDING_TIEAWAY
:
8752 rmode
= float_round_ties_away
;
8754 case FPROUNDING_ODD
:
8755 /* FIXME: add support for TIEAWAY and ODD */
8756 qemu_log_mask(LOG_UNIMP
, "arm: unimplemented rounding mode: %d\n",
8758 case FPROUNDING_TIEEVEN
:
8760 rmode
= float_round_nearest_even
;
8762 case FPROUNDING_POSINF
:
8763 rmode
= float_round_up
;
8765 case FPROUNDING_NEGINF
:
8766 rmode
= float_round_down
;
8768 case FPROUNDING_ZERO
:
8769 rmode
= float_round_to_zero
;
8776 * The upper bytes of val (above the number specified by 'bytes') must have
8777 * been zeroed out by the caller.
8779 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
8785 /* zlib crc32 converts the accumulator and output to one's complement. */
8786 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
8789 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
8795 /* Linux crc32c converts the output to one's complement. */
8796 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;