4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "qemu/osdep.h"
23 #include "internals.h"
24 #include "qemu-common.h"
25 #include "hw/qdev-properties.h"
26 #if !defined(CONFIG_USER_ONLY)
27 #include "hw/loader.h"
29 #include "hw/arm/arm.h"
30 #include "sysemu/sysemu.h"
31 #include "sysemu/kvm.h"
34 static void arm_cpu_set_pc(CPUState
*cs
, vaddr value
)
36 ARMCPU
*cpu
= ARM_CPU(cs
);
38 cpu
->env
.regs
[15] = value
;
41 static bool arm_cpu_has_work(CPUState
*cs
)
43 ARMCPU
*cpu
= ARM_CPU(cs
);
45 return !cpu
->powered_off
46 && cs
->interrupt_request
&
47 (CPU_INTERRUPT_FIQ
| CPU_INTERRUPT_HARD
48 | CPU_INTERRUPT_VFIQ
| CPU_INTERRUPT_VIRQ
49 | CPU_INTERRUPT_EXITTB
);
52 static void cp_reg_reset(gpointer key
, gpointer value
, gpointer opaque
)
54 /* Reset a single ARMCPRegInfo register */
55 ARMCPRegInfo
*ri
= value
;
58 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
)) {
63 ri
->resetfn(&cpu
->env
, ri
);
67 /* A zero offset is never possible as it would be regs[0]
68 * so we use it to indicate that reset is being handled elsewhere.
69 * This is basically only used for fields in non-core coprocessors
70 * (like the pxa2xx ones).
72 if (!ri
->fieldoffset
) {
76 if (cpreg_field_is_64bit(ri
)) {
77 CPREG_FIELD64(&cpu
->env
, ri
) = ri
->resetvalue
;
79 CPREG_FIELD32(&cpu
->env
, ri
) = ri
->resetvalue
;
83 static void cp_reg_check_reset(gpointer key
, gpointer value
, gpointer opaque
)
85 /* Purely an assertion check: we've already done reset once,
86 * so now check that running the reset for the cpreg doesn't
87 * change its value. This traps bugs where two different cpregs
88 * both try to reset the same state field but to different values.
90 ARMCPRegInfo
*ri
= value
;
92 uint64_t oldvalue
, newvalue
;
94 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
| ARM_CP_NO_RAW
)) {
98 oldvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
99 cp_reg_reset(key
, value
, opaque
);
100 newvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
101 assert(oldvalue
== newvalue
);
104 /* CPUClass::reset() */
105 static void arm_cpu_reset(CPUState
*s
)
107 ARMCPU
*cpu
= ARM_CPU(s
);
108 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(cpu
);
109 CPUARMState
*env
= &cpu
->env
;
111 acc
->parent_reset(s
);
113 memset(env
, 0, offsetof(CPUARMState
, features
));
114 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_reset
, cpu
);
115 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_check_reset
, cpu
);
117 env
->vfp
.xregs
[ARM_VFP_FPSID
] = cpu
->reset_fpsid
;
118 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = cpu
->mvfr0
;
119 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = cpu
->mvfr1
;
120 env
->vfp
.xregs
[ARM_VFP_MVFR2
] = cpu
->mvfr2
;
122 cpu
->powered_off
= cpu
->start_powered_off
;
123 s
->halted
= cpu
->start_powered_off
;
125 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
126 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
129 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
130 /* 64 bit CPUs always start in 64 bit mode */
132 #if defined(CONFIG_USER_ONLY)
133 env
->pstate
= PSTATE_MODE_EL0t
;
134 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
135 env
->cp15
.sctlr_el
[1] |= SCTLR_UCT
| SCTLR_UCI
| SCTLR_DZE
;
136 /* and to the FP/Neon instructions */
137 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 2, 3);
139 /* Reset into the highest available EL */
140 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
141 env
->pstate
= PSTATE_MODE_EL3h
;
142 } else if (arm_feature(env
, ARM_FEATURE_EL2
)) {
143 env
->pstate
= PSTATE_MODE_EL2h
;
145 env
->pstate
= PSTATE_MODE_EL1h
;
147 env
->pc
= cpu
->rvbar
;
150 #if defined(CONFIG_USER_ONLY)
151 /* Userspace expects access to cp10 and cp11 for FP/Neon */
152 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 4, 0xf);
156 #if defined(CONFIG_USER_ONLY)
157 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
158 /* For user mode we must enable access to coprocessors */
159 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
160 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
161 env
->cp15
.c15_cpar
= 3;
162 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
163 env
->cp15
.c15_cpar
= 1;
166 /* SVC mode with interrupts disabled. */
167 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
;
168 env
->daif
= PSTATE_D
| PSTATE_A
| PSTATE_I
| PSTATE_F
;
169 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
170 * clear at reset. Initial SP and PC are loaded from ROM.
173 uint32_t initial_msp
; /* Loaded from 0x0 */
174 uint32_t initial_pc
; /* Loaded from 0x4 */
177 env
->daif
&= ~PSTATE_I
;
180 /* Address zero is covered by ROM which hasn't yet been
181 * copied into physical memory.
183 initial_msp
= ldl_p(rom
);
184 initial_pc
= ldl_p(rom
+ 4);
186 /* Address zero not covered by a ROM blob, or the ROM blob
187 * is in non-modifiable memory and this is a second reset after
188 * it got copied into memory. In the latter case, rom_ptr
189 * will return a NULL pointer and we should use ldl_phys instead.
191 initial_msp
= ldl_phys(s
->as
, 0);
192 initial_pc
= ldl_phys(s
->as
, 4);
195 env
->regs
[13] = initial_msp
& 0xFFFFFFFC;
196 env
->regs
[15] = initial_pc
& ~1;
197 env
->thumb
= initial_pc
& 1;
200 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
201 * executing as AArch32 then check if highvecs are enabled and
202 * adjust the PC accordingly.
204 if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
205 env
->regs
[15] = 0xFFFF0000;
208 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
210 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
211 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
212 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
213 set_float_detect_tininess(float_tininess_before_rounding
,
214 &env
->vfp
.fp_status
);
215 set_float_detect_tininess(float_tininess_before_rounding
,
216 &env
->vfp
.standard_fp_status
);
219 #ifndef CONFIG_USER_ONLY
221 kvm_arm_reset_vcpu(cpu
);
225 hw_breakpoint_update_all(cpu
);
226 hw_watchpoint_update_all(cpu
);
229 bool arm_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
231 CPUClass
*cc
= CPU_GET_CLASS(cs
);
232 CPUARMState
*env
= cs
->env_ptr
;
233 uint32_t cur_el
= arm_current_el(env
);
234 bool secure
= arm_is_secure(env
);
239 if (interrupt_request
& CPU_INTERRUPT_FIQ
) {
241 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
242 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
243 cs
->exception_index
= excp_idx
;
244 env
->exception
.target_el
= target_el
;
245 cc
->do_interrupt(cs
);
249 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
251 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
252 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
253 cs
->exception_index
= excp_idx
;
254 env
->exception
.target_el
= target_el
;
255 cc
->do_interrupt(cs
);
259 if (interrupt_request
& CPU_INTERRUPT_VIRQ
) {
260 excp_idx
= EXCP_VIRQ
;
262 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
263 cs
->exception_index
= excp_idx
;
264 env
->exception
.target_el
= target_el
;
265 cc
->do_interrupt(cs
);
269 if (interrupt_request
& CPU_INTERRUPT_VFIQ
) {
270 excp_idx
= EXCP_VFIQ
;
272 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
273 cs
->exception_index
= excp_idx
;
274 env
->exception
.target_el
= target_el
;
275 cc
->do_interrupt(cs
);
283 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
284 static bool arm_v7m_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
286 CPUClass
*cc
= CPU_GET_CLASS(cs
);
287 ARMCPU
*cpu
= ARM_CPU(cs
);
288 CPUARMState
*env
= &cpu
->env
;
292 if (interrupt_request
& CPU_INTERRUPT_FIQ
293 && !(env
->daif
& PSTATE_F
)) {
294 cs
->exception_index
= EXCP_FIQ
;
295 cc
->do_interrupt(cs
);
298 /* ARMv7-M interrupt return works by loading a magic value
299 * into the PC. On real hardware the load causes the
300 * return to occur. The qemu implementation performs the
301 * jump normally, then does the exception return when the
302 * CPU tries to execute code at the magic address.
303 * This will cause the magic PC value to be pushed to
304 * the stack if an interrupt occurred at the wrong time.
305 * We avoid this by disabling interrupts when
306 * pc contains a magic address.
308 if (interrupt_request
& CPU_INTERRUPT_HARD
309 && !(env
->daif
& PSTATE_I
)
310 && (env
->regs
[15] < 0xfffffff0)) {
311 cs
->exception_index
= EXCP_IRQ
;
312 cc
->do_interrupt(cs
);
319 #ifndef CONFIG_USER_ONLY
320 static void arm_cpu_set_irq(void *opaque
, int irq
, int level
)
322 ARMCPU
*cpu
= opaque
;
323 CPUARMState
*env
= &cpu
->env
;
324 CPUState
*cs
= CPU(cpu
);
325 static const int mask
[] = {
326 [ARM_CPU_IRQ
] = CPU_INTERRUPT_HARD
,
327 [ARM_CPU_FIQ
] = CPU_INTERRUPT_FIQ
,
328 [ARM_CPU_VIRQ
] = CPU_INTERRUPT_VIRQ
,
329 [ARM_CPU_VFIQ
] = CPU_INTERRUPT_VFIQ
335 assert(arm_feature(env
, ARM_FEATURE_EL2
));
340 cpu_interrupt(cs
, mask
[irq
]);
342 cpu_reset_interrupt(cs
, mask
[irq
]);
346 g_assert_not_reached();
350 static void arm_cpu_kvm_set_irq(void *opaque
, int irq
, int level
)
353 ARMCPU
*cpu
= opaque
;
354 CPUState
*cs
= CPU(cpu
);
355 int kvm_irq
= KVM_ARM_IRQ_TYPE_CPU
<< KVM_ARM_IRQ_TYPE_SHIFT
;
359 kvm_irq
|= KVM_ARM_IRQ_CPU_IRQ
;
362 kvm_irq
|= KVM_ARM_IRQ_CPU_FIQ
;
365 g_assert_not_reached();
367 kvm_irq
|= cs
->cpu_index
<< KVM_ARM_IRQ_VCPU_SHIFT
;
368 kvm_set_irq(kvm_state
, kvm_irq
, level
? 1 : 0);
372 static bool arm_cpu_is_big_endian(CPUState
*cs
)
374 ARMCPU
*cpu
= ARM_CPU(cs
);
375 CPUARMState
*env
= &cpu
->env
;
378 cpu_synchronize_state(cs
);
380 /* In 32bit guest endianness is determined by looking at CPSR's E bit */
382 return (env
->uncached_cpsr
& CPSR_E
) ? 1 : 0;
385 cur_el
= arm_current_el(env
);
388 return (env
->cp15
.sctlr_el
[1] & SCTLR_E0E
) != 0;
391 return (env
->cp15
.sctlr_el
[cur_el
] & SCTLR_EE
) != 0;
396 static inline void set_feature(CPUARMState
*env
, int feature
)
398 env
->features
|= 1ULL << feature
;
401 static inline void unset_feature(CPUARMState
*env
, int feature
)
403 env
->features
&= ~(1ULL << feature
);
407 print_insn_thumb1(bfd_vma pc
, disassemble_info
*info
)
409 return print_insn_arm(pc
| 1, info
);
412 static void arm_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
414 ARMCPU
*ac
= ARM_CPU(cpu
);
415 CPUARMState
*env
= &ac
->env
;
418 /* We might not be compiled with the A64 disassembler
419 * because it needs a C++ compiler. Leave print_insn
420 * unset in this case to use the caller default behaviour.
422 #if defined(CONFIG_ARM_A64_DIS)
423 info
->print_insn
= print_insn_arm_a64
;
425 } else if (env
->thumb
) {
426 info
->print_insn
= print_insn_thumb1
;
428 info
->print_insn
= print_insn_arm
;
430 if (env
->bswap_code
) {
431 #ifdef TARGET_WORDS_BIGENDIAN
432 info
->endian
= BFD_ENDIAN_LITTLE
;
434 info
->endian
= BFD_ENDIAN_BIG
;
439 #define ARM_CPUS_PER_CLUSTER 8
441 static void arm_cpu_initfn(Object
*obj
)
443 CPUState
*cs
= CPU(obj
);
444 ARMCPU
*cpu
= ARM_CPU(obj
);
448 cs
->env_ptr
= &cpu
->env
;
449 cpu_exec_init(cs
, &error_abort
);
450 cpu
->cp_regs
= g_hash_table_new_full(g_int_hash
, g_int_equal
,
453 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
454 * We don't support setting cluster ID ([16..23]) (known as Aff2
455 * in later ARM ARM versions), or any of the higher affinity level fields,
456 * so these bits always RAZ.
458 Aff1
= cs
->cpu_index
/ ARM_CPUS_PER_CLUSTER
;
459 Aff0
= cs
->cpu_index
% ARM_CPUS_PER_CLUSTER
;
460 cpu
->mp_affinity
= (Aff1
<< ARM_AFF1_SHIFT
) | Aff0
;
462 #ifndef CONFIG_USER_ONLY
463 /* Our inbound IRQ and FIQ lines */
465 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
466 * the same interface as non-KVM CPUs.
468 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_kvm_set_irq
, 4);
470 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_set_irq
, 4);
473 cpu
->gt_timer
[GTIMER_PHYS
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
474 arm_gt_ptimer_cb
, cpu
);
475 cpu
->gt_timer
[GTIMER_VIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
476 arm_gt_vtimer_cb
, cpu
);
477 cpu
->gt_timer
[GTIMER_HYP
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
478 arm_gt_htimer_cb
, cpu
);
479 cpu
->gt_timer
[GTIMER_SEC
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
480 arm_gt_stimer_cb
, cpu
);
481 qdev_init_gpio_out(DEVICE(cpu
), cpu
->gt_timer_outputs
,
482 ARRAY_SIZE(cpu
->gt_timer_outputs
));
485 /* DTB consumers generally don't in fact care what the 'compatible'
486 * string is, so always provide some string and trust that a hypothetical
487 * picky DTB consumer will also provide a helpful error message.
489 cpu
->dtb_compatible
= "qemu,unknown";
490 cpu
->psci_version
= 1; /* By default assume PSCI v0.1 */
491 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_NONE
;
494 cpu
->psci_version
= 2; /* TCG implements PSCI 0.2 */
497 arm_translate_init();
502 static Property arm_cpu_reset_cbar_property
=
503 DEFINE_PROP_UINT64("reset-cbar", ARMCPU
, reset_cbar
, 0);
505 static Property arm_cpu_reset_hivecs_property
=
506 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU
, reset_hivecs
, false);
508 static Property arm_cpu_rvbar_property
=
509 DEFINE_PROP_UINT64("rvbar", ARMCPU
, rvbar
, 0);
511 static Property arm_cpu_has_el3_property
=
512 DEFINE_PROP_BOOL("has_el3", ARMCPU
, has_el3
, true);
514 static Property arm_cpu_has_mpu_property
=
515 DEFINE_PROP_BOOL("has-mpu", ARMCPU
, has_mpu
, true);
517 static Property arm_cpu_pmsav7_dregion_property
=
518 DEFINE_PROP_UINT32("pmsav7-dregion", ARMCPU
, pmsav7_dregion
, 16);
520 static void arm_cpu_post_init(Object
*obj
)
522 ARMCPU
*cpu
= ARM_CPU(obj
);
524 if (arm_feature(&cpu
->env
, ARM_FEATURE_CBAR
) ||
525 arm_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
)) {
526 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_cbar_property
,
530 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
531 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_hivecs_property
,
535 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
536 qdev_property_add_static(DEVICE(obj
), &arm_cpu_rvbar_property
,
540 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
541 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
542 * prevent "has_el3" from existing on CPUs which cannot support EL3.
544 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el3_property
,
547 #ifndef CONFIG_USER_ONLY
548 object_property_add_link(obj
, "secure-memory",
550 (Object
**)&cpu
->secure_memory
,
551 qdev_prop_allow_set_link_before_realize
,
552 OBJ_PROP_LINK_UNREF_ON_RELEASE
,
557 if (arm_feature(&cpu
->env
, ARM_FEATURE_MPU
)) {
558 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_mpu_property
,
560 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
561 qdev_property_add_static(DEVICE(obj
),
562 &arm_cpu_pmsav7_dregion_property
,
569 static void arm_cpu_finalizefn(Object
*obj
)
571 ARMCPU
*cpu
= ARM_CPU(obj
);
572 g_hash_table_destroy(cpu
->cp_regs
);
575 static void arm_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
577 CPUState
*cs
= CPU(dev
);
578 ARMCPU
*cpu
= ARM_CPU(dev
);
579 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(dev
);
580 CPUARMState
*env
= &cpu
->env
;
582 /* Some features automatically imply others: */
583 if (arm_feature(env
, ARM_FEATURE_V8
)) {
584 set_feature(env
, ARM_FEATURE_V7
);
585 set_feature(env
, ARM_FEATURE_ARM_DIV
);
586 set_feature(env
, ARM_FEATURE_LPAE
);
588 if (arm_feature(env
, ARM_FEATURE_V7
)) {
589 set_feature(env
, ARM_FEATURE_VAPA
);
590 set_feature(env
, ARM_FEATURE_THUMB2
);
591 set_feature(env
, ARM_FEATURE_MPIDR
);
592 if (!arm_feature(env
, ARM_FEATURE_M
)) {
593 set_feature(env
, ARM_FEATURE_V6K
);
595 set_feature(env
, ARM_FEATURE_V6
);
598 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
599 set_feature(env
, ARM_FEATURE_V6
);
600 set_feature(env
, ARM_FEATURE_MVFR
);
602 if (arm_feature(env
, ARM_FEATURE_V6
)) {
603 set_feature(env
, ARM_FEATURE_V5
);
604 if (!arm_feature(env
, ARM_FEATURE_M
)) {
605 set_feature(env
, ARM_FEATURE_AUXCR
);
608 if (arm_feature(env
, ARM_FEATURE_V5
)) {
609 set_feature(env
, ARM_FEATURE_V4T
);
611 if (arm_feature(env
, ARM_FEATURE_M
)) {
612 set_feature(env
, ARM_FEATURE_THUMB_DIV
);
614 if (arm_feature(env
, ARM_FEATURE_ARM_DIV
)) {
615 set_feature(env
, ARM_FEATURE_THUMB_DIV
);
617 if (arm_feature(env
, ARM_FEATURE_VFP4
)) {
618 set_feature(env
, ARM_FEATURE_VFP3
);
619 set_feature(env
, ARM_FEATURE_VFP_FP16
);
621 if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
622 set_feature(env
, ARM_FEATURE_VFP
);
624 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
625 set_feature(env
, ARM_FEATURE_V7MP
);
626 set_feature(env
, ARM_FEATURE_PXN
);
628 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
629 set_feature(env
, ARM_FEATURE_CBAR
);
631 if (arm_feature(env
, ARM_FEATURE_THUMB2
) &&
632 !arm_feature(env
, ARM_FEATURE_M
)) {
633 set_feature(env
, ARM_FEATURE_THUMB_DSP
);
636 if (cpu
->reset_hivecs
) {
637 cpu
->reset_sctlr
|= (1 << 13);
641 /* If the has_el3 CPU property is disabled then we need to disable the
644 unset_feature(env
, ARM_FEATURE_EL3
);
646 /* Disable the security extension feature bits in the processor feature
647 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
649 cpu
->id_pfr1
&= ~0xf0;
650 cpu
->id_aa64pfr0
&= ~0xf000;
654 unset_feature(env
, ARM_FEATURE_MPU
);
657 if (arm_feature(env
, ARM_FEATURE_MPU
) &&
658 arm_feature(env
, ARM_FEATURE_V7
)) {
659 uint32_t nr
= cpu
->pmsav7_dregion
;
662 error_setg(errp
, "PMSAv7 MPU #regions invalid %" PRIu32
, nr
);
667 env
->pmsav7
.drbar
= g_new0(uint32_t, nr
);
668 env
->pmsav7
.drsr
= g_new0(uint32_t, nr
);
669 env
->pmsav7
.dracr
= g_new0(uint32_t, nr
);
673 register_cp_regs_for_features(cpu
);
674 arm_cpu_register_gdb_regs_for_features(cpu
);
676 init_cpreg_list(cpu
);
678 #ifndef CONFIG_USER_ONLY
688 if (!cpu
->secure_memory
) {
689 cpu
->secure_memory
= cs
->memory
;
691 as
= address_space_init_shareable(cpu
->secure_memory
,
692 "cpu-secure-memory");
693 cpu_address_space_init(cs
, as
, ARMASIdx_S
);
695 cpu_address_space_init(cs
,
696 address_space_init_shareable(cs
->memory
,
704 acc
->parent_realize(dev
, errp
);
707 static ObjectClass
*arm_cpu_class_by_name(const char *cpu_model
)
717 cpuname
= g_strsplit(cpu_model
, ",", 1);
718 typename
= g_strdup_printf("%s-" TYPE_ARM_CPU
, cpuname
[0]);
719 oc
= object_class_by_name(typename
);
722 if (!oc
|| !object_class_dynamic_cast(oc
, TYPE_ARM_CPU
) ||
723 object_class_is_abstract(oc
)) {
729 /* CPU models. These are not needed for the AArch64 linux-user build. */
730 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
732 static void arm926_initfn(Object
*obj
)
734 ARMCPU
*cpu
= ARM_CPU(obj
);
736 cpu
->dtb_compatible
= "arm,arm926";
737 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
738 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
739 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
740 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
741 cpu
->midr
= 0x41069265;
742 cpu
->reset_fpsid
= 0x41011090;
743 cpu
->ctr
= 0x1dd20d2;
744 cpu
->reset_sctlr
= 0x00090078;
747 static void arm946_initfn(Object
*obj
)
749 ARMCPU
*cpu
= ARM_CPU(obj
);
751 cpu
->dtb_compatible
= "arm,arm946";
752 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
753 set_feature(&cpu
->env
, ARM_FEATURE_MPU
);
754 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
755 cpu
->midr
= 0x41059461;
756 cpu
->ctr
= 0x0f004006;
757 cpu
->reset_sctlr
= 0x00000078;
760 static void arm1026_initfn(Object
*obj
)
762 ARMCPU
*cpu
= ARM_CPU(obj
);
764 cpu
->dtb_compatible
= "arm,arm1026";
765 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
766 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
767 set_feature(&cpu
->env
, ARM_FEATURE_AUXCR
);
768 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
769 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
770 cpu
->midr
= 0x4106a262;
771 cpu
->reset_fpsid
= 0x410110a0;
772 cpu
->ctr
= 0x1dd20d2;
773 cpu
->reset_sctlr
= 0x00090078;
774 cpu
->reset_auxcr
= 1;
776 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
777 ARMCPRegInfo ifar
= {
778 .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
780 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifar_ns
),
783 define_one_arm_cp_reg(cpu
, &ifar
);
787 static void arm1136_r2_initfn(Object
*obj
)
789 ARMCPU
*cpu
= ARM_CPU(obj
);
790 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
791 * older core than plain "arm1136". In particular this does not
792 * have the v6K features.
793 * These ID register values are correct for 1136 but may be wrong
794 * for 1136_r2 (in particular r0p2 does not actually implement most
795 * of the ID registers).
798 cpu
->dtb_compatible
= "arm,arm1136";
799 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
800 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
801 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
802 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
803 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
804 cpu
->midr
= 0x4107b362;
805 cpu
->reset_fpsid
= 0x410120b4;
806 cpu
->mvfr0
= 0x11111111;
807 cpu
->mvfr1
= 0x00000000;
808 cpu
->ctr
= 0x1dd20d2;
809 cpu
->reset_sctlr
= 0x00050078;
810 cpu
->id_pfr0
= 0x111;
814 cpu
->id_mmfr0
= 0x01130003;
815 cpu
->id_mmfr1
= 0x10030302;
816 cpu
->id_mmfr2
= 0x01222110;
817 cpu
->id_isar0
= 0x00140011;
818 cpu
->id_isar1
= 0x12002111;
819 cpu
->id_isar2
= 0x11231111;
820 cpu
->id_isar3
= 0x01102131;
821 cpu
->id_isar4
= 0x141;
822 cpu
->reset_auxcr
= 7;
825 static void arm1136_initfn(Object
*obj
)
827 ARMCPU
*cpu
= ARM_CPU(obj
);
829 cpu
->dtb_compatible
= "arm,arm1136";
830 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
831 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
832 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
833 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
834 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
835 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
836 cpu
->midr
= 0x4117b363;
837 cpu
->reset_fpsid
= 0x410120b4;
838 cpu
->mvfr0
= 0x11111111;
839 cpu
->mvfr1
= 0x00000000;
840 cpu
->ctr
= 0x1dd20d2;
841 cpu
->reset_sctlr
= 0x00050078;
842 cpu
->id_pfr0
= 0x111;
846 cpu
->id_mmfr0
= 0x01130003;
847 cpu
->id_mmfr1
= 0x10030302;
848 cpu
->id_mmfr2
= 0x01222110;
849 cpu
->id_isar0
= 0x00140011;
850 cpu
->id_isar1
= 0x12002111;
851 cpu
->id_isar2
= 0x11231111;
852 cpu
->id_isar3
= 0x01102131;
853 cpu
->id_isar4
= 0x141;
854 cpu
->reset_auxcr
= 7;
857 static void arm1176_initfn(Object
*obj
)
859 ARMCPU
*cpu
= ARM_CPU(obj
);
861 cpu
->dtb_compatible
= "arm,arm1176";
862 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
863 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
864 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
865 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
866 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
867 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
868 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
869 cpu
->midr
= 0x410fb767;
870 cpu
->reset_fpsid
= 0x410120b5;
871 cpu
->mvfr0
= 0x11111111;
872 cpu
->mvfr1
= 0x00000000;
873 cpu
->ctr
= 0x1dd20d2;
874 cpu
->reset_sctlr
= 0x00050078;
875 cpu
->id_pfr0
= 0x111;
879 cpu
->id_mmfr0
= 0x01130003;
880 cpu
->id_mmfr1
= 0x10030302;
881 cpu
->id_mmfr2
= 0x01222100;
882 cpu
->id_isar0
= 0x0140011;
883 cpu
->id_isar1
= 0x12002111;
884 cpu
->id_isar2
= 0x11231121;
885 cpu
->id_isar3
= 0x01102131;
886 cpu
->id_isar4
= 0x01141;
887 cpu
->reset_auxcr
= 7;
890 static void arm11mpcore_initfn(Object
*obj
)
892 ARMCPU
*cpu
= ARM_CPU(obj
);
894 cpu
->dtb_compatible
= "arm,arm11mpcore";
895 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
896 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
897 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
898 set_feature(&cpu
->env
, ARM_FEATURE_MPIDR
);
899 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
900 cpu
->midr
= 0x410fb022;
901 cpu
->reset_fpsid
= 0x410120b4;
902 cpu
->mvfr0
= 0x11111111;
903 cpu
->mvfr1
= 0x00000000;
904 cpu
->ctr
= 0x1d192992; /* 32K icache 32K dcache */
905 cpu
->id_pfr0
= 0x111;
909 cpu
->id_mmfr0
= 0x01100103;
910 cpu
->id_mmfr1
= 0x10020302;
911 cpu
->id_mmfr2
= 0x01222000;
912 cpu
->id_isar0
= 0x00100011;
913 cpu
->id_isar1
= 0x12002111;
914 cpu
->id_isar2
= 0x11221011;
915 cpu
->id_isar3
= 0x01102131;
916 cpu
->id_isar4
= 0x141;
917 cpu
->reset_auxcr
= 1;
920 static void cortex_m3_initfn(Object
*obj
)
922 ARMCPU
*cpu
= ARM_CPU(obj
);
923 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
924 set_feature(&cpu
->env
, ARM_FEATURE_M
);
925 cpu
->midr
= 0x410fc231;
928 static void cortex_m4_initfn(Object
*obj
)
930 ARMCPU
*cpu
= ARM_CPU(obj
);
932 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
933 set_feature(&cpu
->env
, ARM_FEATURE_M
);
934 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
);
935 cpu
->midr
= 0x410fc240; /* r0p0 */
937 static void arm_v7m_class_init(ObjectClass
*oc
, void *data
)
939 CPUClass
*cc
= CPU_CLASS(oc
);
941 #ifndef CONFIG_USER_ONLY
942 cc
->do_interrupt
= arm_v7m_cpu_do_interrupt
;
945 cc
->cpu_exec_interrupt
= arm_v7m_cpu_exec_interrupt
;
948 static const ARMCPRegInfo cortexr5_cp_reginfo
[] = {
949 /* Dummy the TCM region regs for the moment */
950 { .name
= "ATCM", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
951 .access
= PL1_RW
, .type
= ARM_CP_CONST
},
952 { .name
= "BTCM", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
953 .access
= PL1_RW
, .type
= ARM_CP_CONST
},
957 static void cortex_r5_initfn(Object
*obj
)
959 ARMCPU
*cpu
= ARM_CPU(obj
);
961 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
962 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DIV
);
963 set_feature(&cpu
->env
, ARM_FEATURE_ARM_DIV
);
964 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
965 set_feature(&cpu
->env
, ARM_FEATURE_MPU
);
966 cpu
->midr
= 0x411fc153; /* r1p3 */
967 cpu
->id_pfr0
= 0x0131;
968 cpu
->id_pfr1
= 0x001;
969 cpu
->id_dfr0
= 0x010400;
971 cpu
->id_mmfr0
= 0x0210030;
972 cpu
->id_mmfr1
= 0x00000000;
973 cpu
->id_mmfr2
= 0x01200000;
974 cpu
->id_mmfr3
= 0x0211;
975 cpu
->id_isar0
= 0x2101111;
976 cpu
->id_isar1
= 0x13112111;
977 cpu
->id_isar2
= 0x21232141;
978 cpu
->id_isar3
= 0x01112131;
979 cpu
->id_isar4
= 0x0010142;
981 cpu
->mp_is_up
= true;
982 define_arm_cp_regs(cpu
, cortexr5_cp_reginfo
);
985 static const ARMCPRegInfo cortexa8_cp_reginfo
[] = {
986 { .name
= "L2LOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 0,
987 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
988 { .name
= "L2AUXCR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
989 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
993 static void cortex_a8_initfn(Object
*obj
)
995 ARMCPU
*cpu
= ARM_CPU(obj
);
997 cpu
->dtb_compatible
= "arm,cortex-a8";
998 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
999 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
1000 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1001 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1002 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1003 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1004 cpu
->midr
= 0x410fc080;
1005 cpu
->reset_fpsid
= 0x410330c0;
1006 cpu
->mvfr0
= 0x11110222;
1007 cpu
->mvfr1
= 0x00011100;
1008 cpu
->ctr
= 0x82048004;
1009 cpu
->reset_sctlr
= 0x00c50078;
1010 cpu
->id_pfr0
= 0x1031;
1011 cpu
->id_pfr1
= 0x11;
1012 cpu
->id_dfr0
= 0x400;
1014 cpu
->id_mmfr0
= 0x31100003;
1015 cpu
->id_mmfr1
= 0x20000000;
1016 cpu
->id_mmfr2
= 0x01202000;
1017 cpu
->id_mmfr3
= 0x11;
1018 cpu
->id_isar0
= 0x00101111;
1019 cpu
->id_isar1
= 0x12112111;
1020 cpu
->id_isar2
= 0x21232031;
1021 cpu
->id_isar3
= 0x11112131;
1022 cpu
->id_isar4
= 0x00111142;
1023 cpu
->dbgdidr
= 0x15141000;
1024 cpu
->clidr
= (1 << 27) | (2 << 24) | 3;
1025 cpu
->ccsidr
[0] = 0xe007e01a; /* 16k L1 dcache. */
1026 cpu
->ccsidr
[1] = 0x2007e01a; /* 16k L1 icache. */
1027 cpu
->ccsidr
[2] = 0xf0000000; /* No L2 icache. */
1028 cpu
->reset_auxcr
= 2;
1029 define_arm_cp_regs(cpu
, cortexa8_cp_reginfo
);
1032 static const ARMCPRegInfo cortexa9_cp_reginfo
[] = {
1033 /* power_control should be set to maximum latency. Again,
1034 * default to 0 and set by private hook
1036 { .name
= "A9_PWRCTL", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
1037 .access
= PL1_RW
, .resetvalue
= 0,
1038 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_control
) },
1039 { .name
= "A9_DIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 1,
1040 .access
= PL1_RW
, .resetvalue
= 0,
1041 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_diagnostic
) },
1042 { .name
= "A9_PWRDIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 2,
1043 .access
= PL1_RW
, .resetvalue
= 0,
1044 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_diagnostic
) },
1045 { .name
= "NEONBUSY", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
1046 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1047 /* TLB lockdown control */
1048 { .name
= "TLB_LOCKR", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 2,
1049 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
1050 { .name
= "TLB_LOCKW", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 4,
1051 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
1052 { .name
= "TLB_VA", .cp
= 15, .crn
= 15, .crm
= 5, .opc1
= 5, .opc2
= 2,
1053 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1054 { .name
= "TLB_PA", .cp
= 15, .crn
= 15, .crm
= 6, .opc1
= 5, .opc2
= 2,
1055 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1056 { .name
= "TLB_ATTR", .cp
= 15, .crn
= 15, .crm
= 7, .opc1
= 5, .opc2
= 2,
1057 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1061 static void cortex_a9_initfn(Object
*obj
)
1063 ARMCPU
*cpu
= ARM_CPU(obj
);
1065 cpu
->dtb_compatible
= "arm,cortex-a9";
1066 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1067 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
1068 set_feature(&cpu
->env
, ARM_FEATURE_VFP_FP16
);
1069 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1070 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1071 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1072 /* Note that A9 supports the MP extensions even for
1073 * A9UP and single-core A9MP (which are both different
1074 * and valid configurations; we don't model A9UP).
1076 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
1077 set_feature(&cpu
->env
, ARM_FEATURE_CBAR
);
1078 cpu
->midr
= 0x410fc090;
1079 cpu
->reset_fpsid
= 0x41033090;
1080 cpu
->mvfr0
= 0x11110222;
1081 cpu
->mvfr1
= 0x01111111;
1082 cpu
->ctr
= 0x80038003;
1083 cpu
->reset_sctlr
= 0x00c50078;
1084 cpu
->id_pfr0
= 0x1031;
1085 cpu
->id_pfr1
= 0x11;
1086 cpu
->id_dfr0
= 0x000;
1088 cpu
->id_mmfr0
= 0x00100103;
1089 cpu
->id_mmfr1
= 0x20000000;
1090 cpu
->id_mmfr2
= 0x01230000;
1091 cpu
->id_mmfr3
= 0x00002111;
1092 cpu
->id_isar0
= 0x00101111;
1093 cpu
->id_isar1
= 0x13112111;
1094 cpu
->id_isar2
= 0x21232041;
1095 cpu
->id_isar3
= 0x11112131;
1096 cpu
->id_isar4
= 0x00111142;
1097 cpu
->dbgdidr
= 0x35141000;
1098 cpu
->clidr
= (1 << 27) | (1 << 24) | 3;
1099 cpu
->ccsidr
[0] = 0xe00fe019; /* 16k L1 dcache. */
1100 cpu
->ccsidr
[1] = 0x200fe019; /* 16k L1 icache. */
1101 define_arm_cp_regs(cpu
, cortexa9_cp_reginfo
);
1104 #ifndef CONFIG_USER_ONLY
1105 static uint64_t a15_l2ctlr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1107 /* Linux wants the number of processors from here.
1108 * Might as well set the interrupt-controller bit too.
1110 return ((smp_cpus
- 1) << 24) | (1 << 23);
1114 static const ARMCPRegInfo cortexa15_cp_reginfo
[] = {
1115 #ifndef CONFIG_USER_ONLY
1116 { .name
= "L2CTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
1117 .access
= PL1_RW
, .resetvalue
= 0, .readfn
= a15_l2ctlr_read
,
1118 .writefn
= arm_cp_write_ignore
, },
1120 { .name
= "L2ECTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 3,
1121 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1125 static void cortex_a15_initfn(Object
*obj
)
1127 ARMCPU
*cpu
= ARM_CPU(obj
);
1129 cpu
->dtb_compatible
= "arm,cortex-a15";
1130 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1131 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
1132 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1133 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1134 set_feature(&cpu
->env
, ARM_FEATURE_ARM_DIV
);
1135 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
1136 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1137 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
1138 set_feature(&cpu
->env
, ARM_FEATURE_LPAE
);
1139 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1140 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A15
;
1141 cpu
->midr
= 0x412fc0f1;
1142 cpu
->reset_fpsid
= 0x410430f0;
1143 cpu
->mvfr0
= 0x10110222;
1144 cpu
->mvfr1
= 0x11111111;
1145 cpu
->ctr
= 0x8444c004;
1146 cpu
->reset_sctlr
= 0x00c50078;
1147 cpu
->id_pfr0
= 0x00001131;
1148 cpu
->id_pfr1
= 0x00011011;
1149 cpu
->id_dfr0
= 0x02010555;
1150 cpu
->id_afr0
= 0x00000000;
1151 cpu
->id_mmfr0
= 0x10201105;
1152 cpu
->id_mmfr1
= 0x20000000;
1153 cpu
->id_mmfr2
= 0x01240000;
1154 cpu
->id_mmfr3
= 0x02102211;
1155 cpu
->id_isar0
= 0x02101110;
1156 cpu
->id_isar1
= 0x13112111;
1157 cpu
->id_isar2
= 0x21232041;
1158 cpu
->id_isar3
= 0x11112131;
1159 cpu
->id_isar4
= 0x10011142;
1160 cpu
->dbgdidr
= 0x3515f021;
1161 cpu
->clidr
= 0x0a200023;
1162 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
1163 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
1164 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
1165 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
);
1168 static void ti925t_initfn(Object
*obj
)
1170 ARMCPU
*cpu
= ARM_CPU(obj
);
1171 set_feature(&cpu
->env
, ARM_FEATURE_V4T
);
1172 set_feature(&cpu
->env
, ARM_FEATURE_OMAPCP
);
1173 cpu
->midr
= ARM_CPUID_TI925T
;
1174 cpu
->ctr
= 0x5109149;
1175 cpu
->reset_sctlr
= 0x00000070;
1178 static void sa1100_initfn(Object
*obj
)
1180 ARMCPU
*cpu
= ARM_CPU(obj
);
1182 cpu
->dtb_compatible
= "intel,sa1100";
1183 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
1184 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1185 cpu
->midr
= 0x4401A11B;
1186 cpu
->reset_sctlr
= 0x00000070;
1189 static void sa1110_initfn(Object
*obj
)
1191 ARMCPU
*cpu
= ARM_CPU(obj
);
1192 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
1193 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1194 cpu
->midr
= 0x6901B119;
1195 cpu
->reset_sctlr
= 0x00000070;
1198 static void pxa250_initfn(Object
*obj
)
1200 ARMCPU
*cpu
= ARM_CPU(obj
);
1202 cpu
->dtb_compatible
= "marvell,xscale";
1203 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1204 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1205 cpu
->midr
= 0x69052100;
1206 cpu
->ctr
= 0xd172172;
1207 cpu
->reset_sctlr
= 0x00000078;
1210 static void pxa255_initfn(Object
*obj
)
1212 ARMCPU
*cpu
= ARM_CPU(obj
);
1214 cpu
->dtb_compatible
= "marvell,xscale";
1215 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1216 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1217 cpu
->midr
= 0x69052d00;
1218 cpu
->ctr
= 0xd172172;
1219 cpu
->reset_sctlr
= 0x00000078;
1222 static void pxa260_initfn(Object
*obj
)
1224 ARMCPU
*cpu
= ARM_CPU(obj
);
1226 cpu
->dtb_compatible
= "marvell,xscale";
1227 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1228 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1229 cpu
->midr
= 0x69052903;
1230 cpu
->ctr
= 0xd172172;
1231 cpu
->reset_sctlr
= 0x00000078;
1234 static void pxa261_initfn(Object
*obj
)
1236 ARMCPU
*cpu
= ARM_CPU(obj
);
1238 cpu
->dtb_compatible
= "marvell,xscale";
1239 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1240 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1241 cpu
->midr
= 0x69052d05;
1242 cpu
->ctr
= 0xd172172;
1243 cpu
->reset_sctlr
= 0x00000078;
1246 static void pxa262_initfn(Object
*obj
)
1248 ARMCPU
*cpu
= ARM_CPU(obj
);
1250 cpu
->dtb_compatible
= "marvell,xscale";
1251 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1252 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1253 cpu
->midr
= 0x69052d06;
1254 cpu
->ctr
= 0xd172172;
1255 cpu
->reset_sctlr
= 0x00000078;
1258 static void pxa270a0_initfn(Object
*obj
)
1260 ARMCPU
*cpu
= ARM_CPU(obj
);
1262 cpu
->dtb_compatible
= "marvell,xscale";
1263 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1264 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1265 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1266 cpu
->midr
= 0x69054110;
1267 cpu
->ctr
= 0xd172172;
1268 cpu
->reset_sctlr
= 0x00000078;
1271 static void pxa270a1_initfn(Object
*obj
)
1273 ARMCPU
*cpu
= ARM_CPU(obj
);
1275 cpu
->dtb_compatible
= "marvell,xscale";
1276 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1277 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1278 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1279 cpu
->midr
= 0x69054111;
1280 cpu
->ctr
= 0xd172172;
1281 cpu
->reset_sctlr
= 0x00000078;
1284 static void pxa270b0_initfn(Object
*obj
)
1286 ARMCPU
*cpu
= ARM_CPU(obj
);
1288 cpu
->dtb_compatible
= "marvell,xscale";
1289 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1290 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1291 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1292 cpu
->midr
= 0x69054112;
1293 cpu
->ctr
= 0xd172172;
1294 cpu
->reset_sctlr
= 0x00000078;
1297 static void pxa270b1_initfn(Object
*obj
)
1299 ARMCPU
*cpu
= ARM_CPU(obj
);
1301 cpu
->dtb_compatible
= "marvell,xscale";
1302 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1303 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1304 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1305 cpu
->midr
= 0x69054113;
1306 cpu
->ctr
= 0xd172172;
1307 cpu
->reset_sctlr
= 0x00000078;
1310 static void pxa270c0_initfn(Object
*obj
)
1312 ARMCPU
*cpu
= ARM_CPU(obj
);
1314 cpu
->dtb_compatible
= "marvell,xscale";
1315 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1316 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1317 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1318 cpu
->midr
= 0x69054114;
1319 cpu
->ctr
= 0xd172172;
1320 cpu
->reset_sctlr
= 0x00000078;
1323 static void pxa270c5_initfn(Object
*obj
)
1325 ARMCPU
*cpu
= ARM_CPU(obj
);
1327 cpu
->dtb_compatible
= "marvell,xscale";
1328 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1329 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1330 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1331 cpu
->midr
= 0x69054117;
1332 cpu
->ctr
= 0xd172172;
1333 cpu
->reset_sctlr
= 0x00000078;
1336 #ifdef CONFIG_USER_ONLY
1337 static void arm_any_initfn(Object
*obj
)
1339 ARMCPU
*cpu
= ARM_CPU(obj
);
1340 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
1341 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
1342 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1343 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1344 set_feature(&cpu
->env
, ARM_FEATURE_V8_AES
);
1345 set_feature(&cpu
->env
, ARM_FEATURE_V8_SHA1
);
1346 set_feature(&cpu
->env
, ARM_FEATURE_V8_SHA256
);
1347 set_feature(&cpu
->env
, ARM_FEATURE_V8_PMULL
);
1348 set_feature(&cpu
->env
, ARM_FEATURE_CRC
);
1349 cpu
->midr
= 0xffffffff;
1353 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1355 typedef struct ARMCPUInfo
{
1357 void (*initfn
)(Object
*obj
);
1358 void (*class_init
)(ObjectClass
*oc
, void *data
);
1361 static const ARMCPUInfo arm_cpus
[] = {
1362 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1363 { .name
= "arm926", .initfn
= arm926_initfn
},
1364 { .name
= "arm946", .initfn
= arm946_initfn
},
1365 { .name
= "arm1026", .initfn
= arm1026_initfn
},
1366 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1367 * older core than plain "arm1136". In particular this does not
1368 * have the v6K features.
1370 { .name
= "arm1136-r2", .initfn
= arm1136_r2_initfn
},
1371 { .name
= "arm1136", .initfn
= arm1136_initfn
},
1372 { .name
= "arm1176", .initfn
= arm1176_initfn
},
1373 { .name
= "arm11mpcore", .initfn
= arm11mpcore_initfn
},
1374 { .name
= "cortex-m3", .initfn
= cortex_m3_initfn
,
1375 .class_init
= arm_v7m_class_init
},
1376 { .name
= "cortex-m4", .initfn
= cortex_m4_initfn
,
1377 .class_init
= arm_v7m_class_init
},
1378 { .name
= "cortex-r5", .initfn
= cortex_r5_initfn
},
1379 { .name
= "cortex-a8", .initfn
= cortex_a8_initfn
},
1380 { .name
= "cortex-a9", .initfn
= cortex_a9_initfn
},
1381 { .name
= "cortex-a15", .initfn
= cortex_a15_initfn
},
1382 { .name
= "ti925t", .initfn
= ti925t_initfn
},
1383 { .name
= "sa1100", .initfn
= sa1100_initfn
},
1384 { .name
= "sa1110", .initfn
= sa1110_initfn
},
1385 { .name
= "pxa250", .initfn
= pxa250_initfn
},
1386 { .name
= "pxa255", .initfn
= pxa255_initfn
},
1387 { .name
= "pxa260", .initfn
= pxa260_initfn
},
1388 { .name
= "pxa261", .initfn
= pxa261_initfn
},
1389 { .name
= "pxa262", .initfn
= pxa262_initfn
},
1390 /* "pxa270" is an alias for "pxa270-a0" */
1391 { .name
= "pxa270", .initfn
= pxa270a0_initfn
},
1392 { .name
= "pxa270-a0", .initfn
= pxa270a0_initfn
},
1393 { .name
= "pxa270-a1", .initfn
= pxa270a1_initfn
},
1394 { .name
= "pxa270-b0", .initfn
= pxa270b0_initfn
},
1395 { .name
= "pxa270-b1", .initfn
= pxa270b1_initfn
},
1396 { .name
= "pxa270-c0", .initfn
= pxa270c0_initfn
},
1397 { .name
= "pxa270-c5", .initfn
= pxa270c5_initfn
},
1398 #ifdef CONFIG_USER_ONLY
1399 { .name
= "any", .initfn
= arm_any_initfn
},
1405 static Property arm_cpu_properties
[] = {
1406 DEFINE_PROP_BOOL("start-powered-off", ARMCPU
, start_powered_off
, false),
1407 DEFINE_PROP_UINT32("psci-conduit", ARMCPU
, psci_conduit
, 0),
1408 DEFINE_PROP_UINT32("midr", ARMCPU
, midr
, 0),
1409 DEFINE_PROP_END_OF_LIST()
1412 #ifdef CONFIG_USER_ONLY
1413 static int arm_cpu_handle_mmu_fault(CPUState
*cs
, vaddr address
, int rw
,
1416 ARMCPU
*cpu
= ARM_CPU(cs
);
1417 CPUARMState
*env
= &cpu
->env
;
1419 env
->exception
.vaddress
= address
;
1421 cs
->exception_index
= EXCP_PREFETCH_ABORT
;
1423 cs
->exception_index
= EXCP_DATA_ABORT
;
1429 static void arm_cpu_class_init(ObjectClass
*oc
, void *data
)
1431 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
1432 CPUClass
*cc
= CPU_CLASS(acc
);
1433 DeviceClass
*dc
= DEVICE_CLASS(oc
);
1435 acc
->parent_realize
= dc
->realize
;
1436 dc
->realize
= arm_cpu_realizefn
;
1437 dc
->props
= arm_cpu_properties
;
1439 acc
->parent_reset
= cc
->reset
;
1440 cc
->reset
= arm_cpu_reset
;
1442 cc
->class_by_name
= arm_cpu_class_by_name
;
1443 cc
->has_work
= arm_cpu_has_work
;
1444 cc
->cpu_exec_interrupt
= arm_cpu_exec_interrupt
;
1445 cc
->dump_state
= arm_cpu_dump_state
;
1446 cc
->set_pc
= arm_cpu_set_pc
;
1447 cc
->gdb_read_register
= arm_cpu_gdb_read_register
;
1448 cc
->gdb_write_register
= arm_cpu_gdb_write_register
;
1449 #ifdef CONFIG_USER_ONLY
1450 cc
->handle_mmu_fault
= arm_cpu_handle_mmu_fault
;
1452 cc
->do_interrupt
= arm_cpu_do_interrupt
;
1453 cc
->do_unaligned_access
= arm_cpu_do_unaligned_access
;
1454 cc
->get_phys_page_attrs_debug
= arm_cpu_get_phys_page_attrs_debug
;
1455 cc
->asidx_from_attrs
= arm_asidx_from_attrs
;
1456 cc
->vmsd
= &vmstate_arm_cpu
;
1457 cc
->virtio_is_big_endian
= arm_cpu_is_big_endian
;
1458 cc
->write_elf64_note
= arm_cpu_write_elf64_note
;
1459 cc
->write_elf32_note
= arm_cpu_write_elf32_note
;
1461 cc
->gdb_num_core_regs
= 26;
1462 cc
->gdb_core_xml_file
= "arm-core.xml";
1463 cc
->gdb_stop_before_watchpoint
= true;
1464 cc
->debug_excp_handler
= arm_debug_excp_handler
;
1466 cc
->disas_set_info
= arm_disas_set_info
;
1469 * Reason: arm_cpu_initfn() calls cpu_exec_init(), which saves
1470 * the object in cpus -> dangling pointer after final
1473 * Once this is fixed, the devices that create ARM CPUs should be
1474 * updated not to set cannot_destroy_with_object_finalize_yet,
1475 * unless they still screw up something else.
1477 dc
->cannot_destroy_with_object_finalize_yet
= true;
1480 static void cpu_register(const ARMCPUInfo
*info
)
1482 TypeInfo type_info
= {
1483 .parent
= TYPE_ARM_CPU
,
1484 .instance_size
= sizeof(ARMCPU
),
1485 .instance_init
= info
->initfn
,
1486 .class_size
= sizeof(ARMCPUClass
),
1487 .class_init
= info
->class_init
,
1490 type_info
.name
= g_strdup_printf("%s-" TYPE_ARM_CPU
, info
->name
);
1491 type_register(&type_info
);
1492 g_free((void *)type_info
.name
);
1495 static const TypeInfo arm_cpu_type_info
= {
1496 .name
= TYPE_ARM_CPU
,
1498 .instance_size
= sizeof(ARMCPU
),
1499 .instance_init
= arm_cpu_initfn
,
1500 .instance_post_init
= arm_cpu_post_init
,
1501 .instance_finalize
= arm_cpu_finalizefn
,
1503 .class_size
= sizeof(ARMCPUClass
),
1504 .class_init
= arm_cpu_class_init
,
1507 static void arm_cpu_register_types(void)
1509 const ARMCPUInfo
*info
= arm_cpus
;
1511 type_register_static(&arm_cpu_type_info
);
1513 while (info
->name
) {
1519 type_init(arm_cpu_register_types
)