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spapr: introduce helpers to migrate HPT chunks and the end marker
[qemu/kevin.git] / hw / ppc / spapr.c
blob0ce3ec87ac5976eb2b44a69d293b97cf6340ec24
1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
27 #include "qemu/osdep.h"
28 #include "qapi/error.h"
29 #include "qapi/visitor.h"
30 #include "sysemu/sysemu.h"
31 #include "sysemu/numa.h"
32 #include "hw/hw.h"
33 #include "qemu/log.h"
34 #include "hw/fw-path-provider.h"
35 #include "elf.h"
36 #include "net/net.h"
37 #include "sysemu/device_tree.h"
38 #include "sysemu/block-backend.h"
39 #include "sysemu/cpus.h"
40 #include "sysemu/hw_accel.h"
41 #include "kvm_ppc.h"
42 #include "migration/misc.h"
43 #include "migration/global_state.h"
44 #include "migration/register.h"
45 #include "mmu-hash64.h"
46 #include "mmu-book3s-v3.h"
47 #include "qom/cpu.h"
48
49 #include "hw/boards.h"
50 #include "hw/ppc/ppc.h"
51 #include "hw/loader.h"
52
53 #include "hw/ppc/fdt.h"
54 #include "hw/ppc/spapr.h"
55 #include "hw/ppc/spapr_vio.h"
56 #include "hw/pci-host/spapr.h"
57 #include "hw/ppc/xics.h"
58 #include "hw/pci/msi.h"
59
60 #include "hw/pci/pci.h"
61 #include "hw/scsi/scsi.h"
62 #include "hw/virtio/virtio-scsi.h"
63 #include "hw/virtio/vhost-scsi-common.h"
64
65 #include "exec/address-spaces.h"
66 #include "hw/usb.h"
67 #include "qemu/config-file.h"
68 #include "qemu/error-report.h"
69 #include "trace.h"
70 #include "hw/nmi.h"
71 #include "hw/intc/intc.h"
72
73 #include "hw/compat.h"
74 #include "qemu/cutils.h"
75 #include "hw/ppc/spapr_cpu_core.h"
76 #include "qmp-commands.h"
77
78 #include <libfdt.h>
79
80 /* SLOF memory layout:
81 *
82 * SLOF raw image loaded at 0, copies its romfs right below the flat
83 * device-tree, then position SLOF itself 31M below that
84 *
85 * So we set FW_OVERHEAD to 40MB which should account for all of that
86 * and more
87 *
88 * We load our kernel at 4M, leaving space for SLOF initial image
89 */
90 #define FDT_MAX_SIZE 0x100000
91 #define RTAS_MAX_SIZE 0x10000
92 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
93 #define FW_MAX_SIZE 0x400000
94 #define FW_FILE_NAME "slof.bin"
95 #define FW_OVERHEAD 0x2800000
96 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
97
98 #define MIN_RMA_SLOF 128UL
99
100 #define PHANDLE_XICP 0x00001111
101
102 static ICSState *spapr_ics_create(sPAPRMachineState *spapr,
103 const char *type_ics,
104 int nr_irqs, Error **errp)
105 {
106 Error *local_err = NULL;
107 Object *obj;
108
109 obj = object_new(type_ics);
110 object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort);
111 object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr),
112 &error_abort);
113 object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err);
114 if (local_err) {
115 goto error;
116 }
117 object_property_set_bool(obj, true, "realized", &local_err);
118 if (local_err) {
119 goto error;
120 }
121
122 return ICS_SIMPLE(obj);
123
124 error:
125 error_propagate(errp, local_err);
126 return NULL;
127 }
128
129 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque)
130 {
131 /* Dummy entries correspond to unused ICPState objects in older QEMUs,
132 * and newer QEMUs don't even have them. In both cases, we don't want
133 * to send anything on the wire.
134 */
135 return false;
136 }
137
138 static const VMStateDescription pre_2_10_vmstate_dummy_icp = {
139 .name = "icp/server",
140 .version_id = 1,
141 .minimum_version_id = 1,
142 .needed = pre_2_10_vmstate_dummy_icp_needed,
143 .fields = (VMStateField[]) {
144 VMSTATE_UNUSED(4), /* uint32_t xirr */
145 VMSTATE_UNUSED(1), /* uint8_t pending_priority */
146 VMSTATE_UNUSED(1), /* uint8_t mfrr */
147 VMSTATE_END_OF_LIST()
148 },
149 };
150
151 static void pre_2_10_vmstate_register_dummy_icp(int i)
152 {
153 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp,
154 (void *)(uintptr_t) i);
155 }
156
157 static void pre_2_10_vmstate_unregister_dummy_icp(int i)
158 {
159 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp,
160 (void *)(uintptr_t) i);
161 }
162
163 static inline int xics_max_server_number(void)
164 {
165 return DIV_ROUND_UP(max_cpus * kvmppc_smt_threads(), smp_threads);
166 }
167
168 static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp)
169 {
170 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
171 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
172
173 if (kvm_enabled()) {
174 if (machine_kernel_irqchip_allowed(machine) &&
175 !xics_kvm_init(spapr, errp)) {
176 spapr->icp_type = TYPE_KVM_ICP;
177 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs, errp);
178 }
179 if (machine_kernel_irqchip_required(machine) && !spapr->ics) {
180 error_prepend(errp, "kernel_irqchip requested but unavailable: ");
181 return;
182 }
183 }
184
185 if (!spapr->ics) {
186 xics_spapr_init(spapr);
187 spapr->icp_type = TYPE_ICP;
188 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs, errp);
189 if (!spapr->ics) {
190 return;
191 }
192 }
193
194 if (smc->pre_2_10_has_unused_icps) {
195 int i;
196
197 for (i = 0; i < xics_max_server_number(); i++) {
198 /* Dummy entries get deregistered when real ICPState objects
199 * are registered during CPU core hotplug.
200 */
201 pre_2_10_vmstate_register_dummy_icp(i);
202 }
203 }
204 }
205
206 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
207 int smt_threads)
208 {
209 int i, ret = 0;
210 uint32_t servers_prop[smt_threads];
211 uint32_t gservers_prop[smt_threads * 2];
212 int index = spapr_vcpu_id(cpu);
213
214 if (cpu->compat_pvr) {
215 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr);
216 if (ret < 0) {
217 return ret;
218 }
219 }
220
221 /* Build interrupt servers and gservers properties */
222 for (i = 0; i < smt_threads; i++) {
223 servers_prop[i] = cpu_to_be32(index + i);
224 /* Hack, direct the group queues back to cpu 0 */
225 gservers_prop[i*2] = cpu_to_be32(index + i);
226 gservers_prop[i*2 + 1] = 0;
227 }
228 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
229 servers_prop, sizeof(servers_prop));
230 if (ret < 0) {
231 return ret;
232 }
233 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
234 gservers_prop, sizeof(gservers_prop));
235
236 return ret;
237 }
238
239 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu)
240 {
241 int index = spapr_vcpu_id(cpu);
242 uint32_t associativity[] = {cpu_to_be32(0x5),
243 cpu_to_be32(0x0),
244 cpu_to_be32(0x0),
245 cpu_to_be32(0x0),
246 cpu_to_be32(cpu->node_id),
247 cpu_to_be32(index)};
248
249 /* Advertise NUMA via ibm,associativity */
250 return fdt_setprop(fdt, offset, "ibm,associativity", associativity,
251 sizeof(associativity));
252 }
253
254 /* Populate the "ibm,pa-features" property */
255 static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset,
256 bool legacy_guest)
257 {
258 uint8_t pa_features_206[] = { 6, 0,
259 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
260 uint8_t pa_features_207[] = { 24, 0,
261 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
262 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
263 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
264 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
265 uint8_t pa_features_300[] = { 66, 0,
266 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
267 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
268 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
269 /* 6: DS207 */
270 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
271 /* 16: Vector */
272 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
273 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
274 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
275 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
276 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
277 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
278 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
279 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */
280 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */
281 /* 42: PM, 44: PC RA, 46: SC vec'd */
282 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
283 /* 48: SIMD, 50: QP BFP, 52: String */
284 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
285 /* 54: DecFP, 56: DecI, 58: SHA */
286 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
287 /* 60: NM atomic, 62: RNG */
288 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
289 };
290 uint8_t *pa_features;
291 size_t pa_size;
292
293 switch (POWERPC_MMU_VER(env->mmu_model)) {
294 case POWERPC_MMU_VER_2_06:
295 pa_features = pa_features_206;
296 pa_size = sizeof(pa_features_206);
297 break;
298 case POWERPC_MMU_VER_2_07:
299 pa_features = pa_features_207;
300 pa_size = sizeof(pa_features_207);
301 break;
302 case POWERPC_MMU_VER_3_00:
303 pa_features = pa_features_300;
304 pa_size = sizeof(pa_features_300);
305 break;
306 default:
307 return;
308 }
309
310 if (env->ci_large_pages) {
311 /*
312 * Note: we keep CI large pages off by default because a 64K capable
313 * guest provisioned with large pages might otherwise try to map a qemu
314 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
315 * even if that qemu runs on a 4k host.
316 * We dd this bit back here if we are confident this is not an issue
317 */
318 pa_features[3] |= 0x20;
319 }
320 if (kvmppc_has_cap_htm() && pa_size > 24) {
321 pa_features[24] |= 0x80; /* Transactional memory support */
322 }
323 if (legacy_guest && pa_size > 40) {
324 /* Workaround for broken kernels that attempt (guest) radix
325 * mode when they can't handle it, if they see the radix bit set
326 * in pa-features. So hide it from them. */
327 pa_features[40 + 2] &= ~0x80; /* Radix MMU */
328 }
329
330 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
331 }
332
333 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
334 {
335 int ret = 0, offset, cpus_offset;
336 CPUState *cs;
337 char cpu_model[32];
338 int smt = kvmppc_smt_threads();
339 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
340
341 CPU_FOREACH(cs) {
342 PowerPCCPU *cpu = POWERPC_CPU(cs);
343 CPUPPCState *env = &cpu->env;
344 DeviceClass *dc = DEVICE_GET_CLASS(cs);
345 int index = spapr_vcpu_id(cpu);
346 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu));
347
348 if ((index % smt) != 0) {
349 continue;
350 }
351
352 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
353
354 cpus_offset = fdt_path_offset(fdt, "/cpus");
355 if (cpus_offset < 0) {
356 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
357 "cpus");
358 if (cpus_offset < 0) {
359 return cpus_offset;
360 }
361 }
362 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
363 if (offset < 0) {
364 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
365 if (offset < 0) {
366 return offset;
367 }
368 }
369
370 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
371 pft_size_prop, sizeof(pft_size_prop));
372 if (ret < 0) {
373 return ret;
374 }
375
376 if (nb_numa_nodes > 1) {
377 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu);
378 if (ret < 0) {
379 return ret;
380 }
381 }
382
383 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt);
384 if (ret < 0) {
385 return ret;
386 }
387
388 spapr_populate_pa_features(env, fdt, offset,
389 spapr->cas_legacy_guest_workaround);
390 }
391 return ret;
392 }
393
394 static hwaddr spapr_node0_size(MachineState *machine)
395 {
396 if (nb_numa_nodes) {
397 int i;
398 for (i = 0; i < nb_numa_nodes; ++i) {
399 if (numa_info[i].node_mem) {
400 return MIN(pow2floor(numa_info[i].node_mem),
401 machine->ram_size);
402 }
403 }
404 }
405 return machine->ram_size;
406 }
407
408 static void add_str(GString *s, const gchar *s1)
409 {
410 g_string_append_len(s, s1, strlen(s1) + 1);
411 }
412
413 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
414 hwaddr size)
415 {
416 uint32_t associativity[] = {
417 cpu_to_be32(0x4), /* length */
418 cpu_to_be32(0x0), cpu_to_be32(0x0),
419 cpu_to_be32(0x0), cpu_to_be32(nodeid)
420 };
421 char mem_name[32];
422 uint64_t mem_reg_property[2];
423 int off;
424
425 mem_reg_property[0] = cpu_to_be64(start);
426 mem_reg_property[1] = cpu_to_be64(size);
427
428 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
429 off = fdt_add_subnode(fdt, 0, mem_name);
430 _FDT(off);
431 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
432 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
433 sizeof(mem_reg_property))));
434 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
435 sizeof(associativity))));
436 return off;
437 }
438
439 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt)
440 {
441 MachineState *machine = MACHINE(spapr);
442 hwaddr mem_start, node_size;
443 int i, nb_nodes = nb_numa_nodes;
444 NodeInfo *nodes = numa_info;
445 NodeInfo ramnode;
446
447 /* No NUMA nodes, assume there is just one node with whole RAM */
448 if (!nb_numa_nodes) {
449 nb_nodes = 1;
450 ramnode.node_mem = machine->ram_size;
451 nodes = &ramnode;
452 }
453
454 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
455 if (!nodes[i].node_mem) {
456 continue;
457 }
458 if (mem_start >= machine->ram_size) {
459 node_size = 0;
460 } else {
461 node_size = nodes[i].node_mem;
462 if (node_size > machine->ram_size - mem_start) {
463 node_size = machine->ram_size - mem_start;
464 }
465 }
466 if (!mem_start) {
467 /* ppc_spapr_init() checks for rma_size <= node0_size already */
468 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
469 mem_start += spapr->rma_size;
470 node_size -= spapr->rma_size;
471 }
472 for ( ; node_size; ) {
473 hwaddr sizetmp = pow2floor(node_size);
474
475 /* mem_start != 0 here */
476 if (ctzl(mem_start) < ctzl(sizetmp)) {
477 sizetmp = 1ULL << ctzl(mem_start);
478 }
479
480 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
481 node_size -= sizetmp;
482 mem_start += sizetmp;
483 }
484 }
485
486 return 0;
487 }
488
489 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
490 sPAPRMachineState *spapr)
491 {
492 PowerPCCPU *cpu = POWERPC_CPU(cs);
493 CPUPPCState *env = &cpu->env;
494 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
495 int index = spapr_vcpu_id(cpu);
496 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
497 0xffffffff, 0xffffffff};
498 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
499 : SPAPR_TIMEBASE_FREQ;
500 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
501 uint32_t page_sizes_prop[64];
502 size_t page_sizes_prop_size;
503 uint32_t vcpus_per_socket = smp_threads * smp_cores;
504 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
505 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu));
506 sPAPRDRConnector *drc;
507 int drc_index;
508 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ];
509 int i;
510
511 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index);
512 if (drc) {
513 drc_index = spapr_drc_index(drc);
514 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
515 }
516
517 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
518 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
519
520 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
521 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
522 env->dcache_line_size)));
523 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
524 env->dcache_line_size)));
525 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
526 env->icache_line_size)));
527 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
528 env->icache_line_size)));
529
530 if (pcc->l1_dcache_size) {
531 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
532 pcc->l1_dcache_size)));
533 } else {
534 warn_report("Unknown L1 dcache size for cpu");
535 }
536 if (pcc->l1_icache_size) {
537 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
538 pcc->l1_icache_size)));
539 } else {
540 warn_report("Unknown L1 icache size for cpu");
541 }
542
543 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
544 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
545 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr)));
546 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
547 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
548 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
549
550 if (env->spr_cb[SPR_PURR].oea_read) {
551 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
552 }
553
554 if (env->mmu_model & POWERPC_MMU_1TSEG) {
555 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
556 segs, sizeof(segs))));
557 }
558
559 /* Advertise VMX/VSX (vector extensions) if available
560 * 0 / no property == no vector extensions
561 * 1 == VMX / Altivec available
562 * 2 == VSX available */
563 if (env->insns_flags & PPC_ALTIVEC) {
564 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
565
566 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
567 }
568
569 /* Advertise DFP (Decimal Floating Point) if available
570 * 0 / no property == no DFP
571 * 1 == DFP available */
572 if (env->insns_flags2 & PPC2_DFP) {
573 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
574 }
575
576 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
577 sizeof(page_sizes_prop));
578 if (page_sizes_prop_size) {
579 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
580 page_sizes_prop, page_sizes_prop_size)));
581 }
582
583 spapr_populate_pa_features(env, fdt, offset, false);
584
585 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
586 cs->cpu_index / vcpus_per_socket)));
587
588 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
589 pft_size_prop, sizeof(pft_size_prop))));
590
591 if (nb_numa_nodes > 1) {
592 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu));
593 }
594
595 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt));
596
597 if (pcc->radix_page_info) {
598 for (i = 0; i < pcc->radix_page_info->count; i++) {
599 radix_AP_encodings[i] =
600 cpu_to_be32(pcc->radix_page_info->entries[i]);
601 }
602 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings",
603 radix_AP_encodings,
604 pcc->radix_page_info->count *
605 sizeof(radix_AP_encodings[0]))));
606 }
607 }
608
609 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
610 {
611 CPUState *cs;
612 int cpus_offset;
613 char *nodename;
614 int smt = kvmppc_smt_threads();
615
616 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
617 _FDT(cpus_offset);
618 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
619 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
620
621 /*
622 * We walk the CPUs in reverse order to ensure that CPU DT nodes
623 * created by fdt_add_subnode() end up in the right order in FDT
624 * for the guest kernel the enumerate the CPUs correctly.
625 */
626 CPU_FOREACH_REVERSE(cs) {
627 PowerPCCPU *cpu = POWERPC_CPU(cs);
628 int index = spapr_vcpu_id(cpu);
629 DeviceClass *dc = DEVICE_GET_CLASS(cs);
630 int offset;
631
632 if ((index % smt) != 0) {
633 continue;
634 }
635
636 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
637 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
638 g_free(nodename);
639 _FDT(offset);
640 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
641 }
642
643 }
644
645 /*
646 * Adds ibm,dynamic-reconfiguration-memory node.
647 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
648 * of this device tree node.
649 */
650 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
651 {
652 MachineState *machine = MACHINE(spapr);
653 int ret, i, offset;
654 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
655 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
656 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size;
657 uint32_t nr_lmbs = (spapr->hotplug_memory.base +
658 memory_region_size(&spapr->hotplug_memory.mr)) /
659 lmb_size;
660 uint32_t *int_buf, *cur_index, buf_len;
661 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
662
663 /*
664 * Don't create the node if there is no hotpluggable memory
665 */
666 if (machine->ram_size == machine->maxram_size) {
667 return 0;
668 }
669
670 /*
671 * Allocate enough buffer size to fit in ibm,dynamic-memory
672 * or ibm,associativity-lookup-arrays
673 */
674 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2)
675 * sizeof(uint32_t);
676 cur_index = int_buf = g_malloc0(buf_len);
677
678 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
679
680 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
681 sizeof(prop_lmb_size));
682 if (ret < 0) {
683 goto out;
684 }
685
686 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
687 if (ret < 0) {
688 goto out;
689 }
690
691 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
692 if (ret < 0) {
693 goto out;
694 }
695
696 /* ibm,dynamic-memory */
697 int_buf[0] = cpu_to_be32(nr_lmbs);
698 cur_index++;
699 for (i = 0; i < nr_lmbs; i++) {
700 uint64_t addr = i * lmb_size;
701 uint32_t *dynamic_memory = cur_index;
702
703 if (i >= hotplug_lmb_start) {
704 sPAPRDRConnector *drc;
705
706 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i);
707 g_assert(drc);
708
709 dynamic_memory[0] = cpu_to_be32(addr >> 32);
710 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
711 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc));
712 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
713 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL));
714 if (memory_region_present(get_system_memory(), addr)) {
715 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
716 } else {
717 dynamic_memory[5] = cpu_to_be32(0);
718 }
719 } else {
720 /*
721 * LMB information for RMA, boot time RAM and gap b/n RAM and
722 * hotplug memory region -- all these are marked as reserved
723 * and as having no valid DRC.
724 */
725 dynamic_memory[0] = cpu_to_be32(addr >> 32);
726 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
727 dynamic_memory[2] = cpu_to_be32(0);
728 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
729 dynamic_memory[4] = cpu_to_be32(-1);
730 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
731 SPAPR_LMB_FLAGS_DRC_INVALID);
732 }
733
734 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
735 }
736 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
737 if (ret < 0) {
738 goto out;
739 }
740
741 /* ibm,associativity-lookup-arrays */
742 cur_index = int_buf;
743 int_buf[0] = cpu_to_be32(nr_nodes);
744 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
745 cur_index += 2;
746 for (i = 0; i < nr_nodes; i++) {
747 uint32_t associativity[] = {
748 cpu_to_be32(0x0),
749 cpu_to_be32(0x0),
750 cpu_to_be32(0x0),
751 cpu_to_be32(i)
752 };
753 memcpy(cur_index, associativity, sizeof(associativity));
754 cur_index += 4;
755 }
756 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
757 (cur_index - int_buf) * sizeof(uint32_t));
758 out:
759 g_free(int_buf);
760 return ret;
761 }
762
763 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt,
764 sPAPROptionVector *ov5_updates)
765 {
766 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
767 int ret = 0, offset;
768
769 /* Generate ibm,dynamic-reconfiguration-memory node if required */
770 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) {
771 g_assert(smc->dr_lmb_enabled);
772 ret = spapr_populate_drconf_memory(spapr, fdt);
773 if (ret) {
774 goto out;
775 }
776 }
777
778 offset = fdt_path_offset(fdt, "/chosen");
779 if (offset < 0) {
780 offset = fdt_add_subnode(fdt, 0, "chosen");
781 if (offset < 0) {
782 return offset;
783 }
784 }
785 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas,
786 "ibm,architecture-vec-5");
787
788 out:
789 return ret;
790 }
791
792 static bool spapr_hotplugged_dev_before_cas(void)
793 {
794 Object *drc_container, *obj;
795 ObjectProperty *prop;
796 ObjectPropertyIterator iter;
797
798 drc_container = container_get(object_get_root(), "/dr-connector");
799 object_property_iter_init(&iter, drc_container);
800 while ((prop = object_property_iter_next(&iter))) {
801 if (!strstart(prop->type, "link<", NULL)) {
802 continue;
803 }
804 obj = object_property_get_link(drc_container, prop->name, NULL);
805 if (spapr_drc_needed(obj)) {
806 return true;
807 }
808 }
809 return false;
810 }
811
812 int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
813 target_ulong addr, target_ulong size,
814 sPAPROptionVector *ov5_updates)
815 {
816 void *fdt, *fdt_skel;
817 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
818
819 if (spapr_hotplugged_dev_before_cas()) {
820 return 1;
821 }
822
823 size -= sizeof(hdr);
824
825 /* Create skeleton */
826 fdt_skel = g_malloc0(size);
827 _FDT((fdt_create(fdt_skel, size)));
828 _FDT((fdt_begin_node(fdt_skel, "")));
829 _FDT((fdt_end_node(fdt_skel)));
830 _FDT((fdt_finish(fdt_skel)));
831 fdt = g_malloc0(size);
832 _FDT((fdt_open_into(fdt_skel, fdt, size)));
833 g_free(fdt_skel);
834
835 /* Fixup cpu nodes */
836 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
837
838 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) {
839 return -1;
840 }
841
842 /* Pack resulting tree */
843 _FDT((fdt_pack(fdt)));
844
845 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
846 trace_spapr_cas_failed(size);
847 return -1;
848 }
849
850 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
851 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
852 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
853 g_free(fdt);
854
855 return 0;
856 }
857
858 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt)
859 {
860 int rtas;
861 GString *hypertas = g_string_sized_new(256);
862 GString *qemu_hypertas = g_string_sized_new(256);
863 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
864 uint64_t max_hotplug_addr = spapr->hotplug_memory.base +
865 memory_region_size(&spapr->hotplug_memory.mr);
866 uint32_t lrdr_capacity[] = {
867 cpu_to_be32(max_hotplug_addr >> 32),
868 cpu_to_be32(max_hotplug_addr & 0xffffffff),
869 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE),
870 cpu_to_be32(max_cpus / smp_threads),
871 };
872
873 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas"));
874
875 /* hypertas */
876 add_str(hypertas, "hcall-pft");
877 add_str(hypertas, "hcall-term");
878 add_str(hypertas, "hcall-dabr");
879 add_str(hypertas, "hcall-interrupt");
880 add_str(hypertas, "hcall-tce");
881 add_str(hypertas, "hcall-vio");
882 add_str(hypertas, "hcall-splpar");
883 add_str(hypertas, "hcall-bulk");
884 add_str(hypertas, "hcall-set-mode");
885 add_str(hypertas, "hcall-sprg0");
886 add_str(hypertas, "hcall-copy");
887 add_str(hypertas, "hcall-debug");
888 add_str(qemu_hypertas, "hcall-memop1");
889
890 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
891 add_str(hypertas, "hcall-multi-tce");
892 }
893
894 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
895 add_str(hypertas, "hcall-hpt-resize");
896 }
897
898 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions",
899 hypertas->str, hypertas->len));
900 g_string_free(hypertas, TRUE);
901 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions",
902 qemu_hypertas->str, qemu_hypertas->len));
903 g_string_free(qemu_hypertas, TRUE);
904
905 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points",
906 refpoints, sizeof(refpoints)));
907
908 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max",
909 RTAS_ERROR_LOG_MAX));
910 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate",
911 RTAS_EVENT_SCAN_RATE));
912
913 if (msi_nonbroken) {
914 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0));
915 }
916
917 /*
918 * According to PAPR, rtas ibm,os-term does not guarantee a return
919 * back to the guest cpu.
920 *
921 * While an additional ibm,extended-os-term property indicates
922 * that rtas call return will always occur. Set this property.
923 */
924 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0));
925
926 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity",
927 lrdr_capacity, sizeof(lrdr_capacity)));
928
929 spapr_dt_rtas_tokens(fdt, rtas);
930 }
931
932 /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features
933 * that the guest may request and thus the valid values for bytes 24..26 of
934 * option vector 5: */
935 static void spapr_dt_ov5_platform_support(void *fdt, int chosen)
936 {
937 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
938
939 char val[2 * 4] = {
940 23, 0x00, /* Xive mode, filled in below. */
941 24, 0x00, /* Hash/Radix, filled in below. */
942 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
943 26, 0x40, /* Radix options: GTSE == yes. */
944 };
945
946 if (kvm_enabled()) {
947 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
948 val[3] = 0x80; /* OV5_MMU_BOTH */
949 } else if (kvmppc_has_cap_mmu_radix()) {
950 val[3] = 0x40; /* OV5_MMU_RADIX_300 */
951 } else {
952 val[3] = 0x00; /* Hash */
953 }
954 } else {
955 if (first_ppc_cpu->env.mmu_model & POWERPC_MMU_V3) {
956 /* V3 MMU supports both hash and radix (with dynamic switching) */
957 val[3] = 0xC0;
958 } else {
959 /* Otherwise we can only do hash */
960 val[3] = 0x00;
961 }
962 }
963 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support",
964 val, sizeof(val)));
965 }
966
967 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt)
968 {
969 MachineState *machine = MACHINE(spapr);
970 int chosen;
971 const char *boot_device = machine->boot_order;
972 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus);
973 size_t cb = 0;
974 char *bootlist = get_boot_devices_list(&cb, true);
975
976 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen"));
977
978 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline));
979 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start",
980 spapr->initrd_base));
981 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end",
982 spapr->initrd_base + spapr->initrd_size));
983
984 if (spapr->kernel_size) {
985 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
986 cpu_to_be64(spapr->kernel_size) };
987
988 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel",
989 &kprop, sizeof(kprop)));
990 if (spapr->kernel_le) {
991 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0));
992 }
993 }
994 if (boot_menu) {
995 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu)));
996 }
997 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width));
998 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height));
999 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth));
1000
1001 if (cb && bootlist) {
1002 int i;
1003
1004 for (i = 0; i < cb; i++) {
1005 if (bootlist[i] == '\n') {
1006 bootlist[i] = ' ';
1007 }
1008 }
1009 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist));
1010 }
1011
1012 if (boot_device && strlen(boot_device)) {
1013 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device));
1014 }
1015
1016 if (!spapr->has_graphics && stdout_path) {
1017 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path));
1018 }
1019
1020 spapr_dt_ov5_platform_support(fdt, chosen);
1021
1022 g_free(stdout_path);
1023 g_free(bootlist);
1024 }
1025
1026 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt)
1027 {
1028 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
1029 * KVM to work under pHyp with some guest co-operation */
1030 int hypervisor;
1031 uint8_t hypercall[16];
1032
1033 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor"));
1034 /* indicate KVM hypercall interface */
1035 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm"));
1036 if (kvmppc_has_cap_fixup_hcalls()) {
1037 /*
1038 * Older KVM versions with older guest kernels were broken
1039 * with the magic page, don't allow the guest to map it.
1040 */
1041 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
1042 sizeof(hypercall))) {
1043 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions",
1044 hypercall, sizeof(hypercall)));
1045 }
1046 }
1047 }
1048
1049 static void *spapr_build_fdt(sPAPRMachineState *spapr,
1050 hwaddr rtas_addr,
1051 hwaddr rtas_size)
1052 {
1053 MachineState *machine = MACHINE(spapr);
1054 MachineClass *mc = MACHINE_GET_CLASS(machine);
1055 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1056 int ret;
1057 void *fdt;
1058 sPAPRPHBState *phb;
1059 char *buf;
1060
1061 fdt = g_malloc0(FDT_MAX_SIZE);
1062 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
1063
1064 /* Root node */
1065 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp"));
1066 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)"));
1067 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries"));
1068
1069 /*
1070 * Add info to guest to indentify which host is it being run on
1071 * and what is the uuid of the guest
1072 */
1073 if (kvmppc_get_host_model(&buf)) {
1074 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf));
1075 g_free(buf);
1076 }
1077 if (kvmppc_get_host_serial(&buf)) {
1078 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf));
1079 g_free(buf);
1080 }
1081
1082 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
1083
1084 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf));
1085 if (qemu_uuid_set) {
1086 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf));
1087 }
1088 g_free(buf);
1089
1090 if (qemu_get_vm_name()) {
1091 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name",
1092 qemu_get_vm_name()));
1093 }
1094
1095 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2));
1096 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2));
1097
1098 /* /interrupt controller */
1099 spapr_dt_xics(xics_max_server_number(), fdt, PHANDLE_XICP);
1100
1101 ret = spapr_populate_memory(spapr, fdt);
1102 if (ret < 0) {
1103 error_report("couldn't setup memory nodes in fdt");
1104 exit(1);
1105 }
1106
1107 /* /vdevice */
1108 spapr_dt_vdevice(spapr->vio_bus, fdt);
1109
1110 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
1111 ret = spapr_rng_populate_dt(fdt);
1112 if (ret < 0) {
1113 error_report("could not set up rng device in the fdt");
1114 exit(1);
1115 }
1116 }
1117
1118 QLIST_FOREACH(phb, &spapr->phbs, list) {
1119 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
1120 if (ret < 0) {
1121 error_report("couldn't setup PCI devices in fdt");
1122 exit(1);
1123 }
1124 }
1125
1126 /* cpus */
1127 spapr_populate_cpus_dt_node(fdt, spapr);
1128
1129 if (smc->dr_lmb_enabled) {
1130 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
1131 }
1132
1133 if (mc->has_hotpluggable_cpus) {
1134 int offset = fdt_path_offset(fdt, "/cpus");
1135 ret = spapr_drc_populate_dt(fdt, offset, NULL,
1136 SPAPR_DR_CONNECTOR_TYPE_CPU);
1137 if (ret < 0) {
1138 error_report("Couldn't set up CPU DR device tree properties");
1139 exit(1);
1140 }
1141 }
1142
1143 /* /event-sources */
1144 spapr_dt_events(spapr, fdt);
1145
1146 /* /rtas */
1147 spapr_dt_rtas(spapr, fdt);
1148
1149 /* /chosen */
1150 spapr_dt_chosen(spapr, fdt);
1151
1152 /* /hypervisor */
1153 if (kvm_enabled()) {
1154 spapr_dt_hypervisor(spapr, fdt);
1155 }
1156
1157 /* Build memory reserve map */
1158 if (spapr->kernel_size) {
1159 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size)));
1160 }
1161 if (spapr->initrd_size) {
1162 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size)));
1163 }
1164
1165 /* ibm,client-architecture-support updates */
1166 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas);
1167 if (ret < 0) {
1168 error_report("couldn't setup CAS properties fdt");
1169 exit(1);
1170 }
1171
1172 return fdt;
1173 }
1174
1175 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1176 {
1177 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1178 }
1179
1180 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp,
1181 PowerPCCPU *cpu)
1182 {
1183 CPUPPCState *env = &cpu->env;
1184
1185 /* The TCG path should also be holding the BQL at this point */
1186 g_assert(qemu_mutex_iothread_locked());
1187
1188 if (msr_pr) {
1189 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1190 env->gpr[3] = H_PRIVILEGE;
1191 } else {
1192 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1193 }
1194 }
1195
1196 static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp)
1197 {
1198 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1199
1200 return spapr->patb_entry;
1201 }
1202
1203 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1204 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1205 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1206 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1207 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1208
1209 /*
1210 * Get the fd to access the kernel htab, re-opening it if necessary
1211 */
1212 static int get_htab_fd(sPAPRMachineState *spapr)
1213 {
1214 Error *local_err = NULL;
1215
1216 if (spapr->htab_fd >= 0) {
1217 return spapr->htab_fd;
1218 }
1219
1220 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err);
1221 if (spapr->htab_fd < 0) {
1222 error_report_err(local_err);
1223 }
1224
1225 return spapr->htab_fd;
1226 }
1227
1228 void close_htab_fd(sPAPRMachineState *spapr)
1229 {
1230 if (spapr->htab_fd >= 0) {
1231 close(spapr->htab_fd);
1232 }
1233 spapr->htab_fd = -1;
1234 }
1235
1236 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp)
1237 {
1238 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1239
1240 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1;
1241 }
1242
1243 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp,
1244 hwaddr ptex, int n)
1245 {
1246 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1247 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64;
1248
1249 if (!spapr->htab) {
1250 /*
1251 * HTAB is controlled by KVM. Fetch into temporary buffer
1252 */
1253 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64);
1254 kvmppc_read_hptes(hptes, ptex, n);
1255 return hptes;
1256 }
1257
1258 /*
1259 * HTAB is controlled by QEMU. Just point to the internally
1260 * accessible PTEG.
1261 */
1262 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset);
1263 }
1264
1265 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp,
1266 const ppc_hash_pte64_t *hptes,
1267 hwaddr ptex, int n)
1268 {
1269 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1270
1271 if (!spapr->htab) {
1272 g_free((void *)hptes);
1273 }
1274
1275 /* Nothing to do for qemu managed HPT */
1276 }
1277
1278 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1279 uint64_t pte0, uint64_t pte1)
1280 {
1281 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1282 hwaddr offset = ptex * HASH_PTE_SIZE_64;
1283
1284 if (!spapr->htab) {
1285 kvmppc_write_hpte(ptex, pte0, pte1);
1286 } else {
1287 stq_p(spapr->htab + offset, pte0);
1288 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1289 }
1290 }
1291
1292 int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1293 {
1294 int shift;
1295
1296 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1297 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1298 * that's much more than is needed for Linux guests */
1299 shift = ctz64(pow2ceil(ramsize)) - 7;
1300 shift = MAX(shift, 18); /* Minimum architected size */
1301 shift = MIN(shift, 46); /* Maximum architected size */
1302 return shift;
1303 }
1304
1305 void spapr_free_hpt(sPAPRMachineState *spapr)
1306 {
1307 g_free(spapr->htab);
1308 spapr->htab = NULL;
1309 spapr->htab_shift = 0;
1310 close_htab_fd(spapr);
1311 }
1312
1313 void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
1314 Error **errp)
1315 {
1316 long rc;
1317
1318 /* Clean up any HPT info from a previous boot */
1319 spapr_free_hpt(spapr);
1320
1321 rc = kvmppc_reset_htab(shift);
1322 if (rc < 0) {
1323 /* kernel-side HPT needed, but couldn't allocate one */
1324 error_setg_errno(errp, errno,
1325 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1326 shift);
1327 /* This is almost certainly fatal, but if the caller really
1328 * wants to carry on with shift == 0, it's welcome to try */
1329 } else if (rc > 0) {
1330 /* kernel-side HPT allocated */
1331 if (rc != shift) {
1332 error_setg(errp,
1333 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1334 shift, rc);
1335 }
1336
1337 spapr->htab_shift = shift;
1338 spapr->htab = NULL;
1339 } else {
1340 /* kernel-side HPT not needed, allocate in userspace instead */
1341 size_t size = 1ULL << shift;
1342 int i;
1343
1344 spapr->htab = qemu_memalign(size, size);
1345 if (!spapr->htab) {
1346 error_setg_errno(errp, errno,
1347 "Could not allocate HPT of order %d", shift);
1348 return;
1349 }
1350
1351 memset(spapr->htab, 0, size);
1352 spapr->htab_shift = shift;
1353
1354 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1355 DIRTY_HPTE(HPTE(spapr->htab, i));
1356 }
1357 }
1358 }
1359
1360 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr)
1361 {
1362 int hpt_shift;
1363
1364 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED)
1365 || (spapr->cas_reboot
1366 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) {
1367 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size);
1368 } else {
1369 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->ram_size);
1370 }
1371 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal);
1372
1373 if (spapr->vrma_adjust) {
1374 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)),
1375 spapr->htab_shift);
1376 }
1377 /* We're setting up a hash table, so that means we're not radix */
1378 spapr->patb_entry = 0;
1379 }
1380
1381 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque)
1382 {
1383 bool matched = false;
1384
1385 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
1386 matched = true;
1387 }
1388
1389 if (!matched) {
1390 error_report("Device %s is not supported by this machine yet.",
1391 qdev_fw_name(DEVICE(sbdev)));
1392 exit(1);
1393 }
1394 }
1395
1396 static void ppc_spapr_reset(void)
1397 {
1398 MachineState *machine = MACHINE(qdev_get_machine());
1399 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1400 PowerPCCPU *first_ppc_cpu;
1401 uint32_t rtas_limit;
1402 hwaddr rtas_addr, fdt_addr;
1403 void *fdt;
1404 int rc;
1405
1406 /* Check for unknown sysbus devices */
1407 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL);
1408
1409 if (kvm_enabled() && kvmppc_has_cap_mmu_radix()) {
1410 /* If using KVM with radix mode available, VCPUs can be started
1411 * without a HPT because KVM will start them in radix mode.
1412 * Set the GR bit in PATB so that we know there is no HPT. */
1413 spapr->patb_entry = PATBE1_GR;
1414 } else {
1415 spapr_setup_hpt_and_vrma(spapr);
1416 }
1417
1418 qemu_devices_reset();
1419 spapr_clear_pending_events(spapr);
1420
1421 /*
1422 * We place the device tree and RTAS just below either the top of the RMA,
1423 * or just below 2GB, whichever is lowere, so that it can be
1424 * processed with 32-bit real mode code if necessary
1425 */
1426 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1427 rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1428 fdt_addr = rtas_addr - FDT_MAX_SIZE;
1429
1430 /* if this reset wasn't generated by CAS, we should reset our
1431 * negotiated options and start from scratch */
1432 if (!spapr->cas_reboot) {
1433 spapr_ovec_cleanup(spapr->ov5_cas);
1434 spapr->ov5_cas = spapr_ovec_new();
1435
1436 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal);
1437 }
1438
1439 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size);
1440
1441 spapr_load_rtas(spapr, fdt, rtas_addr);
1442
1443 rc = fdt_pack(fdt);
1444
1445 /* Should only fail if we've built a corrupted tree */
1446 assert(rc == 0);
1447
1448 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
1449 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1450 fdt_totalsize(fdt), FDT_MAX_SIZE);
1451 exit(1);
1452 }
1453
1454 /* Load the fdt */
1455 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
1456 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
1457 g_free(fdt);
1458
1459 /* Set up the entry state */
1460 first_ppc_cpu = POWERPC_CPU(first_cpu);
1461 first_ppc_cpu->env.gpr[3] = fdt_addr;
1462 first_ppc_cpu->env.gpr[5] = 0;
1463 first_cpu->halted = 0;
1464 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT;
1465
1466 spapr->cas_reboot = false;
1467 }
1468
1469 static void spapr_create_nvram(sPAPRMachineState *spapr)
1470 {
1471 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
1472 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1473
1474 if (dinfo) {
1475 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1476 &error_fatal);
1477 }
1478
1479 qdev_init_nofail(dev);
1480
1481 spapr->nvram = (struct sPAPRNVRAM *)dev;
1482 }
1483
1484 static void spapr_rtc_create(sPAPRMachineState *spapr)
1485 {
1486 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC);
1487 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc),
1488 &error_fatal);
1489 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized",
1490 &error_fatal);
1491 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc),
1492 "date", &error_fatal);
1493 }
1494
1495 /* Returns whether we want to use VGA or not */
1496 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1497 {
1498 switch (vga_interface_type) {
1499 case VGA_NONE:
1500 return false;
1501 case VGA_DEVICE:
1502 return true;
1503 case VGA_STD:
1504 case VGA_VIRTIO:
1505 return pci_vga_init(pci_bus) != NULL;
1506 default:
1507 error_setg(errp,
1508 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1509 return false;
1510 }
1511 }
1512
1513 static int spapr_post_load(void *opaque, int version_id)
1514 {
1515 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1516 int err = 0;
1517
1518 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) {
1519 CPUState *cs;
1520 CPU_FOREACH(cs) {
1521 PowerPCCPU *cpu = POWERPC_CPU(cs);
1522 icp_resend(ICP(cpu->intc));
1523 }
1524 }
1525
1526 /* In earlier versions, there was no separate qdev for the PAPR
1527 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1528 * So when migrating from those versions, poke the incoming offset
1529 * value into the RTC device */
1530 if (version_id < 3) {
1531 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset);
1532 }
1533
1534 if (spapr->patb_entry) {
1535 PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
1536 bool radix = !!(spapr->patb_entry & PATBE1_GR);
1537 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE);
1538
1539 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry);
1540 if (err) {
1541 error_report("Process table config unsupported by the host");
1542 return -EINVAL;
1543 }
1544 }
1545
1546 return err;
1547 }
1548
1549 static bool version_before_3(void *opaque, int version_id)
1550 {
1551 return version_id < 3;
1552 }
1553
1554 static bool spapr_pending_events_needed(void *opaque)
1555 {
1556 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1557 return !QTAILQ_EMPTY(&spapr->pending_events);
1558 }
1559
1560 static const VMStateDescription vmstate_spapr_event_entry = {
1561 .name = "spapr_event_log_entry",
1562 .version_id = 1,
1563 .minimum_version_id = 1,
1564 .fields = (VMStateField[]) {
1565 VMSTATE_UINT32(summary, sPAPREventLogEntry),
1566 VMSTATE_UINT32(extended_length, sPAPREventLogEntry),
1567 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, sPAPREventLogEntry, 0,
1568 NULL, extended_length),
1569 VMSTATE_END_OF_LIST()
1570 },
1571 };
1572
1573 static const VMStateDescription vmstate_spapr_pending_events = {
1574 .name = "spapr_pending_events",
1575 .version_id = 1,
1576 .minimum_version_id = 1,
1577 .needed = spapr_pending_events_needed,
1578 .fields = (VMStateField[]) {
1579 VMSTATE_QTAILQ_V(pending_events, sPAPRMachineState, 1,
1580 vmstate_spapr_event_entry, sPAPREventLogEntry, next),
1581 VMSTATE_END_OF_LIST()
1582 },
1583 };
1584
1585 static bool spapr_ov5_cas_needed(void *opaque)
1586 {
1587 sPAPRMachineState *spapr = opaque;
1588 sPAPROptionVector *ov5_mask = spapr_ovec_new();
1589 sPAPROptionVector *ov5_legacy = spapr_ovec_new();
1590 sPAPROptionVector *ov5_removed = spapr_ovec_new();
1591 bool cas_needed;
1592
1593 /* Prior to the introduction of sPAPROptionVector, we had two option
1594 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1595 * Both of these options encode machine topology into the device-tree
1596 * in such a way that the now-booted OS should still be able to interact
1597 * appropriately with QEMU regardless of what options were actually
1598 * negotiatied on the source side.
1599 *
1600 * As such, we can avoid migrating the CAS-negotiated options if these
1601 * are the only options available on the current machine/platform.
1602 * Since these are the only options available for pseries-2.7 and
1603 * earlier, this allows us to maintain old->new/new->old migration
1604 * compatibility.
1605 *
1606 * For QEMU 2.8+, there are additional CAS-negotiatable options available
1607 * via default pseries-2.8 machines and explicit command-line parameters.
1608 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
1609 * of the actual CAS-negotiated values to continue working properly. For
1610 * example, availability of memory unplug depends on knowing whether
1611 * OV5_HP_EVT was negotiated via CAS.
1612 *
1613 * Thus, for any cases where the set of available CAS-negotiatable
1614 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
1615 * include the CAS-negotiated options in the migration stream.
1616 */
1617 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY);
1618 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY);
1619
1620 /* spapr_ovec_diff returns true if bits were removed. we avoid using
1621 * the mask itself since in the future it's possible "legacy" bits may be
1622 * removed via machine options, which could generate a false positive
1623 * that breaks migration.
1624 */
1625 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask);
1626 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy);
1627
1628 spapr_ovec_cleanup(ov5_mask);
1629 spapr_ovec_cleanup(ov5_legacy);
1630 spapr_ovec_cleanup(ov5_removed);
1631
1632 return cas_needed;
1633 }
1634
1635 static const VMStateDescription vmstate_spapr_ov5_cas = {
1636 .name = "spapr_option_vector_ov5_cas",
1637 .version_id = 1,
1638 .minimum_version_id = 1,
1639 .needed = spapr_ov5_cas_needed,
1640 .fields = (VMStateField[]) {
1641 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1,
1642 vmstate_spapr_ovec, sPAPROptionVector),
1643 VMSTATE_END_OF_LIST()
1644 },
1645 };
1646
1647 static bool spapr_patb_entry_needed(void *opaque)
1648 {
1649 sPAPRMachineState *spapr = opaque;
1650
1651 return !!spapr->patb_entry;
1652 }
1653
1654 static const VMStateDescription vmstate_spapr_patb_entry = {
1655 .name = "spapr_patb_entry",
1656 .version_id = 1,
1657 .minimum_version_id = 1,
1658 .needed = spapr_patb_entry_needed,
1659 .fields = (VMStateField[]) {
1660 VMSTATE_UINT64(patb_entry, sPAPRMachineState),
1661 VMSTATE_END_OF_LIST()
1662 },
1663 };
1664
1665 static const VMStateDescription vmstate_spapr = {
1666 .name = "spapr",
1667 .version_id = 3,
1668 .minimum_version_id = 1,
1669 .post_load = spapr_post_load,
1670 .fields = (VMStateField[]) {
1671 /* used to be @next_irq */
1672 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
1673
1674 /* RTC offset */
1675 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3),
1676
1677 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2),
1678 VMSTATE_END_OF_LIST()
1679 },
1680 .subsections = (const VMStateDescription*[]) {
1681 &vmstate_spapr_ov5_cas,
1682 &vmstate_spapr_patb_entry,
1683 &vmstate_spapr_pending_events,
1684 NULL
1685 }
1686 };
1687
1688 static int htab_save_setup(QEMUFile *f, void *opaque)
1689 {
1690 sPAPRMachineState *spapr = opaque;
1691
1692 /* "Iteration" header */
1693 if (!spapr->htab_shift) {
1694 qemu_put_be32(f, -1);
1695 } else {
1696 qemu_put_be32(f, spapr->htab_shift);
1697 }
1698
1699 if (spapr->htab) {
1700 spapr->htab_save_index = 0;
1701 spapr->htab_first_pass = true;
1702 } else {
1703 if (spapr->htab_shift) {
1704 assert(kvm_enabled());
1705 }
1706 }
1707
1708
1709 return 0;
1710 }
1711
1712 static void htab_save_chunk(QEMUFile *f, sPAPRMachineState *spapr,
1713 int chunkstart, int n_valid, int n_invalid)
1714 {
1715 qemu_put_be32(f, chunkstart);
1716 qemu_put_be16(f, n_valid);
1717 qemu_put_be16(f, n_invalid);
1718 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1719 HASH_PTE_SIZE_64 * n_valid);
1720 }
1721
1722 static void htab_save_end_marker(QEMUFile *f)
1723 {
1724 qemu_put_be32(f, 0);
1725 qemu_put_be16(f, 0);
1726 qemu_put_be16(f, 0);
1727 }
1728
1729 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr,
1730 int64_t max_ns)
1731 {
1732 bool has_timeout = max_ns != -1;
1733 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1734 int index = spapr->htab_save_index;
1735 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1736
1737 assert(spapr->htab_first_pass);
1738
1739 do {
1740 int chunkstart;
1741
1742 /* Consume invalid HPTEs */
1743 while ((index < htabslots)
1744 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1745 CLEAN_HPTE(HPTE(spapr->htab, index));
1746 index++;
1747 }
1748
1749 /* Consume valid HPTEs */
1750 chunkstart = index;
1751 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1752 && HPTE_VALID(HPTE(spapr->htab, index))) {
1753 CLEAN_HPTE(HPTE(spapr->htab, index));
1754 index++;
1755 }
1756
1757 if (index > chunkstart) {
1758 int n_valid = index - chunkstart;
1759
1760 htab_save_chunk(f, spapr, chunkstart, n_valid, 0);
1761
1762 if (has_timeout &&
1763 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1764 break;
1765 }
1766 }
1767 } while ((index < htabslots) && !qemu_file_rate_limit(f));
1768
1769 if (index >= htabslots) {
1770 assert(index == htabslots);
1771 index = 0;
1772 spapr->htab_first_pass = false;
1773 }
1774 spapr->htab_save_index = index;
1775 }
1776
1777 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr,
1778 int64_t max_ns)
1779 {
1780 bool final = max_ns < 0;
1781 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1782 int examined = 0, sent = 0;
1783 int index = spapr->htab_save_index;
1784 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1785
1786 assert(!spapr->htab_first_pass);
1787
1788 do {
1789 int chunkstart, invalidstart;
1790
1791 /* Consume non-dirty HPTEs */
1792 while ((index < htabslots)
1793 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
1794 index++;
1795 examined++;
1796 }
1797
1798 chunkstart = index;
1799 /* Consume valid dirty HPTEs */
1800 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1801 && HPTE_DIRTY(HPTE(spapr->htab, index))
1802 && HPTE_VALID(HPTE(spapr->htab, index))) {
1803 CLEAN_HPTE(HPTE(spapr->htab, index));
1804 index++;
1805 examined++;
1806 }
1807
1808 invalidstart = index;
1809 /* Consume invalid dirty HPTEs */
1810 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
1811 && HPTE_DIRTY(HPTE(spapr->htab, index))
1812 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1813 CLEAN_HPTE(HPTE(spapr->htab, index));
1814 index++;
1815 examined++;
1816 }
1817
1818 if (index > chunkstart) {
1819 int n_valid = invalidstart - chunkstart;
1820 int n_invalid = index - invalidstart;
1821
1822 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid);
1823 sent += index - chunkstart;
1824
1825 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1826 break;
1827 }
1828 }
1829
1830 if (examined >= htabslots) {
1831 break;
1832 }
1833
1834 if (index >= htabslots) {
1835 assert(index == htabslots);
1836 index = 0;
1837 }
1838 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
1839
1840 if (index >= htabslots) {
1841 assert(index == htabslots);
1842 index = 0;
1843 }
1844
1845 spapr->htab_save_index = index;
1846
1847 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
1848 }
1849
1850 #define MAX_ITERATION_NS 5000000 /* 5 ms */
1851 #define MAX_KVM_BUF_SIZE 2048
1852
1853 static int htab_save_iterate(QEMUFile *f, void *opaque)
1854 {
1855 sPAPRMachineState *spapr = opaque;
1856 int fd;
1857 int rc = 0;
1858
1859 /* Iteration header */
1860 if (!spapr->htab_shift) {
1861 qemu_put_be32(f, -1);
1862 return 1;
1863 } else {
1864 qemu_put_be32(f, 0);
1865 }
1866
1867 if (!spapr->htab) {
1868 assert(kvm_enabled());
1869
1870 fd = get_htab_fd(spapr);
1871 if (fd < 0) {
1872 return fd;
1873 }
1874
1875 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
1876 if (rc < 0) {
1877 return rc;
1878 }
1879 } else if (spapr->htab_first_pass) {
1880 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
1881 } else {
1882 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
1883 }
1884
1885 htab_save_end_marker(f);
1886
1887 return rc;
1888 }
1889
1890 static int htab_save_complete(QEMUFile *f, void *opaque)
1891 {
1892 sPAPRMachineState *spapr = opaque;
1893 int fd;
1894
1895 /* Iteration header */
1896 if (!spapr->htab_shift) {
1897 qemu_put_be32(f, -1);
1898 return 0;
1899 } else {
1900 qemu_put_be32(f, 0);
1901 }
1902
1903 if (!spapr->htab) {
1904 int rc;
1905
1906 assert(kvm_enabled());
1907
1908 fd = get_htab_fd(spapr);
1909 if (fd < 0) {
1910 return fd;
1911 }
1912
1913 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
1914 if (rc < 0) {
1915 return rc;
1916 }
1917 } else {
1918 if (spapr->htab_first_pass) {
1919 htab_save_first_pass(f, spapr, -1);
1920 }
1921 htab_save_later_pass(f, spapr, -1);
1922 }
1923
1924 /* End marker */
1925 htab_save_end_marker(f);
1926
1927 return 0;
1928 }
1929
1930 static int htab_load(QEMUFile *f, void *opaque, int version_id)
1931 {
1932 sPAPRMachineState *spapr = opaque;
1933 uint32_t section_hdr;
1934 int fd = -1;
1935 Error *local_err = NULL;
1936
1937 if (version_id < 1 || version_id > 1) {
1938 error_report("htab_load() bad version");
1939 return -EINVAL;
1940 }
1941
1942 section_hdr = qemu_get_be32(f);
1943
1944 if (section_hdr == -1) {
1945 spapr_free_hpt(spapr);
1946 return 0;
1947 }
1948
1949 if (section_hdr) {
1950 /* First section gives the htab size */
1951 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
1952 if (local_err) {
1953 error_report_err(local_err);
1954 return -EINVAL;
1955 }
1956 return 0;
1957 }
1958
1959 if (!spapr->htab) {
1960 assert(kvm_enabled());
1961
1962 fd = kvmppc_get_htab_fd(true, 0, &local_err);
1963 if (fd < 0) {
1964 error_report_err(local_err);
1965 return fd;
1966 }
1967 }
1968
1969 while (true) {
1970 uint32_t index;
1971 uint16_t n_valid, n_invalid;
1972
1973 index = qemu_get_be32(f);
1974 n_valid = qemu_get_be16(f);
1975 n_invalid = qemu_get_be16(f);
1976
1977 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
1978 /* End of Stream */
1979 break;
1980 }
1981
1982 if ((index + n_valid + n_invalid) >
1983 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
1984 /* Bad index in stream */
1985 error_report(
1986 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
1987 index, n_valid, n_invalid, spapr->htab_shift);
1988 return -EINVAL;
1989 }
1990
1991 if (spapr->htab) {
1992 if (n_valid) {
1993 qemu_get_buffer(f, HPTE(spapr->htab, index),
1994 HASH_PTE_SIZE_64 * n_valid);
1995 }
1996 if (n_invalid) {
1997 memset(HPTE(spapr->htab, index + n_valid), 0,
1998 HASH_PTE_SIZE_64 * n_invalid);
1999 }
2000 } else {
2001 int rc;
2002
2003 assert(fd >= 0);
2004
2005 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
2006 if (rc < 0) {
2007 return rc;
2008 }
2009 }
2010 }
2011
2012 if (!spapr->htab) {
2013 assert(fd >= 0);
2014 close(fd);
2015 }
2016
2017 return 0;
2018 }
2019
2020 static void htab_save_cleanup(void *opaque)
2021 {
2022 sPAPRMachineState *spapr = opaque;
2023
2024 close_htab_fd(spapr);
2025 }
2026
2027 static SaveVMHandlers savevm_htab_handlers = {
2028 .save_setup = htab_save_setup,
2029 .save_live_iterate = htab_save_iterate,
2030 .save_live_complete_precopy = htab_save_complete,
2031 .save_cleanup = htab_save_cleanup,
2032 .load_state = htab_load,
2033 };
2034
2035 static void spapr_boot_set(void *opaque, const char *boot_device,
2036 Error **errp)
2037 {
2038 MachineState *machine = MACHINE(opaque);
2039 machine->boot_order = g_strdup(boot_device);
2040 }
2041
2042 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
2043 {
2044 MachineState *machine = MACHINE(spapr);
2045 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
2046 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
2047 int i;
2048
2049 for (i = 0; i < nr_lmbs; i++) {
2050 uint64_t addr;
2051
2052 addr = i * lmb_size + spapr->hotplug_memory.base;
2053 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB,
2054 addr / lmb_size);
2055 }
2056 }
2057
2058 /*
2059 * If RAM size, maxmem size and individual node mem sizes aren't aligned
2060 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
2061 * since we can't support such unaligned sizes with DRCONF_MEMORY.
2062 */
2063 static void spapr_validate_node_memory(MachineState *machine, Error **errp)
2064 {
2065 int i;
2066
2067 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2068 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
2069 " is not aligned to %llu MiB",
2070 machine->ram_size,
2071 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
2072 return;
2073 }
2074
2075 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2076 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
2077 " is not aligned to %llu MiB",
2078 machine->ram_size,
2079 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
2080 return;
2081 }
2082
2083 for (i = 0; i < nb_numa_nodes; i++) {
2084 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
2085 error_setg(errp,
2086 "Node %d memory size 0x%" PRIx64
2087 " is not aligned to %llu MiB",
2088 i, numa_info[i].node_mem,
2089 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
2090 return;
2091 }
2092 }
2093 }
2094
2095 /* find cpu slot in machine->possible_cpus by core_id */
2096 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
2097 {
2098 int index = id / smp_threads;
2099
2100 if (index >= ms->possible_cpus->len) {
2101 return NULL;
2102 }
2103 if (idx) {
2104 *idx = index;
2105 }
2106 return &ms->possible_cpus->cpus[index];
2107 }
2108
2109 static void spapr_init_cpus(sPAPRMachineState *spapr)
2110 {
2111 MachineState *machine = MACHINE(spapr);
2112 MachineClass *mc = MACHINE_GET_CLASS(machine);
2113 char *type = spapr_get_cpu_core_type(machine->cpu_model);
2114 int smt = kvmppc_smt_threads();
2115 const CPUArchIdList *possible_cpus;
2116 int boot_cores_nr = smp_cpus / smp_threads;
2117 int i;
2118
2119 if (!type) {
2120 error_report("Unable to find sPAPR CPU Core definition");
2121 exit(1);
2122 }
2123
2124 possible_cpus = mc->possible_cpu_arch_ids(machine);
2125 if (mc->has_hotpluggable_cpus) {
2126 if (smp_cpus % smp_threads) {
2127 error_report("smp_cpus (%u) must be multiple of threads (%u)",
2128 smp_cpus, smp_threads);
2129 exit(1);
2130 }
2131 if (max_cpus % smp_threads) {
2132 error_report("max_cpus (%u) must be multiple of threads (%u)",
2133 max_cpus, smp_threads);
2134 exit(1);
2135 }
2136 } else {
2137 if (max_cpus != smp_cpus) {
2138 error_report("This machine version does not support CPU hotplug");
2139 exit(1);
2140 }
2141 boot_cores_nr = possible_cpus->len;
2142 }
2143
2144 for (i = 0; i < possible_cpus->len; i++) {
2145 int core_id = i * smp_threads;
2146
2147 if (mc->has_hotpluggable_cpus) {
2148 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU,
2149 (core_id / smp_threads) * smt);
2150 }
2151
2152 if (i < boot_cores_nr) {
2153 Object *core = object_new(type);
2154 int nr_threads = smp_threads;
2155
2156 /* Handle the partially filled core for older machine types */
2157 if ((i + 1) * smp_threads >= smp_cpus) {
2158 nr_threads = smp_cpus - i * smp_threads;
2159 }
2160
2161 object_property_set_int(core, nr_threads, "nr-threads",
2162 &error_fatal);
2163 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
2164 &error_fatal);
2165 object_property_set_bool(core, true, "realized", &error_fatal);
2166 }
2167 }
2168 g_free(type);
2169 }
2170
2171 static void spapr_set_vsmt_mode(sPAPRMachineState *spapr, Error **errp)
2172 {
2173 Error *local_err = NULL;
2174 bool vsmt_user = !!spapr->vsmt;
2175 int kvm_smt = kvmppc_smt_threads();
2176 int ret;
2177
2178 if (!kvm_enabled() && (smp_threads > 1)) {
2179 error_setg(&local_err, "TCG cannot support more than 1 thread/core "
2180 "on a pseries machine");
2181 goto out;
2182 }
2183 if (!is_power_of_2(smp_threads)) {
2184 error_setg(&local_err, "Cannot support %d threads/core on a pseries "
2185 "machine because it must be a power of 2", smp_threads);
2186 goto out;
2187 }
2188
2189 /* Detemine the VSMT mode to use: */
2190 if (vsmt_user) {
2191 if (spapr->vsmt < smp_threads) {
2192 error_setg(&local_err, "Cannot support VSMT mode %d"
2193 " because it must be >= threads/core (%d)",
2194 spapr->vsmt, smp_threads);
2195 goto out;
2196 }
2197 /* In this case, spapr->vsmt has been set by the command line */
2198 } else {
2199 /* Choose a VSMT mode that may be higher than necessary but is
2200 * likely to be compatible with hosts that don't have VSMT. */
2201 spapr->vsmt = MAX(kvm_smt, smp_threads);
2202 }
2203
2204 /* KVM: If necessary, set the SMT mode: */
2205 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) {
2206 ret = kvmppc_set_smt_threads(spapr->vsmt);
2207 if (ret) {
2208 error_setg(&local_err,
2209 "Failed to set KVM's VSMT mode to %d (errno %d)",
2210 spapr->vsmt, ret);
2211 if (!vsmt_user) {
2212 error_append_hint(&local_err, "On PPC, a VM with %d threads/"
2213 "core on a host with %d threads/core requires "
2214 " the use of VSMT mode %d.\n",
2215 smp_threads, kvm_smt, spapr->vsmt);
2216 }
2217 kvmppc_hint_smt_possible(&local_err);
2218 goto out;
2219 }
2220 }
2221 /* else TCG: nothing to do currently */
2222 out:
2223 error_propagate(errp, local_err);
2224 }
2225
2226 /* pSeries LPAR / sPAPR hardware init */
2227 static void ppc_spapr_init(MachineState *machine)
2228 {
2229 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
2230 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2231 const char *kernel_filename = machine->kernel_filename;
2232 const char *initrd_filename = machine->initrd_filename;
2233 PCIHostState *phb;
2234 int i;
2235 MemoryRegion *sysmem = get_system_memory();
2236 MemoryRegion *ram = g_new(MemoryRegion, 1);
2237 MemoryRegion *rma_region;
2238 void *rma = NULL;
2239 hwaddr rma_alloc_size;
2240 hwaddr node0_size = spapr_node0_size(machine);
2241 long load_limit, fw_size;
2242 char *filename;
2243 Error *resize_hpt_err = NULL;
2244
2245 msi_nonbroken = true;
2246
2247 QLIST_INIT(&spapr->phbs);
2248 QTAILQ_INIT(&spapr->pending_dimm_unplugs);
2249
2250 /* Check HPT resizing availability */
2251 kvmppc_check_papr_resize_hpt(&resize_hpt_err);
2252 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) {
2253 /*
2254 * If the user explicitly requested a mode we should either
2255 * supply it, or fail completely (which we do below). But if
2256 * it's not set explicitly, we reset our mode to something
2257 * that works
2258 */
2259 if (resize_hpt_err) {
2260 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
2261 error_free(resize_hpt_err);
2262 resize_hpt_err = NULL;
2263 } else {
2264 spapr->resize_hpt = smc->resize_hpt_default;
2265 }
2266 }
2267
2268 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT);
2269
2270 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) {
2271 /*
2272 * User requested HPT resize, but this host can't supply it. Bail out
2273 */
2274 error_report_err(resize_hpt_err);
2275 exit(1);
2276 }
2277
2278 /* Allocate RMA if necessary */
2279 rma_alloc_size = kvmppc_alloc_rma(&rma);
2280
2281 if (rma_alloc_size == -1) {
2282 error_report("Unable to create RMA");
2283 exit(1);
2284 }
2285
2286 if (rma_alloc_size && (rma_alloc_size < node0_size)) {
2287 spapr->rma_size = rma_alloc_size;
2288 } else {
2289 spapr->rma_size = node0_size;
2290
2291 /* With KVM, we don't actually know whether KVM supports an
2292 * unbounded RMA (PR KVM) or is limited by the hash table size
2293 * (HV KVM using VRMA), so we always assume the latter
2294 *
2295 * In that case, we also limit the initial allocations for RTAS
2296 * etc... to 256M since we have no way to know what the VRMA size
2297 * is going to be as it depends on the size of the hash table
2298 * isn't determined yet.
2299 */
2300 if (kvm_enabled()) {
2301 spapr->vrma_adjust = 1;
2302 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
2303 }
2304
2305 /* Actually we don't support unbounded RMA anymore since we
2306 * added proper emulation of HV mode. The max we can get is
2307 * 16G which also happens to be what we configure for PAPR
2308 * mode so make sure we don't do anything bigger than that
2309 */
2310 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull);
2311 }
2312
2313 if (spapr->rma_size > node0_size) {
2314 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
2315 spapr->rma_size);
2316 exit(1);
2317 }
2318
2319 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
2320 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
2321
2322 /* Set up Interrupt Controller before we create the VCPUs */
2323 xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal);
2324
2325 /* Set up containers for ibm,client-set-architecture negotiated options */
2326 spapr->ov5 = spapr_ovec_new();
2327 spapr->ov5_cas = spapr_ovec_new();
2328
2329 if (smc->dr_lmb_enabled) {
2330 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY);
2331 spapr_validate_node_memory(machine, &error_fatal);
2332 }
2333
2334 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY);
2335 if (!kvm_enabled() || kvmppc_has_cap_mmu_radix()) {
2336 /* KVM and TCG always allow GTSE with radix... */
2337 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE);
2338 }
2339 /* ... but not with hash (currently). */
2340
2341 /* advertise support for dedicated HP event source to guests */
2342 if (spapr->use_hotplug_event_source) {
2343 spapr_ovec_set(spapr->ov5, OV5_HP_EVT);
2344 }
2345
2346 /* advertise support for HPT resizing */
2347 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
2348 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE);
2349 }
2350
2351 /* init CPUs */
2352 if (machine->cpu_model == NULL) {
2353 machine->cpu_model = kvm_enabled() ? "host" : smc->tcg_default_cpu;
2354 }
2355
2356 spapr_cpu_parse_features(spapr);
2357
2358 spapr_set_vsmt_mode(spapr, &error_fatal);
2359
2360 spapr_init_cpus(spapr);
2361
2362 if (kvm_enabled()) {
2363 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2364 kvmppc_enable_logical_ci_hcalls();
2365 kvmppc_enable_set_mode_hcall();
2366
2367 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
2368 kvmppc_enable_clear_ref_mod_hcalls();
2369 }
2370
2371 /* allocate RAM */
2372 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
2373 machine->ram_size);
2374 memory_region_add_subregion(sysmem, 0, ram);
2375
2376 if (rma_alloc_size && rma) {
2377 rma_region = g_new(MemoryRegion, 1);
2378 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma",
2379 rma_alloc_size, rma);
2380 vmstate_register_ram_global(rma_region);
2381 memory_region_add_subregion(sysmem, 0, rma_region);
2382 }
2383
2384 /* initialize hotplug memory address space */
2385 if (machine->ram_size < machine->maxram_size) {
2386 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size;
2387 /*
2388 * Limit the number of hotpluggable memory slots to half the number
2389 * slots that KVM supports, leaving the other half for PCI and other
2390 * devices. However ensure that number of slots doesn't drop below 32.
2391 */
2392 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
2393 SPAPR_MAX_RAM_SLOTS;
2394
2395 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
2396 max_memslots = SPAPR_MAX_RAM_SLOTS;
2397 }
2398 if (machine->ram_slots > max_memslots) {
2399 error_report("Specified number of memory slots %"
2400 PRIu64" exceeds max supported %d",
2401 machine->ram_slots, max_memslots);
2402 exit(1);
2403 }
2404
2405 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size,
2406 SPAPR_HOTPLUG_MEM_ALIGN);
2407 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr),
2408 "hotplug-memory", hotplug_mem_size);
2409 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base,
2410 &spapr->hotplug_memory.mr);
2411 }
2412
2413 if (smc->dr_lmb_enabled) {
2414 spapr_create_lmb_dr_connectors(spapr);
2415 }
2416
2417 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
2418 if (!filename) {
2419 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
2420 exit(1);
2421 }
2422 spapr->rtas_size = get_image_size(filename);
2423 if (spapr->rtas_size < 0) {
2424 error_report("Could not get size of LPAR rtas '%s'", filename);
2425 exit(1);
2426 }
2427 spapr->rtas_blob = g_malloc(spapr->rtas_size);
2428 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
2429 error_report("Could not load LPAR rtas '%s'", filename);
2430 exit(1);
2431 }
2432 if (spapr->rtas_size > RTAS_MAX_SIZE) {
2433 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
2434 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
2435 exit(1);
2436 }
2437 g_free(filename);
2438
2439 /* Set up RTAS event infrastructure */
2440 spapr_events_init(spapr);
2441
2442 /* Set up the RTC RTAS interfaces */
2443 spapr_rtc_create(spapr);
2444
2445 /* Set up VIO bus */
2446 spapr->vio_bus = spapr_vio_bus_init();
2447
2448 for (i = 0; i < MAX_SERIAL_PORTS; i++) {
2449 if (serial_hds[i]) {
2450 spapr_vty_create(spapr->vio_bus, serial_hds[i]);
2451 }
2452 }
2453
2454 /* We always have at least the nvram device on VIO */
2455 spapr_create_nvram(spapr);
2456
2457 /* Set up PCI */
2458 spapr_pci_rtas_init();
2459
2460 phb = spapr_create_phb(spapr, 0);
2461
2462 for (i = 0; i < nb_nics; i++) {
2463 NICInfo *nd = &nd_table[i];
2464
2465 if (!nd->model) {
2466 nd->model = g_strdup("ibmveth");
2467 }
2468
2469 if (strcmp(nd->model, "ibmveth") == 0) {
2470 spapr_vlan_create(spapr->vio_bus, nd);
2471 } else {
2472 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
2473 }
2474 }
2475
2476 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
2477 spapr_vscsi_create(spapr->vio_bus);
2478 }
2479
2480 /* Graphics */
2481 if (spapr_vga_init(phb->bus, &error_fatal)) {
2482 spapr->has_graphics = true;
2483 machine->usb |= defaults_enabled() && !machine->usb_disabled;
2484 }
2485
2486 if (machine->usb) {
2487 if (smc->use_ohci_by_default) {
2488 pci_create_simple(phb->bus, -1, "pci-ohci");
2489 } else {
2490 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
2491 }
2492
2493 if (spapr->has_graphics) {
2494 USBBus *usb_bus = usb_bus_find(-1);
2495
2496 usb_create_simple(usb_bus, "usb-kbd");
2497 usb_create_simple(usb_bus, "usb-mouse");
2498 }
2499 }
2500
2501 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
2502 error_report(
2503 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
2504 MIN_RMA_SLOF);
2505 exit(1);
2506 }
2507
2508 if (kernel_filename) {
2509 uint64_t lowaddr = 0;
2510
2511 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address,
2512 NULL, NULL, &lowaddr, NULL, 1,
2513 PPC_ELF_MACHINE, 0, 0);
2514 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) {
2515 spapr->kernel_size = load_elf(kernel_filename,
2516 translate_kernel_address, NULL, NULL,
2517 &lowaddr, NULL, 0, PPC_ELF_MACHINE,
2518 0, 0);
2519 spapr->kernel_le = spapr->kernel_size > 0;
2520 }
2521 if (spapr->kernel_size < 0) {
2522 error_report("error loading %s: %s", kernel_filename,
2523 load_elf_strerror(spapr->kernel_size));
2524 exit(1);
2525 }
2526
2527 /* load initrd */
2528 if (initrd_filename) {
2529 /* Try to locate the initrd in the gap between the kernel
2530 * and the firmware. Add a bit of space just in case
2531 */
2532 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size
2533 + 0x1ffff) & ~0xffff;
2534 spapr->initrd_size = load_image_targphys(initrd_filename,
2535 spapr->initrd_base,
2536 load_limit
2537 - spapr->initrd_base);
2538 if (spapr->initrd_size < 0) {
2539 error_report("could not load initial ram disk '%s'",
2540 initrd_filename);
2541 exit(1);
2542 }
2543 }
2544 }
2545
2546 if (bios_name == NULL) {
2547 bios_name = FW_FILE_NAME;
2548 }
2549 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
2550 if (!filename) {
2551 error_report("Could not find LPAR firmware '%s'", bios_name);
2552 exit(1);
2553 }
2554 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
2555 if (fw_size <= 0) {
2556 error_report("Could not load LPAR firmware '%s'", filename);
2557 exit(1);
2558 }
2559 g_free(filename);
2560
2561 /* FIXME: Should register things through the MachineState's qdev
2562 * interface, this is a legacy from the sPAPREnvironment structure
2563 * which predated MachineState but had a similar function */
2564 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
2565 register_savevm_live(NULL, "spapr/htab", -1, 1,
2566 &savevm_htab_handlers, spapr);
2567
2568 qemu_register_boot_set(spapr_boot_set, spapr);
2569
2570 if (kvm_enabled()) {
2571 /* to stop and start vmclock */
2572 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change,
2573 &spapr->tb);
2574
2575 kvmppc_spapr_enable_inkernel_multitce();
2576 }
2577 }
2578
2579 static int spapr_kvm_type(const char *vm_type)
2580 {
2581 if (!vm_type) {
2582 return 0;
2583 }
2584
2585 if (!strcmp(vm_type, "HV")) {
2586 return 1;
2587 }
2588
2589 if (!strcmp(vm_type, "PR")) {
2590 return 2;
2591 }
2592
2593 error_report("Unknown kvm-type specified '%s'", vm_type);
2594 exit(1);
2595 }
2596
2597 /*
2598 * Implementation of an interface to adjust firmware path
2599 * for the bootindex property handling.
2600 */
2601 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
2602 DeviceState *dev)
2603 {
2604 #define CAST(type, obj, name) \
2605 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2606 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
2607 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
2608 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON);
2609
2610 if (d) {
2611 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
2612 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
2613 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
2614
2615 if (spapr) {
2616 /*
2617 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
2618 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
2619 * in the top 16 bits of the 64-bit LUN
2620 */
2621 unsigned id = 0x8000 | (d->id << 8) | d->lun;
2622 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2623 (uint64_t)id << 48);
2624 } else if (virtio) {
2625 /*
2626 * We use SRP luns of the form 01000000 | (target << 8) | lun
2627 * in the top 32 bits of the 64-bit LUN
2628 * Note: the quote above is from SLOF and it is wrong,
2629 * the actual binding is:
2630 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
2631 */
2632 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
2633 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2634 (uint64_t)id << 32);
2635 } else if (usb) {
2636 /*
2637 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
2638 * in the top 32 bits of the 64-bit LUN
2639 */
2640 unsigned usb_port = atoi(usb->port->path);
2641 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
2642 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2643 (uint64_t)id << 32);
2644 }
2645 }
2646
2647 /*
2648 * SLOF probes the USB devices, and if it recognizes that the device is a
2649 * storage device, it changes its name to "storage" instead of "usb-host",
2650 * and additionally adds a child node for the SCSI LUN, so the correct
2651 * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
2652 */
2653 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) {
2654 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE);
2655 if (usb_host_dev_is_scsi_storage(usbdev)) {
2656 return g_strdup_printf("storage@%s/disk", usbdev->port->path);
2657 }
2658 }
2659
2660 if (phb) {
2661 /* Replace "pci" with "pci@800000020000000" */
2662 return g_strdup_printf("pci@%"PRIX64, phb->buid);
2663 }
2664
2665 if (vsc) {
2666 /* Same logic as virtio above */
2667 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun;
2668 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32);
2669 }
2670
2671 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) {
2672 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */
2673 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE);
2674 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn));
2675 }
2676
2677 return NULL;
2678 }
2679
2680 static char *spapr_get_kvm_type(Object *obj, Error **errp)
2681 {
2682 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2683
2684 return g_strdup(spapr->kvm_type);
2685 }
2686
2687 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
2688 {
2689 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2690
2691 g_free(spapr->kvm_type);
2692 spapr->kvm_type = g_strdup(value);
2693 }
2694
2695 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp)
2696 {
2697 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2698
2699 return spapr->use_hotplug_event_source;
2700 }
2701
2702 static void spapr_set_modern_hotplug_events(Object *obj, bool value,
2703 Error **errp)
2704 {
2705 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2706
2707 spapr->use_hotplug_event_source = value;
2708 }
2709
2710 static char *spapr_get_resize_hpt(Object *obj, Error **errp)
2711 {
2712 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2713
2714 switch (spapr->resize_hpt) {
2715 case SPAPR_RESIZE_HPT_DEFAULT:
2716 return g_strdup("default");
2717 case SPAPR_RESIZE_HPT_DISABLED:
2718 return g_strdup("disabled");
2719 case SPAPR_RESIZE_HPT_ENABLED:
2720 return g_strdup("enabled");
2721 case SPAPR_RESIZE_HPT_REQUIRED:
2722 return g_strdup("required");
2723 }
2724 g_assert_not_reached();
2725 }
2726
2727 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp)
2728 {
2729 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2730
2731 if (strcmp(value, "default") == 0) {
2732 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT;
2733 } else if (strcmp(value, "disabled") == 0) {
2734 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
2735 } else if (strcmp(value, "enabled") == 0) {
2736 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED;
2737 } else if (strcmp(value, "required") == 0) {
2738 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED;
2739 } else {
2740 error_setg(errp, "Bad value for \"resize-hpt\" property");
2741 }
2742 }
2743
2744 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name,
2745 void *opaque, Error **errp)
2746 {
2747 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
2748 }
2749
2750 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name,
2751 void *opaque, Error **errp)
2752 {
2753 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
2754 }
2755
2756 static void spapr_machine_initfn(Object *obj)
2757 {
2758 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2759
2760 spapr->htab_fd = -1;
2761 spapr->use_hotplug_event_source = true;
2762 object_property_add_str(obj, "kvm-type",
2763 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
2764 object_property_set_description(obj, "kvm-type",
2765 "Specifies the KVM virtualization mode (HV, PR)",
2766 NULL);
2767 object_property_add_bool(obj, "modern-hotplug-events",
2768 spapr_get_modern_hotplug_events,
2769 spapr_set_modern_hotplug_events,
2770 NULL);
2771 object_property_set_description(obj, "modern-hotplug-events",
2772 "Use dedicated hotplug event mechanism in"
2773 " place of standard EPOW events when possible"
2774 " (required for memory hot-unplug support)",
2775 NULL);
2776
2777 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr,
2778 "Maximum permitted CPU compatibility mode",
2779 &error_fatal);
2780
2781 object_property_add_str(obj, "resize-hpt",
2782 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL);
2783 object_property_set_description(obj, "resize-hpt",
2784 "Resizing of the Hash Page Table (enabled, disabled, required)",
2785 NULL);
2786 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt,
2787 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort);
2788 object_property_set_description(obj, "vsmt",
2789 "Virtual SMT: KVM behaves as if this were"
2790 " the host's SMT mode", &error_abort);
2791 }
2792
2793 static void spapr_machine_finalizefn(Object *obj)
2794 {
2795 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2796
2797 g_free(spapr->kvm_type);
2798 }
2799
2800 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg)
2801 {
2802 cpu_synchronize_state(cs);
2803 ppc_cpu_do_system_reset(cs);
2804 }
2805
2806 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
2807 {
2808 CPUState *cs;
2809
2810 CPU_FOREACH(cs) {
2811 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
2812 }
2813 }
2814
2815 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size,
2816 uint32_t node, bool dedicated_hp_event_source,
2817 Error **errp)
2818 {
2819 sPAPRDRConnector *drc;
2820 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
2821 int i, fdt_offset, fdt_size;
2822 void *fdt;
2823 uint64_t addr = addr_start;
2824 bool hotplugged = spapr_drc_hotplugged(dev);
2825 Error *local_err = NULL;
2826
2827 for (i = 0; i < nr_lmbs; i++) {
2828 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
2829 addr / SPAPR_MEMORY_BLOCK_SIZE);
2830 g_assert(drc);
2831
2832 fdt = create_device_tree(&fdt_size);
2833 fdt_offset = spapr_populate_memory_node(fdt, node, addr,
2834 SPAPR_MEMORY_BLOCK_SIZE);
2835
2836 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err);
2837 if (local_err) {
2838 while (addr > addr_start) {
2839 addr -= SPAPR_MEMORY_BLOCK_SIZE;
2840 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
2841 addr / SPAPR_MEMORY_BLOCK_SIZE);
2842 spapr_drc_detach(drc);
2843 }
2844 g_free(fdt);
2845 error_propagate(errp, local_err);
2846 return;
2847 }
2848 if (!hotplugged) {
2849 spapr_drc_reset(drc);
2850 }
2851 addr += SPAPR_MEMORY_BLOCK_SIZE;
2852 }
2853 /* send hotplug notification to the
2854 * guest only in case of hotplugged memory
2855 */
2856 if (hotplugged) {
2857 if (dedicated_hp_event_source) {
2858 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
2859 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
2860 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
2861 nr_lmbs,
2862 spapr_drc_index(drc));
2863 } else {
2864 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB,
2865 nr_lmbs);
2866 }
2867 }
2868 }
2869
2870 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2871 uint32_t node, Error **errp)
2872 {
2873 Error *local_err = NULL;
2874 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
2875 PCDIMMDevice *dimm = PC_DIMM(dev);
2876 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2877 MemoryRegion *mr;
2878 uint64_t align, size, addr;
2879
2880 mr = ddc->get_memory_region(dimm, &local_err);
2881 if (local_err) {
2882 goto out;
2883 }
2884 align = memory_region_get_alignment(mr);
2885 size = memory_region_size(mr);
2886
2887 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err);
2888 if (local_err) {
2889 goto out;
2890 }
2891
2892 addr = object_property_get_uint(OBJECT(dimm),
2893 PC_DIMM_ADDR_PROP, &local_err);
2894 if (local_err) {
2895 goto out_unplug;
2896 }
2897
2898 spapr_add_lmbs(dev, addr, size, node,
2899 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT),
2900 &local_err);
2901 if (local_err) {
2902 goto out_unplug;
2903 }
2904
2905 return;
2906
2907 out_unplug:
2908 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
2909 out:
2910 error_propagate(errp, local_err);
2911 }
2912
2913 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2914 Error **errp)
2915 {
2916 PCDIMMDevice *dimm = PC_DIMM(dev);
2917 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2918 MemoryRegion *mr;
2919 uint64_t size;
2920 char *mem_dev;
2921
2922 mr = ddc->get_memory_region(dimm, errp);
2923 if (!mr) {
2924 return;
2925 }
2926 size = memory_region_size(mr);
2927
2928 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
2929 error_setg(errp, "Hotplugged memory size must be a multiple of "
2930 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
2931 return;
2932 }
2933
2934 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL);
2935 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) {
2936 error_setg(errp, "Memory backend has bad page size. "
2937 "Use 'memory-backend-file' with correct mem-path.");
2938 goto out;
2939 }
2940
2941 out:
2942 g_free(mem_dev);
2943 }
2944
2945 struct sPAPRDIMMState {
2946 PCDIMMDevice *dimm;
2947 uint32_t nr_lmbs;
2948 QTAILQ_ENTRY(sPAPRDIMMState) next;
2949 };
2950
2951 static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s,
2952 PCDIMMDevice *dimm)
2953 {
2954 sPAPRDIMMState *dimm_state = NULL;
2955
2956 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) {
2957 if (dimm_state->dimm == dimm) {
2958 break;
2959 }
2960 }
2961 return dimm_state;
2962 }
2963
2964 static sPAPRDIMMState *spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr,
2965 uint32_t nr_lmbs,
2966 PCDIMMDevice *dimm)
2967 {
2968 sPAPRDIMMState *ds = NULL;
2969
2970 /*
2971 * If this request is for a DIMM whose removal had failed earlier
2972 * (due to guest's refusal to remove the LMBs), we would have this
2973 * dimm already in the pending_dimm_unplugs list. In that
2974 * case don't add again.
2975 */
2976 ds = spapr_pending_dimm_unplugs_find(spapr, dimm);
2977 if (!ds) {
2978 ds = g_malloc0(sizeof(sPAPRDIMMState));
2979 ds->nr_lmbs = nr_lmbs;
2980 ds->dimm = dimm;
2981 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next);
2982 }
2983 return ds;
2984 }
2985
2986 static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr,
2987 sPAPRDIMMState *dimm_state)
2988 {
2989 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next);
2990 g_free(dimm_state);
2991 }
2992
2993 static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms,
2994 PCDIMMDevice *dimm)
2995 {
2996 sPAPRDRConnector *drc;
2997 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2998 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort);
2999 uint64_t size = memory_region_size(mr);
3000 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
3001 uint32_t avail_lmbs = 0;
3002 uint64_t addr_start, addr;
3003 int i;
3004
3005 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP,
3006 &error_abort);
3007
3008 addr = addr_start;
3009 for (i = 0; i < nr_lmbs; i++) {
3010 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3011 addr / SPAPR_MEMORY_BLOCK_SIZE);
3012 g_assert(drc);
3013 if (drc->dev) {
3014 avail_lmbs++;
3015 }
3016 addr += SPAPR_MEMORY_BLOCK_SIZE;
3017 }
3018
3019 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm);
3020 }
3021
3022 /* Callback to be called during DRC release. */
3023 void spapr_lmb_release(DeviceState *dev)
3024 {
3025 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_hotplug_handler(dev));
3026 PCDIMMDevice *dimm = PC_DIMM(dev);
3027 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
3028 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort);
3029 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev));
3030
3031 /* This information will get lost if a migration occurs
3032 * during the unplug process. In this case recover it. */
3033 if (ds == NULL) {
3034 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev));
3035 g_assert(ds);
3036 /* The DRC being examined by the caller at least must be counted */
3037 g_assert(ds->nr_lmbs);
3038 }
3039
3040 if (--ds->nr_lmbs) {
3041 return;
3042 }
3043
3044 spapr_pending_dimm_unplugs_remove(spapr, ds);
3045
3046 /*
3047 * Now that all the LMBs have been removed by the guest, call the
3048 * pc-dimm unplug handler to cleanup up the pc-dimm device.
3049 */
3050 pc_dimm_memory_unplug(dev, &spapr->hotplug_memory, mr);
3051 object_unparent(OBJECT(dev));
3052 }
3053
3054 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev,
3055 DeviceState *dev, Error **errp)
3056 {
3057 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3058 Error *local_err = NULL;
3059 PCDIMMDevice *dimm = PC_DIMM(dev);
3060 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
3061 MemoryRegion *mr;
3062 uint32_t nr_lmbs;
3063 uint64_t size, addr_start, addr;
3064 int i;
3065 sPAPRDRConnector *drc;
3066
3067 mr = ddc->get_memory_region(dimm, &local_err);
3068 if (local_err) {
3069 goto out;
3070 }
3071 size = memory_region_size(mr);
3072 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
3073
3074 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP,
3075 &local_err);
3076 if (local_err) {
3077 goto out;
3078 }
3079
3080 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm);
3081
3082 addr = addr_start;
3083 for (i = 0; i < nr_lmbs; i++) {
3084 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3085 addr / SPAPR_MEMORY_BLOCK_SIZE);
3086 g_assert(drc);
3087
3088 spapr_drc_detach(drc);
3089 addr += SPAPR_MEMORY_BLOCK_SIZE;
3090 }
3091
3092 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3093 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
3094 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
3095 nr_lmbs, spapr_drc_index(drc));
3096 out:
3097 error_propagate(errp, local_err);
3098 }
3099
3100 static void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
3101 sPAPRMachineState *spapr)
3102 {
3103 PowerPCCPU *cpu = POWERPC_CPU(cs);
3104 DeviceClass *dc = DEVICE_GET_CLASS(cs);
3105 int id = spapr_vcpu_id(cpu);
3106 void *fdt;
3107 int offset, fdt_size;
3108 char *nodename;
3109
3110 fdt = create_device_tree(&fdt_size);
3111 nodename = g_strdup_printf("%s@%x", dc->fw_name, id);
3112 offset = fdt_add_subnode(fdt, 0, nodename);
3113
3114 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
3115 g_free(nodename);
3116
3117 *fdt_offset = offset;
3118 return fdt;
3119 }
3120
3121 /* Callback to be called during DRC release. */
3122 void spapr_core_release(DeviceState *dev)
3123 {
3124 MachineState *ms = MACHINE(qdev_get_hotplug_handler(dev));
3125 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms);
3126 CPUCore *cc = CPU_CORE(dev);
3127 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL);
3128
3129 if (smc->pre_2_10_has_unused_icps) {
3130 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
3131 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(cc));
3132 const char *typename = object_class_get_name(scc->cpu_class);
3133 size_t size = object_type_get_instance_size(typename);
3134 int i;
3135
3136 for (i = 0; i < cc->nr_threads; i++) {
3137 CPUState *cs = CPU(sc->threads + i * size);
3138
3139 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index);
3140 }
3141 }
3142
3143 assert(core_slot);
3144 core_slot->cpu = NULL;
3145 object_unparent(OBJECT(dev));
3146 }
3147
3148 static
3149 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev,
3150 Error **errp)
3151 {
3152 int index;
3153 sPAPRDRConnector *drc;
3154 CPUCore *cc = CPU_CORE(dev);
3155 int smt = kvmppc_smt_threads();
3156
3157 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) {
3158 error_setg(errp, "Unable to find CPU core with core-id: %d",
3159 cc->core_id);
3160 return;
3161 }
3162 if (index == 0) {
3163 error_setg(errp, "Boot CPU core may not be unplugged");
3164 return;
3165 }
3166
3167 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index * smt);
3168 g_assert(drc);
3169
3170 spapr_drc_detach(drc);
3171
3172 spapr_hotplug_req_remove_by_index(drc);
3173 }
3174
3175 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3176 Error **errp)
3177 {
3178 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3179 MachineClass *mc = MACHINE_GET_CLASS(spapr);
3180 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3181 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev));
3182 CPUCore *cc = CPU_CORE(dev);
3183 CPUState *cs = CPU(core->threads);
3184 sPAPRDRConnector *drc;
3185 Error *local_err = NULL;
3186 int smt = kvmppc_smt_threads();
3187 CPUArchId *core_slot;
3188 int index;
3189 bool hotplugged = spapr_drc_hotplugged(dev);
3190
3191 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3192 if (!core_slot) {
3193 error_setg(errp, "Unable to find CPU core with core-id: %d",
3194 cc->core_id);
3195 return;
3196 }
3197 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index * smt);
3198
3199 g_assert(drc || !mc->has_hotpluggable_cpus);
3200
3201 if (drc) {
3202 void *fdt;
3203 int fdt_offset;
3204
3205 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr);
3206
3207 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err);
3208 if (local_err) {
3209 g_free(fdt);
3210 error_propagate(errp, local_err);
3211 return;
3212 }
3213
3214 if (hotplugged) {
3215 /*
3216 * Send hotplug notification interrupt to the guest only
3217 * in case of hotplugged CPUs.
3218 */
3219 spapr_hotplug_req_add_by_index(drc);
3220 } else {
3221 spapr_drc_reset(drc);
3222 }
3223 }
3224
3225 core_slot->cpu = OBJECT(dev);
3226
3227 if (smc->pre_2_10_has_unused_icps) {
3228 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(cc));
3229 const char *typename = object_class_get_name(scc->cpu_class);
3230 size_t size = object_type_get_instance_size(typename);
3231 int i;
3232
3233 for (i = 0; i < cc->nr_threads; i++) {
3234 sPAPRCPUCore *sc = SPAPR_CPU_CORE(dev);
3235 void *obj = sc->threads + i * size;
3236
3237 cs = CPU(obj);
3238 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index);
3239 }
3240 }
3241 }
3242
3243 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3244 Error **errp)
3245 {
3246 MachineState *machine = MACHINE(OBJECT(hotplug_dev));
3247 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
3248 Error *local_err = NULL;
3249 CPUCore *cc = CPU_CORE(dev);
3250 char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model);
3251 const char *type = object_get_typename(OBJECT(dev));
3252 CPUArchId *core_slot;
3253 int index;
3254
3255 if (dev->hotplugged && !mc->has_hotpluggable_cpus) {
3256 error_setg(&local_err, "CPU hotplug not supported for this machine");
3257 goto out;
3258 }
3259
3260 if (strcmp(base_core_type, type)) {
3261 error_setg(&local_err, "CPU core type should be %s", base_core_type);
3262 goto out;
3263 }
3264
3265 if (cc->core_id % smp_threads) {
3266 error_setg(&local_err, "invalid core id %d", cc->core_id);
3267 goto out;
3268 }
3269
3270 /*
3271 * In general we should have homogeneous threads-per-core, but old
3272 * (pre hotplug support) machine types allow the last core to have
3273 * reduced threads as a compatibility hack for when we allowed
3274 * total vcpus not a multiple of threads-per-core.
3275 */
3276 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) {
3277 error_setg(&local_err, "invalid nr-threads %d, must be %d",
3278 cc->nr_threads, smp_threads);
3279 goto out;
3280 }
3281
3282 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3283 if (!core_slot) {
3284 error_setg(&local_err, "core id %d out of range", cc->core_id);
3285 goto out;
3286 }
3287
3288 if (core_slot->cpu) {
3289 error_setg(&local_err, "core %d already populated", cc->core_id);
3290 goto out;
3291 }
3292
3293 numa_cpu_pre_plug(core_slot, dev, &local_err);
3294
3295 out:
3296 g_free(base_core_type);
3297 error_propagate(errp, local_err);
3298 }
3299
3300 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
3301 DeviceState *dev, Error **errp)
3302 {
3303 MachineState *ms = MACHINE(hotplug_dev);
3304 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms);
3305
3306 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3307 int node;
3308
3309 if (!smc->dr_lmb_enabled) {
3310 error_setg(errp, "Memory hotplug not supported for this machine");
3311 return;
3312 }
3313 node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP, errp);
3314 if (*errp) {
3315 return;
3316 }
3317 if (node < 0 || node >= MAX_NODES) {
3318 error_setg(errp, "Invaild node %d", node);
3319 return;
3320 }
3321
3322 /*
3323 * Currently PowerPC kernel doesn't allow hot-adding memory to
3324 * memory-less node, but instead will silently add the memory
3325 * to the first node that has some memory. This causes two
3326 * unexpected behaviours for the user.
3327 *
3328 * - Memory gets hotplugged to a different node than what the user
3329 * specified.
3330 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs
3331 * to memory-less node, a reboot will set things accordingly
3332 * and the previously hotplugged memory now ends in the right node.
3333 * This appears as if some memory moved from one node to another.
3334 *
3335 * So until kernel starts supporting memory hotplug to memory-less
3336 * nodes, just prevent such attempts upfront in QEMU.
3337 */
3338 if (nb_numa_nodes && !numa_info[node].node_mem) {
3339 error_setg(errp, "Can't hotplug memory to memory-less node %d",
3340 node);
3341 return;
3342 }
3343
3344 spapr_memory_plug(hotplug_dev, dev, node, errp);
3345 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3346 spapr_core_plug(hotplug_dev, dev, errp);
3347 }
3348 }
3349
3350 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev,
3351 DeviceState *dev, Error **errp)
3352 {
3353 sPAPRMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev));
3354 MachineClass *mc = MACHINE_GET_CLASS(sms);
3355
3356 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3357 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) {
3358 spapr_memory_unplug_request(hotplug_dev, dev, errp);
3359 } else {
3360 /* NOTE: this means there is a window after guest reset, prior to
3361 * CAS negotiation, where unplug requests will fail due to the
3362 * capability not being detected yet. This is a bit different than
3363 * the case with PCI unplug, where the events will be queued and
3364 * eventually handled by the guest after boot
3365 */
3366 error_setg(errp, "Memory hot unplug not supported for this guest");
3367 }
3368 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3369 if (!mc->has_hotpluggable_cpus) {
3370 error_setg(errp, "CPU hot unplug not supported on this machine");
3371 return;
3372 }
3373 spapr_core_unplug_request(hotplug_dev, dev, errp);
3374 }
3375 }
3376
3377 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev,
3378 DeviceState *dev, Error **errp)
3379 {
3380 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3381 spapr_memory_pre_plug(hotplug_dev, dev, errp);
3382 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3383 spapr_core_pre_plug(hotplug_dev, dev, errp);
3384 }
3385 }
3386
3387 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine,
3388 DeviceState *dev)
3389 {
3390 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
3391 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3392 return HOTPLUG_HANDLER(machine);
3393 }
3394 return NULL;
3395 }
3396
3397 static CpuInstanceProperties
3398 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index)
3399 {
3400 CPUArchId *core_slot;
3401 MachineClass *mc = MACHINE_GET_CLASS(machine);
3402
3403 /* make sure possible_cpu are intialized */
3404 mc->possible_cpu_arch_ids(machine);
3405 /* get CPU core slot containing thread that matches cpu_index */
3406 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL);
3407 assert(core_slot);
3408 return core_slot->props;
3409 }
3410
3411 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx)
3412 {
3413 return idx / smp_cores % nb_numa_nodes;
3414 }
3415
3416 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine)
3417 {
3418 int i;
3419 int spapr_max_cores = max_cpus / smp_threads;
3420 MachineClass *mc = MACHINE_GET_CLASS(machine);
3421
3422 if (!mc->has_hotpluggable_cpus) {
3423 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads;
3424 }
3425 if (machine->possible_cpus) {
3426 assert(machine->possible_cpus->len == spapr_max_cores);
3427 return machine->possible_cpus;
3428 }
3429
3430 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
3431 sizeof(CPUArchId) * spapr_max_cores);
3432 machine->possible_cpus->len = spapr_max_cores;
3433 for (i = 0; i < machine->possible_cpus->len; i++) {
3434 int core_id = i * smp_threads;
3435
3436 machine->possible_cpus->cpus[i].vcpus_count = smp_threads;
3437 machine->possible_cpus->cpus[i].arch_id = core_id;
3438 machine->possible_cpus->cpus[i].props.has_core_id = true;
3439 machine->possible_cpus->cpus[i].props.core_id = core_id;
3440 }
3441 return machine->possible_cpus;
3442 }
3443
3444 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index,
3445 uint64_t *buid, hwaddr *pio,
3446 hwaddr *mmio32, hwaddr *mmio64,
3447 unsigned n_dma, uint32_t *liobns, Error **errp)
3448 {
3449 /*
3450 * New-style PHB window placement.
3451 *
3452 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
3453 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
3454 * windows.
3455 *
3456 * Some guest kernels can't work with MMIO windows above 1<<46
3457 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
3458 *
3459 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
3460 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the
3461 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the
3462 * 1TiB 64-bit MMIO windows for each PHB.
3463 */
3464 const uint64_t base_buid = 0x800000020000000ULL;
3465 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \
3466 SPAPR_PCI_MEM64_WIN_SIZE - 1)
3467 int i;
3468
3469 /* Sanity check natural alignments */
3470 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
3471 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
3472 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0);
3473 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0);
3474 /* Sanity check bounds */
3475 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) >
3476 SPAPR_PCI_MEM32_WIN_SIZE);
3477 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) >
3478 SPAPR_PCI_MEM64_WIN_SIZE);
3479
3480 if (index >= SPAPR_MAX_PHBS) {
3481 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)",
3482 SPAPR_MAX_PHBS - 1);
3483 return;
3484 }
3485
3486 *buid = base_buid + index;
3487 for (i = 0; i < n_dma; ++i) {
3488 liobns[i] = SPAPR_PCI_LIOBN(index, i);
3489 }
3490
3491 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE;
3492 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE;
3493 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE;
3494 }
3495
3496 static ICSState *spapr_ics_get(XICSFabric *dev, int irq)
3497 {
3498 sPAPRMachineState *spapr = SPAPR_MACHINE(dev);
3499
3500 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL;
3501 }
3502
3503 static void spapr_ics_resend(XICSFabric *dev)
3504 {
3505 sPAPRMachineState *spapr = SPAPR_MACHINE(dev);
3506
3507 ics_resend(spapr->ics);
3508 }
3509
3510 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id)
3511 {
3512 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id);
3513
3514 return cpu ? ICP(cpu->intc) : NULL;
3515 }
3516
3517 static void spapr_pic_print_info(InterruptStatsProvider *obj,
3518 Monitor *mon)
3519 {
3520 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3521 CPUState *cs;
3522
3523 CPU_FOREACH(cs) {
3524 PowerPCCPU *cpu = POWERPC_CPU(cs);
3525
3526 icp_pic_print_info(ICP(cpu->intc), mon);
3527 }
3528
3529 ics_pic_print_info(spapr->ics, mon);
3530 }
3531
3532 int spapr_vcpu_id(PowerPCCPU *cpu)
3533 {
3534 CPUState *cs = CPU(cpu);
3535
3536 if (kvm_enabled()) {
3537 return kvm_arch_vcpu_id(cs);
3538 } else {
3539 return cs->cpu_index;
3540 }
3541 }
3542
3543 PowerPCCPU *spapr_find_cpu(int vcpu_id)
3544 {
3545 CPUState *cs;
3546
3547 CPU_FOREACH(cs) {
3548 PowerPCCPU *cpu = POWERPC_CPU(cs);
3549
3550 if (spapr_vcpu_id(cpu) == vcpu_id) {
3551 return cpu;
3552 }
3553 }
3554
3555 return NULL;
3556 }
3557
3558 static void spapr_machine_class_init(ObjectClass *oc, void *data)
3559 {
3560 MachineClass *mc = MACHINE_CLASS(oc);
3561 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
3562 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
3563 NMIClass *nc = NMI_CLASS(oc);
3564 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
3565 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc);
3566 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
3567 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
3568
3569 mc->desc = "pSeries Logical Partition (PAPR compliant)";
3570
3571 /*
3572 * We set up the default / latest behaviour here. The class_init
3573 * functions for the specific versioned machine types can override
3574 * these details for backwards compatibility
3575 */
3576 mc->init = ppc_spapr_init;
3577 mc->reset = ppc_spapr_reset;
3578 mc->block_default_type = IF_SCSI;
3579 mc->max_cpus = 1024;
3580 mc->no_parallel = 1;
3581 mc->default_boot_order = "";
3582 mc->default_ram_size = 512 * M_BYTE;
3583 mc->kvm_type = spapr_kvm_type;
3584 mc->has_dynamic_sysbus = true;
3585 mc->pci_allow_0_address = true;
3586 mc->get_hotplug_handler = spapr_get_hotplug_handler;
3587 hc->pre_plug = spapr_machine_device_pre_plug;
3588 hc->plug = spapr_machine_device_plug;
3589 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props;
3590 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id;
3591 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids;
3592 hc->unplug_request = spapr_machine_device_unplug_request;
3593
3594 smc->dr_lmb_enabled = true;
3595 smc->tcg_default_cpu = "POWER8";
3596 mc->has_hotpluggable_cpus = true;
3597 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED;
3598 fwc->get_dev_path = spapr_get_fw_dev_path;
3599 nc->nmi_monitor_handler = spapr_nmi;
3600 smc->phb_placement = spapr_phb_placement;
3601 vhc->hypercall = emulate_spapr_hypercall;
3602 vhc->hpt_mask = spapr_hpt_mask;
3603 vhc->map_hptes = spapr_map_hptes;
3604 vhc->unmap_hptes = spapr_unmap_hptes;
3605 vhc->store_hpte = spapr_store_hpte;
3606 vhc->get_patbe = spapr_get_patbe;
3607 xic->ics_get = spapr_ics_get;
3608 xic->ics_resend = spapr_ics_resend;
3609 xic->icp_get = spapr_icp_get;
3610 ispc->print_info = spapr_pic_print_info;
3611 /* Force NUMA node memory size to be a multiple of
3612 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity
3613 * in which LMBs are represented and hot-added
3614 */
3615 mc->numa_mem_align_shift = 28;
3616 }
3617
3618 static const TypeInfo spapr_machine_info = {
3619 .name = TYPE_SPAPR_MACHINE,
3620 .parent = TYPE_MACHINE,
3621 .abstract = true,
3622 .instance_size = sizeof(sPAPRMachineState),
3623 .instance_init = spapr_machine_initfn,
3624 .instance_finalize = spapr_machine_finalizefn,
3625 .class_size = sizeof(sPAPRMachineClass),
3626 .class_init = spapr_machine_class_init,
3627 .interfaces = (InterfaceInfo[]) {
3628 { TYPE_FW_PATH_PROVIDER },
3629 { TYPE_NMI },
3630 { TYPE_HOTPLUG_HANDLER },
3631 { TYPE_PPC_VIRTUAL_HYPERVISOR },
3632 { TYPE_XICS_FABRIC },
3633 { TYPE_INTERRUPT_STATS_PROVIDER },
3634 { }
3635 },
3636 };
3637
3638 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
3639 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
3640 void *data) \
3641 { \
3642 MachineClass *mc = MACHINE_CLASS(oc); \
3643 spapr_machine_##suffix##_class_options(mc); \
3644 if (latest) { \
3645 mc->alias = "pseries"; \
3646 mc->is_default = 1; \
3647 } \
3648 } \
3649 static void spapr_machine_##suffix##_instance_init(Object *obj) \
3650 { \
3651 MachineState *machine = MACHINE(obj); \
3652 spapr_machine_##suffix##_instance_options(machine); \
3653 } \
3654 static const TypeInfo spapr_machine_##suffix##_info = { \
3655 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
3656 .parent = TYPE_SPAPR_MACHINE, \
3657 .class_init = spapr_machine_##suffix##_class_init, \
3658 .instance_init = spapr_machine_##suffix##_instance_init, \
3659 }; \
3660 static void spapr_machine_register_##suffix(void) \
3661 { \
3662 type_register(&spapr_machine_##suffix##_info); \
3663 } \
3664 type_init(spapr_machine_register_##suffix)
3665
3666 /*
3667 * pseries-2.11
3668 */
3669 static void spapr_machine_2_11_instance_options(MachineState *machine)
3670 {
3671 }
3672
3673 static void spapr_machine_2_11_class_options(MachineClass *mc)
3674 {
3675 /* Defaults for the latest behaviour inherited from the base class */
3676 }
3677
3678 DEFINE_SPAPR_MACHINE(2_11, "2.11", true);
3679
3680 /*
3681 * pseries-2.10
3682 */
3683 #define SPAPR_COMPAT_2_10 \
3684 HW_COMPAT_2_10 \
3685
3686 static void spapr_machine_2_10_instance_options(MachineState *machine)
3687 {
3688 }
3689
3690 static void spapr_machine_2_10_class_options(MachineClass *mc)
3691 {
3692 spapr_machine_2_11_class_options(mc);
3693 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_10);
3694 }
3695
3696 DEFINE_SPAPR_MACHINE(2_10, "2.10", false);
3697
3698 /*
3699 * pseries-2.9
3700 */
3701 #define SPAPR_COMPAT_2_9 \
3702 HW_COMPAT_2_9 \
3703 { \
3704 .driver = TYPE_POWERPC_CPU, \
3705 .property = "pre-2.10-migration", \
3706 .value = "on", \
3707 }, \
3708
3709 static void spapr_machine_2_9_instance_options(MachineState *machine)
3710 {
3711 spapr_machine_2_10_instance_options(machine);
3712 }
3713
3714 static void spapr_machine_2_9_class_options(MachineClass *mc)
3715 {
3716 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3717
3718 spapr_machine_2_10_class_options(mc);
3719 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9);
3720 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram;
3721 smc->pre_2_10_has_unused_icps = true;
3722 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED;
3723 }
3724
3725 DEFINE_SPAPR_MACHINE(2_9, "2.9", false);
3726
3727 /*
3728 * pseries-2.8
3729 */
3730 #define SPAPR_COMPAT_2_8 \
3731 HW_COMPAT_2_8 \
3732 { \
3733 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3734 .property = "pcie-extended-configuration-space", \
3735 .value = "off", \
3736 },
3737
3738 static void spapr_machine_2_8_instance_options(MachineState *machine)
3739 {
3740 spapr_machine_2_9_instance_options(machine);
3741 }
3742
3743 static void spapr_machine_2_8_class_options(MachineClass *mc)
3744 {
3745 spapr_machine_2_9_class_options(mc);
3746 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8);
3747 mc->numa_mem_align_shift = 23;
3748 }
3749
3750 DEFINE_SPAPR_MACHINE(2_8, "2.8", false);
3751
3752 /*
3753 * pseries-2.7
3754 */
3755 #define SPAPR_COMPAT_2_7 \
3756 HW_COMPAT_2_7 \
3757 { \
3758 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3759 .property = "mem_win_size", \
3760 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\
3761 }, \
3762 { \
3763 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3764 .property = "mem64_win_size", \
3765 .value = "0", \
3766 }, \
3767 { \
3768 .driver = TYPE_POWERPC_CPU, \
3769 .property = "pre-2.8-migration", \
3770 .value = "on", \
3771 }, \
3772 { \
3773 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3774 .property = "pre-2.8-migration", \
3775 .value = "on", \
3776 },
3777
3778 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index,
3779 uint64_t *buid, hwaddr *pio,
3780 hwaddr *mmio32, hwaddr *mmio64,
3781 unsigned n_dma, uint32_t *liobns, Error **errp)
3782 {
3783 /* Legacy PHB placement for pseries-2.7 and earlier machine types */
3784 const uint64_t base_buid = 0x800000020000000ULL;
3785 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */
3786 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */
3787 const hwaddr pio_offset = 0x80000000; /* 2 GiB */
3788 const uint32_t max_index = 255;
3789 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */
3790
3791 uint64_t ram_top = MACHINE(spapr)->ram_size;
3792 hwaddr phb0_base, phb_base;
3793 int i;
3794
3795 /* Do we have hotpluggable memory? */
3796 if (MACHINE(spapr)->maxram_size > ram_top) {
3797 /* Can't just use maxram_size, because there may be an
3798 * alignment gap between normal and hotpluggable memory
3799 * regions */
3800 ram_top = spapr->hotplug_memory.base +
3801 memory_region_size(&spapr->hotplug_memory.mr);
3802 }
3803
3804 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment);
3805
3806 if (index > max_index) {
3807 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)",
3808 max_index);
3809 return;
3810 }
3811
3812 *buid = base_buid + index;
3813 for (i = 0; i < n_dma; ++i) {
3814 liobns[i] = SPAPR_PCI_LIOBN(index, i);
3815 }
3816
3817 phb_base = phb0_base + index * phb_spacing;
3818 *pio = phb_base + pio_offset;
3819 *mmio32 = phb_base + mmio_offset;
3820 /*
3821 * We don't set the 64-bit MMIO window, relying on the PHB's
3822 * fallback behaviour of automatically splitting a large "32-bit"
3823 * window into contiguous 32-bit and 64-bit windows
3824 */
3825 }
3826
3827 static void spapr_machine_2_7_instance_options(MachineState *machine)
3828 {
3829 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
3830
3831 spapr_machine_2_8_instance_options(machine);
3832 spapr->use_hotplug_event_source = false;
3833 }
3834
3835 static void spapr_machine_2_7_class_options(MachineClass *mc)
3836 {
3837 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3838
3839 spapr_machine_2_8_class_options(mc);
3840 smc->tcg_default_cpu = "POWER7";
3841 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7);
3842 smc->phb_placement = phb_placement_2_7;
3843 }
3844
3845 DEFINE_SPAPR_MACHINE(2_7, "2.7", false);
3846
3847 /*
3848 * pseries-2.6
3849 */
3850 #define SPAPR_COMPAT_2_6 \
3851 HW_COMPAT_2_6 \
3852 { \
3853 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
3854 .property = "ddw",\
3855 .value = stringify(off),\
3856 },
3857
3858 static void spapr_machine_2_6_instance_options(MachineState *machine)
3859 {
3860 spapr_machine_2_7_instance_options(machine);
3861 }
3862
3863 static void spapr_machine_2_6_class_options(MachineClass *mc)
3864 {
3865 spapr_machine_2_7_class_options(mc);
3866 mc->has_hotpluggable_cpus = false;
3867 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6);
3868 }
3869
3870 DEFINE_SPAPR_MACHINE(2_6, "2.6", false);
3871
3872 /*
3873 * pseries-2.5
3874 */
3875 #define SPAPR_COMPAT_2_5 \
3876 HW_COMPAT_2_5 \
3877 { \
3878 .driver = "spapr-vlan", \
3879 .property = "use-rx-buffer-pools", \
3880 .value = "off", \
3881 },
3882
3883 static void spapr_machine_2_5_instance_options(MachineState *machine)
3884 {
3885 spapr_machine_2_6_instance_options(machine);
3886 }
3887
3888 static void spapr_machine_2_5_class_options(MachineClass *mc)
3889 {
3890 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3891
3892 spapr_machine_2_6_class_options(mc);
3893 smc->use_ohci_by_default = true;
3894 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5);
3895 }
3896
3897 DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
3898
3899 /*
3900 * pseries-2.4
3901 */
3902 #define SPAPR_COMPAT_2_4 \
3903 HW_COMPAT_2_4
3904
3905 static void spapr_machine_2_4_instance_options(MachineState *machine)
3906 {
3907 spapr_machine_2_5_instance_options(machine);
3908 }
3909
3910 static void spapr_machine_2_4_class_options(MachineClass *mc)
3911 {
3912 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3913
3914 spapr_machine_2_5_class_options(mc);
3915 smc->dr_lmb_enabled = false;
3916 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4);
3917 }
3918
3919 DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
3920
3921 /*
3922 * pseries-2.3
3923 */
3924 #define SPAPR_COMPAT_2_3 \
3925 HW_COMPAT_2_3 \
3926 {\
3927 .driver = "spapr-pci-host-bridge",\
3928 .property = "dynamic-reconfiguration",\
3929 .value = "off",\
3930 },
3931
3932 static void spapr_machine_2_3_instance_options(MachineState *machine)
3933 {
3934 spapr_machine_2_4_instance_options(machine);
3935 }
3936
3937 static void spapr_machine_2_3_class_options(MachineClass *mc)
3938 {
3939 spapr_machine_2_4_class_options(mc);
3940 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3);
3941 }
3942 DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
3943
3944 /*
3945 * pseries-2.2
3946 */
3947
3948 #define SPAPR_COMPAT_2_2 \
3949 HW_COMPAT_2_2 \
3950 {\
3951 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
3952 .property = "mem_win_size",\
3953 .value = "0x20000000",\
3954 },
3955
3956 static void spapr_machine_2_2_instance_options(MachineState *machine)
3957 {
3958 spapr_machine_2_3_instance_options(machine);
3959 machine->suppress_vmdesc = true;
3960 }
3961
3962 static void spapr_machine_2_2_class_options(MachineClass *mc)
3963 {
3964 spapr_machine_2_3_class_options(mc);
3965 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2);
3966 }
3967 DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
3968
3969 /*
3970 * pseries-2.1
3971 */
3972 #define SPAPR_COMPAT_2_1 \
3973 HW_COMPAT_2_1
3974
3975 static void spapr_machine_2_1_instance_options(MachineState *machine)
3976 {
3977 spapr_machine_2_2_instance_options(machine);
3978 }
3979
3980 static void spapr_machine_2_1_class_options(MachineClass *mc)
3981 {
3982 spapr_machine_2_2_class_options(mc);
3983 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1);
3984 }
3985 DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
3986
3987 static void spapr_machine_register_types(void)
3988 {
3989 type_register_static(&spapr_machine_info);
3990 }
3991
3992 type_init(spapr_machine_register_types)
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