2 * MIPS32 emulation for qemu: main translation routines.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
7 * Copyright (c) 2009 CodeSourcery (MIPS16 support)
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2 of the License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
33 #include "qemu-common.h"
39 //#define MIPS_DEBUG_DISAS
40 //#define MIPS_DEBUG_SIGN_EXTENSIONS
42 /* MIPS major opcodes */
43 #define MASK_OP_MAJOR(op) (op & (0x3F << 26))
46 /* indirect opcode tables */
47 OPC_SPECIAL
= (0x00 << 26),
48 OPC_REGIMM
= (0x01 << 26),
49 OPC_CP0
= (0x10 << 26),
50 OPC_CP1
= (0x11 << 26),
51 OPC_CP2
= (0x12 << 26),
52 OPC_CP3
= (0x13 << 26),
53 OPC_SPECIAL2
= (0x1C << 26),
54 OPC_SPECIAL3
= (0x1F << 26),
55 /* arithmetic with immediate */
56 OPC_ADDI
= (0x08 << 26),
57 OPC_ADDIU
= (0x09 << 26),
58 OPC_SLTI
= (0x0A << 26),
59 OPC_SLTIU
= (0x0B << 26),
60 /* logic with immediate */
61 OPC_ANDI
= (0x0C << 26),
62 OPC_ORI
= (0x0D << 26),
63 OPC_XORI
= (0x0E << 26),
64 OPC_LUI
= (0x0F << 26),
65 /* arithmetic with immediate */
66 OPC_DADDI
= (0x18 << 26),
67 OPC_DADDIU
= (0x19 << 26),
68 /* Jump and branches */
70 OPC_JAL
= (0x03 << 26),
71 OPC_BEQ
= (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */
72 OPC_BEQL
= (0x14 << 26),
73 OPC_BNE
= (0x05 << 26),
74 OPC_BNEL
= (0x15 << 26),
75 OPC_BLEZ
= (0x06 << 26),
76 OPC_BLEZL
= (0x16 << 26),
77 OPC_BGTZ
= (0x07 << 26),
78 OPC_BGTZL
= (0x17 << 26),
79 OPC_JALX
= (0x1D << 26), /* MIPS 16 only */
81 OPC_LDL
= (0x1A << 26),
82 OPC_LDR
= (0x1B << 26),
83 OPC_LB
= (0x20 << 26),
84 OPC_LH
= (0x21 << 26),
85 OPC_LWL
= (0x22 << 26),
86 OPC_LW
= (0x23 << 26),
87 OPC_LWPC
= OPC_LW
| 0x5,
88 OPC_LBU
= (0x24 << 26),
89 OPC_LHU
= (0x25 << 26),
90 OPC_LWR
= (0x26 << 26),
91 OPC_LWU
= (0x27 << 26),
92 OPC_SB
= (0x28 << 26),
93 OPC_SH
= (0x29 << 26),
94 OPC_SWL
= (0x2A << 26),
95 OPC_SW
= (0x2B << 26),
96 OPC_SDL
= (0x2C << 26),
97 OPC_SDR
= (0x2D << 26),
98 OPC_SWR
= (0x2E << 26),
99 OPC_LL
= (0x30 << 26),
100 OPC_LLD
= (0x34 << 26),
101 OPC_LD
= (0x37 << 26),
102 OPC_LDPC
= OPC_LD
| 0x5,
103 OPC_SC
= (0x38 << 26),
104 OPC_SCD
= (0x3C << 26),
105 OPC_SD
= (0x3F << 26),
106 /* Floating point load/store */
107 OPC_LWC1
= (0x31 << 26),
108 OPC_LWC2
= (0x32 << 26),
109 OPC_LDC1
= (0x35 << 26),
110 OPC_LDC2
= (0x36 << 26),
111 OPC_SWC1
= (0x39 << 26),
112 OPC_SWC2
= (0x3A << 26),
113 OPC_SDC1
= (0x3D << 26),
114 OPC_SDC2
= (0x3E << 26),
115 /* MDMX ASE specific */
116 OPC_MDMX
= (0x1E << 26),
117 /* Cache and prefetch */
118 OPC_CACHE
= (0x2F << 26),
119 OPC_PREF
= (0x33 << 26),
120 /* Reserved major opcode */
121 OPC_MAJOR3B_RESERVED
= (0x3B << 26),
124 /* MIPS special opcodes */
125 #define MASK_SPECIAL(op) MASK_OP_MAJOR(op) | (op & 0x3F)
129 OPC_SLL
= 0x00 | OPC_SPECIAL
,
130 /* NOP is SLL r0, r0, 0 */
131 /* SSNOP is SLL r0, r0, 1 */
132 /* EHB is SLL r0, r0, 3 */
133 OPC_SRL
= 0x02 | OPC_SPECIAL
, /* also ROTR */
134 OPC_ROTR
= OPC_SRL
| (1 << 21),
135 OPC_SRA
= 0x03 | OPC_SPECIAL
,
136 OPC_SLLV
= 0x04 | OPC_SPECIAL
,
137 OPC_SRLV
= 0x06 | OPC_SPECIAL
, /* also ROTRV */
138 OPC_ROTRV
= OPC_SRLV
| (1 << 6),
139 OPC_SRAV
= 0x07 | OPC_SPECIAL
,
140 OPC_DSLLV
= 0x14 | OPC_SPECIAL
,
141 OPC_DSRLV
= 0x16 | OPC_SPECIAL
, /* also DROTRV */
142 OPC_DROTRV
= OPC_DSRLV
| (1 << 6),
143 OPC_DSRAV
= 0x17 | OPC_SPECIAL
,
144 OPC_DSLL
= 0x38 | OPC_SPECIAL
,
145 OPC_DSRL
= 0x3A | OPC_SPECIAL
, /* also DROTR */
146 OPC_DROTR
= OPC_DSRL
| (1 << 21),
147 OPC_DSRA
= 0x3B | OPC_SPECIAL
,
148 OPC_DSLL32
= 0x3C | OPC_SPECIAL
,
149 OPC_DSRL32
= 0x3E | OPC_SPECIAL
, /* also DROTR32 */
150 OPC_DROTR32
= OPC_DSRL32
| (1 << 21),
151 OPC_DSRA32
= 0x3F | OPC_SPECIAL
,
152 /* Multiplication / division */
153 OPC_MULT
= 0x18 | OPC_SPECIAL
,
154 OPC_MULTU
= 0x19 | OPC_SPECIAL
,
155 OPC_DIV
= 0x1A | OPC_SPECIAL
,
156 OPC_DIVU
= 0x1B | OPC_SPECIAL
,
157 OPC_DMULT
= 0x1C | OPC_SPECIAL
,
158 OPC_DMULTU
= 0x1D | OPC_SPECIAL
,
159 OPC_DDIV
= 0x1E | OPC_SPECIAL
,
160 OPC_DDIVU
= 0x1F | OPC_SPECIAL
,
161 /* 2 registers arithmetic / logic */
162 OPC_ADD
= 0x20 | OPC_SPECIAL
,
163 OPC_ADDU
= 0x21 | OPC_SPECIAL
,
164 OPC_SUB
= 0x22 | OPC_SPECIAL
,
165 OPC_SUBU
= 0x23 | OPC_SPECIAL
,
166 OPC_AND
= 0x24 | OPC_SPECIAL
,
167 OPC_OR
= 0x25 | OPC_SPECIAL
,
168 OPC_XOR
= 0x26 | OPC_SPECIAL
,
169 OPC_NOR
= 0x27 | OPC_SPECIAL
,
170 OPC_SLT
= 0x2A | OPC_SPECIAL
,
171 OPC_SLTU
= 0x2B | OPC_SPECIAL
,
172 OPC_DADD
= 0x2C | OPC_SPECIAL
,
173 OPC_DADDU
= 0x2D | OPC_SPECIAL
,
174 OPC_DSUB
= 0x2E | OPC_SPECIAL
,
175 OPC_DSUBU
= 0x2F | OPC_SPECIAL
,
177 OPC_JR
= 0x08 | OPC_SPECIAL
, /* Also JR.HB */
178 OPC_JALR
= 0x09 | OPC_SPECIAL
, /* Also JALR.HB */
179 OPC_JALRC
= OPC_JALR
| (0x5 << 6),
181 OPC_TGE
= 0x30 | OPC_SPECIAL
,
182 OPC_TGEU
= 0x31 | OPC_SPECIAL
,
183 OPC_TLT
= 0x32 | OPC_SPECIAL
,
184 OPC_TLTU
= 0x33 | OPC_SPECIAL
,
185 OPC_TEQ
= 0x34 | OPC_SPECIAL
,
186 OPC_TNE
= 0x36 | OPC_SPECIAL
,
187 /* HI / LO registers load & stores */
188 OPC_MFHI
= 0x10 | OPC_SPECIAL
,
189 OPC_MTHI
= 0x11 | OPC_SPECIAL
,
190 OPC_MFLO
= 0x12 | OPC_SPECIAL
,
191 OPC_MTLO
= 0x13 | OPC_SPECIAL
,
192 /* Conditional moves */
193 OPC_MOVZ
= 0x0A | OPC_SPECIAL
,
194 OPC_MOVN
= 0x0B | OPC_SPECIAL
,
196 OPC_MOVCI
= 0x01 | OPC_SPECIAL
,
199 OPC_PMON
= 0x05 | OPC_SPECIAL
, /* unofficial */
200 OPC_SYSCALL
= 0x0C | OPC_SPECIAL
,
201 OPC_BREAK
= 0x0D | OPC_SPECIAL
,
202 OPC_SPIM
= 0x0E | OPC_SPECIAL
, /* unofficial */
203 OPC_SYNC
= 0x0F | OPC_SPECIAL
,
205 OPC_SPECIAL15_RESERVED
= 0x15 | OPC_SPECIAL
,
206 OPC_SPECIAL28_RESERVED
= 0x28 | OPC_SPECIAL
,
207 OPC_SPECIAL29_RESERVED
= 0x29 | OPC_SPECIAL
,
208 OPC_SPECIAL35_RESERVED
= 0x35 | OPC_SPECIAL
,
209 OPC_SPECIAL37_RESERVED
= 0x37 | OPC_SPECIAL
,
210 OPC_SPECIAL39_RESERVED
= 0x39 | OPC_SPECIAL
,
211 OPC_SPECIAL3D_RESERVED
= 0x3D | OPC_SPECIAL
,
214 /* Multiplication variants of the vr54xx. */
215 #define MASK_MUL_VR54XX(op) MASK_SPECIAL(op) | (op & (0x1F << 6))
218 OPC_VR54XX_MULS
= (0x03 << 6) | OPC_MULT
,
219 OPC_VR54XX_MULSU
= (0x03 << 6) | OPC_MULTU
,
220 OPC_VR54XX_MACC
= (0x05 << 6) | OPC_MULT
,
221 OPC_VR54XX_MACCU
= (0x05 << 6) | OPC_MULTU
,
222 OPC_VR54XX_MSAC
= (0x07 << 6) | OPC_MULT
,
223 OPC_VR54XX_MSACU
= (0x07 << 6) | OPC_MULTU
,
224 OPC_VR54XX_MULHI
= (0x09 << 6) | OPC_MULT
,
225 OPC_VR54XX_MULHIU
= (0x09 << 6) | OPC_MULTU
,
226 OPC_VR54XX_MULSHI
= (0x0B << 6) | OPC_MULT
,
227 OPC_VR54XX_MULSHIU
= (0x0B << 6) | OPC_MULTU
,
228 OPC_VR54XX_MACCHI
= (0x0D << 6) | OPC_MULT
,
229 OPC_VR54XX_MACCHIU
= (0x0D << 6) | OPC_MULTU
,
230 OPC_VR54XX_MSACHI
= (0x0F << 6) | OPC_MULT
,
231 OPC_VR54XX_MSACHIU
= (0x0F << 6) | OPC_MULTU
,
234 /* REGIMM (rt field) opcodes */
235 #define MASK_REGIMM(op) MASK_OP_MAJOR(op) | (op & (0x1F << 16))
238 OPC_BLTZ
= (0x00 << 16) | OPC_REGIMM
,
239 OPC_BLTZL
= (0x02 << 16) | OPC_REGIMM
,
240 OPC_BGEZ
= (0x01 << 16) | OPC_REGIMM
,
241 OPC_BGEZL
= (0x03 << 16) | OPC_REGIMM
,
242 OPC_BLTZAL
= (0x10 << 16) | OPC_REGIMM
,
243 OPC_BLTZALL
= (0x12 << 16) | OPC_REGIMM
,
244 OPC_BGEZAL
= (0x11 << 16) | OPC_REGIMM
,
245 OPC_BGEZALL
= (0x13 << 16) | OPC_REGIMM
,
246 OPC_TGEI
= (0x08 << 16) | OPC_REGIMM
,
247 OPC_TGEIU
= (0x09 << 16) | OPC_REGIMM
,
248 OPC_TLTI
= (0x0A << 16) | OPC_REGIMM
,
249 OPC_TLTIU
= (0x0B << 16) | OPC_REGIMM
,
250 OPC_TEQI
= (0x0C << 16) | OPC_REGIMM
,
251 OPC_TNEI
= (0x0E << 16) | OPC_REGIMM
,
252 OPC_SYNCI
= (0x1F << 16) | OPC_REGIMM
,
255 /* Special2 opcodes */
256 #define MASK_SPECIAL2(op) MASK_OP_MAJOR(op) | (op & 0x3F)
259 /* Multiply & xxx operations */
260 OPC_MADD
= 0x00 | OPC_SPECIAL2
,
261 OPC_MADDU
= 0x01 | OPC_SPECIAL2
,
262 OPC_MUL
= 0x02 | OPC_SPECIAL2
,
263 OPC_MSUB
= 0x04 | OPC_SPECIAL2
,
264 OPC_MSUBU
= 0x05 | OPC_SPECIAL2
,
266 OPC_CLZ
= 0x20 | OPC_SPECIAL2
,
267 OPC_CLO
= 0x21 | OPC_SPECIAL2
,
268 OPC_DCLZ
= 0x24 | OPC_SPECIAL2
,
269 OPC_DCLO
= 0x25 | OPC_SPECIAL2
,
271 OPC_SDBBP
= 0x3F | OPC_SPECIAL2
,
274 /* Special3 opcodes */
275 #define MASK_SPECIAL3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
278 OPC_EXT
= 0x00 | OPC_SPECIAL3
,
279 OPC_DEXTM
= 0x01 | OPC_SPECIAL3
,
280 OPC_DEXTU
= 0x02 | OPC_SPECIAL3
,
281 OPC_DEXT
= 0x03 | OPC_SPECIAL3
,
282 OPC_INS
= 0x04 | OPC_SPECIAL3
,
283 OPC_DINSM
= 0x05 | OPC_SPECIAL3
,
284 OPC_DINSU
= 0x06 | OPC_SPECIAL3
,
285 OPC_DINS
= 0x07 | OPC_SPECIAL3
,
286 OPC_FORK
= 0x08 | OPC_SPECIAL3
,
287 OPC_YIELD
= 0x09 | OPC_SPECIAL3
,
288 OPC_BSHFL
= 0x20 | OPC_SPECIAL3
,
289 OPC_DBSHFL
= 0x24 | OPC_SPECIAL3
,
290 OPC_RDHWR
= 0x3B | OPC_SPECIAL3
,
294 #define MASK_BSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
297 OPC_WSBH
= (0x02 << 6) | OPC_BSHFL
,
298 OPC_SEB
= (0x10 << 6) | OPC_BSHFL
,
299 OPC_SEH
= (0x18 << 6) | OPC_BSHFL
,
303 #define MASK_DBSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
306 OPC_DSBH
= (0x02 << 6) | OPC_DBSHFL
,
307 OPC_DSHD
= (0x05 << 6) | OPC_DBSHFL
,
310 /* Coprocessor 0 (rs field) */
311 #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
314 OPC_MFC0
= (0x00 << 21) | OPC_CP0
,
315 OPC_DMFC0
= (0x01 << 21) | OPC_CP0
,
316 OPC_MTC0
= (0x04 << 21) | OPC_CP0
,
317 OPC_DMTC0
= (0x05 << 21) | OPC_CP0
,
318 OPC_MFTR
= (0x08 << 21) | OPC_CP0
,
319 OPC_RDPGPR
= (0x0A << 21) | OPC_CP0
,
320 OPC_MFMC0
= (0x0B << 21) | OPC_CP0
,
321 OPC_MTTR
= (0x0C << 21) | OPC_CP0
,
322 OPC_WRPGPR
= (0x0E << 21) | OPC_CP0
,
323 OPC_C0
= (0x10 << 21) | OPC_CP0
,
324 OPC_C0_FIRST
= (0x10 << 21) | OPC_CP0
,
325 OPC_C0_LAST
= (0x1F << 21) | OPC_CP0
,
329 #define MASK_MFMC0(op) MASK_CP0(op) | (op & 0xFFFF)
332 OPC_DMT
= 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0
,
333 OPC_EMT
= 0x01 | (1 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0
,
334 OPC_DVPE
= 0x01 | (0 << 5) | OPC_MFMC0
,
335 OPC_EVPE
= 0x01 | (1 << 5) | OPC_MFMC0
,
336 OPC_DI
= (0 << 5) | (0x0C << 11) | OPC_MFMC0
,
337 OPC_EI
= (1 << 5) | (0x0C << 11) | OPC_MFMC0
,
340 /* Coprocessor 0 (with rs == C0) */
341 #define MASK_C0(op) MASK_CP0(op) | (op & 0x3F)
344 OPC_TLBR
= 0x01 | OPC_C0
,
345 OPC_TLBWI
= 0x02 | OPC_C0
,
346 OPC_TLBWR
= 0x06 | OPC_C0
,
347 OPC_TLBP
= 0x08 | OPC_C0
,
348 OPC_RFE
= 0x10 | OPC_C0
,
349 OPC_ERET
= 0x18 | OPC_C0
,
350 OPC_DERET
= 0x1F | OPC_C0
,
351 OPC_WAIT
= 0x20 | OPC_C0
,
354 /* Coprocessor 1 (rs field) */
355 #define MASK_CP1(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
358 OPC_MFC1
= (0x00 << 21) | OPC_CP1
,
359 OPC_DMFC1
= (0x01 << 21) | OPC_CP1
,
360 OPC_CFC1
= (0x02 << 21) | OPC_CP1
,
361 OPC_MFHC1
= (0x03 << 21) | OPC_CP1
,
362 OPC_MTC1
= (0x04 << 21) | OPC_CP1
,
363 OPC_DMTC1
= (0x05 << 21) | OPC_CP1
,
364 OPC_CTC1
= (0x06 << 21) | OPC_CP1
,
365 OPC_MTHC1
= (0x07 << 21) | OPC_CP1
,
366 OPC_BC1
= (0x08 << 21) | OPC_CP1
, /* bc */
367 OPC_BC1ANY2
= (0x09 << 21) | OPC_CP1
,
368 OPC_BC1ANY4
= (0x0A << 21) | OPC_CP1
,
369 OPC_S_FMT
= (0x10 << 21) | OPC_CP1
, /* 16: fmt=single fp */
370 OPC_D_FMT
= (0x11 << 21) | OPC_CP1
, /* 17: fmt=double fp */
371 OPC_E_FMT
= (0x12 << 21) | OPC_CP1
, /* 18: fmt=extended fp */
372 OPC_Q_FMT
= (0x13 << 21) | OPC_CP1
, /* 19: fmt=quad fp */
373 OPC_W_FMT
= (0x14 << 21) | OPC_CP1
, /* 20: fmt=32bit fixed */
374 OPC_L_FMT
= (0x15 << 21) | OPC_CP1
, /* 21: fmt=64bit fixed */
375 OPC_PS_FMT
= (0x16 << 21) | OPC_CP1
, /* 22: fmt=paired single fp */
378 #define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F)
379 #define MASK_BC1(op) MASK_CP1(op) | (op & (0x3 << 16))
382 OPC_BC1F
= (0x00 << 16) | OPC_BC1
,
383 OPC_BC1T
= (0x01 << 16) | OPC_BC1
,
384 OPC_BC1FL
= (0x02 << 16) | OPC_BC1
,
385 OPC_BC1TL
= (0x03 << 16) | OPC_BC1
,
389 OPC_BC1FANY2
= (0x00 << 16) | OPC_BC1ANY2
,
390 OPC_BC1TANY2
= (0x01 << 16) | OPC_BC1ANY2
,
394 OPC_BC1FANY4
= (0x00 << 16) | OPC_BC1ANY4
,
395 OPC_BC1TANY4
= (0x01 << 16) | OPC_BC1ANY4
,
398 #define MASK_CP2(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
401 OPC_MFC2
= (0x00 << 21) | OPC_CP2
,
402 OPC_DMFC2
= (0x01 << 21) | OPC_CP2
,
403 OPC_CFC2
= (0x02 << 21) | OPC_CP2
,
404 OPC_MFHC2
= (0x03 << 21) | OPC_CP2
,
405 OPC_MTC2
= (0x04 << 21) | OPC_CP2
,
406 OPC_DMTC2
= (0x05 << 21) | OPC_CP2
,
407 OPC_CTC2
= (0x06 << 21) | OPC_CP2
,
408 OPC_MTHC2
= (0x07 << 21) | OPC_CP2
,
409 OPC_BC2
= (0x08 << 21) | OPC_CP2
,
412 #define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
415 OPC_LWXC1
= 0x00 | OPC_CP3
,
416 OPC_LDXC1
= 0x01 | OPC_CP3
,
417 OPC_LUXC1
= 0x05 | OPC_CP3
,
418 OPC_SWXC1
= 0x08 | OPC_CP3
,
419 OPC_SDXC1
= 0x09 | OPC_CP3
,
420 OPC_SUXC1
= 0x0D | OPC_CP3
,
421 OPC_PREFX
= 0x0F | OPC_CP3
,
422 OPC_ALNV_PS
= 0x1E | OPC_CP3
,
423 OPC_MADD_S
= 0x20 | OPC_CP3
,
424 OPC_MADD_D
= 0x21 | OPC_CP3
,
425 OPC_MADD_PS
= 0x26 | OPC_CP3
,
426 OPC_MSUB_S
= 0x28 | OPC_CP3
,
427 OPC_MSUB_D
= 0x29 | OPC_CP3
,
428 OPC_MSUB_PS
= 0x2E | OPC_CP3
,
429 OPC_NMADD_S
= 0x30 | OPC_CP3
,
430 OPC_NMADD_D
= 0x31 | OPC_CP3
,
431 OPC_NMADD_PS
= 0x36 | OPC_CP3
,
432 OPC_NMSUB_S
= 0x38 | OPC_CP3
,
433 OPC_NMSUB_D
= 0x39 | OPC_CP3
,
434 OPC_NMSUB_PS
= 0x3E | OPC_CP3
,
437 /* global register indices */
438 static TCGv_ptr cpu_env
;
439 static TCGv cpu_gpr
[32], cpu_PC
;
440 static TCGv cpu_HI
[MIPS_DSP_ACC
], cpu_LO
[MIPS_DSP_ACC
], cpu_ACX
[MIPS_DSP_ACC
];
441 static TCGv cpu_dspctrl
, btarget
, bcond
;
442 static TCGv_i32 hflags
;
443 static TCGv_i32 fpu_fcr0
, fpu_fcr31
;
445 #include "gen-icount.h"
447 #define gen_helper_0i(name, arg) do { \
448 TCGv_i32 helper_tmp = tcg_const_i32(arg); \
449 gen_helper_##name(helper_tmp); \
450 tcg_temp_free_i32(helper_tmp); \
453 #define gen_helper_1i(name, arg1, arg2) do { \
454 TCGv_i32 helper_tmp = tcg_const_i32(arg2); \
455 gen_helper_##name(arg1, helper_tmp); \
456 tcg_temp_free_i32(helper_tmp); \
459 #define gen_helper_2i(name, arg1, arg2, arg3) do { \
460 TCGv_i32 helper_tmp = tcg_const_i32(arg3); \
461 gen_helper_##name(arg1, arg2, helper_tmp); \
462 tcg_temp_free_i32(helper_tmp); \
465 #define gen_helper_3i(name, arg1, arg2, arg3, arg4) do { \
466 TCGv_i32 helper_tmp = tcg_const_i32(arg4); \
467 gen_helper_##name(arg1, arg2, arg3, helper_tmp); \
468 tcg_temp_free_i32(helper_tmp); \
471 typedef struct DisasContext
{
472 struct TranslationBlock
*tb
;
473 target_ulong pc
, saved_pc
;
475 int singlestep_enabled
;
476 /* Routine used to access memory */
478 uint32_t hflags
, saved_hflags
;
480 target_ulong btarget
;
484 BS_NONE
= 0, /* We go out of the TB without reaching a branch or an
485 * exception condition */
486 BS_STOP
= 1, /* We want to stop translation for any reason */
487 BS_BRANCH
= 2, /* We reached a branch condition */
488 BS_EXCP
= 3, /* We reached an exception condition */
491 static const char *regnames
[] =
492 { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
493 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
494 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
495 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", };
497 static const char *regnames_HI
[] =
498 { "HI0", "HI1", "HI2", "HI3", };
500 static const char *regnames_LO
[] =
501 { "LO0", "LO1", "LO2", "LO3", };
503 static const char *regnames_ACX
[] =
504 { "ACX0", "ACX1", "ACX2", "ACX3", };
506 static const char *fregnames
[] =
507 { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
508 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
509 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
510 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", };
512 #ifdef MIPS_DEBUG_DISAS
513 #define MIPS_DEBUG(fmt, ...) \
514 qemu_log_mask(CPU_LOG_TB_IN_ASM, \
515 TARGET_FMT_lx ": %08x " fmt "\n", \
516 ctx->pc, ctx->opcode , ## __VA_ARGS__)
517 #define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
519 #define MIPS_DEBUG(fmt, ...) do { } while(0)
520 #define LOG_DISAS(...) do { } while (0)
523 #define MIPS_INVAL(op) \
525 MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \
526 ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
529 /* General purpose registers moves. */
530 static inline void gen_load_gpr (TCGv t
, int reg
)
533 tcg_gen_movi_tl(t
, 0);
535 tcg_gen_mov_tl(t
, cpu_gpr
[reg
]);
538 static inline void gen_store_gpr (TCGv t
, int reg
)
541 tcg_gen_mov_tl(cpu_gpr
[reg
], t
);
544 /* Moves to/from ACX register. */
545 static inline void gen_load_ACX (TCGv t
, int reg
)
547 tcg_gen_mov_tl(t
, cpu_ACX
[reg
]);
550 static inline void gen_store_ACX (TCGv t
, int reg
)
552 tcg_gen_mov_tl(cpu_ACX
[reg
], t
);
555 /* Moves to/from shadow registers. */
556 static inline void gen_load_srsgpr (int from
, int to
)
558 TCGv t0
= tcg_temp_new();
561 tcg_gen_movi_tl(t0
, 0);
563 TCGv_i32 t2
= tcg_temp_new_i32();
564 TCGv_ptr addr
= tcg_temp_new_ptr();
566 tcg_gen_ld_i32(t2
, cpu_env
, offsetof(CPUState
, CP0_SRSCtl
));
567 tcg_gen_shri_i32(t2
, t2
, CP0SRSCtl_PSS
);
568 tcg_gen_andi_i32(t2
, t2
, 0xf);
569 tcg_gen_muli_i32(t2
, t2
, sizeof(target_ulong
) * 32);
570 tcg_gen_ext_i32_ptr(addr
, t2
);
571 tcg_gen_add_ptr(addr
, cpu_env
, addr
);
573 tcg_gen_ld_tl(t0
, addr
, sizeof(target_ulong
) * from
);
574 tcg_temp_free_ptr(addr
);
575 tcg_temp_free_i32(t2
);
577 gen_store_gpr(t0
, to
);
581 static inline void gen_store_srsgpr (int from
, int to
)
584 TCGv t0
= tcg_temp_new();
585 TCGv_i32 t2
= tcg_temp_new_i32();
586 TCGv_ptr addr
= tcg_temp_new_ptr();
588 gen_load_gpr(t0
, from
);
589 tcg_gen_ld_i32(t2
, cpu_env
, offsetof(CPUState
, CP0_SRSCtl
));
590 tcg_gen_shri_i32(t2
, t2
, CP0SRSCtl_PSS
);
591 tcg_gen_andi_i32(t2
, t2
, 0xf);
592 tcg_gen_muli_i32(t2
, t2
, sizeof(target_ulong
) * 32);
593 tcg_gen_ext_i32_ptr(addr
, t2
);
594 tcg_gen_add_ptr(addr
, cpu_env
, addr
);
596 tcg_gen_st_tl(t0
, addr
, sizeof(target_ulong
) * to
);
597 tcg_temp_free_ptr(addr
);
598 tcg_temp_free_i32(t2
);
603 /* Floating point register moves. */
604 static inline void gen_load_fpr32 (TCGv_i32 t
, int reg
)
606 tcg_gen_ld_i32(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].w
[FP_ENDIAN_IDX
]));
609 static inline void gen_store_fpr32 (TCGv_i32 t
, int reg
)
611 tcg_gen_st_i32(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].w
[FP_ENDIAN_IDX
]));
614 static inline void gen_load_fpr32h (TCGv_i32 t
, int reg
)
616 tcg_gen_ld_i32(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].w
[!FP_ENDIAN_IDX
]));
619 static inline void gen_store_fpr32h (TCGv_i32 t
, int reg
)
621 tcg_gen_st_i32(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].w
[!FP_ENDIAN_IDX
]));
624 static inline void gen_load_fpr64 (DisasContext
*ctx
, TCGv_i64 t
, int reg
)
626 if (ctx
->hflags
& MIPS_HFLAG_F64
) {
627 tcg_gen_ld_i64(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].d
));
629 TCGv_i32 t0
= tcg_temp_new_i32();
630 TCGv_i32 t1
= tcg_temp_new_i32();
631 gen_load_fpr32(t0
, reg
& ~1);
632 gen_load_fpr32(t1
, reg
| 1);
633 tcg_gen_concat_i32_i64(t
, t0
, t1
);
634 tcg_temp_free_i32(t0
);
635 tcg_temp_free_i32(t1
);
639 static inline void gen_store_fpr64 (DisasContext
*ctx
, TCGv_i64 t
, int reg
)
641 if (ctx
->hflags
& MIPS_HFLAG_F64
) {
642 tcg_gen_st_i64(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].d
));
644 TCGv_i64 t0
= tcg_temp_new_i64();
645 TCGv_i32 t1
= tcg_temp_new_i32();
646 tcg_gen_trunc_i64_i32(t1
, t
);
647 gen_store_fpr32(t1
, reg
& ~1);
648 tcg_gen_shri_i64(t0
, t
, 32);
649 tcg_gen_trunc_i64_i32(t1
, t0
);
650 gen_store_fpr32(t1
, reg
| 1);
651 tcg_temp_free_i32(t1
);
652 tcg_temp_free_i64(t0
);
656 static inline int get_fp_bit (int cc
)
664 #define FOP_CONDS(type, fmt, bits) \
665 static inline void gen_cmp ## type ## _ ## fmt(int n, TCGv_i##bits a, \
666 TCGv_i##bits b, int cc) \
669 case 0: gen_helper_2i(cmp ## type ## _ ## fmt ## _f, a, b, cc); break;\
670 case 1: gen_helper_2i(cmp ## type ## _ ## fmt ## _un, a, b, cc); break;\
671 case 2: gen_helper_2i(cmp ## type ## _ ## fmt ## _eq, a, b, cc); break;\
672 case 3: gen_helper_2i(cmp ## type ## _ ## fmt ## _ueq, a, b, cc); break;\
673 case 4: gen_helper_2i(cmp ## type ## _ ## fmt ## _olt, a, b, cc); break;\
674 case 5: gen_helper_2i(cmp ## type ## _ ## fmt ## _ult, a, b, cc); break;\
675 case 6: gen_helper_2i(cmp ## type ## _ ## fmt ## _ole, a, b, cc); break;\
676 case 7: gen_helper_2i(cmp ## type ## _ ## fmt ## _ule, a, b, cc); break;\
677 case 8: gen_helper_2i(cmp ## type ## _ ## fmt ## _sf, a, b, cc); break;\
678 case 9: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngle, a, b, cc); break;\
679 case 10: gen_helper_2i(cmp ## type ## _ ## fmt ## _seq, a, b, cc); break;\
680 case 11: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngl, a, b, cc); break;\
681 case 12: gen_helper_2i(cmp ## type ## _ ## fmt ## _lt, a, b, cc); break;\
682 case 13: gen_helper_2i(cmp ## type ## _ ## fmt ## _nge, a, b, cc); break;\
683 case 14: gen_helper_2i(cmp ## type ## _ ## fmt ## _le, a, b, cc); break;\
684 case 15: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngt, a, b, cc); break;\
690 FOP_CONDS(abs
, d
, 64)
692 FOP_CONDS(abs
, s
, 32)
694 FOP_CONDS(abs
, ps
, 64)
698 static inline void gen_save_pc(target_ulong pc
)
700 tcg_gen_movi_tl(cpu_PC
, pc
);
703 static inline void save_cpu_state (DisasContext
*ctx
, int do_save_pc
)
705 LOG_DISAS("hflags %08x saved %08x\n", ctx
->hflags
, ctx
->saved_hflags
);
706 if (do_save_pc
&& ctx
->pc
!= ctx
->saved_pc
) {
707 gen_save_pc(ctx
->pc
);
708 ctx
->saved_pc
= ctx
->pc
;
710 if (ctx
->hflags
!= ctx
->saved_hflags
) {
711 tcg_gen_movi_i32(hflags
, ctx
->hflags
);
712 ctx
->saved_hflags
= ctx
->hflags
;
713 switch (ctx
->hflags
& MIPS_HFLAG_BMASK_BASE
) {
719 tcg_gen_movi_tl(btarget
, ctx
->btarget
);
725 static inline void restore_cpu_state (CPUState
*env
, DisasContext
*ctx
)
727 ctx
->saved_hflags
= ctx
->hflags
;
728 switch (ctx
->hflags
& MIPS_HFLAG_BMASK_BASE
) {
734 ctx
->btarget
= env
->btarget
;
740 generate_exception_err (DisasContext
*ctx
, int excp
, int err
)
742 TCGv_i32 texcp
= tcg_const_i32(excp
);
743 TCGv_i32 terr
= tcg_const_i32(err
);
744 save_cpu_state(ctx
, 1);
745 gen_helper_raise_exception_err(texcp
, terr
);
746 tcg_temp_free_i32(terr
);
747 tcg_temp_free_i32(texcp
);
751 generate_exception (DisasContext
*ctx
, int excp
)
753 save_cpu_state(ctx
, 1);
754 gen_helper_0i(raise_exception
, excp
);
757 /* Addresses computation */
758 static inline void gen_op_addr_add (DisasContext
*ctx
, TCGv ret
, TCGv arg0
, TCGv arg1
)
760 tcg_gen_add_tl(ret
, arg0
, arg1
);
762 #if defined(TARGET_MIPS64)
763 /* For compatibility with 32-bit code, data reference in user mode
764 with Status_UX = 0 should be casted to 32-bit and sign extended.
765 See the MIPS64 PRA manual, section 4.10. */
766 if (((ctx
->hflags
& MIPS_HFLAG_KSU
) == MIPS_HFLAG_UM
) &&
767 !(ctx
->hflags
& MIPS_HFLAG_UX
)) {
768 tcg_gen_ext32s_i64(ret
, ret
);
773 static inline void check_cp0_enabled(DisasContext
*ctx
)
775 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_CP0
)))
776 generate_exception_err(ctx
, EXCP_CpU
, 0);
779 static inline void check_cp1_enabled(DisasContext
*ctx
)
781 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_FPU
)))
782 generate_exception_err(ctx
, EXCP_CpU
, 1);
785 /* Verify that the processor is running with COP1X instructions enabled.
786 This is associated with the nabla symbol in the MIPS32 and MIPS64
789 static inline void check_cop1x(DisasContext
*ctx
)
791 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_COP1X
)))
792 generate_exception(ctx
, EXCP_RI
);
795 /* Verify that the processor is running with 64-bit floating-point
796 operations enabled. */
798 static inline void check_cp1_64bitmode(DisasContext
*ctx
)
800 if (unlikely(~ctx
->hflags
& (MIPS_HFLAG_F64
| MIPS_HFLAG_COP1X
)))
801 generate_exception(ctx
, EXCP_RI
);
805 * Verify if floating point register is valid; an operation is not defined
806 * if bit 0 of any register specification is set and the FR bit in the
807 * Status register equals zero, since the register numbers specify an
808 * even-odd pair of adjacent coprocessor general registers. When the FR bit
809 * in the Status register equals one, both even and odd register numbers
810 * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers.
812 * Multiple 64 bit wide registers can be checked by calling
813 * gen_op_cp1_registers(freg1 | freg2 | ... | fregN);
815 static inline void check_cp1_registers(DisasContext
*ctx
, int regs
)
817 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_F64
) && (regs
& 1)))
818 generate_exception(ctx
, EXCP_RI
);
821 /* This code generates a "reserved instruction" exception if the
822 CPU does not support the instruction set corresponding to flags. */
823 static inline void check_insn(CPUState
*env
, DisasContext
*ctx
, int flags
)
825 if (unlikely(!(env
->insn_flags
& flags
)))
826 generate_exception(ctx
, EXCP_RI
);
829 /* This code generates a "reserved instruction" exception if 64-bit
830 instructions are not enabled. */
831 static inline void check_mips_64(DisasContext
*ctx
)
833 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_64
)))
834 generate_exception(ctx
, EXCP_RI
);
837 /* load/store instructions. */
838 #define OP_LD(insn,fname) \
839 static inline void op_ldst_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
841 tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
848 #if defined(TARGET_MIPS64)
854 #define OP_ST(insn,fname) \
855 static inline void op_ldst_##insn(TCGv arg1, TCGv arg2, DisasContext *ctx) \
857 tcg_gen_qemu_##fname(arg1, arg2, ctx->mem_idx); \
862 #if defined(TARGET_MIPS64)
867 #ifdef CONFIG_USER_ONLY
868 #define OP_LD_ATOMIC(insn,fname) \
869 static inline void op_ldst_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
871 TCGv t0 = tcg_temp_new(); \
872 tcg_gen_mov_tl(t0, arg1); \
873 tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
874 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \
875 tcg_gen_st_tl(ret, cpu_env, offsetof(CPUState, llval)); \
879 #define OP_LD_ATOMIC(insn,fname) \
880 static inline void op_ldst_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
882 gen_helper_2i(insn, ret, arg1, ctx->mem_idx); \
885 OP_LD_ATOMIC(ll
,ld32s
);
886 #if defined(TARGET_MIPS64)
887 OP_LD_ATOMIC(lld
,ld64
);
891 #ifdef CONFIG_USER_ONLY
892 #define OP_ST_ATOMIC(insn,fname,ldname,almask) \
893 static inline void op_ldst_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) \
895 TCGv t0 = tcg_temp_new(); \
896 int l1 = gen_new_label(); \
897 int l2 = gen_new_label(); \
899 tcg_gen_andi_tl(t0, arg2, almask); \
900 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); \
901 tcg_gen_st_tl(arg2, cpu_env, offsetof(CPUState, CP0_BadVAddr)); \
902 generate_exception(ctx, EXCP_AdES); \
904 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \
905 tcg_gen_brcond_tl(TCG_COND_NE, arg2, t0, l2); \
906 tcg_gen_movi_tl(t0, rt | ((almask << 3) & 0x20)); \
907 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, llreg)); \
908 tcg_gen_st_tl(arg1, cpu_env, offsetof(CPUState, llnewval)); \
909 gen_helper_0i(raise_exception, EXCP_SC); \
911 tcg_gen_movi_tl(t0, 0); \
912 gen_store_gpr(t0, rt); \
916 #define OP_ST_ATOMIC(insn,fname,ldname,almask) \
917 static inline void op_ldst_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) \
919 TCGv t0 = tcg_temp_new(); \
920 gen_helper_3i(insn, t0, arg1, arg2, ctx->mem_idx); \
921 gen_store_gpr(t0, rt); \
925 OP_ST_ATOMIC(sc
,st32
,ld32s
,0x3);
926 #if defined(TARGET_MIPS64)
927 OP_ST_ATOMIC(scd
,st64
,ld64
,0x7);
931 static void gen_base_offset_addr (DisasContext
*ctx
, TCGv addr
,
932 int base
, int16_t offset
)
935 tcg_gen_movi_tl(addr
, offset
);
936 } else if (offset
== 0) {
937 gen_load_gpr(addr
, base
);
939 tcg_gen_movi_tl(addr
, offset
);
940 gen_op_addr_add(ctx
, addr
, cpu_gpr
[base
], addr
);
944 static target_ulong
pc_relative_pc (DisasContext
*ctx
)
946 target_ulong pc
= ctx
->pc
;
948 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
949 int branch_bytes
= ctx
->hflags
& MIPS_HFLAG_BDS16
? 2 : 4;
954 pc
&= ~(target_ulong
)3;
959 static void gen_ldst (DisasContext
*ctx
, uint32_t opc
, int rt
,
960 int base
, int16_t offset
)
962 const char *opn
= "ldst";
963 TCGv t0
= tcg_temp_new();
964 TCGv t1
= tcg_temp_new();
966 gen_base_offset_addr(ctx
, t0
, base
, offset
);
967 /* Don't do NOP if destination is zero: we must perform the actual
970 #if defined(TARGET_MIPS64)
972 save_cpu_state(ctx
, 0);
973 op_ldst_lwu(t0
, t0
, ctx
);
974 gen_store_gpr(t0
, rt
);
978 save_cpu_state(ctx
, 0);
979 op_ldst_ld(t0
, t0
, ctx
);
980 gen_store_gpr(t0
, rt
);
984 save_cpu_state(ctx
, 0);
985 op_ldst_lld(t0
, t0
, ctx
);
986 gen_store_gpr(t0
, rt
);
990 save_cpu_state(ctx
, 0);
991 gen_load_gpr(t1
, rt
);
992 op_ldst_sd(t1
, t0
, ctx
);
996 save_cpu_state(ctx
, 1);
997 gen_load_gpr(t1
, rt
);
998 gen_helper_3i(ldl
, t1
, t1
, t0
, ctx
->mem_idx
);
999 gen_store_gpr(t1
, rt
);
1003 save_cpu_state(ctx
, 1);
1004 gen_load_gpr(t1
, rt
);
1005 gen_helper_2i(sdl
, t1
, t0
, ctx
->mem_idx
);
1009 save_cpu_state(ctx
, 1);
1010 gen_load_gpr(t1
, rt
);
1011 gen_helper_3i(ldr
, t1
, t1
, t0
, ctx
->mem_idx
);
1012 gen_store_gpr(t1
, rt
);
1016 save_cpu_state(ctx
, 1);
1017 gen_load_gpr(t1
, rt
);
1018 gen_helper_2i(sdr
, t1
, t0
, ctx
->mem_idx
);
1022 save_cpu_state(ctx
, 1);
1023 tcg_gen_movi_tl(t1
, pc_relative_pc(ctx
));
1024 gen_op_addr_add(ctx
, t0
, t0
, t1
);
1025 op_ldst_ld(t0
, t0
, ctx
);
1026 gen_store_gpr(t0
, rt
);
1030 save_cpu_state(ctx
, 1);
1031 tcg_gen_movi_tl(t1
, pc_relative_pc(ctx
));
1032 gen_op_addr_add(ctx
, t0
, t0
, t1
);
1033 op_ldst_lw(t0
, t0
, ctx
);
1034 gen_store_gpr(t0
, rt
);
1037 save_cpu_state(ctx
, 0);
1038 op_ldst_lw(t0
, t0
, ctx
);
1039 gen_store_gpr(t0
, rt
);
1043 save_cpu_state(ctx
, 0);
1044 gen_load_gpr(t1
, rt
);
1045 op_ldst_sw(t1
, t0
, ctx
);
1049 save_cpu_state(ctx
, 0);
1050 op_ldst_lh(t0
, t0
, ctx
);
1051 gen_store_gpr(t0
, rt
);
1055 save_cpu_state(ctx
, 0);
1056 gen_load_gpr(t1
, rt
);
1057 op_ldst_sh(t1
, t0
, ctx
);
1061 save_cpu_state(ctx
, 0);
1062 op_ldst_lhu(t0
, t0
, ctx
);
1063 gen_store_gpr(t0
, rt
);
1067 save_cpu_state(ctx
, 0);
1068 op_ldst_lb(t0
, t0
, ctx
);
1069 gen_store_gpr(t0
, rt
);
1073 save_cpu_state(ctx
, 0);
1074 gen_load_gpr(t1
, rt
);
1075 op_ldst_sb(t1
, t0
, ctx
);
1079 save_cpu_state(ctx
, 0);
1080 op_ldst_lbu(t0
, t0
, ctx
);
1081 gen_store_gpr(t0
, rt
);
1085 save_cpu_state(ctx
, 1);
1086 gen_load_gpr(t1
, rt
);
1087 gen_helper_3i(lwl
, t1
, t1
, t0
, ctx
->mem_idx
);
1088 gen_store_gpr(t1
, rt
);
1092 save_cpu_state(ctx
, 1);
1093 gen_load_gpr(t1
, rt
);
1094 gen_helper_2i(swl
, t1
, t0
, ctx
->mem_idx
);
1098 save_cpu_state(ctx
, 1);
1099 gen_load_gpr(t1
, rt
);
1100 gen_helper_3i(lwr
, t1
, t1
, t0
, ctx
->mem_idx
);
1101 gen_store_gpr(t1
, rt
);
1105 save_cpu_state(ctx
, 1);
1106 gen_load_gpr(t1
, rt
);
1107 gen_helper_2i(swr
, t1
, t0
, ctx
->mem_idx
);
1111 save_cpu_state(ctx
, 1);
1112 op_ldst_ll(t0
, t0
, ctx
);
1113 gen_store_gpr(t0
, rt
);
1117 MIPS_DEBUG("%s %s, %d(%s)", opn
, regnames
[rt
], offset
, regnames
[base
]);
1122 /* Store conditional */
1123 static void gen_st_cond (DisasContext
*ctx
, uint32_t opc
, int rt
,
1124 int base
, int16_t offset
)
1126 const char *opn
= "st_cond";
1129 t0
= tcg_temp_local_new();
1131 gen_base_offset_addr(ctx
, t0
, base
, offset
);
1132 /* Don't do NOP if destination is zero: we must perform the actual
1135 t1
= tcg_temp_local_new();
1136 gen_load_gpr(t1
, rt
);
1138 #if defined(TARGET_MIPS64)
1140 save_cpu_state(ctx
, 0);
1141 op_ldst_scd(t1
, t0
, rt
, ctx
);
1146 save_cpu_state(ctx
, 1);
1147 op_ldst_sc(t1
, t0
, rt
, ctx
);
1151 MIPS_DEBUG("%s %s, %d(%s)", opn
, regnames
[rt
], offset
, regnames
[base
]);
1156 /* Load and store */
1157 static void gen_flt_ldst (DisasContext
*ctx
, uint32_t opc
, int ft
,
1158 int base
, int16_t offset
)
1160 const char *opn
= "flt_ldst";
1161 TCGv t0
= tcg_temp_new();
1163 gen_base_offset_addr(ctx
, t0
, base
, offset
);
1164 /* Don't do NOP if destination is zero: we must perform the actual
1169 TCGv_i32 fp0
= tcg_temp_new_i32();
1171 tcg_gen_qemu_ld32s(t0
, t0
, ctx
->mem_idx
);
1172 tcg_gen_trunc_tl_i32(fp0
, t0
);
1173 gen_store_fpr32(fp0
, ft
);
1174 tcg_temp_free_i32(fp0
);
1180 TCGv_i32 fp0
= tcg_temp_new_i32();
1181 TCGv t1
= tcg_temp_new();
1183 gen_load_fpr32(fp0
, ft
);
1184 tcg_gen_extu_i32_tl(t1
, fp0
);
1185 tcg_gen_qemu_st32(t1
, t0
, ctx
->mem_idx
);
1187 tcg_temp_free_i32(fp0
);
1193 TCGv_i64 fp0
= tcg_temp_new_i64();
1195 tcg_gen_qemu_ld64(fp0
, t0
, ctx
->mem_idx
);
1196 gen_store_fpr64(ctx
, fp0
, ft
);
1197 tcg_temp_free_i64(fp0
);
1203 TCGv_i64 fp0
= tcg_temp_new_i64();
1205 gen_load_fpr64(ctx
, fp0
, ft
);
1206 tcg_gen_qemu_st64(fp0
, t0
, ctx
->mem_idx
);
1207 tcg_temp_free_i64(fp0
);
1213 generate_exception(ctx
, EXCP_RI
);
1216 MIPS_DEBUG("%s %s, %d(%s)", opn
, fregnames
[ft
], offset
, regnames
[base
]);
1221 /* Arithmetic with immediate operand */
1222 static void gen_arith_imm (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1223 int rt
, int rs
, int16_t imm
)
1225 target_ulong uimm
= (target_long
)imm
; /* Sign extend to 32/64 bits */
1226 const char *opn
= "imm arith";
1228 if (rt
== 0 && opc
!= OPC_ADDI
&& opc
!= OPC_DADDI
) {
1229 /* If no destination, treat it as a NOP.
1230 For addi, we must generate the overflow exception when needed. */
1237 TCGv t0
= tcg_temp_local_new();
1238 TCGv t1
= tcg_temp_new();
1239 TCGv t2
= tcg_temp_new();
1240 int l1
= gen_new_label();
1242 gen_load_gpr(t1
, rs
);
1243 tcg_gen_addi_tl(t0
, t1
, uimm
);
1244 tcg_gen_ext32s_tl(t0
, t0
);
1246 tcg_gen_xori_tl(t1
, t1
, ~uimm
);
1247 tcg_gen_xori_tl(t2
, t0
, uimm
);
1248 tcg_gen_and_tl(t1
, t1
, t2
);
1250 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
1252 /* operands of same sign, result different sign */
1253 generate_exception(ctx
, EXCP_OVERFLOW
);
1255 tcg_gen_ext32s_tl(t0
, t0
);
1256 gen_store_gpr(t0
, rt
);
1263 tcg_gen_addi_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
1264 tcg_gen_ext32s_tl(cpu_gpr
[rt
], cpu_gpr
[rt
]);
1266 tcg_gen_movi_tl(cpu_gpr
[rt
], uimm
);
1270 #if defined(TARGET_MIPS64)
1273 TCGv t0
= tcg_temp_local_new();
1274 TCGv t1
= tcg_temp_new();
1275 TCGv t2
= tcg_temp_new();
1276 int l1
= gen_new_label();
1278 gen_load_gpr(t1
, rs
);
1279 tcg_gen_addi_tl(t0
, t1
, uimm
);
1281 tcg_gen_xori_tl(t1
, t1
, ~uimm
);
1282 tcg_gen_xori_tl(t2
, t0
, uimm
);
1283 tcg_gen_and_tl(t1
, t1
, t2
);
1285 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
1287 /* operands of same sign, result different sign */
1288 generate_exception(ctx
, EXCP_OVERFLOW
);
1290 gen_store_gpr(t0
, rt
);
1297 tcg_gen_addi_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
1299 tcg_gen_movi_tl(cpu_gpr
[rt
], uimm
);
1305 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx
, opn
, regnames
[rt
], regnames
[rs
], uimm
);
1308 /* Logic with immediate operand */
1309 static void gen_logic_imm (CPUState
*env
, uint32_t opc
, int rt
, int rs
, int16_t imm
)
1312 const char *opn
= "imm logic";
1315 /* If no destination, treat it as a NOP. */
1319 uimm
= (uint16_t)imm
;
1322 if (likely(rs
!= 0))
1323 tcg_gen_andi_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
1325 tcg_gen_movi_tl(cpu_gpr
[rt
], 0);
1330 tcg_gen_ori_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
1332 tcg_gen_movi_tl(cpu_gpr
[rt
], uimm
);
1336 if (likely(rs
!= 0))
1337 tcg_gen_xori_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
1339 tcg_gen_movi_tl(cpu_gpr
[rt
], uimm
);
1343 tcg_gen_movi_tl(cpu_gpr
[rt
], imm
<< 16);
1347 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx
, opn
, regnames
[rt
], regnames
[rs
], uimm
);
1350 /* Set on less than with immediate operand */
1351 static void gen_slt_imm (CPUState
*env
, uint32_t opc
, int rt
, int rs
, int16_t imm
)
1353 target_ulong uimm
= (target_long
)imm
; /* Sign extend to 32/64 bits */
1354 const char *opn
= "imm arith";
1358 /* If no destination, treat it as a NOP. */
1362 t0
= tcg_temp_new();
1363 gen_load_gpr(t0
, rs
);
1366 tcg_gen_setcondi_tl(TCG_COND_LT
, cpu_gpr
[rt
], t0
, uimm
);
1370 tcg_gen_setcondi_tl(TCG_COND_LTU
, cpu_gpr
[rt
], t0
, uimm
);
1374 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx
, opn
, regnames
[rt
], regnames
[rs
], uimm
);
1378 /* Shifts with immediate operand */
1379 static void gen_shift_imm(CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1380 int rt
, int rs
, int16_t imm
)
1382 target_ulong uimm
= ((uint16_t)imm
) & 0x1f;
1383 const char *opn
= "imm shift";
1387 /* If no destination, treat it as a NOP. */
1392 t0
= tcg_temp_new();
1393 gen_load_gpr(t0
, rs
);
1396 tcg_gen_shli_tl(t0
, t0
, uimm
);
1397 tcg_gen_ext32s_tl(cpu_gpr
[rt
], t0
);
1401 tcg_gen_sari_tl(cpu_gpr
[rt
], t0
, uimm
);
1406 tcg_gen_ext32u_tl(t0
, t0
);
1407 tcg_gen_shri_tl(cpu_gpr
[rt
], t0
, uimm
);
1409 tcg_gen_ext32s_tl(cpu_gpr
[rt
], t0
);
1415 TCGv_i32 t1
= tcg_temp_new_i32();
1417 tcg_gen_trunc_tl_i32(t1
, t0
);
1418 tcg_gen_rotri_i32(t1
, t1
, uimm
);
1419 tcg_gen_ext_i32_tl(cpu_gpr
[rt
], t1
);
1420 tcg_temp_free_i32(t1
);
1422 tcg_gen_ext32s_tl(cpu_gpr
[rt
], t0
);
1426 #if defined(TARGET_MIPS64)
1428 tcg_gen_shli_tl(cpu_gpr
[rt
], t0
, uimm
);
1432 tcg_gen_sari_tl(cpu_gpr
[rt
], t0
, uimm
);
1436 tcg_gen_shri_tl(cpu_gpr
[rt
], t0
, uimm
);
1441 tcg_gen_rotri_tl(cpu_gpr
[rt
], t0
, uimm
);
1443 tcg_gen_mov_tl(cpu_gpr
[rt
], t0
);
1448 tcg_gen_shli_tl(cpu_gpr
[rt
], t0
, uimm
+ 32);
1452 tcg_gen_sari_tl(cpu_gpr
[rt
], t0
, uimm
+ 32);
1456 tcg_gen_shri_tl(cpu_gpr
[rt
], t0
, uimm
+ 32);
1460 tcg_gen_rotri_tl(cpu_gpr
[rt
], t0
, uimm
+ 32);
1465 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx
, opn
, regnames
[rt
], regnames
[rs
], uimm
);
1470 static void gen_arith (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1471 int rd
, int rs
, int rt
)
1473 const char *opn
= "arith";
1475 if (rd
== 0 && opc
!= OPC_ADD
&& opc
!= OPC_SUB
1476 && opc
!= OPC_DADD
&& opc
!= OPC_DSUB
) {
1477 /* If no destination, treat it as a NOP.
1478 For add & sub, we must generate the overflow exception when needed. */
1486 TCGv t0
= tcg_temp_local_new();
1487 TCGv t1
= tcg_temp_new();
1488 TCGv t2
= tcg_temp_new();
1489 int l1
= gen_new_label();
1491 gen_load_gpr(t1
, rs
);
1492 gen_load_gpr(t2
, rt
);
1493 tcg_gen_add_tl(t0
, t1
, t2
);
1494 tcg_gen_ext32s_tl(t0
, t0
);
1495 tcg_gen_xor_tl(t1
, t1
, t2
);
1496 tcg_gen_xor_tl(t2
, t0
, t2
);
1497 tcg_gen_andc_tl(t1
, t2
, t1
);
1499 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
1501 /* operands of same sign, result different sign */
1502 generate_exception(ctx
, EXCP_OVERFLOW
);
1504 gen_store_gpr(t0
, rd
);
1510 if (rs
!= 0 && rt
!= 0) {
1511 tcg_gen_add_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1512 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
1513 } else if (rs
== 0 && rt
!= 0) {
1514 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1515 } else if (rs
!= 0 && rt
== 0) {
1516 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1518 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1524 TCGv t0
= tcg_temp_local_new();
1525 TCGv t1
= tcg_temp_new();
1526 TCGv t2
= tcg_temp_new();
1527 int l1
= gen_new_label();
1529 gen_load_gpr(t1
, rs
);
1530 gen_load_gpr(t2
, rt
);
1531 tcg_gen_sub_tl(t0
, t1
, t2
);
1532 tcg_gen_ext32s_tl(t0
, t0
);
1533 tcg_gen_xor_tl(t2
, t1
, t2
);
1534 tcg_gen_xor_tl(t1
, t0
, t1
);
1535 tcg_gen_and_tl(t1
, t1
, t2
);
1537 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
1539 /* operands of different sign, first operand and result different sign */
1540 generate_exception(ctx
, EXCP_OVERFLOW
);
1542 gen_store_gpr(t0
, rd
);
1548 if (rs
!= 0 && rt
!= 0) {
1549 tcg_gen_sub_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1550 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
1551 } else if (rs
== 0 && rt
!= 0) {
1552 tcg_gen_neg_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1553 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
1554 } else if (rs
!= 0 && rt
== 0) {
1555 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1557 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1561 #if defined(TARGET_MIPS64)
1564 TCGv t0
= tcg_temp_local_new();
1565 TCGv t1
= tcg_temp_new();
1566 TCGv t2
= tcg_temp_new();
1567 int l1
= gen_new_label();
1569 gen_load_gpr(t1
, rs
);
1570 gen_load_gpr(t2
, rt
);
1571 tcg_gen_add_tl(t0
, t1
, t2
);
1572 tcg_gen_xor_tl(t1
, t1
, t2
);
1573 tcg_gen_xor_tl(t2
, t0
, t2
);
1574 tcg_gen_andc_tl(t1
, t2
, t1
);
1576 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
1578 /* operands of same sign, result different sign */
1579 generate_exception(ctx
, EXCP_OVERFLOW
);
1581 gen_store_gpr(t0
, rd
);
1587 if (rs
!= 0 && rt
!= 0) {
1588 tcg_gen_add_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1589 } else if (rs
== 0 && rt
!= 0) {
1590 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1591 } else if (rs
!= 0 && rt
== 0) {
1592 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1594 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1600 TCGv t0
= tcg_temp_local_new();
1601 TCGv t1
= tcg_temp_new();
1602 TCGv t2
= tcg_temp_new();
1603 int l1
= gen_new_label();
1605 gen_load_gpr(t1
, rs
);
1606 gen_load_gpr(t2
, rt
);
1607 tcg_gen_sub_tl(t0
, t1
, t2
);
1608 tcg_gen_xor_tl(t2
, t1
, t2
);
1609 tcg_gen_xor_tl(t1
, t0
, t1
);
1610 tcg_gen_and_tl(t1
, t1
, t2
);
1612 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
1614 /* operands of different sign, first operand and result different sign */
1615 generate_exception(ctx
, EXCP_OVERFLOW
);
1617 gen_store_gpr(t0
, rd
);
1623 if (rs
!= 0 && rt
!= 0) {
1624 tcg_gen_sub_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1625 } else if (rs
== 0 && rt
!= 0) {
1626 tcg_gen_neg_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1627 } else if (rs
!= 0 && rt
== 0) {
1628 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1630 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1636 if (likely(rs
!= 0 && rt
!= 0)) {
1637 tcg_gen_mul_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1638 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
1640 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1645 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1648 /* Conditional move */
1649 static void gen_cond_move (CPUState
*env
, uint32_t opc
, int rd
, int rs
, int rt
)
1651 const char *opn
= "cond move";
1655 /* If no destination, treat it as a NOP.
1656 For add & sub, we must generate the overflow exception when needed. */
1661 l1
= gen_new_label();
1664 if (likely(rt
!= 0))
1665 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rt
], 0, l1
);
1671 if (likely(rt
!= 0))
1672 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[rt
], 0, l1
);
1677 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1679 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1682 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1686 static void gen_logic (CPUState
*env
, uint32_t opc
, int rd
, int rs
, int rt
)
1688 const char *opn
= "logic";
1691 /* If no destination, treat it as a NOP. */
1698 if (likely(rs
!= 0 && rt
!= 0)) {
1699 tcg_gen_and_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1701 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1706 if (rs
!= 0 && rt
!= 0) {
1707 tcg_gen_nor_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1708 } else if (rs
== 0 && rt
!= 0) {
1709 tcg_gen_not_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1710 } else if (rs
!= 0 && rt
== 0) {
1711 tcg_gen_not_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1713 tcg_gen_movi_tl(cpu_gpr
[rd
], ~((target_ulong
)0));
1718 if (likely(rs
!= 0 && rt
!= 0)) {
1719 tcg_gen_or_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1720 } else if (rs
== 0 && rt
!= 0) {
1721 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1722 } else if (rs
!= 0 && rt
== 0) {
1723 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1725 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1730 if (likely(rs
!= 0 && rt
!= 0)) {
1731 tcg_gen_xor_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1732 } else if (rs
== 0 && rt
!= 0) {
1733 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1734 } else if (rs
!= 0 && rt
== 0) {
1735 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1737 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1742 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1745 /* Set on lower than */
1746 static void gen_slt (CPUState
*env
, uint32_t opc
, int rd
, int rs
, int rt
)
1748 const char *opn
= "slt";
1752 /* If no destination, treat it as a NOP. */
1757 t0
= tcg_temp_new();
1758 t1
= tcg_temp_new();
1759 gen_load_gpr(t0
, rs
);
1760 gen_load_gpr(t1
, rt
);
1763 tcg_gen_setcond_tl(TCG_COND_LT
, cpu_gpr
[rd
], t0
, t1
);
1767 tcg_gen_setcond_tl(TCG_COND_LTU
, cpu_gpr
[rd
], t0
, t1
);
1771 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1777 static void gen_shift (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1778 int rd
, int rs
, int rt
)
1780 const char *opn
= "shifts";
1784 /* If no destination, treat it as a NOP.
1785 For add & sub, we must generate the overflow exception when needed. */
1790 t0
= tcg_temp_new();
1791 t1
= tcg_temp_new();
1792 gen_load_gpr(t0
, rs
);
1793 gen_load_gpr(t1
, rt
);
1796 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1797 tcg_gen_shl_tl(t0
, t1
, t0
);
1798 tcg_gen_ext32s_tl(cpu_gpr
[rd
], t0
);
1802 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1803 tcg_gen_sar_tl(cpu_gpr
[rd
], t1
, t0
);
1807 tcg_gen_ext32u_tl(t1
, t1
);
1808 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1809 tcg_gen_shr_tl(t0
, t1
, t0
);
1810 tcg_gen_ext32s_tl(cpu_gpr
[rd
], t0
);
1815 TCGv_i32 t2
= tcg_temp_new_i32();
1816 TCGv_i32 t3
= tcg_temp_new_i32();
1818 tcg_gen_trunc_tl_i32(t2
, t0
);
1819 tcg_gen_trunc_tl_i32(t3
, t1
);
1820 tcg_gen_andi_i32(t2
, t2
, 0x1f);
1821 tcg_gen_rotr_i32(t2
, t3
, t2
);
1822 tcg_gen_ext_i32_tl(cpu_gpr
[rd
], t2
);
1823 tcg_temp_free_i32(t2
);
1824 tcg_temp_free_i32(t3
);
1828 #if defined(TARGET_MIPS64)
1830 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1831 tcg_gen_shl_tl(cpu_gpr
[rd
], t1
, t0
);
1835 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1836 tcg_gen_sar_tl(cpu_gpr
[rd
], t1
, t0
);
1840 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1841 tcg_gen_shr_tl(cpu_gpr
[rd
], t1
, t0
);
1845 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1846 tcg_gen_rotr_tl(cpu_gpr
[rd
], t1
, t0
);
1851 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1856 /* Arithmetic on HI/LO registers */
1857 static void gen_HILO (DisasContext
*ctx
, uint32_t opc
, int reg
)
1859 const char *opn
= "hilo";
1861 if (reg
== 0 && (opc
== OPC_MFHI
|| opc
== OPC_MFLO
)) {
1868 tcg_gen_mov_tl(cpu_gpr
[reg
], cpu_HI
[0]);
1872 tcg_gen_mov_tl(cpu_gpr
[reg
], cpu_LO
[0]);
1877 tcg_gen_mov_tl(cpu_HI
[0], cpu_gpr
[reg
]);
1879 tcg_gen_movi_tl(cpu_HI
[0], 0);
1884 tcg_gen_mov_tl(cpu_LO
[0], cpu_gpr
[reg
]);
1886 tcg_gen_movi_tl(cpu_LO
[0], 0);
1890 MIPS_DEBUG("%s %s", opn
, regnames
[reg
]);
1893 static void gen_muldiv (DisasContext
*ctx
, uint32_t opc
,
1896 const char *opn
= "mul/div";
1902 #if defined(TARGET_MIPS64)
1906 t0
= tcg_temp_local_new();
1907 t1
= tcg_temp_local_new();
1910 t0
= tcg_temp_new();
1911 t1
= tcg_temp_new();
1915 gen_load_gpr(t0
, rs
);
1916 gen_load_gpr(t1
, rt
);
1920 int l1
= gen_new_label();
1921 int l2
= gen_new_label();
1923 tcg_gen_ext32s_tl(t0
, t0
);
1924 tcg_gen_ext32s_tl(t1
, t1
);
1925 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
1926 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, INT_MIN
, l2
);
1927 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, -1, l2
);
1929 tcg_gen_mov_tl(cpu_LO
[0], t0
);
1930 tcg_gen_movi_tl(cpu_HI
[0], 0);
1933 tcg_gen_div_tl(cpu_LO
[0], t0
, t1
);
1934 tcg_gen_rem_tl(cpu_HI
[0], t0
, t1
);
1935 tcg_gen_ext32s_tl(cpu_LO
[0], cpu_LO
[0]);
1936 tcg_gen_ext32s_tl(cpu_HI
[0], cpu_HI
[0]);
1943 int l1
= gen_new_label();
1945 tcg_gen_ext32u_tl(t0
, t0
);
1946 tcg_gen_ext32u_tl(t1
, t1
);
1947 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
1948 tcg_gen_divu_tl(cpu_LO
[0], t0
, t1
);
1949 tcg_gen_remu_tl(cpu_HI
[0], t0
, t1
);
1950 tcg_gen_ext32s_tl(cpu_LO
[0], cpu_LO
[0]);
1951 tcg_gen_ext32s_tl(cpu_HI
[0], cpu_HI
[0]);
1958 TCGv_i64 t2
= tcg_temp_new_i64();
1959 TCGv_i64 t3
= tcg_temp_new_i64();
1961 tcg_gen_ext_tl_i64(t2
, t0
);
1962 tcg_gen_ext_tl_i64(t3
, t1
);
1963 tcg_gen_mul_i64(t2
, t2
, t3
);
1964 tcg_temp_free_i64(t3
);
1965 tcg_gen_trunc_i64_tl(t0
, t2
);
1966 tcg_gen_shri_i64(t2
, t2
, 32);
1967 tcg_gen_trunc_i64_tl(t1
, t2
);
1968 tcg_temp_free_i64(t2
);
1969 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
1970 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
1976 TCGv_i64 t2
= tcg_temp_new_i64();
1977 TCGv_i64 t3
= tcg_temp_new_i64();
1979 tcg_gen_ext32u_tl(t0
, t0
);
1980 tcg_gen_ext32u_tl(t1
, t1
);
1981 tcg_gen_extu_tl_i64(t2
, t0
);
1982 tcg_gen_extu_tl_i64(t3
, t1
);
1983 tcg_gen_mul_i64(t2
, t2
, t3
);
1984 tcg_temp_free_i64(t3
);
1985 tcg_gen_trunc_i64_tl(t0
, t2
);
1986 tcg_gen_shri_i64(t2
, t2
, 32);
1987 tcg_gen_trunc_i64_tl(t1
, t2
);
1988 tcg_temp_free_i64(t2
);
1989 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
1990 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
1994 #if defined(TARGET_MIPS64)
1997 int l1
= gen_new_label();
1998 int l2
= gen_new_label();
2000 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
2001 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, -1LL << 63, l2
);
2002 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, -1LL, l2
);
2003 tcg_gen_mov_tl(cpu_LO
[0], t0
);
2004 tcg_gen_movi_tl(cpu_HI
[0], 0);
2007 tcg_gen_div_i64(cpu_LO
[0], t0
, t1
);
2008 tcg_gen_rem_i64(cpu_HI
[0], t0
, t1
);
2015 int l1
= gen_new_label();
2017 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
2018 tcg_gen_divu_i64(cpu_LO
[0], t0
, t1
);
2019 tcg_gen_remu_i64(cpu_HI
[0], t0
, t1
);
2025 gen_helper_dmult(t0
, t1
);
2029 gen_helper_dmultu(t0
, t1
);
2035 TCGv_i64 t2
= tcg_temp_new_i64();
2036 TCGv_i64 t3
= tcg_temp_new_i64();
2038 tcg_gen_ext_tl_i64(t2
, t0
);
2039 tcg_gen_ext_tl_i64(t3
, t1
);
2040 tcg_gen_mul_i64(t2
, t2
, t3
);
2041 tcg_gen_concat_tl_i64(t3
, cpu_LO
[0], cpu_HI
[0]);
2042 tcg_gen_add_i64(t2
, t2
, t3
);
2043 tcg_temp_free_i64(t3
);
2044 tcg_gen_trunc_i64_tl(t0
, t2
);
2045 tcg_gen_shri_i64(t2
, t2
, 32);
2046 tcg_gen_trunc_i64_tl(t1
, t2
);
2047 tcg_temp_free_i64(t2
);
2048 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2049 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2055 TCGv_i64 t2
= tcg_temp_new_i64();
2056 TCGv_i64 t3
= tcg_temp_new_i64();
2058 tcg_gen_ext32u_tl(t0
, t0
);
2059 tcg_gen_ext32u_tl(t1
, t1
);
2060 tcg_gen_extu_tl_i64(t2
, t0
);
2061 tcg_gen_extu_tl_i64(t3
, t1
);
2062 tcg_gen_mul_i64(t2
, t2
, t3
);
2063 tcg_gen_concat_tl_i64(t3
, cpu_LO
[0], cpu_HI
[0]);
2064 tcg_gen_add_i64(t2
, t2
, t3
);
2065 tcg_temp_free_i64(t3
);
2066 tcg_gen_trunc_i64_tl(t0
, t2
);
2067 tcg_gen_shri_i64(t2
, t2
, 32);
2068 tcg_gen_trunc_i64_tl(t1
, t2
);
2069 tcg_temp_free_i64(t2
);
2070 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2071 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2077 TCGv_i64 t2
= tcg_temp_new_i64();
2078 TCGv_i64 t3
= tcg_temp_new_i64();
2080 tcg_gen_ext_tl_i64(t2
, t0
);
2081 tcg_gen_ext_tl_i64(t3
, t1
);
2082 tcg_gen_mul_i64(t2
, t2
, t3
);
2083 tcg_gen_concat_tl_i64(t3
, cpu_LO
[0], cpu_HI
[0]);
2084 tcg_gen_sub_i64(t2
, t3
, t2
);
2085 tcg_temp_free_i64(t3
);
2086 tcg_gen_trunc_i64_tl(t0
, t2
);
2087 tcg_gen_shri_i64(t2
, t2
, 32);
2088 tcg_gen_trunc_i64_tl(t1
, t2
);
2089 tcg_temp_free_i64(t2
);
2090 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2091 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2097 TCGv_i64 t2
= tcg_temp_new_i64();
2098 TCGv_i64 t3
= tcg_temp_new_i64();
2100 tcg_gen_ext32u_tl(t0
, t0
);
2101 tcg_gen_ext32u_tl(t1
, t1
);
2102 tcg_gen_extu_tl_i64(t2
, t0
);
2103 tcg_gen_extu_tl_i64(t3
, t1
);
2104 tcg_gen_mul_i64(t2
, t2
, t3
);
2105 tcg_gen_concat_tl_i64(t3
, cpu_LO
[0], cpu_HI
[0]);
2106 tcg_gen_sub_i64(t2
, t3
, t2
);
2107 tcg_temp_free_i64(t3
);
2108 tcg_gen_trunc_i64_tl(t0
, t2
);
2109 tcg_gen_shri_i64(t2
, t2
, 32);
2110 tcg_gen_trunc_i64_tl(t1
, t2
);
2111 tcg_temp_free_i64(t2
);
2112 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2113 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2119 generate_exception(ctx
, EXCP_RI
);
2122 MIPS_DEBUG("%s %s %s", opn
, regnames
[rs
], regnames
[rt
]);
2128 static void gen_mul_vr54xx (DisasContext
*ctx
, uint32_t opc
,
2129 int rd
, int rs
, int rt
)
2131 const char *opn
= "mul vr54xx";
2132 TCGv t0
= tcg_temp_new();
2133 TCGv t1
= tcg_temp_new();
2135 gen_load_gpr(t0
, rs
);
2136 gen_load_gpr(t1
, rt
);
2139 case OPC_VR54XX_MULS
:
2140 gen_helper_muls(t0
, t0
, t1
);
2143 case OPC_VR54XX_MULSU
:
2144 gen_helper_mulsu(t0
, t0
, t1
);
2147 case OPC_VR54XX_MACC
:
2148 gen_helper_macc(t0
, t0
, t1
);
2151 case OPC_VR54XX_MACCU
:
2152 gen_helper_maccu(t0
, t0
, t1
);
2155 case OPC_VR54XX_MSAC
:
2156 gen_helper_msac(t0
, t0
, t1
);
2159 case OPC_VR54XX_MSACU
:
2160 gen_helper_msacu(t0
, t0
, t1
);
2163 case OPC_VR54XX_MULHI
:
2164 gen_helper_mulhi(t0
, t0
, t1
);
2167 case OPC_VR54XX_MULHIU
:
2168 gen_helper_mulhiu(t0
, t0
, t1
);
2171 case OPC_VR54XX_MULSHI
:
2172 gen_helper_mulshi(t0
, t0
, t1
);
2175 case OPC_VR54XX_MULSHIU
:
2176 gen_helper_mulshiu(t0
, t0
, t1
);
2179 case OPC_VR54XX_MACCHI
:
2180 gen_helper_macchi(t0
, t0
, t1
);
2183 case OPC_VR54XX_MACCHIU
:
2184 gen_helper_macchiu(t0
, t0
, t1
);
2187 case OPC_VR54XX_MSACHI
:
2188 gen_helper_msachi(t0
, t0
, t1
);
2191 case OPC_VR54XX_MSACHIU
:
2192 gen_helper_msachiu(t0
, t0
, t1
);
2196 MIPS_INVAL("mul vr54xx");
2197 generate_exception(ctx
, EXCP_RI
);
2200 gen_store_gpr(t0
, rd
);
2201 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
2208 static void gen_cl (DisasContext
*ctx
, uint32_t opc
,
2211 const char *opn
= "CLx";
2219 t0
= tcg_temp_new();
2220 gen_load_gpr(t0
, rs
);
2223 gen_helper_clo(cpu_gpr
[rd
], t0
);
2227 gen_helper_clz(cpu_gpr
[rd
], t0
);
2230 #if defined(TARGET_MIPS64)
2232 gen_helper_dclo(cpu_gpr
[rd
], t0
);
2236 gen_helper_dclz(cpu_gpr
[rd
], t0
);
2241 MIPS_DEBUG("%s %s, %s", opn
, regnames
[rd
], regnames
[rs
]);
2246 static void gen_trap (DisasContext
*ctx
, uint32_t opc
,
2247 int rs
, int rt
, int16_t imm
)
2250 TCGv t0
= tcg_temp_new();
2251 TCGv t1
= tcg_temp_new();
2254 /* Load needed operands */
2262 /* Compare two registers */
2264 gen_load_gpr(t0
, rs
);
2265 gen_load_gpr(t1
, rt
);
2275 /* Compare register to immediate */
2276 if (rs
!= 0 || imm
!= 0) {
2277 gen_load_gpr(t0
, rs
);
2278 tcg_gen_movi_tl(t1
, (int32_t)imm
);
2285 case OPC_TEQ
: /* rs == rs */
2286 case OPC_TEQI
: /* r0 == 0 */
2287 case OPC_TGE
: /* rs >= rs */
2288 case OPC_TGEI
: /* r0 >= 0 */
2289 case OPC_TGEU
: /* rs >= rs unsigned */
2290 case OPC_TGEIU
: /* r0 >= 0 unsigned */
2292 generate_exception(ctx
, EXCP_TRAP
);
2294 case OPC_TLT
: /* rs < rs */
2295 case OPC_TLTI
: /* r0 < 0 */
2296 case OPC_TLTU
: /* rs < rs unsigned */
2297 case OPC_TLTIU
: /* r0 < 0 unsigned */
2298 case OPC_TNE
: /* rs != rs */
2299 case OPC_TNEI
: /* r0 != 0 */
2300 /* Never trap: treat as NOP. */
2304 int l1
= gen_new_label();
2309 tcg_gen_brcond_tl(TCG_COND_NE
, t0
, t1
, l1
);
2313 tcg_gen_brcond_tl(TCG_COND_LT
, t0
, t1
, l1
);
2317 tcg_gen_brcond_tl(TCG_COND_LTU
, t0
, t1
, l1
);
2321 tcg_gen_brcond_tl(TCG_COND_GE
, t0
, t1
, l1
);
2325 tcg_gen_brcond_tl(TCG_COND_GEU
, t0
, t1
, l1
);
2329 tcg_gen_brcond_tl(TCG_COND_EQ
, t0
, t1
, l1
);
2332 generate_exception(ctx
, EXCP_TRAP
);
2339 static inline void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
2341 TranslationBlock
*tb
;
2343 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) &&
2344 likely(!ctx
->singlestep_enabled
)) {
2347 tcg_gen_exit_tb((long)tb
+ n
);
2350 if (ctx
->singlestep_enabled
) {
2351 save_cpu_state(ctx
, 0);
2352 gen_helper_0i(raise_exception
, EXCP_DEBUG
);
2358 /* Branches (before delay slot) */
2359 static void gen_compute_branch (DisasContext
*ctx
, uint32_t opc
,
2361 int rs
, int rt
, int32_t offset
)
2363 target_ulong btgt
= -1;
2365 int bcond_compute
= 0;
2366 TCGv t0
= tcg_temp_new();
2367 TCGv t1
= tcg_temp_new();
2369 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
2370 #ifdef MIPS_DEBUG_DISAS
2371 LOG_DISAS("Branch in delay slot at PC 0x" TARGET_FMT_lx
"\n", ctx
->pc
);
2373 generate_exception(ctx
, EXCP_RI
);
2377 /* Load needed operands */
2383 /* Compare two registers */
2385 gen_load_gpr(t0
, rs
);
2386 gen_load_gpr(t1
, rt
);
2389 btgt
= ctx
->pc
+ insn_bytes
+ offset
;
2403 /* Compare to zero */
2405 gen_load_gpr(t0
, rs
);
2408 btgt
= ctx
->pc
+ insn_bytes
+ offset
;
2413 /* Jump to immediate */
2414 btgt
= ((ctx
->pc
+ insn_bytes
) & (int32_t)0xF0000000) | (uint32_t)offset
;
2419 /* Jump to register */
2420 if (offset
!= 0 && offset
!= 16) {
2421 /* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
2422 others are reserved. */
2423 MIPS_INVAL("jump hint");
2424 generate_exception(ctx
, EXCP_RI
);
2427 gen_load_gpr(btarget
, rs
);
2430 MIPS_INVAL("branch/jump");
2431 generate_exception(ctx
, EXCP_RI
);
2434 if (bcond_compute
== 0) {
2435 /* No condition to be computed */
2437 case OPC_BEQ
: /* rx == rx */
2438 case OPC_BEQL
: /* rx == rx likely */
2439 case OPC_BGEZ
: /* 0 >= 0 */
2440 case OPC_BGEZL
: /* 0 >= 0 likely */
2441 case OPC_BLEZ
: /* 0 <= 0 */
2442 case OPC_BLEZL
: /* 0 <= 0 likely */
2444 ctx
->hflags
|= MIPS_HFLAG_B
;
2445 MIPS_DEBUG("balways");
2447 case OPC_BGEZAL
: /* 0 >= 0 */
2448 case OPC_BGEZALL
: /* 0 >= 0 likely */
2449 /* Always take and link */
2451 ctx
->hflags
|= MIPS_HFLAG_B
;
2452 MIPS_DEBUG("balways and link");
2454 case OPC_BNE
: /* rx != rx */
2455 case OPC_BGTZ
: /* 0 > 0 */
2456 case OPC_BLTZ
: /* 0 < 0 */
2458 MIPS_DEBUG("bnever (NOP)");
2460 case OPC_BLTZAL
: /* 0 < 0 */
2461 tcg_gen_movi_tl(cpu_gpr
[31], ctx
->pc
+ 8);
2462 MIPS_DEBUG("bnever and link");
2464 case OPC_BLTZALL
: /* 0 < 0 likely */
2465 tcg_gen_movi_tl(cpu_gpr
[31], ctx
->pc
+ 8);
2466 /* Skip the instruction in the delay slot */
2467 MIPS_DEBUG("bnever, link and skip");
2470 case OPC_BNEL
: /* rx != rx likely */
2471 case OPC_BGTZL
: /* 0 > 0 likely */
2472 case OPC_BLTZL
: /* 0 < 0 likely */
2473 /* Skip the instruction in the delay slot */
2474 MIPS_DEBUG("bnever and skip");
2478 ctx
->hflags
|= MIPS_HFLAG_B
;
2479 MIPS_DEBUG("j " TARGET_FMT_lx
, btgt
);
2482 ctx
->hflags
|= MIPS_HFLAG_BX
;
2486 ctx
->hflags
|= MIPS_HFLAG_B
;
2487 ctx
->hflags
|= (ctx
->hflags
& MIPS_HFLAG_M16
2489 : MIPS_HFLAG_BDS32
);
2490 MIPS_DEBUG("jal " TARGET_FMT_lx
, btgt
);
2493 ctx
->hflags
|= MIPS_HFLAG_BR
;
2494 if (ctx
->hflags
& MIPS_HFLAG_M16
)
2495 ctx
->hflags
|= MIPS_HFLAG_BDS16
;
2496 MIPS_DEBUG("jr %s", regnames
[rs
]);
2501 ctx
->hflags
|= MIPS_HFLAG_BR
;
2502 if (ctx
->hflags
& MIPS_HFLAG_M16
)
2503 ctx
->hflags
|= MIPS_HFLAG_BDS16
;
2504 MIPS_DEBUG("jalr %s, %s", regnames
[rt
], regnames
[rs
]);
2507 MIPS_INVAL("branch/jump");
2508 generate_exception(ctx
, EXCP_RI
);
2514 tcg_gen_setcond_tl(TCG_COND_EQ
, bcond
, t0
, t1
);
2515 MIPS_DEBUG("beq %s, %s, " TARGET_FMT_lx
,
2516 regnames
[rs
], regnames
[rt
], btgt
);
2519 tcg_gen_setcond_tl(TCG_COND_EQ
, bcond
, t0
, t1
);
2520 MIPS_DEBUG("beql %s, %s, " TARGET_FMT_lx
,
2521 regnames
[rs
], regnames
[rt
], btgt
);
2524 tcg_gen_setcond_tl(TCG_COND_NE
, bcond
, t0
, t1
);
2525 MIPS_DEBUG("bne %s, %s, " TARGET_FMT_lx
,
2526 regnames
[rs
], regnames
[rt
], btgt
);
2529 tcg_gen_setcond_tl(TCG_COND_NE
, bcond
, t0
, t1
);
2530 MIPS_DEBUG("bnel %s, %s, " TARGET_FMT_lx
,
2531 regnames
[rs
], regnames
[rt
], btgt
);
2534 tcg_gen_setcondi_tl(TCG_COND_GE
, bcond
, t0
, 0);
2535 MIPS_DEBUG("bgez %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2538 tcg_gen_setcondi_tl(TCG_COND_GE
, bcond
, t0
, 0);
2539 MIPS_DEBUG("bgezl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2542 tcg_gen_setcondi_tl(TCG_COND_GE
, bcond
, t0
, 0);
2543 MIPS_DEBUG("bgezal %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2547 tcg_gen_setcondi_tl(TCG_COND_GE
, bcond
, t0
, 0);
2549 MIPS_DEBUG("bgezall %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2552 tcg_gen_setcondi_tl(TCG_COND_GT
, bcond
, t0
, 0);
2553 MIPS_DEBUG("bgtz %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2556 tcg_gen_setcondi_tl(TCG_COND_GT
, bcond
, t0
, 0);
2557 MIPS_DEBUG("bgtzl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2560 tcg_gen_setcondi_tl(TCG_COND_LE
, bcond
, t0
, 0);
2561 MIPS_DEBUG("blez %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2564 tcg_gen_setcondi_tl(TCG_COND_LE
, bcond
, t0
, 0);
2565 MIPS_DEBUG("blezl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2568 tcg_gen_setcondi_tl(TCG_COND_LT
, bcond
, t0
, 0);
2569 MIPS_DEBUG("bltz %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2572 tcg_gen_setcondi_tl(TCG_COND_LT
, bcond
, t0
, 0);
2573 MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2576 tcg_gen_setcondi_tl(TCG_COND_LT
, bcond
, t0
, 0);
2578 MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2580 ctx
->hflags
|= MIPS_HFLAG_BC
;
2583 tcg_gen_setcondi_tl(TCG_COND_LT
, bcond
, t0
, 0);
2585 MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2587 ctx
->hflags
|= MIPS_HFLAG_BL
;
2590 MIPS_INVAL("conditional branch/jump");
2591 generate_exception(ctx
, EXCP_RI
);
2595 MIPS_DEBUG("enter ds: link %d cond %02x target " TARGET_FMT_lx
,
2596 blink
, ctx
->hflags
, btgt
);
2598 ctx
->btarget
= btgt
;
2600 int post_delay
= insn_bytes
;
2601 int lowbit
= !!(ctx
->hflags
& MIPS_HFLAG_M16
);
2603 if (opc
!= OPC_JALRC
)
2604 post_delay
+= ((ctx
->hflags
& MIPS_HFLAG_BDS16
) ? 2 : 4);
2606 tcg_gen_movi_tl(cpu_gpr
[blink
], ctx
->pc
+ post_delay
+ lowbit
);
2610 if (insn_bytes
== 2)
2611 ctx
->hflags
|= MIPS_HFLAG_B16
;
2616 /* special3 bitfield operations */
2617 static void gen_bitops (DisasContext
*ctx
, uint32_t opc
, int rt
,
2618 int rs
, int lsb
, int msb
)
2620 TCGv t0
= tcg_temp_new();
2621 TCGv t1
= tcg_temp_new();
2624 gen_load_gpr(t1
, rs
);
2629 tcg_gen_shri_tl(t0
, t1
, lsb
);
2631 tcg_gen_andi_tl(t0
, t0
, (1 << (msb
+ 1)) - 1);
2633 tcg_gen_ext32s_tl(t0
, t0
);
2636 #if defined(TARGET_MIPS64)
2638 tcg_gen_shri_tl(t0
, t1
, lsb
);
2640 tcg_gen_andi_tl(t0
, t0
, (1ULL << (msb
+ 1 + 32)) - 1);
2644 tcg_gen_shri_tl(t0
, t1
, lsb
+ 32);
2645 tcg_gen_andi_tl(t0
, t0
, (1ULL << (msb
+ 1)) - 1);
2648 tcg_gen_shri_tl(t0
, t1
, lsb
);
2649 tcg_gen_andi_tl(t0
, t0
, (1ULL << (msb
+ 1)) - 1);
2655 mask
= ((msb
- lsb
+ 1 < 32) ? ((1 << (msb
- lsb
+ 1)) - 1) : ~0) << lsb
;
2656 gen_load_gpr(t0
, rt
);
2657 tcg_gen_andi_tl(t0
, t0
, ~mask
);
2658 tcg_gen_shli_tl(t1
, t1
, lsb
);
2659 tcg_gen_andi_tl(t1
, t1
, mask
);
2660 tcg_gen_or_tl(t0
, t0
, t1
);
2661 tcg_gen_ext32s_tl(t0
, t0
);
2663 #if defined(TARGET_MIPS64)
2667 mask
= ((msb
- lsb
+ 1 + 32 < 64) ? ((1ULL << (msb
- lsb
+ 1 + 32)) - 1) : ~0ULL) << lsb
;
2668 gen_load_gpr(t0
, rt
);
2669 tcg_gen_andi_tl(t0
, t0
, ~mask
);
2670 tcg_gen_shli_tl(t1
, t1
, lsb
);
2671 tcg_gen_andi_tl(t1
, t1
, mask
);
2672 tcg_gen_or_tl(t0
, t0
, t1
);
2677 mask
= ((1ULL << (msb
- lsb
+ 1)) - 1) << lsb
;
2678 gen_load_gpr(t0
, rt
);
2679 tcg_gen_andi_tl(t0
, t0
, ~mask
);
2680 tcg_gen_shli_tl(t1
, t1
, lsb
+ 32);
2681 tcg_gen_andi_tl(t1
, t1
, mask
);
2682 tcg_gen_or_tl(t0
, t0
, t1
);
2687 gen_load_gpr(t0
, rt
);
2688 mask
= ((1ULL << (msb
- lsb
+ 1)) - 1) << lsb
;
2689 gen_load_gpr(t0
, rt
);
2690 tcg_gen_andi_tl(t0
, t0
, ~mask
);
2691 tcg_gen_shli_tl(t1
, t1
, lsb
);
2692 tcg_gen_andi_tl(t1
, t1
, mask
);
2693 tcg_gen_or_tl(t0
, t0
, t1
);
2698 MIPS_INVAL("bitops");
2699 generate_exception(ctx
, EXCP_RI
);
2704 gen_store_gpr(t0
, rt
);
2709 static void gen_bshfl (DisasContext
*ctx
, uint32_t op2
, int rt
, int rd
)
2714 /* If no destination, treat it as a NOP. */
2719 t0
= tcg_temp_new();
2720 gen_load_gpr(t0
, rt
);
2724 TCGv t1
= tcg_temp_new();
2726 tcg_gen_shri_tl(t1
, t0
, 8);
2727 tcg_gen_andi_tl(t1
, t1
, 0x00FF00FF);
2728 tcg_gen_shli_tl(t0
, t0
, 8);
2729 tcg_gen_andi_tl(t0
, t0
, ~0x00FF00FF);
2730 tcg_gen_or_tl(t0
, t0
, t1
);
2732 tcg_gen_ext32s_tl(cpu_gpr
[rd
], t0
);
2736 tcg_gen_ext8s_tl(cpu_gpr
[rd
], t0
);
2739 tcg_gen_ext16s_tl(cpu_gpr
[rd
], t0
);
2741 #if defined(TARGET_MIPS64)
2744 TCGv t1
= tcg_temp_new();
2746 tcg_gen_shri_tl(t1
, t0
, 8);
2747 tcg_gen_andi_tl(t1
, t1
, 0x00FF00FF00FF00FFULL
);
2748 tcg_gen_shli_tl(t0
, t0
, 8);
2749 tcg_gen_andi_tl(t0
, t0
, ~0x00FF00FF00FF00FFULL
);
2750 tcg_gen_or_tl(cpu_gpr
[rd
], t0
, t1
);
2756 TCGv t1
= tcg_temp_new();
2758 tcg_gen_shri_tl(t1
, t0
, 16);
2759 tcg_gen_andi_tl(t1
, t1
, 0x0000FFFF0000FFFFULL
);
2760 tcg_gen_shli_tl(t0
, t0
, 16);
2761 tcg_gen_andi_tl(t0
, t0
, ~0x0000FFFF0000FFFFULL
);
2762 tcg_gen_or_tl(t0
, t0
, t1
);
2763 tcg_gen_shri_tl(t1
, t0
, 32);
2764 tcg_gen_shli_tl(t0
, t0
, 32);
2765 tcg_gen_or_tl(cpu_gpr
[rd
], t0
, t1
);
2771 MIPS_INVAL("bsfhl");
2772 generate_exception(ctx
, EXCP_RI
);
2779 #ifndef CONFIG_USER_ONLY
2780 /* CP0 (MMU and control) */
2781 static inline void gen_mfc0_load32 (TCGv arg
, target_ulong off
)
2783 TCGv_i32 t0
= tcg_temp_new_i32();
2785 tcg_gen_ld_i32(t0
, cpu_env
, off
);
2786 tcg_gen_ext_i32_tl(arg
, t0
);
2787 tcg_temp_free_i32(t0
);
2790 static inline void gen_mfc0_load64 (TCGv arg
, target_ulong off
)
2792 tcg_gen_ld_tl(arg
, cpu_env
, off
);
2793 tcg_gen_ext32s_tl(arg
, arg
);
2796 static inline void gen_mtc0_store32 (TCGv arg
, target_ulong off
)
2798 TCGv_i32 t0
= tcg_temp_new_i32();
2800 tcg_gen_trunc_tl_i32(t0
, arg
);
2801 tcg_gen_st_i32(t0
, cpu_env
, off
);
2802 tcg_temp_free_i32(t0
);
2805 static inline void gen_mtc0_store64 (TCGv arg
, target_ulong off
)
2807 tcg_gen_ext32s_tl(arg
, arg
);
2808 tcg_gen_st_tl(arg
, cpu_env
, off
);
2811 static void gen_mfc0 (CPUState
*env
, DisasContext
*ctx
, TCGv arg
, int reg
, int sel
)
2813 const char *rn
= "invalid";
2816 check_insn(env
, ctx
, ISA_MIPS32
);
2822 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Index
));
2826 check_insn(env
, ctx
, ASE_MT
);
2827 gen_helper_mfc0_mvpcontrol(arg
);
2831 check_insn(env
, ctx
, ASE_MT
);
2832 gen_helper_mfc0_mvpconf0(arg
);
2836 check_insn(env
, ctx
, ASE_MT
);
2837 gen_helper_mfc0_mvpconf1(arg
);
2847 gen_helper_mfc0_random(arg
);
2851 check_insn(env
, ctx
, ASE_MT
);
2852 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEControl
));
2856 check_insn(env
, ctx
, ASE_MT
);
2857 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEConf0
));
2861 check_insn(env
, ctx
, ASE_MT
);
2862 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEConf1
));
2866 check_insn(env
, ctx
, ASE_MT
);
2867 gen_mfc0_load64(arg
, offsetof(CPUState
, CP0_YQMask
));
2871 check_insn(env
, ctx
, ASE_MT
);
2872 gen_mfc0_load64(arg
, offsetof(CPUState
, CP0_VPESchedule
));
2876 check_insn(env
, ctx
, ASE_MT
);
2877 gen_mfc0_load64(arg
, offsetof(CPUState
, CP0_VPEScheFBack
));
2878 rn
= "VPEScheFBack";
2881 check_insn(env
, ctx
, ASE_MT
);
2882 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEOpt
));
2892 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EntryLo0
));
2893 tcg_gen_ext32s_tl(arg
, arg
);
2897 check_insn(env
, ctx
, ASE_MT
);
2898 gen_helper_mfc0_tcstatus(arg
);
2902 check_insn(env
, ctx
, ASE_MT
);
2903 gen_helper_mfc0_tcbind(arg
);
2907 check_insn(env
, ctx
, ASE_MT
);
2908 gen_helper_mfc0_tcrestart(arg
);
2912 check_insn(env
, ctx
, ASE_MT
);
2913 gen_helper_mfc0_tchalt(arg
);
2917 check_insn(env
, ctx
, ASE_MT
);
2918 gen_helper_mfc0_tccontext(arg
);
2922 check_insn(env
, ctx
, ASE_MT
);
2923 gen_helper_mfc0_tcschedule(arg
);
2927 check_insn(env
, ctx
, ASE_MT
);
2928 gen_helper_mfc0_tcschefback(arg
);
2938 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EntryLo1
));
2939 tcg_gen_ext32s_tl(arg
, arg
);
2949 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_Context
));
2950 tcg_gen_ext32s_tl(arg
, arg
);
2954 // gen_helper_mfc0_contextconfig(arg); /* SmartMIPS ASE */
2955 rn
= "ContextConfig";
2964 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_PageMask
));
2968 check_insn(env
, ctx
, ISA_MIPS32R2
);
2969 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_PageGrain
));
2979 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Wired
));
2983 check_insn(env
, ctx
, ISA_MIPS32R2
);
2984 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf0
));
2988 check_insn(env
, ctx
, ISA_MIPS32R2
);
2989 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf1
));
2993 check_insn(env
, ctx
, ISA_MIPS32R2
);
2994 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf2
));
2998 check_insn(env
, ctx
, ISA_MIPS32R2
);
2999 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf3
));
3003 check_insn(env
, ctx
, ISA_MIPS32R2
);
3004 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf4
));
3014 check_insn(env
, ctx
, ISA_MIPS32R2
);
3015 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_HWREna
));
3025 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_BadVAddr
));
3026 tcg_gen_ext32s_tl(arg
, arg
);
3036 /* Mark as an IO operation because we read the time. */
3039 gen_helper_mfc0_count(arg
);
3042 ctx
->bstate
= BS_STOP
;
3046 /* 6,7 are implementation dependent */
3054 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EntryHi
));
3055 tcg_gen_ext32s_tl(arg
, arg
);
3065 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Compare
));
3068 /* 6,7 are implementation dependent */
3076 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Status
));
3080 check_insn(env
, ctx
, ISA_MIPS32R2
);
3081 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_IntCtl
));
3085 check_insn(env
, ctx
, ISA_MIPS32R2
);
3086 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSCtl
));
3090 check_insn(env
, ctx
, ISA_MIPS32R2
);
3091 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSMap
));
3101 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Cause
));
3111 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EPC
));
3112 tcg_gen_ext32s_tl(arg
, arg
);
3122 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_PRid
));
3126 check_insn(env
, ctx
, ISA_MIPS32R2
);
3127 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_EBase
));
3137 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config0
));
3141 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config1
));
3145 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config2
));
3149 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config3
));
3152 /* 4,5 are reserved */
3153 /* 6,7 are implementation dependent */
3155 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config6
));
3159 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config7
));
3169 gen_helper_mfc0_lladdr(arg
);
3179 gen_helper_1i(mfc0_watchlo
, arg
, sel
);
3189 gen_helper_1i(mfc0_watchhi
, arg
, sel
);
3199 #if defined(TARGET_MIPS64)
3200 check_insn(env
, ctx
, ISA_MIPS3
);
3201 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_XContext
));
3202 tcg_gen_ext32s_tl(arg
, arg
);
3211 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3214 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Framemask
));
3222 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
3223 rn
= "'Diagnostic"; /* implementation dependent */
3228 gen_helper_mfc0_debug(arg
); /* EJTAG support */
3232 // gen_helper_mfc0_tracecontrol(arg); /* PDtrace support */
3233 rn
= "TraceControl";
3236 // gen_helper_mfc0_tracecontrol2(arg); /* PDtrace support */
3237 rn
= "TraceControl2";
3240 // gen_helper_mfc0_usertracedata(arg); /* PDtrace support */
3241 rn
= "UserTraceData";
3244 // gen_helper_mfc0_tracebpc(arg); /* PDtrace support */
3255 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_DEPC
));
3256 tcg_gen_ext32s_tl(arg
, arg
);
3266 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Performance0
));
3267 rn
= "Performance0";
3270 // gen_helper_mfc0_performance1(arg);
3271 rn
= "Performance1";
3274 // gen_helper_mfc0_performance2(arg);
3275 rn
= "Performance2";
3278 // gen_helper_mfc0_performance3(arg);
3279 rn
= "Performance3";
3282 // gen_helper_mfc0_performance4(arg);
3283 rn
= "Performance4";
3286 // gen_helper_mfc0_performance5(arg);
3287 rn
= "Performance5";
3290 // gen_helper_mfc0_performance6(arg);
3291 rn
= "Performance6";
3294 // gen_helper_mfc0_performance7(arg);
3295 rn
= "Performance7";
3302 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
3308 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
3321 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_TagLo
));
3328 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_DataLo
));
3341 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_TagHi
));
3348 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_DataHi
));
3358 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_ErrorEPC
));
3359 tcg_gen_ext32s_tl(arg
, arg
);
3370 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_DESAVE
));
3380 LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
3384 LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
3385 generate_exception(ctx
, EXCP_RI
);
3388 static void gen_mtc0 (CPUState
*env
, DisasContext
*ctx
, TCGv arg
, int reg
, int sel
)
3390 const char *rn
= "invalid";
3393 check_insn(env
, ctx
, ISA_MIPS32
);
3402 gen_helper_mtc0_index(arg
);
3406 check_insn(env
, ctx
, ASE_MT
);
3407 gen_helper_mtc0_mvpcontrol(arg
);
3411 check_insn(env
, ctx
, ASE_MT
);
3416 check_insn(env
, ctx
, ASE_MT
);
3431 check_insn(env
, ctx
, ASE_MT
);
3432 gen_helper_mtc0_vpecontrol(arg
);
3436 check_insn(env
, ctx
, ASE_MT
);
3437 gen_helper_mtc0_vpeconf0(arg
);
3441 check_insn(env
, ctx
, ASE_MT
);
3442 gen_helper_mtc0_vpeconf1(arg
);
3446 check_insn(env
, ctx
, ASE_MT
);
3447 gen_helper_mtc0_yqmask(arg
);
3451 check_insn(env
, ctx
, ASE_MT
);
3452 gen_mtc0_store64(arg
, offsetof(CPUState
, CP0_VPESchedule
));
3456 check_insn(env
, ctx
, ASE_MT
);
3457 gen_mtc0_store64(arg
, offsetof(CPUState
, CP0_VPEScheFBack
));
3458 rn
= "VPEScheFBack";
3461 check_insn(env
, ctx
, ASE_MT
);
3462 gen_helper_mtc0_vpeopt(arg
);
3472 gen_helper_mtc0_entrylo0(arg
);
3476 check_insn(env
, ctx
, ASE_MT
);
3477 gen_helper_mtc0_tcstatus(arg
);
3481 check_insn(env
, ctx
, ASE_MT
);
3482 gen_helper_mtc0_tcbind(arg
);
3486 check_insn(env
, ctx
, ASE_MT
);
3487 gen_helper_mtc0_tcrestart(arg
);
3491 check_insn(env
, ctx
, ASE_MT
);
3492 gen_helper_mtc0_tchalt(arg
);
3496 check_insn(env
, ctx
, ASE_MT
);
3497 gen_helper_mtc0_tccontext(arg
);
3501 check_insn(env
, ctx
, ASE_MT
);
3502 gen_helper_mtc0_tcschedule(arg
);
3506 check_insn(env
, ctx
, ASE_MT
);
3507 gen_helper_mtc0_tcschefback(arg
);
3517 gen_helper_mtc0_entrylo1(arg
);
3527 gen_helper_mtc0_context(arg
);
3531 // gen_helper_mtc0_contextconfig(arg); /* SmartMIPS ASE */
3532 rn
= "ContextConfig";
3541 gen_helper_mtc0_pagemask(arg
);
3545 check_insn(env
, ctx
, ISA_MIPS32R2
);
3546 gen_helper_mtc0_pagegrain(arg
);
3556 gen_helper_mtc0_wired(arg
);
3560 check_insn(env
, ctx
, ISA_MIPS32R2
);
3561 gen_helper_mtc0_srsconf0(arg
);
3565 check_insn(env
, ctx
, ISA_MIPS32R2
);
3566 gen_helper_mtc0_srsconf1(arg
);
3570 check_insn(env
, ctx
, ISA_MIPS32R2
);
3571 gen_helper_mtc0_srsconf2(arg
);
3575 check_insn(env
, ctx
, ISA_MIPS32R2
);
3576 gen_helper_mtc0_srsconf3(arg
);
3580 check_insn(env
, ctx
, ISA_MIPS32R2
);
3581 gen_helper_mtc0_srsconf4(arg
);
3591 check_insn(env
, ctx
, ISA_MIPS32R2
);
3592 gen_helper_mtc0_hwrena(arg
);
3606 gen_helper_mtc0_count(arg
);
3609 /* 6,7 are implementation dependent */
3617 gen_helper_mtc0_entryhi(arg
);
3627 gen_helper_mtc0_compare(arg
);
3630 /* 6,7 are implementation dependent */
3638 save_cpu_state(ctx
, 1);
3639 gen_helper_mtc0_status(arg
);
3640 /* BS_STOP isn't good enough here, hflags may have changed. */
3641 gen_save_pc(ctx
->pc
+ 4);
3642 ctx
->bstate
= BS_EXCP
;
3646 check_insn(env
, ctx
, ISA_MIPS32R2
);
3647 gen_helper_mtc0_intctl(arg
);
3648 /* Stop translation as we may have switched the execution mode */
3649 ctx
->bstate
= BS_STOP
;
3653 check_insn(env
, ctx
, ISA_MIPS32R2
);
3654 gen_helper_mtc0_srsctl(arg
);
3655 /* Stop translation as we may have switched the execution mode */
3656 ctx
->bstate
= BS_STOP
;
3660 check_insn(env
, ctx
, ISA_MIPS32R2
);
3661 gen_mtc0_store32(arg
, offsetof(CPUState
, CP0_SRSMap
));
3662 /* Stop translation as we may have switched the execution mode */
3663 ctx
->bstate
= BS_STOP
;
3673 save_cpu_state(ctx
, 1);
3674 gen_helper_mtc0_cause(arg
);
3684 gen_mtc0_store64(arg
, offsetof(CPUState
, CP0_EPC
));
3698 check_insn(env
, ctx
, ISA_MIPS32R2
);
3699 gen_helper_mtc0_ebase(arg
);
3709 gen_helper_mtc0_config0(arg
);
3711 /* Stop translation as we may have switched the execution mode */
3712 ctx
->bstate
= BS_STOP
;
3715 /* ignored, read only */
3719 gen_helper_mtc0_config2(arg
);
3721 /* Stop translation as we may have switched the execution mode */
3722 ctx
->bstate
= BS_STOP
;
3725 /* ignored, read only */
3728 /* 4,5 are reserved */
3729 /* 6,7 are implementation dependent */
3739 rn
= "Invalid config selector";
3746 gen_helper_mtc0_lladdr(arg
);
3756 gen_helper_1i(mtc0_watchlo
, arg
, sel
);
3766 gen_helper_1i(mtc0_watchhi
, arg
, sel
);
3776 #if defined(TARGET_MIPS64)
3777 check_insn(env
, ctx
, ISA_MIPS3
);
3778 gen_helper_mtc0_xcontext(arg
);
3787 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3790 gen_helper_mtc0_framemask(arg
);
3799 rn
= "Diagnostic"; /* implementation dependent */
3804 gen_helper_mtc0_debug(arg
); /* EJTAG support */
3805 /* BS_STOP isn't good enough here, hflags may have changed. */
3806 gen_save_pc(ctx
->pc
+ 4);
3807 ctx
->bstate
= BS_EXCP
;
3811 // gen_helper_mtc0_tracecontrol(arg); /* PDtrace support */
3812 rn
= "TraceControl";
3813 /* Stop translation as we may have switched the execution mode */
3814 ctx
->bstate
= BS_STOP
;
3817 // gen_helper_mtc0_tracecontrol2(arg); /* PDtrace support */
3818 rn
= "TraceControl2";
3819 /* Stop translation as we may have switched the execution mode */
3820 ctx
->bstate
= BS_STOP
;
3823 /* Stop translation as we may have switched the execution mode */
3824 ctx
->bstate
= BS_STOP
;
3825 // gen_helper_mtc0_usertracedata(arg); /* PDtrace support */
3826 rn
= "UserTraceData";
3827 /* Stop translation as we may have switched the execution mode */
3828 ctx
->bstate
= BS_STOP
;
3831 // gen_helper_mtc0_tracebpc(arg); /* PDtrace support */
3832 /* Stop translation as we may have switched the execution mode */
3833 ctx
->bstate
= BS_STOP
;
3844 gen_mtc0_store64(arg
, offsetof(CPUState
, CP0_DEPC
));
3854 gen_helper_mtc0_performance0(arg
);
3855 rn
= "Performance0";
3858 // gen_helper_mtc0_performance1(arg);
3859 rn
= "Performance1";
3862 // gen_helper_mtc0_performance2(arg);
3863 rn
= "Performance2";
3866 // gen_helper_mtc0_performance3(arg);
3867 rn
= "Performance3";
3870 // gen_helper_mtc0_performance4(arg);
3871 rn
= "Performance4";
3874 // gen_helper_mtc0_performance5(arg);
3875 rn
= "Performance5";
3878 // gen_helper_mtc0_performance6(arg);
3879 rn
= "Performance6";
3882 // gen_helper_mtc0_performance7(arg);
3883 rn
= "Performance7";
3909 gen_helper_mtc0_taglo(arg
);
3916 gen_helper_mtc0_datalo(arg
);
3929 gen_helper_mtc0_taghi(arg
);
3936 gen_helper_mtc0_datahi(arg
);
3947 gen_mtc0_store64(arg
, offsetof(CPUState
, CP0_ErrorEPC
));
3958 gen_mtc0_store32(arg
, offsetof(CPUState
, CP0_DESAVE
));
3964 /* Stop translation as we may have switched the execution mode */
3965 ctx
->bstate
= BS_STOP
;
3970 LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
3971 /* For simplicity assume that all writes can cause interrupts. */
3974 ctx
->bstate
= BS_STOP
;
3979 LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
3980 generate_exception(ctx
, EXCP_RI
);
3983 #if defined(TARGET_MIPS64)
3984 static void gen_dmfc0 (CPUState
*env
, DisasContext
*ctx
, TCGv arg
, int reg
, int sel
)
3986 const char *rn
= "invalid";
3989 check_insn(env
, ctx
, ISA_MIPS64
);
3995 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Index
));
3999 check_insn(env
, ctx
, ASE_MT
);
4000 gen_helper_mfc0_mvpcontrol(arg
);
4004 check_insn(env
, ctx
, ASE_MT
);
4005 gen_helper_mfc0_mvpconf0(arg
);
4009 check_insn(env
, ctx
, ASE_MT
);
4010 gen_helper_mfc0_mvpconf1(arg
);
4020 gen_helper_mfc0_random(arg
);
4024 check_insn(env
, ctx
, ASE_MT
);
4025 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEControl
));
4029 check_insn(env
, ctx
, ASE_MT
);
4030 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEConf0
));
4034 check_insn(env
, ctx
, ASE_MT
);
4035 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEConf1
));
4039 check_insn(env
, ctx
, ASE_MT
);
4040 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_YQMask
));
4044 check_insn(env
, ctx
, ASE_MT
);
4045 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_VPESchedule
));
4049 check_insn(env
, ctx
, ASE_MT
);
4050 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_VPEScheFBack
));
4051 rn
= "VPEScheFBack";
4054 check_insn(env
, ctx
, ASE_MT
);
4055 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEOpt
));
4065 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EntryLo0
));
4069 check_insn(env
, ctx
, ASE_MT
);
4070 gen_helper_mfc0_tcstatus(arg
);
4074 check_insn(env
, ctx
, ASE_MT
);
4075 gen_helper_mfc0_tcbind(arg
);
4079 check_insn(env
, ctx
, ASE_MT
);
4080 gen_helper_dmfc0_tcrestart(arg
);
4084 check_insn(env
, ctx
, ASE_MT
);
4085 gen_helper_dmfc0_tchalt(arg
);
4089 check_insn(env
, ctx
, ASE_MT
);
4090 gen_helper_dmfc0_tccontext(arg
);
4094 check_insn(env
, ctx
, ASE_MT
);
4095 gen_helper_dmfc0_tcschedule(arg
);
4099 check_insn(env
, ctx
, ASE_MT
);
4100 gen_helper_dmfc0_tcschefback(arg
);
4110 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EntryLo1
));
4120 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_Context
));
4124 // gen_helper_dmfc0_contextconfig(arg); /* SmartMIPS ASE */
4125 rn
= "ContextConfig";
4134 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_PageMask
));
4138 check_insn(env
, ctx
, ISA_MIPS32R2
);
4139 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_PageGrain
));
4149 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Wired
));
4153 check_insn(env
, ctx
, ISA_MIPS32R2
);
4154 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf0
));
4158 check_insn(env
, ctx
, ISA_MIPS32R2
);
4159 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf1
));
4163 check_insn(env
, ctx
, ISA_MIPS32R2
);
4164 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf2
));
4168 check_insn(env
, ctx
, ISA_MIPS32R2
);
4169 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf3
));
4173 check_insn(env
, ctx
, ISA_MIPS32R2
);
4174 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf4
));
4184 check_insn(env
, ctx
, ISA_MIPS32R2
);
4185 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_HWREna
));
4195 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_BadVAddr
));
4205 /* Mark as an IO operation because we read the time. */
4208 gen_helper_mfc0_count(arg
);
4211 ctx
->bstate
= BS_STOP
;
4215 /* 6,7 are implementation dependent */
4223 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EntryHi
));
4233 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Compare
));
4236 /* 6,7 are implementation dependent */
4244 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Status
));
4248 check_insn(env
, ctx
, ISA_MIPS32R2
);
4249 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_IntCtl
));
4253 check_insn(env
, ctx
, ISA_MIPS32R2
);
4254 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSCtl
));
4258 check_insn(env
, ctx
, ISA_MIPS32R2
);
4259 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSMap
));
4269 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Cause
));
4279 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EPC
));
4289 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_PRid
));
4293 check_insn(env
, ctx
, ISA_MIPS32R2
);
4294 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_EBase
));
4304 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config0
));
4308 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config1
));
4312 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config2
));
4316 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config3
));
4319 /* 6,7 are implementation dependent */
4321 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config6
));
4325 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config7
));
4335 gen_helper_dmfc0_lladdr(arg
);
4345 gen_helper_1i(dmfc0_watchlo
, arg
, sel
);
4355 gen_helper_1i(mfc0_watchhi
, arg
, sel
);
4365 check_insn(env
, ctx
, ISA_MIPS3
);
4366 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_XContext
));
4374 /* Officially reserved, but sel 0 is used for R1x000 framemask */
4377 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Framemask
));
4385 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
4386 rn
= "'Diagnostic"; /* implementation dependent */
4391 gen_helper_mfc0_debug(arg
); /* EJTAG support */
4395 // gen_helper_dmfc0_tracecontrol(arg); /* PDtrace support */
4396 rn
= "TraceControl";
4399 // gen_helper_dmfc0_tracecontrol2(arg); /* PDtrace support */
4400 rn
= "TraceControl2";
4403 // gen_helper_dmfc0_usertracedata(arg); /* PDtrace support */
4404 rn
= "UserTraceData";
4407 // gen_helper_dmfc0_tracebpc(arg); /* PDtrace support */
4418 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_DEPC
));
4428 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Performance0
));
4429 rn
= "Performance0";
4432 // gen_helper_dmfc0_performance1(arg);
4433 rn
= "Performance1";
4436 // gen_helper_dmfc0_performance2(arg);
4437 rn
= "Performance2";
4440 // gen_helper_dmfc0_performance3(arg);
4441 rn
= "Performance3";
4444 // gen_helper_dmfc0_performance4(arg);
4445 rn
= "Performance4";
4448 // gen_helper_dmfc0_performance5(arg);
4449 rn
= "Performance5";
4452 // gen_helper_dmfc0_performance6(arg);
4453 rn
= "Performance6";
4456 // gen_helper_dmfc0_performance7(arg);
4457 rn
= "Performance7";
4464 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
4471 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
4484 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_TagLo
));
4491 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_DataLo
));
4504 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_TagHi
));
4511 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_DataHi
));
4521 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_ErrorEPC
));
4532 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_DESAVE
));
4542 LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
4546 LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
4547 generate_exception(ctx
, EXCP_RI
);
4550 static void gen_dmtc0 (CPUState
*env
, DisasContext
*ctx
, TCGv arg
, int reg
, int sel
)
4552 const char *rn
= "invalid";
4555 check_insn(env
, ctx
, ISA_MIPS64
);
4564 gen_helper_mtc0_index(arg
);
4568 check_insn(env
, ctx
, ASE_MT
);
4569 gen_helper_mtc0_mvpcontrol(arg
);
4573 check_insn(env
, ctx
, ASE_MT
);
4578 check_insn(env
, ctx
, ASE_MT
);
4593 check_insn(env
, ctx
, ASE_MT
);
4594 gen_helper_mtc0_vpecontrol(arg
);
4598 check_insn(env
, ctx
, ASE_MT
);
4599 gen_helper_mtc0_vpeconf0(arg
);
4603 check_insn(env
, ctx
, ASE_MT
);
4604 gen_helper_mtc0_vpeconf1(arg
);
4608 check_insn(env
, ctx
, ASE_MT
);
4609 gen_helper_mtc0_yqmask(arg
);
4613 check_insn(env
, ctx
, ASE_MT
);
4614 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_VPESchedule
));
4618 check_insn(env
, ctx
, ASE_MT
);
4619 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_VPEScheFBack
));
4620 rn
= "VPEScheFBack";
4623 check_insn(env
, ctx
, ASE_MT
);
4624 gen_helper_mtc0_vpeopt(arg
);
4634 gen_helper_mtc0_entrylo0(arg
);
4638 check_insn(env
, ctx
, ASE_MT
);
4639 gen_helper_mtc0_tcstatus(arg
);
4643 check_insn(env
, ctx
, ASE_MT
);
4644 gen_helper_mtc0_tcbind(arg
);
4648 check_insn(env
, ctx
, ASE_MT
);
4649 gen_helper_mtc0_tcrestart(arg
);
4653 check_insn(env
, ctx
, ASE_MT
);
4654 gen_helper_mtc0_tchalt(arg
);
4658 check_insn(env
, ctx
, ASE_MT
);
4659 gen_helper_mtc0_tccontext(arg
);
4663 check_insn(env
, ctx
, ASE_MT
);
4664 gen_helper_mtc0_tcschedule(arg
);
4668 check_insn(env
, ctx
, ASE_MT
);
4669 gen_helper_mtc0_tcschefback(arg
);
4679 gen_helper_mtc0_entrylo1(arg
);
4689 gen_helper_mtc0_context(arg
);
4693 // gen_helper_mtc0_contextconfig(arg); /* SmartMIPS ASE */
4694 rn
= "ContextConfig";
4703 gen_helper_mtc0_pagemask(arg
);
4707 check_insn(env
, ctx
, ISA_MIPS32R2
);
4708 gen_helper_mtc0_pagegrain(arg
);
4718 gen_helper_mtc0_wired(arg
);
4722 check_insn(env
, ctx
, ISA_MIPS32R2
);
4723 gen_helper_mtc0_srsconf0(arg
);
4727 check_insn(env
, ctx
, ISA_MIPS32R2
);
4728 gen_helper_mtc0_srsconf1(arg
);
4732 check_insn(env
, ctx
, ISA_MIPS32R2
);
4733 gen_helper_mtc0_srsconf2(arg
);
4737 check_insn(env
, ctx
, ISA_MIPS32R2
);
4738 gen_helper_mtc0_srsconf3(arg
);
4742 check_insn(env
, ctx
, ISA_MIPS32R2
);
4743 gen_helper_mtc0_srsconf4(arg
);
4753 check_insn(env
, ctx
, ISA_MIPS32R2
);
4754 gen_helper_mtc0_hwrena(arg
);
4768 gen_helper_mtc0_count(arg
);
4771 /* 6,7 are implementation dependent */
4775 /* Stop translation as we may have switched the execution mode */
4776 ctx
->bstate
= BS_STOP
;
4781 gen_helper_mtc0_entryhi(arg
);
4791 gen_helper_mtc0_compare(arg
);
4794 /* 6,7 are implementation dependent */
4798 /* Stop translation as we may have switched the execution mode */
4799 ctx
->bstate
= BS_STOP
;
4804 save_cpu_state(ctx
, 1);
4805 gen_helper_mtc0_status(arg
);
4806 /* BS_STOP isn't good enough here, hflags may have changed. */
4807 gen_save_pc(ctx
->pc
+ 4);
4808 ctx
->bstate
= BS_EXCP
;
4812 check_insn(env
, ctx
, ISA_MIPS32R2
);
4813 gen_helper_mtc0_intctl(arg
);
4814 /* Stop translation as we may have switched the execution mode */
4815 ctx
->bstate
= BS_STOP
;
4819 check_insn(env
, ctx
, ISA_MIPS32R2
);
4820 gen_helper_mtc0_srsctl(arg
);
4821 /* Stop translation as we may have switched the execution mode */
4822 ctx
->bstate
= BS_STOP
;
4826 check_insn(env
, ctx
, ISA_MIPS32R2
);
4827 gen_mtc0_store32(arg
, offsetof(CPUState
, CP0_SRSMap
));
4828 /* Stop translation as we may have switched the execution mode */
4829 ctx
->bstate
= BS_STOP
;
4839 save_cpu_state(ctx
, 1);
4840 gen_helper_mtc0_cause(arg
);
4850 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EPC
));
4864 check_insn(env
, ctx
, ISA_MIPS32R2
);
4865 gen_helper_mtc0_ebase(arg
);
4875 gen_helper_mtc0_config0(arg
);
4877 /* Stop translation as we may have switched the execution mode */
4878 ctx
->bstate
= BS_STOP
;
4881 /* ignored, read only */
4885 gen_helper_mtc0_config2(arg
);
4887 /* Stop translation as we may have switched the execution mode */
4888 ctx
->bstate
= BS_STOP
;
4894 /* 6,7 are implementation dependent */
4896 rn
= "Invalid config selector";
4903 gen_helper_mtc0_lladdr(arg
);
4913 gen_helper_1i(mtc0_watchlo
, arg
, sel
);
4923 gen_helper_1i(mtc0_watchhi
, arg
, sel
);
4933 check_insn(env
, ctx
, ISA_MIPS3
);
4934 gen_helper_mtc0_xcontext(arg
);
4942 /* Officially reserved, but sel 0 is used for R1x000 framemask */
4945 gen_helper_mtc0_framemask(arg
);
4954 rn
= "Diagnostic"; /* implementation dependent */
4959 gen_helper_mtc0_debug(arg
); /* EJTAG support */
4960 /* BS_STOP isn't good enough here, hflags may have changed. */
4961 gen_save_pc(ctx
->pc
+ 4);
4962 ctx
->bstate
= BS_EXCP
;
4966 // gen_helper_mtc0_tracecontrol(arg); /* PDtrace support */
4967 /* Stop translation as we may have switched the execution mode */
4968 ctx
->bstate
= BS_STOP
;
4969 rn
= "TraceControl";
4972 // gen_helper_mtc0_tracecontrol2(arg); /* PDtrace support */
4973 /* Stop translation as we may have switched the execution mode */
4974 ctx
->bstate
= BS_STOP
;
4975 rn
= "TraceControl2";
4978 // gen_helper_mtc0_usertracedata(arg); /* PDtrace support */
4979 /* Stop translation as we may have switched the execution mode */
4980 ctx
->bstate
= BS_STOP
;
4981 rn
= "UserTraceData";
4984 // gen_helper_mtc0_tracebpc(arg); /* PDtrace support */
4985 /* Stop translation as we may have switched the execution mode */
4986 ctx
->bstate
= BS_STOP
;
4997 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_DEPC
));
5007 gen_helper_mtc0_performance0(arg
);
5008 rn
= "Performance0";
5011 // gen_helper_mtc0_performance1(arg);
5012 rn
= "Performance1";
5015 // gen_helper_mtc0_performance2(arg);
5016 rn
= "Performance2";
5019 // gen_helper_mtc0_performance3(arg);
5020 rn
= "Performance3";
5023 // gen_helper_mtc0_performance4(arg);
5024 rn
= "Performance4";
5027 // gen_helper_mtc0_performance5(arg);
5028 rn
= "Performance5";
5031 // gen_helper_mtc0_performance6(arg);
5032 rn
= "Performance6";
5035 // gen_helper_mtc0_performance7(arg);
5036 rn
= "Performance7";
5062 gen_helper_mtc0_taglo(arg
);
5069 gen_helper_mtc0_datalo(arg
);
5082 gen_helper_mtc0_taghi(arg
);
5089 gen_helper_mtc0_datahi(arg
);
5100 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_ErrorEPC
));
5111 gen_mtc0_store32(arg
, offsetof(CPUState
, CP0_DESAVE
));
5117 /* Stop translation as we may have switched the execution mode */
5118 ctx
->bstate
= BS_STOP
;
5123 LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
5124 /* For simplicity assume that all writes can cause interrupts. */
5127 ctx
->bstate
= BS_STOP
;
5132 LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
5133 generate_exception(ctx
, EXCP_RI
);
5135 #endif /* TARGET_MIPS64 */
5137 static void gen_mftr(CPUState
*env
, DisasContext
*ctx
, int rt
, int rd
,
5138 int u
, int sel
, int h
)
5140 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
5141 TCGv t0
= tcg_temp_local_new();
5143 if ((env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) == 0 &&
5144 ((env
->tcs
[other_tc
].CP0_TCBind
& (0xf << CP0TCBd_CurVPE
)) !=
5145 (env
->active_tc
.CP0_TCBind
& (0xf << CP0TCBd_CurVPE
))))
5146 tcg_gen_movi_tl(t0
, -1);
5147 else if ((env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
)) >
5148 (env
->mvp
->CP0_MVPConf0
& (0xff << CP0MVPC0_PTC
)))
5149 tcg_gen_movi_tl(t0
, -1);
5155 gen_helper_mftc0_tcstatus(t0
);
5158 gen_helper_mftc0_tcbind(t0
);
5161 gen_helper_mftc0_tcrestart(t0
);
5164 gen_helper_mftc0_tchalt(t0
);
5167 gen_helper_mftc0_tccontext(t0
);
5170 gen_helper_mftc0_tcschedule(t0
);
5173 gen_helper_mftc0_tcschefback(t0
);
5176 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5183 gen_helper_mftc0_entryhi(t0
);
5186 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5192 gen_helper_mftc0_status(t0
);
5195 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5201 gen_helper_mftc0_debug(t0
);
5204 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5209 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5211 } else switch (sel
) {
5212 /* GPR registers. */
5214 gen_helper_1i(mftgpr
, t0
, rt
);
5216 /* Auxiliary CPU registers */
5220 gen_helper_1i(mftlo
, t0
, 0);
5223 gen_helper_1i(mfthi
, t0
, 0);
5226 gen_helper_1i(mftacx
, t0
, 0);
5229 gen_helper_1i(mftlo
, t0
, 1);
5232 gen_helper_1i(mfthi
, t0
, 1);
5235 gen_helper_1i(mftacx
, t0
, 1);
5238 gen_helper_1i(mftlo
, t0
, 2);
5241 gen_helper_1i(mfthi
, t0
, 2);
5244 gen_helper_1i(mftacx
, t0
, 2);
5247 gen_helper_1i(mftlo
, t0
, 3);
5250 gen_helper_1i(mfthi
, t0
, 3);
5253 gen_helper_1i(mftacx
, t0
, 3);
5256 gen_helper_mftdsp(t0
);
5262 /* Floating point (COP1). */
5264 /* XXX: For now we support only a single FPU context. */
5266 TCGv_i32 fp0
= tcg_temp_new_i32();
5268 gen_load_fpr32(fp0
, rt
);
5269 tcg_gen_ext_i32_tl(t0
, fp0
);
5270 tcg_temp_free_i32(fp0
);
5272 TCGv_i32 fp0
= tcg_temp_new_i32();
5274 gen_load_fpr32h(fp0
, rt
);
5275 tcg_gen_ext_i32_tl(t0
, fp0
);
5276 tcg_temp_free_i32(fp0
);
5280 /* XXX: For now we support only a single FPU context. */
5281 gen_helper_1i(cfc1
, t0
, rt
);
5283 /* COP2: Not implemented. */
5290 LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt
, u
, sel
, h
);
5291 gen_store_gpr(t0
, rd
);
5297 LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt
, u
, sel
, h
);
5298 generate_exception(ctx
, EXCP_RI
);
5301 static void gen_mttr(CPUState
*env
, DisasContext
*ctx
, int rd
, int rt
,
5302 int u
, int sel
, int h
)
5304 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
5305 TCGv t0
= tcg_temp_local_new();
5307 gen_load_gpr(t0
, rt
);
5308 if ((env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) == 0 &&
5309 ((env
->tcs
[other_tc
].CP0_TCBind
& (0xf << CP0TCBd_CurVPE
)) !=
5310 (env
->active_tc
.CP0_TCBind
& (0xf << CP0TCBd_CurVPE
))))
5312 else if ((env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
)) >
5313 (env
->mvp
->CP0_MVPConf0
& (0xff << CP0MVPC0_PTC
)))
5320 gen_helper_mttc0_tcstatus(t0
);
5323 gen_helper_mttc0_tcbind(t0
);
5326 gen_helper_mttc0_tcrestart(t0
);
5329 gen_helper_mttc0_tchalt(t0
);
5332 gen_helper_mttc0_tccontext(t0
);
5335 gen_helper_mttc0_tcschedule(t0
);
5338 gen_helper_mttc0_tcschefback(t0
);
5341 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5348 gen_helper_mttc0_entryhi(t0
);
5351 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5357 gen_helper_mttc0_status(t0
);
5360 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5366 gen_helper_mttc0_debug(t0
);
5369 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5374 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5376 } else switch (sel
) {
5377 /* GPR registers. */
5379 gen_helper_1i(mttgpr
, t0
, rd
);
5381 /* Auxiliary CPU registers */
5385 gen_helper_1i(mttlo
, t0
, 0);
5388 gen_helper_1i(mtthi
, t0
, 0);
5391 gen_helper_1i(mttacx
, t0
, 0);
5394 gen_helper_1i(mttlo
, t0
, 1);
5397 gen_helper_1i(mtthi
, t0
, 1);
5400 gen_helper_1i(mttacx
, t0
, 1);
5403 gen_helper_1i(mttlo
, t0
, 2);
5406 gen_helper_1i(mtthi
, t0
, 2);
5409 gen_helper_1i(mttacx
, t0
, 2);
5412 gen_helper_1i(mttlo
, t0
, 3);
5415 gen_helper_1i(mtthi
, t0
, 3);
5418 gen_helper_1i(mttacx
, t0
, 3);
5421 gen_helper_mttdsp(t0
);
5427 /* Floating point (COP1). */
5429 /* XXX: For now we support only a single FPU context. */
5431 TCGv_i32 fp0
= tcg_temp_new_i32();
5433 tcg_gen_trunc_tl_i32(fp0
, t0
);
5434 gen_store_fpr32(fp0
, rd
);
5435 tcg_temp_free_i32(fp0
);
5437 TCGv_i32 fp0
= tcg_temp_new_i32();
5439 tcg_gen_trunc_tl_i32(fp0
, t0
);
5440 gen_store_fpr32h(fp0
, rd
);
5441 tcg_temp_free_i32(fp0
);
5445 /* XXX: For now we support only a single FPU context. */
5446 gen_helper_1i(ctc1
, t0
, rd
);
5448 /* COP2: Not implemented. */
5455 LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd
, u
, sel
, h
);
5461 LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd
, u
, sel
, h
);
5462 generate_exception(ctx
, EXCP_RI
);
5465 static void gen_cp0 (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
, int rt
, int rd
)
5467 const char *opn
= "ldst";
5475 gen_mfc0(env
, ctx
, cpu_gpr
[rt
], rd
, ctx
->opcode
& 0x7);
5480 TCGv t0
= tcg_temp_new();
5482 gen_load_gpr(t0
, rt
);
5483 gen_mtc0(env
, ctx
, t0
, rd
, ctx
->opcode
& 0x7);
5488 #if defined(TARGET_MIPS64)
5490 check_insn(env
, ctx
, ISA_MIPS3
);
5495 gen_dmfc0(env
, ctx
, cpu_gpr
[rt
], rd
, ctx
->opcode
& 0x7);
5499 check_insn(env
, ctx
, ISA_MIPS3
);
5501 TCGv t0
= tcg_temp_new();
5503 gen_load_gpr(t0
, rt
);
5504 gen_dmtc0(env
, ctx
, t0
, rd
, ctx
->opcode
& 0x7);
5511 check_insn(env
, ctx
, ASE_MT
);
5516 gen_mftr(env
, ctx
, rt
, rd
, (ctx
->opcode
>> 5) & 1,
5517 ctx
->opcode
& 0x7, (ctx
->opcode
>> 4) & 1);
5521 check_insn(env
, ctx
, ASE_MT
);
5522 gen_mttr(env
, ctx
, rd
, rt
, (ctx
->opcode
>> 5) & 1,
5523 ctx
->opcode
& 0x7, (ctx
->opcode
>> 4) & 1);
5528 if (!env
->tlb
->helper_tlbwi
)
5534 if (!env
->tlb
->helper_tlbwr
)
5540 if (!env
->tlb
->helper_tlbp
)
5546 if (!env
->tlb
->helper_tlbr
)
5552 check_insn(env
, ctx
, ISA_MIPS2
);
5554 ctx
->bstate
= BS_EXCP
;
5558 check_insn(env
, ctx
, ISA_MIPS32
);
5559 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
5561 generate_exception(ctx
, EXCP_RI
);
5564 ctx
->bstate
= BS_EXCP
;
5569 check_insn(env
, ctx
, ISA_MIPS3
| ISA_MIPS32
);
5570 /* If we get an exception, we want to restart at next instruction */
5572 save_cpu_state(ctx
, 1);
5575 ctx
->bstate
= BS_EXCP
;
5580 generate_exception(ctx
, EXCP_RI
);
5583 MIPS_DEBUG("%s %s %d", opn
, regnames
[rt
], rd
);
5585 #endif /* !CONFIG_USER_ONLY */
5587 /* CP1 Branches (before delay slot) */
5588 static void gen_compute_branch1 (CPUState
*env
, DisasContext
*ctx
, uint32_t op
,
5589 int32_t cc
, int32_t offset
)
5591 target_ulong btarget
;
5592 const char *opn
= "cp1 cond branch";
5593 TCGv_i32 t0
= tcg_temp_new_i32();
5596 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
5598 btarget
= ctx
->pc
+ 4 + offset
;
5602 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5603 tcg_gen_not_i32(t0
, t0
);
5604 tcg_gen_andi_i32(t0
, t0
, 1);
5605 tcg_gen_extu_i32_tl(bcond
, t0
);
5609 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5610 tcg_gen_not_i32(t0
, t0
);
5611 tcg_gen_andi_i32(t0
, t0
, 1);
5612 tcg_gen_extu_i32_tl(bcond
, t0
);
5616 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5617 tcg_gen_andi_i32(t0
, t0
, 1);
5618 tcg_gen_extu_i32_tl(bcond
, t0
);
5622 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5623 tcg_gen_andi_i32(t0
, t0
, 1);
5624 tcg_gen_extu_i32_tl(bcond
, t0
);
5627 ctx
->hflags
|= MIPS_HFLAG_BL
;
5631 TCGv_i32 t1
= tcg_temp_new_i32();
5632 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5633 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+1));
5634 tcg_gen_nor_i32(t0
, t0
, t1
);
5635 tcg_temp_free_i32(t1
);
5636 tcg_gen_andi_i32(t0
, t0
, 1);
5637 tcg_gen_extu_i32_tl(bcond
, t0
);
5643 TCGv_i32 t1
= tcg_temp_new_i32();
5644 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5645 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+1));
5646 tcg_gen_or_i32(t0
, t0
, t1
);
5647 tcg_temp_free_i32(t1
);
5648 tcg_gen_andi_i32(t0
, t0
, 1);
5649 tcg_gen_extu_i32_tl(bcond
, t0
);
5655 TCGv_i32 t1
= tcg_temp_new_i32();
5656 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5657 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+1));
5658 tcg_gen_or_i32(t0
, t0
, t1
);
5659 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+2));
5660 tcg_gen_or_i32(t0
, t0
, t1
);
5661 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+3));
5662 tcg_gen_nor_i32(t0
, t0
, t1
);
5663 tcg_temp_free_i32(t1
);
5664 tcg_gen_andi_i32(t0
, t0
, 1);
5665 tcg_gen_extu_i32_tl(bcond
, t0
);
5671 TCGv_i32 t1
= tcg_temp_new_i32();
5672 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5673 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+1));
5674 tcg_gen_or_i32(t0
, t0
, t1
);
5675 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+2));
5676 tcg_gen_or_i32(t0
, t0
, t1
);
5677 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+3));
5678 tcg_gen_or_i32(t0
, t0
, t1
);
5679 tcg_temp_free_i32(t1
);
5680 tcg_gen_andi_i32(t0
, t0
, 1);
5681 tcg_gen_extu_i32_tl(bcond
, t0
);
5685 ctx
->hflags
|= MIPS_HFLAG_BC
;
5689 generate_exception (ctx
, EXCP_RI
);
5692 MIPS_DEBUG("%s: cond %02x target " TARGET_FMT_lx
, opn
,
5693 ctx
->hflags
, btarget
);
5694 ctx
->btarget
= btarget
;
5697 tcg_temp_free_i32(t0
);
5700 /* Coprocessor 1 (FPU) */
5702 #define FOP(func, fmt) (((fmt) << 21) | (func))
5704 static void gen_cp1 (DisasContext
*ctx
, uint32_t opc
, int rt
, int fs
)
5706 const char *opn
= "cp1 move";
5707 TCGv t0
= tcg_temp_new();
5712 TCGv_i32 fp0
= tcg_temp_new_i32();
5714 gen_load_fpr32(fp0
, fs
);
5715 tcg_gen_ext_i32_tl(t0
, fp0
);
5716 tcg_temp_free_i32(fp0
);
5718 gen_store_gpr(t0
, rt
);
5722 gen_load_gpr(t0
, rt
);
5724 TCGv_i32 fp0
= tcg_temp_new_i32();
5726 tcg_gen_trunc_tl_i32(fp0
, t0
);
5727 gen_store_fpr32(fp0
, fs
);
5728 tcg_temp_free_i32(fp0
);
5733 gen_helper_1i(cfc1
, t0
, fs
);
5734 gen_store_gpr(t0
, rt
);
5738 gen_load_gpr(t0
, rt
);
5739 gen_helper_1i(ctc1
, t0
, fs
);
5742 #if defined(TARGET_MIPS64)
5744 gen_load_fpr64(ctx
, t0
, fs
);
5745 gen_store_gpr(t0
, rt
);
5749 gen_load_gpr(t0
, rt
);
5750 gen_store_fpr64(ctx
, t0
, fs
);
5756 TCGv_i32 fp0
= tcg_temp_new_i32();
5758 gen_load_fpr32h(fp0
, fs
);
5759 tcg_gen_ext_i32_tl(t0
, fp0
);
5760 tcg_temp_free_i32(fp0
);
5762 gen_store_gpr(t0
, rt
);
5766 gen_load_gpr(t0
, rt
);
5768 TCGv_i32 fp0
= tcg_temp_new_i32();
5770 tcg_gen_trunc_tl_i32(fp0
, t0
);
5771 gen_store_fpr32h(fp0
, fs
);
5772 tcg_temp_free_i32(fp0
);
5778 generate_exception (ctx
, EXCP_RI
);
5781 MIPS_DEBUG("%s %s %s", opn
, regnames
[rt
], fregnames
[fs
]);
5787 static void gen_movci (DisasContext
*ctx
, int rd
, int rs
, int cc
, int tf
)
5803 l1
= gen_new_label();
5804 t0
= tcg_temp_new_i32();
5805 tcg_gen_andi_i32(t0
, fpu_fcr31
, 1 << get_fp_bit(cc
));
5806 tcg_gen_brcondi_i32(cond
, t0
, 0, l1
);
5807 tcg_temp_free_i32(t0
);
5809 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
5811 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
5816 static inline void gen_movcf_s (int fs
, int fd
, int cc
, int tf
)
5819 TCGv_i32 t0
= tcg_temp_new_i32();
5820 int l1
= gen_new_label();
5827 tcg_gen_andi_i32(t0
, fpu_fcr31
, 1 << get_fp_bit(cc
));
5828 tcg_gen_brcondi_i32(cond
, t0
, 0, l1
);
5829 gen_load_fpr32(t0
, fs
);
5830 gen_store_fpr32(t0
, fd
);
5832 tcg_temp_free_i32(t0
);
5835 static inline void gen_movcf_d (DisasContext
*ctx
, int fs
, int fd
, int cc
, int tf
)
5838 TCGv_i32 t0
= tcg_temp_new_i32();
5840 int l1
= gen_new_label();
5847 tcg_gen_andi_i32(t0
, fpu_fcr31
, 1 << get_fp_bit(cc
));
5848 tcg_gen_brcondi_i32(cond
, t0
, 0, l1
);
5849 tcg_temp_free_i32(t0
);
5850 fp0
= tcg_temp_new_i64();
5851 gen_load_fpr64(ctx
, fp0
, fs
);
5852 gen_store_fpr64(ctx
, fp0
, fd
);
5853 tcg_temp_free_i64(fp0
);
5857 static inline void gen_movcf_ps (int fs
, int fd
, int cc
, int tf
)
5860 TCGv_i32 t0
= tcg_temp_new_i32();
5861 int l1
= gen_new_label();
5862 int l2
= gen_new_label();
5869 tcg_gen_andi_i32(t0
, fpu_fcr31
, 1 << get_fp_bit(cc
));
5870 tcg_gen_brcondi_i32(cond
, t0
, 0, l1
);
5871 gen_load_fpr32(t0
, fs
);
5872 gen_store_fpr32(t0
, fd
);
5875 tcg_gen_andi_i32(t0
, fpu_fcr31
, 1 << get_fp_bit(cc
+1));
5876 tcg_gen_brcondi_i32(cond
, t0
, 0, l2
);
5877 gen_load_fpr32h(t0
, fs
);
5878 gen_store_fpr32h(t0
, fd
);
5879 tcg_temp_free_i32(t0
);
5884 static void gen_farith (DisasContext
*ctx
, uint32_t op1
,
5885 int ft
, int fs
, int fd
, int cc
)
5887 const char *opn
= "farith";
5888 const char *condnames
[] = {
5906 const char *condnames_abs
[] = {
5924 enum { BINOP
, CMPOP
, OTHEROP
} optype
= OTHEROP
;
5925 uint32_t func
= ctx
->opcode
& 0x3f;
5927 switch (ctx
->opcode
& FOP(0x3f, 0x1f)) {
5930 TCGv_i32 fp0
= tcg_temp_new_i32();
5931 TCGv_i32 fp1
= tcg_temp_new_i32();
5933 gen_load_fpr32(fp0
, fs
);
5934 gen_load_fpr32(fp1
, ft
);
5935 gen_helper_float_add_s(fp0
, fp0
, fp1
);
5936 tcg_temp_free_i32(fp1
);
5937 gen_store_fpr32(fp0
, fd
);
5938 tcg_temp_free_i32(fp0
);
5945 TCGv_i32 fp0
= tcg_temp_new_i32();
5946 TCGv_i32 fp1
= tcg_temp_new_i32();
5948 gen_load_fpr32(fp0
, fs
);
5949 gen_load_fpr32(fp1
, ft
);
5950 gen_helper_float_sub_s(fp0
, fp0
, fp1
);
5951 tcg_temp_free_i32(fp1
);
5952 gen_store_fpr32(fp0
, fd
);
5953 tcg_temp_free_i32(fp0
);
5960 TCGv_i32 fp0
= tcg_temp_new_i32();
5961 TCGv_i32 fp1
= tcg_temp_new_i32();
5963 gen_load_fpr32(fp0
, fs
);
5964 gen_load_fpr32(fp1
, ft
);
5965 gen_helper_float_mul_s(fp0
, fp0
, fp1
);
5966 tcg_temp_free_i32(fp1
);
5967 gen_store_fpr32(fp0
, fd
);
5968 tcg_temp_free_i32(fp0
);
5975 TCGv_i32 fp0
= tcg_temp_new_i32();
5976 TCGv_i32 fp1
= tcg_temp_new_i32();
5978 gen_load_fpr32(fp0
, fs
);
5979 gen_load_fpr32(fp1
, ft
);
5980 gen_helper_float_div_s(fp0
, fp0
, fp1
);
5981 tcg_temp_free_i32(fp1
);
5982 gen_store_fpr32(fp0
, fd
);
5983 tcg_temp_free_i32(fp0
);
5990 TCGv_i32 fp0
= tcg_temp_new_i32();
5992 gen_load_fpr32(fp0
, fs
);
5993 gen_helper_float_sqrt_s(fp0
, fp0
);
5994 gen_store_fpr32(fp0
, fd
);
5995 tcg_temp_free_i32(fp0
);
6001 TCGv_i32 fp0
= tcg_temp_new_i32();
6003 gen_load_fpr32(fp0
, fs
);
6004 gen_helper_float_abs_s(fp0
, fp0
);
6005 gen_store_fpr32(fp0
, fd
);
6006 tcg_temp_free_i32(fp0
);
6012 TCGv_i32 fp0
= tcg_temp_new_i32();
6014 gen_load_fpr32(fp0
, fs
);
6015 gen_store_fpr32(fp0
, fd
);
6016 tcg_temp_free_i32(fp0
);
6022 TCGv_i32 fp0
= tcg_temp_new_i32();
6024 gen_load_fpr32(fp0
, fs
);
6025 gen_helper_float_chs_s(fp0
, fp0
);
6026 gen_store_fpr32(fp0
, fd
);
6027 tcg_temp_free_i32(fp0
);
6032 check_cp1_64bitmode(ctx
);
6034 TCGv_i32 fp32
= tcg_temp_new_i32();
6035 TCGv_i64 fp64
= tcg_temp_new_i64();
6037 gen_load_fpr32(fp32
, fs
);
6038 gen_helper_float_roundl_s(fp64
, fp32
);
6039 tcg_temp_free_i32(fp32
);
6040 gen_store_fpr64(ctx
, fp64
, fd
);
6041 tcg_temp_free_i64(fp64
);
6046 check_cp1_64bitmode(ctx
);
6048 TCGv_i32 fp32
= tcg_temp_new_i32();
6049 TCGv_i64 fp64
= tcg_temp_new_i64();
6051 gen_load_fpr32(fp32
, fs
);
6052 gen_helper_float_truncl_s(fp64
, fp32
);
6053 tcg_temp_free_i32(fp32
);
6054 gen_store_fpr64(ctx
, fp64
, fd
);
6055 tcg_temp_free_i64(fp64
);
6060 check_cp1_64bitmode(ctx
);
6062 TCGv_i32 fp32
= tcg_temp_new_i32();
6063 TCGv_i64 fp64
= tcg_temp_new_i64();
6065 gen_load_fpr32(fp32
, fs
);
6066 gen_helper_float_ceill_s(fp64
, fp32
);
6067 tcg_temp_free_i32(fp32
);
6068 gen_store_fpr64(ctx
, fp64
, fd
);
6069 tcg_temp_free_i64(fp64
);
6074 check_cp1_64bitmode(ctx
);
6076 TCGv_i32 fp32
= tcg_temp_new_i32();
6077 TCGv_i64 fp64
= tcg_temp_new_i64();
6079 gen_load_fpr32(fp32
, fs
);
6080 gen_helper_float_floorl_s(fp64
, fp32
);
6081 tcg_temp_free_i32(fp32
);
6082 gen_store_fpr64(ctx
, fp64
, fd
);
6083 tcg_temp_free_i64(fp64
);
6089 TCGv_i32 fp0
= tcg_temp_new_i32();
6091 gen_load_fpr32(fp0
, fs
);
6092 gen_helper_float_roundw_s(fp0
, fp0
);
6093 gen_store_fpr32(fp0
, fd
);
6094 tcg_temp_free_i32(fp0
);
6100 TCGv_i32 fp0
= tcg_temp_new_i32();
6102 gen_load_fpr32(fp0
, fs
);
6103 gen_helper_float_truncw_s(fp0
, fp0
);
6104 gen_store_fpr32(fp0
, fd
);
6105 tcg_temp_free_i32(fp0
);
6111 TCGv_i32 fp0
= tcg_temp_new_i32();
6113 gen_load_fpr32(fp0
, fs
);
6114 gen_helper_float_ceilw_s(fp0
, fp0
);
6115 gen_store_fpr32(fp0
, fd
);
6116 tcg_temp_free_i32(fp0
);
6122 TCGv_i32 fp0
= tcg_temp_new_i32();
6124 gen_load_fpr32(fp0
, fs
);
6125 gen_helper_float_floorw_s(fp0
, fp0
);
6126 gen_store_fpr32(fp0
, fd
);
6127 tcg_temp_free_i32(fp0
);
6132 gen_movcf_s(fs
, fd
, (ft
>> 2) & 0x7, ft
& 0x1);
6137 int l1
= gen_new_label();
6141 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[ft
], 0, l1
);
6143 fp0
= tcg_temp_new_i32();
6144 gen_load_fpr32(fp0
, fs
);
6145 gen_store_fpr32(fp0
, fd
);
6146 tcg_temp_free_i32(fp0
);
6153 int l1
= gen_new_label();
6157 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[ft
], 0, l1
);
6158 fp0
= tcg_temp_new_i32();
6159 gen_load_fpr32(fp0
, fs
);
6160 gen_store_fpr32(fp0
, fd
);
6161 tcg_temp_free_i32(fp0
);
6170 TCGv_i32 fp0
= tcg_temp_new_i32();
6172 gen_load_fpr32(fp0
, fs
);
6173 gen_helper_float_recip_s(fp0
, fp0
);
6174 gen_store_fpr32(fp0
, fd
);
6175 tcg_temp_free_i32(fp0
);
6182 TCGv_i32 fp0
= tcg_temp_new_i32();
6184 gen_load_fpr32(fp0
, fs
);
6185 gen_helper_float_rsqrt_s(fp0
, fp0
);
6186 gen_store_fpr32(fp0
, fd
);
6187 tcg_temp_free_i32(fp0
);
6192 check_cp1_64bitmode(ctx
);
6194 TCGv_i32 fp0
= tcg_temp_new_i32();
6195 TCGv_i32 fp1
= tcg_temp_new_i32();
6197 gen_load_fpr32(fp0
, fs
);
6198 gen_load_fpr32(fp1
, fd
);
6199 gen_helper_float_recip2_s(fp0
, fp0
, fp1
);
6200 tcg_temp_free_i32(fp1
);
6201 gen_store_fpr32(fp0
, fd
);
6202 tcg_temp_free_i32(fp0
);
6207 check_cp1_64bitmode(ctx
);
6209 TCGv_i32 fp0
= tcg_temp_new_i32();
6211 gen_load_fpr32(fp0
, fs
);
6212 gen_helper_float_recip1_s(fp0
, fp0
);
6213 gen_store_fpr32(fp0
, fd
);
6214 tcg_temp_free_i32(fp0
);
6219 check_cp1_64bitmode(ctx
);
6221 TCGv_i32 fp0
= tcg_temp_new_i32();
6223 gen_load_fpr32(fp0
, fs
);
6224 gen_helper_float_rsqrt1_s(fp0
, fp0
);
6225 gen_store_fpr32(fp0
, fd
);
6226 tcg_temp_free_i32(fp0
);
6231 check_cp1_64bitmode(ctx
);
6233 TCGv_i32 fp0
= tcg_temp_new_i32();
6234 TCGv_i32 fp1
= tcg_temp_new_i32();
6236 gen_load_fpr32(fp0
, fs
);
6237 gen_load_fpr32(fp1
, ft
);
6238 gen_helper_float_rsqrt2_s(fp0
, fp0
, fp1
);
6239 tcg_temp_free_i32(fp1
);
6240 gen_store_fpr32(fp0
, fd
);
6241 tcg_temp_free_i32(fp0
);
6246 check_cp1_registers(ctx
, fd
);
6248 TCGv_i32 fp32
= tcg_temp_new_i32();
6249 TCGv_i64 fp64
= tcg_temp_new_i64();
6251 gen_load_fpr32(fp32
, fs
);
6252 gen_helper_float_cvtd_s(fp64
, fp32
);
6253 tcg_temp_free_i32(fp32
);
6254 gen_store_fpr64(ctx
, fp64
, fd
);
6255 tcg_temp_free_i64(fp64
);
6261 TCGv_i32 fp0
= tcg_temp_new_i32();
6263 gen_load_fpr32(fp0
, fs
);
6264 gen_helper_float_cvtw_s(fp0
, fp0
);
6265 gen_store_fpr32(fp0
, fd
);
6266 tcg_temp_free_i32(fp0
);
6271 check_cp1_64bitmode(ctx
);
6273 TCGv_i32 fp32
= tcg_temp_new_i32();
6274 TCGv_i64 fp64
= tcg_temp_new_i64();
6276 gen_load_fpr32(fp32
, fs
);
6277 gen_helper_float_cvtl_s(fp64
, fp32
);
6278 tcg_temp_free_i32(fp32
);
6279 gen_store_fpr64(ctx
, fp64
, fd
);
6280 tcg_temp_free_i64(fp64
);
6285 check_cp1_64bitmode(ctx
);
6287 TCGv_i64 fp64
= tcg_temp_new_i64();
6288 TCGv_i32 fp32_0
= tcg_temp_new_i32();
6289 TCGv_i32 fp32_1
= tcg_temp_new_i32();
6291 gen_load_fpr32(fp32_0
, fs
);
6292 gen_load_fpr32(fp32_1
, ft
);
6293 tcg_gen_concat_i32_i64(fp64
, fp32_0
, fp32_1
);
6294 tcg_temp_free_i32(fp32_1
);
6295 tcg_temp_free_i32(fp32_0
);
6296 gen_store_fpr64(ctx
, fp64
, fd
);
6297 tcg_temp_free_i64(fp64
);
6318 TCGv_i32 fp0
= tcg_temp_new_i32();
6319 TCGv_i32 fp1
= tcg_temp_new_i32();
6321 gen_load_fpr32(fp0
, fs
);
6322 gen_load_fpr32(fp1
, ft
);
6323 if (ctx
->opcode
& (1 << 6)) {
6325 gen_cmpabs_s(func
-48, fp0
, fp1
, cc
);
6326 opn
= condnames_abs
[func
-48];
6328 gen_cmp_s(func
-48, fp0
, fp1
, cc
);
6329 opn
= condnames
[func
-48];
6331 tcg_temp_free_i32(fp0
);
6332 tcg_temp_free_i32(fp1
);
6336 check_cp1_registers(ctx
, fs
| ft
| fd
);
6338 TCGv_i64 fp0
= tcg_temp_new_i64();
6339 TCGv_i64 fp1
= tcg_temp_new_i64();
6341 gen_load_fpr64(ctx
, fp0
, fs
);
6342 gen_load_fpr64(ctx
, fp1
, ft
);
6343 gen_helper_float_add_d(fp0
, fp0
, fp1
);
6344 tcg_temp_free_i64(fp1
);
6345 gen_store_fpr64(ctx
, fp0
, fd
);
6346 tcg_temp_free_i64(fp0
);
6352 check_cp1_registers(ctx
, fs
| ft
| fd
);
6354 TCGv_i64 fp0
= tcg_temp_new_i64();
6355 TCGv_i64 fp1
= tcg_temp_new_i64();
6357 gen_load_fpr64(ctx
, fp0
, fs
);
6358 gen_load_fpr64(ctx
, fp1
, ft
);
6359 gen_helper_float_sub_d(fp0
, fp0
, fp1
);
6360 tcg_temp_free_i64(fp1
);
6361 gen_store_fpr64(ctx
, fp0
, fd
);
6362 tcg_temp_free_i64(fp0
);
6368 check_cp1_registers(ctx
, fs
| ft
| fd
);
6370 TCGv_i64 fp0
= tcg_temp_new_i64();
6371 TCGv_i64 fp1
= tcg_temp_new_i64();
6373 gen_load_fpr64(ctx
, fp0
, fs
);
6374 gen_load_fpr64(ctx
, fp1
, ft
);
6375 gen_helper_float_mul_d(fp0
, fp0
, fp1
);
6376 tcg_temp_free_i64(fp1
);
6377 gen_store_fpr64(ctx
, fp0
, fd
);
6378 tcg_temp_free_i64(fp0
);
6384 check_cp1_registers(ctx
, fs
| ft
| fd
);
6386 TCGv_i64 fp0
= tcg_temp_new_i64();
6387 TCGv_i64 fp1
= tcg_temp_new_i64();
6389 gen_load_fpr64(ctx
, fp0
, fs
);
6390 gen_load_fpr64(ctx
, fp1
, ft
);
6391 gen_helper_float_div_d(fp0
, fp0
, fp1
);
6392 tcg_temp_free_i64(fp1
);
6393 gen_store_fpr64(ctx
, fp0
, fd
);
6394 tcg_temp_free_i64(fp0
);
6400 check_cp1_registers(ctx
, fs
| fd
);
6402 TCGv_i64 fp0
= tcg_temp_new_i64();
6404 gen_load_fpr64(ctx
, fp0
, fs
);
6405 gen_helper_float_sqrt_d(fp0
, fp0
);
6406 gen_store_fpr64(ctx
, fp0
, fd
);
6407 tcg_temp_free_i64(fp0
);
6412 check_cp1_registers(ctx
, fs
| fd
);
6414 TCGv_i64 fp0
= tcg_temp_new_i64();
6416 gen_load_fpr64(ctx
, fp0
, fs
);
6417 gen_helper_float_abs_d(fp0
, fp0
);
6418 gen_store_fpr64(ctx
, fp0
, fd
);
6419 tcg_temp_free_i64(fp0
);
6424 check_cp1_registers(ctx
, fs
| fd
);
6426 TCGv_i64 fp0
= tcg_temp_new_i64();
6428 gen_load_fpr64(ctx
, fp0
, fs
);
6429 gen_store_fpr64(ctx
, fp0
, fd
);
6430 tcg_temp_free_i64(fp0
);
6435 check_cp1_registers(ctx
, fs
| fd
);
6437 TCGv_i64 fp0
= tcg_temp_new_i64();
6439 gen_load_fpr64(ctx
, fp0
, fs
);
6440 gen_helper_float_chs_d(fp0
, fp0
);
6441 gen_store_fpr64(ctx
, fp0
, fd
);
6442 tcg_temp_free_i64(fp0
);
6447 check_cp1_64bitmode(ctx
);
6449 TCGv_i64 fp0
= tcg_temp_new_i64();
6451 gen_load_fpr64(ctx
, fp0
, fs
);
6452 gen_helper_float_roundl_d(fp0
, fp0
);
6453 gen_store_fpr64(ctx
, fp0
, fd
);
6454 tcg_temp_free_i64(fp0
);
6459 check_cp1_64bitmode(ctx
);
6461 TCGv_i64 fp0
= tcg_temp_new_i64();
6463 gen_load_fpr64(ctx
, fp0
, fs
);
6464 gen_helper_float_truncl_d(fp0
, fp0
);
6465 gen_store_fpr64(ctx
, fp0
, fd
);
6466 tcg_temp_free_i64(fp0
);
6471 check_cp1_64bitmode(ctx
);
6473 TCGv_i64 fp0
= tcg_temp_new_i64();
6475 gen_load_fpr64(ctx
, fp0
, fs
);
6476 gen_helper_float_ceill_d(fp0
, fp0
);
6477 gen_store_fpr64(ctx
, fp0
, fd
);
6478 tcg_temp_free_i64(fp0
);
6483 check_cp1_64bitmode(ctx
);
6485 TCGv_i64 fp0
= tcg_temp_new_i64();
6487 gen_load_fpr64(ctx
, fp0
, fs
);
6488 gen_helper_float_floorl_d(fp0
, fp0
);
6489 gen_store_fpr64(ctx
, fp0
, fd
);
6490 tcg_temp_free_i64(fp0
);
6495 check_cp1_registers(ctx
, fs
);
6497 TCGv_i32 fp32
= tcg_temp_new_i32();
6498 TCGv_i64 fp64
= tcg_temp_new_i64();
6500 gen_load_fpr64(ctx
, fp64
, fs
);
6501 gen_helper_float_roundw_d(fp32
, fp64
);
6502 tcg_temp_free_i64(fp64
);
6503 gen_store_fpr32(fp32
, fd
);
6504 tcg_temp_free_i32(fp32
);
6509 check_cp1_registers(ctx
, fs
);
6511 TCGv_i32 fp32
= tcg_temp_new_i32();
6512 TCGv_i64 fp64
= tcg_temp_new_i64();
6514 gen_load_fpr64(ctx
, fp64
, fs
);
6515 gen_helper_float_truncw_d(fp32
, fp64
);
6516 tcg_temp_free_i64(fp64
);
6517 gen_store_fpr32(fp32
, fd
);
6518 tcg_temp_free_i32(fp32
);
6523 check_cp1_registers(ctx
, fs
);
6525 TCGv_i32 fp32
= tcg_temp_new_i32();
6526 TCGv_i64 fp64
= tcg_temp_new_i64();
6528 gen_load_fpr64(ctx
, fp64
, fs
);
6529 gen_helper_float_ceilw_d(fp32
, fp64
);
6530 tcg_temp_free_i64(fp64
);
6531 gen_store_fpr32(fp32
, fd
);
6532 tcg_temp_free_i32(fp32
);
6537 check_cp1_registers(ctx
, fs
);
6539 TCGv_i32 fp32
= tcg_temp_new_i32();
6540 TCGv_i64 fp64
= tcg_temp_new_i64();
6542 gen_load_fpr64(ctx
, fp64
, fs
);
6543 gen_helper_float_floorw_d(fp32
, fp64
);
6544 tcg_temp_free_i64(fp64
);
6545 gen_store_fpr32(fp32
, fd
);
6546 tcg_temp_free_i32(fp32
);
6551 gen_movcf_d(ctx
, fs
, fd
, (ft
>> 2) & 0x7, ft
& 0x1);
6556 int l1
= gen_new_label();
6560 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[ft
], 0, l1
);
6562 fp0
= tcg_temp_new_i64();
6563 gen_load_fpr64(ctx
, fp0
, fs
);
6564 gen_store_fpr64(ctx
, fp0
, fd
);
6565 tcg_temp_free_i64(fp0
);
6572 int l1
= gen_new_label();
6576 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[ft
], 0, l1
);
6577 fp0
= tcg_temp_new_i64();
6578 gen_load_fpr64(ctx
, fp0
, fs
);
6579 gen_store_fpr64(ctx
, fp0
, fd
);
6580 tcg_temp_free_i64(fp0
);
6587 check_cp1_64bitmode(ctx
);
6589 TCGv_i64 fp0
= tcg_temp_new_i64();
6591 gen_load_fpr64(ctx
, fp0
, fs
);
6592 gen_helper_float_recip_d(fp0
, fp0
);
6593 gen_store_fpr64(ctx
, fp0
, fd
);
6594 tcg_temp_free_i64(fp0
);
6599 check_cp1_64bitmode(ctx
);
6601 TCGv_i64 fp0
= tcg_temp_new_i64();
6603 gen_load_fpr64(ctx
, fp0
, fs
);
6604 gen_helper_float_rsqrt_d(fp0
, fp0
);
6605 gen_store_fpr64(ctx
, fp0
, fd
);
6606 tcg_temp_free_i64(fp0
);
6611 check_cp1_64bitmode(ctx
);
6613 TCGv_i64 fp0
= tcg_temp_new_i64();
6614 TCGv_i64 fp1
= tcg_temp_new_i64();
6616 gen_load_fpr64(ctx
, fp0
, fs
);
6617 gen_load_fpr64(ctx
, fp1
, ft
);
6618 gen_helper_float_recip2_d(fp0
, fp0
, fp1
);
6619 tcg_temp_free_i64(fp1
);
6620 gen_store_fpr64(ctx
, fp0
, fd
);
6621 tcg_temp_free_i64(fp0
);
6626 check_cp1_64bitmode(ctx
);
6628 TCGv_i64 fp0
= tcg_temp_new_i64();
6630 gen_load_fpr64(ctx
, fp0
, fs
);
6631 gen_helper_float_recip1_d(fp0
, fp0
);
6632 gen_store_fpr64(ctx
, fp0
, fd
);
6633 tcg_temp_free_i64(fp0
);
6638 check_cp1_64bitmode(ctx
);
6640 TCGv_i64 fp0
= tcg_temp_new_i64();
6642 gen_load_fpr64(ctx
, fp0
, fs
);
6643 gen_helper_float_rsqrt1_d(fp0
, fp0
);
6644 gen_store_fpr64(ctx
, fp0
, fd
);
6645 tcg_temp_free_i64(fp0
);
6650 check_cp1_64bitmode(ctx
);
6652 TCGv_i64 fp0
= tcg_temp_new_i64();
6653 TCGv_i64 fp1
= tcg_temp_new_i64();
6655 gen_load_fpr64(ctx
, fp0
, fs
);
6656 gen_load_fpr64(ctx
, fp1
, ft
);
6657 gen_helper_float_rsqrt2_d(fp0
, fp0
, fp1
);
6658 tcg_temp_free_i64(fp1
);
6659 gen_store_fpr64(ctx
, fp0
, fd
);
6660 tcg_temp_free_i64(fp0
);
6681 TCGv_i64 fp0
= tcg_temp_new_i64();
6682 TCGv_i64 fp1
= tcg_temp_new_i64();
6684 gen_load_fpr64(ctx
, fp0
, fs
);
6685 gen_load_fpr64(ctx
, fp1
, ft
);
6686 if (ctx
->opcode
& (1 << 6)) {
6688 check_cp1_registers(ctx
, fs
| ft
);
6689 gen_cmpabs_d(func
-48, fp0
, fp1
, cc
);
6690 opn
= condnames_abs
[func
-48];
6692 check_cp1_registers(ctx
, fs
| ft
);
6693 gen_cmp_d(func
-48, fp0
, fp1
, cc
);
6694 opn
= condnames
[func
-48];
6696 tcg_temp_free_i64(fp0
);
6697 tcg_temp_free_i64(fp1
);
6701 check_cp1_registers(ctx
, fs
);
6703 TCGv_i32 fp32
= tcg_temp_new_i32();
6704 TCGv_i64 fp64
= tcg_temp_new_i64();
6706 gen_load_fpr64(ctx
, fp64
, fs
);
6707 gen_helper_float_cvts_d(fp32
, fp64
);
6708 tcg_temp_free_i64(fp64
);
6709 gen_store_fpr32(fp32
, fd
);
6710 tcg_temp_free_i32(fp32
);
6715 check_cp1_registers(ctx
, fs
);
6717 TCGv_i32 fp32
= tcg_temp_new_i32();
6718 TCGv_i64 fp64
= tcg_temp_new_i64();
6720 gen_load_fpr64(ctx
, fp64
, fs
);
6721 gen_helper_float_cvtw_d(fp32
, fp64
);
6722 tcg_temp_free_i64(fp64
);
6723 gen_store_fpr32(fp32
, fd
);
6724 tcg_temp_free_i32(fp32
);
6729 check_cp1_64bitmode(ctx
);
6731 TCGv_i64 fp0
= tcg_temp_new_i64();
6733 gen_load_fpr64(ctx
, fp0
, fs
);
6734 gen_helper_float_cvtl_d(fp0
, fp0
);
6735 gen_store_fpr64(ctx
, fp0
, fd
);
6736 tcg_temp_free_i64(fp0
);
6742 TCGv_i32 fp0
= tcg_temp_new_i32();
6744 gen_load_fpr32(fp0
, fs
);
6745 gen_helper_float_cvts_w(fp0
, fp0
);
6746 gen_store_fpr32(fp0
, fd
);
6747 tcg_temp_free_i32(fp0
);
6752 check_cp1_registers(ctx
, fd
);
6754 TCGv_i32 fp32
= tcg_temp_new_i32();
6755 TCGv_i64 fp64
= tcg_temp_new_i64();
6757 gen_load_fpr32(fp32
, fs
);
6758 gen_helper_float_cvtd_w(fp64
, fp32
);
6759 tcg_temp_free_i32(fp32
);
6760 gen_store_fpr64(ctx
, fp64
, fd
);
6761 tcg_temp_free_i64(fp64
);
6766 check_cp1_64bitmode(ctx
);
6768 TCGv_i32 fp32
= tcg_temp_new_i32();
6769 TCGv_i64 fp64
= tcg_temp_new_i64();
6771 gen_load_fpr64(ctx
, fp64
, fs
);
6772 gen_helper_float_cvts_l(fp32
, fp64
);
6773 tcg_temp_free_i64(fp64
);
6774 gen_store_fpr32(fp32
, fd
);
6775 tcg_temp_free_i32(fp32
);
6780 check_cp1_64bitmode(ctx
);
6782 TCGv_i64 fp0
= tcg_temp_new_i64();
6784 gen_load_fpr64(ctx
, fp0
, fs
);
6785 gen_helper_float_cvtd_l(fp0
, fp0
);
6786 gen_store_fpr64(ctx
, fp0
, fd
);
6787 tcg_temp_free_i64(fp0
);
6792 check_cp1_64bitmode(ctx
);
6794 TCGv_i64 fp0
= tcg_temp_new_i64();
6796 gen_load_fpr64(ctx
, fp0
, fs
);
6797 gen_helper_float_cvtps_pw(fp0
, fp0
);
6798 gen_store_fpr64(ctx
, fp0
, fd
);
6799 tcg_temp_free_i64(fp0
);
6804 check_cp1_64bitmode(ctx
);
6806 TCGv_i64 fp0
= tcg_temp_new_i64();
6807 TCGv_i64 fp1
= tcg_temp_new_i64();
6809 gen_load_fpr64(ctx
, fp0
, fs
);
6810 gen_load_fpr64(ctx
, fp1
, ft
);
6811 gen_helper_float_add_ps(fp0
, fp0
, fp1
);
6812 tcg_temp_free_i64(fp1
);
6813 gen_store_fpr64(ctx
, fp0
, fd
);
6814 tcg_temp_free_i64(fp0
);
6819 check_cp1_64bitmode(ctx
);
6821 TCGv_i64 fp0
= tcg_temp_new_i64();
6822 TCGv_i64 fp1
= tcg_temp_new_i64();
6824 gen_load_fpr64(ctx
, fp0
, fs
);
6825 gen_load_fpr64(ctx
, fp1
, ft
);
6826 gen_helper_float_sub_ps(fp0
, fp0
, fp1
);
6827 tcg_temp_free_i64(fp1
);
6828 gen_store_fpr64(ctx
, fp0
, fd
);
6829 tcg_temp_free_i64(fp0
);
6834 check_cp1_64bitmode(ctx
);
6836 TCGv_i64 fp0
= tcg_temp_new_i64();
6837 TCGv_i64 fp1
= tcg_temp_new_i64();
6839 gen_load_fpr64(ctx
, fp0
, fs
);
6840 gen_load_fpr64(ctx
, fp1
, ft
);
6841 gen_helper_float_mul_ps(fp0
, fp0
, fp1
);
6842 tcg_temp_free_i64(fp1
);
6843 gen_store_fpr64(ctx
, fp0
, fd
);
6844 tcg_temp_free_i64(fp0
);
6849 check_cp1_64bitmode(ctx
);
6851 TCGv_i64 fp0
= tcg_temp_new_i64();
6853 gen_load_fpr64(ctx
, fp0
, fs
);
6854 gen_helper_float_abs_ps(fp0
, fp0
);
6855 gen_store_fpr64(ctx
, fp0
, fd
);
6856 tcg_temp_free_i64(fp0
);
6861 check_cp1_64bitmode(ctx
);
6863 TCGv_i64 fp0
= tcg_temp_new_i64();
6865 gen_load_fpr64(ctx
, fp0
, fs
);
6866 gen_store_fpr64(ctx
, fp0
, fd
);
6867 tcg_temp_free_i64(fp0
);
6872 check_cp1_64bitmode(ctx
);
6874 TCGv_i64 fp0
= tcg_temp_new_i64();
6876 gen_load_fpr64(ctx
, fp0
, fs
);
6877 gen_helper_float_chs_ps(fp0
, fp0
);
6878 gen_store_fpr64(ctx
, fp0
, fd
);
6879 tcg_temp_free_i64(fp0
);
6884 check_cp1_64bitmode(ctx
);
6885 gen_movcf_ps(fs
, fd
, (ft
>> 2) & 0x7, ft
& 0x1);
6889 check_cp1_64bitmode(ctx
);
6891 int l1
= gen_new_label();
6895 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[ft
], 0, l1
);
6896 fp0
= tcg_temp_new_i64();
6897 gen_load_fpr64(ctx
, fp0
, fs
);
6898 gen_store_fpr64(ctx
, fp0
, fd
);
6899 tcg_temp_free_i64(fp0
);
6905 check_cp1_64bitmode(ctx
);
6907 int l1
= gen_new_label();
6911 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[ft
], 0, l1
);
6912 fp0
= tcg_temp_new_i64();
6913 gen_load_fpr64(ctx
, fp0
, fs
);
6914 gen_store_fpr64(ctx
, fp0
, fd
);
6915 tcg_temp_free_i64(fp0
);
6922 check_cp1_64bitmode(ctx
);
6924 TCGv_i64 fp0
= tcg_temp_new_i64();
6925 TCGv_i64 fp1
= tcg_temp_new_i64();
6927 gen_load_fpr64(ctx
, fp0
, ft
);
6928 gen_load_fpr64(ctx
, fp1
, fs
);
6929 gen_helper_float_addr_ps(fp0
, fp0
, fp1
);
6930 tcg_temp_free_i64(fp1
);
6931 gen_store_fpr64(ctx
, fp0
, fd
);
6932 tcg_temp_free_i64(fp0
);
6937 check_cp1_64bitmode(ctx
);
6939 TCGv_i64 fp0
= tcg_temp_new_i64();
6940 TCGv_i64 fp1
= tcg_temp_new_i64();
6942 gen_load_fpr64(ctx
, fp0
, ft
);
6943 gen_load_fpr64(ctx
, fp1
, fs
);
6944 gen_helper_float_mulr_ps(fp0
, fp0
, fp1
);
6945 tcg_temp_free_i64(fp1
);
6946 gen_store_fpr64(ctx
, fp0
, fd
);
6947 tcg_temp_free_i64(fp0
);
6952 check_cp1_64bitmode(ctx
);
6954 TCGv_i64 fp0
= tcg_temp_new_i64();
6955 TCGv_i64 fp1
= tcg_temp_new_i64();
6957 gen_load_fpr64(ctx
, fp0
, fs
);
6958 gen_load_fpr64(ctx
, fp1
, fd
);
6959 gen_helper_float_recip2_ps(fp0
, fp0
, fp1
);
6960 tcg_temp_free_i64(fp1
);
6961 gen_store_fpr64(ctx
, fp0
, fd
);
6962 tcg_temp_free_i64(fp0
);
6967 check_cp1_64bitmode(ctx
);
6969 TCGv_i64 fp0
= tcg_temp_new_i64();
6971 gen_load_fpr64(ctx
, fp0
, fs
);
6972 gen_helper_float_recip1_ps(fp0
, fp0
);
6973 gen_store_fpr64(ctx
, fp0
, fd
);
6974 tcg_temp_free_i64(fp0
);
6979 check_cp1_64bitmode(ctx
);
6981 TCGv_i64 fp0
= tcg_temp_new_i64();
6983 gen_load_fpr64(ctx
, fp0
, fs
);
6984 gen_helper_float_rsqrt1_ps(fp0
, fp0
);
6985 gen_store_fpr64(ctx
, fp0
, fd
);
6986 tcg_temp_free_i64(fp0
);
6991 check_cp1_64bitmode(ctx
);
6993 TCGv_i64 fp0
= tcg_temp_new_i64();
6994 TCGv_i64 fp1
= tcg_temp_new_i64();
6996 gen_load_fpr64(ctx
, fp0
, fs
);
6997 gen_load_fpr64(ctx
, fp1
, ft
);
6998 gen_helper_float_rsqrt2_ps(fp0
, fp0
, fp1
);
6999 tcg_temp_free_i64(fp1
);
7000 gen_store_fpr64(ctx
, fp0
, fd
);
7001 tcg_temp_free_i64(fp0
);
7006 check_cp1_64bitmode(ctx
);
7008 TCGv_i32 fp0
= tcg_temp_new_i32();
7010 gen_load_fpr32h(fp0
, fs
);
7011 gen_helper_float_cvts_pu(fp0
, fp0
);
7012 gen_store_fpr32(fp0
, fd
);
7013 tcg_temp_free_i32(fp0
);
7018 check_cp1_64bitmode(ctx
);
7020 TCGv_i64 fp0
= tcg_temp_new_i64();
7022 gen_load_fpr64(ctx
, fp0
, fs
);
7023 gen_helper_float_cvtpw_ps(fp0
, fp0
);
7024 gen_store_fpr64(ctx
, fp0
, fd
);
7025 tcg_temp_free_i64(fp0
);
7030 check_cp1_64bitmode(ctx
);
7032 TCGv_i32 fp0
= tcg_temp_new_i32();
7034 gen_load_fpr32(fp0
, fs
);
7035 gen_helper_float_cvts_pl(fp0
, fp0
);
7036 gen_store_fpr32(fp0
, fd
);
7037 tcg_temp_free_i32(fp0
);
7042 check_cp1_64bitmode(ctx
);
7044 TCGv_i32 fp0
= tcg_temp_new_i32();
7045 TCGv_i32 fp1
= tcg_temp_new_i32();
7047 gen_load_fpr32(fp0
, fs
);
7048 gen_load_fpr32(fp1
, ft
);
7049 gen_store_fpr32h(fp0
, fd
);
7050 gen_store_fpr32(fp1
, fd
);
7051 tcg_temp_free_i32(fp0
);
7052 tcg_temp_free_i32(fp1
);
7057 check_cp1_64bitmode(ctx
);
7059 TCGv_i32 fp0
= tcg_temp_new_i32();
7060 TCGv_i32 fp1
= tcg_temp_new_i32();
7062 gen_load_fpr32(fp0
, fs
);
7063 gen_load_fpr32h(fp1
, ft
);
7064 gen_store_fpr32(fp1
, fd
);
7065 gen_store_fpr32h(fp0
, fd
);
7066 tcg_temp_free_i32(fp0
);
7067 tcg_temp_free_i32(fp1
);
7072 check_cp1_64bitmode(ctx
);
7074 TCGv_i32 fp0
= tcg_temp_new_i32();
7075 TCGv_i32 fp1
= tcg_temp_new_i32();
7077 gen_load_fpr32h(fp0
, fs
);
7078 gen_load_fpr32(fp1
, ft
);
7079 gen_store_fpr32(fp1
, fd
);
7080 gen_store_fpr32h(fp0
, fd
);
7081 tcg_temp_free_i32(fp0
);
7082 tcg_temp_free_i32(fp1
);
7087 check_cp1_64bitmode(ctx
);
7089 TCGv_i32 fp0
= tcg_temp_new_i32();
7090 TCGv_i32 fp1
= tcg_temp_new_i32();
7092 gen_load_fpr32h(fp0
, fs
);
7093 gen_load_fpr32h(fp1
, ft
);
7094 gen_store_fpr32(fp1
, fd
);
7095 gen_store_fpr32h(fp0
, fd
);
7096 tcg_temp_free_i32(fp0
);
7097 tcg_temp_free_i32(fp1
);
7117 check_cp1_64bitmode(ctx
);
7119 TCGv_i64 fp0
= tcg_temp_new_i64();
7120 TCGv_i64 fp1
= tcg_temp_new_i64();
7122 gen_load_fpr64(ctx
, fp0
, fs
);
7123 gen_load_fpr64(ctx
, fp1
, ft
);
7124 if (ctx
->opcode
& (1 << 6)) {
7125 gen_cmpabs_ps(func
-48, fp0
, fp1
, cc
);
7126 opn
= condnames_abs
[func
-48];
7128 gen_cmp_ps(func
-48, fp0
, fp1
, cc
);
7129 opn
= condnames
[func
-48];
7131 tcg_temp_free_i64(fp0
);
7132 tcg_temp_free_i64(fp1
);
7137 generate_exception (ctx
, EXCP_RI
);
7142 MIPS_DEBUG("%s %s, %s, %s", opn
, fregnames
[fd
], fregnames
[fs
], fregnames
[ft
]);
7145 MIPS_DEBUG("%s %s,%s", opn
, fregnames
[fs
], fregnames
[ft
]);
7148 MIPS_DEBUG("%s %s,%s", opn
, fregnames
[fd
], fregnames
[fs
]);
7153 /* Coprocessor 3 (FPU) */
7154 static void gen_flt3_ldst (DisasContext
*ctx
, uint32_t opc
,
7155 int fd
, int fs
, int base
, int index
)
7157 const char *opn
= "extended float load/store";
7159 TCGv t0
= tcg_temp_new();
7162 gen_load_gpr(t0
, index
);
7163 } else if (index
== 0) {
7164 gen_load_gpr(t0
, base
);
7166 gen_load_gpr(t0
, index
);
7167 gen_op_addr_add(ctx
, t0
, cpu_gpr
[base
], t0
);
7169 /* Don't do NOP if destination is zero: we must perform the actual
7171 save_cpu_state(ctx
, 0);
7176 TCGv_i32 fp0
= tcg_temp_new_i32();
7178 tcg_gen_qemu_ld32s(t0
, t0
, ctx
->mem_idx
);
7179 tcg_gen_trunc_tl_i32(fp0
, t0
);
7180 gen_store_fpr32(fp0
, fd
);
7181 tcg_temp_free_i32(fp0
);
7187 check_cp1_registers(ctx
, fd
);
7189 TCGv_i64 fp0
= tcg_temp_new_i64();
7191 tcg_gen_qemu_ld64(fp0
, t0
, ctx
->mem_idx
);
7192 gen_store_fpr64(ctx
, fp0
, fd
);
7193 tcg_temp_free_i64(fp0
);
7198 check_cp1_64bitmode(ctx
);
7199 tcg_gen_andi_tl(t0
, t0
, ~0x7);
7201 TCGv_i64 fp0
= tcg_temp_new_i64();
7203 tcg_gen_qemu_ld64(fp0
, t0
, ctx
->mem_idx
);
7204 gen_store_fpr64(ctx
, fp0
, fd
);
7205 tcg_temp_free_i64(fp0
);
7212 TCGv_i32 fp0
= tcg_temp_new_i32();
7213 TCGv t1
= tcg_temp_new();
7215 gen_load_fpr32(fp0
, fs
);
7216 tcg_gen_extu_i32_tl(t1
, fp0
);
7217 tcg_gen_qemu_st32(t1
, t0
, ctx
->mem_idx
);
7218 tcg_temp_free_i32(fp0
);
7226 check_cp1_registers(ctx
, fs
);
7228 TCGv_i64 fp0
= tcg_temp_new_i64();
7230 gen_load_fpr64(ctx
, fp0
, fs
);
7231 tcg_gen_qemu_st64(fp0
, t0
, ctx
->mem_idx
);
7232 tcg_temp_free_i64(fp0
);
7238 check_cp1_64bitmode(ctx
);
7239 tcg_gen_andi_tl(t0
, t0
, ~0x7);
7241 TCGv_i64 fp0
= tcg_temp_new_i64();
7243 gen_load_fpr64(ctx
, fp0
, fs
);
7244 tcg_gen_qemu_st64(fp0
, t0
, ctx
->mem_idx
);
7245 tcg_temp_free_i64(fp0
);
7252 MIPS_DEBUG("%s %s, %s(%s)", opn
, fregnames
[store
? fs
: fd
],
7253 regnames
[index
], regnames
[base
]);
7256 static void gen_flt3_arith (DisasContext
*ctx
, uint32_t opc
,
7257 int fd
, int fr
, int fs
, int ft
)
7259 const char *opn
= "flt3_arith";
7263 check_cp1_64bitmode(ctx
);
7265 TCGv t0
= tcg_temp_local_new();
7266 TCGv_i32 fp
= tcg_temp_new_i32();
7267 TCGv_i32 fph
= tcg_temp_new_i32();
7268 int l1
= gen_new_label();
7269 int l2
= gen_new_label();
7271 gen_load_gpr(t0
, fr
);
7272 tcg_gen_andi_tl(t0
, t0
, 0x7);
7274 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
7275 gen_load_fpr32(fp
, fs
);
7276 gen_load_fpr32h(fph
, fs
);
7277 gen_store_fpr32(fp
, fd
);
7278 gen_store_fpr32h(fph
, fd
);
7281 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 4, l2
);
7283 #ifdef TARGET_WORDS_BIGENDIAN
7284 gen_load_fpr32(fp
, fs
);
7285 gen_load_fpr32h(fph
, ft
);
7286 gen_store_fpr32h(fp
, fd
);
7287 gen_store_fpr32(fph
, fd
);
7289 gen_load_fpr32h(fph
, fs
);
7290 gen_load_fpr32(fp
, ft
);
7291 gen_store_fpr32(fph
, fd
);
7292 gen_store_fpr32h(fp
, fd
);
7295 tcg_temp_free_i32(fp
);
7296 tcg_temp_free_i32(fph
);
7303 TCGv_i32 fp0
= tcg_temp_new_i32();
7304 TCGv_i32 fp1
= tcg_temp_new_i32();
7305 TCGv_i32 fp2
= tcg_temp_new_i32();
7307 gen_load_fpr32(fp0
, fs
);
7308 gen_load_fpr32(fp1
, ft
);
7309 gen_load_fpr32(fp2
, fr
);
7310 gen_helper_float_muladd_s(fp2
, fp0
, fp1
, fp2
);
7311 tcg_temp_free_i32(fp0
);
7312 tcg_temp_free_i32(fp1
);
7313 gen_store_fpr32(fp2
, fd
);
7314 tcg_temp_free_i32(fp2
);
7320 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7322 TCGv_i64 fp0
= tcg_temp_new_i64();
7323 TCGv_i64 fp1
= tcg_temp_new_i64();
7324 TCGv_i64 fp2
= tcg_temp_new_i64();
7326 gen_load_fpr64(ctx
, fp0
, fs
);
7327 gen_load_fpr64(ctx
, fp1
, ft
);
7328 gen_load_fpr64(ctx
, fp2
, fr
);
7329 gen_helper_float_muladd_d(fp2
, fp0
, fp1
, fp2
);
7330 tcg_temp_free_i64(fp0
);
7331 tcg_temp_free_i64(fp1
);
7332 gen_store_fpr64(ctx
, fp2
, fd
);
7333 tcg_temp_free_i64(fp2
);
7338 check_cp1_64bitmode(ctx
);
7340 TCGv_i64 fp0
= tcg_temp_new_i64();
7341 TCGv_i64 fp1
= tcg_temp_new_i64();
7342 TCGv_i64 fp2
= tcg_temp_new_i64();
7344 gen_load_fpr64(ctx
, fp0
, fs
);
7345 gen_load_fpr64(ctx
, fp1
, ft
);
7346 gen_load_fpr64(ctx
, fp2
, fr
);
7347 gen_helper_float_muladd_ps(fp2
, fp0
, fp1
, fp2
);
7348 tcg_temp_free_i64(fp0
);
7349 tcg_temp_free_i64(fp1
);
7350 gen_store_fpr64(ctx
, fp2
, fd
);
7351 tcg_temp_free_i64(fp2
);
7358 TCGv_i32 fp0
= tcg_temp_new_i32();
7359 TCGv_i32 fp1
= tcg_temp_new_i32();
7360 TCGv_i32 fp2
= tcg_temp_new_i32();
7362 gen_load_fpr32(fp0
, fs
);
7363 gen_load_fpr32(fp1
, ft
);
7364 gen_load_fpr32(fp2
, fr
);
7365 gen_helper_float_mulsub_s(fp2
, fp0
, fp1
, fp2
);
7366 tcg_temp_free_i32(fp0
);
7367 tcg_temp_free_i32(fp1
);
7368 gen_store_fpr32(fp2
, fd
);
7369 tcg_temp_free_i32(fp2
);
7375 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7377 TCGv_i64 fp0
= tcg_temp_new_i64();
7378 TCGv_i64 fp1
= tcg_temp_new_i64();
7379 TCGv_i64 fp2
= tcg_temp_new_i64();
7381 gen_load_fpr64(ctx
, fp0
, fs
);
7382 gen_load_fpr64(ctx
, fp1
, ft
);
7383 gen_load_fpr64(ctx
, fp2
, fr
);
7384 gen_helper_float_mulsub_d(fp2
, fp0
, fp1
, fp2
);
7385 tcg_temp_free_i64(fp0
);
7386 tcg_temp_free_i64(fp1
);
7387 gen_store_fpr64(ctx
, fp2
, fd
);
7388 tcg_temp_free_i64(fp2
);
7393 check_cp1_64bitmode(ctx
);
7395 TCGv_i64 fp0
= tcg_temp_new_i64();
7396 TCGv_i64 fp1
= tcg_temp_new_i64();
7397 TCGv_i64 fp2
= tcg_temp_new_i64();
7399 gen_load_fpr64(ctx
, fp0
, fs
);
7400 gen_load_fpr64(ctx
, fp1
, ft
);
7401 gen_load_fpr64(ctx
, fp2
, fr
);
7402 gen_helper_float_mulsub_ps(fp2
, fp0
, fp1
, fp2
);
7403 tcg_temp_free_i64(fp0
);
7404 tcg_temp_free_i64(fp1
);
7405 gen_store_fpr64(ctx
, fp2
, fd
);
7406 tcg_temp_free_i64(fp2
);
7413 TCGv_i32 fp0
= tcg_temp_new_i32();
7414 TCGv_i32 fp1
= tcg_temp_new_i32();
7415 TCGv_i32 fp2
= tcg_temp_new_i32();
7417 gen_load_fpr32(fp0
, fs
);
7418 gen_load_fpr32(fp1
, ft
);
7419 gen_load_fpr32(fp2
, fr
);
7420 gen_helper_float_nmuladd_s(fp2
, fp0
, fp1
, fp2
);
7421 tcg_temp_free_i32(fp0
);
7422 tcg_temp_free_i32(fp1
);
7423 gen_store_fpr32(fp2
, fd
);
7424 tcg_temp_free_i32(fp2
);
7430 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7432 TCGv_i64 fp0
= tcg_temp_new_i64();
7433 TCGv_i64 fp1
= tcg_temp_new_i64();
7434 TCGv_i64 fp2
= tcg_temp_new_i64();
7436 gen_load_fpr64(ctx
, fp0
, fs
);
7437 gen_load_fpr64(ctx
, fp1
, ft
);
7438 gen_load_fpr64(ctx
, fp2
, fr
);
7439 gen_helper_float_nmuladd_d(fp2
, fp0
, fp1
, fp2
);
7440 tcg_temp_free_i64(fp0
);
7441 tcg_temp_free_i64(fp1
);
7442 gen_store_fpr64(ctx
, fp2
, fd
);
7443 tcg_temp_free_i64(fp2
);
7448 check_cp1_64bitmode(ctx
);
7450 TCGv_i64 fp0
= tcg_temp_new_i64();
7451 TCGv_i64 fp1
= tcg_temp_new_i64();
7452 TCGv_i64 fp2
= tcg_temp_new_i64();
7454 gen_load_fpr64(ctx
, fp0
, fs
);
7455 gen_load_fpr64(ctx
, fp1
, ft
);
7456 gen_load_fpr64(ctx
, fp2
, fr
);
7457 gen_helper_float_nmuladd_ps(fp2
, fp0
, fp1
, fp2
);
7458 tcg_temp_free_i64(fp0
);
7459 tcg_temp_free_i64(fp1
);
7460 gen_store_fpr64(ctx
, fp2
, fd
);
7461 tcg_temp_free_i64(fp2
);
7468 TCGv_i32 fp0
= tcg_temp_new_i32();
7469 TCGv_i32 fp1
= tcg_temp_new_i32();
7470 TCGv_i32 fp2
= tcg_temp_new_i32();
7472 gen_load_fpr32(fp0
, fs
);
7473 gen_load_fpr32(fp1
, ft
);
7474 gen_load_fpr32(fp2
, fr
);
7475 gen_helper_float_nmulsub_s(fp2
, fp0
, fp1
, fp2
);
7476 tcg_temp_free_i32(fp0
);
7477 tcg_temp_free_i32(fp1
);
7478 gen_store_fpr32(fp2
, fd
);
7479 tcg_temp_free_i32(fp2
);
7485 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7487 TCGv_i64 fp0
= tcg_temp_new_i64();
7488 TCGv_i64 fp1
= tcg_temp_new_i64();
7489 TCGv_i64 fp2
= tcg_temp_new_i64();
7491 gen_load_fpr64(ctx
, fp0
, fs
);
7492 gen_load_fpr64(ctx
, fp1
, ft
);
7493 gen_load_fpr64(ctx
, fp2
, fr
);
7494 gen_helper_float_nmulsub_d(fp2
, fp0
, fp1
, fp2
);
7495 tcg_temp_free_i64(fp0
);
7496 tcg_temp_free_i64(fp1
);
7497 gen_store_fpr64(ctx
, fp2
, fd
);
7498 tcg_temp_free_i64(fp2
);
7503 check_cp1_64bitmode(ctx
);
7505 TCGv_i64 fp0
= tcg_temp_new_i64();
7506 TCGv_i64 fp1
= tcg_temp_new_i64();
7507 TCGv_i64 fp2
= tcg_temp_new_i64();
7509 gen_load_fpr64(ctx
, fp0
, fs
);
7510 gen_load_fpr64(ctx
, fp1
, ft
);
7511 gen_load_fpr64(ctx
, fp2
, fr
);
7512 gen_helper_float_nmulsub_ps(fp2
, fp0
, fp1
, fp2
);
7513 tcg_temp_free_i64(fp0
);
7514 tcg_temp_free_i64(fp1
);
7515 gen_store_fpr64(ctx
, fp2
, fd
);
7516 tcg_temp_free_i64(fp2
);
7522 generate_exception (ctx
, EXCP_RI
);
7525 MIPS_DEBUG("%s %s, %s, %s, %s", opn
, fregnames
[fd
], fregnames
[fr
],
7526 fregnames
[fs
], fregnames
[ft
]);
7529 static void handle_delay_slot (CPUState
*env
, DisasContext
*ctx
,
7532 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
7533 int proc_hflags
= ctx
->hflags
& MIPS_HFLAG_BMASK
;
7534 /* Branches completion */
7535 ctx
->hflags
&= ~MIPS_HFLAG_BMASK
;
7536 ctx
->bstate
= BS_BRANCH
;
7537 save_cpu_state(ctx
, 0);
7538 /* FIXME: Need to clear can_do_io. */
7539 switch (proc_hflags
& MIPS_HFLAG_BMASK_BASE
) {
7541 /* unconditional branch */
7542 MIPS_DEBUG("unconditional branch");
7543 if (proc_hflags
& MIPS_HFLAG_BX
) {
7544 tcg_gen_xori_i32(hflags
, hflags
, MIPS_HFLAG_M16
);
7546 gen_goto_tb(ctx
, 0, ctx
->btarget
);
7549 /* blikely taken case */
7550 MIPS_DEBUG("blikely branch taken");
7551 gen_goto_tb(ctx
, 0, ctx
->btarget
);
7554 /* Conditional branch */
7555 MIPS_DEBUG("conditional branch");
7557 int l1
= gen_new_label();
7559 tcg_gen_brcondi_tl(TCG_COND_NE
, bcond
, 0, l1
);
7560 gen_goto_tb(ctx
, 1, ctx
->pc
+ insn_bytes
);
7562 gen_goto_tb(ctx
, 0, ctx
->btarget
);
7566 /* unconditional branch to register */
7567 MIPS_DEBUG("branch to register");
7568 if (env
->insn_flags
& ASE_MIPS16
) {
7569 TCGv t0
= tcg_temp_new();
7570 TCGv_i32 t1
= tcg_temp_new_i32();
7572 tcg_gen_andi_tl(t0
, btarget
, 0x1);
7573 tcg_gen_trunc_tl_i32(t1
, t0
);
7575 tcg_gen_andi_i32(hflags
, hflags
, ~(uint32_t)MIPS_HFLAG_M16
);
7576 tcg_gen_shli_i32(t1
, t1
, MIPS_HFLAG_M16_SHIFT
);
7577 tcg_gen_or_i32(hflags
, hflags
, t1
);
7578 tcg_temp_free_i32(t1
);
7580 tcg_gen_andi_tl(cpu_PC
, btarget
, ~(target_ulong
)0x1);
7582 tcg_gen_mov_tl(cpu_PC
, btarget
);
7584 if (ctx
->singlestep_enabled
) {
7585 save_cpu_state(ctx
, 0);
7586 gen_helper_0i(raise_exception
, EXCP_DEBUG
);
7591 MIPS_DEBUG("unknown branch");
7597 /* ISA extensions (ASEs) */
7598 /* MIPS16 extension to MIPS32 */
7600 /* MIPS16 major opcodes */
7602 M16_OPC_ADDIUSP
= 0x00,
7603 M16_OPC_ADDIUPC
= 0x01,
7606 M16_OPC_BEQZ
= 0x04,
7607 M16_OPC_BNEQZ
= 0x05,
7608 M16_OPC_SHIFT
= 0x06,
7610 M16_OPC_RRIA
= 0x08,
7611 M16_OPC_ADDIU8
= 0x09,
7612 M16_OPC_SLTI
= 0x0a,
7613 M16_OPC_SLTIU
= 0x0b,
7616 M16_OPC_CMPI
= 0x0e,
7620 M16_OPC_LWSP
= 0x12,
7624 M16_OPC_LWPC
= 0x16,
7628 M16_OPC_SWSP
= 0x1a,
7632 M16_OPC_EXTEND
= 0x1e,
7636 /* I8 funct field */
7655 /* RR funct field */
7689 /* I64 funct field */
7701 /* RR ry field for CNVT */
7703 RR_RY_CNVT_ZEB
= 0x0,
7704 RR_RY_CNVT_ZEH
= 0x1,
7705 RR_RY_CNVT_ZEW
= 0x2,
7706 RR_RY_CNVT_SEB
= 0x4,
7707 RR_RY_CNVT_SEH
= 0x5,
7708 RR_RY_CNVT_SEW
= 0x6,
7711 static int xlat (int r
)
7713 static int map
[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
7718 static void gen_mips16_save (DisasContext
*ctx
,
7719 int xsregs
, int aregs
,
7720 int do_ra
, int do_s0
, int do_s1
,
7723 TCGv t0
= tcg_temp_new();
7724 TCGv t1
= tcg_temp_new();
7754 generate_exception(ctx
, EXCP_RI
);
7760 gen_base_offset_addr(ctx
, t0
, 29, 12);
7761 gen_load_gpr(t1
, 7);
7762 op_ldst_sw(t1
, t0
, ctx
);
7765 gen_base_offset_addr(ctx
, t0
, 29, 8);
7766 gen_load_gpr(t1
, 6);
7767 op_ldst_sw(t1
, t0
, ctx
);
7770 gen_base_offset_addr(ctx
, t0
, 29, 4);
7771 gen_load_gpr(t1
, 5);
7772 op_ldst_sw(t1
, t0
, ctx
);
7775 gen_base_offset_addr(ctx
, t0
, 29, 0);
7776 gen_load_gpr(t1
, 4);
7777 op_ldst_sw(t1
, t0
, ctx
);
7780 gen_load_gpr(t0
, 29);
7782 #define DECR_AND_STORE(reg) do { \
7783 tcg_gen_subi_tl(t0, t0, 4); \
7784 gen_load_gpr(t1, reg); \
7785 op_ldst_sw(t1, t0, ctx); \
7849 generate_exception(ctx
, EXCP_RI
);
7865 #undef DECR_AND_STORE
7867 tcg_gen_subi_tl(cpu_gpr
[29], cpu_gpr
[29], framesize
);
7872 static void gen_mips16_restore (DisasContext
*ctx
,
7873 int xsregs
, int aregs
,
7874 int do_ra
, int do_s0
, int do_s1
,
7878 TCGv t0
= tcg_temp_new();
7879 TCGv t1
= tcg_temp_new();
7881 tcg_gen_addi_tl(t0
, cpu_gpr
[29], framesize
);
7883 #define DECR_AND_LOAD(reg) do { \
7884 tcg_gen_subi_tl(t0, t0, 4); \
7885 op_ldst_lw(t1, t0, ctx); \
7886 gen_store_gpr(t1, reg); \
7950 generate_exception(ctx
, EXCP_RI
);
7966 #undef DECR_AND_LOAD
7968 tcg_gen_addi_tl(cpu_gpr
[29], cpu_gpr
[29], framesize
);
7973 static void gen_addiupc (DisasContext
*ctx
, int rx
, int imm
,
7974 int is_64_bit
, int extended
)
7978 if (extended
&& (ctx
->hflags
& MIPS_HFLAG_BMASK
)) {
7979 generate_exception(ctx
, EXCP_RI
);
7983 t0
= tcg_temp_new();
7985 tcg_gen_movi_tl(t0
, pc_relative_pc(ctx
));
7986 tcg_gen_addi_tl(cpu_gpr
[rx
], t0
, imm
);
7988 tcg_gen_ext32s_tl(cpu_gpr
[rx
], cpu_gpr
[rx
]);
7994 #if defined(TARGET_MIPS64)
7995 static void decode_i64_mips16 (CPUState
*env
, DisasContext
*ctx
,
7996 int ry
, int funct
, int16_t offset
,
8002 offset
= extended
? offset
: offset
<< 3;
8003 gen_ldst(ctx
, OPC_LD
, ry
, 29, offset
);
8007 offset
= extended
? offset
: offset
<< 3;
8008 gen_ldst(ctx
, OPC_SD
, ry
, 29, offset
);
8012 offset
= extended
? offset
: (ctx
->opcode
& 0xff) << 3;
8013 gen_ldst(ctx
, OPC_SD
, 31, 29, offset
);
8017 offset
= extended
? offset
: ((int8_t)ctx
->opcode
) << 3;
8018 gen_arith_imm(env
, ctx
, OPC_DADDIU
, 29, 29, offset
);
8021 if (extended
&& (ctx
->hflags
& MIPS_HFLAG_BMASK
)) {
8022 generate_exception(ctx
, EXCP_RI
);
8024 offset
= extended
? offset
: offset
<< 3;
8025 gen_ldst(ctx
, OPC_LDPC
, ry
, 0, offset
);
8030 offset
= extended
? offset
: ((int8_t)(offset
<< 3)) >> 3;
8031 gen_arith_imm(env
, ctx
, OPC_DADDIU
, ry
, ry
, offset
);
8035 offset
= extended
? offset
: offset
<< 2;
8036 gen_addiupc(ctx
, ry
, offset
, 1, extended
);
8040 offset
= extended
? offset
: offset
<< 2;
8041 gen_arith_imm(env
, ctx
, OPC_DADDIU
, ry
, 29, offset
);
8047 static int decode_extended_mips16_opc (CPUState
*env
, DisasContext
*ctx
,
8050 int extend
= lduw_code(ctx
->pc
+ 2);
8051 int op
, rx
, ry
, funct
, sa
;
8052 int16_t imm
, offset
;
8054 ctx
->opcode
= (ctx
->opcode
<< 16) | extend
;
8055 op
= (ctx
->opcode
>> 11) & 0x1f;
8056 sa
= (ctx
->opcode
>> 22) & 0x1f;
8057 funct
= (ctx
->opcode
>> 8) & 0x7;
8058 rx
= xlat((ctx
->opcode
>> 8) & 0x7);
8059 ry
= xlat((ctx
->opcode
>> 5) & 0x7);
8060 offset
= imm
= (int16_t) (((ctx
->opcode
>> 16) & 0x1f) << 11
8061 | ((ctx
->opcode
>> 21) & 0x3f) << 5
8062 | (ctx
->opcode
& 0x1f));
8064 /* The extended opcodes cleverly reuse the opcodes from their 16-bit
8067 case M16_OPC_ADDIUSP
:
8068 gen_arith_imm(env
, ctx
, OPC_ADDIU
, rx
, 29, imm
);
8070 case M16_OPC_ADDIUPC
:
8071 gen_addiupc(ctx
, rx
, imm
, 0, 1);
8074 gen_compute_branch(ctx
, OPC_BEQ
, 4, 0, 0, offset
<< 1);
8075 /* No delay slot, so just process as a normal instruction */
8078 gen_compute_branch(ctx
, OPC_BEQ
, 4, rx
, 0, offset
<< 1);
8079 /* No delay slot, so just process as a normal instruction */
8082 gen_compute_branch(ctx
, OPC_BNE
, 4, rx
, 0, offset
<< 1);
8083 /* No delay slot, so just process as a normal instruction */
8086 switch (ctx
->opcode
& 0x3) {
8088 gen_shift_imm(env
, ctx
, OPC_SLL
, rx
, ry
, sa
);
8091 #if defined(TARGET_MIPS64)
8093 gen_shift_imm(env
, ctx
, OPC_DSLL
, rx
, ry
, sa
);
8095 generate_exception(ctx
, EXCP_RI
);
8099 gen_shift_imm(env
, ctx
, OPC_SRL
, rx
, ry
, sa
);
8102 gen_shift_imm(env
, ctx
, OPC_SRA
, rx
, ry
, sa
);
8106 #if defined(TARGET_MIPS64)
8109 gen_ldst(ctx
, OPC_LD
, ry
, rx
, offset
);
8113 imm
= ctx
->opcode
& 0xf;
8114 imm
= imm
| ((ctx
->opcode
>> 20) & 0x7f) << 4;
8115 imm
= imm
| ((ctx
->opcode
>> 16) & 0xf) << 11;
8116 imm
= (int16_t) (imm
<< 1) >> 1;
8117 if ((ctx
->opcode
>> 4) & 0x1) {
8118 #if defined(TARGET_MIPS64)
8120 gen_arith_imm(env
, ctx
, OPC_DADDIU
, ry
, rx
, imm
);
8122 generate_exception(ctx
, EXCP_RI
);
8125 gen_arith_imm(env
, ctx
, OPC_ADDIU
, ry
, rx
, imm
);
8128 case M16_OPC_ADDIU8
:
8129 gen_arith_imm(env
, ctx
, OPC_ADDIU
, rx
, rx
, imm
);
8132 gen_slt_imm(env
, OPC_SLTI
, 24, rx
, imm
);
8135 gen_slt_imm(env
, OPC_SLTIU
, 24, rx
, imm
);
8140 gen_compute_branch(ctx
, OPC_BEQ
, 4, 24, 0, offset
<< 1);
8143 gen_compute_branch(ctx
, OPC_BNE
, 4, 24, 0, offset
<< 1);
8146 gen_ldst(ctx
, OPC_SW
, 31, 29, imm
);
8149 gen_arith_imm(env
, ctx
, OPC_ADDIU
, 29, 29, imm
);
8153 int xsregs
= (ctx
->opcode
>> 24) & 0x7;
8154 int aregs
= (ctx
->opcode
>> 16) & 0xf;
8155 int do_ra
= (ctx
->opcode
>> 6) & 0x1;
8156 int do_s0
= (ctx
->opcode
>> 5) & 0x1;
8157 int do_s1
= (ctx
->opcode
>> 4) & 0x1;
8158 int framesize
= (((ctx
->opcode
>> 20) & 0xf) << 4
8159 | (ctx
->opcode
& 0xf)) << 3;
8161 if (ctx
->opcode
& (1 << 7)) {
8162 gen_mips16_save(ctx
, xsregs
, aregs
,
8163 do_ra
, do_s0
, do_s1
,
8166 gen_mips16_restore(ctx
, xsregs
, aregs
,
8167 do_ra
, do_s0
, do_s1
,
8173 generate_exception(ctx
, EXCP_RI
);
8178 tcg_gen_movi_tl(cpu_gpr
[rx
], (uint16_t) imm
);
8181 tcg_gen_xori_tl(cpu_gpr
[24], cpu_gpr
[rx
], (uint16_t) imm
);
8183 #if defined(TARGET_MIPS64)
8185 gen_ldst(ctx
, OPC_SD
, ry
, rx
, offset
);
8189 gen_ldst(ctx
, OPC_LB
, ry
, rx
, offset
);
8192 gen_ldst(ctx
, OPC_LH
, ry
, rx
, offset
);
8195 gen_ldst(ctx
, OPC_LW
, rx
, 29, offset
);
8198 gen_ldst(ctx
, OPC_LW
, ry
, rx
, offset
);
8201 gen_ldst(ctx
, OPC_LBU
, ry
, rx
, offset
);
8204 gen_ldst(ctx
, OPC_LHU
, ry
, rx
, offset
);
8207 gen_ldst(ctx
, OPC_LWPC
, rx
, 0, offset
);
8209 #if defined(TARGET_MIPS64)
8211 gen_ldst(ctx
, OPC_LWU
, ry
, rx
, offset
);
8215 gen_ldst(ctx
, OPC_SB
, ry
, rx
, offset
);
8218 gen_ldst(ctx
, OPC_SH
, ry
, rx
, offset
);
8221 gen_ldst(ctx
, OPC_SW
, rx
, 29, offset
);
8224 gen_ldst(ctx
, OPC_SW
, ry
, rx
, offset
);
8226 #if defined(TARGET_MIPS64)
8228 decode_i64_mips16(env
, ctx
, ry
, funct
, offset
, 1);
8232 generate_exception(ctx
, EXCP_RI
);
8239 static int decode_mips16_opc (CPUState
*env
, DisasContext
*ctx
,
8244 int op
, cnvt_op
, op1
, offset
;
8248 op
= (ctx
->opcode
>> 11) & 0x1f;
8249 sa
= (ctx
->opcode
>> 2) & 0x7;
8250 sa
= sa
== 0 ? 8 : sa
;
8251 rx
= xlat((ctx
->opcode
>> 8) & 0x7);
8252 cnvt_op
= (ctx
->opcode
>> 5) & 0x7;
8253 ry
= xlat((ctx
->opcode
>> 5) & 0x7);
8254 op1
= offset
= ctx
->opcode
& 0x1f;
8259 case M16_OPC_ADDIUSP
:
8261 int16_t imm
= ((uint8_t) ctx
->opcode
) << 2;
8263 gen_arith_imm(env
, ctx
, OPC_ADDIU
, rx
, 29, imm
);
8266 case M16_OPC_ADDIUPC
:
8267 gen_addiupc(ctx
, rx
, ((uint8_t) ctx
->opcode
) << 2, 0, 0);
8270 offset
= (ctx
->opcode
& 0x7ff) << 1;
8271 offset
= (int16_t)(offset
<< 4) >> 4;
8272 gen_compute_branch(ctx
, OPC_BEQ
, 2, 0, 0, offset
);
8273 /* No delay slot, so just process as a normal instruction */
8276 offset
= lduw_code(ctx
->pc
+ 2);
8277 offset
= (((ctx
->opcode
& 0x1f) << 21)
8278 | ((ctx
->opcode
>> 5) & 0x1f) << 16
8280 op
= ((ctx
->opcode
>> 10) & 0x1) ? OPC_JALX
: OPC_JAL
;
8281 gen_compute_branch(ctx
, op
, 4, rx
, ry
, offset
);
8286 gen_compute_branch(ctx
, OPC_BEQ
, 2, rx
, 0, ((int8_t)ctx
->opcode
) << 1);
8287 /* No delay slot, so just process as a normal instruction */
8290 gen_compute_branch(ctx
, OPC_BNE
, 2, rx
, 0, ((int8_t)ctx
->opcode
) << 1);
8291 /* No delay slot, so just process as a normal instruction */
8294 switch (ctx
->opcode
& 0x3) {
8296 gen_shift_imm(env
, ctx
, OPC_SLL
, rx
, ry
, sa
);
8299 #if defined(TARGET_MIPS64)
8301 gen_shift_imm(env
, ctx
, OPC_DSLL
, rx
, ry
, sa
);
8303 generate_exception(ctx
, EXCP_RI
);
8307 gen_shift_imm(env
, ctx
, OPC_SRL
, rx
, ry
, sa
);
8310 gen_shift_imm(env
, ctx
, OPC_SRA
, rx
, ry
, sa
);
8314 #if defined(TARGET_MIPS64)
8317 gen_ldst(ctx
, OPC_LD
, ry
, rx
, offset
<< 3);
8322 int16_t imm
= (int8_t)((ctx
->opcode
& 0xf) << 4) >> 4;
8324 if ((ctx
->opcode
>> 4) & 1) {
8325 #if defined(TARGET_MIPS64)
8327 gen_arith_imm(env
, ctx
, OPC_DADDIU
, ry
, rx
, imm
);
8329 generate_exception(ctx
, EXCP_RI
);
8332 gen_arith_imm(env
, ctx
, OPC_ADDIU
, ry
, rx
, imm
);
8336 case M16_OPC_ADDIU8
:
8338 int16_t imm
= (int8_t) ctx
->opcode
;
8340 gen_arith_imm(env
, ctx
, OPC_ADDIU
, rx
, rx
, imm
);
8345 int16_t imm
= (uint8_t) ctx
->opcode
;
8347 gen_slt_imm(env
, OPC_SLTI
, 24, rx
, imm
);
8352 int16_t imm
= (uint8_t) ctx
->opcode
;
8354 gen_slt_imm(env
, OPC_SLTIU
, 24, rx
, imm
);
8361 funct
= (ctx
->opcode
>> 8) & 0x7;
8364 gen_compute_branch(ctx
, OPC_BEQ
, 2, 24, 0,
8365 ((int8_t)ctx
->opcode
) << 1);
8368 gen_compute_branch(ctx
, OPC_BNE
, 2, 24, 0,
8369 ((int8_t)ctx
->opcode
) << 1);
8372 gen_ldst(ctx
, OPC_SW
, 31, 29, (ctx
->opcode
& 0xff) << 2);
8375 gen_arith_imm(env
, ctx
, OPC_ADDIU
, 29, 29,
8376 ((int8_t)ctx
->opcode
) << 3);
8380 int do_ra
= ctx
->opcode
& (1 << 6);
8381 int do_s0
= ctx
->opcode
& (1 << 5);
8382 int do_s1
= ctx
->opcode
& (1 << 4);
8383 int framesize
= ctx
->opcode
& 0xf;
8385 if (framesize
== 0) {
8388 framesize
= framesize
<< 3;
8391 if (ctx
->opcode
& (1 << 7)) {
8392 gen_mips16_save(ctx
, 0, 0,
8393 do_ra
, do_s0
, do_s1
, framesize
);
8395 gen_mips16_restore(ctx
, 0, 0,
8396 do_ra
, do_s0
, do_s1
, framesize
);
8402 int rz
= xlat(ctx
->opcode
& 0x7);
8404 reg32
= (((ctx
->opcode
>> 3) & 0x3) << 3) |
8405 ((ctx
->opcode
>> 5) & 0x7);
8406 gen_arith(env
, ctx
, OPC_ADDU
, reg32
, rz
, 0);
8410 reg32
= ctx
->opcode
& 0x1f;
8411 gen_arith(env
, ctx
, OPC_ADDU
, ry
, reg32
, 0);
8414 generate_exception(ctx
, EXCP_RI
);
8421 int16_t imm
= (uint8_t) ctx
->opcode
;
8423 gen_arith_imm(env
, ctx
, OPC_ADDIU
, rx
, 0, imm
);
8428 int16_t imm
= (uint8_t) ctx
->opcode
;
8430 gen_logic_imm(env
, OPC_XORI
, 24, rx
, imm
);
8433 #if defined(TARGET_MIPS64)
8436 gen_ldst(ctx
, OPC_SD
, ry
, rx
, offset
<< 3);
8440 gen_ldst(ctx
, OPC_LB
, ry
, rx
, offset
);
8443 gen_ldst(ctx
, OPC_LH
, ry
, rx
, offset
<< 1);
8446 gen_ldst(ctx
, OPC_LW
, rx
, 29, ((uint8_t)ctx
->opcode
) << 2);
8449 gen_ldst(ctx
, OPC_LW
, ry
, rx
, offset
<< 2);
8452 gen_ldst(ctx
, OPC_LBU
, ry
, rx
, offset
);
8455 gen_ldst(ctx
, OPC_LHU
, ry
, rx
, offset
<< 1);
8458 gen_ldst(ctx
, OPC_LWPC
, rx
, 0, ((uint8_t)ctx
->opcode
) << 2);
8460 #if defined (TARGET_MIPS64)
8463 gen_ldst(ctx
, OPC_LWU
, ry
, rx
, offset
<< 2);
8467 gen_ldst(ctx
, OPC_SB
, ry
, rx
, offset
);
8470 gen_ldst(ctx
, OPC_SH
, ry
, rx
, offset
<< 1);
8473 gen_ldst(ctx
, OPC_SW
, rx
, 29, ((uint8_t)ctx
->opcode
) << 2);
8476 gen_ldst(ctx
, OPC_SW
, ry
, rx
, offset
<< 2);
8480 int rz
= xlat((ctx
->opcode
>> 2) & 0x7);
8483 switch (ctx
->opcode
& 0x3) {
8485 mips32_op
= OPC_ADDU
;
8488 mips32_op
= OPC_SUBU
;
8490 #if defined(TARGET_MIPS64)
8492 mips32_op
= OPC_DADDU
;
8496 mips32_op
= OPC_DSUBU
;
8501 generate_exception(ctx
, EXCP_RI
);
8505 gen_arith(env
, ctx
, mips32_op
, rz
, rx
, ry
);
8514 int nd
= (ctx
->opcode
>> 7) & 0x1;
8515 int link
= (ctx
->opcode
>> 6) & 0x1;
8516 int ra
= (ctx
->opcode
>> 5) & 0x1;
8519 op
= nd
? OPC_JALRC
: OPC_JALR
;
8524 gen_compute_branch(ctx
, op
, 2, ra
? 31 : rx
, 31, 0);
8531 /* XXX: not clear which exception should be raised
8532 * when in debug mode...
8534 check_insn(env
, ctx
, ISA_MIPS32
);
8535 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
8536 generate_exception(ctx
, EXCP_DBp
);
8538 generate_exception(ctx
, EXCP_DBp
);
8542 gen_slt(env
, OPC_SLT
, 24, rx
, ry
);
8545 gen_slt(env
, OPC_SLTU
, 24, rx
, ry
);
8548 generate_exception(ctx
, EXCP_BREAK
);
8551 gen_shift(env
, ctx
, OPC_SLLV
, ry
, rx
, ry
);
8554 gen_shift(env
, ctx
, OPC_SRLV
, ry
, rx
, ry
);
8557 gen_shift(env
, ctx
, OPC_SRAV
, ry
, rx
, ry
);
8559 #if defined (TARGET_MIPS64)
8562 gen_shift_imm(env
, ctx
, OPC_DSRL
, ry
, ry
, sa
);
8566 gen_logic(env
, OPC_XOR
, 24, rx
, ry
);
8569 gen_arith(env
, ctx
, OPC_SUBU
, rx
, 0, ry
);
8572 gen_logic(env
, OPC_AND
, rx
, rx
, ry
);
8575 gen_logic(env
, OPC_OR
, rx
, rx
, ry
);
8578 gen_logic(env
, OPC_XOR
, rx
, rx
, ry
);
8581 gen_logic(env
, OPC_NOR
, rx
, ry
, 0);
8584 gen_HILO(ctx
, OPC_MFHI
, rx
);
8588 case RR_RY_CNVT_ZEB
:
8589 tcg_gen_ext8u_tl(cpu_gpr
[rx
], cpu_gpr
[rx
]);
8591 case RR_RY_CNVT_ZEH
:
8592 tcg_gen_ext16u_tl(cpu_gpr
[rx
], cpu_gpr
[rx
]);
8594 case RR_RY_CNVT_SEB
:
8595 tcg_gen_ext8s_tl(cpu_gpr
[rx
], cpu_gpr
[rx
]);
8597 case RR_RY_CNVT_SEH
:
8598 tcg_gen_ext16s_tl(cpu_gpr
[rx
], cpu_gpr
[rx
]);
8600 #if defined (TARGET_MIPS64)
8601 case RR_RY_CNVT_ZEW
:
8603 tcg_gen_ext32u_tl(cpu_gpr
[rx
], cpu_gpr
[rx
]);
8605 case RR_RY_CNVT_SEW
:
8607 tcg_gen_ext32s_tl(cpu_gpr
[rx
], cpu_gpr
[rx
]);
8611 generate_exception(ctx
, EXCP_RI
);
8616 gen_HILO(ctx
, OPC_MFLO
, rx
);
8618 #if defined (TARGET_MIPS64)
8621 gen_shift_imm(env
, ctx
, OPC_DSRA
, ry
, ry
, sa
);
8625 gen_shift(env
, ctx
, OPC_DSLLV
, ry
, rx
, ry
);
8629 gen_shift(env
, ctx
, OPC_DSRLV
, ry
, rx
, ry
);
8633 gen_shift(env
, ctx
, OPC_DSRAV
, ry
, rx
, ry
);
8637 gen_muldiv(ctx
, OPC_MULT
, rx
, ry
);
8640 gen_muldiv(ctx
, OPC_MULTU
, rx
, ry
);
8643 gen_muldiv(ctx
, OPC_DIV
, rx
, ry
);
8646 gen_muldiv(ctx
, OPC_DIVU
, rx
, ry
);
8648 #if defined (TARGET_MIPS64)
8651 gen_muldiv(ctx
, OPC_DMULT
, rx
, ry
);
8655 gen_muldiv(ctx
, OPC_DMULTU
, rx
, ry
);
8659 gen_muldiv(ctx
, OPC_DDIV
, rx
, ry
);
8663 gen_muldiv(ctx
, OPC_DDIVU
, rx
, ry
);
8667 generate_exception(ctx
, EXCP_RI
);
8671 case M16_OPC_EXTEND
:
8672 decode_extended_mips16_opc(env
, ctx
, is_branch
);
8675 #if defined(TARGET_MIPS64)
8677 funct
= (ctx
->opcode
>> 8) & 0x7;
8678 decode_i64_mips16(env
, ctx
, ry
, funct
, offset
, 0);
8682 generate_exception(ctx
, EXCP_RI
);
8689 /* SmartMIPS extension to MIPS32 */
8691 #if defined(TARGET_MIPS64)
8693 /* MDMX extension to MIPS64 */
8697 static void decode_opc (CPUState
*env
, DisasContext
*ctx
, int *is_branch
)
8701 uint32_t op
, op1
, op2
;
8704 /* make sure instructions are on a word boundary */
8705 if (ctx
->pc
& 0x3) {
8706 env
->CP0_BadVAddr
= ctx
->pc
;
8707 generate_exception(ctx
, EXCP_AdEL
);
8711 /* Handle blikely not taken case */
8712 if ((ctx
->hflags
& MIPS_HFLAG_BMASK_BASE
) == MIPS_HFLAG_BL
) {
8713 int l1
= gen_new_label();
8715 MIPS_DEBUG("blikely condition (" TARGET_FMT_lx
")", ctx
->pc
+ 4);
8716 tcg_gen_brcondi_tl(TCG_COND_NE
, bcond
, 0, l1
);
8717 tcg_gen_movi_i32(hflags
, ctx
->hflags
& ~MIPS_HFLAG_BMASK
);
8718 gen_goto_tb(ctx
, 1, ctx
->pc
+ 4);
8722 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
)))
8723 tcg_gen_debug_insn_start(ctx
->pc
);
8725 op
= MASK_OP_MAJOR(ctx
->opcode
);
8726 rs
= (ctx
->opcode
>> 21) & 0x1f;
8727 rt
= (ctx
->opcode
>> 16) & 0x1f;
8728 rd
= (ctx
->opcode
>> 11) & 0x1f;
8729 sa
= (ctx
->opcode
>> 6) & 0x1f;
8730 imm
= (int16_t)ctx
->opcode
;
8733 op1
= MASK_SPECIAL(ctx
->opcode
);
8735 case OPC_SLL
: /* Shift with immediate */
8737 gen_shift_imm(env
, ctx
, op1
, rd
, rt
, sa
);
8740 switch ((ctx
->opcode
>> 21) & 0x1f) {
8742 /* rotr is decoded as srl on non-R2 CPUs */
8743 if (env
->insn_flags
& ISA_MIPS32R2
) {
8748 gen_shift_imm(env
, ctx
, op1
, rd
, rt
, sa
);
8751 generate_exception(ctx
, EXCP_RI
);
8755 case OPC_MOVN
: /* Conditional move */
8757 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
8758 gen_cond_move(env
, op1
, rd
, rs
, rt
);
8760 case OPC_ADD
... OPC_SUBU
:
8761 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
8763 case OPC_SLLV
: /* Shifts */
8765 gen_shift(env
, ctx
, op1
, rd
, rs
, rt
);
8768 switch ((ctx
->opcode
>> 6) & 0x1f) {
8770 /* rotrv is decoded as srlv on non-R2 CPUs */
8771 if (env
->insn_flags
& ISA_MIPS32R2
) {
8776 gen_shift(env
, ctx
, op1
, rd
, rs
, rt
);
8779 generate_exception(ctx
, EXCP_RI
);
8783 case OPC_SLT
: /* Set on less than */
8785 gen_slt(env
, op1
, rd
, rs
, rt
);
8787 case OPC_AND
: /* Logic*/
8791 gen_logic(env
, op1
, rd
, rs
, rt
);
8793 case OPC_MULT
... OPC_DIVU
:
8795 check_insn(env
, ctx
, INSN_VR54XX
);
8796 op1
= MASK_MUL_VR54XX(ctx
->opcode
);
8797 gen_mul_vr54xx(ctx
, op1
, rd
, rs
, rt
);
8799 gen_muldiv(ctx
, op1
, rs
, rt
);
8801 case OPC_JR
... OPC_JALR
:
8802 gen_compute_branch(ctx
, op1
, 4, rs
, rd
, sa
);
8805 case OPC_TGE
... OPC_TEQ
: /* Traps */
8807 gen_trap(ctx
, op1
, rs
, rt
, -1);
8809 case OPC_MFHI
: /* Move from HI/LO */
8811 gen_HILO(ctx
, op1
, rd
);
8814 case OPC_MTLO
: /* Move to HI/LO */
8815 gen_HILO(ctx
, op1
, rs
);
8817 case OPC_PMON
: /* Pmon entry point, also R4010 selsl */
8818 #ifdef MIPS_STRICT_STANDARD
8819 MIPS_INVAL("PMON / selsl");
8820 generate_exception(ctx
, EXCP_RI
);
8822 gen_helper_0i(pmon
, sa
);
8826 generate_exception(ctx
, EXCP_SYSCALL
);
8827 ctx
->bstate
= BS_STOP
;
8830 generate_exception(ctx
, EXCP_BREAK
);
8833 #ifdef MIPS_STRICT_STANDARD
8835 generate_exception(ctx
, EXCP_RI
);
8837 /* Implemented as RI exception for now. */
8838 MIPS_INVAL("spim (unofficial)");
8839 generate_exception(ctx
, EXCP_RI
);
8847 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
8848 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
8849 check_cp1_enabled(ctx
);
8850 gen_movci(ctx
, rd
, rs
, (ctx
->opcode
>> 18) & 0x7,
8851 (ctx
->opcode
>> 16) & 1);
8853 generate_exception_err(ctx
, EXCP_CpU
, 1);
8857 #if defined(TARGET_MIPS64)
8858 /* MIPS64 specific opcodes */
8863 check_insn(env
, ctx
, ISA_MIPS3
);
8865 gen_shift_imm(env
, ctx
, op1
, rd
, rt
, sa
);
8868 switch ((ctx
->opcode
>> 21) & 0x1f) {
8870 /* drotr is decoded as dsrl on non-R2 CPUs */
8871 if (env
->insn_flags
& ISA_MIPS32R2
) {
8876 check_insn(env
, ctx
, ISA_MIPS3
);
8878 gen_shift_imm(env
, ctx
, op1
, rd
, rt
, sa
);
8881 generate_exception(ctx
, EXCP_RI
);
8886 switch ((ctx
->opcode
>> 21) & 0x1f) {
8888 /* drotr32 is decoded as dsrl32 on non-R2 CPUs */
8889 if (env
->insn_flags
& ISA_MIPS32R2
) {
8894 check_insn(env
, ctx
, ISA_MIPS3
);
8896 gen_shift_imm(env
, ctx
, op1
, rd
, rt
, sa
);
8899 generate_exception(ctx
, EXCP_RI
);
8903 case OPC_DADD
... OPC_DSUBU
:
8904 check_insn(env
, ctx
, ISA_MIPS3
);
8906 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
8910 check_insn(env
, ctx
, ISA_MIPS3
);
8912 gen_shift(env
, ctx
, op1
, rd
, rs
, rt
);
8915 switch ((ctx
->opcode
>> 6) & 0x1f) {
8917 /* drotrv is decoded as dsrlv on non-R2 CPUs */
8918 if (env
->insn_flags
& ISA_MIPS32R2
) {
8923 check_insn(env
, ctx
, ISA_MIPS3
);
8925 gen_shift(env
, ctx
, op1
, rd
, rs
, rt
);
8928 generate_exception(ctx
, EXCP_RI
);
8932 case OPC_DMULT
... OPC_DDIVU
:
8933 check_insn(env
, ctx
, ISA_MIPS3
);
8935 gen_muldiv(ctx
, op1
, rs
, rt
);
8938 default: /* Invalid */
8939 MIPS_INVAL("special");
8940 generate_exception(ctx
, EXCP_RI
);
8945 op1
= MASK_SPECIAL2(ctx
->opcode
);
8947 case OPC_MADD
... OPC_MADDU
: /* Multiply and add/sub */
8948 case OPC_MSUB
... OPC_MSUBU
:
8949 check_insn(env
, ctx
, ISA_MIPS32
);
8950 gen_muldiv(ctx
, op1
, rs
, rt
);
8953 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
8957 check_insn(env
, ctx
, ISA_MIPS32
);
8958 gen_cl(ctx
, op1
, rd
, rs
);
8961 /* XXX: not clear which exception should be raised
8962 * when in debug mode...
8964 check_insn(env
, ctx
, ISA_MIPS32
);
8965 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
8966 generate_exception(ctx
, EXCP_DBp
);
8968 generate_exception(ctx
, EXCP_DBp
);
8972 #if defined(TARGET_MIPS64)
8975 check_insn(env
, ctx
, ISA_MIPS64
);
8977 gen_cl(ctx
, op1
, rd
, rs
);
8980 default: /* Invalid */
8981 MIPS_INVAL("special2");
8982 generate_exception(ctx
, EXCP_RI
);
8987 op1
= MASK_SPECIAL3(ctx
->opcode
);
8991 check_insn(env
, ctx
, ISA_MIPS32R2
);
8992 gen_bitops(ctx
, op1
, rt
, rs
, sa
, rd
);
8995 check_insn(env
, ctx
, ISA_MIPS32R2
);
8996 op2
= MASK_BSHFL(ctx
->opcode
);
8997 gen_bshfl(ctx
, op2
, rt
, rd
);
9000 check_insn(env
, ctx
, ISA_MIPS32R2
);
9002 TCGv t0
= tcg_temp_new();
9006 save_cpu_state(ctx
, 1);
9007 gen_helper_rdhwr_cpunum(t0
);
9008 gen_store_gpr(t0
, rt
);
9011 save_cpu_state(ctx
, 1);
9012 gen_helper_rdhwr_synci_step(t0
);
9013 gen_store_gpr(t0
, rt
);
9016 save_cpu_state(ctx
, 1);
9017 gen_helper_rdhwr_cc(t0
);
9018 gen_store_gpr(t0
, rt
);
9021 save_cpu_state(ctx
, 1);
9022 gen_helper_rdhwr_ccres(t0
);
9023 gen_store_gpr(t0
, rt
);
9026 #if defined(CONFIG_USER_ONLY)
9027 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, tls_value
));
9028 gen_store_gpr(t0
, rt
);
9031 /* XXX: Some CPUs implement this in hardware.
9032 Not supported yet. */
9034 default: /* Invalid */
9035 MIPS_INVAL("rdhwr");
9036 generate_exception(ctx
, EXCP_RI
);
9043 check_insn(env
, ctx
, ASE_MT
);
9045 TCGv t0
= tcg_temp_new();
9046 TCGv t1
= tcg_temp_new();
9048 gen_load_gpr(t0
, rt
);
9049 gen_load_gpr(t1
, rs
);
9050 gen_helper_fork(t0
, t1
);
9056 check_insn(env
, ctx
, ASE_MT
);
9058 TCGv t0
= tcg_temp_new();
9060 save_cpu_state(ctx
, 1);
9061 gen_load_gpr(t0
, rs
);
9062 gen_helper_yield(t0
, t0
);
9063 gen_store_gpr(t0
, rd
);
9067 #if defined(TARGET_MIPS64)
9068 case OPC_DEXTM
... OPC_DEXT
:
9069 case OPC_DINSM
... OPC_DINS
:
9070 check_insn(env
, ctx
, ISA_MIPS64R2
);
9072 gen_bitops(ctx
, op1
, rt
, rs
, sa
, rd
);
9075 check_insn(env
, ctx
, ISA_MIPS64R2
);
9077 op2
= MASK_DBSHFL(ctx
->opcode
);
9078 gen_bshfl(ctx
, op2
, rt
, rd
);
9081 default: /* Invalid */
9082 MIPS_INVAL("special3");
9083 generate_exception(ctx
, EXCP_RI
);
9088 op1
= MASK_REGIMM(ctx
->opcode
);
9090 case OPC_BLTZ
... OPC_BGEZL
: /* REGIMM branches */
9091 case OPC_BLTZAL
... OPC_BGEZALL
:
9092 gen_compute_branch(ctx
, op1
, 4, rs
, -1, imm
<< 2);
9095 case OPC_TGEI
... OPC_TEQI
: /* REGIMM traps */
9097 gen_trap(ctx
, op1
, rs
, -1, imm
);
9100 check_insn(env
, ctx
, ISA_MIPS32R2
);
9103 default: /* Invalid */
9104 MIPS_INVAL("regimm");
9105 generate_exception(ctx
, EXCP_RI
);
9110 check_cp0_enabled(ctx
);
9111 op1
= MASK_CP0(ctx
->opcode
);
9117 #if defined(TARGET_MIPS64)
9121 #ifndef CONFIG_USER_ONLY
9122 gen_cp0(env
, ctx
, op1
, rt
, rd
);
9123 #endif /* !CONFIG_USER_ONLY */
9125 case OPC_C0_FIRST
... OPC_C0_LAST
:
9126 #ifndef CONFIG_USER_ONLY
9127 gen_cp0(env
, ctx
, MASK_C0(ctx
->opcode
), rt
, rd
);
9128 #endif /* !CONFIG_USER_ONLY */
9131 #ifndef CONFIG_USER_ONLY
9133 TCGv t0
= tcg_temp_new();
9135 op2
= MASK_MFMC0(ctx
->opcode
);
9138 check_insn(env
, ctx
, ASE_MT
);
9139 gen_helper_dmt(t0
, t0
);
9140 gen_store_gpr(t0
, rt
);
9143 check_insn(env
, ctx
, ASE_MT
);
9144 gen_helper_emt(t0
, t0
);
9145 gen_store_gpr(t0
, rt
);
9148 check_insn(env
, ctx
, ASE_MT
);
9149 gen_helper_dvpe(t0
, t0
);
9150 gen_store_gpr(t0
, rt
);
9153 check_insn(env
, ctx
, ASE_MT
);
9154 gen_helper_evpe(t0
, t0
);
9155 gen_store_gpr(t0
, rt
);
9158 check_insn(env
, ctx
, ISA_MIPS32R2
);
9159 save_cpu_state(ctx
, 1);
9161 gen_store_gpr(t0
, rt
);
9162 /* Stop translation as we may have switched the execution mode */
9163 ctx
->bstate
= BS_STOP
;
9166 check_insn(env
, ctx
, ISA_MIPS32R2
);
9167 save_cpu_state(ctx
, 1);
9169 gen_store_gpr(t0
, rt
);
9170 /* Stop translation as we may have switched the execution mode */
9171 ctx
->bstate
= BS_STOP
;
9173 default: /* Invalid */
9174 MIPS_INVAL("mfmc0");
9175 generate_exception(ctx
, EXCP_RI
);
9180 #endif /* !CONFIG_USER_ONLY */
9183 check_insn(env
, ctx
, ISA_MIPS32R2
);
9184 gen_load_srsgpr(rt
, rd
);
9187 check_insn(env
, ctx
, ISA_MIPS32R2
);
9188 gen_store_srsgpr(rt
, rd
);
9192 generate_exception(ctx
, EXCP_RI
);
9196 case OPC_ADDI
: /* Arithmetic with immediate opcode */
9198 gen_arith_imm(env
, ctx
, op
, rt
, rs
, imm
);
9200 case OPC_SLTI
: /* Set on less than with immediate opcode */
9202 gen_slt_imm(env
, op
, rt
, rs
, imm
);
9204 case OPC_ANDI
: /* Arithmetic with immediate opcode */
9208 gen_logic_imm(env
, op
, rt
, rs
, imm
);
9210 case OPC_J
... OPC_JAL
: /* Jump */
9211 offset
= (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 2;
9212 gen_compute_branch(ctx
, op
, 4, rs
, rt
, offset
);
9215 case OPC_BEQ
... OPC_BGTZ
: /* Branch */
9216 case OPC_BEQL
... OPC_BGTZL
:
9217 gen_compute_branch(ctx
, op
, 4, rs
, rt
, imm
<< 2);
9220 case OPC_LB
... OPC_LWR
: /* Load and stores */
9221 case OPC_SB
... OPC_SW
:
9224 gen_ldst(ctx
, op
, rt
, rs
, imm
);
9227 gen_st_cond(ctx
, op
, rt
, rs
, imm
);
9230 check_insn(env
, ctx
, ISA_MIPS3
| ISA_MIPS32
);
9234 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
9238 /* Floating point (COP1). */
9243 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
9244 check_cp1_enabled(ctx
);
9245 gen_flt_ldst(ctx
, op
, rt
, rs
, imm
);
9247 generate_exception_err(ctx
, EXCP_CpU
, 1);
9252 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
9253 check_cp1_enabled(ctx
);
9254 op1
= MASK_CP1(ctx
->opcode
);
9258 check_insn(env
, ctx
, ISA_MIPS32R2
);
9263 gen_cp1(ctx
, op1
, rt
, rd
);
9265 #if defined(TARGET_MIPS64)
9268 check_insn(env
, ctx
, ISA_MIPS3
);
9269 gen_cp1(ctx
, op1
, rt
, rd
);
9275 check_insn(env
, ctx
, ASE_MIPS3D
);
9278 gen_compute_branch1(env
, ctx
, MASK_BC1(ctx
->opcode
),
9279 (rt
>> 2) & 0x7, imm
<< 2);
9287 gen_farith(ctx
, MASK_CP1_FUNC(ctx
->opcode
), rt
, rd
, sa
,
9292 generate_exception (ctx
, EXCP_RI
);
9296 generate_exception_err(ctx
, EXCP_CpU
, 1);
9306 /* COP2: Not implemented. */
9307 generate_exception_err(ctx
, EXCP_CpU
, 2);
9311 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
9312 check_cp1_enabled(ctx
);
9313 op1
= MASK_CP3(ctx
->opcode
);
9321 gen_flt3_ldst(ctx
, op1
, sa
, rd
, rs
, rt
);
9339 gen_flt3_arith(ctx
, op1
, sa
, rs
, rd
, rt
);
9343 generate_exception (ctx
, EXCP_RI
);
9347 generate_exception_err(ctx
, EXCP_CpU
, 1);
9351 #if defined(TARGET_MIPS64)
9352 /* MIPS64 opcodes */
9354 case OPC_LDL
... OPC_LDR
:
9355 case OPC_SDL
... OPC_SDR
:
9359 check_insn(env
, ctx
, ISA_MIPS3
);
9361 gen_ldst(ctx
, op
, rt
, rs
, imm
);
9364 check_insn(env
, ctx
, ISA_MIPS3
);
9366 gen_st_cond(ctx
, op
, rt
, rs
, imm
);
9370 check_insn(env
, ctx
, ISA_MIPS3
);
9372 gen_arith_imm(env
, ctx
, op
, rt
, rs
, imm
);
9376 check_insn(env
, ctx
, ASE_MIPS16
);
9377 offset
= (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 2;
9378 gen_compute_branch(ctx
, op
, 4, rs
, rt
, offset
);
9382 check_insn(env
, ctx
, ASE_MDMX
);
9383 /* MDMX: Not implemented. */
9384 default: /* Invalid */
9385 MIPS_INVAL("major opcode");
9386 generate_exception(ctx
, EXCP_RI
);
9392 gen_intermediate_code_internal (CPUState
*env
, TranslationBlock
*tb
,
9396 target_ulong pc_start
;
9397 uint16_t *gen_opc_end
;
9406 qemu_log("search pc %d\n", search_pc
);
9409 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
9412 ctx
.singlestep_enabled
= env
->singlestep_enabled
;
9414 ctx
.bstate
= BS_NONE
;
9415 /* Restore delay slot state from the tb context. */
9416 ctx
.hflags
= (uint32_t)tb
->flags
; /* FIXME: maybe use 64 bits here? */
9417 restore_cpu_state(env
, &ctx
);
9418 #ifdef CONFIG_USER_ONLY
9419 ctx
.mem_idx
= MIPS_HFLAG_UM
;
9421 ctx
.mem_idx
= ctx
.hflags
& MIPS_HFLAG_KSU
;
9424 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
9426 max_insns
= CF_COUNT_MASK
;
9428 qemu_log_mask(CPU_LOG_TB_CPU
, "------------------------------------------------\n");
9429 /* FIXME: This may print out stale hflags from env... */
9430 log_cpu_state_mask(CPU_LOG_TB_CPU
, env
, 0);
9432 LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb
, ctx
.mem_idx
, ctx
.hflags
);
9434 while (ctx
.bstate
== BS_NONE
) {
9435 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
9436 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
9437 if (bp
->pc
== ctx
.pc
) {
9438 save_cpu_state(&ctx
, 1);
9439 ctx
.bstate
= BS_BRANCH
;
9440 gen_helper_0i(raise_exception
, EXCP_DEBUG
);
9441 /* Include the breakpoint location or the tb won't
9442 * be flushed when it must be. */
9444 goto done_generating
;
9450 j
= gen_opc_ptr
- gen_opc_buf
;
9454 gen_opc_instr_start
[lj
++] = 0;
9456 gen_opc_pc
[lj
] = ctx
.pc
;
9457 gen_opc_hflags
[lj
] = ctx
.hflags
& MIPS_HFLAG_BMASK
;
9458 gen_opc_instr_start
[lj
] = 1;
9459 gen_opc_icount
[lj
] = num_insns
;
9461 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
9465 if (!(ctx
.hflags
& MIPS_HFLAG_M16
)) {
9466 ctx
.opcode
= ldl_code(ctx
.pc
);
9468 decode_opc(env
, &ctx
, &is_branch
);
9469 } else if (env
->insn_flags
& ASE_MIPS16
) {
9470 ctx
.opcode
= lduw_code(ctx
.pc
);
9471 insn_bytes
= decode_mips16_opc(env
, &ctx
, &is_branch
);
9473 generate_exception(&ctx
, EXCP_RI
);
9477 handle_delay_slot(env
, &ctx
, insn_bytes
);
9479 ctx
.pc
+= insn_bytes
;
9483 /* Execute a branch and its delay slot as a single instruction.
9484 This is what GDB expects and is consistent with what the
9485 hardware does (e.g. if a delay slot instruction faults, the
9486 reported PC is the PC of the branch). */
9487 if (env
->singlestep_enabled
&& (ctx
.hflags
& MIPS_HFLAG_BMASK
) == 0)
9490 if ((ctx
.pc
& (TARGET_PAGE_SIZE
- 1)) == 0)
9493 if (gen_opc_ptr
>= gen_opc_end
)
9496 if (num_insns
>= max_insns
)
9502 if (tb
->cflags
& CF_LAST_IO
)
9504 if (env
->singlestep_enabled
&& ctx
.bstate
!= BS_BRANCH
) {
9505 save_cpu_state(&ctx
, ctx
.bstate
== BS_NONE
);
9506 gen_helper_0i(raise_exception
, EXCP_DEBUG
);
9508 switch (ctx
.bstate
) {
9510 gen_helper_interrupt_restart();
9511 gen_goto_tb(&ctx
, 0, ctx
.pc
);
9514 save_cpu_state(&ctx
, 0);
9515 gen_goto_tb(&ctx
, 0, ctx
.pc
);
9518 gen_helper_interrupt_restart();
9527 gen_icount_end(tb
, num_insns
);
9528 *gen_opc_ptr
= INDEX_op_end
;
9530 j
= gen_opc_ptr
- gen_opc_buf
;
9533 gen_opc_instr_start
[lj
++] = 0;
9535 tb
->size
= ctx
.pc
- pc_start
;
9536 tb
->icount
= num_insns
;
9540 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
9541 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
9542 log_target_disas(pc_start
, ctx
.pc
- pc_start
, 0);
9545 qemu_log_mask(CPU_LOG_TB_CPU
, "---------------- %d %08x\n", ctx
.bstate
, ctx
.hflags
);
9549 void gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
9551 gen_intermediate_code_internal(env
, tb
, 0);
9554 void gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
9556 gen_intermediate_code_internal(env
, tb
, 1);
9559 static void fpu_dump_state(CPUState
*env
, FILE *f
,
9560 int (*fpu_fprintf
)(FILE *f
, const char *fmt
, ...),
9564 int is_fpu64
= !!(env
->hflags
& MIPS_HFLAG_F64
);
9566 #define printfpr(fp) \
9569 fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu: %13g\n", \
9570 (fp)->w[FP_ENDIAN_IDX], (fp)->d, (fp)->fd, \
9571 (fp)->fs[FP_ENDIAN_IDX], (fp)->fs[!FP_ENDIAN_IDX]); \
9574 tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX]; \
9575 tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX]; \
9576 fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu:%13g\n", \
9577 tmp.w[FP_ENDIAN_IDX], tmp.d, tmp.fd, \
9578 tmp.fs[FP_ENDIAN_IDX], tmp.fs[!FP_ENDIAN_IDX]); \
9583 fpu_fprintf(f
, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%08x(0x%02x)\n",
9584 env
->active_fpu
.fcr0
, env
->active_fpu
.fcr31
, is_fpu64
, env
->active_fpu
.fp_status
,
9585 get_float_exception_flags(&env
->active_fpu
.fp_status
));
9586 for (i
= 0; i
< 32; (is_fpu64
) ? i
++ : (i
+= 2)) {
9587 fpu_fprintf(f
, "%3s: ", fregnames
[i
]);
9588 printfpr(&env
->active_fpu
.fpr
[i
]);
9594 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
9595 /* Debug help: The architecture requires 32bit code to maintain proper
9596 sign-extended values on 64bit machines. */
9598 #define SIGN_EXT_P(val) ((((val) & ~0x7fffffff) == 0) || (((val) & ~0x7fffffff) == ~0x7fffffff))
9601 cpu_mips_check_sign_extensions (CPUState
*env
, FILE *f
,
9602 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
9607 if (!SIGN_EXT_P(env
->active_tc
.PC
))
9608 cpu_fprintf(f
, "BROKEN: pc=0x" TARGET_FMT_lx
"\n", env
->active_tc
.PC
);
9609 if (!SIGN_EXT_P(env
->active_tc
.HI
[0]))
9610 cpu_fprintf(f
, "BROKEN: HI=0x" TARGET_FMT_lx
"\n", env
->active_tc
.HI
[0]);
9611 if (!SIGN_EXT_P(env
->active_tc
.LO
[0]))
9612 cpu_fprintf(f
, "BROKEN: LO=0x" TARGET_FMT_lx
"\n", env
->active_tc
.LO
[0]);
9613 if (!SIGN_EXT_P(env
->btarget
))
9614 cpu_fprintf(f
, "BROKEN: btarget=0x" TARGET_FMT_lx
"\n", env
->btarget
);
9616 for (i
= 0; i
< 32; i
++) {
9617 if (!SIGN_EXT_P(env
->active_tc
.gpr
[i
]))
9618 cpu_fprintf(f
, "BROKEN: %s=0x" TARGET_FMT_lx
"\n", regnames
[i
], env
->active_tc
.gpr
[i
]);
9621 if (!SIGN_EXT_P(env
->CP0_EPC
))
9622 cpu_fprintf(f
, "BROKEN: EPC=0x" TARGET_FMT_lx
"\n", env
->CP0_EPC
);
9623 if (!SIGN_EXT_P(env
->lladdr
))
9624 cpu_fprintf(f
, "BROKEN: LLAddr=0x" TARGET_FMT_lx
"\n", env
->lladdr
);
9628 void cpu_dump_state (CPUState
*env
, FILE *f
,
9629 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
9634 cpu_fprintf(f
, "pc=0x" TARGET_FMT_lx
" HI=0x" TARGET_FMT_lx
" LO=0x" TARGET_FMT_lx
" ds %04x " TARGET_FMT_lx
" %d\n",
9635 env
->active_tc
.PC
, env
->active_tc
.HI
[0], env
->active_tc
.LO
[0],
9636 env
->hflags
, env
->btarget
, env
->bcond
);
9637 for (i
= 0; i
< 32; i
++) {
9639 cpu_fprintf(f
, "GPR%02d:", i
);
9640 cpu_fprintf(f
, " %s " TARGET_FMT_lx
, regnames
[i
], env
->active_tc
.gpr
[i
]);
9642 cpu_fprintf(f
, "\n");
9645 cpu_fprintf(f
, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx
"\n",
9646 env
->CP0_Status
, env
->CP0_Cause
, env
->CP0_EPC
);
9647 cpu_fprintf(f
, " Config0 0x%08x Config1 0x%08x LLAddr 0x" TARGET_FMT_lx
"\n",
9648 env
->CP0_Config0
, env
->CP0_Config1
, env
->lladdr
);
9649 if (env
->hflags
& MIPS_HFLAG_FPU
)
9650 fpu_dump_state(env
, f
, cpu_fprintf
, flags
);
9651 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
9652 cpu_mips_check_sign_extensions(env
, f
, cpu_fprintf
, flags
);
9656 static void mips_tcg_init(void)
9661 /* Initialize various static tables. */
9665 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
9666 TCGV_UNUSED(cpu_gpr
[0]);
9667 for (i
= 1; i
< 32; i
++)
9668 cpu_gpr
[i
] = tcg_global_mem_new(TCG_AREG0
,
9669 offsetof(CPUState
, active_tc
.gpr
[i
]),
9671 cpu_PC
= tcg_global_mem_new(TCG_AREG0
,
9672 offsetof(CPUState
, active_tc
.PC
), "PC");
9673 for (i
= 0; i
< MIPS_DSP_ACC
; i
++) {
9674 cpu_HI
[i
] = tcg_global_mem_new(TCG_AREG0
,
9675 offsetof(CPUState
, active_tc
.HI
[i
]),
9677 cpu_LO
[i
] = tcg_global_mem_new(TCG_AREG0
,
9678 offsetof(CPUState
, active_tc
.LO
[i
]),
9680 cpu_ACX
[i
] = tcg_global_mem_new(TCG_AREG0
,
9681 offsetof(CPUState
, active_tc
.ACX
[i
]),
9684 cpu_dspctrl
= tcg_global_mem_new(TCG_AREG0
,
9685 offsetof(CPUState
, active_tc
.DSPControl
),
9687 bcond
= tcg_global_mem_new(TCG_AREG0
,
9688 offsetof(CPUState
, bcond
), "bcond");
9689 btarget
= tcg_global_mem_new(TCG_AREG0
,
9690 offsetof(CPUState
, btarget
), "btarget");
9691 hflags
= tcg_global_mem_new_i32(TCG_AREG0
,
9692 offsetof(CPUState
, hflags
), "hflags");
9694 fpu_fcr0
= tcg_global_mem_new_i32(TCG_AREG0
,
9695 offsetof(CPUState
, active_fpu
.fcr0
),
9697 fpu_fcr31
= tcg_global_mem_new_i32(TCG_AREG0
,
9698 offsetof(CPUState
, active_fpu
.fcr31
),
9701 /* register helpers */
9702 #define GEN_HELPER 2
9708 #include "translate_init.c"
9710 CPUMIPSState
*cpu_mips_init (const char *cpu_model
)
9713 const mips_def_t
*def
;
9715 def
= cpu_mips_find_by_name(cpu_model
);
9718 env
= qemu_mallocz(sizeof(CPUMIPSState
));
9719 env
->cpu_model
= def
;
9720 env
->cpu_model_str
= cpu_model
;
9723 #ifndef CONFIG_USER_ONLY
9730 qemu_init_vcpu(env
);
9734 void cpu_reset (CPUMIPSState
*env
)
9736 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
9737 qemu_log("CPU Reset (CPU %d)\n", env
->cpu_index
);
9738 log_cpu_state(env
, 0);
9741 memset(env
, 0, offsetof(CPUMIPSState
, breakpoints
));
9744 /* Reset registers to their default values */
9745 env
->CP0_PRid
= env
->cpu_model
->CP0_PRid
;
9746 env
->CP0_Config0
= env
->cpu_model
->CP0_Config0
;
9747 #ifdef TARGET_WORDS_BIGENDIAN
9748 env
->CP0_Config0
|= (1 << CP0C0_BE
);
9750 env
->CP0_Config1
= env
->cpu_model
->CP0_Config1
;
9751 env
->CP0_Config2
= env
->cpu_model
->CP0_Config2
;
9752 env
->CP0_Config3
= env
->cpu_model
->CP0_Config3
;
9753 env
->CP0_Config6
= env
->cpu_model
->CP0_Config6
;
9754 env
->CP0_Config7
= env
->cpu_model
->CP0_Config7
;
9755 env
->CP0_LLAddr_rw_bitmask
= env
->cpu_model
->CP0_LLAddr_rw_bitmask
9756 << env
->cpu_model
->CP0_LLAddr_shift
;
9757 env
->CP0_LLAddr_shift
= env
->cpu_model
->CP0_LLAddr_shift
;
9758 env
->SYNCI_Step
= env
->cpu_model
->SYNCI_Step
;
9759 env
->CCRes
= env
->cpu_model
->CCRes
;
9760 env
->CP0_Status_rw_bitmask
= env
->cpu_model
->CP0_Status_rw_bitmask
;
9761 env
->CP0_TCStatus_rw_bitmask
= env
->cpu_model
->CP0_TCStatus_rw_bitmask
;
9762 env
->CP0_SRSCtl
= env
->cpu_model
->CP0_SRSCtl
;
9763 env
->current_tc
= 0;
9764 env
->SEGBITS
= env
->cpu_model
->SEGBITS
;
9765 env
->SEGMask
= (target_ulong
)((1ULL << env
->cpu_model
->SEGBITS
) - 1);
9766 #if defined(TARGET_MIPS64)
9767 if (env
->cpu_model
->insn_flags
& ISA_MIPS3
) {
9768 env
->SEGMask
|= 3ULL << 62;
9771 env
->PABITS
= env
->cpu_model
->PABITS
;
9772 env
->PAMask
= (target_ulong
)((1ULL << env
->cpu_model
->PABITS
) - 1);
9773 env
->CP0_SRSConf0_rw_bitmask
= env
->cpu_model
->CP0_SRSConf0_rw_bitmask
;
9774 env
->CP0_SRSConf0
= env
->cpu_model
->CP0_SRSConf0
;
9775 env
->CP0_SRSConf1_rw_bitmask
= env
->cpu_model
->CP0_SRSConf1_rw_bitmask
;
9776 env
->CP0_SRSConf1
= env
->cpu_model
->CP0_SRSConf1
;
9777 env
->CP0_SRSConf2_rw_bitmask
= env
->cpu_model
->CP0_SRSConf2_rw_bitmask
;
9778 env
->CP0_SRSConf2
= env
->cpu_model
->CP0_SRSConf2
;
9779 env
->CP0_SRSConf3_rw_bitmask
= env
->cpu_model
->CP0_SRSConf3_rw_bitmask
;
9780 env
->CP0_SRSConf3
= env
->cpu_model
->CP0_SRSConf3
;
9781 env
->CP0_SRSConf4_rw_bitmask
= env
->cpu_model
->CP0_SRSConf4_rw_bitmask
;
9782 env
->CP0_SRSConf4
= env
->cpu_model
->CP0_SRSConf4
;
9783 env
->insn_flags
= env
->cpu_model
->insn_flags
;
9785 #if defined(CONFIG_USER_ONLY)
9786 env
->hflags
= MIPS_HFLAG_UM
;
9787 /* Enable access to the SYNCI_Step register. */
9788 env
->CP0_HWREna
|= (1 << 1);
9789 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
9790 env
->hflags
|= MIPS_HFLAG_FPU
;
9792 #ifdef TARGET_MIPS64
9793 if (env
->active_fpu
.fcr0
& (1 << FCR0_F64
)) {
9794 env
->hflags
|= MIPS_HFLAG_F64
;
9798 if (env
->hflags
& MIPS_HFLAG_BMASK
) {
9799 /* If the exception was raised from a delay slot,
9800 come back to the jump. */
9801 env
->CP0_ErrorEPC
= env
->active_tc
.PC
- 4;
9803 env
->CP0_ErrorEPC
= env
->active_tc
.PC
;
9805 env
->active_tc
.PC
= (int32_t)0xBFC00000;
9806 env
->CP0_Random
= env
->tlb
->nb_tlb
- 1;
9807 env
->tlb
->tlb_in_use
= env
->tlb
->nb_tlb
;
9809 /* SMP not implemented */
9810 env
->CP0_EBase
= 0x80000000;
9811 env
->CP0_Status
= (1 << CP0St_BEV
) | (1 << CP0St_ERL
);
9812 /* vectored interrupts not implemented, timer on int 7,
9813 no performance counters. */
9814 env
->CP0_IntCtl
= 0xe0000000;
9818 for (i
= 0; i
< 7; i
++) {
9819 env
->CP0_WatchLo
[i
] = 0;
9820 env
->CP0_WatchHi
[i
] = 0x80000000;
9822 env
->CP0_WatchLo
[7] = 0;
9823 env
->CP0_WatchHi
[7] = 0;
9825 /* Count register increments in debug mode, EJTAG version 1 */
9826 env
->CP0_Debug
= (1 << CP0DB_CNT
) | (0x1 << CP0DB_VER
);
9827 env
->hflags
= MIPS_HFLAG_CP0
;
9829 #if defined(TARGET_MIPS64)
9830 if (env
->cpu_model
->insn_flags
& ISA_MIPS3
) {
9831 env
->hflags
|= MIPS_HFLAG_64
;
9834 env
->exception_index
= EXCP_NONE
;
9837 void gen_pc_load(CPUState
*env
, TranslationBlock
*tb
,
9838 unsigned long searched_pc
, int pc_pos
, void *puc
)
9840 env
->active_tc
.PC
= gen_opc_pc
[pc_pos
];
9841 env
->hflags
&= ~MIPS_HFLAG_BMASK
;
9842 env
->hflags
|= gen_opc_hflags
[pc_pos
];