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timer/cpus: fix some typos and update some comments
[qemu/kevin.git] / target-ppc / translate / vmx-impl.inc.c
blobb9841222ea332bb38da6ff3b9343f6659884c87d
1 /*
2 * translate/vmx-impl.c
3 *
4 * Altivec/VMX translation
5 */
6
7 /*** Altivec vector extension ***/
8 /* Altivec registers moves */
9
10 static inline TCGv_ptr gen_avr_ptr(int reg)
11 {
12 TCGv_ptr r = tcg_temp_new_ptr();
13 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
14 return r;
15 }
16
17 #define GEN_VR_LDX(name, opc2, opc3) \
18 static void glue(gen_, name)(DisasContext *ctx) \
19 { \
20 TCGv EA; \
21 if (unlikely(!ctx->altivec_enabled)) { \
22 gen_exception(ctx, POWERPC_EXCP_VPU); \
23 return; \
24 } \
25 gen_set_access_type(ctx, ACCESS_INT); \
26 EA = tcg_temp_new(); \
27 gen_addr_reg_index(ctx, EA); \
28 tcg_gen_andi_tl(EA, EA, ~0xf); \
29 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
30 64-bit byteswap already. */ \
31 if (ctx->le_mode) { \
32 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
33 tcg_gen_addi_tl(EA, EA, 8); \
34 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
35 } else { \
36 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
37 tcg_gen_addi_tl(EA, EA, 8); \
38 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
39 } \
40 tcg_temp_free(EA); \
41 }
42
43 #define GEN_VR_STX(name, opc2, opc3) \
44 static void gen_st##name(DisasContext *ctx) \
45 { \
46 TCGv EA; \
47 if (unlikely(!ctx->altivec_enabled)) { \
48 gen_exception(ctx, POWERPC_EXCP_VPU); \
49 return; \
50 } \
51 gen_set_access_type(ctx, ACCESS_INT); \
52 EA = tcg_temp_new(); \
53 gen_addr_reg_index(ctx, EA); \
54 tcg_gen_andi_tl(EA, EA, ~0xf); \
55 /* We only need to swap high and low halves. gen_qemu_st64 does necessary \
56 64-bit byteswap already. */ \
57 if (ctx->le_mode) { \
58 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
59 tcg_gen_addi_tl(EA, EA, 8); \
60 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
61 } else { \
62 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
63 tcg_gen_addi_tl(EA, EA, 8); \
64 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
65 } \
66 tcg_temp_free(EA); \
67 }
68
69 #define GEN_VR_LVE(name, opc2, opc3, size) \
70 static void gen_lve##name(DisasContext *ctx) \
71 { \
72 TCGv EA; \
73 TCGv_ptr rs; \
74 if (unlikely(!ctx->altivec_enabled)) { \
75 gen_exception(ctx, POWERPC_EXCP_VPU); \
76 return; \
77 } \
78 gen_set_access_type(ctx, ACCESS_INT); \
79 EA = tcg_temp_new(); \
80 gen_addr_reg_index(ctx, EA); \
81 if (size > 1) { \
82 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
83 } \
84 rs = gen_avr_ptr(rS(ctx->opcode)); \
85 gen_helper_lve##name(cpu_env, rs, EA); \
86 tcg_temp_free(EA); \
87 tcg_temp_free_ptr(rs); \
88 }
89
90 #define GEN_VR_STVE(name, opc2, opc3, size) \
91 static void gen_stve##name(DisasContext *ctx) \
92 { \
93 TCGv EA; \
94 TCGv_ptr rs; \
95 if (unlikely(!ctx->altivec_enabled)) { \
96 gen_exception(ctx, POWERPC_EXCP_VPU); \
97 return; \
98 } \
99 gen_set_access_type(ctx, ACCESS_INT); \
100 EA = tcg_temp_new(); \
101 gen_addr_reg_index(ctx, EA); \
102 if (size > 1) { \
103 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
104 } \
105 rs = gen_avr_ptr(rS(ctx->opcode)); \
106 gen_helper_stve##name(cpu_env, rs, EA); \
107 tcg_temp_free(EA); \
108 tcg_temp_free_ptr(rs); \
109 }
110
111 GEN_VR_LDX(lvx, 0x07, 0x03);
112 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
113 GEN_VR_LDX(lvxl, 0x07, 0x0B);
114
115 GEN_VR_LVE(bx, 0x07, 0x00, 1);
116 GEN_VR_LVE(hx, 0x07, 0x01, 2);
117 GEN_VR_LVE(wx, 0x07, 0x02, 4);
118
119 GEN_VR_STX(svx, 0x07, 0x07);
120 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
121 GEN_VR_STX(svxl, 0x07, 0x0F);
122
123 GEN_VR_STVE(bx, 0x07, 0x04, 1);
124 GEN_VR_STVE(hx, 0x07, 0x05, 2);
125 GEN_VR_STVE(wx, 0x07, 0x06, 4);
126
127 static void gen_lvsl(DisasContext *ctx)
128 {
129 TCGv_ptr rd;
130 TCGv EA;
131 if (unlikely(!ctx->altivec_enabled)) {
132 gen_exception(ctx, POWERPC_EXCP_VPU);
133 return;
134 }
135 EA = tcg_temp_new();
136 gen_addr_reg_index(ctx, EA);
137 rd = gen_avr_ptr(rD(ctx->opcode));
138 gen_helper_lvsl(rd, EA);
139 tcg_temp_free(EA);
140 tcg_temp_free_ptr(rd);
141 }
142
143 static void gen_lvsr(DisasContext *ctx)
144 {
145 TCGv_ptr rd;
146 TCGv EA;
147 if (unlikely(!ctx->altivec_enabled)) {
148 gen_exception(ctx, POWERPC_EXCP_VPU);
149 return;
150 }
151 EA = tcg_temp_new();
152 gen_addr_reg_index(ctx, EA);
153 rd = gen_avr_ptr(rD(ctx->opcode));
154 gen_helper_lvsr(rd, EA);
155 tcg_temp_free(EA);
156 tcg_temp_free_ptr(rd);
157 }
158
159 static void gen_mfvscr(DisasContext *ctx)
160 {
161 TCGv_i32 t;
162 if (unlikely(!ctx->altivec_enabled)) {
163 gen_exception(ctx, POWERPC_EXCP_VPU);
164 return;
165 }
166 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
167 t = tcg_temp_new_i32();
168 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
169 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
170 tcg_temp_free_i32(t);
171 }
172
173 static void gen_mtvscr(DisasContext *ctx)
174 {
175 TCGv_ptr p;
176 if (unlikely(!ctx->altivec_enabled)) {
177 gen_exception(ctx, POWERPC_EXCP_VPU);
178 return;
179 }
180 p = gen_avr_ptr(rB(ctx->opcode));
181 gen_helper_mtvscr(cpu_env, p);
182 tcg_temp_free_ptr(p);
183 }
184
185 /* Logical operations */
186 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
187 static void glue(gen_, name)(DisasContext *ctx) \
188 { \
189 if (unlikely(!ctx->altivec_enabled)) { \
190 gen_exception(ctx, POWERPC_EXCP_VPU); \
191 return; \
192 } \
193 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
194 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
195 }
196
197 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
198 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
199 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
200 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
201 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
202 GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
203 GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
204 GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
205
206 #define GEN_VXFORM(name, opc2, opc3) \
207 static void glue(gen_, name)(DisasContext *ctx) \
208 { \
209 TCGv_ptr ra, rb, rd; \
210 if (unlikely(!ctx->altivec_enabled)) { \
211 gen_exception(ctx, POWERPC_EXCP_VPU); \
212 return; \
213 } \
214 ra = gen_avr_ptr(rA(ctx->opcode)); \
215 rb = gen_avr_ptr(rB(ctx->opcode)); \
216 rd = gen_avr_ptr(rD(ctx->opcode)); \
217 gen_helper_##name (rd, ra, rb); \
218 tcg_temp_free_ptr(ra); \
219 tcg_temp_free_ptr(rb); \
220 tcg_temp_free_ptr(rd); \
221 }
222
223 #define GEN_VXFORM_ENV(name, opc2, opc3) \
224 static void glue(gen_, name)(DisasContext *ctx) \
225 { \
226 TCGv_ptr ra, rb, rd; \
227 if (unlikely(!ctx->altivec_enabled)) { \
228 gen_exception(ctx, POWERPC_EXCP_VPU); \
229 return; \
230 } \
231 ra = gen_avr_ptr(rA(ctx->opcode)); \
232 rb = gen_avr_ptr(rB(ctx->opcode)); \
233 rd = gen_avr_ptr(rD(ctx->opcode)); \
234 gen_helper_##name(cpu_env, rd, ra, rb); \
235 tcg_temp_free_ptr(ra); \
236 tcg_temp_free_ptr(rb); \
237 tcg_temp_free_ptr(rd); \
238 }
239
240 #define GEN_VXFORM3(name, opc2, opc3) \
241 static void glue(gen_, name)(DisasContext *ctx) \
242 { \
243 TCGv_ptr ra, rb, rc, rd; \
244 if (unlikely(!ctx->altivec_enabled)) { \
245 gen_exception(ctx, POWERPC_EXCP_VPU); \
246 return; \
247 } \
248 ra = gen_avr_ptr(rA(ctx->opcode)); \
249 rb = gen_avr_ptr(rB(ctx->opcode)); \
250 rc = gen_avr_ptr(rC(ctx->opcode)); \
251 rd = gen_avr_ptr(rD(ctx->opcode)); \
252 gen_helper_##name(rd, ra, rb, rc); \
253 tcg_temp_free_ptr(ra); \
254 tcg_temp_free_ptr(rb); \
255 tcg_temp_free_ptr(rc); \
256 tcg_temp_free_ptr(rd); \
257 }
258
259 /*
260 * Support for Altivec instruction pairs that use bit 31 (Rc) as
261 * an opcode bit. In general, these pairs come from different
262 * versions of the ISA, so we must also support a pair of flags for
263 * each instruction.
264 */
265 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
266 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
267 { \
268 if ((Rc(ctx->opcode) == 0) && \
269 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
270 gen_##name0(ctx); \
271 } else if ((Rc(ctx->opcode) == 1) && \
272 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
273 gen_##name1(ctx); \
274 } else { \
275 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
276 } \
277 }
278
279 GEN_VXFORM(vaddubm, 0, 0);
280 GEN_VXFORM(vadduhm, 0, 1);
281 GEN_VXFORM(vadduwm, 0, 2);
282 GEN_VXFORM(vaddudm, 0, 3);
283 GEN_VXFORM(vsububm, 0, 16);
284 GEN_VXFORM(vsubuhm, 0, 17);
285 GEN_VXFORM(vsubuwm, 0, 18);
286 GEN_VXFORM(vsubudm, 0, 19);
287 GEN_VXFORM(vmaxub, 1, 0);
288 GEN_VXFORM(vmaxuh, 1, 1);
289 GEN_VXFORM(vmaxuw, 1, 2);
290 GEN_VXFORM(vmaxud, 1, 3);
291 GEN_VXFORM(vmaxsb, 1, 4);
292 GEN_VXFORM(vmaxsh, 1, 5);
293 GEN_VXFORM(vmaxsw, 1, 6);
294 GEN_VXFORM(vmaxsd, 1, 7);
295 GEN_VXFORM(vminub, 1, 8);
296 GEN_VXFORM(vminuh, 1, 9);
297 GEN_VXFORM(vminuw, 1, 10);
298 GEN_VXFORM(vminud, 1, 11);
299 GEN_VXFORM(vminsb, 1, 12);
300 GEN_VXFORM(vminsh, 1, 13);
301 GEN_VXFORM(vminsw, 1, 14);
302 GEN_VXFORM(vminsd, 1, 15);
303 GEN_VXFORM(vavgub, 1, 16);
304 GEN_VXFORM(vabsdub, 1, 16);
305 GEN_VXFORM_DUAL(vavgub, PPC_ALTIVEC, PPC_NONE, \
306 vabsdub, PPC_NONE, PPC2_ISA300)
307 GEN_VXFORM(vavguh, 1, 17);
308 GEN_VXFORM(vabsduh, 1, 17);
309 GEN_VXFORM_DUAL(vavguh, PPC_ALTIVEC, PPC_NONE, \
310 vabsduh, PPC_NONE, PPC2_ISA300)
311 GEN_VXFORM(vavguw, 1, 18);
312 GEN_VXFORM(vabsduw, 1, 18);
313 GEN_VXFORM_DUAL(vavguw, PPC_ALTIVEC, PPC_NONE, \
314 vabsduw, PPC_NONE, PPC2_ISA300)
315 GEN_VXFORM(vavgsb, 1, 20);
316 GEN_VXFORM(vavgsh, 1, 21);
317 GEN_VXFORM(vavgsw, 1, 22);
318 GEN_VXFORM(vmrghb, 6, 0);
319 GEN_VXFORM(vmrghh, 6, 1);
320 GEN_VXFORM(vmrghw, 6, 2);
321 GEN_VXFORM(vmrglb, 6, 4);
322 GEN_VXFORM(vmrglh, 6, 5);
323 GEN_VXFORM(vmrglw, 6, 6);
324
325 static void gen_vmrgew(DisasContext *ctx)
326 {
327 TCGv_i64 tmp;
328 int VT, VA, VB;
329 if (unlikely(!ctx->altivec_enabled)) {
330 gen_exception(ctx, POWERPC_EXCP_VPU);
331 return;
332 }
333 VT = rD(ctx->opcode);
334 VA = rA(ctx->opcode);
335 VB = rB(ctx->opcode);
336 tmp = tcg_temp_new_i64();
337 tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32);
338 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32);
339 tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32);
340 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32);
341 tcg_temp_free_i64(tmp);
342 }
343
344 static void gen_vmrgow(DisasContext *ctx)
345 {
346 int VT, VA, VB;
347 if (unlikely(!ctx->altivec_enabled)) {
348 gen_exception(ctx, POWERPC_EXCP_VPU);
349 return;
350 }
351 VT = rD(ctx->opcode);
352 VA = rA(ctx->opcode);
353 VB = rB(ctx->opcode);
354
355 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32);
356 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32);
357 }
358
359 GEN_VXFORM(vmuloub, 4, 0);
360 GEN_VXFORM(vmulouh, 4, 1);
361 GEN_VXFORM(vmulouw, 4, 2);
362 GEN_VXFORM(vmuluwm, 4, 2);
363 GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
364 vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
365 GEN_VXFORM(vmulosb, 4, 4);
366 GEN_VXFORM(vmulosh, 4, 5);
367 GEN_VXFORM(vmulosw, 4, 6);
368 GEN_VXFORM(vmuleub, 4, 8);
369 GEN_VXFORM(vmuleuh, 4, 9);
370 GEN_VXFORM(vmuleuw, 4, 10);
371 GEN_VXFORM(vmulesb, 4, 12);
372 GEN_VXFORM(vmulesh, 4, 13);
373 GEN_VXFORM(vmulesw, 4, 14);
374 GEN_VXFORM(vslb, 2, 4);
375 GEN_VXFORM(vslh, 2, 5);
376 GEN_VXFORM(vslw, 2, 6);
377 GEN_VXFORM(vsld, 2, 23);
378 GEN_VXFORM(vsrb, 2, 8);
379 GEN_VXFORM(vsrh, 2, 9);
380 GEN_VXFORM(vsrw, 2, 10);
381 GEN_VXFORM(vsrd, 2, 27);
382 GEN_VXFORM(vsrab, 2, 12);
383 GEN_VXFORM(vsrah, 2, 13);
384 GEN_VXFORM(vsraw, 2, 14);
385 GEN_VXFORM(vsrad, 2, 15);
386 GEN_VXFORM(vsrv, 2, 28);
387 GEN_VXFORM(vslv, 2, 29);
388 GEN_VXFORM(vslo, 6, 16);
389 GEN_VXFORM(vsro, 6, 17);
390 GEN_VXFORM(vaddcuw, 0, 6);
391 GEN_VXFORM(vsubcuw, 0, 22);
392 GEN_VXFORM_ENV(vaddubs, 0, 8);
393 GEN_VXFORM_ENV(vadduhs, 0, 9);
394 GEN_VXFORM_ENV(vadduws, 0, 10);
395 GEN_VXFORM_ENV(vaddsbs, 0, 12);
396 GEN_VXFORM_ENV(vaddshs, 0, 13);
397 GEN_VXFORM_ENV(vaddsws, 0, 14);
398 GEN_VXFORM_ENV(vsububs, 0, 24);
399 GEN_VXFORM_ENV(vsubuhs, 0, 25);
400 GEN_VXFORM_ENV(vsubuws, 0, 26);
401 GEN_VXFORM_ENV(vsubsbs, 0, 28);
402 GEN_VXFORM_ENV(vsubshs, 0, 29);
403 GEN_VXFORM_ENV(vsubsws, 0, 30);
404 GEN_VXFORM(vadduqm, 0, 4);
405 GEN_VXFORM(vaddcuq, 0, 5);
406 GEN_VXFORM3(vaddeuqm, 30, 0);
407 GEN_VXFORM3(vaddecuq, 30, 0);
408 GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
409 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
410 GEN_VXFORM(vsubuqm, 0, 20);
411 GEN_VXFORM(vsubcuq, 0, 21);
412 GEN_VXFORM3(vsubeuqm, 31, 0);
413 GEN_VXFORM3(vsubecuq, 31, 0);
414 GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
415 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
416 GEN_VXFORM(vrlb, 2, 0);
417 GEN_VXFORM(vrlh, 2, 1);
418 GEN_VXFORM(vrlw, 2, 2);
419 GEN_VXFORM(vrld, 2, 3);
420 GEN_VXFORM(vsl, 2, 7);
421 GEN_VXFORM(vsr, 2, 11);
422 GEN_VXFORM_ENV(vpkuhum, 7, 0);
423 GEN_VXFORM_ENV(vpkuwum, 7, 1);
424 GEN_VXFORM_ENV(vpkudum, 7, 17);
425 GEN_VXFORM_ENV(vpkuhus, 7, 2);
426 GEN_VXFORM_ENV(vpkuwus, 7, 3);
427 GEN_VXFORM_ENV(vpkudus, 7, 19);
428 GEN_VXFORM_ENV(vpkshus, 7, 4);
429 GEN_VXFORM_ENV(vpkswus, 7, 5);
430 GEN_VXFORM_ENV(vpksdus, 7, 21);
431 GEN_VXFORM_ENV(vpkshss, 7, 6);
432 GEN_VXFORM_ENV(vpkswss, 7, 7);
433 GEN_VXFORM_ENV(vpksdss, 7, 23);
434 GEN_VXFORM(vpkpx, 7, 12);
435 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
436 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
437 GEN_VXFORM_ENV(vsum4shs, 4, 25);
438 GEN_VXFORM_ENV(vsum2sws, 4, 26);
439 GEN_VXFORM_ENV(vsumsws, 4, 30);
440 GEN_VXFORM_ENV(vaddfp, 5, 0);
441 GEN_VXFORM_ENV(vsubfp, 5, 1);
442 GEN_VXFORM_ENV(vmaxfp, 5, 16);
443 GEN_VXFORM_ENV(vminfp, 5, 17);
444
445 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
446 static void glue(gen_, name)(DisasContext *ctx) \
447 { \
448 TCGv_ptr ra, rb, rd; \
449 if (unlikely(!ctx->altivec_enabled)) { \
450 gen_exception(ctx, POWERPC_EXCP_VPU); \
451 return; \
452 } \
453 ra = gen_avr_ptr(rA(ctx->opcode)); \
454 rb = gen_avr_ptr(rB(ctx->opcode)); \
455 rd = gen_avr_ptr(rD(ctx->opcode)); \
456 gen_helper_##opname(cpu_env, rd, ra, rb); \
457 tcg_temp_free_ptr(ra); \
458 tcg_temp_free_ptr(rb); \
459 tcg_temp_free_ptr(rd); \
460 }
461
462 #define GEN_VXRFORM(name, opc2, opc3) \
463 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
464 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
465
466 /*
467 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
468 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
469 * come from different versions of the ISA, so we must also support a
470 * pair of flags for each instruction.
471 */
472 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
473 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
474 { \
475 if ((Rc(ctx->opcode) == 0) && \
476 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
477 if (Rc21(ctx->opcode) == 0) { \
478 gen_##name0(ctx); \
479 } else { \
480 gen_##name0##_(ctx); \
481 } \
482 } else if ((Rc(ctx->opcode) == 1) && \
483 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
484 if (Rc21(ctx->opcode) == 0) { \
485 gen_##name1(ctx); \
486 } else { \
487 gen_##name1##_(ctx); \
488 } \
489 } else { \
490 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
491 } \
492 }
493
494 GEN_VXRFORM(vcmpequb, 3, 0)
495 GEN_VXRFORM(vcmpequh, 3, 1)
496 GEN_VXRFORM(vcmpequw, 3, 2)
497 GEN_VXRFORM(vcmpequd, 3, 3)
498 GEN_VXRFORM(vcmpnezb, 3, 4)
499 GEN_VXRFORM(vcmpnezh, 3, 5)
500 GEN_VXRFORM(vcmpnezw, 3, 6)
501 GEN_VXRFORM(vcmpgtsb, 3, 12)
502 GEN_VXRFORM(vcmpgtsh, 3, 13)
503 GEN_VXRFORM(vcmpgtsw, 3, 14)
504 GEN_VXRFORM(vcmpgtsd, 3, 15)
505 GEN_VXRFORM(vcmpgtub, 3, 8)
506 GEN_VXRFORM(vcmpgtuh, 3, 9)
507 GEN_VXRFORM(vcmpgtuw, 3, 10)
508 GEN_VXRFORM(vcmpgtud, 3, 11)
509 GEN_VXRFORM(vcmpeqfp, 3, 3)
510 GEN_VXRFORM(vcmpgefp, 3, 7)
511 GEN_VXRFORM(vcmpgtfp, 3, 11)
512 GEN_VXRFORM(vcmpbfp, 3, 15)
513
514 GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
515 vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
516 GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
517 vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
518 GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
519 vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
520
521 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
522 static void glue(gen_, name)(DisasContext *ctx) \
523 { \
524 TCGv_ptr rd; \
525 TCGv_i32 simm; \
526 if (unlikely(!ctx->altivec_enabled)) { \
527 gen_exception(ctx, POWERPC_EXCP_VPU); \
528 return; \
529 } \
530 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
531 rd = gen_avr_ptr(rD(ctx->opcode)); \
532 gen_helper_##name (rd, simm); \
533 tcg_temp_free_i32(simm); \
534 tcg_temp_free_ptr(rd); \
535 }
536
537 GEN_VXFORM_SIMM(vspltisb, 6, 12);
538 GEN_VXFORM_SIMM(vspltish, 6, 13);
539 GEN_VXFORM_SIMM(vspltisw, 6, 14);
540
541 #define GEN_VXFORM_NOA(name, opc2, opc3) \
542 static void glue(gen_, name)(DisasContext *ctx) \
543 { \
544 TCGv_ptr rb, rd; \
545 if (unlikely(!ctx->altivec_enabled)) { \
546 gen_exception(ctx, POWERPC_EXCP_VPU); \
547 return; \
548 } \
549 rb = gen_avr_ptr(rB(ctx->opcode)); \
550 rd = gen_avr_ptr(rD(ctx->opcode)); \
551 gen_helper_##name (rd, rb); \
552 tcg_temp_free_ptr(rb); \
553 tcg_temp_free_ptr(rd); \
554 }
555
556 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
557 static void glue(gen_, name)(DisasContext *ctx) \
558 { \
559 TCGv_ptr rb, rd; \
560 \
561 if (unlikely(!ctx->altivec_enabled)) { \
562 gen_exception(ctx, POWERPC_EXCP_VPU); \
563 return; \
564 } \
565 rb = gen_avr_ptr(rB(ctx->opcode)); \
566 rd = gen_avr_ptr(rD(ctx->opcode)); \
567 gen_helper_##name(cpu_env, rd, rb); \
568 tcg_temp_free_ptr(rb); \
569 tcg_temp_free_ptr(rd); \
570 }
571
572 GEN_VXFORM_NOA(vupkhsb, 7, 8);
573 GEN_VXFORM_NOA(vupkhsh, 7, 9);
574 GEN_VXFORM_NOA(vupkhsw, 7, 25);
575 GEN_VXFORM_NOA(vupklsb, 7, 10);
576 GEN_VXFORM_NOA(vupklsh, 7, 11);
577 GEN_VXFORM_NOA(vupklsw, 7, 27);
578 GEN_VXFORM_NOA(vupkhpx, 7, 13);
579 GEN_VXFORM_NOA(vupklpx, 7, 15);
580 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
581 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
582 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
583 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
584 GEN_VXFORM_NOA_ENV(vrfim, 5, 11);
585 GEN_VXFORM_NOA_ENV(vrfin, 5, 8);
586 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
587 GEN_VXFORM_NOA_ENV(vrfiz, 5, 9);
588
589 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
590 static void glue(gen_, name)(DisasContext *ctx) \
591 { \
592 TCGv_ptr rd; \
593 TCGv_i32 simm; \
594 if (unlikely(!ctx->altivec_enabled)) { \
595 gen_exception(ctx, POWERPC_EXCP_VPU); \
596 return; \
597 } \
598 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
599 rd = gen_avr_ptr(rD(ctx->opcode)); \
600 gen_helper_##name (rd, simm); \
601 tcg_temp_free_i32(simm); \
602 tcg_temp_free_ptr(rd); \
603 }
604
605 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
606 static void glue(gen_, name)(DisasContext *ctx) \
607 { \
608 TCGv_ptr rb, rd; \
609 TCGv_i32 uimm; \
610 if (unlikely(!ctx->altivec_enabled)) { \
611 gen_exception(ctx, POWERPC_EXCP_VPU); \
612 return; \
613 } \
614 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
615 rb = gen_avr_ptr(rB(ctx->opcode)); \
616 rd = gen_avr_ptr(rD(ctx->opcode)); \
617 gen_helper_##name (rd, rb, uimm); \
618 tcg_temp_free_i32(uimm); \
619 tcg_temp_free_ptr(rb); \
620 tcg_temp_free_ptr(rd); \
621 }
622
623 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
624 static void glue(gen_, name)(DisasContext *ctx) \
625 { \
626 TCGv_ptr rb, rd; \
627 TCGv_i32 uimm; \
628 \
629 if (unlikely(!ctx->altivec_enabled)) { \
630 gen_exception(ctx, POWERPC_EXCP_VPU); \
631 return; \
632 } \
633 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
634 rb = gen_avr_ptr(rB(ctx->opcode)); \
635 rd = gen_avr_ptr(rD(ctx->opcode)); \
636 gen_helper_##name(cpu_env, rd, rb, uimm); \
637 tcg_temp_free_i32(uimm); \
638 tcg_temp_free_ptr(rb); \
639 tcg_temp_free_ptr(rd); \
640 }
641
642 GEN_VXFORM_UIMM(vspltb, 6, 8);
643 GEN_VXFORM_UIMM(vsplth, 6, 9);
644 GEN_VXFORM_UIMM(vspltw, 6, 10);
645 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
646 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
647 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
648 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
649
650 static void gen_vsldoi(DisasContext *ctx)
651 {
652 TCGv_ptr ra, rb, rd;
653 TCGv_i32 sh;
654 if (unlikely(!ctx->altivec_enabled)) {
655 gen_exception(ctx, POWERPC_EXCP_VPU);
656 return;
657 }
658 ra = gen_avr_ptr(rA(ctx->opcode));
659 rb = gen_avr_ptr(rB(ctx->opcode));
660 rd = gen_avr_ptr(rD(ctx->opcode));
661 sh = tcg_const_i32(VSH(ctx->opcode));
662 gen_helper_vsldoi (rd, ra, rb, sh);
663 tcg_temp_free_ptr(ra);
664 tcg_temp_free_ptr(rb);
665 tcg_temp_free_ptr(rd);
666 tcg_temp_free_i32(sh);
667 }
668
669 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
670 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
671 { \
672 TCGv_ptr ra, rb, rc, rd; \
673 if (unlikely(!ctx->altivec_enabled)) { \
674 gen_exception(ctx, POWERPC_EXCP_VPU); \
675 return; \
676 } \
677 ra = gen_avr_ptr(rA(ctx->opcode)); \
678 rb = gen_avr_ptr(rB(ctx->opcode)); \
679 rc = gen_avr_ptr(rC(ctx->opcode)); \
680 rd = gen_avr_ptr(rD(ctx->opcode)); \
681 if (Rc(ctx->opcode)) { \
682 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
683 } else { \
684 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
685 } \
686 tcg_temp_free_ptr(ra); \
687 tcg_temp_free_ptr(rb); \
688 tcg_temp_free_ptr(rc); \
689 tcg_temp_free_ptr(rd); \
690 }
691
692 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
693
694 static void gen_vmladduhm(DisasContext *ctx)
695 {
696 TCGv_ptr ra, rb, rc, rd;
697 if (unlikely(!ctx->altivec_enabled)) {
698 gen_exception(ctx, POWERPC_EXCP_VPU);
699 return;
700 }
701 ra = gen_avr_ptr(rA(ctx->opcode));
702 rb = gen_avr_ptr(rB(ctx->opcode));
703 rc = gen_avr_ptr(rC(ctx->opcode));
704 rd = gen_avr_ptr(rD(ctx->opcode));
705 gen_helper_vmladduhm(rd, ra, rb, rc);
706 tcg_temp_free_ptr(ra);
707 tcg_temp_free_ptr(rb);
708 tcg_temp_free_ptr(rc);
709 tcg_temp_free_ptr(rd);
710 }
711
712 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
713 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
714 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
715 GEN_VAFORM_PAIRED(vsel, vperm, 21)
716 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
717
718 GEN_VXFORM_NOA(vclzb, 1, 28)
719 GEN_VXFORM_NOA(vclzh, 1, 29)
720 GEN_VXFORM_NOA(vclzw, 1, 30)
721 GEN_VXFORM_NOA(vclzd, 1, 31)
722 GEN_VXFORM_NOA(vpopcntb, 1, 28)
723 GEN_VXFORM_NOA(vpopcnth, 1, 29)
724 GEN_VXFORM_NOA(vpopcntw, 1, 30)
725 GEN_VXFORM_NOA(vpopcntd, 1, 31)
726 GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
727 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
728 GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
729 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
730 GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
731 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
732 GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
733 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
734 GEN_VXFORM(vbpermq, 6, 21);
735 GEN_VXFORM_NOA(vgbbd, 6, 20);
736 GEN_VXFORM(vpmsumb, 4, 16)
737 GEN_VXFORM(vpmsumh, 4, 17)
738 GEN_VXFORM(vpmsumw, 4, 18)
739 GEN_VXFORM(vpmsumd, 4, 19)
740
741 #define GEN_BCD(op) \
742 static void gen_##op(DisasContext *ctx) \
743 { \
744 TCGv_ptr ra, rb, rd; \
745 TCGv_i32 ps; \
746 \
747 if (unlikely(!ctx->altivec_enabled)) { \
748 gen_exception(ctx, POWERPC_EXCP_VPU); \
749 return; \
750 } \
751 \
752 ra = gen_avr_ptr(rA(ctx->opcode)); \
753 rb = gen_avr_ptr(rB(ctx->opcode)); \
754 rd = gen_avr_ptr(rD(ctx->opcode)); \
755 \
756 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
757 \
758 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
759 \
760 tcg_temp_free_ptr(ra); \
761 tcg_temp_free_ptr(rb); \
762 tcg_temp_free_ptr(rd); \
763 tcg_temp_free_i32(ps); \
764 }
765
766 GEN_BCD(bcdadd)
767 GEN_BCD(bcdsub)
768
769 GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
770 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
771 GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
772 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
773 GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
774 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
775 GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
776 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
777
778 static void gen_vsbox(DisasContext *ctx)
779 {
780 TCGv_ptr ra, rd;
781 if (unlikely(!ctx->altivec_enabled)) {
782 gen_exception(ctx, POWERPC_EXCP_VPU);
783 return;
784 }
785 ra = gen_avr_ptr(rA(ctx->opcode));
786 rd = gen_avr_ptr(rD(ctx->opcode));
787 gen_helper_vsbox(rd, ra);
788 tcg_temp_free_ptr(ra);
789 tcg_temp_free_ptr(rd);
790 }
791
792 GEN_VXFORM(vcipher, 4, 20)
793 GEN_VXFORM(vcipherlast, 4, 20)
794 GEN_VXFORM(vncipher, 4, 21)
795 GEN_VXFORM(vncipherlast, 4, 21)
796
797 GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
798 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
799 GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
800 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
801
802 #define VSHASIGMA(op) \
803 static void gen_##op(DisasContext *ctx) \
804 { \
805 TCGv_ptr ra, rd; \
806 TCGv_i32 st_six; \
807 if (unlikely(!ctx->altivec_enabled)) { \
808 gen_exception(ctx, POWERPC_EXCP_VPU); \
809 return; \
810 } \
811 ra = gen_avr_ptr(rA(ctx->opcode)); \
812 rd = gen_avr_ptr(rD(ctx->opcode)); \
813 st_six = tcg_const_i32(rB(ctx->opcode)); \
814 gen_helper_##op(rd, ra, st_six); \
815 tcg_temp_free_ptr(ra); \
816 tcg_temp_free_ptr(rd); \
817 tcg_temp_free_i32(st_six); \
818 }
819
820 VSHASIGMA(vshasigmaw)
821 VSHASIGMA(vshasigmad)
822
823 GEN_VXFORM3(vpermxor, 22, 0xFF)
824 GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
825 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
826
827 #undef GEN_VR_LDX
828 #undef GEN_VR_STX
829 #undef GEN_VR_LVE
830 #undef GEN_VR_STVE
831
832 #undef GEN_VX_LOGICAL
833 #undef GEN_VX_LOGICAL_207
834 #undef GEN_VXFORM
835 #undef GEN_VXFORM_207
836 #undef GEN_VXFORM_DUAL
837 #undef GEN_VXRFORM_DUAL
838 #undef GEN_VXRFORM1
839 #undef GEN_VXRFORM
840 #undef GEN_VXFORM_SIMM
841 #undef GEN_VXFORM_NOA
842 #undef GEN_VXFORM_UIMM
843 #undef GEN_VAFORM_PAIRED
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