2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 #include "qemu/osdep.h"
29 #include "qemu/units.h"
30 #include "qapi/error.h"
32 #include "sysemu/sysemu.h"
33 #include "hw/boards.h"
34 #include "hw/loader.h"
35 #include "hw/qdev-properties.h"
37 #include "exec/memory.h"
38 #include "hw/char/serial.h"
40 #include "hw/sysbus.h"
41 #include "hw/block/flash.h"
42 #include "chardev/char.h"
43 #include "sysemu/device_tree.h"
44 #include "sysemu/reset.h"
45 #include "sysemu/runstate.h"
46 #include "qemu/error-report.h"
47 #include "qemu/option.h"
48 #include "bootparam.h"
49 #include "xtensa_memory.h"
50 #include "hw/xtensa/mx_pic.h"
51 #include "migration/vmstate.h"
53 typedef struct XtfpgaFlashDesc
{
60 typedef struct XtfpgaBoardDesc
{
61 const XtfpgaFlashDesc
*flash
;
66 typedef struct XtfpgaFpgaState
{
73 static void xtfpga_fpga_reset(void *opaque
)
75 XtfpgaFpgaState
*s
= opaque
;
81 static uint64_t xtfpga_fpga_read(void *opaque
, hwaddr addr
,
84 XtfpgaFpgaState
*s
= opaque
;
87 case 0x0: /*build date code*/
90 case 0x4: /*processor clock frequency, Hz*/
93 case 0x8: /*LEDs (off = 0, on = 1)*/
96 case 0xc: /*DIP switches (off = 0, on = 1)*/
102 static void xtfpga_fpga_write(void *opaque
, hwaddr addr
,
103 uint64_t val
, unsigned size
)
105 XtfpgaFpgaState
*s
= opaque
;
108 case 0x8: /*LEDs (off = 0, on = 1)*/
112 case 0x10: /*board reset*/
114 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
120 static const MemoryRegionOps xtfpga_fpga_ops
= {
121 .read
= xtfpga_fpga_read
,
122 .write
= xtfpga_fpga_write
,
123 .endianness
= DEVICE_NATIVE_ENDIAN
,
126 static XtfpgaFpgaState
*xtfpga_fpga_init(MemoryRegion
*address_space
,
127 hwaddr base
, uint32_t freq
)
129 XtfpgaFpgaState
*s
= g_new(XtfpgaFpgaState
, 1);
131 memory_region_init_io(&s
->iomem
, NULL
, &xtfpga_fpga_ops
, s
,
132 "xtfpga.fpga", 0x10000);
133 memory_region_add_subregion(address_space
, base
, &s
->iomem
);
135 xtfpga_fpga_reset(s
);
136 qemu_register_reset(xtfpga_fpga_reset
, s
);
140 static void xtfpga_net_init(MemoryRegion
*address_space
,
150 dev
= qemu_create_nic_device("open_eth", true, NULL
);
155 s
= SYS_BUS_DEVICE(dev
);
156 sysbus_realize_and_unref(s
, &error_fatal
);
157 sysbus_connect_irq(s
, 0, irq
);
158 memory_region_add_subregion(address_space
, base
,
159 sysbus_mmio_get_region(s
, 0));
160 memory_region_add_subregion(address_space
, descriptors
,
161 sysbus_mmio_get_region(s
, 1));
163 ram
= g_malloc(sizeof(*ram
));
164 memory_region_init_ram_nomigrate(ram
, OBJECT(s
), "open_eth.ram", 16 * KiB
,
166 vmstate_register_ram_global(ram
);
167 memory_region_add_subregion(address_space
, buffers
, ram
);
170 static PFlashCFI01
*xtfpga_flash_init(MemoryRegion
*address_space
,
171 const XtfpgaBoardDesc
*board
,
172 DriveInfo
*dinfo
, int be
)
175 DeviceState
*dev
= qdev_new(TYPE_PFLASH_CFI01
);
177 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(dinfo
));
178 qdev_prop_set_uint32(dev
, "num-blocks",
179 board
->flash
->size
/ board
->flash
->sector_size
);
180 qdev_prop_set_uint64(dev
, "sector-length", board
->flash
->sector_size
);
181 qdev_prop_set_uint8(dev
, "width", 2);
182 qdev_prop_set_bit(dev
, "big-endian", be
);
183 qdev_prop_set_string(dev
, "name", "xtfpga.io.flash");
184 s
= SYS_BUS_DEVICE(dev
);
185 sysbus_realize_and_unref(s
, &error_fatal
);
186 memory_region_add_subregion(address_space
, board
->flash
->base
,
187 sysbus_mmio_get_region(s
, 0));
188 return PFLASH_CFI01(dev
);
191 static uint64_t translate_phys_addr(void *opaque
, uint64_t addr
)
193 XtensaCPU
*cpu
= opaque
;
195 return cpu_get_phys_page_debug(CPU(cpu
), addr
);
198 static void xtfpga_reset(void *opaque
)
200 XtensaCPU
*cpu
= opaque
;
205 static uint64_t xtfpga_io_read(void *opaque
, hwaddr addr
,
211 static void xtfpga_io_write(void *opaque
, hwaddr addr
,
212 uint64_t val
, unsigned size
)
216 static const MemoryRegionOps xtfpga_io_ops
= {
217 .read
= xtfpga_io_read
,
218 .write
= xtfpga_io_write
,
219 .endianness
= DEVICE_NATIVE_ENDIAN
,
222 static void xtfpga_init(const XtfpgaBoardDesc
*board
, MachineState
*machine
)
224 MemoryRegion
*system_memory
= get_system_memory();
225 XtensaCPU
*cpu
= NULL
;
226 CPUXtensaState
*env
= NULL
;
227 MemoryRegion
*system_io
;
228 XtensaMxPic
*mx_pic
= NULL
;
231 PFlashCFI01
*flash
= NULL
;
232 const char *kernel_filename
= machine
->kernel_filename
;
233 const char *kernel_cmdline
= machine
->kernel_cmdline
;
234 const char *dtb_filename
= machine
->dtb
;
235 const char *initrd_filename
= machine
->initrd_filename
;
236 const unsigned system_io_size
= 224 * MiB
;
237 uint32_t freq
= 10000000;
239 unsigned int smp_cpus
= machine
->smp
.cpus
;
242 mx_pic
= xtensa_mx_pic_init(31);
243 qemu_register_reset(xtensa_mx_pic_reset
, mx_pic
);
245 for (n
= 0; n
< smp_cpus
; n
++) {
246 CPUXtensaState
*cenv
= NULL
;
248 cpu
= XTENSA_CPU(cpu_create(machine
->cpu_type
));
252 freq
= env
->config
->clock_freq_khz
* 1000;
256 MemoryRegion
*mx_eri
;
258 mx_eri
= xtensa_mx_pic_register_cpu(mx_pic
,
259 xtensa_get_extints(cenv
),
260 xtensa_get_runstall(cenv
));
261 memory_region_add_subregion(xtensa_get_er_region(cenv
),
264 cenv
->sregs
[PRID
] = n
;
265 xtensa_select_static_vectors(cenv
, n
!= 0);
266 qemu_register_reset(xtfpga_reset
, cpu
);
267 /* Need MMU initialized prior to ELF loading,
268 * so that ELF gets loaded into virtual addresses
273 extints
= xtensa_mx_pic_get_extints(mx_pic
);
275 extints
= xtensa_get_extints(env
);
279 XtensaMemory sysram
= env
->config
->sysram
;
281 sysram
.location
[0].size
= machine
->ram_size
;
282 xtensa_create_memory_regions(&env
->config
->instrom
, "xtensa.instrom",
284 xtensa_create_memory_regions(&env
->config
->instram
, "xtensa.instram",
286 xtensa_create_memory_regions(&env
->config
->datarom
, "xtensa.datarom",
288 xtensa_create_memory_regions(&env
->config
->dataram
, "xtensa.dataram",
290 xtensa_create_memory_regions(&sysram
, "xtensa.sysram",
294 system_io
= g_malloc(sizeof(*system_io
));
295 memory_region_init_io(system_io
, NULL
, &xtfpga_io_ops
, NULL
, "xtfpga.io",
297 memory_region_add_subregion(system_memory
, board
->io
[0], system_io
);
299 MemoryRegion
*io
= g_malloc(sizeof(*io
));
301 memory_region_init_alias(io
, NULL
, "xtfpga.io.cached",
302 system_io
, 0, system_io_size
);
303 memory_region_add_subregion(system_memory
, board
->io
[1], io
);
305 xtfpga_fpga_init(system_io
, 0x0d020000, freq
);
306 xtfpga_net_init(system_io
, 0x0d030000, 0x0d030400, 0x0d800000, extints
[1]);
308 serial_mm_init(system_io
, 0x0d050020, 2, extints
[0],
309 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN
);
311 dinfo
= drive_get(IF_PFLASH
, 0, 0);
313 flash
= xtfpga_flash_init(system_io
, board
, dinfo
, TARGET_BIG_ENDIAN
);
316 /* Use presence of kernel file name as 'boot from SRAM' switch. */
317 if (kernel_filename
) {
318 uint32_t entry_point
= env
->pc
;
319 size_t bp_size
= 3 * get_tag_size(0); /* first/last and memory tags */
320 uint32_t tagptr
= env
->config
->sysrom
.location
[0].addr
+
323 BpMemInfo memory_location
= {
324 .type
= tswap32(MEMORY_TYPE_CONVENTIONAL
),
325 .start
= tswap32(env
->config
->sysram
.location
[0].addr
),
326 .end
= tswap32(env
->config
->sysram
.location
[0].addr
+
329 uint32_t lowmem_end
= machine
->ram_size
< 0x08000000 ?
330 machine
->ram_size
: 0x08000000;
331 uint32_t cur_lowmem
= QEMU_ALIGN_UP(lowmem_end
/ 2, 4096);
333 lowmem_end
+= env
->config
->sysram
.location
[0].addr
;
334 cur_lowmem
+= env
->config
->sysram
.location
[0].addr
;
336 xtensa_create_memory_regions(&env
->config
->sysrom
, "xtensa.sysrom",
339 if (kernel_cmdline
) {
340 bp_size
+= get_tag_size(strlen(kernel_cmdline
) + 1);
343 bp_size
+= get_tag_size(sizeof(uint32_t));
345 if (initrd_filename
) {
346 bp_size
+= get_tag_size(sizeof(BpMemInfo
));
349 /* Put kernel bootparameters to the end of that SRAM */
350 tagptr
= (tagptr
- bp_size
) & ~0xff;
351 cur_tagptr
= put_tag(tagptr
, BP_TAG_FIRST
, 0, NULL
);
352 cur_tagptr
= put_tag(cur_tagptr
, BP_TAG_MEMORY
,
353 sizeof(memory_location
), &memory_location
);
355 if (kernel_cmdline
) {
356 cur_tagptr
= put_tag(cur_tagptr
, BP_TAG_COMMAND_LINE
,
357 strlen(kernel_cmdline
) + 1, kernel_cmdline
);
362 void *fdt
= load_device_tree(dtb_filename
, &fdt_size
);
363 uint32_t dtb_addr
= tswap32(cur_lowmem
);
366 error_report("could not load DTB '%s'", dtb_filename
);
370 cpu_physical_memory_write(cur_lowmem
, fdt
, fdt_size
);
371 cur_tagptr
= put_tag(cur_tagptr
, BP_TAG_FDT
,
372 sizeof(dtb_addr
), &dtb_addr
);
373 cur_lowmem
= QEMU_ALIGN_UP(cur_lowmem
+ fdt_size
, 4 * KiB
);
378 error_report("could not load DTB '%s': "
379 "FDT support is not configured in QEMU",
384 if (initrd_filename
) {
385 BpMemInfo initrd_location
= { 0 };
386 int initrd_size
= load_ramdisk(initrd_filename
, cur_lowmem
,
387 lowmem_end
- cur_lowmem
);
389 if (initrd_size
< 0) {
390 initrd_size
= load_image_targphys(initrd_filename
,
392 lowmem_end
- cur_lowmem
);
394 if (initrd_size
< 0) {
395 error_report("could not load initrd '%s'", initrd_filename
);
398 initrd_location
.start
= tswap32(cur_lowmem
);
399 initrd_location
.end
= tswap32(cur_lowmem
+ initrd_size
);
400 cur_tagptr
= put_tag(cur_tagptr
, BP_TAG_INITRD
,
401 sizeof(initrd_location
), &initrd_location
);
402 cur_lowmem
= QEMU_ALIGN_UP(cur_lowmem
+ initrd_size
, 4 * KiB
);
404 cur_tagptr
= put_tag(cur_tagptr
, BP_TAG_LAST
, 0, NULL
);
405 env
->regs
[2] = tagptr
;
408 int success
= load_elf(kernel_filename
, NULL
, translate_phys_addr
, cpu
,
409 &elf_entry
, NULL
, NULL
, NULL
, TARGET_BIG_ENDIAN
,
412 entry_point
= elf_entry
;
416 success
= load_uimage(kernel_filename
, &ep
, NULL
, &is_linux
,
417 translate_phys_addr
, cpu
);
418 if (success
> 0 && is_linux
) {
421 error_report("could not load kernel '%s'",
426 if (entry_point
!= env
->pc
) {
428 #if TARGET_BIG_ENDIAN
429 0x60, 0x00, 0x08, /* j 1f */
430 0x00, /* .literal_position */
431 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
432 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */
434 0x10, 0xff, 0xfe, /* l32r a0, entry_pc */
435 0x12, 0xff, 0xfe, /* l32r a2, entry_a2 */
436 0x0a, 0x00, 0x00, /* jx a0 */
438 0x06, 0x02, 0x00, /* j 1f */
439 0x00, /* .literal_position */
440 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
441 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */
443 0x01, 0xfe, 0xff, /* l32r a0, entry_pc */
444 0x21, 0xfe, 0xff, /* l32r a2, entry_a2 */
445 0xa0, 0x00, 0x00, /* jx a0 */
448 uint32_t entry_pc
= tswap32(entry_point
);
449 uint32_t entry_a2
= tswap32(tagptr
);
451 memcpy(boot
+ 4, &entry_pc
, sizeof(entry_pc
));
452 memcpy(boot
+ 8, &entry_a2
, sizeof(entry_a2
));
453 cpu_physical_memory_write(env
->pc
, boot
, sizeof(boot
));
457 MemoryRegion
*flash_mr
= pflash_cfi01_get_memory(flash
);
458 MemoryRegion
*flash_io
= g_malloc(sizeof(*flash_io
));
459 uint32_t size
= env
->config
->sysrom
.location
[0].size
;
461 if (board
->flash
->size
- board
->flash
->boot_base
< size
) {
462 size
= board
->flash
->size
- board
->flash
->boot_base
;
465 memory_region_init_alias(flash_io
, NULL
, "xtfpga.flash",
466 flash_mr
, board
->flash
->boot_base
, size
);
467 memory_region_add_subregion(system_memory
,
468 env
->config
->sysrom
.location
[0].addr
,
471 xtensa_create_memory_regions(&env
->config
->sysrom
, "xtensa.sysrom",
477 #define XTFPGA_MMU_RESERVED_MEMORY_SIZE (128 * MiB)
479 static const hwaddr xtfpga_mmu_io
[2] = {
483 static const hwaddr xtfpga_nommu_io
[2] = {
488 static const XtfpgaFlashDesc lx60_flash
= {
491 .sector_size
= 0x10000,
494 static void xtfpga_lx60_init(MachineState
*machine
)
496 static const XtfpgaBoardDesc lx60_board
= {
497 .flash
= &lx60_flash
,
498 .sram_size
= 0x20000,
501 xtfpga_init(&lx60_board
, machine
);
504 static void xtfpga_lx60_nommu_init(MachineState
*machine
)
506 static const XtfpgaBoardDesc lx60_board
= {
507 .flash
= &lx60_flash
,
508 .sram_size
= 0x20000,
509 .io
= xtfpga_nommu_io
,
511 xtfpga_init(&lx60_board
, machine
);
514 static const XtfpgaFlashDesc lx200_flash
= {
517 .sector_size
= 0x20000,
520 static void xtfpga_lx200_init(MachineState
*machine
)
522 static const XtfpgaBoardDesc lx200_board
= {
523 .flash
= &lx200_flash
,
524 .sram_size
= 0x2000000,
527 xtfpga_init(&lx200_board
, machine
);
530 static void xtfpga_lx200_nommu_init(MachineState
*machine
)
532 static const XtfpgaBoardDesc lx200_board
= {
533 .flash
= &lx200_flash
,
534 .sram_size
= 0x2000000,
535 .io
= xtfpga_nommu_io
,
537 xtfpga_init(&lx200_board
, machine
);
540 static const XtfpgaFlashDesc ml605_flash
= {
543 .sector_size
= 0x20000,
546 static void xtfpga_ml605_init(MachineState
*machine
)
548 static const XtfpgaBoardDesc ml605_board
= {
549 .flash
= &ml605_flash
,
550 .sram_size
= 0x2000000,
553 xtfpga_init(&ml605_board
, machine
);
556 static void xtfpga_ml605_nommu_init(MachineState
*machine
)
558 static const XtfpgaBoardDesc ml605_board
= {
559 .flash
= &ml605_flash
,
560 .sram_size
= 0x2000000,
561 .io
= xtfpga_nommu_io
,
563 xtfpga_init(&ml605_board
, machine
);
566 static const XtfpgaFlashDesc kc705_flash
= {
569 .boot_base
= 0x06000000,
570 .sector_size
= 0x20000,
573 static void xtfpga_kc705_init(MachineState
*machine
)
575 static const XtfpgaBoardDesc kc705_board
= {
576 .flash
= &kc705_flash
,
577 .sram_size
= 0x2000000,
580 xtfpga_init(&kc705_board
, machine
);
583 static void xtfpga_kc705_nommu_init(MachineState
*machine
)
585 static const XtfpgaBoardDesc kc705_board
= {
586 .flash
= &kc705_flash
,
587 .sram_size
= 0x2000000,
588 .io
= xtfpga_nommu_io
,
590 xtfpga_init(&kc705_board
, machine
);
593 static void xtfpga_lx60_class_init(ObjectClass
*oc
, void *data
)
595 MachineClass
*mc
= MACHINE_CLASS(oc
);
597 mc
->desc
= "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL
")";
598 mc
->init
= xtfpga_lx60_init
;
600 mc
->default_cpu_type
= XTENSA_DEFAULT_CPU_TYPE
;
601 mc
->default_ram_size
= 64 * MiB
;
604 static const TypeInfo xtfpga_lx60_type
= {
605 .name
= MACHINE_TYPE_NAME("lx60"),
606 .parent
= TYPE_MACHINE
,
607 .class_init
= xtfpga_lx60_class_init
,
610 static void xtfpga_lx60_nommu_class_init(ObjectClass
*oc
, void *data
)
612 MachineClass
*mc
= MACHINE_CLASS(oc
);
614 mc
->desc
= "lx60 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL
")";
615 mc
->init
= xtfpga_lx60_nommu_init
;
617 mc
->default_cpu_type
= XTENSA_DEFAULT_CPU_NOMMU_TYPE
;
618 mc
->default_ram_size
= 64 * MiB
;
621 static const TypeInfo xtfpga_lx60_nommu_type
= {
622 .name
= MACHINE_TYPE_NAME("lx60-nommu"),
623 .parent
= TYPE_MACHINE
,
624 .class_init
= xtfpga_lx60_nommu_class_init
,
627 static void xtfpga_lx200_class_init(ObjectClass
*oc
, void *data
)
629 MachineClass
*mc
= MACHINE_CLASS(oc
);
631 mc
->desc
= "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL
")";
632 mc
->init
= xtfpga_lx200_init
;
634 mc
->default_cpu_type
= XTENSA_DEFAULT_CPU_TYPE
;
635 mc
->default_ram_size
= 96 * MiB
;
638 static const TypeInfo xtfpga_lx200_type
= {
639 .name
= MACHINE_TYPE_NAME("lx200"),
640 .parent
= TYPE_MACHINE
,
641 .class_init
= xtfpga_lx200_class_init
,
644 static void xtfpga_lx200_nommu_class_init(ObjectClass
*oc
, void *data
)
646 MachineClass
*mc
= MACHINE_CLASS(oc
);
648 mc
->desc
= "lx200 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL
")";
649 mc
->init
= xtfpga_lx200_nommu_init
;
651 mc
->default_cpu_type
= XTENSA_DEFAULT_CPU_NOMMU_TYPE
;
652 mc
->default_ram_size
= 96 * MiB
;
655 static const TypeInfo xtfpga_lx200_nommu_type
= {
656 .name
= MACHINE_TYPE_NAME("lx200-nommu"),
657 .parent
= TYPE_MACHINE
,
658 .class_init
= xtfpga_lx200_nommu_class_init
,
661 static void xtfpga_ml605_class_init(ObjectClass
*oc
, void *data
)
663 MachineClass
*mc
= MACHINE_CLASS(oc
);
665 mc
->desc
= "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL
")";
666 mc
->init
= xtfpga_ml605_init
;
668 mc
->default_cpu_type
= XTENSA_DEFAULT_CPU_TYPE
;
669 mc
->default_ram_size
= 512 * MiB
- XTFPGA_MMU_RESERVED_MEMORY_SIZE
;
672 static const TypeInfo xtfpga_ml605_type
= {
673 .name
= MACHINE_TYPE_NAME("ml605"),
674 .parent
= TYPE_MACHINE
,
675 .class_init
= xtfpga_ml605_class_init
,
678 static void xtfpga_ml605_nommu_class_init(ObjectClass
*oc
, void *data
)
680 MachineClass
*mc
= MACHINE_CLASS(oc
);
682 mc
->desc
= "ml605 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL
")";
683 mc
->init
= xtfpga_ml605_nommu_init
;
685 mc
->default_cpu_type
= XTENSA_DEFAULT_CPU_NOMMU_TYPE
;
686 mc
->default_ram_size
= 256 * MiB
;
689 static const TypeInfo xtfpga_ml605_nommu_type
= {
690 .name
= MACHINE_TYPE_NAME("ml605-nommu"),
691 .parent
= TYPE_MACHINE
,
692 .class_init
= xtfpga_ml605_nommu_class_init
,
695 static void xtfpga_kc705_class_init(ObjectClass
*oc
, void *data
)
697 MachineClass
*mc
= MACHINE_CLASS(oc
);
699 mc
->desc
= "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL
")";
700 mc
->init
= xtfpga_kc705_init
;
702 mc
->default_cpu_type
= XTENSA_DEFAULT_CPU_TYPE
;
703 mc
->default_ram_size
= 1 * GiB
- XTFPGA_MMU_RESERVED_MEMORY_SIZE
;
706 static const TypeInfo xtfpga_kc705_type
= {
707 .name
= MACHINE_TYPE_NAME("kc705"),
708 .parent
= TYPE_MACHINE
,
709 .class_init
= xtfpga_kc705_class_init
,
712 static void xtfpga_kc705_nommu_class_init(ObjectClass
*oc
, void *data
)
714 MachineClass
*mc
= MACHINE_CLASS(oc
);
716 mc
->desc
= "kc705 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL
")";
717 mc
->init
= xtfpga_kc705_nommu_init
;
719 mc
->default_cpu_type
= XTENSA_DEFAULT_CPU_NOMMU_TYPE
;
720 mc
->default_ram_size
= 256 * MiB
;
723 static const TypeInfo xtfpga_kc705_nommu_type
= {
724 .name
= MACHINE_TYPE_NAME("kc705-nommu"),
725 .parent
= TYPE_MACHINE
,
726 .class_init
= xtfpga_kc705_nommu_class_init
,
729 static void xtfpga_machines_init(void)
731 type_register_static(&xtfpga_lx60_type
);
732 type_register_static(&xtfpga_lx200_type
);
733 type_register_static(&xtfpga_ml605_type
);
734 type_register_static(&xtfpga_kc705_type
);
735 type_register_static(&xtfpga_lx60_nommu_type
);
736 type_register_static(&xtfpga_lx200_nommu_type
);
737 type_register_static(&xtfpga_ml605_nommu_type
);
738 type_register_static(&xtfpga_kc705_nommu_type
);
741 type_init(xtfpga_machines_init
)