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qapi: Rename QAPIDoc.Section.name to .tag
[qemu/kevin.git] / hw / i386 / pc.c
blobf8eb684a492689d7f6519b7f3cfb7f8ec7ed3bab
1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "hw/i386/pc.h"
28 #include "hw/char/serial.h"
29 #include "hw/char/parallel.h"
30 #include "hw/hyperv/hv-balloon.h"
31 #include "hw/i386/fw_cfg.h"
32 #include "hw/i386/vmport.h"
33 #include "sysemu/cpus.h"
34 #include "hw/ide/ide-bus.h"
35 #include "hw/timer/hpet.h"
36 #include "hw/loader.h"
37 #include "hw/rtc/mc146818rtc.h"
38 #include "hw/intc/i8259.h"
39 #include "hw/timer/i8254.h"
40 #include "hw/input/i8042.h"
41 #include "hw/audio/pcspk.h"
42 #include "sysemu/sysemu.h"
43 #include "sysemu/xen.h"
44 #include "sysemu/reset.h"
45 #include "kvm/kvm_i386.h"
46 #include "hw/xen/xen.h"
47 #include "qapi/qmp/qlist.h"
48 #include "qemu/error-report.h"
49 #include "hw/acpi/cpu_hotplug.h"
50 #include "acpi-build.h"
51 #include "hw/mem/nvdimm.h"
52 #include "hw/cxl/cxl_host.h"
53 #include "hw/usb.h"
54 #include "hw/i386/intel_iommu.h"
55 #include "hw/net/ne2000-isa.h"
56 #include "hw/virtio/virtio-iommu.h"
57 #include "hw/virtio/virtio-md-pci.h"
58 #include "hw/i386/kvm/xen_overlay.h"
59 #include "hw/i386/kvm/xen_evtchn.h"
60 #include "hw/i386/kvm/xen_gnttab.h"
61 #include "hw/i386/kvm/xen_xenstore.h"
62 #include "hw/mem/memory-device.h"
63 #include "e820_memory_layout.h"
64 #include "trace.h"
65 #include CONFIG_DEVICES
66
67 #ifdef CONFIG_XEN_EMU
68 #include "hw/xen/xen-legacy-backend.h"
69 #include "hw/xen/xen-bus.h"
70 #endif
71
72 /*
73 * Helper for setting model-id for CPU models that changed model-id
74 * depending on QEMU versions up to QEMU 2.4.
75 */
76 #define PC_CPU_MODEL_IDS(v) \
77 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
78 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
79 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },
80
81 GlobalProperty pc_compat_8_2[] = {};
82 const size_t pc_compat_8_2_len = G_N_ELEMENTS(pc_compat_8_2);
83
84 GlobalProperty pc_compat_8_1[] = {};
85 const size_t pc_compat_8_1_len = G_N_ELEMENTS(pc_compat_8_1);
86
87 GlobalProperty pc_compat_8_0[] = {
88 { "virtio-mem", "unplugged-inaccessible", "auto" },
89 };
90 const size_t pc_compat_8_0_len = G_N_ELEMENTS(pc_compat_8_0);
91
92 GlobalProperty pc_compat_7_2[] = {
93 { "ICH9-LPC", "noreboot", "true" },
94 };
95 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2);
96
97 GlobalProperty pc_compat_7_1[] = {};
98 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1);
99
100 GlobalProperty pc_compat_7_0[] = {};
101 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0);
102
103 GlobalProperty pc_compat_6_2[] = {
104 { "virtio-mem", "unplugged-inaccessible", "off" },
105 };
106 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2);
107
108 GlobalProperty pc_compat_6_1[] = {
109 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" },
110 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" },
111 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" },
112 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" },
113 };
114 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1);
115
116 GlobalProperty pc_compat_6_0[] = {
117 { "qemu64" "-" TYPE_X86_CPU, "family", "6" },
118 { "qemu64" "-" TYPE_X86_CPU, "model", "6" },
119 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" },
120 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" },
121 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" },
122 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" },
123 };
124 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0);
125
126 GlobalProperty pc_compat_5_2[] = {
127 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" },
128 };
129 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2);
130
131 GlobalProperty pc_compat_5_1[] = {
132 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" },
133 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" },
134 };
135 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1);
136
137 GlobalProperty pc_compat_5_0[] = {
138 };
139 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0);
140
141 GlobalProperty pc_compat_4_2[] = {
142 { "mch", "smbase-smram", "off" },
143 };
144 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2);
145
146 GlobalProperty pc_compat_4_1[] = {};
147 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
148
149 GlobalProperty pc_compat_4_0[] = {};
150 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
151
152 GlobalProperty pc_compat_3_1[] = {
153 { "intel-iommu", "dma-drain", "off" },
154 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
155 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
156 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
157 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
158 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
159 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
160 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
161 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
162 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
163 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
164 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
165 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
166 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
167 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
168 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
169 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
170 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
171 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
172 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
173 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
174 };
175 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
176
177 GlobalProperty pc_compat_3_0[] = {
178 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
179 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
180 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
181 };
182 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
183
184 GlobalProperty pc_compat_2_12[] = {
185 { TYPE_X86_CPU, "legacy-cache", "on" },
186 { TYPE_X86_CPU, "topoext", "off" },
187 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
188 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
189 };
190 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
191
192 GlobalProperty pc_compat_2_11[] = {
193 { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
194 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
195 };
196 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
197
198 GlobalProperty pc_compat_2_10[] = {
199 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
200 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
201 { "q35-pcihost", "x-pci-hole64-fix", "off" },
202 };
203 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
204
205 GlobalProperty pc_compat_2_9[] = {
206 { "mch", "extended-tseg-mbytes", "0" },
207 };
208 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
209
210 GlobalProperty pc_compat_2_8[] = {
211 { TYPE_X86_CPU, "tcg-cpuid", "off" },
212 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
213 { "ICH9-LPC", "x-smi-broadcast", "off" },
214 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
215 { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
216 };
217 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
218
219 GlobalProperty pc_compat_2_7[] = {
220 { TYPE_X86_CPU, "l3-cache", "off" },
221 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
222 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
223 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
224 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
225 { "isa-pcspk", "migrate", "off" },
226 };
227 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
228
229 GlobalProperty pc_compat_2_6[] = {
230 { TYPE_X86_CPU, "cpuid-0xb", "off" },
231 { "vmxnet3", "romfile", "" },
232 { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
233 { "apic-common", "legacy-instance-id", "on", }
234 };
235 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
236
237 GlobalProperty pc_compat_2_5[] = {};
238 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
239
240 GlobalProperty pc_compat_2_4[] = {
241 PC_CPU_MODEL_IDS("2.4.0")
242 { "Haswell-" TYPE_X86_CPU, "abm", "off" },
243 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
244 { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
245 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
246 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
247 { TYPE_X86_CPU, "check", "off" },
248 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
249 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
250 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
251 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
252 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
253 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
254 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
255 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
256 };
257 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
258
259 GlobalProperty pc_compat_2_3[] = {
260 PC_CPU_MODEL_IDS("2.3.0")
261 { TYPE_X86_CPU, "arat", "off" },
262 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
263 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
264 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
265 { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
266 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
267 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
268 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
269 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
270 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
271 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
272 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
273 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
274 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
275 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
276 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
277 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
278 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
279 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
280 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
281 };
282 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
283
284 GlobalProperty pc_compat_2_2[] = {
285 PC_CPU_MODEL_IDS("2.2.0")
286 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
287 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
288 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
289 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
290 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
291 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
292 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
293 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
294 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
295 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
296 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
297 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
298 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
299 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
300 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
301 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
302 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
303 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
304 };
305 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
306
307 GlobalProperty pc_compat_2_1[] = {
308 PC_CPU_MODEL_IDS("2.1.0")
309 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
310 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
311 };
312 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
313
314 GlobalProperty pc_compat_2_0[] = {
315 PC_CPU_MODEL_IDS("2.0.0")
316 { "virtio-scsi-pci", "any_layout", "off" },
317 { "PIIX4_PM", "memory-hotplug-support", "off" },
318 { "apic", "version", "0x11" },
319 { "nec-usb-xhci", "superspeed-ports-first", "off" },
320 { "nec-usb-xhci", "force-pcie-endcap", "on" },
321 { "pci-serial", "prog_if", "0" },
322 { "pci-serial-2x", "prog_if", "0" },
323 { "pci-serial-4x", "prog_if", "0" },
324 { "virtio-net-pci", "guest_announce", "off" },
325 { "ICH9-LPC", "memory-hotplug-support", "off" },
326 };
327 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
328
329 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
330 {
331 GSIState *s;
332
333 s = g_new0(GSIState, 1);
334 if (kvm_ioapic_in_kernel()) {
335 kvm_pc_setup_irq_routing(pci_enabled);
336 }
337 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS);
338
339 return s;
340 }
341
342 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
343 unsigned size)
344 {
345 }
346
347 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
348 {
349 return 0xffffffffffffffffULL;
350 }
351
352 /* MS-DOS compatibility mode FPU exception support */
353 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
354 unsigned size)
355 {
356 if (tcg_enabled()) {
357 cpu_set_ignne();
358 }
359 }
360
361 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
362 {
363 return 0xffffffffffffffffULL;
364 }
365
366 /* PC cmos mappings */
367
368 #define REG_EQUIPMENT_BYTE 0x14
369
370 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs,
371 int16_t cylinders, int8_t heads, int8_t sectors)
372 {
373 mc146818rtc_set_cmos_data(s, type_ofs, 47);
374 mc146818rtc_set_cmos_data(s, info_ofs, cylinders);
375 mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8);
376 mc146818rtc_set_cmos_data(s, info_ofs + 2, heads);
377 mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff);
378 mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff);
379 mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
380 mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders);
381 mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8);
382 mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors);
383 }
384
385 /* convert boot_device letter to something recognizable by the bios */
386 static int boot_device2nibble(char boot_device)
387 {
388 switch(boot_device) {
389 case 'a':
390 case 'b':
391 return 0x01; /* floppy boot */
392 case 'c':
393 return 0x02; /* hard drive boot */
394 case 'd':
395 return 0x03; /* CD-ROM boot */
396 case 'n':
397 return 0x04; /* Network boot */
398 }
399 return 0;
400 }
401
402 static void set_boot_dev(MC146818RtcState *s, const char *boot_device,
403 Error **errp)
404 {
405 #define PC_MAX_BOOT_DEVICES 3
406 int nbds, bds[3] = { 0, };
407 int i;
408
409 nbds = strlen(boot_device);
410 if (nbds > PC_MAX_BOOT_DEVICES) {
411 error_setg(errp, "Too many boot devices for PC");
412 return;
413 }
414 for (i = 0; i < nbds; i++) {
415 bds[i] = boot_device2nibble(boot_device[i]);
416 if (bds[i] == 0) {
417 error_setg(errp, "Invalid boot device for PC: '%c'",
418 boot_device[i]);
419 return;
420 }
421 }
422 mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]);
423 mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
424 }
425
426 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
427 {
428 set_boot_dev(opaque, boot_device, errp);
429 }
430
431 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy)
432 {
433 int val, nb, i;
434 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
435 FLOPPY_DRIVE_TYPE_NONE };
436
437 /* floppy type */
438 if (floppy) {
439 for (i = 0; i < 2; i++) {
440 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
441 }
442 }
443 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
444 cmos_get_fd_drive_type(fd_type[1]);
445 mc146818rtc_set_cmos_data(rtc_state, 0x10, val);
446
447 val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE);
448 nb = 0;
449 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
450 nb++;
451 }
452 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
453 nb++;
454 }
455 switch (nb) {
456 case 0:
457 break;
458 case 1:
459 val |= 0x01; /* 1 drive, ready for boot */
460 break;
461 case 2:
462 val |= 0x41; /* 2 drives, ready for boot */
463 break;
464 }
465 mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val);
466 }
467
468 typedef struct check_fdc_state {
469 ISADevice *floppy;
470 bool multiple;
471 } CheckFdcState;
472
473 static int check_fdc(Object *obj, void *opaque)
474 {
475 CheckFdcState *state = opaque;
476 Object *fdc;
477 uint32_t iobase;
478 Error *local_err = NULL;
479
480 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
481 if (!fdc) {
482 return 0;
483 }
484
485 iobase = object_property_get_uint(obj, "iobase", &local_err);
486 if (local_err || iobase != 0x3f0) {
487 error_free(local_err);
488 return 0;
489 }
490
491 if (state->floppy) {
492 state->multiple = true;
493 } else {
494 state->floppy = ISA_DEVICE(obj);
495 }
496 return 0;
497 }
498
499 static const char * const fdc_container_path[] = {
500 "/unattached", "/peripheral", "/peripheral-anon"
501 };
502
503 /*
504 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
505 * and ACPI objects.
506 */
507 static ISADevice *pc_find_fdc0(void)
508 {
509 int i;
510 Object *container;
511 CheckFdcState state = { 0 };
512
513 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
514 container = container_get(qdev_get_machine(), fdc_container_path[i]);
515 object_child_foreach(container, check_fdc, &state);
516 }
517
518 if (state.multiple) {
519 warn_report("multiple floppy disk controllers with "
520 "iobase=0x3f0 have been found");
521 error_printf("the one being picked for CMOS setup might not reflect "
522 "your intent");
523 }
524
525 return state.floppy;
526 }
527
528 static void pc_cmos_init_late(PCMachineState *pcms)
529 {
530 X86MachineState *x86ms = X86_MACHINE(pcms);
531 MC146818RtcState *s = MC146818_RTC(x86ms->rtc);
532 int16_t cylinders;
533 int8_t heads, sectors;
534 int val;
535 int i, trans;
536
537 val = 0;
538 if (pcms->idebus[0] &&
539 ide_get_geometry(pcms->idebus[0], 0,
540 &cylinders, &heads, &sectors) >= 0) {
541 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
542 val |= 0xf0;
543 }
544 if (pcms->idebus[0] &&
545 ide_get_geometry(pcms->idebus[0], 1,
546 &cylinders, &heads, &sectors) >= 0) {
547 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
548 val |= 0x0f;
549 }
550 mc146818rtc_set_cmos_data(s, 0x12, val);
551
552 val = 0;
553 for (i = 0; i < 4; i++) {
554 /* NOTE: ide_get_geometry() returns the physical
555 geometry. It is always such that: 1 <= sects <= 63, 1
556 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
557 geometry can be different if a translation is done. */
558 BusState *idebus = pcms->idebus[i / 2];
559 if (idebus &&
560 ide_get_geometry(idebus, i % 2,
561 &cylinders, &heads, &sectors) >= 0) {
562 trans = ide_get_bios_chs_trans(idebus, i % 2) - 1;
563 assert((trans & ~3) == 0);
564 val |= trans << (i * 2);
565 }
566 }
567 mc146818rtc_set_cmos_data(s, 0x39, val);
568
569 pc_cmos_init_floppy(s, pc_find_fdc0());
570 }
571
572 void pc_cmos_init(PCMachineState *pcms,
573 ISADevice *rtc)
574 {
575 int val;
576 X86MachineState *x86ms = X86_MACHINE(pcms);
577 MC146818RtcState *s = MC146818_RTC(rtc);
578
579 /* various important CMOS locations needed by PC/Bochs bios */
580
581 /* memory size */
582 /* base memory (first MiB) */
583 val = MIN(x86ms->below_4g_mem_size / KiB, 640);
584 mc146818rtc_set_cmos_data(s, 0x15, val);
585 mc146818rtc_set_cmos_data(s, 0x16, val >> 8);
586 /* extended memory (next 64MiB) */
587 if (x86ms->below_4g_mem_size > 1 * MiB) {
588 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
589 } else {
590 val = 0;
591 }
592 if (val > 65535)
593 val = 65535;
594 mc146818rtc_set_cmos_data(s, 0x17, val);
595 mc146818rtc_set_cmos_data(s, 0x18, val >> 8);
596 mc146818rtc_set_cmos_data(s, 0x30, val);
597 mc146818rtc_set_cmos_data(s, 0x31, val >> 8);
598 /* memory between 16MiB and 4GiB */
599 if (x86ms->below_4g_mem_size > 16 * MiB) {
600 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
601 } else {
602 val = 0;
603 }
604 if (val > 65535)
605 val = 65535;
606 mc146818rtc_set_cmos_data(s, 0x34, val);
607 mc146818rtc_set_cmos_data(s, 0x35, val >> 8);
608 /* memory above 4GiB */
609 val = x86ms->above_4g_mem_size / 65536;
610 mc146818rtc_set_cmos_data(s, 0x5b, val);
611 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8);
612 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16);
613
614 object_property_add_link(OBJECT(pcms), "rtc_state",
615 TYPE_ISA_DEVICE,
616 (Object **)&x86ms->rtc,
617 object_property_allow_set_link,
618 OBJ_PROP_LINK_STRONG);
619 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s),
620 &error_abort);
621
622 set_boot_dev(s, MACHINE(pcms)->boot_config.order, &error_fatal);
623
624 val = 0;
625 val |= 0x02; /* FPU is there */
626 val |= 0x04; /* PS/2 mouse installed */
627 mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val);
628
629 /* hard drives and FDC are handled by pc_cmos_init_late() */
630 }
631
632 static void handle_a20_line_change(void *opaque, int irq, int level)
633 {
634 X86CPU *cpu = opaque;
635
636 /* XXX: send to all CPUs ? */
637 /* XXX: add logic to handle multiple A20 line sources */
638 x86_cpu_set_a20(cpu, level);
639 }
640
641 #define NE2000_NB_MAX 6
642
643 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
644 0x280, 0x380 };
645 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
646
647 static gboolean pc_init_ne2k_isa(ISABus *bus, NICInfo *nd, Error **errp)
648 {
649 static int nb_ne2k = 0;
650
651 if (nb_ne2k == NE2000_NB_MAX) {
652 error_setg(errp,
653 "maximum number of ISA NE2000 devices exceeded");
654 return false;
655 }
656 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
657 ne2000_irq[nb_ne2k], nd);
658 nb_ne2k++;
659 return true;
660 }
661
662 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
663 {
664 X86CPU *cpu = opaque;
665
666 if (level) {
667 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
668 }
669 }
670
671 static
672 void pc_machine_done(Notifier *notifier, void *data)
673 {
674 PCMachineState *pcms = container_of(notifier,
675 PCMachineState, machine_done);
676 X86MachineState *x86ms = X86_MACHINE(pcms);
677
678 cxl_hook_up_pxb_registers(pcms->bus, &pcms->cxl_devices_state,
679 &error_fatal);
680
681 if (pcms->cxl_devices_state.is_enabled) {
682 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal);
683 }
684
685 /* set the number of CPUs */
686 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
687
688 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg);
689
690 acpi_setup();
691 if (x86ms->fw_cfg) {
692 fw_cfg_build_smbios(pcms, x86ms->fw_cfg);
693 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg);
694 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
695 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
696 }
697
698 pc_cmos_init_late(pcms);
699 }
700
701 /* setup pci memory address space mapping into system address space */
702 void pc_pci_as_mapping_init(MemoryRegion *system_memory,
703 MemoryRegion *pci_address_space)
704 {
705 /* Set to lower priority than RAM */
706 memory_region_add_subregion_overlap(system_memory, 0x0,
707 pci_address_space, -1);
708 }
709
710 void xen_load_linux(PCMachineState *pcms)
711 {
712 int i;
713 FWCfgState *fw_cfg;
714 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
715 X86MachineState *x86ms = X86_MACHINE(pcms);
716
717 assert(MACHINE(pcms)->kernel_filename != NULL);
718
719 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
720 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
721 rom_set_fw(fw_cfg);
722
723 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
724 pcmc->pvh_enabled);
725 for (i = 0; i < nb_option_roms; i++) {
726 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
727 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
728 !strcmp(option_rom[i].name, "pvh.bin") ||
729 !strcmp(option_rom[i].name, "multiboot.bin") ||
730 !strcmp(option_rom[i].name, "multiboot_dma.bin"));
731 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
732 }
733 x86ms->fw_cfg = fw_cfg;
734 }
735
736 #define PC_ROM_MIN_VGA 0xc0000
737 #define PC_ROM_MIN_OPTION 0xc8000
738 #define PC_ROM_MAX 0xe0000
739 #define PC_ROM_ALIGN 0x800
740 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA)
741
742 static hwaddr pc_above_4g_end(PCMachineState *pcms)
743 {
744 X86MachineState *x86ms = X86_MACHINE(pcms);
745
746 if (pcms->sgx_epc.size != 0) {
747 return sgx_epc_above_4g_end(&pcms->sgx_epc);
748 }
749
750 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size;
751 }
752
753 static void pc_get_device_memory_range(PCMachineState *pcms,
754 hwaddr *base,
755 ram_addr_t *device_mem_size)
756 {
757 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
758 MachineState *machine = MACHINE(pcms);
759 ram_addr_t size;
760 hwaddr addr;
761
762 size = machine->maxram_size - machine->ram_size;
763 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB);
764
765 if (pcmc->enforce_aligned_dimm) {
766 /* size device region assuming 1G page max alignment per slot */
767 size += (1 * GiB) * machine->ram_slots;
768 }
769
770 *base = addr;
771 *device_mem_size = size;
772 }
773
774 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms)
775 {
776 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
777 MachineState *ms = MACHINE(pcms);
778 hwaddr cxl_base;
779 ram_addr_t size;
780
781 if (pcmc->has_reserved_memory &&
782 (ms->ram_size < ms->maxram_size)) {
783 pc_get_device_memory_range(pcms, &cxl_base, &size);
784 cxl_base += size;
785 } else {
786 cxl_base = pc_above_4g_end(pcms);
787 }
788
789 return cxl_base;
790 }
791
792 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms)
793 {
794 uint64_t start = pc_get_cxl_range_start(pcms) + MiB;
795
796 if (pcms->cxl_devices_state.fixed_windows) {
797 GList *it;
798
799 start = ROUND_UP(start, 256 * MiB);
800 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) {
801 CXLFixedWindow *fw = it->data;
802 start += fw->size;
803 }
804 }
805
806 return start;
807 }
808
809 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size)
810 {
811 X86CPU *cpu = X86_CPU(first_cpu);
812 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
813 MachineState *ms = MACHINE(pcms);
814
815 if (cpu->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
816 /* 64-bit systems */
817 return pc_pci_hole64_start() + pci_hole64_size - 1;
818 }
819
820 /* 32-bit systems */
821 if (pcmc->broken_32bit_mem_addr_check) {
822 /* old value for compatibility reasons */
823 return ((hwaddr)1 << cpu->phys_bits) - 1;
824 }
825
826 /*
827 * 32-bit systems don't have hole64 but they might have a region for
828 * memory devices. Even if additional hotplugged memory devices might
829 * not be usable by most guest OSes, we need to still consider them for
830 * calculating the highest possible GPA so that we can properly report
831 * if someone configures them on a CPU that cannot possibly address them.
832 */
833 if (pcmc->has_reserved_memory &&
834 (ms->ram_size < ms->maxram_size)) {
835 hwaddr devmem_start;
836 ram_addr_t devmem_size;
837
838 pc_get_device_memory_range(pcms, &devmem_start, &devmem_size);
839 devmem_start += devmem_size;
840 return devmem_start - 1;
841 }
842
843 /* configuration without any memory hotplug */
844 return pc_above_4g_end(pcms) - 1;
845 }
846
847 /*
848 * AMD systems with an IOMMU have an additional hole close to the
849 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending
850 * on kernel version, VFIO may or may not let you DMA map those ranges.
851 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines
852 * with certain memory sizes. It's also wrong to use those IOVA ranges
853 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse.
854 * The ranges reserved for Hyper-Transport are:
855 *
856 * FD_0000_0000h - FF_FFFF_FFFFh
857 *
858 * The ranges represent the following:
859 *
860 * Base Address Top Address Use
861 *
862 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space
863 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl
864 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK
865 * FD_F910_0000h FD_F91F_FFFFh System Management
866 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables
867 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation
868 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space
869 * FD_FE00_0000h FD_FFFF_FFFFh Configuration
870 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages
871 * FE_2000_0000h FF_FFFF_FFFFh Reserved
872 *
873 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology",
874 * Table 3: Special Address Controls (GPA) for more information.
875 */
876 #define AMD_HT_START 0xfd00000000UL
877 #define AMD_HT_END 0xffffffffffUL
878 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1)
879 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START)
880
881 void pc_memory_init(PCMachineState *pcms,
882 MemoryRegion *system_memory,
883 MemoryRegion *rom_memory,
884 uint64_t pci_hole64_size)
885 {
886 int linux_boot, i;
887 MemoryRegion *option_rom_mr;
888 MemoryRegion *ram_below_4g, *ram_above_4g;
889 FWCfgState *fw_cfg;
890 MachineState *machine = MACHINE(pcms);
891 MachineClass *mc = MACHINE_GET_CLASS(machine);
892 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
893 X86MachineState *x86ms = X86_MACHINE(pcms);
894 hwaddr maxphysaddr, maxusedaddr;
895 hwaddr cxl_base, cxl_resv_end = 0;
896 X86CPU *cpu = X86_CPU(first_cpu);
897
898 assert(machine->ram_size == x86ms->below_4g_mem_size +
899 x86ms->above_4g_mem_size);
900
901 linux_boot = (machine->kernel_filename != NULL);
902
903 /*
904 * The HyperTransport range close to the 1T boundary is unique to AMD
905 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation
906 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in
907 * older machine types (<= 7.0) for compatibility purposes.
908 */
909 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) {
910 /* Bail out if max possible address does not cross HT range */
911 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) {
912 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START;
913 }
914
915 /*
916 * Advertise the HT region if address space covers the reserved
917 * region or if we relocate.
918 */
919 if (cpu->phys_bits >= 40) {
920 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED);
921 }
922 }
923
924 /*
925 * phys-bits is required to be appropriately configured
926 * to make sure max used GPA is reachable.
927 */
928 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size);
929 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1;
930 if (maxphysaddr < maxusedaddr) {
931 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64
932 " phys-bits too low (%u)",
933 maxphysaddr, maxusedaddr, cpu->phys_bits);
934 exit(EXIT_FAILURE);
935 }
936
937 /*
938 * Split single memory region and use aliases to address portions of it,
939 * done for backwards compatibility with older qemus.
940 */
941 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
942 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram,
943 0, x86ms->below_4g_mem_size);
944 memory_region_add_subregion(system_memory, 0, ram_below_4g);
945 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
946 if (x86ms->above_4g_mem_size > 0) {
947 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
948 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g",
949 machine->ram,
950 x86ms->below_4g_mem_size,
951 x86ms->above_4g_mem_size);
952 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start,
953 ram_above_4g);
954 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size,
955 E820_RAM);
956 }
957
958 if (pcms->sgx_epc.size != 0) {
959 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED);
960 }
961
962 if (!pcmc->has_reserved_memory &&
963 (machine->ram_slots ||
964 (machine->maxram_size > machine->ram_size))) {
965
966 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
967 mc->name);
968 exit(EXIT_FAILURE);
969 }
970
971 /* initialize device memory address space */
972 if (pcmc->has_reserved_memory &&
973 (machine->ram_size < machine->maxram_size)) {
974 ram_addr_t device_mem_size;
975 hwaddr device_mem_base;
976
977 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
978 error_report("unsupported amount of memory slots: %"PRIu64,
979 machine->ram_slots);
980 exit(EXIT_FAILURE);
981 }
982
983 if (QEMU_ALIGN_UP(machine->maxram_size,
984 TARGET_PAGE_SIZE) != machine->maxram_size) {
985 error_report("maximum memory size must by aligned to multiple of "
986 "%d bytes", TARGET_PAGE_SIZE);
987 exit(EXIT_FAILURE);
988 }
989
990 pc_get_device_memory_range(pcms, &device_mem_base, &device_mem_size);
991
992 if (device_mem_base + device_mem_size < device_mem_size) {
993 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
994 machine->maxram_size);
995 exit(EXIT_FAILURE);
996 }
997 machine_memory_devices_init(machine, device_mem_base, device_mem_size);
998 }
999
1000 if (pcms->cxl_devices_state.is_enabled) {
1001 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr;
1002 hwaddr cxl_size = MiB;
1003
1004 cxl_base = pc_get_cxl_range_start(pcms);
1005 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size);
1006 memory_region_add_subregion(system_memory, cxl_base, mr);
1007 cxl_resv_end = cxl_base + cxl_size;
1008 if (pcms->cxl_devices_state.fixed_windows) {
1009 hwaddr cxl_fmw_base;
1010 GList *it;
1011
1012 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB);
1013 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) {
1014 CXLFixedWindow *fw = it->data;
1015
1016 fw->base = cxl_fmw_base;
1017 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw,
1018 "cxl-fixed-memory-region", fw->size);
1019 memory_region_add_subregion(system_memory, fw->base, &fw->mr);
1020 cxl_fmw_base += fw->size;
1021 cxl_resv_end = cxl_fmw_base;
1022 }
1023 }
1024 }
1025
1026 /* Initialize PC system firmware */
1027 pc_system_firmware_init(pcms, rom_memory);
1028
1029 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1030 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1031 &error_fatal);
1032 if (pcmc->pci_enabled) {
1033 memory_region_set_readonly(option_rom_mr, true);
1034 }
1035 memory_region_add_subregion_overlap(rom_memory,
1036 PC_ROM_MIN_VGA,
1037 option_rom_mr,
1038 1);
1039
1040 fw_cfg = fw_cfg_arch_create(machine,
1041 x86ms->boot_cpus, x86ms->apic_id_limit);
1042
1043 rom_set_fw(fw_cfg);
1044
1045 if (machine->device_memory) {
1046 uint64_t *val = g_malloc(sizeof(*val));
1047 uint64_t res_mem_end = machine->device_memory->base;
1048
1049 if (!pcmc->broken_reserved_end) {
1050 res_mem_end += memory_region_size(&machine->device_memory->mr);
1051 }
1052
1053 if (pcms->cxl_devices_state.is_enabled) {
1054 res_mem_end = cxl_resv_end;
1055 }
1056 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
1057 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1058 }
1059
1060 if (linux_boot) {
1061 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
1062 pcmc->pvh_enabled);
1063 }
1064
1065 for (i = 0; i < nb_option_roms; i++) {
1066 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1067 }
1068 x86ms->fw_cfg = fw_cfg;
1069
1070 /* Init default IOAPIC address space */
1071 x86ms->ioapic_as = &address_space_memory;
1072
1073 /* Init ACPI memory hotplug IO base address */
1074 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
1075 }
1076
1077 /*
1078 * The 64bit pci hole starts after "above 4G RAM" and
1079 * potentially the space reserved for memory hotplug.
1080 */
1081 uint64_t pc_pci_hole64_start(void)
1082 {
1083 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1084 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1085 MachineState *ms = MACHINE(pcms);
1086 uint64_t hole64_start = 0;
1087 ram_addr_t size = 0;
1088
1089 if (pcms->cxl_devices_state.is_enabled) {
1090 hole64_start = pc_get_cxl_range_end(pcms);
1091 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) {
1092 pc_get_device_memory_range(pcms, &hole64_start, &size);
1093 if (!pcmc->broken_reserved_end) {
1094 hole64_start += size;
1095 }
1096 } else {
1097 hole64_start = pc_above_4g_end(pcms);
1098 }
1099
1100 return ROUND_UP(hole64_start, 1 * GiB);
1101 }
1102
1103 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1104 {
1105 DeviceState *dev = NULL;
1106
1107 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1108 if (pci_bus) {
1109 PCIDevice *pcidev = pci_vga_init(pci_bus);
1110 dev = pcidev ? &pcidev->qdev : NULL;
1111 } else if (isa_bus) {
1112 ISADevice *isadev = isa_vga_init(isa_bus);
1113 dev = isadev ? DEVICE(isadev) : NULL;
1114 }
1115 rom_reset_order_override();
1116 return dev;
1117 }
1118
1119 static const MemoryRegionOps ioport80_io_ops = {
1120 .write = ioport80_write,
1121 .read = ioport80_read,
1122 .endianness = DEVICE_NATIVE_ENDIAN,
1123 .impl = {
1124 .min_access_size = 1,
1125 .max_access_size = 1,
1126 },
1127 };
1128
1129 static const MemoryRegionOps ioportF0_io_ops = {
1130 .write = ioportF0_write,
1131 .read = ioportF0_read,
1132 .endianness = DEVICE_NATIVE_ENDIAN,
1133 .impl = {
1134 .min_access_size = 1,
1135 .max_access_size = 1,
1136 },
1137 };
1138
1139 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl,
1140 bool create_i8042, bool no_vmport)
1141 {
1142 int i;
1143 DriveInfo *fd[MAX_FD];
1144 qemu_irq *a20_line;
1145 ISADevice *fdc, *i8042, *port92, *vmmouse;
1146
1147 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1148 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1149
1150 for (i = 0; i < MAX_FD; i++) {
1151 fd[i] = drive_get(IF_FLOPPY, 0, i);
1152 create_fdctrl |= !!fd[i];
1153 }
1154 if (create_fdctrl) {
1155 fdc = isa_new(TYPE_ISA_FDC);
1156 if (fdc) {
1157 isa_realize_and_unref(fdc, isa_bus, &error_fatal);
1158 isa_fdc_init_drives(fdc, fd);
1159 }
1160 }
1161
1162 if (!create_i8042) {
1163 return;
1164 }
1165
1166 i8042 = isa_create_simple(isa_bus, TYPE_I8042);
1167 if (!no_vmport) {
1168 isa_create_simple(isa_bus, TYPE_VMPORT);
1169 vmmouse = isa_try_new("vmmouse");
1170 } else {
1171 vmmouse = NULL;
1172 }
1173 if (vmmouse) {
1174 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042),
1175 &error_abort);
1176 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal);
1177 }
1178 port92 = isa_create_simple(isa_bus, TYPE_PORT92);
1179
1180 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1181 qdev_connect_gpio_out_named(DEVICE(i8042),
1182 I8042_A20_LINE, 0, a20_line[0]);
1183 qdev_connect_gpio_out_named(DEVICE(port92),
1184 PORT92_A20_LINE, 0, a20_line[1]);
1185 g_free(a20_line);
1186 }
1187
1188 void pc_basic_device_init(struct PCMachineState *pcms,
1189 ISABus *isa_bus, qemu_irq *gsi,
1190 ISADevice *rtc_state,
1191 bool create_fdctrl,
1192 uint32_t hpet_irqs)
1193 {
1194 int i;
1195 DeviceState *hpet = NULL;
1196 int pit_isa_irq = 0;
1197 qemu_irq pit_alt_irq = NULL;
1198 ISADevice *pit = NULL;
1199 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1200 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1201 X86MachineState *x86ms = X86_MACHINE(pcms);
1202
1203 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1204 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1205
1206 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1207 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1208
1209 /*
1210 * Check if an HPET shall be created.
1211 */
1212 if (pcms->hpet_enabled) {
1213 qemu_irq rtc_irq;
1214
1215 hpet = qdev_try_new(TYPE_HPET);
1216 if (!hpet) {
1217 error_report("couldn't create HPET device");
1218 exit(1);
1219 }
1220 /*
1221 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-*,
1222 * use IRQ16~23, IRQ8 and IRQ2. If the user has already set
1223 * the property, use whatever mask they specified.
1224 */
1225 uint8_t compat = object_property_get_uint(OBJECT(hpet),
1226 HPET_INTCAP, NULL);
1227 if (!compat) {
1228 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1229 }
1230 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal);
1231 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1232
1233 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1234 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1235 }
1236 pit_isa_irq = -1;
1237 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1238 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1239
1240 /* overwrite connection created by south bridge */
1241 qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq);
1242 }
1243
1244 object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state),
1245 "date");
1246
1247 #ifdef CONFIG_XEN_EMU
1248 if (xen_mode == XEN_EMULATE) {
1249 xen_overlay_create();
1250 xen_evtchn_create(IOAPIC_NUM_PINS, gsi);
1251 xen_gnttab_create();
1252 xen_xenstore_create();
1253 if (pcms->bus) {
1254 pci_create_simple(pcms->bus, -1, "xen-platform");
1255 }
1256 xen_bus_init();
1257 xen_be_init();
1258 }
1259 #endif
1260
1261 qemu_register_boot_set(pc_boot_set, rtc_state);
1262
1263 if (!xen_enabled() &&
1264 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) {
1265 if (kvm_pit_in_kernel()) {
1266 pit = kvm_pit_init(isa_bus, 0x40);
1267 } else {
1268 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1269 }
1270 if (hpet) {
1271 /* connect PIT to output control line of the HPET */
1272 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1273 }
1274 object_property_set_link(OBJECT(pcms->pcspk), "pit",
1275 OBJECT(pit), &error_fatal);
1276 isa_realize_and_unref(pcms->pcspk, isa_bus, &error_fatal);
1277 }
1278
1279 /* Super I/O */
1280 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled,
1281 pcms->vmport != ON_OFF_AUTO_ON);
1282 }
1283
1284 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
1285 {
1286 MachineClass *mc = MACHINE_CLASS(pcmc);
1287 bool default_is_ne2k = g_str_equal(mc->default_nic, TYPE_ISA_NE2000);
1288 NICInfo *nd;
1289
1290 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1291
1292 while ((nd = qemu_find_nic_info(TYPE_ISA_NE2000, default_is_ne2k, NULL))) {
1293 pc_init_ne2k_isa(isa_bus, nd, &error_fatal);
1294 }
1295
1296 /* Anything remaining should be a PCI NIC */
1297 pci_init_nic_devices(pci_bus, mc->default_nic);
1298
1299 rom_reset_order_override();
1300 }
1301
1302 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
1303 {
1304 qemu_irq *i8259;
1305
1306 if (kvm_pic_in_kernel()) {
1307 i8259 = kvm_i8259_init(isa_bus);
1308 } else if (xen_enabled()) {
1309 i8259 = xen_interrupt_controller_init();
1310 } else {
1311 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq());
1312 }
1313
1314 for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
1315 i8259_irqs[i] = i8259[i];
1316 }
1317
1318 g_free(i8259);
1319 }
1320
1321 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1322 Error **errp)
1323 {
1324 const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1325 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1326 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1327 const MachineState *ms = MACHINE(hotplug_dev);
1328 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1329 const uint64_t legacy_align = TARGET_PAGE_SIZE;
1330 Error *local_err = NULL;
1331
1332 /*
1333 * When "acpi=off" is used with the Q35 machine type, no ACPI is built,
1334 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1335 * addition to cover this case.
1336 */
1337 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1338 error_setg(errp,
1339 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1340 return;
1341 }
1342
1343 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
1344 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1345 return;
1346 }
1347
1348 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err);
1349 if (local_err) {
1350 error_propagate(errp, local_err);
1351 return;
1352 }
1353
1354 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
1355 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
1356 }
1357
1358 static void pc_memory_plug(HotplugHandler *hotplug_dev,
1359 DeviceState *dev, Error **errp)
1360 {
1361 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1362 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1363 MachineState *ms = MACHINE(hotplug_dev);
1364 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1365
1366 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms));
1367
1368 if (is_nvdimm) {
1369 nvdimm_plug(ms->nvdimms_state);
1370 }
1371
1372 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort);
1373 }
1374
1375 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1376 DeviceState *dev, Error **errp)
1377 {
1378 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1379
1380 /*
1381 * When "acpi=off" is used with the Q35 machine type, no ACPI is built,
1382 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1383 * addition to cover this case.
1384 */
1385 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1386 error_setg(errp,
1387 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1388 return;
1389 }
1390
1391 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1392 error_setg(errp, "nvdimm device hot unplug is not supported yet.");
1393 return;
1394 }
1395
1396 hotplug_handler_unplug_request(x86ms->acpi_dev, dev,
1397 errp);
1398 }
1399
1400 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1401 DeviceState *dev, Error **errp)
1402 {
1403 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1404 X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1405 Error *local_err = NULL;
1406
1407 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err);
1408 if (local_err) {
1409 goto out;
1410 }
1411
1412 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
1413 qdev_unrealize(dev);
1414 out:
1415 error_propagate(errp, local_err);
1416 }
1417
1418 static void pc_hv_balloon_pre_plug(HotplugHandler *hotplug_dev,
1419 DeviceState *dev, Error **errp)
1420 {
1421 /* The vmbus handler has no hotplug handler; we should never end up here. */
1422 g_assert(!dev->hotplugged);
1423 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL,
1424 errp);
1425 }
1426
1427 static void pc_hv_balloon_plug(HotplugHandler *hotplug_dev,
1428 DeviceState *dev, Error **errp)
1429 {
1430 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1431 }
1432
1433 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
1434 DeviceState *dev, Error **errp)
1435 {
1436 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1437 pc_memory_pre_plug(hotplug_dev, dev, errp);
1438 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1439 x86_cpu_pre_plug(hotplug_dev, dev, errp);
1440 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1441 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
1442 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1443 /* Declare the APIC range as the reserved MSI region */
1444 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d",
1445 VIRTIO_IOMMU_RESV_MEM_T_MSI);
1446 QList *reserved_regions = qlist_new();
1447
1448 qlist_append_str(reserved_regions, resv_prop_str);
1449 qdev_prop_set_array(dev, "reserved-regions", reserved_regions);
1450
1451 g_free(resv_prop_str);
1452 }
1453
1454 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) ||
1455 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1456 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1457
1458 if (pcms->iommu) {
1459 error_setg(errp, "QEMU does not support multiple vIOMMUs "
1460 "for x86 yet.");
1461 return;
1462 }
1463 pcms->iommu = dev;
1464 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) {
1465 pc_hv_balloon_pre_plug(hotplug_dev, dev, errp);
1466 }
1467 }
1468
1469 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1470 DeviceState *dev, Error **errp)
1471 {
1472 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1473 pc_memory_plug(hotplug_dev, dev, errp);
1474 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1475 x86_cpu_plug(hotplug_dev, dev, errp);
1476 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1477 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
1478 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) {
1479 pc_hv_balloon_plug(hotplug_dev, dev, errp);
1480 }
1481 }
1482
1483 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1484 DeviceState *dev, Error **errp)
1485 {
1486 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1487 pc_memory_unplug_request(hotplug_dev, dev, errp);
1488 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1489 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp);
1490 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1491 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev),
1492 errp);
1493 } else {
1494 error_setg(errp, "acpi: device unplug request for not supported device"
1495 " type: %s", object_get_typename(OBJECT(dev)));
1496 }
1497 }
1498
1499 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
1500 DeviceState *dev, Error **errp)
1501 {
1502 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1503 pc_memory_unplug(hotplug_dev, dev, errp);
1504 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1505 x86_cpu_unplug_cb(hotplug_dev, dev, errp);
1506 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1507 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
1508 } else {
1509 error_setg(errp, "acpi: device unplug for not supported device"
1510 " type: %s", object_get_typename(OBJECT(dev)));
1511 }
1512 }
1513
1514 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
1515 DeviceState *dev)
1516 {
1517 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
1518 object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
1519 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) ||
1520 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) ||
1521 object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON) ||
1522 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) {
1523 return HOTPLUG_HANDLER(machine);
1524 }
1525
1526 return NULL;
1527 }
1528
1529 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
1530 void *opaque, Error **errp)
1531 {
1532 PCMachineState *pcms = PC_MACHINE(obj);
1533 OnOffAuto vmport = pcms->vmport;
1534
1535 visit_type_OnOffAuto(v, name, &vmport, errp);
1536 }
1537
1538 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
1539 void *opaque, Error **errp)
1540 {
1541 PCMachineState *pcms = PC_MACHINE(obj);
1542
1543 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
1544 }
1545
1546 static bool pc_machine_get_smbus(Object *obj, Error **errp)
1547 {
1548 PCMachineState *pcms = PC_MACHINE(obj);
1549
1550 return pcms->smbus_enabled;
1551 }
1552
1553 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
1554 {
1555 PCMachineState *pcms = PC_MACHINE(obj);
1556
1557 pcms->smbus_enabled = value;
1558 }
1559
1560 static bool pc_machine_get_sata(Object *obj, Error **errp)
1561 {
1562 PCMachineState *pcms = PC_MACHINE(obj);
1563
1564 return pcms->sata_enabled;
1565 }
1566
1567 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
1568 {
1569 PCMachineState *pcms = PC_MACHINE(obj);
1570
1571 pcms->sata_enabled = value;
1572 }
1573
1574 static bool pc_machine_get_hpet(Object *obj, Error **errp)
1575 {
1576 PCMachineState *pcms = PC_MACHINE(obj);
1577
1578 return pcms->hpet_enabled;
1579 }
1580
1581 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp)
1582 {
1583 PCMachineState *pcms = PC_MACHINE(obj);
1584
1585 pcms->hpet_enabled = value;
1586 }
1587
1588 static bool pc_machine_get_i8042(Object *obj, Error **errp)
1589 {
1590 PCMachineState *pcms = PC_MACHINE(obj);
1591
1592 return pcms->i8042_enabled;
1593 }
1594
1595 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp)
1596 {
1597 PCMachineState *pcms = PC_MACHINE(obj);
1598
1599 pcms->i8042_enabled = value;
1600 }
1601
1602 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp)
1603 {
1604 PCMachineState *pcms = PC_MACHINE(obj);
1605
1606 return pcms->default_bus_bypass_iommu;
1607 }
1608
1609 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value,
1610 Error **errp)
1611 {
1612 PCMachineState *pcms = PC_MACHINE(obj);
1613
1614 pcms->default_bus_bypass_iommu = value;
1615 }
1616
1617 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name,
1618 void *opaque, Error **errp)
1619 {
1620 PCMachineState *pcms = PC_MACHINE(obj);
1621 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type;
1622
1623 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp);
1624 }
1625
1626 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name,
1627 void *opaque, Error **errp)
1628 {
1629 PCMachineState *pcms = PC_MACHINE(obj);
1630
1631 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp);
1632 }
1633
1634 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
1635 const char *name, void *opaque,
1636 Error **errp)
1637 {
1638 PCMachineState *pcms = PC_MACHINE(obj);
1639 uint64_t value = pcms->max_ram_below_4g;
1640
1641 visit_type_size(v, name, &value, errp);
1642 }
1643
1644 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
1645 const char *name, void *opaque,
1646 Error **errp)
1647 {
1648 PCMachineState *pcms = PC_MACHINE(obj);
1649 uint64_t value;
1650
1651 if (!visit_type_size(v, name, &value, errp)) {
1652 return;
1653 }
1654 if (value > 4 * GiB) {
1655 error_setg(errp,
1656 "Machine option 'max-ram-below-4g=%"PRIu64
1657 "' expects size less than or equal to 4G", value);
1658 return;
1659 }
1660
1661 if (value < 1 * MiB) {
1662 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
1663 "BIOS may not work with less than 1MiB", value);
1664 }
1665
1666 pcms->max_ram_below_4g = value;
1667 }
1668
1669 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v,
1670 const char *name, void *opaque,
1671 Error **errp)
1672 {
1673 PCMachineState *pcms = PC_MACHINE(obj);
1674 uint64_t value = pcms->max_fw_size;
1675
1676 visit_type_size(v, name, &value, errp);
1677 }
1678
1679 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v,
1680 const char *name, void *opaque,
1681 Error **errp)
1682 {
1683 PCMachineState *pcms = PC_MACHINE(obj);
1684 uint64_t value;
1685
1686 if (!visit_type_size(v, name, &value, errp)) {
1687 return;
1688 }
1689
1690 /*
1691 * We don't have a theoretically justifiable exact lower bound on the base
1692 * address of any flash mapping. In practice, the IO-APIC MMIO range is
1693 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free
1694 * only 18MiB-4KiB below 4GiB. For now, restrict the cumulative mapping to
1695 * 16MiB in size.
1696 */
1697 if (value > 16 * MiB) {
1698 error_setg(errp,
1699 "User specified max allowed firmware size %" PRIu64 " is "
1700 "greater than 16MiB. If combined firmware size exceeds "
1701 "16MiB the system may not boot, or experience intermittent"
1702 "stability issues.",
1703 value);
1704 return;
1705 }
1706
1707 pcms->max_fw_size = value;
1708 }
1709
1710
1711 static void pc_machine_initfn(Object *obj)
1712 {
1713 PCMachineState *pcms = PC_MACHINE(obj);
1714 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1715
1716 #ifdef CONFIG_VMPORT
1717 pcms->vmport = ON_OFF_AUTO_AUTO;
1718 #else
1719 pcms->vmport = ON_OFF_AUTO_OFF;
1720 #endif /* CONFIG_VMPORT */
1721 pcms->max_ram_below_4g = 0; /* use default */
1722 pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type;
1723 pcms->south_bridge = pcmc->default_south_bridge;
1724
1725 /* acpi build is enabled by default if machine supports it */
1726 pcms->acpi_build_enabled = pcmc->has_acpi_build;
1727 pcms->smbus_enabled = true;
1728 pcms->sata_enabled = true;
1729 pcms->i8042_enabled = true;
1730 pcms->max_fw_size = 8 * MiB;
1731 #ifdef CONFIG_HPET
1732 pcms->hpet_enabled = true;
1733 #endif
1734 pcms->default_bus_bypass_iommu = false;
1735
1736 pcms->pcspk = isa_new(TYPE_PC_SPEAKER);
1737 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev",
1738 OBJECT(pcms->pcspk), "audiodev");
1739 cxl_machine_init(obj, &pcms->cxl_devices_state);
1740
1741 pcms->machine_done.notify = pc_machine_done;
1742 qemu_add_machine_init_done_notifier(&pcms->machine_done);
1743 }
1744
1745 static void pc_machine_reset(MachineState *machine, ShutdownCause reason)
1746 {
1747 CPUState *cs;
1748 X86CPU *cpu;
1749
1750 qemu_devices_reset(reason);
1751
1752 /* Reset APIC after devices have been reset to cancel
1753 * any changes that qemu_devices_reset() might have done.
1754 */
1755 CPU_FOREACH(cs) {
1756 cpu = X86_CPU(cs);
1757
1758 x86_cpu_after_reset(cpu);
1759 }
1760 }
1761
1762 static void pc_machine_wakeup(MachineState *machine)
1763 {
1764 cpu_synchronize_all_states();
1765 pc_machine_reset(machine, SHUTDOWN_CAUSE_NONE);
1766 cpu_synchronize_all_post_reset();
1767 }
1768
1769 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp)
1770 {
1771 X86IOMMUState *iommu = x86_iommu_get_default();
1772 IntelIOMMUState *intel_iommu;
1773
1774 if (iommu &&
1775 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) &&
1776 object_dynamic_cast((Object *)dev, "vfio-pci")) {
1777 intel_iommu = INTEL_IOMMU_DEVICE(iommu);
1778 if (!intel_iommu->caching_mode) {
1779 error_setg(errp, "Device assignment is not allowed without "
1780 "enabling caching-mode=on for Intel IOMMU.");
1781 return false;
1782 }
1783 }
1784
1785 return true;
1786 }
1787
1788 static void pc_machine_class_init(ObjectClass *oc, void *data)
1789 {
1790 MachineClass *mc = MACHINE_CLASS(oc);
1791 X86MachineClass *x86mc = X86_MACHINE_CLASS(oc);
1792 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
1793 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1794
1795 pcmc->pci_enabled = true;
1796 pcmc->has_acpi_build = true;
1797 pcmc->rsdp_in_ram = true;
1798 pcmc->smbios_defaults = true;
1799 pcmc->smbios_uuid_encoded = true;
1800 pcmc->gigabyte_align = true;
1801 pcmc->has_reserved_memory = true;
1802 pcmc->kvmclock_enabled = true;
1803 pcmc->enforce_aligned_dimm = true;
1804 pcmc->enforce_amd_1tb_hole = true;
1805 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
1806 * to be used at the moment, 32K should be enough for a while. */
1807 pcmc->acpi_data_size = 0x20000 + 0x8000;
1808 pcmc->pvh_enabled = true;
1809 pcmc->kvmclock_create_always = true;
1810 pcmc->resizable_acpi_blob = true;
1811 x86mc->apic_xrupt_override = true;
1812 assert(!mc->get_hotplug_handler);
1813 mc->get_hotplug_handler = pc_get_hotplug_handler;
1814 mc->hotplug_allowed = pc_hotplug_allowed;
1815 mc->cpu_index_to_instance_props = x86_cpu_index_to_props;
1816 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id;
1817 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids;
1818 mc->auto_enable_numa_with_memhp = true;
1819 mc->auto_enable_numa_with_memdev = true;
1820 mc->has_hotpluggable_cpus = true;
1821 mc->default_boot_order = "cad";
1822 mc->block_default_type = IF_IDE;
1823 mc->max_cpus = 255;
1824 mc->reset = pc_machine_reset;
1825 mc->wakeup = pc_machine_wakeup;
1826 hc->pre_plug = pc_machine_device_pre_plug_cb;
1827 hc->plug = pc_machine_device_plug_cb;
1828 hc->unplug_request = pc_machine_device_unplug_request_cb;
1829 hc->unplug = pc_machine_device_unplug_cb;
1830 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
1831 mc->nvdimm_supported = true;
1832 mc->smp_props.dies_supported = true;
1833 mc->default_ram_id = "pc.ram";
1834 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_64;
1835
1836 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
1837 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
1838 NULL, NULL);
1839 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
1840 "Maximum ram below the 4G boundary (32bit boundary)");
1841
1842 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
1843 pc_machine_get_vmport, pc_machine_set_vmport,
1844 NULL, NULL);
1845 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
1846 "Enable vmport (pc & q35)");
1847
1848 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
1849 pc_machine_get_smbus, pc_machine_set_smbus);
1850 object_class_property_set_description(oc, PC_MACHINE_SMBUS,
1851 "Enable/disable system management bus");
1852
1853 object_class_property_add_bool(oc, PC_MACHINE_SATA,
1854 pc_machine_get_sata, pc_machine_set_sata);
1855 object_class_property_set_description(oc, PC_MACHINE_SATA,
1856 "Enable/disable Serial ATA bus");
1857
1858 object_class_property_add_bool(oc, "hpet",
1859 pc_machine_get_hpet, pc_machine_set_hpet);
1860 object_class_property_set_description(oc, "hpet",
1861 "Enable/disable high precision event timer emulation");
1862
1863 object_class_property_add_bool(oc, PC_MACHINE_I8042,
1864 pc_machine_get_i8042, pc_machine_set_i8042);
1865
1866 object_class_property_add_bool(oc, "default-bus-bypass-iommu",
1867 pc_machine_get_default_bus_bypass_iommu,
1868 pc_machine_set_default_bus_bypass_iommu);
1869
1870 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size",
1871 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size,
1872 NULL, NULL);
1873 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE,
1874 "Maximum combined firmware size");
1875
1876 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str",
1877 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep,
1878 NULL, NULL);
1879 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP,
1880 "SMBIOS Entry Point type [32, 64]");
1881 }
1882
1883 static const TypeInfo pc_machine_info = {
1884 .name = TYPE_PC_MACHINE,
1885 .parent = TYPE_X86_MACHINE,
1886 .abstract = true,
1887 .instance_size = sizeof(PCMachineState),
1888 .instance_init = pc_machine_initfn,
1889 .class_size = sizeof(PCMachineClass),
1890 .class_init = pc_machine_class_init,
1891 .interfaces = (InterfaceInfo[]) {
1892 { TYPE_HOTPLUG_HANDLER },
1893 { }
1894 },
1895 };
1896
1897 static void pc_machine_register_types(void)
1898 {
1899 type_register_static(&pc_machine_info);
1900 }
1901
1902 type_init(pc_machine_register_types)
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