tests/tco-test.c

   1 /*
   2  * QEMU ICH9 TCO emulation tests
   3  *
   4  * Copyright (c) 2015 Paulo Alcantara <pcacjr@zytor.com>
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   7  * See the COPYING file in the top-level directory.
   8  */
   9 #include "qemu/osdep.h"
  10
  11 #include "libqtest.h"
  12 #include "libqos/pci.h"
  13 #include "libqos/pci-pc.h"
  14 #include "hw/pci/pci_regs.h"
  15 #include "hw/i386/ich9.h"
  16 #include "hw/acpi/ich9.h"
  17 #include "hw/acpi/tco.h"
  18
  19 #define RCBA_BASE_ADDR    0xfed1c000
  20 #define PM_IO_BASE_ADDR   0xb000
  21
  22 enum {
  23     TCO_RLD_DEFAULT         = 0x0000,
  24     TCO_DAT_IN_DEFAULT      = 0x00,
  25     TCO_DAT_OUT_DEFAULT     = 0x00,
  26     TCO1_STS_DEFAULT        = 0x0000,
  27     TCO2_STS_DEFAULT        = 0x0000,
  28     TCO1_CNT_DEFAULT        = 0x0000,
  29     TCO2_CNT_DEFAULT        = 0x0008,
  30     TCO_MESSAGE1_DEFAULT    = 0x00,
  31     TCO_MESSAGE2_DEFAULT    = 0x00,
  32     TCO_WDCNT_DEFAULT       = 0x00,
  33     TCO_TMR_DEFAULT         = 0x0004,
  34     SW_IRQ_GEN_DEFAULT      = 0x03,
  35 };
  36
  37 #define TCO_SECS_TO_TICKS(secs)     (((secs) * 10) / 6)
  38 #define TCO_TICKS_TO_SECS(ticks)    (((ticks) * 6) / 10)
  39
  40 typedef struct {
  41     const char *args;
  42     bool noreboot;
  43     QPCIDevice *dev;
  44     QPCIBar tco_io_bar;
  45     QPCIBus *bus;
  46 } TestData;
  47
  48 static void test_end(TestData *d)
  49 {
  50     g_free(d->dev);
  51     qpci_free_pc(d->bus);
  52     qtest_end();
  53 }
  54
  55 static void test_init(TestData *d)
  56 {
  57     QTestState *qs;
  58     char *s;
  59
  60     s = g_strdup_printf("-machine q35 %s %s",
  61                         d->noreboot ? "" : "-global ICH9-LPC.noreboot=false",
  62                         !d->args ? "" : d->args);
  63     qs = qtest_start(s);
  64     qtest_irq_intercept_in(qs, "ioapic");
  65     g_free(s);
  66
  67     d->bus = qpci_init_pc(NULL);
  68     d->dev = qpci_device_find(d->bus, QPCI_DEVFN(0x1f, 0x00));
  69     g_assert(d->dev != NULL);
  70
  71     qpci_device_enable(d->dev);
  72
  73     /* set ACPI PM I/O space base address */
  74     qpci_config_writel(d->dev, ICH9_LPC_PMBASE, PM_IO_BASE_ADDR | 0x1);
  75     /* enable ACPI I/O */
  76     qpci_config_writeb(d->dev, ICH9_LPC_ACPI_CTRL, 0x80);
  77     /* set Root Complex BAR */
  78     qpci_config_writel(d->dev, ICH9_LPC_RCBA, RCBA_BASE_ADDR | 0x1);
  79
  80     d->tco_io_bar = qpci_legacy_iomap(d->dev, PM_IO_BASE_ADDR + 0x60);
  81 }
  82
  83 static void stop_tco(const TestData *d)
  84 {
  85     uint32_t val;
  86
  87     val = qpci_io_readw(d->dev, d->tco_io_bar, TCO1_CNT);
  88     val |= TCO_TMR_HLT;
  89     qpci_io_writew(d->dev, d->tco_io_bar, TCO1_CNT, val);
  90 }
  91
  92 static void start_tco(const TestData *d)
  93 {
  94     uint32_t val;
  95
  96     val = qpci_io_readw(d->dev, d->tco_io_bar, TCO1_CNT);
  97     val &= ~TCO_TMR_HLT;
  98     qpci_io_writew(d->dev, d->tco_io_bar, TCO1_CNT, val);
  99 }
 100
 101 static void load_tco(const TestData *d)
 102 {
 103     qpci_io_writew(d->dev, d->tco_io_bar, TCO_RLD, 4);
 104 }
 105
 106 static void set_tco_timeout(const TestData *d, uint16_t ticks)
 107 {
 108     qpci_io_writew(d->dev, d->tco_io_bar, TCO_TMR, ticks);
 109 }
 110
 111 static void clear_tco_status(const TestData *d)
 112 {
 113     qpci_io_writew(d->dev, d->tco_io_bar, TCO1_STS, 0x0008);
 114     qpci_io_writew(d->dev, d->tco_io_bar, TCO2_STS, 0x0002);
 115     qpci_io_writew(d->dev, d->tco_io_bar, TCO2_STS, 0x0004);
 116 }
 117
 118 static void reset_on_second_timeout(bool enable)
 119 {
 120     uint32_t val;
 121
 122     val = readl(RCBA_BASE_ADDR + ICH9_CC_GCS);
 123     if (enable) {
 124         val &= ~ICH9_CC_GCS_NO_REBOOT;
 125     } else {
 126         val |= ICH9_CC_GCS_NO_REBOOT;
 127     }
 128     writel(RCBA_BASE_ADDR + ICH9_CC_GCS, val);
 129 }
 130
 131 static void test_tco_defaults(void)
 132 {
 133     TestData d;
 134
 135     d.args = NULL;
 136     d.noreboot = true;
 137     test_init(&d);
 138     g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO_RLD), ==,
 139                     TCO_RLD_DEFAULT);
 140     /* TCO_DAT_IN & TCO_DAT_OUT */
 141     g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO_DAT_IN), ==,
 142                     (TCO_DAT_OUT_DEFAULT << 8) | TCO_DAT_IN_DEFAULT);
 143     /* TCO1_STS & TCO2_STS */
 144     g_assert_cmpint(qpci_io_readl(d.dev, d.tco_io_bar, TCO1_STS), ==,
 145                     (TCO2_STS_DEFAULT << 16) | TCO1_STS_DEFAULT);
 146     /* TCO1_CNT & TCO2_CNT */
 147     g_assert_cmpint(qpci_io_readl(d.dev, d.tco_io_bar, TCO1_CNT), ==,
 148                     (TCO2_CNT_DEFAULT << 16) | TCO1_CNT_DEFAULT);
 149     /* TCO_MESSAGE1 & TCO_MESSAGE2 */
 150     g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO_MESSAGE1), ==,
 151                     (TCO_MESSAGE2_DEFAULT << 8) | TCO_MESSAGE1_DEFAULT);
 152     g_assert_cmpint(qpci_io_readb(d.dev, d.tco_io_bar, TCO_WDCNT), ==,
 153                     TCO_WDCNT_DEFAULT);
 154     g_assert_cmpint(qpci_io_readb(d.dev, d.tco_io_bar, SW_IRQ_GEN), ==,
 155                     SW_IRQ_GEN_DEFAULT);
 156     g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO_TMR), ==,
 157                     TCO_TMR_DEFAULT);
 158     test_end(&d);
 159 }
 160
 161 static void test_tco_timeout(void)
 162 {
 163     TestData d;
 164     const uint16_t ticks = TCO_SECS_TO_TICKS(4);
 165     uint32_t val;
 166     int ret;
 167
 168     d.args = NULL;
 169     d.noreboot = true;
 170     test_init(&d);
 171
 172     stop_tco(&d);
 173     clear_tco_status(&d);
 174     reset_on_second_timeout(false);
 175     set_tco_timeout(&d, ticks);
 176     load_tco(&d);
 177     start_tco(&d);
 178     clock_step(ticks * TCO_TICK_NSEC);
 179
 180     /* test first timeout */
 181     val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
 182     ret = val & TCO_TIMEOUT ? 1 : 0;
 183     g_assert(ret == 1);
 184
 185     /* test clearing timeout bit */
 186     val |= TCO_TIMEOUT;
 187     qpci_io_writew(d.dev, d.tco_io_bar, TCO1_STS, val);
 188     val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
 189     ret = val & TCO_TIMEOUT ? 1 : 0;
 190     g_assert(ret == 0);
 191
 192     /* test second timeout */
 193     clock_step(ticks * TCO_TICK_NSEC);
 194     val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
 195     ret = val & TCO_TIMEOUT ? 1 : 0;
 196     g_assert(ret == 1);
 197     val = qpci_io_readw(d.dev, d.tco_io_bar, TCO2_STS);
 198     ret = val & TCO_SECOND_TO_STS ? 1 : 0;
 199     g_assert(ret == 1);
 200
 201     stop_tco(&d);
 202     test_end(&d);
 203 }
 204
 205 static void test_tco_max_timeout(void)
 206 {
 207     TestData d;
 208     const uint16_t ticks = 0xffff;
 209     uint32_t val;
 210     int ret;
 211
 212     d.args = NULL;
 213     d.noreboot = true;
 214     test_init(&d);
 215
 216     stop_tco(&d);
 217     clear_tco_status(&d);
 218     reset_on_second_timeout(false);
 219     set_tco_timeout(&d, ticks);
 220     load_tco(&d);
 221     start_tco(&d);
 222     clock_step(((ticks & TCO_TMR_MASK) - 1) * TCO_TICK_NSEC);
 223
 224     val = qpci_io_readw(d.dev, d.tco_io_bar, TCO_RLD);
 225     g_assert_cmpint(val & TCO_RLD_MASK, ==, 1);
 226     val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
 227     ret = val & TCO_TIMEOUT ? 1 : 0;
 228     g_assert(ret == 0);
 229     clock_step(TCO_TICK_NSEC);
 230     val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
 231     ret = val & TCO_TIMEOUT ? 1 : 0;
 232     g_assert(ret == 1);
 233
 234     stop_tco(&d);
 235     test_end(&d);
 236 }
 237
 238 static QDict *get_watchdog_action(void)
 239 {
 240     QDict *ev = qmp("");
 241     QDict *data;
 242     g_assert(!strcmp(qdict_get_str(ev, "event"), "WATCHDOG"));
 243
 244     data = qdict_get_qdict(ev, "data");
 245     QINCREF(data);
 246     QDECREF(ev);
 247     return data;
 248 }
 249
 250 static void test_tco_second_timeout_pause(void)
 251 {
 252     TestData td;
 253     const uint16_t ticks = TCO_SECS_TO_TICKS(32);
 254     QDict *ad;
 255
 256     td.args = "-watchdog-action pause";
 257     td.noreboot = false;
 258     test_init(&td);
 259
 260     stop_tco(&td);
 261     clear_tco_status(&td);
 262     reset_on_second_timeout(true);
 263     set_tco_timeout(&td, TCO_SECS_TO_TICKS(16));
 264     load_tco(&td);
 265     start_tco(&td);
 266     clock_step(ticks * TCO_TICK_NSEC * 2);
 267     ad = get_watchdog_action();
 268     g_assert(!strcmp(qdict_get_str(ad, "action"), "pause"));
 269     QDECREF(ad);
 270
 271     stop_tco(&td);
 272     test_end(&td);
 273 }
 274
 275 static void test_tco_second_timeout_reset(void)
 276 {
 277     TestData td;
 278     const uint16_t ticks = TCO_SECS_TO_TICKS(16);
 279     QDict *ad;
 280
 281     td.args = "-watchdog-action reset";
 282     td.noreboot = false;
 283     test_init(&td);
 284
 285     stop_tco(&td);
 286     clear_tco_status(&td);
 287     reset_on_second_timeout(true);
 288     set_tco_timeout(&td, TCO_SECS_TO_TICKS(16));
 289     load_tco(&td);
 290     start_tco(&td);
 291     clock_step(ticks * TCO_TICK_NSEC * 2);
 292     ad = get_watchdog_action();
 293     g_assert(!strcmp(qdict_get_str(ad, "action"), "reset"));
 294     QDECREF(ad);
 295
 296     stop_tco(&td);
 297     test_end(&td);
 298 }
 299
 300 static void test_tco_second_timeout_shutdown(void)
 301 {
 302     TestData td;
 303     const uint16_t ticks = TCO_SECS_TO_TICKS(128);
 304     QDict *ad;
 305
 306     td.args = "-watchdog-action shutdown";
 307     td.noreboot = false;
 308     test_init(&td);
 309
 310     stop_tco(&td);
 311     clear_tco_status(&td);
 312     reset_on_second_timeout(true);
 313     set_tco_timeout(&td, ticks);
 314     load_tco(&td);
 315     start_tco(&td);
 316     clock_step(ticks * TCO_TICK_NSEC * 2);
 317     ad = get_watchdog_action();
 318     g_assert(!strcmp(qdict_get_str(ad, "action"), "shutdown"));
 319     QDECREF(ad);
 320
 321     stop_tco(&td);
 322     test_end(&td);
 323 }
 324
 325 static void test_tco_second_timeout_none(void)
 326 {
 327     TestData td;
 328     const uint16_t ticks = TCO_SECS_TO_TICKS(256);
 329     QDict *ad;
 330
 331     td.args = "-watchdog-action none";
 332     td.noreboot = false;
 333     test_init(&td);
 334
 335     stop_tco(&td);
 336     clear_tco_status(&td);
 337     reset_on_second_timeout(true);
 338     set_tco_timeout(&td, ticks);
 339     load_tco(&td);
 340     start_tco(&td);
 341     clock_step(ticks * TCO_TICK_NSEC * 2);
 342     ad = get_watchdog_action();
 343     g_assert(!strcmp(qdict_get_str(ad, "action"), "none"));
 344     QDECREF(ad);
 345
 346     stop_tco(&td);
 347     test_end(&td);
 348 }
 349
 350 static void test_tco_ticks_counter(void)
 351 {
 352     TestData d;
 353     uint16_t ticks = TCO_SECS_TO_TICKS(8);
 354     uint16_t rld;
 355
 356     d.args = NULL;
 357     d.noreboot = true;
 358     test_init(&d);
 359
 360     stop_tco(&d);
 361     clear_tco_status(&d);
 362     reset_on_second_timeout(false);
 363     set_tco_timeout(&d, ticks);
 364     load_tco(&d);
 365     start_tco(&d);
 366
 367     do {
 368         rld = qpci_io_readw(d.dev, d.tco_io_bar, TCO_RLD) & TCO_RLD_MASK;
 369         g_assert_cmpint(rld, ==, ticks);
 370         clock_step(TCO_TICK_NSEC);
 371         ticks--;
 372     } while (!(qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS) & TCO_TIMEOUT));
 373
 374     stop_tco(&d);
 375     test_end(&d);
 376 }
 377
 378 static void test_tco1_control_bits(void)
 379 {
 380     TestData d;
 381     uint16_t val;
 382
 383     d.args = NULL;
 384     d.noreboot = true;
 385     test_init(&d);
 386
 387     val = TCO_LOCK;
 388     qpci_io_writew(d.dev, d.tco_io_bar, TCO1_CNT, val);
 389     val &= ~TCO_LOCK;
 390     qpci_io_writew(d.dev, d.tco_io_bar, TCO1_CNT, val);
 391     g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO1_CNT), ==,
 392                     TCO_LOCK);
 393     test_end(&d);
 394 }
 395
 396 static void test_tco1_status_bits(void)
 397 {
 398     TestData d;
 399     uint16_t ticks = 8;
 400     uint16_t val;
 401     int ret;
 402
 403     d.args = NULL;
 404     d.noreboot = true;
 405     test_init(&d);
 406
 407     stop_tco(&d);
 408     clear_tco_status(&d);
 409     reset_on_second_timeout(false);
 410     set_tco_timeout(&d, ticks);
 411     load_tco(&d);
 412     start_tco(&d);
 413     clock_step(ticks * TCO_TICK_NSEC);
 414
 415     qpci_io_writeb(d.dev, d.tco_io_bar, TCO_DAT_IN, 0);
 416     qpci_io_writeb(d.dev, d.tco_io_bar, TCO_DAT_OUT, 0);
 417     val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
 418     ret = val & (TCO_TIMEOUT | SW_TCO_SMI | TCO_INT_STS) ? 1 : 0;
 419     g_assert(ret == 1);
 420     qpci_io_writew(d.dev, d.tco_io_bar, TCO1_STS, val);
 421     g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS), ==, 0);
 422     test_end(&d);
 423 }
 424
 425 static void test_tco2_status_bits(void)
 426 {
 427     TestData d;
 428     uint16_t ticks = 8;
 429     uint16_t val;
 430     int ret;
 431
 432     d.args = NULL;
 433     d.noreboot = true;
 434     test_init(&d);
 435
 436     stop_tco(&d);
 437     clear_tco_status(&d);
 438     reset_on_second_timeout(true);
 439     set_tco_timeout(&d, ticks);
 440     load_tco(&d);
 441     start_tco(&d);
 442     clock_step(ticks * TCO_TICK_NSEC * 2);
 443
 444     val = qpci_io_readw(d.dev, d.tco_io_bar, TCO2_STS);
 445     ret = val & (TCO_SECOND_TO_STS | TCO_BOOT_STS) ? 1 : 0;
 446     g_assert(ret == 1);
 447     qpci_io_writew(d.dev, d.tco_io_bar, TCO2_STS, val);
 448     g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO2_STS), ==, 0);
 449     test_end(&d);
 450 }
 451
 452 int main(int argc, char **argv)
 453 {
 454     g_test_init(&argc, &argv, NULL);
 455
 456     qtest_add_func("tco/defaults", test_tco_defaults);
 457     qtest_add_func("tco/timeout/no_action", test_tco_timeout);
 458     qtest_add_func("tco/timeout/no_action/max", test_tco_max_timeout);
 459     qtest_add_func("tco/second_timeout/pause", test_tco_second_timeout_pause);
 460     qtest_add_func("tco/second_timeout/reset", test_tco_second_timeout_reset);
 461     qtest_add_func("tco/second_timeout/shutdown",
 462                    test_tco_second_timeout_shutdown);
 463     qtest_add_func("tco/second_timeout/none", test_tco_second_timeout_none);
 464     qtest_add_func("tco/counter", test_tco_ticks_counter);
 465     qtest_add_func("tco/tco1_control/bits", test_tco1_control_bits);
 466     qtest_add_func("tco/tco1_status/bits", test_tco1_status_bits);
 467     qtest_add_func("tco/tco2_status/bits", test_tco2_status_bits);
 468     return g_test_run();
 469 }