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hw/net: add MII definitions
[qemu/kevin.git] / hw / sparc / sun4m.c
blob873cd7df9adbece6a80ff01b10036eb8c245973b
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "qemu/osdep.h"
25 #include "qapi/error.h"
26 #include "qemu-common.h"
27 #include "cpu.h"
28 #include "hw/sysbus.h"
29 #include "qemu/error-report.h"
30 #include "qemu/timer.h"
31 #include "hw/sparc/sun4m.h"
32 #include "hw/timer/m48t59.h"
33 #include "hw/sparc/sparc32_dma.h"
34 #include "hw/block/fdc.h"
35 #include "sysemu/sysemu.h"
36 #include "net/net.h"
37 #include "hw/boards.h"
38 #include "hw/scsi/esp.h"
39 #include "hw/i386/pc.h"
40 #include "hw/isa/isa.h"
41 #include "hw/nvram/sun_nvram.h"
42 #include "hw/nvram/chrp_nvram.h"
43 #include "hw/nvram/fw_cfg.h"
44 #include "hw/char/escc.h"
45 #include "hw/empty_slot.h"
46 #include "hw/loader.h"
47 #include "elf.h"
48 #include "sysemu/block-backend.h"
49 #include "trace.h"
50 #include "qemu/cutils.h"
51
52 /*
53 * Sun4m architecture was used in the following machines:
54 *
55 * SPARCserver 6xxMP/xx
56 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
57 * SPARCclassic X (4/10)
58 * SPARCstation LX/ZX (4/30)
59 * SPARCstation Voyager
60 * SPARCstation 10/xx, SPARCserver 10/xx
61 * SPARCstation 5, SPARCserver 5
62 * SPARCstation 20/xx, SPARCserver 20
63 * SPARCstation 4
64 *
65 * See for example: http://www.sunhelp.org/faq/sunref1.html
66 */
67
68 #define KERNEL_LOAD_ADDR 0x00004000
69 #define CMDLINE_ADDR 0x007ff000
70 #define INITRD_LOAD_ADDR 0x00800000
71 #define PROM_SIZE_MAX (1024 * 1024)
72 #define PROM_VADDR 0xffd00000
73 #define PROM_FILENAME "openbios-sparc32"
74 #define CFG_ADDR 0xd00000510ULL
75 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
76 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
77 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
78
79 #define MAX_CPUS 16
80 #define MAX_PILS 16
81 #define MAX_VSIMMS 4
82
83 #define ESCC_CLOCK 4915200
84
85 struct sun4m_hwdef {
86 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
87 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
88 hwaddr serial_base, fd_base;
89 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
90 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
91 hwaddr bpp_base, dbri_base, sx_base;
92 struct {
93 hwaddr reg_base, vram_base;
94 } vsimm[MAX_VSIMMS];
95 hwaddr ecc_base;
96 uint64_t max_mem;
97 const char * const default_cpu_model;
98 uint32_t ecc_version;
99 uint32_t iommu_version;
100 uint16_t machine_id;
101 uint8_t nvram_machine_id;
102 };
103
104 void DMA_init(ISABus *bus, int high_page_enable)
105 {
106 }
107
108 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
109 Error **errp)
110 {
111 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
112 }
113
114 static void nvram_init(Nvram *nvram, uint8_t *macaddr,
115 const char *cmdline, const char *boot_devices,
116 ram_addr_t RAM_size, uint32_t kernel_size,
117 int width, int height, int depth,
118 int nvram_machine_id, const char *arch)
119 {
120 unsigned int i;
121 int sysp_end;
122 uint8_t image[0x1ff0];
123 NvramClass *k = NVRAM_GET_CLASS(nvram);
124
125 memset(image, '\0', sizeof(image));
126
127 /* OpenBIOS nvram variables partition */
128 sysp_end = chrp_nvram_create_system_partition(image, 0);
129
130 /* Free space partition */
131 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
132
133 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
134 nvram_machine_id);
135
136 for (i = 0; i < sizeof(image); i++) {
137 (k->write)(nvram, i, image[i]);
138 }
139 }
140
141 void cpu_check_irqs(CPUSPARCState *env)
142 {
143 CPUState *cs;
144
145 /* We should be holding the BQL before we mess with IRQs */
146 g_assert(qemu_mutex_iothread_locked());
147
148 if (env->pil_in && (env->interrupt_index == 0 ||
149 (env->interrupt_index & ~15) == TT_EXTINT)) {
150 unsigned int i;
151
152 for (i = 15; i > 0; i--) {
153 if (env->pil_in & (1 << i)) {
154 int old_interrupt = env->interrupt_index;
155
156 env->interrupt_index = TT_EXTINT | i;
157 if (old_interrupt != env->interrupt_index) {
158 cs = CPU(sparc_env_get_cpu(env));
159 trace_sun4m_cpu_interrupt(i);
160 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
161 }
162 break;
163 }
164 }
165 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
166 cs = CPU(sparc_env_get_cpu(env));
167 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
168 env->interrupt_index = 0;
169 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
170 }
171 }
172
173 static void cpu_kick_irq(SPARCCPU *cpu)
174 {
175 CPUSPARCState *env = &cpu->env;
176 CPUState *cs = CPU(cpu);
177
178 cs->halted = 0;
179 cpu_check_irqs(env);
180 qemu_cpu_kick(cs);
181 }
182
183 static void cpu_set_irq(void *opaque, int irq, int level)
184 {
185 SPARCCPU *cpu = opaque;
186 CPUSPARCState *env = &cpu->env;
187
188 if (level) {
189 trace_sun4m_cpu_set_irq_raise(irq);
190 env->pil_in |= 1 << irq;
191 cpu_kick_irq(cpu);
192 } else {
193 trace_sun4m_cpu_set_irq_lower(irq);
194 env->pil_in &= ~(1 << irq);
195 cpu_check_irqs(env);
196 }
197 }
198
199 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
200 {
201 }
202
203 static void main_cpu_reset(void *opaque)
204 {
205 SPARCCPU *cpu = opaque;
206 CPUState *cs = CPU(cpu);
207
208 cpu_reset(cs);
209 cs->halted = 0;
210 }
211
212 static void secondary_cpu_reset(void *opaque)
213 {
214 SPARCCPU *cpu = opaque;
215 CPUState *cs = CPU(cpu);
216
217 cpu_reset(cs);
218 cs->halted = 1;
219 }
220
221 static void cpu_halt_signal(void *opaque, int irq, int level)
222 {
223 if (level && current_cpu) {
224 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
225 }
226 }
227
228 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
229 {
230 return addr - 0xf0000000ULL;
231 }
232
233 static unsigned long sun4m_load_kernel(const char *kernel_filename,
234 const char *initrd_filename,
235 ram_addr_t RAM_size)
236 {
237 int linux_boot;
238 unsigned int i;
239 long initrd_size, kernel_size;
240 uint8_t *ptr;
241
242 linux_boot = (kernel_filename != NULL);
243
244 kernel_size = 0;
245 if (linux_boot) {
246 int bswap_needed;
247
248 #ifdef BSWAP_NEEDED
249 bswap_needed = 1;
250 #else
251 bswap_needed = 0;
252 #endif
253 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
254 NULL, NULL, NULL, 1, EM_SPARC, 0, 0);
255 if (kernel_size < 0)
256 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
257 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
258 TARGET_PAGE_SIZE);
259 if (kernel_size < 0)
260 kernel_size = load_image_targphys(kernel_filename,
261 KERNEL_LOAD_ADDR,
262 RAM_size - KERNEL_LOAD_ADDR);
263 if (kernel_size < 0) {
264 fprintf(stderr, "qemu: could not load kernel '%s'\n",
265 kernel_filename);
266 exit(1);
267 }
268
269 /* load initrd */
270 initrd_size = 0;
271 if (initrd_filename) {
272 initrd_size = load_image_targphys(initrd_filename,
273 INITRD_LOAD_ADDR,
274 RAM_size - INITRD_LOAD_ADDR);
275 if (initrd_size < 0) {
276 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
277 initrd_filename);
278 exit(1);
279 }
280 }
281 if (initrd_size > 0) {
282 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
283 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
284 if (ldl_p(ptr) == 0x48647253) { // HdrS
285 stl_p(ptr + 16, INITRD_LOAD_ADDR);
286 stl_p(ptr + 20, initrd_size);
287 break;
288 }
289 }
290 }
291 }
292 return kernel_size;
293 }
294
295 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
296 {
297 DeviceState *dev;
298 SysBusDevice *s;
299
300 dev = qdev_create(NULL, "iommu");
301 qdev_prop_set_uint32(dev, "version", version);
302 qdev_init_nofail(dev);
303 s = SYS_BUS_DEVICE(dev);
304 sysbus_connect_irq(s, 0, irq);
305 sysbus_mmio_map(s, 0, addr);
306
307 return s;
308 }
309
310 static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq,
311 void *iommu, qemu_irq *dev_irq, int is_ledma)
312 {
313 DeviceState *dev;
314 SysBusDevice *s;
315
316 dev = qdev_create(NULL, "sparc32_dma");
317 qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
318 qdev_prop_set_uint32(dev, "is_ledma", is_ledma);
319 qdev_init_nofail(dev);
320 s = SYS_BUS_DEVICE(dev);
321 sysbus_connect_irq(s, 0, parent_irq);
322 *dev_irq = qdev_get_gpio_in(dev, 0);
323 sysbus_mmio_map(s, 0, daddr);
324
325 return s;
326 }
327
328 static void lance_init(NICInfo *nd, hwaddr leaddr,
329 void *dma_opaque, qemu_irq irq)
330 {
331 DeviceState *dev;
332 SysBusDevice *s;
333 qemu_irq reset;
334
335 qemu_check_nic_model(&nd_table[0], "lance");
336
337 dev = qdev_create(NULL, "lance");
338 qdev_set_nic_properties(dev, nd);
339 qdev_prop_set_ptr(dev, "dma", dma_opaque);
340 qdev_init_nofail(dev);
341 s = SYS_BUS_DEVICE(dev);
342 sysbus_mmio_map(s, 0, leaddr);
343 sysbus_connect_irq(s, 0, irq);
344 reset = qdev_get_gpio_in(dev, 0);
345 qdev_connect_gpio_out(dma_opaque, 0, reset);
346 }
347
348 static DeviceState *slavio_intctl_init(hwaddr addr,
349 hwaddr addrg,
350 qemu_irq **parent_irq)
351 {
352 DeviceState *dev;
353 SysBusDevice *s;
354 unsigned int i, j;
355
356 dev = qdev_create(NULL, "slavio_intctl");
357 qdev_init_nofail(dev);
358
359 s = SYS_BUS_DEVICE(dev);
360
361 for (i = 0; i < MAX_CPUS; i++) {
362 for (j = 0; j < MAX_PILS; j++) {
363 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
364 }
365 }
366 sysbus_mmio_map(s, 0, addrg);
367 for (i = 0; i < MAX_CPUS; i++) {
368 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
369 }
370
371 return dev;
372 }
373
374 #define SYS_TIMER_OFFSET 0x10000ULL
375 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
376
377 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
378 qemu_irq *cpu_irqs, unsigned int num_cpus)
379 {
380 DeviceState *dev;
381 SysBusDevice *s;
382 unsigned int i;
383
384 dev = qdev_create(NULL, "slavio_timer");
385 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
386 qdev_init_nofail(dev);
387 s = SYS_BUS_DEVICE(dev);
388 sysbus_connect_irq(s, 0, master_irq);
389 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
390
391 for (i = 0; i < MAX_CPUS; i++) {
392 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
393 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
394 }
395 }
396
397 static qemu_irq slavio_system_powerdown;
398
399 static void slavio_powerdown_req(Notifier *n, void *opaque)
400 {
401 qemu_irq_raise(slavio_system_powerdown);
402 }
403
404 static Notifier slavio_system_powerdown_notifier = {
405 .notify = slavio_powerdown_req
406 };
407
408 #define MISC_LEDS 0x01600000
409 #define MISC_CFG 0x01800000
410 #define MISC_DIAG 0x01a00000
411 #define MISC_MDM 0x01b00000
412 #define MISC_SYS 0x01f00000
413
414 static void slavio_misc_init(hwaddr base,
415 hwaddr aux1_base,
416 hwaddr aux2_base, qemu_irq irq,
417 qemu_irq fdc_tc)
418 {
419 DeviceState *dev;
420 SysBusDevice *s;
421
422 dev = qdev_create(NULL, "slavio_misc");
423 qdev_init_nofail(dev);
424 s = SYS_BUS_DEVICE(dev);
425 if (base) {
426 /* 8 bit registers */
427 /* Slavio control */
428 sysbus_mmio_map(s, 0, base + MISC_CFG);
429 /* Diagnostics */
430 sysbus_mmio_map(s, 1, base + MISC_DIAG);
431 /* Modem control */
432 sysbus_mmio_map(s, 2, base + MISC_MDM);
433 /* 16 bit registers */
434 /* ss600mp diag LEDs */
435 sysbus_mmio_map(s, 3, base + MISC_LEDS);
436 /* 32 bit registers */
437 /* System control */
438 sysbus_mmio_map(s, 4, base + MISC_SYS);
439 }
440 if (aux1_base) {
441 /* AUX 1 (Misc System Functions) */
442 sysbus_mmio_map(s, 5, aux1_base);
443 }
444 if (aux2_base) {
445 /* AUX 2 (Software Powerdown Control) */
446 sysbus_mmio_map(s, 6, aux2_base);
447 }
448 sysbus_connect_irq(s, 0, irq);
449 sysbus_connect_irq(s, 1, fdc_tc);
450 slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
451 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
452 }
453
454 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
455 {
456 DeviceState *dev;
457 SysBusDevice *s;
458
459 dev = qdev_create(NULL, "eccmemctl");
460 qdev_prop_set_uint32(dev, "version", version);
461 qdev_init_nofail(dev);
462 s = SYS_BUS_DEVICE(dev);
463 sysbus_connect_irq(s, 0, irq);
464 sysbus_mmio_map(s, 0, base);
465 if (version == 0) { // SS-600MP only
466 sysbus_mmio_map(s, 1, base + 0x1000);
467 }
468 }
469
470 static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
471 {
472 DeviceState *dev;
473 SysBusDevice *s;
474
475 dev = qdev_create(NULL, "apc");
476 qdev_init_nofail(dev);
477 s = SYS_BUS_DEVICE(dev);
478 /* Power management (APC) XXX: not a Slavio device */
479 sysbus_mmio_map(s, 0, power_base);
480 sysbus_connect_irq(s, 0, cpu_halt);
481 }
482
483 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
484 int height, int depth)
485 {
486 DeviceState *dev;
487 SysBusDevice *s;
488
489 dev = qdev_create(NULL, "SUNW,tcx");
490 qdev_prop_set_uint32(dev, "vram_size", vram_size);
491 qdev_prop_set_uint16(dev, "width", width);
492 qdev_prop_set_uint16(dev, "height", height);
493 qdev_prop_set_uint16(dev, "depth", depth);
494 qdev_prop_set_uint64(dev, "prom_addr", addr);
495 qdev_init_nofail(dev);
496 s = SYS_BUS_DEVICE(dev);
497
498 /* 10/ROM : FCode ROM */
499 sysbus_mmio_map(s, 0, addr);
500 /* 2/STIP : Stipple */
501 sysbus_mmio_map(s, 1, addr + 0x04000000ULL);
502 /* 3/BLIT : Blitter */
503 sysbus_mmio_map(s, 2, addr + 0x06000000ULL);
504 /* 5/RSTIP : Raw Stipple */
505 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL);
506 /* 6/RBLIT : Raw Blitter */
507 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL);
508 /* 7/TEC : Transform Engine */
509 sysbus_mmio_map(s, 5, addr + 0x00700000ULL);
510 /* 8/CMAP : DAC */
511 sysbus_mmio_map(s, 6, addr + 0x00200000ULL);
512 /* 9/THC : */
513 if (depth == 8) {
514 sysbus_mmio_map(s, 7, addr + 0x00300000ULL);
515 } else {
516 sysbus_mmio_map(s, 7, addr + 0x00301000ULL);
517 }
518 /* 11/DHC : */
519 sysbus_mmio_map(s, 8, addr + 0x00240000ULL);
520 /* 12/ALT : */
521 sysbus_mmio_map(s, 9, addr + 0x00280000ULL);
522 /* 0/DFB8 : 8-bit plane */
523 sysbus_mmio_map(s, 10, addr + 0x00800000ULL);
524 /* 1/DFB24 : 24bit plane */
525 sysbus_mmio_map(s, 11, addr + 0x02000000ULL);
526 /* 4/RDFB32: Raw framebuffer. Control plane */
527 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL);
528 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
529 if (depth == 8) {
530 sysbus_mmio_map(s, 13, addr + 0x00301000ULL);
531 }
532
533 sysbus_connect_irq(s, 0, irq);
534 }
535
536 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
537 int height, int depth)
538 {
539 DeviceState *dev;
540 SysBusDevice *s;
541
542 dev = qdev_create(NULL, "cgthree");
543 qdev_prop_set_uint32(dev, "vram-size", vram_size);
544 qdev_prop_set_uint16(dev, "width", width);
545 qdev_prop_set_uint16(dev, "height", height);
546 qdev_prop_set_uint16(dev, "depth", depth);
547 qdev_prop_set_uint64(dev, "prom-addr", addr);
548 qdev_init_nofail(dev);
549 s = SYS_BUS_DEVICE(dev);
550
551 /* FCode ROM */
552 sysbus_mmio_map(s, 0, addr);
553 /* DAC */
554 sysbus_mmio_map(s, 1, addr + 0x400000ULL);
555 /* 8-bit plane */
556 sysbus_mmio_map(s, 2, addr + 0x800000ULL);
557
558 sysbus_connect_irq(s, 0, irq);
559 }
560
561 /* NCR89C100/MACIO Internal ID register */
562
563 #define TYPE_MACIO_ID_REGISTER "macio_idreg"
564
565 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
566
567 static void idreg_init(hwaddr addr)
568 {
569 DeviceState *dev;
570 SysBusDevice *s;
571
572 dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER);
573 qdev_init_nofail(dev);
574 s = SYS_BUS_DEVICE(dev);
575
576 sysbus_mmio_map(s, 0, addr);
577 cpu_physical_memory_write_rom(&address_space_memory,
578 addr, idreg_data, sizeof(idreg_data));
579 }
580
581 #define MACIO_ID_REGISTER(obj) \
582 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER)
583
584 typedef struct IDRegState {
585 SysBusDevice parent_obj;
586
587 MemoryRegion mem;
588 } IDRegState;
589
590 static int idreg_init1(SysBusDevice *dev)
591 {
592 IDRegState *s = MACIO_ID_REGISTER(dev);
593
594 memory_region_init_ram(&s->mem, OBJECT(s),
595 "sun4m.idreg", sizeof(idreg_data), &error_fatal);
596 vmstate_register_ram_global(&s->mem);
597 memory_region_set_readonly(&s->mem, true);
598 sysbus_init_mmio(dev, &s->mem);
599 return 0;
600 }
601
602 static void idreg_class_init(ObjectClass *klass, void *data)
603 {
604 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
605
606 k->init = idreg_init1;
607 }
608
609 static const TypeInfo idreg_info = {
610 .name = TYPE_MACIO_ID_REGISTER,
611 .parent = TYPE_SYS_BUS_DEVICE,
612 .instance_size = sizeof(IDRegState),
613 .class_init = idreg_class_init,
614 };
615
616 #define TYPE_TCX_AFX "tcx_afx"
617 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX)
618
619 typedef struct AFXState {
620 SysBusDevice parent_obj;
621
622 MemoryRegion mem;
623 } AFXState;
624
625 /* SS-5 TCX AFX register */
626 static void afx_init(hwaddr addr)
627 {
628 DeviceState *dev;
629 SysBusDevice *s;
630
631 dev = qdev_create(NULL, TYPE_TCX_AFX);
632 qdev_init_nofail(dev);
633 s = SYS_BUS_DEVICE(dev);
634
635 sysbus_mmio_map(s, 0, addr);
636 }
637
638 static int afx_init1(SysBusDevice *dev)
639 {
640 AFXState *s = TCX_AFX(dev);
641
642 memory_region_init_ram(&s->mem, OBJECT(s), "sun4m.afx", 4, &error_fatal);
643 vmstate_register_ram_global(&s->mem);
644 sysbus_init_mmio(dev, &s->mem);
645 return 0;
646 }
647
648 static void afx_class_init(ObjectClass *klass, void *data)
649 {
650 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
651
652 k->init = afx_init1;
653 }
654
655 static const TypeInfo afx_info = {
656 .name = TYPE_TCX_AFX,
657 .parent = TYPE_SYS_BUS_DEVICE,
658 .instance_size = sizeof(AFXState),
659 .class_init = afx_class_init,
660 };
661
662 #define TYPE_OPENPROM "openprom"
663 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
664
665 typedef struct PROMState {
666 SysBusDevice parent_obj;
667
668 MemoryRegion prom;
669 } PROMState;
670
671 /* Boot PROM (OpenBIOS) */
672 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
673 {
674 hwaddr *base_addr = (hwaddr *)opaque;
675 return addr + *base_addr - PROM_VADDR;
676 }
677
678 static void prom_init(hwaddr addr, const char *bios_name)
679 {
680 DeviceState *dev;
681 SysBusDevice *s;
682 char *filename;
683 int ret;
684
685 dev = qdev_create(NULL, TYPE_OPENPROM);
686 qdev_init_nofail(dev);
687 s = SYS_BUS_DEVICE(dev);
688
689 sysbus_mmio_map(s, 0, addr);
690
691 /* load boot prom */
692 if (bios_name == NULL) {
693 bios_name = PROM_FILENAME;
694 }
695 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
696 if (filename) {
697 ret = load_elf(filename, translate_prom_address, &addr, NULL,
698 NULL, NULL, 1, EM_SPARC, 0, 0);
699 if (ret < 0 || ret > PROM_SIZE_MAX) {
700 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
701 }
702 g_free(filename);
703 } else {
704 ret = -1;
705 }
706 if (ret < 0 || ret > PROM_SIZE_MAX) {
707 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
708 exit(1);
709 }
710 }
711
712 static int prom_init1(SysBusDevice *dev)
713 {
714 PROMState *s = OPENPROM(dev);
715
716 memory_region_init_ram(&s->prom, OBJECT(s), "sun4m.prom", PROM_SIZE_MAX,
717 &error_fatal);
718 vmstate_register_ram_global(&s->prom);
719 memory_region_set_readonly(&s->prom, true);
720 sysbus_init_mmio(dev, &s->prom);
721 return 0;
722 }
723
724 static Property prom_properties[] = {
725 {/* end of property list */},
726 };
727
728 static void prom_class_init(ObjectClass *klass, void *data)
729 {
730 DeviceClass *dc = DEVICE_CLASS(klass);
731 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
732
733 k->init = prom_init1;
734 dc->props = prom_properties;
735 }
736
737 static const TypeInfo prom_info = {
738 .name = TYPE_OPENPROM,
739 .parent = TYPE_SYS_BUS_DEVICE,
740 .instance_size = sizeof(PROMState),
741 .class_init = prom_class_init,
742 };
743
744 #define TYPE_SUN4M_MEMORY "memory"
745 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY)
746
747 typedef struct RamDevice {
748 SysBusDevice parent_obj;
749
750 MemoryRegion ram;
751 uint64_t size;
752 } RamDevice;
753
754 /* System RAM */
755 static int ram_init1(SysBusDevice *dev)
756 {
757 RamDevice *d = SUN4M_RAM(dev);
758
759 memory_region_allocate_system_memory(&d->ram, OBJECT(d), "sun4m.ram",
760 d->size);
761 sysbus_init_mmio(dev, &d->ram);
762 return 0;
763 }
764
765 static void ram_init(hwaddr addr, ram_addr_t RAM_size,
766 uint64_t max_mem)
767 {
768 DeviceState *dev;
769 SysBusDevice *s;
770 RamDevice *d;
771
772 /* allocate RAM */
773 if ((uint64_t)RAM_size > max_mem) {
774 fprintf(stderr,
775 "qemu: Too much memory for this machine: %d, maximum %d\n",
776 (unsigned int)(RAM_size / (1024 * 1024)),
777 (unsigned int)(max_mem / (1024 * 1024)));
778 exit(1);
779 }
780 dev = qdev_create(NULL, "memory");
781 s = SYS_BUS_DEVICE(dev);
782
783 d = SUN4M_RAM(dev);
784 d->size = RAM_size;
785 qdev_init_nofail(dev);
786
787 sysbus_mmio_map(s, 0, addr);
788 }
789
790 static Property ram_properties[] = {
791 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
792 DEFINE_PROP_END_OF_LIST(),
793 };
794
795 static void ram_class_init(ObjectClass *klass, void *data)
796 {
797 DeviceClass *dc = DEVICE_CLASS(klass);
798 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
799
800 k->init = ram_init1;
801 dc->props = ram_properties;
802 }
803
804 static const TypeInfo ram_info = {
805 .name = TYPE_SUN4M_MEMORY,
806 .parent = TYPE_SYS_BUS_DEVICE,
807 .instance_size = sizeof(RamDevice),
808 .class_init = ram_class_init,
809 };
810
811 static void cpu_devinit(const char *cpu_model, unsigned int id,
812 uint64_t prom_addr, qemu_irq **cpu_irqs)
813 {
814 CPUState *cs;
815 SPARCCPU *cpu;
816 CPUSPARCState *env;
817
818 cpu = cpu_sparc_init(cpu_model);
819 if (cpu == NULL) {
820 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
821 exit(1);
822 }
823 env = &cpu->env;
824
825 cpu_sparc_set_id(env, id);
826 if (id == 0) {
827 qemu_register_reset(main_cpu_reset, cpu);
828 } else {
829 qemu_register_reset(secondary_cpu_reset, cpu);
830 cs = CPU(cpu);
831 cs->halted = 1;
832 }
833 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
834 env->prom_addr = prom_addr;
835 }
836
837 static void dummy_fdc_tc(void *opaque, int irq, int level)
838 {
839 }
840
841 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
842 MachineState *machine)
843 {
844 DeviceState *slavio_intctl;
845 const char *cpu_model = machine->cpu_model;
846 unsigned int i;
847 void *iommu, *espdma, *ledma, *nvram;
848 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
849 espdma_irq, ledma_irq;
850 qemu_irq esp_reset, dma_enable;
851 qemu_irq fdc_tc;
852 unsigned long kernel_size;
853 DriveInfo *fd[MAX_FD];
854 FWCfgState *fw_cfg;
855 unsigned int num_vsimms;
856
857 /* init CPUs */
858 if (!cpu_model)
859 cpu_model = hwdef->default_cpu_model;
860
861 for(i = 0; i < smp_cpus; i++) {
862 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
863 }
864
865 for (i = smp_cpus; i < MAX_CPUS; i++)
866 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
867
868
869 /* set up devices */
870 ram_init(0, machine->ram_size, hwdef->max_mem);
871 /* models without ECC don't trap when missing ram is accessed */
872 if (!hwdef->ecc_base) {
873 empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size);
874 }
875
876 prom_init(hwdef->slavio_base, bios_name);
877
878 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
879 hwdef->intctl_base + 0x10000ULL,
880 cpu_irqs);
881
882 for (i = 0; i < 32; i++) {
883 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
884 }
885 for (i = 0; i < MAX_CPUS; i++) {
886 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
887 }
888
889 if (hwdef->idreg_base) {
890 idreg_init(hwdef->idreg_base);
891 }
892
893 if (hwdef->afx_base) {
894 afx_init(hwdef->afx_base);
895 }
896
897 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
898 slavio_irq[30]);
899
900 if (hwdef->iommu_pad_base) {
901 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
902 Software shouldn't use aliased addresses, neither should it crash
903 when does. Using empty_slot instead of aliasing can help with
904 debugging such accesses */
905 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
906 }
907
908 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
909 iommu, &espdma_irq, 0);
910
911 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
912 slavio_irq[16], iommu, &ledma_irq, 1);
913
914 if (graphic_depth != 8 && graphic_depth != 24) {
915 error_report("Unsupported depth: %d", graphic_depth);
916 exit (1);
917 }
918 num_vsimms = 0;
919 if (num_vsimms == 0) {
920 if (vga_interface_type == VGA_CG3) {
921 if (graphic_depth != 8) {
922 error_report("Unsupported depth: %d", graphic_depth);
923 exit(1);
924 }
925
926 if (!(graphic_width == 1024 && graphic_height == 768) &&
927 !(graphic_width == 1152 && graphic_height == 900)) {
928 error_report("Unsupported resolution: %d x %d", graphic_width,
929 graphic_height);
930 exit(1);
931 }
932
933 /* sbus irq 5 */
934 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
935 graphic_width, graphic_height, graphic_depth);
936 } else {
937 /* If no display specified, default to TCX */
938 if (graphic_depth != 8 && graphic_depth != 24) {
939 error_report("Unsupported depth: %d", graphic_depth);
940 exit(1);
941 }
942
943 if (!(graphic_width == 1024 && graphic_height == 768)) {
944 error_report("Unsupported resolution: %d x %d",
945 graphic_width, graphic_height);
946 exit(1);
947 }
948
949 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
950 graphic_width, graphic_height, graphic_depth);
951 }
952 }
953
954 for (i = num_vsimms; i < MAX_VSIMMS; i++) {
955 /* vsimm registers probed by OBP */
956 if (hwdef->vsimm[i].reg_base) {
957 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
958 }
959 }
960
961 if (hwdef->sx_base) {
962 empty_slot_init(hwdef->sx_base, 0x2000);
963 }
964
965 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
966
967 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8);
968
969 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
970
971 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
972 !machine->enable_graphics, ESCC_CLOCK, 1);
973 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
974 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
975 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
976 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
977
978 if (hwdef->apc_base) {
979 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0));
980 }
981
982 if (hwdef->fd_base) {
983 /* there is zero or one floppy drive */
984 memset(fd, 0, sizeof(fd));
985 fd[0] = drive_get(IF_FLOPPY, 0, 0);
986 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
987 &fdc_tc);
988 } else {
989 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0);
990 }
991
992 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
993 slavio_irq[30], fdc_tc);
994
995 esp_init(hwdef->esp_base, 2,
996 espdma_memory_read, espdma_memory_write,
997 espdma, espdma_irq, &esp_reset, &dma_enable);
998
999 qdev_connect_gpio_out(espdma, 0, esp_reset);
1000 qdev_connect_gpio_out(espdma, 1, dma_enable);
1001
1002 if (hwdef->cs_base) {
1003 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
1004 slavio_irq[5]);
1005 }
1006
1007 if (hwdef->dbri_base) {
1008 /* ISDN chip with attached CS4215 audio codec */
1009 /* prom space */
1010 empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
1011 /* reg space */
1012 empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
1013 }
1014
1015 if (hwdef->bpp_base) {
1016 /* parallel port */
1017 empty_slot_init(hwdef->bpp_base, 0x20);
1018 }
1019
1020 kernel_size = sun4m_load_kernel(machine->kernel_filename,
1021 machine->initrd_filename,
1022 machine->ram_size);
1023
1024 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline,
1025 machine->boot_order, machine->ram_size, kernel_size,
1026 graphic_width, graphic_height, graphic_depth,
1027 hwdef->nvram_machine_id, "Sun4m");
1028
1029 if (hwdef->ecc_base)
1030 ecc_init(hwdef->ecc_base, slavio_irq[28],
1031 hwdef->ecc_version);
1032
1033 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);
1034 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
1035 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1036 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1037 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1038 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1039 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width);
1040 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height);
1041 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1042 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1043 if (machine->kernel_cmdline) {
1044 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1045 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
1046 machine->kernel_cmdline);
1047 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
1048 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1049 strlen(machine->kernel_cmdline) + 1);
1050 } else {
1051 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1052 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1053 }
1054 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1055 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1056 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
1057 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1058 }
1059
1060 enum {
1061 ss5_id = 32,
1062 vger_id,
1063 lx_id,
1064 ss4_id,
1065 scls_id,
1066 sbook_id,
1067 ss10_id = 64,
1068 ss20_id,
1069 ss600mp_id,
1070 };
1071
1072 static const struct sun4m_hwdef sun4m_hwdefs[] = {
1073 /* SS-5 */
1074 {
1075 .iommu_base = 0x10000000,
1076 .iommu_pad_base = 0x10004000,
1077 .iommu_pad_len = 0x0fffb000,
1078 .tcx_base = 0x50000000,
1079 .cs_base = 0x6c000000,
1080 .slavio_base = 0x70000000,
1081 .ms_kb_base = 0x71000000,
1082 .serial_base = 0x71100000,
1083 .nvram_base = 0x71200000,
1084 .fd_base = 0x71400000,
1085 .counter_base = 0x71d00000,
1086 .intctl_base = 0x71e00000,
1087 .idreg_base = 0x78000000,
1088 .dma_base = 0x78400000,
1089 .esp_base = 0x78800000,
1090 .le_base = 0x78c00000,
1091 .apc_base = 0x6a000000,
1092 .afx_base = 0x6e000000,
1093 .aux1_base = 0x71900000,
1094 .aux2_base = 0x71910000,
1095 .nvram_machine_id = 0x80,
1096 .machine_id = ss5_id,
1097 .iommu_version = 0x05000000,
1098 .max_mem = 0x10000000,
1099 .default_cpu_model = "Fujitsu MB86904",
1100 },
1101 /* SS-10 */
1102 {
1103 .iommu_base = 0xfe0000000ULL,
1104 .tcx_base = 0xe20000000ULL,
1105 .slavio_base = 0xff0000000ULL,
1106 .ms_kb_base = 0xff1000000ULL,
1107 .serial_base = 0xff1100000ULL,
1108 .nvram_base = 0xff1200000ULL,
1109 .fd_base = 0xff1700000ULL,
1110 .counter_base = 0xff1300000ULL,
1111 .intctl_base = 0xff1400000ULL,
1112 .idreg_base = 0xef0000000ULL,
1113 .dma_base = 0xef0400000ULL,
1114 .esp_base = 0xef0800000ULL,
1115 .le_base = 0xef0c00000ULL,
1116 .apc_base = 0xefa000000ULL, // XXX should not exist
1117 .aux1_base = 0xff1800000ULL,
1118 .aux2_base = 0xff1a01000ULL,
1119 .ecc_base = 0xf00000000ULL,
1120 .ecc_version = 0x10000000, // version 0, implementation 1
1121 .nvram_machine_id = 0x72,
1122 .machine_id = ss10_id,
1123 .iommu_version = 0x03000000,
1124 .max_mem = 0xf00000000ULL,
1125 .default_cpu_model = "TI SuperSparc II",
1126 },
1127 /* SS-600MP */
1128 {
1129 .iommu_base = 0xfe0000000ULL,
1130 .tcx_base = 0xe20000000ULL,
1131 .slavio_base = 0xff0000000ULL,
1132 .ms_kb_base = 0xff1000000ULL,
1133 .serial_base = 0xff1100000ULL,
1134 .nvram_base = 0xff1200000ULL,
1135 .counter_base = 0xff1300000ULL,
1136 .intctl_base = 0xff1400000ULL,
1137 .dma_base = 0xef0081000ULL,
1138 .esp_base = 0xef0080000ULL,
1139 .le_base = 0xef0060000ULL,
1140 .apc_base = 0xefa000000ULL, // XXX should not exist
1141 .aux1_base = 0xff1800000ULL,
1142 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1143 .ecc_base = 0xf00000000ULL,
1144 .ecc_version = 0x00000000, // version 0, implementation 0
1145 .nvram_machine_id = 0x71,
1146 .machine_id = ss600mp_id,
1147 .iommu_version = 0x01000000,
1148 .max_mem = 0xf00000000ULL,
1149 .default_cpu_model = "TI SuperSparc II",
1150 },
1151 /* SS-20 */
1152 {
1153 .iommu_base = 0xfe0000000ULL,
1154 .tcx_base = 0xe20000000ULL,
1155 .slavio_base = 0xff0000000ULL,
1156 .ms_kb_base = 0xff1000000ULL,
1157 .serial_base = 0xff1100000ULL,
1158 .nvram_base = 0xff1200000ULL,
1159 .fd_base = 0xff1700000ULL,
1160 .counter_base = 0xff1300000ULL,
1161 .intctl_base = 0xff1400000ULL,
1162 .idreg_base = 0xef0000000ULL,
1163 .dma_base = 0xef0400000ULL,
1164 .esp_base = 0xef0800000ULL,
1165 .le_base = 0xef0c00000ULL,
1166 .bpp_base = 0xef4800000ULL,
1167 .apc_base = 0xefa000000ULL, // XXX should not exist
1168 .aux1_base = 0xff1800000ULL,
1169 .aux2_base = 0xff1a01000ULL,
1170 .dbri_base = 0xee0000000ULL,
1171 .sx_base = 0xf80000000ULL,
1172 .vsimm = {
1173 {
1174 .reg_base = 0x9c000000ULL,
1175 .vram_base = 0xfc000000ULL
1176 }, {
1177 .reg_base = 0x90000000ULL,
1178 .vram_base = 0xf0000000ULL
1179 }, {
1180 .reg_base = 0x94000000ULL
1181 }, {
1182 .reg_base = 0x98000000ULL
1183 }
1184 },
1185 .ecc_base = 0xf00000000ULL,
1186 .ecc_version = 0x20000000, // version 0, implementation 2
1187 .nvram_machine_id = 0x72,
1188 .machine_id = ss20_id,
1189 .iommu_version = 0x13000000,
1190 .max_mem = 0xf00000000ULL,
1191 .default_cpu_model = "TI SuperSparc II",
1192 },
1193 /* Voyager */
1194 {
1195 .iommu_base = 0x10000000,
1196 .tcx_base = 0x50000000,
1197 .slavio_base = 0x70000000,
1198 .ms_kb_base = 0x71000000,
1199 .serial_base = 0x71100000,
1200 .nvram_base = 0x71200000,
1201 .fd_base = 0x71400000,
1202 .counter_base = 0x71d00000,
1203 .intctl_base = 0x71e00000,
1204 .idreg_base = 0x78000000,
1205 .dma_base = 0x78400000,
1206 .esp_base = 0x78800000,
1207 .le_base = 0x78c00000,
1208 .apc_base = 0x71300000, // pmc
1209 .aux1_base = 0x71900000,
1210 .aux2_base = 0x71910000,
1211 .nvram_machine_id = 0x80,
1212 .machine_id = vger_id,
1213 .iommu_version = 0x05000000,
1214 .max_mem = 0x10000000,
1215 .default_cpu_model = "Fujitsu MB86904",
1216 },
1217 /* LX */
1218 {
1219 .iommu_base = 0x10000000,
1220 .iommu_pad_base = 0x10004000,
1221 .iommu_pad_len = 0x0fffb000,
1222 .tcx_base = 0x50000000,
1223 .slavio_base = 0x70000000,
1224 .ms_kb_base = 0x71000000,
1225 .serial_base = 0x71100000,
1226 .nvram_base = 0x71200000,
1227 .fd_base = 0x71400000,
1228 .counter_base = 0x71d00000,
1229 .intctl_base = 0x71e00000,
1230 .idreg_base = 0x78000000,
1231 .dma_base = 0x78400000,
1232 .esp_base = 0x78800000,
1233 .le_base = 0x78c00000,
1234 .aux1_base = 0x71900000,
1235 .aux2_base = 0x71910000,
1236 .nvram_machine_id = 0x80,
1237 .machine_id = lx_id,
1238 .iommu_version = 0x04000000,
1239 .max_mem = 0x10000000,
1240 .default_cpu_model = "TI MicroSparc I",
1241 },
1242 /* SS-4 */
1243 {
1244 .iommu_base = 0x10000000,
1245 .tcx_base = 0x50000000,
1246 .cs_base = 0x6c000000,
1247 .slavio_base = 0x70000000,
1248 .ms_kb_base = 0x71000000,
1249 .serial_base = 0x71100000,
1250 .nvram_base = 0x71200000,
1251 .fd_base = 0x71400000,
1252 .counter_base = 0x71d00000,
1253 .intctl_base = 0x71e00000,
1254 .idreg_base = 0x78000000,
1255 .dma_base = 0x78400000,
1256 .esp_base = 0x78800000,
1257 .le_base = 0x78c00000,
1258 .apc_base = 0x6a000000,
1259 .aux1_base = 0x71900000,
1260 .aux2_base = 0x71910000,
1261 .nvram_machine_id = 0x80,
1262 .machine_id = ss4_id,
1263 .iommu_version = 0x05000000,
1264 .max_mem = 0x10000000,
1265 .default_cpu_model = "Fujitsu MB86904",
1266 },
1267 /* SPARCClassic */
1268 {
1269 .iommu_base = 0x10000000,
1270 .tcx_base = 0x50000000,
1271 .slavio_base = 0x70000000,
1272 .ms_kb_base = 0x71000000,
1273 .serial_base = 0x71100000,
1274 .nvram_base = 0x71200000,
1275 .fd_base = 0x71400000,
1276 .counter_base = 0x71d00000,
1277 .intctl_base = 0x71e00000,
1278 .idreg_base = 0x78000000,
1279 .dma_base = 0x78400000,
1280 .esp_base = 0x78800000,
1281 .le_base = 0x78c00000,
1282 .apc_base = 0x6a000000,
1283 .aux1_base = 0x71900000,
1284 .aux2_base = 0x71910000,
1285 .nvram_machine_id = 0x80,
1286 .machine_id = scls_id,
1287 .iommu_version = 0x05000000,
1288 .max_mem = 0x10000000,
1289 .default_cpu_model = "TI MicroSparc I",
1290 },
1291 /* SPARCbook */
1292 {
1293 .iommu_base = 0x10000000,
1294 .tcx_base = 0x50000000, // XXX
1295 .slavio_base = 0x70000000,
1296 .ms_kb_base = 0x71000000,
1297 .serial_base = 0x71100000,
1298 .nvram_base = 0x71200000,
1299 .fd_base = 0x71400000,
1300 .counter_base = 0x71d00000,
1301 .intctl_base = 0x71e00000,
1302 .idreg_base = 0x78000000,
1303 .dma_base = 0x78400000,
1304 .esp_base = 0x78800000,
1305 .le_base = 0x78c00000,
1306 .apc_base = 0x6a000000,
1307 .aux1_base = 0x71900000,
1308 .aux2_base = 0x71910000,
1309 .nvram_machine_id = 0x80,
1310 .machine_id = sbook_id,
1311 .iommu_version = 0x05000000,
1312 .max_mem = 0x10000000,
1313 .default_cpu_model = "TI MicroSparc I",
1314 },
1315 };
1316
1317 /* SPARCstation 5 hardware initialisation */
1318 static void ss5_init(MachineState *machine)
1319 {
1320 sun4m_hw_init(&sun4m_hwdefs[0], machine);
1321 }
1322
1323 /* SPARCstation 10 hardware initialisation */
1324 static void ss10_init(MachineState *machine)
1325 {
1326 sun4m_hw_init(&sun4m_hwdefs[1], machine);
1327 }
1328
1329 /* SPARCserver 600MP hardware initialisation */
1330 static void ss600mp_init(MachineState *machine)
1331 {
1332 sun4m_hw_init(&sun4m_hwdefs[2], machine);
1333 }
1334
1335 /* SPARCstation 20 hardware initialisation */
1336 static void ss20_init(MachineState *machine)
1337 {
1338 sun4m_hw_init(&sun4m_hwdefs[3], machine);
1339 }
1340
1341 /* SPARCstation Voyager hardware initialisation */
1342 static void vger_init(MachineState *machine)
1343 {
1344 sun4m_hw_init(&sun4m_hwdefs[4], machine);
1345 }
1346
1347 /* SPARCstation LX hardware initialisation */
1348 static void ss_lx_init(MachineState *machine)
1349 {
1350 sun4m_hw_init(&sun4m_hwdefs[5], machine);
1351 }
1352
1353 /* SPARCstation 4 hardware initialisation */
1354 static void ss4_init(MachineState *machine)
1355 {
1356 sun4m_hw_init(&sun4m_hwdefs[6], machine);
1357 }
1358
1359 /* SPARCClassic hardware initialisation */
1360 static void scls_init(MachineState *machine)
1361 {
1362 sun4m_hw_init(&sun4m_hwdefs[7], machine);
1363 }
1364
1365 /* SPARCbook hardware initialisation */
1366 static void sbook_init(MachineState *machine)
1367 {
1368 sun4m_hw_init(&sun4m_hwdefs[8], machine);
1369 }
1370
1371 static void ss5_class_init(ObjectClass *oc, void *data)
1372 {
1373 MachineClass *mc = MACHINE_CLASS(oc);
1374
1375 mc->desc = "Sun4m platform, SPARCstation 5";
1376 mc->init = ss5_init;
1377 mc->block_default_type = IF_SCSI;
1378 mc->is_default = 1;
1379 mc->default_boot_order = "c";
1380 }
1381
1382 static const TypeInfo ss5_type = {
1383 .name = MACHINE_TYPE_NAME("SS-5"),
1384 .parent = TYPE_MACHINE,
1385 .class_init = ss5_class_init,
1386 };
1387
1388 static void ss10_class_init(ObjectClass *oc, void *data)
1389 {
1390 MachineClass *mc = MACHINE_CLASS(oc);
1391
1392 mc->desc = "Sun4m platform, SPARCstation 10";
1393 mc->init = ss10_init;
1394 mc->block_default_type = IF_SCSI;
1395 mc->max_cpus = 4;
1396 mc->default_boot_order = "c";
1397 }
1398
1399 static const TypeInfo ss10_type = {
1400 .name = MACHINE_TYPE_NAME("SS-10"),
1401 .parent = TYPE_MACHINE,
1402 .class_init = ss10_class_init,
1403 };
1404
1405 static void ss600mp_class_init(ObjectClass *oc, void *data)
1406 {
1407 MachineClass *mc = MACHINE_CLASS(oc);
1408
1409 mc->desc = "Sun4m platform, SPARCserver 600MP";
1410 mc->init = ss600mp_init;
1411 mc->block_default_type = IF_SCSI;
1412 mc->max_cpus = 4;
1413 mc->default_boot_order = "c";
1414 }
1415
1416 static const TypeInfo ss600mp_type = {
1417 .name = MACHINE_TYPE_NAME("SS-600MP"),
1418 .parent = TYPE_MACHINE,
1419 .class_init = ss600mp_class_init,
1420 };
1421
1422 static void ss20_class_init(ObjectClass *oc, void *data)
1423 {
1424 MachineClass *mc = MACHINE_CLASS(oc);
1425
1426 mc->desc = "Sun4m platform, SPARCstation 20";
1427 mc->init = ss20_init;
1428 mc->block_default_type = IF_SCSI;
1429 mc->max_cpus = 4;
1430 mc->default_boot_order = "c";
1431 }
1432
1433 static const TypeInfo ss20_type = {
1434 .name = MACHINE_TYPE_NAME("SS-20"),
1435 .parent = TYPE_MACHINE,
1436 .class_init = ss20_class_init,
1437 };
1438
1439 static void voyager_class_init(ObjectClass *oc, void *data)
1440 {
1441 MachineClass *mc = MACHINE_CLASS(oc);
1442
1443 mc->desc = "Sun4m platform, SPARCstation Voyager";
1444 mc->init = vger_init;
1445 mc->block_default_type = IF_SCSI;
1446 mc->default_boot_order = "c";
1447 }
1448
1449 static const TypeInfo voyager_type = {
1450 .name = MACHINE_TYPE_NAME("Voyager"),
1451 .parent = TYPE_MACHINE,
1452 .class_init = voyager_class_init,
1453 };
1454
1455 static void ss_lx_class_init(ObjectClass *oc, void *data)
1456 {
1457 MachineClass *mc = MACHINE_CLASS(oc);
1458
1459 mc->desc = "Sun4m platform, SPARCstation LX";
1460 mc->init = ss_lx_init;
1461 mc->block_default_type = IF_SCSI;
1462 mc->default_boot_order = "c";
1463 }
1464
1465 static const TypeInfo ss_lx_type = {
1466 .name = MACHINE_TYPE_NAME("LX"),
1467 .parent = TYPE_MACHINE,
1468 .class_init = ss_lx_class_init,
1469 };
1470
1471 static void ss4_class_init(ObjectClass *oc, void *data)
1472 {
1473 MachineClass *mc = MACHINE_CLASS(oc);
1474
1475 mc->desc = "Sun4m platform, SPARCstation 4";
1476 mc->init = ss4_init;
1477 mc->block_default_type = IF_SCSI;
1478 mc->default_boot_order = "c";
1479 }
1480
1481 static const TypeInfo ss4_type = {
1482 .name = MACHINE_TYPE_NAME("SS-4"),
1483 .parent = TYPE_MACHINE,
1484 .class_init = ss4_class_init,
1485 };
1486
1487 static void scls_class_init(ObjectClass *oc, void *data)
1488 {
1489 MachineClass *mc = MACHINE_CLASS(oc);
1490
1491 mc->desc = "Sun4m platform, SPARCClassic";
1492 mc->init = scls_init;
1493 mc->block_default_type = IF_SCSI;
1494 mc->default_boot_order = "c";
1495 }
1496
1497 static const TypeInfo scls_type = {
1498 .name = MACHINE_TYPE_NAME("SPARCClassic"),
1499 .parent = TYPE_MACHINE,
1500 .class_init = scls_class_init,
1501 };
1502
1503 static void sbook_class_init(ObjectClass *oc, void *data)
1504 {
1505 MachineClass *mc = MACHINE_CLASS(oc);
1506
1507 mc->desc = "Sun4m platform, SPARCbook";
1508 mc->init = sbook_init;
1509 mc->block_default_type = IF_SCSI;
1510 mc->default_boot_order = "c";
1511 }
1512
1513 static const TypeInfo sbook_type = {
1514 .name = MACHINE_TYPE_NAME("SPARCbook"),
1515 .parent = TYPE_MACHINE,
1516 .class_init = sbook_class_init,
1517 };
1518
1519 static void sun4m_register_types(void)
1520 {
1521 type_register_static(&idreg_info);
1522 type_register_static(&afx_info);
1523 type_register_static(&prom_info);
1524 type_register_static(&ram_info);
1525
1526 type_register_static(&ss5_type);
1527 type_register_static(&ss10_type);
1528 type_register_static(&ss600mp_type);
1529 type_register_static(&ss20_type);
1530 type_register_static(&voyager_type);
1531 type_register_static(&ss_lx_type);
1532 type_register_static(&ss4_type);
1533 type_register_static(&scls_type);
1534 type_register_static(&sbook_type);
1535 }
1536
1537 type_init(sun4m_register_types)
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