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qxl: fix > 80 chars line
[qemu/kevin.git] / hw / qxl.c
blobb22f86e634e6fbb742bd64b500aa2074daf9f409
1 /*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <kraxel@redhat.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu-common.h"
22 #include "qemu-timer.h"
23 #include "qemu-queue.h"
24 #include "monitor.h"
25 #include "sysemu.h"
26 #include "trace.h"
27
28 #include "qxl.h"
29
30 #undef SPICE_RING_PROD_ITEM
31 #define SPICE_RING_PROD_ITEM(r, ret) { \
32 typeof(r) start = r; \
33 typeof(r) end = r + 1; \
34 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
35 typeof(&(r)->items[prod]) m_item = &(r)->items[prod]; \
36 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
37 abort(); \
38 } \
39 ret = &m_item->el; \
40 }
41
42 #undef SPICE_RING_CONS_ITEM
43 #define SPICE_RING_CONS_ITEM(r, ret) { \
44 typeof(r) start = r; \
45 typeof(r) end = r + 1; \
46 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
47 typeof(&(r)->items[cons]) m_item = &(r)->items[cons]; \
48 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
49 abort(); \
50 } \
51 ret = &m_item->el; \
52 }
53
54 #undef ALIGN
55 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
56
57 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
58
59 #define QXL_MODE(_x, _y, _b, _o) \
60 { .x_res = _x, \
61 .y_res = _y, \
62 .bits = _b, \
63 .stride = (_x) * (_b) / 8, \
64 .x_mili = PIXEL_SIZE * (_x), \
65 .y_mili = PIXEL_SIZE * (_y), \
66 .orientation = _o, \
67 }
68
69 #define QXL_MODE_16_32(x_res, y_res, orientation) \
70 QXL_MODE(x_res, y_res, 16, orientation), \
71 QXL_MODE(x_res, y_res, 32, orientation)
72
73 #define QXL_MODE_EX(x_res, y_res) \
74 QXL_MODE_16_32(x_res, y_res, 0), \
75 QXL_MODE_16_32(y_res, x_res, 1), \
76 QXL_MODE_16_32(x_res, y_res, 2), \
77 QXL_MODE_16_32(y_res, x_res, 3)
78
79 static QXLMode qxl_modes[] = {
80 QXL_MODE_EX(640, 480),
81 QXL_MODE_EX(800, 480),
82 QXL_MODE_EX(800, 600),
83 QXL_MODE_EX(832, 624),
84 QXL_MODE_EX(960, 640),
85 QXL_MODE_EX(1024, 600),
86 QXL_MODE_EX(1024, 768),
87 QXL_MODE_EX(1152, 864),
88 QXL_MODE_EX(1152, 870),
89 QXL_MODE_EX(1280, 720),
90 QXL_MODE_EX(1280, 760),
91 QXL_MODE_EX(1280, 768),
92 QXL_MODE_EX(1280, 800),
93 QXL_MODE_EX(1280, 960),
94 QXL_MODE_EX(1280, 1024),
95 QXL_MODE_EX(1360, 768),
96 QXL_MODE_EX(1366, 768),
97 QXL_MODE_EX(1400, 1050),
98 QXL_MODE_EX(1440, 900),
99 QXL_MODE_EX(1600, 900),
100 QXL_MODE_EX(1600, 1200),
101 QXL_MODE_EX(1680, 1050),
102 QXL_MODE_EX(1920, 1080),
103 #if VGA_RAM_SIZE >= (16 * 1024 * 1024)
104 /* these modes need more than 8 MB video memory */
105 QXL_MODE_EX(1920, 1200),
106 QXL_MODE_EX(1920, 1440),
107 QXL_MODE_EX(2048, 1536),
108 QXL_MODE_EX(2560, 1440),
109 QXL_MODE_EX(2560, 1600),
110 #endif
111 #if VGA_RAM_SIZE >= (32 * 1024 * 1024)
112 /* these modes need more than 16 MB video memory */
113 QXL_MODE_EX(2560, 2048),
114 QXL_MODE_EX(2800, 2100),
115 QXL_MODE_EX(3200, 2400),
116 #endif
117 };
118
119 static PCIQXLDevice *qxl0;
120
121 static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
122 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async);
123 static void qxl_reset_memslots(PCIQXLDevice *d);
124 static void qxl_reset_surfaces(PCIQXLDevice *d);
125 static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
126
127 void qxl_guest_bug(PCIQXLDevice *qxl, const char *msg, ...)
128 {
129 qxl_send_events(qxl, QXL_INTERRUPT_ERROR);
130 if (qxl->guestdebug) {
131 va_list ap;
132 va_start(ap, msg);
133 fprintf(stderr, "qxl-%d: guest bug: ", qxl->id);
134 vfprintf(stderr, msg, ap);
135 fprintf(stderr, "\n");
136 va_end(ap);
137 }
138 }
139
140
141 void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
142 struct QXLRect *area, struct QXLRect *dirty_rects,
143 uint32_t num_dirty_rects,
144 uint32_t clear_dirty_region,
145 qxl_async_io async, struct QXLCookie *cookie)
146 {
147 trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right,
148 area->top, area->bottom);
149 trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects,
150 clear_dirty_region);
151 if (async == QXL_SYNC) {
152 qxl->ssd.worker->update_area(qxl->ssd.worker, surface_id, area,
153 dirty_rects, num_dirty_rects, clear_dirty_region);
154 } else {
155 assert(cookie != NULL);
156 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area,
157 clear_dirty_region, (uintptr_t)cookie);
158 }
159 }
160
161 static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl,
162 uint32_t id)
163 {
164 trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id);
165 qemu_mutex_lock(&qxl->track_lock);
166 qxl->guest_surfaces.cmds[id] = 0;
167 qxl->guest_surfaces.count--;
168 qemu_mutex_unlock(&qxl->track_lock);
169 }
170
171 static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id,
172 qxl_async_io async)
173 {
174 QXLCookie *cookie;
175
176 trace_qxl_spice_destroy_surface_wait(qxl->id, id, async);
177 if (async) {
178 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
179 QXL_IO_DESTROY_SURFACE_ASYNC);
180 cookie->u.surface_id = id;
181 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie);
182 } else {
183 qxl->ssd.worker->destroy_surface_wait(qxl->ssd.worker, id);
184 }
185 }
186
187 static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl)
188 {
189 trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count,
190 qxl->num_free_res);
191 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl,
192 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
193 QXL_IO_FLUSH_SURFACES_ASYNC));
194 }
195
196 void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext,
197 uint32_t count)
198 {
199 trace_qxl_spice_loadvm_commands(qxl->id, ext, count);
200 qxl->ssd.worker->loadvm_commands(qxl->ssd.worker, ext, count);
201 }
202
203 void qxl_spice_oom(PCIQXLDevice *qxl)
204 {
205 trace_qxl_spice_oom(qxl->id);
206 qxl->ssd.worker->oom(qxl->ssd.worker);
207 }
208
209 void qxl_spice_reset_memslots(PCIQXLDevice *qxl)
210 {
211 trace_qxl_spice_reset_memslots(qxl->id);
212 qxl->ssd.worker->reset_memslots(qxl->ssd.worker);
213 }
214
215 static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl)
216 {
217 trace_qxl_spice_destroy_surfaces_complete(qxl->id);
218 qemu_mutex_lock(&qxl->track_lock);
219 memset(&qxl->guest_surfaces.cmds, 0, sizeof(qxl->guest_surfaces.cmds));
220 qxl->guest_surfaces.count = 0;
221 qemu_mutex_unlock(&qxl->track_lock);
222 }
223
224 static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async)
225 {
226 trace_qxl_spice_destroy_surfaces(qxl->id, async);
227 if (async) {
228 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl,
229 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
230 QXL_IO_DESTROY_ALL_SURFACES_ASYNC));
231 } else {
232 qxl->ssd.worker->destroy_surfaces(qxl->ssd.worker);
233 qxl_spice_destroy_surfaces_complete(qxl);
234 }
235 }
236
237 void qxl_spice_reset_image_cache(PCIQXLDevice *qxl)
238 {
239 trace_qxl_spice_reset_image_cache(qxl->id);
240 qxl->ssd.worker->reset_image_cache(qxl->ssd.worker);
241 }
242
243 void qxl_spice_reset_cursor(PCIQXLDevice *qxl)
244 {
245 trace_qxl_spice_reset_cursor(qxl->id);
246 qxl->ssd.worker->reset_cursor(qxl->ssd.worker);
247 qemu_mutex_lock(&qxl->track_lock);
248 qxl->guest_cursor = 0;
249 qemu_mutex_unlock(&qxl->track_lock);
250 }
251
252
253 static inline uint32_t msb_mask(uint32_t val)
254 {
255 uint32_t mask;
256
257 do {
258 mask = ~(val - 1) & val;
259 val &= ~mask;
260 } while (mask < val);
261
262 return mask;
263 }
264
265 static ram_addr_t qxl_rom_size(void)
266 {
267 uint32_t rom_size = sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes);
268 rom_size = MAX(rom_size, TARGET_PAGE_SIZE);
269 rom_size = msb_mask(rom_size * 2 - 1);
270 return rom_size;
271 }
272
273 static void init_qxl_rom(PCIQXLDevice *d)
274 {
275 QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar);
276 QXLModes *modes = (QXLModes *)(rom + 1);
277 uint32_t ram_header_size;
278 uint32_t surface0_area_size;
279 uint32_t num_pages;
280 uint32_t fb, maxfb = 0;
281 int i;
282
283 memset(rom, 0, d->rom_size);
284
285 rom->magic = cpu_to_le32(QXL_ROM_MAGIC);
286 rom->id = cpu_to_le32(d->id);
287 rom->log_level = cpu_to_le32(d->guestdebug);
288 rom->modes_offset = cpu_to_le32(sizeof(QXLRom));
289
290 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS;
291 rom->slot_id_bits = MEMSLOT_SLOT_BITS;
292 rom->slots_start = 1;
293 rom->slots_end = NUM_MEMSLOTS - 1;
294 rom->n_surfaces = cpu_to_le32(NUM_SURFACES);
295
296 modes->n_modes = cpu_to_le32(ARRAY_SIZE(qxl_modes));
297 for (i = 0; i < modes->n_modes; i++) {
298 fb = qxl_modes[i].y_res * qxl_modes[i].stride;
299 if (maxfb < fb) {
300 maxfb = fb;
301 }
302 modes->modes[i].id = cpu_to_le32(i);
303 modes->modes[i].x_res = cpu_to_le32(qxl_modes[i].x_res);
304 modes->modes[i].y_res = cpu_to_le32(qxl_modes[i].y_res);
305 modes->modes[i].bits = cpu_to_le32(qxl_modes[i].bits);
306 modes->modes[i].stride = cpu_to_le32(qxl_modes[i].stride);
307 modes->modes[i].x_mili = cpu_to_le32(qxl_modes[i].x_mili);
308 modes->modes[i].y_mili = cpu_to_le32(qxl_modes[i].y_mili);
309 modes->modes[i].orientation = cpu_to_le32(qxl_modes[i].orientation);
310 }
311 if (maxfb < VGA_RAM_SIZE && d->id == 0)
312 maxfb = VGA_RAM_SIZE;
313
314 ram_header_size = ALIGN(sizeof(QXLRam), 4096);
315 surface0_area_size = ALIGN(maxfb, 4096);
316 num_pages = d->vga.vram_size;
317 num_pages -= ram_header_size;
318 num_pages -= surface0_area_size;
319 num_pages = num_pages / TARGET_PAGE_SIZE;
320
321 rom->draw_area_offset = cpu_to_le32(0);
322 rom->surface0_area_size = cpu_to_le32(surface0_area_size);
323 rom->pages_offset = cpu_to_le32(surface0_area_size);
324 rom->num_pages = cpu_to_le32(num_pages);
325 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size);
326
327 d->shadow_rom = *rom;
328 d->rom = rom;
329 d->modes = modes;
330 }
331
332 static void init_qxl_ram(PCIQXLDevice *d)
333 {
334 uint8_t *buf;
335 uint64_t *item;
336
337 buf = d->vga.vram_ptr;
338 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
339 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC);
340 d->ram->int_pending = cpu_to_le32(0);
341 d->ram->int_mask = cpu_to_le32(0);
342 d->ram->update_surface = 0;
343 SPICE_RING_INIT(&d->ram->cmd_ring);
344 SPICE_RING_INIT(&d->ram->cursor_ring);
345 SPICE_RING_INIT(&d->ram->release_ring);
346 SPICE_RING_PROD_ITEM(&d->ram->release_ring, item);
347 *item = 0;
348 qxl_ring_set_dirty(d);
349 }
350
351 /* can be called from spice server thread context */
352 static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end)
353 {
354 memory_region_set_dirty(mr, addr, end - addr);
355 }
356
357 static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
358 {
359 qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size);
360 }
361
362 /* called from spice server thread context only */
363 static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
364 {
365 void *base = qxl->vga.vram_ptr;
366 intptr_t offset;
367
368 offset = ptr - base;
369 offset &= ~(TARGET_PAGE_SIZE-1);
370 assert(offset < qxl->vga.vram_size);
371 qxl_set_dirty(&qxl->vga.vram, offset, offset + TARGET_PAGE_SIZE);
372 }
373
374 /* can be called from spice server thread context */
375 static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
376 {
377 ram_addr_t addr = qxl->shadow_rom.ram_header_offset;
378 ram_addr_t end = qxl->vga.vram_size;
379 qxl_set_dirty(&qxl->vga.vram, addr, end);
380 }
381
382 /*
383 * keep track of some command state, for savevm/loadvm.
384 * called from spice server thread context only
385 */
386 static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
387 {
388 switch (le32_to_cpu(ext->cmd.type)) {
389 case QXL_CMD_SURFACE:
390 {
391 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
392
393 if (!cmd) {
394 return 1;
395 }
396 uint32_t id = le32_to_cpu(cmd->surface_id);
397
398 if (id >= NUM_SURFACES) {
399 qxl_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id, NUM_SURFACES);
400 return 1;
401 }
402 qemu_mutex_lock(&qxl->track_lock);
403 if (cmd->type == QXL_SURFACE_CMD_CREATE) {
404 qxl->guest_surfaces.cmds[id] = ext->cmd.data;
405 qxl->guest_surfaces.count++;
406 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count)
407 qxl->guest_surfaces.max = qxl->guest_surfaces.count;
408 }
409 if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
410 qxl->guest_surfaces.cmds[id] = 0;
411 qxl->guest_surfaces.count--;
412 }
413 qemu_mutex_unlock(&qxl->track_lock);
414 break;
415 }
416 case QXL_CMD_CURSOR:
417 {
418 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
419
420 if (!cmd) {
421 return 1;
422 }
423 if (cmd->type == QXL_CURSOR_SET) {
424 qemu_mutex_lock(&qxl->track_lock);
425 qxl->guest_cursor = ext->cmd.data;
426 qemu_mutex_unlock(&qxl->track_lock);
427 }
428 break;
429 }
430 }
431 return 0;
432 }
433
434 /* spice display interface callbacks */
435
436 static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
437 {
438 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
439
440 trace_qxl_interface_attach_worker(qxl->id);
441 qxl->ssd.worker = qxl_worker;
442 }
443
444 static void interface_set_compression_level(QXLInstance *sin, int level)
445 {
446 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
447
448 trace_qxl_interface_set_compression_level(qxl->id, level);
449 qxl->shadow_rom.compression_level = cpu_to_le32(level);
450 qxl->rom->compression_level = cpu_to_le32(level);
451 qxl_rom_set_dirty(qxl);
452 }
453
454 static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
455 {
456 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
457
458 trace_qxl_interface_set_mm_time(qxl->id, mm_time);
459 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time);
460 qxl->rom->mm_clock = cpu_to_le32(mm_time);
461 qxl_rom_set_dirty(qxl);
462 }
463
464 static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
465 {
466 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
467
468 trace_qxl_interface_get_init_info(qxl->id);
469 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS;
470 info->memslot_id_bits = MEMSLOT_SLOT_BITS;
471 info->num_memslots = NUM_MEMSLOTS;
472 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS;
473 info->internal_groupslot_id = 0;
474 info->qxl_ram_size = le32_to_cpu(qxl->shadow_rom.num_pages) << TARGET_PAGE_BITS;
475 info->n_surfaces = NUM_SURFACES;
476 }
477
478 static const char *qxl_mode_to_string(int mode)
479 {
480 switch (mode) {
481 case QXL_MODE_COMPAT:
482 return "compat";
483 case QXL_MODE_NATIVE:
484 return "native";
485 case QXL_MODE_UNDEFINED:
486 return "undefined";
487 case QXL_MODE_VGA:
488 return "vga";
489 }
490 return "INVALID";
491 }
492
493 static const char *io_port_to_string(uint32_t io_port)
494 {
495 if (io_port >= QXL_IO_RANGE_SIZE) {
496 return "out of range";
497 }
498 static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = {
499 [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD",
500 [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR",
501 [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA",
502 [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ",
503 [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM",
504 [QXL_IO_RESET] = "QXL_IO_RESET",
505 [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE",
506 [QXL_IO_LOG] = "QXL_IO_LOG",
507 [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD",
508 [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL",
509 [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY",
510 [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY",
511 [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY",
512 [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY",
513 [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT",
514 [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES",
515 [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC",
516 [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC",
517 [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC",
518 [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
519 [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC",
520 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC]
521 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
522 [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC",
523 [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE",
524 };
525 return io_port_to_string[io_port];
526 }
527
528 /* called from spice server thread context only */
529 static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
530 {
531 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
532 SimpleSpiceUpdate *update;
533 QXLCommandRing *ring;
534 QXLCommand *cmd;
535 int notify, ret;
536
537 trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode));
538
539 switch (qxl->mode) {
540 case QXL_MODE_VGA:
541 ret = false;
542 qemu_mutex_lock(&qxl->ssd.lock);
543 if (qxl->ssd.update != NULL) {
544 update = qxl->ssd.update;
545 qxl->ssd.update = NULL;
546 *ext = update->ext;
547 ret = true;
548 }
549 qemu_mutex_unlock(&qxl->ssd.lock);
550 if (ret) {
551 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
552 qxl_log_command(qxl, "vga", ext);
553 }
554 return ret;
555 case QXL_MODE_COMPAT:
556 case QXL_MODE_NATIVE:
557 case QXL_MODE_UNDEFINED:
558 ring = &qxl->ram->cmd_ring;
559 if (SPICE_RING_IS_EMPTY(ring)) {
560 return false;
561 }
562 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
563 SPICE_RING_CONS_ITEM(ring, cmd);
564 ext->cmd = *cmd;
565 ext->group_id = MEMSLOT_GROUP_GUEST;
566 ext->flags = qxl->cmdflags;
567 SPICE_RING_POP(ring, notify);
568 qxl_ring_set_dirty(qxl);
569 if (notify) {
570 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
571 }
572 qxl->guest_primary.commands++;
573 qxl_track_command(qxl, ext);
574 qxl_log_command(qxl, "cmd", ext);
575 return true;
576 default:
577 return false;
578 }
579 }
580
581 /* called from spice server thread context only */
582 static int interface_req_cmd_notification(QXLInstance *sin)
583 {
584 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
585 int wait = 1;
586
587 trace_qxl_ring_command_req_notification(qxl->id);
588 switch (qxl->mode) {
589 case QXL_MODE_COMPAT:
590 case QXL_MODE_NATIVE:
591 case QXL_MODE_UNDEFINED:
592 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait);
593 qxl_ring_set_dirty(qxl);
594 break;
595 default:
596 /* nothing */
597 break;
598 }
599 return wait;
600 }
601
602 /* called from spice server thread context only */
603 static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
604 {
605 QXLReleaseRing *ring = &d->ram->release_ring;
606 uint64_t *item;
607 int notify;
608
609 #define QXL_FREE_BUNCH_SIZE 32
610
611 if (ring->prod - ring->cons + 1 == ring->num_items) {
612 /* ring full -- can't push */
613 return;
614 }
615 if (!flush && d->oom_running) {
616 /* collect everything from oom handler before pushing */
617 return;
618 }
619 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
620 /* collect a bit more before pushing */
621 return;
622 }
623
624 SPICE_RING_PUSH(ring, notify);
625 trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode),
626 d->guest_surfaces.count, d->num_free_res,
627 d->last_release, notify ? "yes" : "no");
628 trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons,
629 ring->num_items, ring->prod, ring->cons);
630 if (notify) {
631 qxl_send_events(d, QXL_INTERRUPT_DISPLAY);
632 }
633 SPICE_RING_PROD_ITEM(ring, item);
634 *item = 0;
635 d->num_free_res = 0;
636 d->last_release = NULL;
637 qxl_ring_set_dirty(d);
638 }
639
640 /* called from spice server thread context only */
641 static void interface_release_resource(QXLInstance *sin,
642 struct QXLReleaseInfoExt ext)
643 {
644 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
645 QXLReleaseRing *ring;
646 uint64_t *item, id;
647
648 if (ext.group_id == MEMSLOT_GROUP_HOST) {
649 /* host group -> vga mode update request */
650 qemu_spice_destroy_update(&qxl->ssd, (void *)(intptr_t)ext.info->id);
651 return;
652 }
653
654 /*
655 * ext->info points into guest-visible memory
656 * pci bar 0, $command.release_info
657 */
658 ring = &qxl->ram->release_ring;
659 SPICE_RING_PROD_ITEM(ring, item);
660 if (*item == 0) {
661 /* stick head into the ring */
662 id = ext.info->id;
663 ext.info->next = 0;
664 qxl_ram_set_dirty(qxl, &ext.info->next);
665 *item = id;
666 qxl_ring_set_dirty(qxl);
667 } else {
668 /* append item to the list */
669 qxl->last_release->next = ext.info->id;
670 qxl_ram_set_dirty(qxl, &qxl->last_release->next);
671 ext.info->next = 0;
672 qxl_ram_set_dirty(qxl, &ext.info->next);
673 }
674 qxl->last_release = ext.info;
675 qxl->num_free_res++;
676 trace_qxl_ring_res_put(qxl->id, qxl->num_free_res);
677 qxl_push_free_res(qxl, 0);
678 }
679
680 /* called from spice server thread context only */
681 static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
682 {
683 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
684 QXLCursorRing *ring;
685 QXLCommand *cmd;
686 int notify;
687
688 trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode));
689
690 switch (qxl->mode) {
691 case QXL_MODE_COMPAT:
692 case QXL_MODE_NATIVE:
693 case QXL_MODE_UNDEFINED:
694 ring = &qxl->ram->cursor_ring;
695 if (SPICE_RING_IS_EMPTY(ring)) {
696 return false;
697 }
698 SPICE_RING_CONS_ITEM(ring, cmd);
699 ext->cmd = *cmd;
700 ext->group_id = MEMSLOT_GROUP_GUEST;
701 ext->flags = qxl->cmdflags;
702 SPICE_RING_POP(ring, notify);
703 qxl_ring_set_dirty(qxl);
704 if (notify) {
705 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR);
706 }
707 qxl->guest_primary.commands++;
708 qxl_track_command(qxl, ext);
709 qxl_log_command(qxl, "csr", ext);
710 if (qxl->id == 0) {
711 qxl_render_cursor(qxl, ext);
712 }
713 trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode));
714 return true;
715 default:
716 return false;
717 }
718 }
719
720 /* called from spice server thread context only */
721 static int interface_req_cursor_notification(QXLInstance *sin)
722 {
723 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
724 int wait = 1;
725
726 trace_qxl_ring_cursor_req_notification(qxl->id);
727 switch (qxl->mode) {
728 case QXL_MODE_COMPAT:
729 case QXL_MODE_NATIVE:
730 case QXL_MODE_UNDEFINED:
731 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait);
732 qxl_ring_set_dirty(qxl);
733 break;
734 default:
735 /* nothing */
736 break;
737 }
738 return wait;
739 }
740
741 /* called from spice server thread context */
742 static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
743 {
744 fprintf(stderr, "%s: abort()\n", __FUNCTION__);
745 abort();
746 }
747
748 /* called from spice server thread context only */
749 static int interface_flush_resources(QXLInstance *sin)
750 {
751 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
752 int ret;
753
754 ret = qxl->num_free_res;
755 if (ret) {
756 qxl_push_free_res(qxl, 1);
757 }
758 return ret;
759 }
760
761 static void qxl_create_guest_primary_complete(PCIQXLDevice *d);
762
763 /* called from spice server thread context only */
764 static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie)
765 {
766 uint32_t current_async;
767
768 qemu_mutex_lock(&qxl->async_lock);
769 current_async = qxl->current_async;
770 qxl->current_async = QXL_UNDEFINED_IO;
771 qemu_mutex_unlock(&qxl->async_lock);
772
773 trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie);
774 if (!cookie) {
775 fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__);
776 return;
777 }
778 if (cookie && current_async != cookie->io) {
779 fprintf(stderr,
780 "qxl: %s: error: current_async = %d != %"
781 PRId64 " = cookie->io\n", __func__, current_async, cookie->io);
782 }
783 switch (current_async) {
784 case QXL_IO_MEMSLOT_ADD_ASYNC:
785 case QXL_IO_DESTROY_PRIMARY_ASYNC:
786 case QXL_IO_UPDATE_AREA_ASYNC:
787 case QXL_IO_FLUSH_SURFACES_ASYNC:
788 break;
789 case QXL_IO_CREATE_PRIMARY_ASYNC:
790 qxl_create_guest_primary_complete(qxl);
791 break;
792 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
793 qxl_spice_destroy_surfaces_complete(qxl);
794 break;
795 case QXL_IO_DESTROY_SURFACE_ASYNC:
796 qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id);
797 break;
798 default:
799 fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__,
800 current_async);
801 }
802 qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD);
803 }
804
805 /* called from spice server thread context only */
806 static void interface_update_area_complete(QXLInstance *sin,
807 uint32_t surface_id,
808 QXLRect *dirty, uint32_t num_updated_rects)
809 {
810 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
811 int i;
812 int qxl_i;
813
814 qemu_mutex_lock(&qxl->ssd.lock);
815 if (surface_id != 0 || !qxl->render_update_cookie_num) {
816 qemu_mutex_unlock(&qxl->ssd.lock);
817 return;
818 }
819 trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left,
820 dirty->right, dirty->top, dirty->bottom);
821 trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects);
822 if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) {
823 /*
824 * overflow - treat this as a full update. Not expected to be common.
825 */
826 trace_qxl_interface_update_area_complete_overflow(qxl->id,
827 QXL_NUM_DIRTY_RECTS);
828 qxl->guest_primary.resized = 1;
829 }
830 if (qxl->guest_primary.resized) {
831 /*
832 * Don't bother copying or scheduling the bh since we will flip
833 * the whole area anyway on completion of the update_area async call
834 */
835 qemu_mutex_unlock(&qxl->ssd.lock);
836 return;
837 }
838 qxl_i = qxl->num_dirty_rects;
839 for (i = 0; i < num_updated_rects; i++) {
840 qxl->dirty[qxl_i++] = dirty[i];
841 }
842 qxl->num_dirty_rects += num_updated_rects;
843 trace_qxl_interface_update_area_complete_schedule_bh(qxl->id,
844 qxl->num_dirty_rects);
845 qemu_bh_schedule(qxl->update_area_bh);
846 qemu_mutex_unlock(&qxl->ssd.lock);
847 }
848
849 /* called from spice server thread context only */
850 static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token)
851 {
852 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
853 QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token;
854
855 switch (cookie->type) {
856 case QXL_COOKIE_TYPE_IO:
857 interface_async_complete_io(qxl, cookie);
858 g_free(cookie);
859 break;
860 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA:
861 qxl_render_update_area_done(qxl, cookie);
862 break;
863 default:
864 fprintf(stderr, "qxl: %s: unexpected cookie type %d\n",
865 __func__, cookie->type);
866 g_free(cookie);
867 }
868 }
869
870 static const QXLInterface qxl_interface = {
871 .base.type = SPICE_INTERFACE_QXL,
872 .base.description = "qxl gpu",
873 .base.major_version = SPICE_INTERFACE_QXL_MAJOR,
874 .base.minor_version = SPICE_INTERFACE_QXL_MINOR,
875
876 .attache_worker = interface_attach_worker,
877 .set_compression_level = interface_set_compression_level,
878 .set_mm_time = interface_set_mm_time,
879 .get_init_info = interface_get_init_info,
880
881 /* the callbacks below are called from spice server thread context */
882 .get_command = interface_get_command,
883 .req_cmd_notification = interface_req_cmd_notification,
884 .release_resource = interface_release_resource,
885 .get_cursor_command = interface_get_cursor_command,
886 .req_cursor_notification = interface_req_cursor_notification,
887 .notify_update = interface_notify_update,
888 .flush_resources = interface_flush_resources,
889 .async_complete = interface_async_complete,
890 .update_area_complete = interface_update_area_complete,
891 };
892
893 static void qxl_enter_vga_mode(PCIQXLDevice *d)
894 {
895 if (d->mode == QXL_MODE_VGA) {
896 return;
897 }
898 trace_qxl_enter_vga_mode(d->id);
899 qemu_spice_create_host_primary(&d->ssd);
900 d->mode = QXL_MODE_VGA;
901 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
902 }
903
904 static void qxl_exit_vga_mode(PCIQXLDevice *d)
905 {
906 if (d->mode != QXL_MODE_VGA) {
907 return;
908 }
909 trace_qxl_exit_vga_mode(d->id);
910 qxl_destroy_primary(d, QXL_SYNC);
911 }
912
913 static void qxl_update_irq(PCIQXLDevice *d)
914 {
915 uint32_t pending = le32_to_cpu(d->ram->int_pending);
916 uint32_t mask = le32_to_cpu(d->ram->int_mask);
917 int level = !!(pending & mask);
918 qemu_set_irq(d->pci.irq[0], level);
919 qxl_ring_set_dirty(d);
920 }
921
922 static void qxl_check_state(PCIQXLDevice *d)
923 {
924 QXLRam *ram = d->ram;
925
926 assert(!d->ssd.running || SPICE_RING_IS_EMPTY(&ram->cmd_ring));
927 assert(!d->ssd.running || SPICE_RING_IS_EMPTY(&ram->cursor_ring));
928 }
929
930 static void qxl_reset_state(PCIQXLDevice *d)
931 {
932 QXLRom *rom = d->rom;
933
934 qxl_check_state(d);
935 d->shadow_rom.update_id = cpu_to_le32(0);
936 *rom = d->shadow_rom;
937 qxl_rom_set_dirty(d);
938 init_qxl_ram(d);
939 d->num_free_res = 0;
940 d->last_release = NULL;
941 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
942 }
943
944 static void qxl_soft_reset(PCIQXLDevice *d)
945 {
946 trace_qxl_soft_reset(d->id);
947 qxl_check_state(d);
948
949 if (d->id == 0) {
950 qxl_enter_vga_mode(d);
951 } else {
952 d->mode = QXL_MODE_UNDEFINED;
953 }
954 }
955
956 static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
957 {
958 trace_qxl_hard_reset(d->id, loadvm);
959
960 qxl_spice_reset_cursor(d);
961 qxl_spice_reset_image_cache(d);
962 qxl_reset_surfaces(d);
963 qxl_reset_memslots(d);
964
965 /* pre loadvm reset must not touch QXLRam. This lives in
966 * device memory, is migrated together with RAM and thus
967 * already loaded at this point */
968 if (!loadvm) {
969 qxl_reset_state(d);
970 }
971 qemu_spice_create_host_memslot(&d->ssd);
972 qxl_soft_reset(d);
973 }
974
975 static void qxl_reset_handler(DeviceState *dev)
976 {
977 PCIQXLDevice *d = DO_UPCAST(PCIQXLDevice, pci.qdev, dev);
978
979 qxl_hard_reset(d, 0);
980 }
981
982 static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
983 {
984 VGACommonState *vga = opaque;
985 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga);
986
987 trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val);
988 if (qxl->mode != QXL_MODE_VGA) {
989 qxl_destroy_primary(qxl, QXL_SYNC);
990 qxl_soft_reset(qxl);
991 }
992 vga_ioport_write(opaque, addr, val);
993 }
994
995 static const MemoryRegionPortio qxl_vga_portio_list[] = {
996 { 0x04, 2, 1, .read = vga_ioport_read,
997 .write = qxl_vga_ioport_write }, /* 3b4 */
998 { 0x0a, 1, 1, .read = vga_ioport_read,
999 .write = qxl_vga_ioport_write }, /* 3ba */
1000 { 0x10, 16, 1, .read = vga_ioport_read,
1001 .write = qxl_vga_ioport_write }, /* 3c0 */
1002 { 0x24, 2, 1, .read = vga_ioport_read,
1003 .write = qxl_vga_ioport_write }, /* 3d4 */
1004 { 0x2a, 1, 1, .read = vga_ioport_read,
1005 .write = qxl_vga_ioport_write }, /* 3da */
1006 PORTIO_END_OF_LIST(),
1007 };
1008
1009 static void qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
1010 qxl_async_io async)
1011 {
1012 static const int regions[] = {
1013 QXL_RAM_RANGE_INDEX,
1014 QXL_VRAM_RANGE_INDEX,
1015 QXL_VRAM64_RANGE_INDEX,
1016 };
1017 uint64_t guest_start;
1018 uint64_t guest_end;
1019 int pci_region;
1020 pcibus_t pci_start;
1021 pcibus_t pci_end;
1022 intptr_t virt_start;
1023 QXLDevMemSlot memslot;
1024 int i;
1025
1026 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
1027 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
1028
1029 trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end);
1030
1031 PANIC_ON(slot_id >= NUM_MEMSLOTS);
1032 PANIC_ON(guest_start > guest_end);
1033
1034 for (i = 0; i < ARRAY_SIZE(regions); i++) {
1035 pci_region = regions[i];
1036 pci_start = d->pci.io_regions[pci_region].addr;
1037 pci_end = pci_start + d->pci.io_regions[pci_region].size;
1038 /* mapped? */
1039 if (pci_start == -1) {
1040 continue;
1041 }
1042 /* start address in range ? */
1043 if (guest_start < pci_start || guest_start > pci_end) {
1044 continue;
1045 }
1046 /* end address in range ? */
1047 if (guest_end > pci_end) {
1048 continue;
1049 }
1050 /* passed */
1051 break;
1052 }
1053 PANIC_ON(i == ARRAY_SIZE(regions)); /* finished loop without match */
1054
1055 switch (pci_region) {
1056 case QXL_RAM_RANGE_INDEX:
1057 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vga.vram);
1058 break;
1059 case QXL_VRAM_RANGE_INDEX:
1060 case 4 /* vram 64bit */:
1061 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vram_bar);
1062 break;
1063 default:
1064 /* should not happen */
1065 abort();
1066 }
1067
1068 memslot.slot_id = slot_id;
1069 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
1070 memslot.virt_start = virt_start + (guest_start - pci_start);
1071 memslot.virt_end = virt_start + (guest_end - pci_start);
1072 memslot.addr_delta = memslot.virt_start - delta;
1073 memslot.generation = d->rom->slot_generation = 0;
1074 qxl_rom_set_dirty(d);
1075
1076 qemu_spice_add_memslot(&d->ssd, &memslot, async);
1077 d->guest_slots[slot_id].ptr = (void*)memslot.virt_start;
1078 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
1079 d->guest_slots[slot_id].delta = delta;
1080 d->guest_slots[slot_id].active = 1;
1081 }
1082
1083 static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
1084 {
1085 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id);
1086 d->guest_slots[slot_id].active = 0;
1087 }
1088
1089 static void qxl_reset_memslots(PCIQXLDevice *d)
1090 {
1091 qxl_spice_reset_memslots(d);
1092 memset(&d->guest_slots, 0, sizeof(d->guest_slots));
1093 }
1094
1095 static void qxl_reset_surfaces(PCIQXLDevice *d)
1096 {
1097 trace_qxl_reset_surfaces(d->id);
1098 d->mode = QXL_MODE_UNDEFINED;
1099 qxl_spice_destroy_surfaces(d, QXL_SYNC);
1100 }
1101
1102 /* can be also called from spice server thread context */
1103 void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
1104 {
1105 uint64_t phys = le64_to_cpu(pqxl);
1106 uint32_t slot = (phys >> (64 - 8)) & 0xff;
1107 uint64_t offset = phys & 0xffffffffffff;
1108
1109 switch (group_id) {
1110 case MEMSLOT_GROUP_HOST:
1111 return (void *)(intptr_t)offset;
1112 case MEMSLOT_GROUP_GUEST:
1113 if (slot >= NUM_MEMSLOTS) {
1114 qxl_guest_bug(qxl, "slot too large %d >= %d", slot, NUM_MEMSLOTS);
1115 return NULL;
1116 }
1117 if (!qxl->guest_slots[slot].active) {
1118 qxl_guest_bug(qxl, "inactive slot %d\n", slot);
1119 return NULL;
1120 }
1121 if (offset < qxl->guest_slots[slot].delta) {
1122 qxl_guest_bug(qxl, "slot %d offset %"PRIu64" < delta %"PRIu64"\n",
1123 slot, offset, qxl->guest_slots[slot].delta);
1124 return NULL;
1125 }
1126 offset -= qxl->guest_slots[slot].delta;
1127 if (offset > qxl->guest_slots[slot].size) {
1128 qxl_guest_bug(qxl, "slot %d offset %"PRIu64" > size %"PRIu64"\n",
1129 slot, offset, qxl->guest_slots[slot].size);
1130 return NULL;
1131 }
1132 return qxl->guest_slots[slot].ptr + offset;
1133 }
1134 return NULL;
1135 }
1136
1137 static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl)
1138 {
1139 /* for local rendering */
1140 qxl_render_resize(qxl);
1141 }
1142
1143 static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm,
1144 qxl_async_io async)
1145 {
1146 QXLDevSurfaceCreate surface;
1147 QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
1148
1149 assert(qxl->mode != QXL_MODE_NATIVE);
1150 qxl_exit_vga_mode(qxl);
1151
1152 surface.format = le32_to_cpu(sc->format);
1153 surface.height = le32_to_cpu(sc->height);
1154 surface.mem = le64_to_cpu(sc->mem);
1155 surface.position = le32_to_cpu(sc->position);
1156 surface.stride = le32_to_cpu(sc->stride);
1157 surface.width = le32_to_cpu(sc->width);
1158 surface.type = le32_to_cpu(sc->type);
1159 surface.flags = le32_to_cpu(sc->flags);
1160 trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem,
1161 sc->format, sc->position);
1162 trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type,
1163 sc->flags);
1164
1165 surface.mouse_mode = true;
1166 surface.group_id = MEMSLOT_GROUP_GUEST;
1167 if (loadvm) {
1168 surface.flags |= QXL_SURF_FLAG_KEEP_DATA;
1169 }
1170
1171 qxl->mode = QXL_MODE_NATIVE;
1172 qxl->cmdflags = 0;
1173 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async);
1174
1175 if (async == QXL_SYNC) {
1176 qxl_create_guest_primary_complete(qxl);
1177 }
1178 }
1179
1180 /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1181 * done (in QXL_SYNC case), 0 otherwise. */
1182 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async)
1183 {
1184 if (d->mode == QXL_MODE_UNDEFINED) {
1185 return 0;
1186 }
1187 trace_qxl_destroy_primary(d->id);
1188 d->mode = QXL_MODE_UNDEFINED;
1189 qemu_spice_destroy_primary_surface(&d->ssd, 0, async);
1190 qxl_spice_reset_cursor(d);
1191 return 1;
1192 }
1193
1194 static void qxl_set_mode(PCIQXLDevice *d, int modenr, int loadvm)
1195 {
1196 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1197 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
1198 QXLMode *mode = d->modes->modes + modenr;
1199 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1200 QXLMemSlot slot = {
1201 .mem_start = start,
1202 .mem_end = end
1203 };
1204 QXLSurfaceCreate surface = {
1205 .width = mode->x_res,
1206 .height = mode->y_res,
1207 .stride = -mode->x_res * 4,
1208 .format = SPICE_SURFACE_FMT_32_xRGB,
1209 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
1210 .mouse_mode = true,
1211 .mem = devmem + d->shadow_rom.draw_area_offset,
1212 };
1213
1214 trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits,
1215 devmem);
1216 if (!loadvm) {
1217 qxl_hard_reset(d, 0);
1218 }
1219
1220 d->guest_slots[0].slot = slot;
1221 qxl_add_memslot(d, 0, devmem, QXL_SYNC);
1222
1223 d->guest_primary.surface = surface;
1224 qxl_create_guest_primary(d, 0, QXL_SYNC);
1225
1226 d->mode = QXL_MODE_COMPAT;
1227 d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
1228 #ifdef QXL_COMMAND_FLAG_COMPAT_16BPP /* new in spice 0.6.1 */
1229 if (mode->bits == 16) {
1230 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
1231 }
1232 #endif
1233 d->shadow_rom.mode = cpu_to_le32(modenr);
1234 d->rom->mode = cpu_to_le32(modenr);
1235 qxl_rom_set_dirty(d);
1236 }
1237
1238 static void ioport_write(void *opaque, target_phys_addr_t addr,
1239 uint64_t val, unsigned size)
1240 {
1241 PCIQXLDevice *d = opaque;
1242 uint32_t io_port = addr;
1243 qxl_async_io async = QXL_SYNC;
1244 uint32_t orig_io_port = io_port;
1245
1246 switch (io_port) {
1247 case QXL_IO_RESET:
1248 case QXL_IO_SET_MODE:
1249 case QXL_IO_MEMSLOT_ADD:
1250 case QXL_IO_MEMSLOT_DEL:
1251 case QXL_IO_CREATE_PRIMARY:
1252 case QXL_IO_UPDATE_IRQ:
1253 case QXL_IO_LOG:
1254 case QXL_IO_MEMSLOT_ADD_ASYNC:
1255 case QXL_IO_CREATE_PRIMARY_ASYNC:
1256 break;
1257 default:
1258 if (d->mode != QXL_MODE_VGA) {
1259 break;
1260 }
1261 trace_qxl_io_unexpected_vga_mode(d->id,
1262 io_port, io_port_to_string(io_port));
1263 /* be nice to buggy guest drivers */
1264 if (io_port >= QXL_IO_UPDATE_AREA_ASYNC &&
1265 io_port <= QXL_IO_DESTROY_ALL_SURFACES_ASYNC) {
1266 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1267 }
1268 return;
1269 }
1270
1271 /* we change the io_port to avoid ifdeffery in the main switch */
1272 orig_io_port = io_port;
1273 switch (io_port) {
1274 case QXL_IO_UPDATE_AREA_ASYNC:
1275 io_port = QXL_IO_UPDATE_AREA;
1276 goto async_common;
1277 case QXL_IO_MEMSLOT_ADD_ASYNC:
1278 io_port = QXL_IO_MEMSLOT_ADD;
1279 goto async_common;
1280 case QXL_IO_CREATE_PRIMARY_ASYNC:
1281 io_port = QXL_IO_CREATE_PRIMARY;
1282 goto async_common;
1283 case QXL_IO_DESTROY_PRIMARY_ASYNC:
1284 io_port = QXL_IO_DESTROY_PRIMARY;
1285 goto async_common;
1286 case QXL_IO_DESTROY_SURFACE_ASYNC:
1287 io_port = QXL_IO_DESTROY_SURFACE_WAIT;
1288 goto async_common;
1289 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
1290 io_port = QXL_IO_DESTROY_ALL_SURFACES;
1291 goto async_common;
1292 case QXL_IO_FLUSH_SURFACES_ASYNC:
1293 async_common:
1294 async = QXL_ASYNC;
1295 qemu_mutex_lock(&d->async_lock);
1296 if (d->current_async != QXL_UNDEFINED_IO) {
1297 qxl_guest_bug(d, "%d async started before last (%d) complete",
1298 io_port, d->current_async);
1299 qemu_mutex_unlock(&d->async_lock);
1300 return;
1301 }
1302 d->current_async = orig_io_port;
1303 qemu_mutex_unlock(&d->async_lock);
1304 break;
1305 default:
1306 break;
1307 }
1308 trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode), addr, val, size,
1309 async);
1310
1311 switch (io_port) {
1312 case QXL_IO_UPDATE_AREA:
1313 {
1314 QXLCookie *cookie = NULL;
1315 QXLRect update = d->ram->update_area;
1316
1317 if (async == QXL_ASYNC) {
1318 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
1319 QXL_IO_UPDATE_AREA_ASYNC);
1320 cookie->u.area = update;
1321 }
1322 qxl_spice_update_area(d, d->ram->update_surface,
1323 cookie ? &cookie->u.area : &update,
1324 NULL, 0, 0, async, cookie);
1325 break;
1326 }
1327 case QXL_IO_NOTIFY_CMD:
1328 qemu_spice_wakeup(&d->ssd);
1329 break;
1330 case QXL_IO_NOTIFY_CURSOR:
1331 qemu_spice_wakeup(&d->ssd);
1332 break;
1333 case QXL_IO_UPDATE_IRQ:
1334 qxl_update_irq(d);
1335 break;
1336 case QXL_IO_NOTIFY_OOM:
1337 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
1338 break;
1339 }
1340 d->oom_running = 1;
1341 qxl_spice_oom(d);
1342 d->oom_running = 0;
1343 break;
1344 case QXL_IO_SET_MODE:
1345 qxl_set_mode(d, val, 0);
1346 break;
1347 case QXL_IO_LOG:
1348 if (d->guestdebug) {
1349 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id,
1350 qemu_get_clock_ns(vm_clock), d->ram->log_buf);
1351 }
1352 break;
1353 case QXL_IO_RESET:
1354 qxl_hard_reset(d, 0);
1355 break;
1356 case QXL_IO_MEMSLOT_ADD:
1357 if (val >= NUM_MEMSLOTS) {
1358 qxl_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range");
1359 break;
1360 }
1361 if (d->guest_slots[val].active) {
1362 qxl_guest_bug(d, "QXL_IO_MEMSLOT_ADD: memory slot already active");
1363 break;
1364 }
1365 d->guest_slots[val].slot = d->ram->mem_slot;
1366 qxl_add_memslot(d, val, 0, async);
1367 break;
1368 case QXL_IO_MEMSLOT_DEL:
1369 if (val >= NUM_MEMSLOTS) {
1370 qxl_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range");
1371 break;
1372 }
1373 qxl_del_memslot(d, val);
1374 break;
1375 case QXL_IO_CREATE_PRIMARY:
1376 if (val != 0) {
1377 qxl_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
1378 async);
1379 goto cancel_async;
1380 }
1381 d->guest_primary.surface = d->ram->create_surface;
1382 qxl_create_guest_primary(d, 0, async);
1383 break;
1384 case QXL_IO_DESTROY_PRIMARY:
1385 if (val != 0) {
1386 qxl_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
1387 async);
1388 goto cancel_async;
1389 }
1390 if (!qxl_destroy_primary(d, async)) {
1391 trace_qxl_io_destroy_primary_ignored(d->id,
1392 qxl_mode_to_string(d->mode));
1393 goto cancel_async;
1394 }
1395 break;
1396 case QXL_IO_DESTROY_SURFACE_WAIT:
1397 if (val >= NUM_SURFACES) {
1398 qxl_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):"
1399 "%" PRIu64 " >= NUM_SURFACES", async, val);
1400 goto cancel_async;
1401 }
1402 qxl_spice_destroy_surface_wait(d, val, async);
1403 break;
1404 case QXL_IO_FLUSH_RELEASE: {
1405 QXLReleaseRing *ring = &d->ram->release_ring;
1406 if (ring->prod - ring->cons + 1 == ring->num_items) {
1407 fprintf(stderr,
1408 "ERROR: no flush, full release ring [p%d,%dc]\n",
1409 ring->prod, ring->cons);
1410 }
1411 qxl_push_free_res(d, 1 /* flush */);
1412 break;
1413 }
1414 case QXL_IO_FLUSH_SURFACES_ASYNC:
1415 qxl_spice_flush_surfaces_async(d);
1416 break;
1417 case QXL_IO_DESTROY_ALL_SURFACES:
1418 d->mode = QXL_MODE_UNDEFINED;
1419 qxl_spice_destroy_surfaces(d, async);
1420 break;
1421 default:
1422 fprintf(stderr, "%s: ioport=0x%x, abort()\n", __FUNCTION__, io_port);
1423 abort();
1424 }
1425 return;
1426 cancel_async:
1427 if (async) {
1428 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1429 qemu_mutex_lock(&d->async_lock);
1430 d->current_async = QXL_UNDEFINED_IO;
1431 qemu_mutex_unlock(&d->async_lock);
1432 }
1433 }
1434
1435 static uint64_t ioport_read(void *opaque, target_phys_addr_t addr,
1436 unsigned size)
1437 {
1438 PCIQXLDevice *d = opaque;
1439
1440 trace_qxl_io_read_unexpected(d->id);
1441 return 0xff;
1442 }
1443
1444 static const MemoryRegionOps qxl_io_ops = {
1445 .read = ioport_read,
1446 .write = ioport_write,
1447 .valid = {
1448 .min_access_size = 1,
1449 .max_access_size = 1,
1450 },
1451 };
1452
1453 static void pipe_read(void *opaque)
1454 {
1455 PCIQXLDevice *d = opaque;
1456 char dummy;
1457 int len;
1458
1459 do {
1460 len = read(d->pipe[0], &dummy, sizeof(dummy));
1461 } while (len == sizeof(dummy));
1462 qxl_update_irq(d);
1463 }
1464
1465 static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
1466 {
1467 uint32_t old_pending;
1468 uint32_t le_events = cpu_to_le32(events);
1469
1470 assert(d->ssd.running);
1471 old_pending = __sync_fetch_and_or(&d->ram->int_pending, le_events);
1472 if ((old_pending & le_events) == le_events) {
1473 return;
1474 }
1475 if (qemu_thread_is_self(&d->main)) {
1476 qxl_update_irq(d);
1477 } else {
1478 if (write(d->pipe[1], d, 1) != 1) {
1479 dprint(d, 1, "%s: write to pipe failed\n", __FUNCTION__);
1480 }
1481 }
1482 }
1483
1484 static void init_pipe_signaling(PCIQXLDevice *d)
1485 {
1486 if (pipe(d->pipe) < 0) {
1487 fprintf(stderr, "%s:%s: qxl pipe creation failed\n",
1488 __FILE__, __func__);
1489 exit(1);
1490 }
1491 fcntl(d->pipe[0], F_SETFL, O_NONBLOCK);
1492 fcntl(d->pipe[1], F_SETFL, O_NONBLOCK);
1493 fcntl(d->pipe[0], F_SETOWN, getpid());
1494
1495 qemu_thread_get_self(&d->main);
1496 qemu_set_fd_handler(d->pipe[0], pipe_read, NULL, d);
1497 }
1498
1499 /* graphics console */
1500
1501 static void qxl_hw_update(void *opaque)
1502 {
1503 PCIQXLDevice *qxl = opaque;
1504 VGACommonState *vga = &qxl->vga;
1505
1506 switch (qxl->mode) {
1507 case QXL_MODE_VGA:
1508 vga->update(vga);
1509 break;
1510 case QXL_MODE_COMPAT:
1511 case QXL_MODE_NATIVE:
1512 qxl_render_update(qxl);
1513 break;
1514 default:
1515 break;
1516 }
1517 }
1518
1519 static void qxl_hw_invalidate(void *opaque)
1520 {
1521 PCIQXLDevice *qxl = opaque;
1522 VGACommonState *vga = &qxl->vga;
1523
1524 vga->invalidate(vga);
1525 }
1526
1527 static void qxl_hw_screen_dump(void *opaque, const char *filename, bool cswitch)
1528 {
1529 PCIQXLDevice *qxl = opaque;
1530 VGACommonState *vga = &qxl->vga;
1531
1532 switch (qxl->mode) {
1533 case QXL_MODE_COMPAT:
1534 case QXL_MODE_NATIVE:
1535 qxl_render_update(qxl);
1536 ppm_save(filename, qxl->ssd.ds->surface);
1537 break;
1538 case QXL_MODE_VGA:
1539 vga->screen_dump(vga, filename, cswitch);
1540 break;
1541 default:
1542 break;
1543 }
1544 }
1545
1546 static void qxl_hw_text_update(void *opaque, console_ch_t *chardata)
1547 {
1548 PCIQXLDevice *qxl = opaque;
1549 VGACommonState *vga = &qxl->vga;
1550
1551 if (qxl->mode == QXL_MODE_VGA) {
1552 vga->text_update(vga, chardata);
1553 return;
1554 }
1555 }
1556
1557 static void qxl_dirty_surfaces(PCIQXLDevice *qxl)
1558 {
1559 intptr_t vram_start;
1560 int i;
1561
1562 if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) {
1563 return;
1564 }
1565
1566 /* dirty the primary surface */
1567 qxl_set_dirty(&qxl->vga.vram, qxl->shadow_rom.draw_area_offset,
1568 qxl->shadow_rom.surface0_area_size);
1569
1570 vram_start = (intptr_t)memory_region_get_ram_ptr(&qxl->vram_bar);
1571
1572 /* dirty the off-screen surfaces */
1573 for (i = 0; i < NUM_SURFACES; i++) {
1574 QXLSurfaceCmd *cmd;
1575 intptr_t surface_offset;
1576 int surface_size;
1577
1578 if (qxl->guest_surfaces.cmds[i] == 0) {
1579 continue;
1580 }
1581
1582 cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i],
1583 MEMSLOT_GROUP_GUEST);
1584 assert(cmd);
1585 assert(cmd->type == QXL_SURFACE_CMD_CREATE);
1586 surface_offset = (intptr_t)qxl_phys2virt(qxl,
1587 cmd->u.surface_create.data,
1588 MEMSLOT_GROUP_GUEST);
1589 assert(surface_offset);
1590 surface_offset -= vram_start;
1591 surface_size = cmd->u.surface_create.height *
1592 abs(cmd->u.surface_create.stride);
1593 trace_qxl_surfaces_dirty(qxl->id, i, (int)surface_offset, surface_size);
1594 qxl_set_dirty(&qxl->vram_bar, surface_offset, surface_size);
1595 }
1596 }
1597
1598 static void qxl_vm_change_state_handler(void *opaque, int running,
1599 RunState state)
1600 {
1601 PCIQXLDevice *qxl = opaque;
1602 qemu_spice_vm_change_state_handler(&qxl->ssd, running, state);
1603
1604 if (running) {
1605 /*
1606 * if qxl_send_events was called from spice server context before
1607 * migration ended, qxl_update_irq for these events might not have been
1608 * called
1609 */
1610 qxl_update_irq(qxl);
1611 } else {
1612 /* make sure surfaces are saved before migration */
1613 qxl_dirty_surfaces(qxl);
1614 }
1615 }
1616
1617 /* display change listener */
1618
1619 static void display_update(struct DisplayState *ds, int x, int y, int w, int h)
1620 {
1621 if (qxl0->mode == QXL_MODE_VGA) {
1622 qemu_spice_display_update(&qxl0->ssd, x, y, w, h);
1623 }
1624 }
1625
1626 static void display_resize(struct DisplayState *ds)
1627 {
1628 if (qxl0->mode == QXL_MODE_VGA) {
1629 qemu_spice_display_resize(&qxl0->ssd);
1630 }
1631 }
1632
1633 static void display_refresh(struct DisplayState *ds)
1634 {
1635 if (qxl0->mode == QXL_MODE_VGA) {
1636 qemu_spice_display_refresh(&qxl0->ssd);
1637 } else {
1638 qemu_mutex_lock(&qxl0->ssd.lock);
1639 qemu_spice_cursor_refresh_unlocked(&qxl0->ssd);
1640 qemu_mutex_unlock(&qxl0->ssd.lock);
1641 }
1642 }
1643
1644 static DisplayChangeListener display_listener = {
1645 .dpy_update = display_update,
1646 .dpy_resize = display_resize,
1647 .dpy_refresh = display_refresh,
1648 };
1649
1650 static void qxl_init_ramsize(PCIQXLDevice *qxl, uint32_t ram_min_mb)
1651 {
1652 /* vga ram (bar 0) */
1653 if (qxl->ram_size_mb != -1) {
1654 qxl->vga.vram_size = qxl->ram_size_mb * 1024 * 1024;
1655 }
1656 if (qxl->vga.vram_size < ram_min_mb * 1024 * 1024) {
1657 qxl->vga.vram_size = ram_min_mb * 1024 * 1024;
1658 }
1659
1660 /* vram32 (surfaces, 32bit, bar 1) */
1661 if (qxl->vram32_size_mb != -1) {
1662 qxl->vram32_size = qxl->vram32_size_mb * 1024 * 1024;
1663 }
1664 if (qxl->vram32_size < 4096) {
1665 qxl->vram32_size = 4096;
1666 }
1667
1668 /* vram (surfaces, 64bit, bar 4+5) */
1669 if (qxl->vram_size_mb != -1) {
1670 qxl->vram_size = qxl->vram_size_mb * 1024 * 1024;
1671 }
1672 if (qxl->vram_size < qxl->vram32_size) {
1673 qxl->vram_size = qxl->vram32_size;
1674 }
1675
1676 if (qxl->revision == 1) {
1677 qxl->vram32_size = 4096;
1678 qxl->vram_size = 4096;
1679 }
1680 qxl->vga.vram_size = msb_mask(qxl->vga.vram_size * 2 - 1);
1681 qxl->vram32_size = msb_mask(qxl->vram32_size * 2 - 1);
1682 qxl->vram_size = msb_mask(qxl->vram_size * 2 - 1);
1683 }
1684
1685 static int qxl_init_common(PCIQXLDevice *qxl)
1686 {
1687 uint8_t* config = qxl->pci.config;
1688 uint32_t pci_device_rev;
1689 uint32_t io_size;
1690
1691 qxl->mode = QXL_MODE_UNDEFINED;
1692 qxl->generation = 1;
1693 qxl->num_memslots = NUM_MEMSLOTS;
1694 qxl->num_surfaces = NUM_SURFACES;
1695 qemu_mutex_init(&qxl->track_lock);
1696 qemu_mutex_init(&qxl->async_lock);
1697 qxl->current_async = QXL_UNDEFINED_IO;
1698
1699 switch (qxl->revision) {
1700 case 1: /* spice 0.4 -- qxl-1 */
1701 pci_device_rev = QXL_REVISION_STABLE_V04;
1702 break;
1703 case 2: /* spice 0.6 -- qxl-2 */
1704 pci_device_rev = QXL_REVISION_STABLE_V06;
1705 break;
1706 case 3: /* qxl-3 */
1707 default:
1708 pci_device_rev = QXL_DEFAULT_REVISION;
1709 break;
1710 }
1711
1712 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
1713 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
1714
1715 qxl->rom_size = qxl_rom_size();
1716 memory_region_init_ram(&qxl->rom_bar, "qxl.vrom", qxl->rom_size);
1717 vmstate_register_ram(&qxl->rom_bar, &qxl->pci.qdev);
1718 init_qxl_rom(qxl);
1719 init_qxl_ram(qxl);
1720
1721 memory_region_init_ram(&qxl->vram_bar, "qxl.vram", qxl->vram_size);
1722 vmstate_register_ram(&qxl->vram_bar, &qxl->pci.qdev);
1723 memory_region_init_alias(&qxl->vram32_bar, "qxl.vram32", &qxl->vram_bar,
1724 0, qxl->vram32_size);
1725
1726 io_size = msb_mask(QXL_IO_RANGE_SIZE * 2 - 1);
1727 if (qxl->revision == 1) {
1728 io_size = 8;
1729 }
1730
1731 memory_region_init_io(&qxl->io_bar, &qxl_io_ops, qxl,
1732 "qxl-ioports", io_size);
1733 if (qxl->id == 0) {
1734 vga_dirty_log_start(&qxl->vga);
1735 }
1736
1737
1738 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
1739 PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar);
1740
1741 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
1742 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar);
1743
1744 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
1745 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram);
1746
1747 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX,
1748 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar);
1749
1750 if (qxl->vram32_size < qxl->vram_size) {
1751 /*
1752 * Make the 64bit vram bar show up only in case it is
1753 * configured to be larger than the 32bit vram bar.
1754 */
1755 pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX,
1756 PCI_BASE_ADDRESS_SPACE_MEMORY |
1757 PCI_BASE_ADDRESS_MEM_TYPE_64 |
1758 PCI_BASE_ADDRESS_MEM_PREFETCH,
1759 &qxl->vram_bar);
1760 }
1761
1762 /* print pci bar details */
1763 dprint(qxl, 1, "ram/%s: %d MB [region 0]\n",
1764 qxl->id == 0 ? "pri" : "sec",
1765 qxl->vga.vram_size / (1024*1024));
1766 dprint(qxl, 1, "vram/32: %d MB [region 1]\n",
1767 qxl->vram32_size / (1024*1024));
1768 dprint(qxl, 1, "vram/64: %d MB %s\n",
1769 qxl->vram_size / (1024*1024),
1770 qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]");
1771
1772 qxl->ssd.qxl.base.sif = &qxl_interface.base;
1773 qxl->ssd.qxl.id = qxl->id;
1774 qemu_spice_add_interface(&qxl->ssd.qxl.base);
1775 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
1776
1777 init_pipe_signaling(qxl);
1778 qxl_reset_state(qxl);
1779
1780 qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl);
1781
1782 return 0;
1783 }
1784
1785 static int qxl_init_primary(PCIDevice *dev)
1786 {
1787 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
1788 VGACommonState *vga = &qxl->vga;
1789 PortioList *qxl_vga_port_list = g_new(PortioList, 1);
1790
1791 qxl->id = 0;
1792 qxl_init_ramsize(qxl, 32);
1793 vga_common_init(vga, qxl->vga.vram_size);
1794 vga_init(vga, pci_address_space(dev), pci_address_space_io(dev), false);
1795 portio_list_init(qxl_vga_port_list, qxl_vga_portio_list, vga, "vga");
1796 portio_list_add(qxl_vga_port_list, pci_address_space_io(dev), 0x3b0);
1797
1798 vga->ds = graphic_console_init(qxl_hw_update, qxl_hw_invalidate,
1799 qxl_hw_screen_dump, qxl_hw_text_update, qxl);
1800 qemu_spice_display_init_common(&qxl->ssd, vga->ds);
1801
1802 qxl0 = qxl;
1803 register_displaychangelistener(vga->ds, &display_listener);
1804
1805 return qxl_init_common(qxl);
1806 }
1807
1808 static int qxl_init_secondary(PCIDevice *dev)
1809 {
1810 static int device_id = 1;
1811 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
1812
1813 qxl->id = device_id++;
1814 qxl_init_ramsize(qxl, 16);
1815 memory_region_init_ram(&qxl->vga.vram, "qxl.vgavram", qxl->vga.vram_size);
1816 vmstate_register_ram(&qxl->vga.vram, &qxl->pci.qdev);
1817 qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
1818
1819 return qxl_init_common(qxl);
1820 }
1821
1822 static void qxl_pre_save(void *opaque)
1823 {
1824 PCIQXLDevice* d = opaque;
1825 uint8_t *ram_start = d->vga.vram_ptr;
1826
1827 trace_qxl_pre_save(d->id);
1828 if (d->last_release == NULL) {
1829 d->last_release_offset = 0;
1830 } else {
1831 d->last_release_offset = (uint8_t *)d->last_release - ram_start;
1832 }
1833 assert(d->last_release_offset < d->vga.vram_size);
1834 }
1835
1836 static int qxl_pre_load(void *opaque)
1837 {
1838 PCIQXLDevice* d = opaque;
1839
1840 trace_qxl_pre_load(d->id);
1841 qxl_hard_reset(d, 1);
1842 qxl_exit_vga_mode(d);
1843 return 0;
1844 }
1845
1846 static void qxl_create_memslots(PCIQXLDevice *d)
1847 {
1848 int i;
1849
1850 for (i = 0; i < NUM_MEMSLOTS; i++) {
1851 if (!d->guest_slots[i].active) {
1852 continue;
1853 }
1854 qxl_add_memslot(d, i, 0, QXL_SYNC);
1855 }
1856 }
1857
1858 static int qxl_post_load(void *opaque, int version)
1859 {
1860 PCIQXLDevice* d = opaque;
1861 uint8_t *ram_start = d->vga.vram_ptr;
1862 QXLCommandExt *cmds;
1863 int in, out, newmode;
1864
1865 assert(d->last_release_offset < d->vga.vram_size);
1866 if (d->last_release_offset == 0) {
1867 d->last_release = NULL;
1868 } else {
1869 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
1870 }
1871
1872 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
1873
1874 trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode));
1875 newmode = d->mode;
1876 d->mode = QXL_MODE_UNDEFINED;
1877
1878 switch (newmode) {
1879 case QXL_MODE_UNDEFINED:
1880 break;
1881 case QXL_MODE_VGA:
1882 qxl_create_memslots(d);
1883 qxl_enter_vga_mode(d);
1884 break;
1885 case QXL_MODE_NATIVE:
1886 qxl_create_memslots(d);
1887 qxl_create_guest_primary(d, 1, QXL_SYNC);
1888
1889 /* replay surface-create and cursor-set commands */
1890 cmds = g_malloc0(sizeof(QXLCommandExt) * (NUM_SURFACES + 1));
1891 for (in = 0, out = 0; in < NUM_SURFACES; in++) {
1892 if (d->guest_surfaces.cmds[in] == 0) {
1893 continue;
1894 }
1895 cmds[out].cmd.data = d->guest_surfaces.cmds[in];
1896 cmds[out].cmd.type = QXL_CMD_SURFACE;
1897 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
1898 out++;
1899 }
1900 if (d->guest_cursor) {
1901 cmds[out].cmd.data = d->guest_cursor;
1902 cmds[out].cmd.type = QXL_CMD_CURSOR;
1903 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
1904 out++;
1905 }
1906 qxl_spice_loadvm_commands(d, cmds, out);
1907 g_free(cmds);
1908
1909 break;
1910 case QXL_MODE_COMPAT:
1911 /* note: no need to call qxl_create_memslots, qxl_set_mode
1912 * creates the mem slot. */
1913 qxl_set_mode(d, d->shadow_rom.mode, 1);
1914 break;
1915 }
1916 return 0;
1917 }
1918
1919 #define QXL_SAVE_VERSION 21
1920
1921 static VMStateDescription qxl_memslot = {
1922 .name = "qxl-memslot",
1923 .version_id = QXL_SAVE_VERSION,
1924 .minimum_version_id = QXL_SAVE_VERSION,
1925 .fields = (VMStateField[]) {
1926 VMSTATE_UINT64(slot.mem_start, struct guest_slots),
1927 VMSTATE_UINT64(slot.mem_end, struct guest_slots),
1928 VMSTATE_UINT32(active, struct guest_slots),
1929 VMSTATE_END_OF_LIST()
1930 }
1931 };
1932
1933 static VMStateDescription qxl_surface = {
1934 .name = "qxl-surface",
1935 .version_id = QXL_SAVE_VERSION,
1936 .minimum_version_id = QXL_SAVE_VERSION,
1937 .fields = (VMStateField[]) {
1938 VMSTATE_UINT32(width, QXLSurfaceCreate),
1939 VMSTATE_UINT32(height, QXLSurfaceCreate),
1940 VMSTATE_INT32(stride, QXLSurfaceCreate),
1941 VMSTATE_UINT32(format, QXLSurfaceCreate),
1942 VMSTATE_UINT32(position, QXLSurfaceCreate),
1943 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate),
1944 VMSTATE_UINT32(flags, QXLSurfaceCreate),
1945 VMSTATE_UINT32(type, QXLSurfaceCreate),
1946 VMSTATE_UINT64(mem, QXLSurfaceCreate),
1947 VMSTATE_END_OF_LIST()
1948 }
1949 };
1950
1951 static VMStateDescription qxl_vmstate = {
1952 .name = "qxl",
1953 .version_id = QXL_SAVE_VERSION,
1954 .minimum_version_id = QXL_SAVE_VERSION,
1955 .pre_save = qxl_pre_save,
1956 .pre_load = qxl_pre_load,
1957 .post_load = qxl_post_load,
1958 .fields = (VMStateField []) {
1959 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice),
1960 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
1961 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice),
1962 VMSTATE_UINT32(num_free_res, PCIQXLDevice),
1963 VMSTATE_UINT32(last_release_offset, PCIQXLDevice),
1964 VMSTATE_UINT32(mode, PCIQXLDevice),
1965 VMSTATE_UINT32(ssd.unique, PCIQXLDevice),
1966 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice),
1967 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
1968 qxl_memslot, struct guest_slots),
1969 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
1970 qxl_surface, QXLSurfaceCreate),
1971 VMSTATE_INT32_EQUAL(num_surfaces, PCIQXLDevice),
1972 VMSTATE_ARRAY(guest_surfaces.cmds, PCIQXLDevice, NUM_SURFACES, 0,
1973 vmstate_info_uint64, uint64_t),
1974 VMSTATE_UINT64(guest_cursor, PCIQXLDevice),
1975 VMSTATE_END_OF_LIST()
1976 },
1977 };
1978
1979 static Property qxl_properties[] = {
1980 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size,
1981 64 * 1024 * 1024),
1982 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram32_size,
1983 64 * 1024 * 1024),
1984 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
1985 QXL_DEFAULT_REVISION),
1986 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
1987 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
1988 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
1989 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1),
1990 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1),
1991 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1),
1992 DEFINE_PROP_END_OF_LIST(),
1993 };
1994
1995 static void qxl_primary_class_init(ObjectClass *klass, void *data)
1996 {
1997 DeviceClass *dc = DEVICE_CLASS(klass);
1998 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1999
2000 k->no_hotplug = 1;
2001 k->init = qxl_init_primary;
2002 k->romfile = "vgabios-qxl.bin";
2003 k->vendor_id = REDHAT_PCI_VENDOR_ID;
2004 k->device_id = QXL_DEVICE_ID_STABLE;
2005 k->class_id = PCI_CLASS_DISPLAY_VGA;
2006 dc->desc = "Spice QXL GPU (primary, vga compatible)";
2007 dc->reset = qxl_reset_handler;
2008 dc->vmsd = &qxl_vmstate;
2009 dc->props = qxl_properties;
2010 }
2011
2012 static TypeInfo qxl_primary_info = {
2013 .name = "qxl-vga",
2014 .parent = TYPE_PCI_DEVICE,
2015 .instance_size = sizeof(PCIQXLDevice),
2016 .class_init = qxl_primary_class_init,
2017 };
2018
2019 static void qxl_secondary_class_init(ObjectClass *klass, void *data)
2020 {
2021 DeviceClass *dc = DEVICE_CLASS(klass);
2022 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2023
2024 k->init = qxl_init_secondary;
2025 k->vendor_id = REDHAT_PCI_VENDOR_ID;
2026 k->device_id = QXL_DEVICE_ID_STABLE;
2027 k->class_id = PCI_CLASS_DISPLAY_OTHER;
2028 dc->desc = "Spice QXL GPU (secondary)";
2029 dc->reset = qxl_reset_handler;
2030 dc->vmsd = &qxl_vmstate;
2031 dc->props = qxl_properties;
2032 }
2033
2034 static TypeInfo qxl_secondary_info = {
2035 .name = "qxl",
2036 .parent = TYPE_PCI_DEVICE,
2037 .instance_size = sizeof(PCIQXLDevice),
2038 .class_init = qxl_secondary_class_init,
2039 };
2040
2041 static void qxl_register_types(void)
2042 {
2043 type_register_static(&qxl_primary_info);
2044 type_register_static(&qxl_secondary_info);
2045 }
2046
2047 type_init(qxl_register_types)
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