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ppc: Fix slbia decode
[qemu/kevin.git] / target-ppc / translate.c
blob0b6a4b680b606b1be021f9427844657084024f85
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg-op.h"
26 #include "qemu/host-utils.h"
27 #include "exec/cpu_ldst.h"
28
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
31
32 #include "trace-tcg.h"
33 #include "exec/log.h"
34
35
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
39
40 /* Include definitions for instructions classes and implementations flags */
41 //#define PPC_DEBUG_DISAS
42 //#define DO_PPC_STATISTICS
43
44 #ifdef PPC_DEBUG_DISAS
45 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
46 #else
47 # define LOG_DISAS(...) do { } while (0)
48 #endif
49 /*****************************************************************************/
50 /* Code translation helpers */
51
52 /* global register indexes */
53 static TCGv_env cpu_env;
54 static char cpu_reg_names[10*3 + 22*4 /* GPR */
55 + 10*4 + 22*5 /* SPE GPRh */
56 + 10*4 + 22*5 /* FPR */
57 + 2*(10*6 + 22*7) /* AVRh, AVRl */
58 + 10*5 + 22*6 /* VSR */
59 + 8*5 /* CRF */];
60 static TCGv cpu_gpr[32];
61 static TCGv cpu_gprh[32];
62 static TCGv_i64 cpu_fpr[32];
63 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
64 static TCGv_i64 cpu_vsr[32];
65 static TCGv_i32 cpu_crf[8];
66 static TCGv cpu_nip;
67 static TCGv cpu_msr;
68 static TCGv cpu_ctr;
69 static TCGv cpu_lr;
70 #if defined(TARGET_PPC64)
71 static TCGv cpu_cfar;
72 #endif
73 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
74 static TCGv cpu_reserve;
75 static TCGv cpu_fpscr;
76 static TCGv_i32 cpu_access_type;
77
78 #include "exec/gen-icount.h"
79
80 void ppc_translate_init(void)
81 {
82 int i;
83 char* p;
84 size_t cpu_reg_names_size;
85 static int done_init = 0;
86
87 if (done_init)
88 return;
89
90 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
91
92 p = cpu_reg_names;
93 cpu_reg_names_size = sizeof(cpu_reg_names);
94
95 for (i = 0; i < 8; i++) {
96 snprintf(p, cpu_reg_names_size, "crf%d", i);
97 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
98 offsetof(CPUPPCState, crf[i]), p);
99 p += 5;
100 cpu_reg_names_size -= 5;
101 }
102
103 for (i = 0; i < 32; i++) {
104 snprintf(p, cpu_reg_names_size, "r%d", i);
105 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
106 offsetof(CPUPPCState, gpr[i]), p);
107 p += (i < 10) ? 3 : 4;
108 cpu_reg_names_size -= (i < 10) ? 3 : 4;
109 snprintf(p, cpu_reg_names_size, "r%dH", i);
110 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
111 offsetof(CPUPPCState, gprh[i]), p);
112 p += (i < 10) ? 4 : 5;
113 cpu_reg_names_size -= (i < 10) ? 4 : 5;
114
115 snprintf(p, cpu_reg_names_size, "fp%d", i);
116 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
117 offsetof(CPUPPCState, fpr[i]), p);
118 p += (i < 10) ? 4 : 5;
119 cpu_reg_names_size -= (i < 10) ? 4 : 5;
120
121 snprintf(p, cpu_reg_names_size, "avr%dH", i);
122 #ifdef HOST_WORDS_BIGENDIAN
123 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
124 offsetof(CPUPPCState, avr[i].u64[0]), p);
125 #else
126 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
127 offsetof(CPUPPCState, avr[i].u64[1]), p);
128 #endif
129 p += (i < 10) ? 6 : 7;
130 cpu_reg_names_size -= (i < 10) ? 6 : 7;
131
132 snprintf(p, cpu_reg_names_size, "avr%dL", i);
133 #ifdef HOST_WORDS_BIGENDIAN
134 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
135 offsetof(CPUPPCState, avr[i].u64[1]), p);
136 #else
137 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
138 offsetof(CPUPPCState, avr[i].u64[0]), p);
139 #endif
140 p += (i < 10) ? 6 : 7;
141 cpu_reg_names_size -= (i < 10) ? 6 : 7;
142 snprintf(p, cpu_reg_names_size, "vsr%d", i);
143 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
144 offsetof(CPUPPCState, vsr[i]), p);
145 p += (i < 10) ? 5 : 6;
146 cpu_reg_names_size -= (i < 10) ? 5 : 6;
147 }
148
149 cpu_nip = tcg_global_mem_new(cpu_env,
150 offsetof(CPUPPCState, nip), "nip");
151
152 cpu_msr = tcg_global_mem_new(cpu_env,
153 offsetof(CPUPPCState, msr), "msr");
154
155 cpu_ctr = tcg_global_mem_new(cpu_env,
156 offsetof(CPUPPCState, ctr), "ctr");
157
158 cpu_lr = tcg_global_mem_new(cpu_env,
159 offsetof(CPUPPCState, lr), "lr");
160
161 #if defined(TARGET_PPC64)
162 cpu_cfar = tcg_global_mem_new(cpu_env,
163 offsetof(CPUPPCState, cfar), "cfar");
164 #endif
165
166 cpu_xer = tcg_global_mem_new(cpu_env,
167 offsetof(CPUPPCState, xer), "xer");
168 cpu_so = tcg_global_mem_new(cpu_env,
169 offsetof(CPUPPCState, so), "SO");
170 cpu_ov = tcg_global_mem_new(cpu_env,
171 offsetof(CPUPPCState, ov), "OV");
172 cpu_ca = tcg_global_mem_new(cpu_env,
173 offsetof(CPUPPCState, ca), "CA");
174
175 cpu_reserve = tcg_global_mem_new(cpu_env,
176 offsetof(CPUPPCState, reserve_addr),
177 "reserve_addr");
178
179 cpu_fpscr = tcg_global_mem_new(cpu_env,
180 offsetof(CPUPPCState, fpscr), "fpscr");
181
182 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
183 offsetof(CPUPPCState, access_type), "access_type");
184
185 done_init = 1;
186 }
187
188 /* internal defines */
189 struct DisasContext {
190 struct TranslationBlock *tb;
191 target_ulong nip;
192 uint32_t opcode;
193 uint32_t exception;
194 /* Routine used to access memory */
195 bool pr, hv;
196 bool lazy_tlb_flush;
197 int mem_idx;
198 int access_type;
199 /* Translation flags */
200 int le_mode;
201 TCGMemOp default_tcg_memop_mask;
202 #if defined(TARGET_PPC64)
203 int sf_mode;
204 int has_cfar;
205 #endif
206 int fpu_enabled;
207 int altivec_enabled;
208 int vsx_enabled;
209 int spe_enabled;
210 int tm_enabled;
211 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
212 int singlestep_enabled;
213 uint64_t insns_flags;
214 uint64_t insns_flags2;
215 };
216
217 /* Return true iff byteswap is needed in a scalar memop */
218 static inline bool need_byteswap(const DisasContext *ctx)
219 {
220 #if defined(TARGET_WORDS_BIGENDIAN)
221 return ctx->le_mode;
222 #else
223 return !ctx->le_mode;
224 #endif
225 }
226
227 /* True when active word size < size of target_long. */
228 #ifdef TARGET_PPC64
229 # define NARROW_MODE(C) (!(C)->sf_mode)
230 #else
231 # define NARROW_MODE(C) 0
232 #endif
233
234 struct opc_handler_t {
235 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
236 uint32_t inval1;
237 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
238 uint32_t inval2;
239 /* instruction type */
240 uint64_t type;
241 /* extended instruction type */
242 uint64_t type2;
243 /* handler */
244 void (*handler)(DisasContext *ctx);
245 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
246 const char *oname;
247 #endif
248 #if defined(DO_PPC_STATISTICS)
249 uint64_t count;
250 #endif
251 };
252
253 static inline void gen_reset_fpstatus(void)
254 {
255 gen_helper_reset_fpstatus(cpu_env);
256 }
257
258 static inline void gen_compute_fprf(TCGv_i64 arg)
259 {
260 gen_helper_compute_fprf(cpu_env, arg);
261 gen_helper_float_check_status(cpu_env);
262 }
263
264 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
265 {
266 if (ctx->access_type != access_type) {
267 tcg_gen_movi_i32(cpu_access_type, access_type);
268 ctx->access_type = access_type;
269 }
270 }
271
272 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
273 {
274 if (NARROW_MODE(ctx)) {
275 nip = (uint32_t)nip;
276 }
277 tcg_gen_movi_tl(cpu_nip, nip);
278 }
279
280 void gen_update_current_nip(void *opaque)
281 {
282 DisasContext *ctx = opaque;
283
284 tcg_gen_movi_tl(cpu_nip, ctx->nip);
285 }
286
287 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
288 {
289 TCGv_i32 t0, t1;
290 if (ctx->exception == POWERPC_EXCP_NONE) {
291 gen_update_nip(ctx, ctx->nip);
292 }
293 t0 = tcg_const_i32(excp);
294 t1 = tcg_const_i32(error);
295 gen_helper_raise_exception_err(cpu_env, t0, t1);
296 tcg_temp_free_i32(t0);
297 tcg_temp_free_i32(t1);
298 ctx->exception = (excp);
299 }
300
301 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
302 {
303 TCGv_i32 t0;
304 if (ctx->exception == POWERPC_EXCP_NONE) {
305 gen_update_nip(ctx, ctx->nip);
306 }
307 t0 = tcg_const_i32(excp);
308 gen_helper_raise_exception(cpu_env, t0);
309 tcg_temp_free_i32(t0);
310 ctx->exception = (excp);
311 }
312
313 static inline void gen_debug_exception(DisasContext *ctx)
314 {
315 TCGv_i32 t0;
316
317 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
318 (ctx->exception != POWERPC_EXCP_SYNC)) {
319 gen_update_nip(ctx, ctx->nip);
320 }
321 t0 = tcg_const_i32(EXCP_DEBUG);
322 gen_helper_raise_exception(cpu_env, t0);
323 tcg_temp_free_i32(t0);
324 }
325
326 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
327 {
328 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
329 }
330
331 /* Stop translation */
332 static inline void gen_stop_exception(DisasContext *ctx)
333 {
334 gen_update_nip(ctx, ctx->nip);
335 ctx->exception = POWERPC_EXCP_STOP;
336 }
337
338 #ifndef CONFIG_USER_ONLY
339 /* No need to update nip here, as execution flow will change */
340 static inline void gen_sync_exception(DisasContext *ctx)
341 {
342 ctx->exception = POWERPC_EXCP_SYNC;
343 }
344 #endif
345
346 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
347 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
348
349 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
350 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
351
352 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
353 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
354
355 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
356 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
357
358 typedef struct opcode_t {
359 unsigned char opc1, opc2, opc3;
360 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
361 unsigned char pad[5];
362 #else
363 unsigned char pad[1];
364 #endif
365 opc_handler_t handler;
366 const char *oname;
367 } opcode_t;
368
369 /*****************************************************************************/
370 /*** Instruction decoding ***/
371 #define EXTRACT_HELPER(name, shift, nb) \
372 static inline uint32_t name(uint32_t opcode) \
373 { \
374 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
375 }
376
377 #define EXTRACT_SHELPER(name, shift, nb) \
378 static inline int32_t name(uint32_t opcode) \
379 { \
380 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
381 }
382
383 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
384 static inline uint32_t name(uint32_t opcode) \
385 { \
386 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
387 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
388 }
389 /* Opcode part 1 */
390 EXTRACT_HELPER(opc1, 26, 6);
391 /* Opcode part 2 */
392 EXTRACT_HELPER(opc2, 1, 5);
393 /* Opcode part 3 */
394 EXTRACT_HELPER(opc3, 6, 5);
395 /* Update Cr0 flags */
396 EXTRACT_HELPER(Rc, 0, 1);
397 /* Update Cr6 flags (Altivec) */
398 EXTRACT_HELPER(Rc21, 10, 1);
399 /* Destination */
400 EXTRACT_HELPER(rD, 21, 5);
401 /* Source */
402 EXTRACT_HELPER(rS, 21, 5);
403 /* First operand */
404 EXTRACT_HELPER(rA, 16, 5);
405 /* Second operand */
406 EXTRACT_HELPER(rB, 11, 5);
407 /* Third operand */
408 EXTRACT_HELPER(rC, 6, 5);
409 /*** Get CRn ***/
410 EXTRACT_HELPER(crfD, 23, 3);
411 EXTRACT_HELPER(crfS, 18, 3);
412 EXTRACT_HELPER(crbD, 21, 5);
413 EXTRACT_HELPER(crbA, 16, 5);
414 EXTRACT_HELPER(crbB, 11, 5);
415 /* SPR / TBL */
416 EXTRACT_HELPER(_SPR, 11, 10);
417 static inline uint32_t SPR(uint32_t opcode)
418 {
419 uint32_t sprn = _SPR(opcode);
420
421 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
422 }
423 /*** Get constants ***/
424 /* 16 bits signed immediate value */
425 EXTRACT_SHELPER(SIMM, 0, 16);
426 /* 16 bits unsigned immediate value */
427 EXTRACT_HELPER(UIMM, 0, 16);
428 /* 5 bits signed immediate value */
429 EXTRACT_HELPER(SIMM5, 16, 5);
430 /* 5 bits signed immediate value */
431 EXTRACT_HELPER(UIMM5, 16, 5);
432 /* Bit count */
433 EXTRACT_HELPER(NB, 11, 5);
434 /* Shift count */
435 EXTRACT_HELPER(SH, 11, 5);
436 /* Vector shift count */
437 EXTRACT_HELPER(VSH, 6, 4);
438 /* Mask start */
439 EXTRACT_HELPER(MB, 6, 5);
440 /* Mask end */
441 EXTRACT_HELPER(ME, 1, 5);
442 /* Trap operand */
443 EXTRACT_HELPER(TO, 21, 5);
444
445 EXTRACT_HELPER(CRM, 12, 8);
446
447 #ifndef CONFIG_USER_ONLY
448 EXTRACT_HELPER(SR, 16, 4);
449 #endif
450
451 /* mtfsf/mtfsfi */
452 EXTRACT_HELPER(FPBF, 23, 3);
453 EXTRACT_HELPER(FPIMM, 12, 4);
454 EXTRACT_HELPER(FPL, 25, 1);
455 EXTRACT_HELPER(FPFLM, 17, 8);
456 EXTRACT_HELPER(FPW, 16, 1);
457
458 /*** Jump target decoding ***/
459 /* Immediate address */
460 static inline target_ulong LI(uint32_t opcode)
461 {
462 return (opcode >> 0) & 0x03FFFFFC;
463 }
464
465 static inline uint32_t BD(uint32_t opcode)
466 {
467 return (opcode >> 0) & 0xFFFC;
468 }
469
470 EXTRACT_HELPER(BO, 21, 5);
471 EXTRACT_HELPER(BI, 16, 5);
472 /* Absolute/relative address */
473 EXTRACT_HELPER(AA, 1, 1);
474 /* Link */
475 EXTRACT_HELPER(LK, 0, 1);
476
477 /* DFP Z22-form */
478 EXTRACT_HELPER(DCM, 10, 6)
479
480 /* DFP Z23-form */
481 EXTRACT_HELPER(RMC, 9, 2)
482
483 /* Create a mask between <start> and <end> bits */
484 static inline target_ulong MASK(uint32_t start, uint32_t end)
485 {
486 target_ulong ret;
487
488 #if defined(TARGET_PPC64)
489 if (likely(start == 0)) {
490 ret = UINT64_MAX << (63 - end);
491 } else if (likely(end == 63)) {
492 ret = UINT64_MAX >> start;
493 }
494 #else
495 if (likely(start == 0)) {
496 ret = UINT32_MAX << (31 - end);
497 } else if (likely(end == 31)) {
498 ret = UINT32_MAX >> start;
499 }
500 #endif
501 else {
502 ret = (((target_ulong)(-1ULL)) >> (start)) ^
503 (((target_ulong)(-1ULL) >> (end)) >> 1);
504 if (unlikely(start > end))
505 return ~ret;
506 }
507
508 return ret;
509 }
510
511 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
512 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
513 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
514 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
515 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
516 EXTRACT_HELPER(DM, 8, 2);
517 EXTRACT_HELPER(UIM, 16, 2);
518 EXTRACT_HELPER(SHW, 8, 2);
519 EXTRACT_HELPER(SP, 19, 2);
520 /*****************************************************************************/
521 /* PowerPC instructions table */
522
523 #if defined(DO_PPC_STATISTICS)
524 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
525 { \
526 .opc1 = op1, \
527 .opc2 = op2, \
528 .opc3 = op3, \
529 .pad = { 0, }, \
530 .handler = { \
531 .inval1 = invl, \
532 .type = _typ, \
533 .type2 = _typ2, \
534 .handler = &gen_##name, \
535 .oname = stringify(name), \
536 }, \
537 .oname = stringify(name), \
538 }
539 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
540 { \
541 .opc1 = op1, \
542 .opc2 = op2, \
543 .opc3 = op3, \
544 .pad = { 0, }, \
545 .handler = { \
546 .inval1 = invl1, \
547 .inval2 = invl2, \
548 .type = _typ, \
549 .type2 = _typ2, \
550 .handler = &gen_##name, \
551 .oname = stringify(name), \
552 }, \
553 .oname = stringify(name), \
554 }
555 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
556 { \
557 .opc1 = op1, \
558 .opc2 = op2, \
559 .opc3 = op3, \
560 .pad = { 0, }, \
561 .handler = { \
562 .inval1 = invl, \
563 .type = _typ, \
564 .type2 = _typ2, \
565 .handler = &gen_##name, \
566 .oname = onam, \
567 }, \
568 .oname = onam, \
569 }
570 #else
571 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
572 { \
573 .opc1 = op1, \
574 .opc2 = op2, \
575 .opc3 = op3, \
576 .pad = { 0, }, \
577 .handler = { \
578 .inval1 = invl, \
579 .type = _typ, \
580 .type2 = _typ2, \
581 .handler = &gen_##name, \
582 }, \
583 .oname = stringify(name), \
584 }
585 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
586 { \
587 .opc1 = op1, \
588 .opc2 = op2, \
589 .opc3 = op3, \
590 .pad = { 0, }, \
591 .handler = { \
592 .inval1 = invl1, \
593 .inval2 = invl2, \
594 .type = _typ, \
595 .type2 = _typ2, \
596 .handler = &gen_##name, \
597 }, \
598 .oname = stringify(name), \
599 }
600 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
601 { \
602 .opc1 = op1, \
603 .opc2 = op2, \
604 .opc3 = op3, \
605 .pad = { 0, }, \
606 .handler = { \
607 .inval1 = invl, \
608 .type = _typ, \
609 .type2 = _typ2, \
610 .handler = &gen_##name, \
611 }, \
612 .oname = onam, \
613 }
614 #endif
615
616 /* SPR load/store helpers */
617 static inline void gen_load_spr(TCGv t, int reg)
618 {
619 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
620 }
621
622 static inline void gen_store_spr(int reg, TCGv t)
623 {
624 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
625 }
626
627 /* Invalid instruction */
628 static void gen_invalid(DisasContext *ctx)
629 {
630 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
631 }
632
633 static opc_handler_t invalid_handler = {
634 .inval1 = 0xFFFFFFFF,
635 .inval2 = 0xFFFFFFFF,
636 .type = PPC_NONE,
637 .type2 = PPC_NONE,
638 .handler = gen_invalid,
639 };
640
641 /*** Integer comparison ***/
642
643 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
644 {
645 TCGv t0 = tcg_temp_new();
646 TCGv_i32 t1 = tcg_temp_new_i32();
647
648 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
649
650 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
651 tcg_gen_trunc_tl_i32(t1, t0);
652 tcg_gen_shli_i32(t1, t1, CRF_LT);
653 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
654
655 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
656 tcg_gen_trunc_tl_i32(t1, t0);
657 tcg_gen_shli_i32(t1, t1, CRF_GT);
658 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
659
660 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
661 tcg_gen_trunc_tl_i32(t1, t0);
662 tcg_gen_shli_i32(t1, t1, CRF_EQ);
663 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
664
665 tcg_temp_free(t0);
666 tcg_temp_free_i32(t1);
667 }
668
669 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
670 {
671 TCGv t0 = tcg_const_tl(arg1);
672 gen_op_cmp(arg0, t0, s, crf);
673 tcg_temp_free(t0);
674 }
675
676 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
677 {
678 TCGv t0, t1;
679 t0 = tcg_temp_new();
680 t1 = tcg_temp_new();
681 if (s) {
682 tcg_gen_ext32s_tl(t0, arg0);
683 tcg_gen_ext32s_tl(t1, arg1);
684 } else {
685 tcg_gen_ext32u_tl(t0, arg0);
686 tcg_gen_ext32u_tl(t1, arg1);
687 }
688 gen_op_cmp(t0, t1, s, crf);
689 tcg_temp_free(t1);
690 tcg_temp_free(t0);
691 }
692
693 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
694 {
695 TCGv t0 = tcg_const_tl(arg1);
696 gen_op_cmp32(arg0, t0, s, crf);
697 tcg_temp_free(t0);
698 }
699
700 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
701 {
702 if (NARROW_MODE(ctx)) {
703 gen_op_cmpi32(reg, 0, 1, 0);
704 } else {
705 gen_op_cmpi(reg, 0, 1, 0);
706 }
707 }
708
709 /* cmp */
710 static void gen_cmp(DisasContext *ctx)
711 {
712 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
713 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
714 1, crfD(ctx->opcode));
715 } else {
716 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
717 1, crfD(ctx->opcode));
718 }
719 }
720
721 /* cmpi */
722 static void gen_cmpi(DisasContext *ctx)
723 {
724 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
725 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
726 1, crfD(ctx->opcode));
727 } else {
728 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
729 1, crfD(ctx->opcode));
730 }
731 }
732
733 /* cmpl */
734 static void gen_cmpl(DisasContext *ctx)
735 {
736 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
737 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
738 0, crfD(ctx->opcode));
739 } else {
740 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
741 0, crfD(ctx->opcode));
742 }
743 }
744
745 /* cmpli */
746 static void gen_cmpli(DisasContext *ctx)
747 {
748 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
749 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
750 0, crfD(ctx->opcode));
751 } else {
752 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
753 0, crfD(ctx->opcode));
754 }
755 }
756
757 /* isel (PowerPC 2.03 specification) */
758 static void gen_isel(DisasContext *ctx)
759 {
760 uint32_t bi = rC(ctx->opcode);
761 uint32_t mask = 0x08 >> (bi & 0x03);
762 TCGv t0 = tcg_temp_new();
763 TCGv zr;
764
765 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
766 tcg_gen_andi_tl(t0, t0, mask);
767
768 zr = tcg_const_tl(0);
769 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
770 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
771 cpu_gpr[rB(ctx->opcode)]);
772 tcg_temp_free(zr);
773 tcg_temp_free(t0);
774 }
775
776 /* cmpb: PowerPC 2.05 specification */
777 static void gen_cmpb(DisasContext *ctx)
778 {
779 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
780 cpu_gpr[rB(ctx->opcode)]);
781 }
782
783 /*** Integer arithmetic ***/
784
785 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
786 TCGv arg1, TCGv arg2, int sub)
787 {
788 TCGv t0 = tcg_temp_new();
789
790 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
791 tcg_gen_xor_tl(t0, arg1, arg2);
792 if (sub) {
793 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
794 } else {
795 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
796 }
797 tcg_temp_free(t0);
798 if (NARROW_MODE(ctx)) {
799 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
800 }
801 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
802 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
803 }
804
805 /* Common add function */
806 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
807 TCGv arg2, bool add_ca, bool compute_ca,
808 bool compute_ov, bool compute_rc0)
809 {
810 TCGv t0 = ret;
811
812 if (compute_ca || compute_ov) {
813 t0 = tcg_temp_new();
814 }
815
816 if (compute_ca) {
817 if (NARROW_MODE(ctx)) {
818 /* Caution: a non-obvious corner case of the spec is that we
819 must produce the *entire* 64-bit addition, but produce the
820 carry into bit 32. */
821 TCGv t1 = tcg_temp_new();
822 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
823 tcg_gen_add_tl(t0, arg1, arg2);
824 if (add_ca) {
825 tcg_gen_add_tl(t0, t0, cpu_ca);
826 }
827 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
828 tcg_temp_free(t1);
829 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
830 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
831 } else {
832 TCGv zero = tcg_const_tl(0);
833 if (add_ca) {
834 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
835 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
836 } else {
837 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
838 }
839 tcg_temp_free(zero);
840 }
841 } else {
842 tcg_gen_add_tl(t0, arg1, arg2);
843 if (add_ca) {
844 tcg_gen_add_tl(t0, t0, cpu_ca);
845 }
846 }
847
848 if (compute_ov) {
849 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
850 }
851 if (unlikely(compute_rc0)) {
852 gen_set_Rc0(ctx, t0);
853 }
854
855 if (!TCGV_EQUAL(t0, ret)) {
856 tcg_gen_mov_tl(ret, t0);
857 tcg_temp_free(t0);
858 }
859 }
860 /* Add functions with two operands */
861 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
862 static void glue(gen_, name)(DisasContext *ctx) \
863 { \
864 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
865 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
866 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
867 }
868 /* Add functions with one operand and one immediate */
869 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
870 add_ca, compute_ca, compute_ov) \
871 static void glue(gen_, name)(DisasContext *ctx) \
872 { \
873 TCGv t0 = tcg_const_tl(const_val); \
874 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
875 cpu_gpr[rA(ctx->opcode)], t0, \
876 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
877 tcg_temp_free(t0); \
878 }
879
880 /* add add. addo addo. */
881 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
882 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
883 /* addc addc. addco addco. */
884 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
885 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
886 /* adde adde. addeo addeo. */
887 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
888 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
889 /* addme addme. addmeo addmeo. */
890 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
891 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
892 /* addze addze. addzeo addzeo.*/
893 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
894 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
895 /* addi */
896 static void gen_addi(DisasContext *ctx)
897 {
898 target_long simm = SIMM(ctx->opcode);
899
900 if (rA(ctx->opcode) == 0) {
901 /* li case */
902 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
903 } else {
904 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
905 cpu_gpr[rA(ctx->opcode)], simm);
906 }
907 }
908 /* addic addic.*/
909 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
910 {
911 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
912 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
913 c, 0, 1, 0, compute_rc0);
914 tcg_temp_free(c);
915 }
916
917 static void gen_addic(DisasContext *ctx)
918 {
919 gen_op_addic(ctx, 0);
920 }
921
922 static void gen_addic_(DisasContext *ctx)
923 {
924 gen_op_addic(ctx, 1);
925 }
926
927 /* addis */
928 static void gen_addis(DisasContext *ctx)
929 {
930 target_long simm = SIMM(ctx->opcode);
931
932 if (rA(ctx->opcode) == 0) {
933 /* lis case */
934 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
935 } else {
936 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
937 cpu_gpr[rA(ctx->opcode)], simm << 16);
938 }
939 }
940
941 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
942 TCGv arg2, int sign, int compute_ov)
943 {
944 TCGLabel *l1 = gen_new_label();
945 TCGLabel *l2 = gen_new_label();
946 TCGv_i32 t0 = tcg_temp_local_new_i32();
947 TCGv_i32 t1 = tcg_temp_local_new_i32();
948
949 tcg_gen_trunc_tl_i32(t0, arg1);
950 tcg_gen_trunc_tl_i32(t1, arg2);
951 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
952 if (sign) {
953 TCGLabel *l3 = gen_new_label();
954 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
955 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
956 gen_set_label(l3);
957 tcg_gen_div_i32(t0, t0, t1);
958 } else {
959 tcg_gen_divu_i32(t0, t0, t1);
960 }
961 if (compute_ov) {
962 tcg_gen_movi_tl(cpu_ov, 0);
963 }
964 tcg_gen_br(l2);
965 gen_set_label(l1);
966 if (sign) {
967 tcg_gen_sari_i32(t0, t0, 31);
968 } else {
969 tcg_gen_movi_i32(t0, 0);
970 }
971 if (compute_ov) {
972 tcg_gen_movi_tl(cpu_ov, 1);
973 tcg_gen_movi_tl(cpu_so, 1);
974 }
975 gen_set_label(l2);
976 tcg_gen_extu_i32_tl(ret, t0);
977 tcg_temp_free_i32(t0);
978 tcg_temp_free_i32(t1);
979 if (unlikely(Rc(ctx->opcode) != 0))
980 gen_set_Rc0(ctx, ret);
981 }
982 /* Div functions */
983 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
984 static void glue(gen_, name)(DisasContext *ctx) \
985 { \
986 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
987 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
988 sign, compute_ov); \
989 }
990 /* divwu divwu. divwuo divwuo. */
991 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
992 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
993 /* divw divw. divwo divwo. */
994 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
995 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
996
997 /* div[wd]eu[o][.] */
998 #define GEN_DIVE(name, hlpr, compute_ov) \
999 static void gen_##name(DisasContext *ctx) \
1000 { \
1001 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1002 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1003 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1004 tcg_temp_free_i32(t0); \
1005 if (unlikely(Rc(ctx->opcode) != 0)) { \
1006 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1007 } \
1008 }
1009
1010 GEN_DIVE(divweu, divweu, 0);
1011 GEN_DIVE(divweuo, divweu, 1);
1012 GEN_DIVE(divwe, divwe, 0);
1013 GEN_DIVE(divweo, divwe, 1);
1014
1015 #if defined(TARGET_PPC64)
1016 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1017 TCGv arg2, int sign, int compute_ov)
1018 {
1019 TCGLabel *l1 = gen_new_label();
1020 TCGLabel *l2 = gen_new_label();
1021
1022 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1023 if (sign) {
1024 TCGLabel *l3 = gen_new_label();
1025 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1026 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1027 gen_set_label(l3);
1028 tcg_gen_div_i64(ret, arg1, arg2);
1029 } else {
1030 tcg_gen_divu_i64(ret, arg1, arg2);
1031 }
1032 if (compute_ov) {
1033 tcg_gen_movi_tl(cpu_ov, 0);
1034 }
1035 tcg_gen_br(l2);
1036 gen_set_label(l1);
1037 if (sign) {
1038 tcg_gen_sari_i64(ret, arg1, 63);
1039 } else {
1040 tcg_gen_movi_i64(ret, 0);
1041 }
1042 if (compute_ov) {
1043 tcg_gen_movi_tl(cpu_ov, 1);
1044 tcg_gen_movi_tl(cpu_so, 1);
1045 }
1046 gen_set_label(l2);
1047 if (unlikely(Rc(ctx->opcode) != 0))
1048 gen_set_Rc0(ctx, ret);
1049 }
1050 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1051 static void glue(gen_, name)(DisasContext *ctx) \
1052 { \
1053 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1054 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1055 sign, compute_ov); \
1056 }
1057 /* divwu divwu. divwuo divwuo. */
1058 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1059 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1060 /* divw divw. divwo divwo. */
1061 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1062 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1063
1064 GEN_DIVE(divdeu, divdeu, 0);
1065 GEN_DIVE(divdeuo, divdeu, 1);
1066 GEN_DIVE(divde, divde, 0);
1067 GEN_DIVE(divdeo, divde, 1);
1068 #endif
1069
1070 /* mulhw mulhw. */
1071 static void gen_mulhw(DisasContext *ctx)
1072 {
1073 TCGv_i32 t0 = tcg_temp_new_i32();
1074 TCGv_i32 t1 = tcg_temp_new_i32();
1075
1076 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1077 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1078 tcg_gen_muls2_i32(t0, t1, t0, t1);
1079 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1080 tcg_temp_free_i32(t0);
1081 tcg_temp_free_i32(t1);
1082 if (unlikely(Rc(ctx->opcode) != 0))
1083 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1084 }
1085
1086 /* mulhwu mulhwu. */
1087 static void gen_mulhwu(DisasContext *ctx)
1088 {
1089 TCGv_i32 t0 = tcg_temp_new_i32();
1090 TCGv_i32 t1 = tcg_temp_new_i32();
1091
1092 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1093 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1094 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1095 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1096 tcg_temp_free_i32(t0);
1097 tcg_temp_free_i32(t1);
1098 if (unlikely(Rc(ctx->opcode) != 0))
1099 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1100 }
1101
1102 /* mullw mullw. */
1103 static void gen_mullw(DisasContext *ctx)
1104 {
1105 #if defined(TARGET_PPC64)
1106 TCGv_i64 t0, t1;
1107 t0 = tcg_temp_new_i64();
1108 t1 = tcg_temp_new_i64();
1109 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1110 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1111 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1112 tcg_temp_free(t0);
1113 tcg_temp_free(t1);
1114 #else
1115 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1116 cpu_gpr[rB(ctx->opcode)]);
1117 #endif
1118 if (unlikely(Rc(ctx->opcode) != 0))
1119 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1120 }
1121
1122 /* mullwo mullwo. */
1123 static void gen_mullwo(DisasContext *ctx)
1124 {
1125 TCGv_i32 t0 = tcg_temp_new_i32();
1126 TCGv_i32 t1 = tcg_temp_new_i32();
1127
1128 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1129 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1130 tcg_gen_muls2_i32(t0, t1, t0, t1);
1131 #if defined(TARGET_PPC64)
1132 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1133 #else
1134 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1135 #endif
1136
1137 tcg_gen_sari_i32(t0, t0, 31);
1138 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1139 tcg_gen_extu_i32_tl(cpu_ov, t0);
1140 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1141
1142 tcg_temp_free_i32(t0);
1143 tcg_temp_free_i32(t1);
1144 if (unlikely(Rc(ctx->opcode) != 0))
1145 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1146 }
1147
1148 /* mulli */
1149 static void gen_mulli(DisasContext *ctx)
1150 {
1151 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1152 SIMM(ctx->opcode));
1153 }
1154
1155 #if defined(TARGET_PPC64)
1156 /* mulhd mulhd. */
1157 static void gen_mulhd(DisasContext *ctx)
1158 {
1159 TCGv lo = tcg_temp_new();
1160 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1161 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1162 tcg_temp_free(lo);
1163 if (unlikely(Rc(ctx->opcode) != 0)) {
1164 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1165 }
1166 }
1167
1168 /* mulhdu mulhdu. */
1169 static void gen_mulhdu(DisasContext *ctx)
1170 {
1171 TCGv lo = tcg_temp_new();
1172 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1173 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1174 tcg_temp_free(lo);
1175 if (unlikely(Rc(ctx->opcode) != 0)) {
1176 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1177 }
1178 }
1179
1180 /* mulld mulld. */
1181 static void gen_mulld(DisasContext *ctx)
1182 {
1183 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1184 cpu_gpr[rB(ctx->opcode)]);
1185 if (unlikely(Rc(ctx->opcode) != 0))
1186 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1187 }
1188
1189 /* mulldo mulldo. */
1190 static void gen_mulldo(DisasContext *ctx)
1191 {
1192 TCGv_i64 t0 = tcg_temp_new_i64();
1193 TCGv_i64 t1 = tcg_temp_new_i64();
1194
1195 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1196 cpu_gpr[rB(ctx->opcode)]);
1197 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1198
1199 tcg_gen_sari_i64(t0, t0, 63);
1200 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1201 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1202
1203 tcg_temp_free_i64(t0);
1204 tcg_temp_free_i64(t1);
1205
1206 if (unlikely(Rc(ctx->opcode) != 0)) {
1207 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1208 }
1209 }
1210 #endif
1211
1212 /* Common subf function */
1213 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1214 TCGv arg2, bool add_ca, bool compute_ca,
1215 bool compute_ov, bool compute_rc0)
1216 {
1217 TCGv t0 = ret;
1218
1219 if (compute_ca || compute_ov) {
1220 t0 = tcg_temp_new();
1221 }
1222
1223 if (compute_ca) {
1224 /* dest = ~arg1 + arg2 [+ ca]. */
1225 if (NARROW_MODE(ctx)) {
1226 /* Caution: a non-obvious corner case of the spec is that we
1227 must produce the *entire* 64-bit addition, but produce the
1228 carry into bit 32. */
1229 TCGv inv1 = tcg_temp_new();
1230 TCGv t1 = tcg_temp_new();
1231 tcg_gen_not_tl(inv1, arg1);
1232 if (add_ca) {
1233 tcg_gen_add_tl(t0, arg2, cpu_ca);
1234 } else {
1235 tcg_gen_addi_tl(t0, arg2, 1);
1236 }
1237 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1238 tcg_gen_add_tl(t0, t0, inv1);
1239 tcg_temp_free(inv1);
1240 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1241 tcg_temp_free(t1);
1242 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1243 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1244 } else if (add_ca) {
1245 TCGv zero, inv1 = tcg_temp_new();
1246 tcg_gen_not_tl(inv1, arg1);
1247 zero = tcg_const_tl(0);
1248 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1249 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1250 tcg_temp_free(zero);
1251 tcg_temp_free(inv1);
1252 } else {
1253 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1254 tcg_gen_sub_tl(t0, arg2, arg1);
1255 }
1256 } else if (add_ca) {
1257 /* Since we're ignoring carry-out, we can simplify the
1258 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1259 tcg_gen_sub_tl(t0, arg2, arg1);
1260 tcg_gen_add_tl(t0, t0, cpu_ca);
1261 tcg_gen_subi_tl(t0, t0, 1);
1262 } else {
1263 tcg_gen_sub_tl(t0, arg2, arg1);
1264 }
1265
1266 if (compute_ov) {
1267 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1268 }
1269 if (unlikely(compute_rc0)) {
1270 gen_set_Rc0(ctx, t0);
1271 }
1272
1273 if (!TCGV_EQUAL(t0, ret)) {
1274 tcg_gen_mov_tl(ret, t0);
1275 tcg_temp_free(t0);
1276 }
1277 }
1278 /* Sub functions with Two operands functions */
1279 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1280 static void glue(gen_, name)(DisasContext *ctx) \
1281 { \
1282 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1283 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1284 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1285 }
1286 /* Sub functions with one operand and one immediate */
1287 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1288 add_ca, compute_ca, compute_ov) \
1289 static void glue(gen_, name)(DisasContext *ctx) \
1290 { \
1291 TCGv t0 = tcg_const_tl(const_val); \
1292 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1293 cpu_gpr[rA(ctx->opcode)], t0, \
1294 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1295 tcg_temp_free(t0); \
1296 }
1297 /* subf subf. subfo subfo. */
1298 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1299 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1300 /* subfc subfc. subfco subfco. */
1301 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1302 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1303 /* subfe subfe. subfeo subfo. */
1304 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1305 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1306 /* subfme subfme. subfmeo subfmeo. */
1307 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1308 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1309 /* subfze subfze. subfzeo subfzeo.*/
1310 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1311 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1312
1313 /* subfic */
1314 static void gen_subfic(DisasContext *ctx)
1315 {
1316 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1317 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1318 c, 0, 1, 0, 0);
1319 tcg_temp_free(c);
1320 }
1321
1322 /* neg neg. nego nego. */
1323 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1324 {
1325 TCGv zero = tcg_const_tl(0);
1326 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1327 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1328 tcg_temp_free(zero);
1329 }
1330
1331 static void gen_neg(DisasContext *ctx)
1332 {
1333 gen_op_arith_neg(ctx, 0);
1334 }
1335
1336 static void gen_nego(DisasContext *ctx)
1337 {
1338 gen_op_arith_neg(ctx, 1);
1339 }
1340
1341 /*** Integer logical ***/
1342 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1343 static void glue(gen_, name)(DisasContext *ctx) \
1344 { \
1345 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1346 cpu_gpr[rB(ctx->opcode)]); \
1347 if (unlikely(Rc(ctx->opcode) != 0)) \
1348 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1349 }
1350
1351 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1352 static void glue(gen_, name)(DisasContext *ctx) \
1353 { \
1354 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1355 if (unlikely(Rc(ctx->opcode) != 0)) \
1356 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1357 }
1358
1359 /* and & and. */
1360 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1361 /* andc & andc. */
1362 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1363
1364 /* andi. */
1365 static void gen_andi_(DisasContext *ctx)
1366 {
1367 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1368 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1369 }
1370
1371 /* andis. */
1372 static void gen_andis_(DisasContext *ctx)
1373 {
1374 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1375 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1376 }
1377
1378 /* cntlzw */
1379 static void gen_cntlzw(DisasContext *ctx)
1380 {
1381 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1382 if (unlikely(Rc(ctx->opcode) != 0))
1383 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1384 }
1385 /* eqv & eqv. */
1386 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1387 /* extsb & extsb. */
1388 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1389 /* extsh & extsh. */
1390 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1391 /* nand & nand. */
1392 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1393 /* nor & nor. */
1394 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1395
1396 #if defined(TARGET_PPC64)
1397 static void gen_pause(DisasContext *ctx)
1398 {
1399 TCGv_i32 t0 = tcg_const_i32(0);
1400 tcg_gen_st_i32(t0, cpu_env,
1401 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
1402 tcg_temp_free_i32(t0);
1403
1404 /* Stop translation, this gives other CPUs a chance to run */
1405 gen_exception_err(ctx, EXCP_HLT, 1);
1406 }
1407 #endif /* defined(TARGET_PPC64) */
1408
1409 /* or & or. */
1410 static void gen_or(DisasContext *ctx)
1411 {
1412 int rs, ra, rb;
1413
1414 rs = rS(ctx->opcode);
1415 ra = rA(ctx->opcode);
1416 rb = rB(ctx->opcode);
1417 /* Optimisation for mr. ri case */
1418 if (rs != ra || rs != rb) {
1419 if (rs != rb)
1420 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1421 else
1422 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1423 if (unlikely(Rc(ctx->opcode) != 0))
1424 gen_set_Rc0(ctx, cpu_gpr[ra]);
1425 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1426 gen_set_Rc0(ctx, cpu_gpr[rs]);
1427 #if defined(TARGET_PPC64)
1428 } else {
1429 int prio = 0;
1430
1431 switch (rs) {
1432 case 1:
1433 /* Set process priority to low */
1434 prio = 2;
1435 break;
1436 case 6:
1437 /* Set process priority to medium-low */
1438 prio = 3;
1439 break;
1440 case 2:
1441 /* Set process priority to normal */
1442 prio = 4;
1443 break;
1444 #if !defined(CONFIG_USER_ONLY)
1445 case 31:
1446 if (!ctx->pr) {
1447 /* Set process priority to very low */
1448 prio = 1;
1449 }
1450 break;
1451 case 5:
1452 if (!ctx->pr) {
1453 /* Set process priority to medium-hight */
1454 prio = 5;
1455 }
1456 break;
1457 case 3:
1458 if (!ctx->pr) {
1459 /* Set process priority to high */
1460 prio = 6;
1461 }
1462 break;
1463 case 7:
1464 if (ctx->hv && !ctx->pr) {
1465 /* Set process priority to very high */
1466 prio = 7;
1467 }
1468 break;
1469 #endif
1470 default:
1471 /* nop */
1472 break;
1473 }
1474 if (prio) {
1475 TCGv t0 = tcg_temp_new();
1476 gen_load_spr(t0, SPR_PPR);
1477 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1478 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1479 gen_store_spr(SPR_PPR, t0);
1480 tcg_temp_free(t0);
1481 /* Pause us out of TCG otherwise spin loops with smt_low
1482 * eat too much CPU and the kernel hangs
1483 */
1484 gen_pause(ctx);
1485 }
1486 #endif
1487 }
1488 }
1489 /* orc & orc. */
1490 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1491
1492 /* xor & xor. */
1493 static void gen_xor(DisasContext *ctx)
1494 {
1495 /* Optimisation for "set to zero" case */
1496 if (rS(ctx->opcode) != rB(ctx->opcode))
1497 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1498 else
1499 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1500 if (unlikely(Rc(ctx->opcode) != 0))
1501 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1502 }
1503
1504 /* ori */
1505 static void gen_ori(DisasContext *ctx)
1506 {
1507 target_ulong uimm = UIMM(ctx->opcode);
1508
1509 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1510 return;
1511 }
1512 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1513 }
1514
1515 /* oris */
1516 static void gen_oris(DisasContext *ctx)
1517 {
1518 target_ulong uimm = UIMM(ctx->opcode);
1519
1520 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1521 /* NOP */
1522 return;
1523 }
1524 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1525 }
1526
1527 /* xori */
1528 static void gen_xori(DisasContext *ctx)
1529 {
1530 target_ulong uimm = UIMM(ctx->opcode);
1531
1532 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1533 /* NOP */
1534 return;
1535 }
1536 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1537 }
1538
1539 /* xoris */
1540 static void gen_xoris(DisasContext *ctx)
1541 {
1542 target_ulong uimm = UIMM(ctx->opcode);
1543
1544 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1545 /* NOP */
1546 return;
1547 }
1548 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1549 }
1550
1551 /* popcntb : PowerPC 2.03 specification */
1552 static void gen_popcntb(DisasContext *ctx)
1553 {
1554 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1555 }
1556
1557 static void gen_popcntw(DisasContext *ctx)
1558 {
1559 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1560 }
1561
1562 #if defined(TARGET_PPC64)
1563 /* popcntd: PowerPC 2.06 specification */
1564 static void gen_popcntd(DisasContext *ctx)
1565 {
1566 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1567 }
1568 #endif
1569
1570 /* prtyw: PowerPC 2.05 specification */
1571 static void gen_prtyw(DisasContext *ctx)
1572 {
1573 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1574 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1575 TCGv t0 = tcg_temp_new();
1576 tcg_gen_shri_tl(t0, rs, 16);
1577 tcg_gen_xor_tl(ra, rs, t0);
1578 tcg_gen_shri_tl(t0, ra, 8);
1579 tcg_gen_xor_tl(ra, ra, t0);
1580 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1581 tcg_temp_free(t0);
1582 }
1583
1584 #if defined(TARGET_PPC64)
1585 /* prtyd: PowerPC 2.05 specification */
1586 static void gen_prtyd(DisasContext *ctx)
1587 {
1588 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1589 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1590 TCGv t0 = tcg_temp_new();
1591 tcg_gen_shri_tl(t0, rs, 32);
1592 tcg_gen_xor_tl(ra, rs, t0);
1593 tcg_gen_shri_tl(t0, ra, 16);
1594 tcg_gen_xor_tl(ra, ra, t0);
1595 tcg_gen_shri_tl(t0, ra, 8);
1596 tcg_gen_xor_tl(ra, ra, t0);
1597 tcg_gen_andi_tl(ra, ra, 1);
1598 tcg_temp_free(t0);
1599 }
1600 #endif
1601
1602 #if defined(TARGET_PPC64)
1603 /* bpermd */
1604 static void gen_bpermd(DisasContext *ctx)
1605 {
1606 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1607 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1608 }
1609 #endif
1610
1611 #if defined(TARGET_PPC64)
1612 /* extsw & extsw. */
1613 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1614
1615 /* cntlzd */
1616 static void gen_cntlzd(DisasContext *ctx)
1617 {
1618 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1619 if (unlikely(Rc(ctx->opcode) != 0))
1620 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1621 }
1622 #endif
1623
1624 /*** Integer rotate ***/
1625
1626 /* rlwimi & rlwimi. */
1627 static void gen_rlwimi(DisasContext *ctx)
1628 {
1629 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1630 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1631 uint32_t sh = SH(ctx->opcode);
1632 uint32_t mb = MB(ctx->opcode);
1633 uint32_t me = ME(ctx->opcode);
1634
1635 if (sh == (31-me) && mb <= me) {
1636 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1637 } else {
1638 target_ulong mask;
1639 TCGv_i32 t0;
1640 TCGv t1;
1641
1642 #if defined(TARGET_PPC64)
1643 mb += 32;
1644 me += 32;
1645 #endif
1646 mask = MASK(mb, me);
1647
1648 t0 = tcg_temp_new_i32();
1649 t1 = tcg_temp_new();
1650 tcg_gen_trunc_tl_i32(t0, t_rs);
1651 tcg_gen_rotli_i32(t0, t0, sh);
1652 tcg_gen_extu_i32_tl(t1, t0);
1653 tcg_temp_free_i32(t0);
1654
1655 tcg_gen_andi_tl(t1, t1, mask);
1656 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1657 tcg_gen_or_tl(t_ra, t_ra, t1);
1658 tcg_temp_free(t1);
1659 }
1660 if (unlikely(Rc(ctx->opcode) != 0)) {
1661 gen_set_Rc0(ctx, t_ra);
1662 }
1663 }
1664
1665 /* rlwinm & rlwinm. */
1666 static void gen_rlwinm(DisasContext *ctx)
1667 {
1668 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1669 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1670 uint32_t sh = SH(ctx->opcode);
1671 uint32_t mb = MB(ctx->opcode);
1672 uint32_t me = ME(ctx->opcode);
1673
1674 if (mb == 0 && me == (31 - sh)) {
1675 tcg_gen_shli_tl(t_ra, t_rs, sh);
1676 tcg_gen_ext32u_tl(t_ra, t_ra);
1677 } else if (sh != 0 && me == 31 && sh == (32 - mb)) {
1678 tcg_gen_ext32u_tl(t_ra, t_rs);
1679 tcg_gen_shri_tl(t_ra, t_ra, mb);
1680 } else {
1681 #if defined(TARGET_PPC64)
1682 mb += 32;
1683 me += 32;
1684 #endif
1685 if (sh == 0) {
1686 tcg_gen_andi_tl(t_ra, t_rs, MASK(mb, me));
1687 } else {
1688 TCGv_i32 t0 = tcg_temp_new_i32();
1689
1690 tcg_gen_trunc_tl_i32(t0, t_rs);
1691 tcg_gen_rotli_i32(t0, t0, sh);
1692 tcg_gen_andi_i32(t0, t0, MASK(mb, me));
1693 tcg_gen_extu_i32_tl(t_ra, t0);
1694 tcg_temp_free_i32(t0);
1695 }
1696 }
1697 if (unlikely(Rc(ctx->opcode) != 0)) {
1698 gen_set_Rc0(ctx, t_ra);
1699 }
1700 }
1701
1702 /* rlwnm & rlwnm. */
1703 static void gen_rlwnm(DisasContext *ctx)
1704 {
1705 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1706 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1707 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1708 uint32_t mb = MB(ctx->opcode);
1709 uint32_t me = ME(ctx->opcode);
1710 TCGv_i32 t0, t1;
1711
1712 #if defined(TARGET_PPC64)
1713 mb += 32;
1714 me += 32;
1715 #endif
1716
1717 t0 = tcg_temp_new_i32();
1718 t1 = tcg_temp_new_i32();
1719 tcg_gen_trunc_tl_i32(t0, t_rb);
1720 tcg_gen_trunc_tl_i32(t1, t_rs);
1721 tcg_gen_andi_i32(t0, t0, 0x1f);
1722 tcg_gen_rotl_i32(t1, t1, t0);
1723 tcg_temp_free_i32(t0);
1724
1725 tcg_gen_andi_i32(t1, t1, MASK(mb, me));
1726 tcg_gen_extu_i32_tl(t_ra, t1);
1727 tcg_temp_free_i32(t1);
1728
1729 if (unlikely(Rc(ctx->opcode) != 0)) {
1730 gen_set_Rc0(ctx, t_ra);
1731 }
1732 }
1733
1734 #if defined(TARGET_PPC64)
1735 #define GEN_PPC64_R2(name, opc1, opc2) \
1736 static void glue(gen_, name##0)(DisasContext *ctx) \
1737 { \
1738 gen_##name(ctx, 0); \
1739 } \
1740 \
1741 static void glue(gen_, name##1)(DisasContext *ctx) \
1742 { \
1743 gen_##name(ctx, 1); \
1744 }
1745 #define GEN_PPC64_R4(name, opc1, opc2) \
1746 static void glue(gen_, name##0)(DisasContext *ctx) \
1747 { \
1748 gen_##name(ctx, 0, 0); \
1749 } \
1750 \
1751 static void glue(gen_, name##1)(DisasContext *ctx) \
1752 { \
1753 gen_##name(ctx, 0, 1); \
1754 } \
1755 \
1756 static void glue(gen_, name##2)(DisasContext *ctx) \
1757 { \
1758 gen_##name(ctx, 1, 0); \
1759 } \
1760 \
1761 static void glue(gen_, name##3)(DisasContext *ctx) \
1762 { \
1763 gen_##name(ctx, 1, 1); \
1764 }
1765
1766 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
1767 {
1768 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1769 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1770
1771 if (sh != 0 && mb == 0 && me == (63 - sh)) {
1772 tcg_gen_shli_tl(t_ra, t_rs, sh);
1773 } else if (sh != 0 && me == 63 && sh == (64 - mb)) {
1774 tcg_gen_shri_tl(t_ra, t_rs, mb);
1775 } else {
1776 tcg_gen_rotli_tl(t_ra, t_rs, sh);
1777 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
1778 }
1779 if (unlikely(Rc(ctx->opcode) != 0)) {
1780 gen_set_Rc0(ctx, t_ra);
1781 }
1782 }
1783
1784 /* rldicl - rldicl. */
1785 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1786 {
1787 uint32_t sh, mb;
1788
1789 sh = SH(ctx->opcode) | (shn << 5);
1790 mb = MB(ctx->opcode) | (mbn << 5);
1791 gen_rldinm(ctx, mb, 63, sh);
1792 }
1793 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1794
1795 /* rldicr - rldicr. */
1796 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1797 {
1798 uint32_t sh, me;
1799
1800 sh = SH(ctx->opcode) | (shn << 5);
1801 me = MB(ctx->opcode) | (men << 5);
1802 gen_rldinm(ctx, 0, me, sh);
1803 }
1804 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1805
1806 /* rldic - rldic. */
1807 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1808 {
1809 uint32_t sh, mb;
1810
1811 sh = SH(ctx->opcode) | (shn << 5);
1812 mb = MB(ctx->opcode) | (mbn << 5);
1813 gen_rldinm(ctx, mb, 63 - sh, sh);
1814 }
1815 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1816
1817 static void gen_rldnm(DisasContext *ctx, int mb, int me)
1818 {
1819 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1820 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1821 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1822 TCGv t0;
1823
1824 t0 = tcg_temp_new();
1825 tcg_gen_andi_tl(t0, t_rb, 0x3f);
1826 tcg_gen_rotl_tl(t_ra, t_rs, t0);
1827 tcg_temp_free(t0);
1828
1829 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
1830 if (unlikely(Rc(ctx->opcode) != 0)) {
1831 gen_set_Rc0(ctx, t_ra);
1832 }
1833 }
1834
1835 /* rldcl - rldcl. */
1836 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1837 {
1838 uint32_t mb;
1839
1840 mb = MB(ctx->opcode) | (mbn << 5);
1841 gen_rldnm(ctx, mb, 63);
1842 }
1843 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1844
1845 /* rldcr - rldcr. */
1846 static inline void gen_rldcr(DisasContext *ctx, int men)
1847 {
1848 uint32_t me;
1849
1850 me = MB(ctx->opcode) | (men << 5);
1851 gen_rldnm(ctx, 0, me);
1852 }
1853 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1854
1855 /* rldimi - rldimi. */
1856 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1857 {
1858 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1859 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1860 uint32_t sh = SH(ctx->opcode) | (shn << 5);
1861 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
1862 uint32_t me = 63 - sh;
1863
1864 if (mb <= me) {
1865 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1866 } else {
1867 target_ulong mask = MASK(mb, me);
1868 TCGv t1 = tcg_temp_new();
1869
1870 tcg_gen_rotli_tl(t1, t_rs, sh);
1871 tcg_gen_andi_tl(t1, t1, mask);
1872 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1873 tcg_gen_or_tl(t_ra, t_ra, t1);
1874 tcg_temp_free(t1);
1875 }
1876 if (unlikely(Rc(ctx->opcode) != 0)) {
1877 gen_set_Rc0(ctx, t_ra);
1878 }
1879 }
1880 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1881 #endif
1882
1883 /*** Integer shift ***/
1884
1885 /* slw & slw. */
1886 static void gen_slw(DisasContext *ctx)
1887 {
1888 TCGv t0, t1;
1889
1890 t0 = tcg_temp_new();
1891 /* AND rS with a mask that is 0 when rB >= 0x20 */
1892 #if defined(TARGET_PPC64)
1893 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1894 tcg_gen_sari_tl(t0, t0, 0x3f);
1895 #else
1896 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1897 tcg_gen_sari_tl(t0, t0, 0x1f);
1898 #endif
1899 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1900 t1 = tcg_temp_new();
1901 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1902 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1903 tcg_temp_free(t1);
1904 tcg_temp_free(t0);
1905 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1906 if (unlikely(Rc(ctx->opcode) != 0))
1907 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1908 }
1909
1910 /* sraw & sraw. */
1911 static void gen_sraw(DisasContext *ctx)
1912 {
1913 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1914 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1915 if (unlikely(Rc(ctx->opcode) != 0))
1916 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1917 }
1918
1919 /* srawi & srawi. */
1920 static void gen_srawi(DisasContext *ctx)
1921 {
1922 int sh = SH(ctx->opcode);
1923 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1924 TCGv src = cpu_gpr[rS(ctx->opcode)];
1925 if (sh == 0) {
1926 tcg_gen_ext32s_tl(dst, src);
1927 tcg_gen_movi_tl(cpu_ca, 0);
1928 } else {
1929 TCGv t0;
1930 tcg_gen_ext32s_tl(dst, src);
1931 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1932 t0 = tcg_temp_new();
1933 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1934 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1935 tcg_temp_free(t0);
1936 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1937 tcg_gen_sari_tl(dst, dst, sh);
1938 }
1939 if (unlikely(Rc(ctx->opcode) != 0)) {
1940 gen_set_Rc0(ctx, dst);
1941 }
1942 }
1943
1944 /* srw & srw. */
1945 static void gen_srw(DisasContext *ctx)
1946 {
1947 TCGv t0, t1;
1948
1949 t0 = tcg_temp_new();
1950 /* AND rS with a mask that is 0 when rB >= 0x20 */
1951 #if defined(TARGET_PPC64)
1952 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1953 tcg_gen_sari_tl(t0, t0, 0x3f);
1954 #else
1955 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1956 tcg_gen_sari_tl(t0, t0, 0x1f);
1957 #endif
1958 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1959 tcg_gen_ext32u_tl(t0, t0);
1960 t1 = tcg_temp_new();
1961 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1962 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1963 tcg_temp_free(t1);
1964 tcg_temp_free(t0);
1965 if (unlikely(Rc(ctx->opcode) != 0))
1966 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1967 }
1968
1969 #if defined(TARGET_PPC64)
1970 /* sld & sld. */
1971 static void gen_sld(DisasContext *ctx)
1972 {
1973 TCGv t0, t1;
1974
1975 t0 = tcg_temp_new();
1976 /* AND rS with a mask that is 0 when rB >= 0x40 */
1977 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1978 tcg_gen_sari_tl(t0, t0, 0x3f);
1979 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1980 t1 = tcg_temp_new();
1981 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1982 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1983 tcg_temp_free(t1);
1984 tcg_temp_free(t0);
1985 if (unlikely(Rc(ctx->opcode) != 0))
1986 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1987 }
1988
1989 /* srad & srad. */
1990 static void gen_srad(DisasContext *ctx)
1991 {
1992 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
1993 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1994 if (unlikely(Rc(ctx->opcode) != 0))
1995 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1996 }
1997 /* sradi & sradi. */
1998 static inline void gen_sradi(DisasContext *ctx, int n)
1999 {
2000 int sh = SH(ctx->opcode) + (n << 5);
2001 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2002 TCGv src = cpu_gpr[rS(ctx->opcode)];
2003 if (sh == 0) {
2004 tcg_gen_mov_tl(dst, src);
2005 tcg_gen_movi_tl(cpu_ca, 0);
2006 } else {
2007 TCGv t0;
2008 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2009 t0 = tcg_temp_new();
2010 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2011 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2012 tcg_temp_free(t0);
2013 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2014 tcg_gen_sari_tl(dst, src, sh);
2015 }
2016 if (unlikely(Rc(ctx->opcode) != 0)) {
2017 gen_set_Rc0(ctx, dst);
2018 }
2019 }
2020
2021 static void gen_sradi0(DisasContext *ctx)
2022 {
2023 gen_sradi(ctx, 0);
2024 }
2025
2026 static void gen_sradi1(DisasContext *ctx)
2027 {
2028 gen_sradi(ctx, 1);
2029 }
2030
2031 /* srd & srd. */
2032 static void gen_srd(DisasContext *ctx)
2033 {
2034 TCGv t0, t1;
2035
2036 t0 = tcg_temp_new();
2037 /* AND rS with a mask that is 0 when rB >= 0x40 */
2038 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2039 tcg_gen_sari_tl(t0, t0, 0x3f);
2040 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2041 t1 = tcg_temp_new();
2042 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2043 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2044 tcg_temp_free(t1);
2045 tcg_temp_free(t0);
2046 if (unlikely(Rc(ctx->opcode) != 0))
2047 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2048 }
2049 #endif
2050
2051 #if defined(TARGET_PPC64)
2052 static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2053 {
2054 TCGv_i32 tmp = tcg_temp_new_i32();
2055 tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
2056 tcg_gen_shri_i32(cpu_crf[1], tmp, 28);
2057 tcg_temp_free_i32(tmp);
2058 }
2059 #else
2060 static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2061 {
2062 tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
2063 }
2064 #endif
2065
2066 /*** Floating-Point arithmetic ***/
2067 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2068 static void gen_f##name(DisasContext *ctx) \
2069 { \
2070 if (unlikely(!ctx->fpu_enabled)) { \
2071 gen_exception(ctx, POWERPC_EXCP_FPU); \
2072 return; \
2073 } \
2074 /* NIP cannot be restored if the memory exception comes from an helper */ \
2075 gen_update_nip(ctx, ctx->nip - 4); \
2076 gen_reset_fpstatus(); \
2077 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2078 cpu_fpr[rA(ctx->opcode)], \
2079 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2080 if (isfloat) { \
2081 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2082 cpu_fpr[rD(ctx->opcode)]); \
2083 } \
2084 if (set_fprf) { \
2085 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2086 } \
2087 if (unlikely(Rc(ctx->opcode) != 0)) { \
2088 gen_set_cr1_from_fpscr(ctx); \
2089 } \
2090 }
2091
2092 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2093 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2094 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2095
2096 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2097 static void gen_f##name(DisasContext *ctx) \
2098 { \
2099 if (unlikely(!ctx->fpu_enabled)) { \
2100 gen_exception(ctx, POWERPC_EXCP_FPU); \
2101 return; \
2102 } \
2103 /* NIP cannot be restored if the memory exception comes from an helper */ \
2104 gen_update_nip(ctx, ctx->nip - 4); \
2105 gen_reset_fpstatus(); \
2106 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2107 cpu_fpr[rA(ctx->opcode)], \
2108 cpu_fpr[rB(ctx->opcode)]); \
2109 if (isfloat) { \
2110 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2111 cpu_fpr[rD(ctx->opcode)]); \
2112 } \
2113 if (set_fprf) { \
2114 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2115 } \
2116 if (unlikely(Rc(ctx->opcode) != 0)) { \
2117 gen_set_cr1_from_fpscr(ctx); \
2118 } \
2119 }
2120 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2121 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2122 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2123
2124 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2125 static void gen_f##name(DisasContext *ctx) \
2126 { \
2127 if (unlikely(!ctx->fpu_enabled)) { \
2128 gen_exception(ctx, POWERPC_EXCP_FPU); \
2129 return; \
2130 } \
2131 /* NIP cannot be restored if the memory exception comes from an helper */ \
2132 gen_update_nip(ctx, ctx->nip - 4); \
2133 gen_reset_fpstatus(); \
2134 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2135 cpu_fpr[rA(ctx->opcode)], \
2136 cpu_fpr[rC(ctx->opcode)]); \
2137 if (isfloat) { \
2138 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2139 cpu_fpr[rD(ctx->opcode)]); \
2140 } \
2141 if (set_fprf) { \
2142 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2143 } \
2144 if (unlikely(Rc(ctx->opcode) != 0)) { \
2145 gen_set_cr1_from_fpscr(ctx); \
2146 } \
2147 }
2148 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2149 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2150 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2151
2152 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2153 static void gen_f##name(DisasContext *ctx) \
2154 { \
2155 if (unlikely(!ctx->fpu_enabled)) { \
2156 gen_exception(ctx, POWERPC_EXCP_FPU); \
2157 return; \
2158 } \
2159 /* NIP cannot be restored if the memory exception comes from an helper */ \
2160 gen_update_nip(ctx, ctx->nip - 4); \
2161 gen_reset_fpstatus(); \
2162 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2163 cpu_fpr[rB(ctx->opcode)]); \
2164 if (set_fprf) { \
2165 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2166 } \
2167 if (unlikely(Rc(ctx->opcode) != 0)) { \
2168 gen_set_cr1_from_fpscr(ctx); \
2169 } \
2170 }
2171
2172 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2173 static void gen_f##name(DisasContext *ctx) \
2174 { \
2175 if (unlikely(!ctx->fpu_enabled)) { \
2176 gen_exception(ctx, POWERPC_EXCP_FPU); \
2177 return; \
2178 } \
2179 /* NIP cannot be restored if the memory exception comes from an helper */ \
2180 gen_update_nip(ctx, ctx->nip - 4); \
2181 gen_reset_fpstatus(); \
2182 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2183 cpu_fpr[rB(ctx->opcode)]); \
2184 if (set_fprf) { \
2185 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2186 } \
2187 if (unlikely(Rc(ctx->opcode) != 0)) { \
2188 gen_set_cr1_from_fpscr(ctx); \
2189 } \
2190 }
2191
2192 /* fadd - fadds */
2193 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2194 /* fdiv - fdivs */
2195 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2196 /* fmul - fmuls */
2197 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2198
2199 /* fre */
2200 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2201
2202 /* fres */
2203 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2204
2205 /* frsqrte */
2206 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2207
2208 /* frsqrtes */
2209 static void gen_frsqrtes(DisasContext *ctx)
2210 {
2211 if (unlikely(!ctx->fpu_enabled)) {
2212 gen_exception(ctx, POWERPC_EXCP_FPU);
2213 return;
2214 }
2215 /* NIP cannot be restored if the memory exception comes from an helper */
2216 gen_update_nip(ctx, ctx->nip - 4);
2217 gen_reset_fpstatus();
2218 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2219 cpu_fpr[rB(ctx->opcode)]);
2220 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2221 cpu_fpr[rD(ctx->opcode)]);
2222 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2223 if (unlikely(Rc(ctx->opcode) != 0)) {
2224 gen_set_cr1_from_fpscr(ctx);
2225 }
2226 }
2227
2228 /* fsel */
2229 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2230 /* fsub - fsubs */
2231 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2232 /* Optional: */
2233
2234 /* fsqrt */
2235 static void gen_fsqrt(DisasContext *ctx)
2236 {
2237 if (unlikely(!ctx->fpu_enabled)) {
2238 gen_exception(ctx, POWERPC_EXCP_FPU);
2239 return;
2240 }
2241 /* NIP cannot be restored if the memory exception comes from an helper */
2242 gen_update_nip(ctx, ctx->nip - 4);
2243 gen_reset_fpstatus();
2244 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2245 cpu_fpr[rB(ctx->opcode)]);
2246 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2247 if (unlikely(Rc(ctx->opcode) != 0)) {
2248 gen_set_cr1_from_fpscr(ctx);
2249 }
2250 }
2251
2252 static void gen_fsqrts(DisasContext *ctx)
2253 {
2254 if (unlikely(!ctx->fpu_enabled)) {
2255 gen_exception(ctx, POWERPC_EXCP_FPU);
2256 return;
2257 }
2258 /* NIP cannot be restored if the memory exception comes from an helper */
2259 gen_update_nip(ctx, ctx->nip - 4);
2260 gen_reset_fpstatus();
2261 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2262 cpu_fpr[rB(ctx->opcode)]);
2263 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2264 cpu_fpr[rD(ctx->opcode)]);
2265 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2266 if (unlikely(Rc(ctx->opcode) != 0)) {
2267 gen_set_cr1_from_fpscr(ctx);
2268 }
2269 }
2270
2271 /*** Floating-Point multiply-and-add ***/
2272 /* fmadd - fmadds */
2273 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2274 /* fmsub - fmsubs */
2275 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2276 /* fnmadd - fnmadds */
2277 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2278 /* fnmsub - fnmsubs */
2279 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2280
2281 /*** Floating-Point round & convert ***/
2282 /* fctiw */
2283 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2284 /* fctiwu */
2285 GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
2286 /* fctiwz */
2287 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2288 /* fctiwuz */
2289 GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
2290 /* frsp */
2291 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2292 /* fcfid */
2293 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC2_FP_CVT_S64);
2294 /* fcfids */
2295 GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
2296 /* fcfidu */
2297 GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2298 /* fcfidus */
2299 GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2300 /* fctid */
2301 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64);
2302 /* fctidu */
2303 GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
2304 /* fctidz */
2305 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64);
2306 /* fctidu */
2307 GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
2308
2309 /* frin */
2310 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2311 /* friz */
2312 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2313 /* frip */
2314 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2315 /* frim */
2316 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2317
2318 static void gen_ftdiv(DisasContext *ctx)
2319 {
2320 if (unlikely(!ctx->fpu_enabled)) {
2321 gen_exception(ctx, POWERPC_EXCP_FPU);
2322 return;
2323 }
2324 gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2325 cpu_fpr[rB(ctx->opcode)]);
2326 }
2327
2328 static void gen_ftsqrt(DisasContext *ctx)
2329 {
2330 if (unlikely(!ctx->fpu_enabled)) {
2331 gen_exception(ctx, POWERPC_EXCP_FPU);
2332 return;
2333 }
2334 gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2335 }
2336
2337
2338
2339 /*** Floating-Point compare ***/
2340
2341 /* fcmpo */
2342 static void gen_fcmpo(DisasContext *ctx)
2343 {
2344 TCGv_i32 crf;
2345 if (unlikely(!ctx->fpu_enabled)) {
2346 gen_exception(ctx, POWERPC_EXCP_FPU);
2347 return;
2348 }
2349 /* NIP cannot be restored if the memory exception comes from an helper */
2350 gen_update_nip(ctx, ctx->nip - 4);
2351 gen_reset_fpstatus();
2352 crf = tcg_const_i32(crfD(ctx->opcode));
2353 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2354 cpu_fpr[rB(ctx->opcode)], crf);
2355 tcg_temp_free_i32(crf);
2356 gen_helper_float_check_status(cpu_env);
2357 }
2358
2359 /* fcmpu */
2360 static void gen_fcmpu(DisasContext *ctx)
2361 {
2362 TCGv_i32 crf;
2363 if (unlikely(!ctx->fpu_enabled)) {
2364 gen_exception(ctx, POWERPC_EXCP_FPU);
2365 return;
2366 }
2367 /* NIP cannot be restored if the memory exception comes from an helper */
2368 gen_update_nip(ctx, ctx->nip - 4);
2369 gen_reset_fpstatus();
2370 crf = tcg_const_i32(crfD(ctx->opcode));
2371 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2372 cpu_fpr[rB(ctx->opcode)], crf);
2373 tcg_temp_free_i32(crf);
2374 gen_helper_float_check_status(cpu_env);
2375 }
2376
2377 /*** Floating-point move ***/
2378 /* fabs */
2379 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2380 static void gen_fabs(DisasContext *ctx)
2381 {
2382 if (unlikely(!ctx->fpu_enabled)) {
2383 gen_exception(ctx, POWERPC_EXCP_FPU);
2384 return;
2385 }
2386 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2387 ~(1ULL << 63));
2388 if (unlikely(Rc(ctx->opcode))) {
2389 gen_set_cr1_from_fpscr(ctx);
2390 }
2391 }
2392
2393 /* fmr - fmr. */
2394 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2395 static void gen_fmr(DisasContext *ctx)
2396 {
2397 if (unlikely(!ctx->fpu_enabled)) {
2398 gen_exception(ctx, POWERPC_EXCP_FPU);
2399 return;
2400 }
2401 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2402 if (unlikely(Rc(ctx->opcode))) {
2403 gen_set_cr1_from_fpscr(ctx);
2404 }
2405 }
2406
2407 /* fnabs */
2408 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2409 static void gen_fnabs(DisasContext *ctx)
2410 {
2411 if (unlikely(!ctx->fpu_enabled)) {
2412 gen_exception(ctx, POWERPC_EXCP_FPU);
2413 return;
2414 }
2415 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2416 1ULL << 63);
2417 if (unlikely(Rc(ctx->opcode))) {
2418 gen_set_cr1_from_fpscr(ctx);
2419 }
2420 }
2421
2422 /* fneg */
2423 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2424 static void gen_fneg(DisasContext *ctx)
2425 {
2426 if (unlikely(!ctx->fpu_enabled)) {
2427 gen_exception(ctx, POWERPC_EXCP_FPU);
2428 return;
2429 }
2430 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2431 1ULL << 63);
2432 if (unlikely(Rc(ctx->opcode))) {
2433 gen_set_cr1_from_fpscr(ctx);
2434 }
2435 }
2436
2437 /* fcpsgn: PowerPC 2.05 specification */
2438 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2439 static void gen_fcpsgn(DisasContext *ctx)
2440 {
2441 if (unlikely(!ctx->fpu_enabled)) {
2442 gen_exception(ctx, POWERPC_EXCP_FPU);
2443 return;
2444 }
2445 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2446 cpu_fpr[rB(ctx->opcode)], 0, 63);
2447 if (unlikely(Rc(ctx->opcode))) {
2448 gen_set_cr1_from_fpscr(ctx);
2449 }
2450 }
2451
2452 static void gen_fmrgew(DisasContext *ctx)
2453 {
2454 TCGv_i64 b0;
2455 if (unlikely(!ctx->fpu_enabled)) {
2456 gen_exception(ctx, POWERPC_EXCP_FPU);
2457 return;
2458 }
2459 b0 = tcg_temp_new_i64();
2460 tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
2461 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2462 b0, 0, 32);
2463 tcg_temp_free_i64(b0);
2464 }
2465
2466 static void gen_fmrgow(DisasContext *ctx)
2467 {
2468 if (unlikely(!ctx->fpu_enabled)) {
2469 gen_exception(ctx, POWERPC_EXCP_FPU);
2470 return;
2471 }
2472 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
2473 cpu_fpr[rB(ctx->opcode)],
2474 cpu_fpr[rA(ctx->opcode)],
2475 32, 32);
2476 }
2477
2478 /*** Floating-Point status & ctrl register ***/
2479
2480 /* mcrfs */
2481 static void gen_mcrfs(DisasContext *ctx)
2482 {
2483 TCGv tmp = tcg_temp_new();
2484 TCGv_i32 tmask;
2485 TCGv_i64 tnew_fpscr = tcg_temp_new_i64();
2486 int bfa;
2487 int nibble;
2488 int shift;
2489
2490 if (unlikely(!ctx->fpu_enabled)) {
2491 gen_exception(ctx, POWERPC_EXCP_FPU);
2492 return;
2493 }
2494 bfa = crfS(ctx->opcode);
2495 nibble = 7 - bfa;
2496 shift = 4 * nibble;
2497 tcg_gen_shri_tl(tmp, cpu_fpscr, shift);
2498 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2499 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2500 tcg_temp_free(tmp);
2501 tcg_gen_extu_tl_i64(tnew_fpscr, cpu_fpscr);
2502 /* Only the exception bits (including FX) should be cleared if read */
2503 tcg_gen_andi_i64(tnew_fpscr, tnew_fpscr, ~((0xF << shift) & FP_EX_CLEAR_BITS));
2504 /* FEX and VX need to be updated, so don't set fpscr directly */
2505 tmask = tcg_const_i32(1 << nibble);
2506 gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask);
2507 tcg_temp_free_i32(tmask);
2508 tcg_temp_free_i64(tnew_fpscr);
2509 }
2510
2511 /* mffs */
2512 static void gen_mffs(DisasContext *ctx)
2513 {
2514 if (unlikely(!ctx->fpu_enabled)) {
2515 gen_exception(ctx, POWERPC_EXCP_FPU);
2516 return;
2517 }
2518 gen_reset_fpstatus();
2519 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2520 if (unlikely(Rc(ctx->opcode))) {
2521 gen_set_cr1_from_fpscr(ctx);
2522 }
2523 }
2524
2525 /* mtfsb0 */
2526 static void gen_mtfsb0(DisasContext *ctx)
2527 {
2528 uint8_t crb;
2529
2530 if (unlikely(!ctx->fpu_enabled)) {
2531 gen_exception(ctx, POWERPC_EXCP_FPU);
2532 return;
2533 }
2534 crb = 31 - crbD(ctx->opcode);
2535 gen_reset_fpstatus();
2536 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2537 TCGv_i32 t0;
2538 /* NIP cannot be restored if the memory exception comes from an helper */
2539 gen_update_nip(ctx, ctx->nip - 4);
2540 t0 = tcg_const_i32(crb);
2541 gen_helper_fpscr_clrbit(cpu_env, t0);
2542 tcg_temp_free_i32(t0);
2543 }
2544 if (unlikely(Rc(ctx->opcode) != 0)) {
2545 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2546 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2547 }
2548 }
2549
2550 /* mtfsb1 */
2551 static void gen_mtfsb1(DisasContext *ctx)
2552 {
2553 uint8_t crb;
2554
2555 if (unlikely(!ctx->fpu_enabled)) {
2556 gen_exception(ctx, POWERPC_EXCP_FPU);
2557 return;
2558 }
2559 crb = 31 - crbD(ctx->opcode);
2560 gen_reset_fpstatus();
2561 /* XXX: we pretend we can only do IEEE floating-point computations */
2562 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2563 TCGv_i32 t0;
2564 /* NIP cannot be restored if the memory exception comes from an helper */
2565 gen_update_nip(ctx, ctx->nip - 4);
2566 t0 = tcg_const_i32(crb);
2567 gen_helper_fpscr_setbit(cpu_env, t0);
2568 tcg_temp_free_i32(t0);
2569 }
2570 if (unlikely(Rc(ctx->opcode) != 0)) {
2571 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2572 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2573 }
2574 /* We can raise a differed exception */
2575 gen_helper_float_check_status(cpu_env);
2576 }
2577
2578 /* mtfsf */
2579 static void gen_mtfsf(DisasContext *ctx)
2580 {
2581 TCGv_i32 t0;
2582 int flm, l, w;
2583
2584 if (unlikely(!ctx->fpu_enabled)) {
2585 gen_exception(ctx, POWERPC_EXCP_FPU);
2586 return;
2587 }
2588 flm = FPFLM(ctx->opcode);
2589 l = FPL(ctx->opcode);
2590 w = FPW(ctx->opcode);
2591 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2592 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2593 return;
2594 }
2595 /* NIP cannot be restored if the memory exception comes from an helper */
2596 gen_update_nip(ctx, ctx->nip - 4);
2597 gen_reset_fpstatus();
2598 if (l) {
2599 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2600 } else {
2601 t0 = tcg_const_i32(flm << (w * 8));
2602 }
2603 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2604 tcg_temp_free_i32(t0);
2605 if (unlikely(Rc(ctx->opcode) != 0)) {
2606 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2607 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2608 }
2609 /* We can raise a differed exception */
2610 gen_helper_float_check_status(cpu_env);
2611 }
2612
2613 /* mtfsfi */
2614 static void gen_mtfsfi(DisasContext *ctx)
2615 {
2616 int bf, sh, w;
2617 TCGv_i64 t0;
2618 TCGv_i32 t1;
2619
2620 if (unlikely(!ctx->fpu_enabled)) {
2621 gen_exception(ctx, POWERPC_EXCP_FPU);
2622 return;
2623 }
2624 w = FPW(ctx->opcode);
2625 bf = FPBF(ctx->opcode);
2626 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2627 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2628 return;
2629 }
2630 sh = (8 * w) + 7 - bf;
2631 /* NIP cannot be restored if the memory exception comes from an helper */
2632 gen_update_nip(ctx, ctx->nip - 4);
2633 gen_reset_fpstatus();
2634 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
2635 t1 = tcg_const_i32(1 << sh);
2636 gen_helper_store_fpscr(cpu_env, t0, t1);
2637 tcg_temp_free_i64(t0);
2638 tcg_temp_free_i32(t1);
2639 if (unlikely(Rc(ctx->opcode) != 0)) {
2640 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2641 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2642 }
2643 /* We can raise a differed exception */
2644 gen_helper_float_check_status(cpu_env);
2645 }
2646
2647 /*** Addressing modes ***/
2648 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2649 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2650 target_long maskl)
2651 {
2652 target_long simm = SIMM(ctx->opcode);
2653
2654 simm &= ~maskl;
2655 if (rA(ctx->opcode) == 0) {
2656 if (NARROW_MODE(ctx)) {
2657 simm = (uint32_t)simm;
2658 }
2659 tcg_gen_movi_tl(EA, simm);
2660 } else if (likely(simm != 0)) {
2661 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2662 if (NARROW_MODE(ctx)) {
2663 tcg_gen_ext32u_tl(EA, EA);
2664 }
2665 } else {
2666 if (NARROW_MODE(ctx)) {
2667 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2668 } else {
2669 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2670 }
2671 }
2672 }
2673
2674 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2675 {
2676 if (rA(ctx->opcode) == 0) {
2677 if (NARROW_MODE(ctx)) {
2678 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2679 } else {
2680 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2681 }
2682 } else {
2683 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2684 if (NARROW_MODE(ctx)) {
2685 tcg_gen_ext32u_tl(EA, EA);
2686 }
2687 }
2688 }
2689
2690 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2691 {
2692 if (rA(ctx->opcode) == 0) {
2693 tcg_gen_movi_tl(EA, 0);
2694 } else if (NARROW_MODE(ctx)) {
2695 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2696 } else {
2697 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2698 }
2699 }
2700
2701 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2702 target_long val)
2703 {
2704 tcg_gen_addi_tl(ret, arg1, val);
2705 if (NARROW_MODE(ctx)) {
2706 tcg_gen_ext32u_tl(ret, ret);
2707 }
2708 }
2709
2710 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2711 {
2712 TCGLabel *l1 = gen_new_label();
2713 TCGv t0 = tcg_temp_new();
2714 TCGv_i32 t1, t2;
2715 /* NIP cannot be restored if the memory exception comes from an helper */
2716 gen_update_nip(ctx, ctx->nip - 4);
2717 tcg_gen_andi_tl(t0, EA, mask);
2718 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2719 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2720 t2 = tcg_const_i32(0);
2721 gen_helper_raise_exception_err(cpu_env, t1, t2);
2722 tcg_temp_free_i32(t1);
2723 tcg_temp_free_i32(t2);
2724 gen_set_label(l1);
2725 tcg_temp_free(t0);
2726 }
2727
2728 /*** Integer load ***/
2729 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2730 {
2731 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2732 }
2733
2734 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2735 {
2736 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2737 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2738 }
2739
2740 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2741 {
2742 TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
2743 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2744 }
2745
2746 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2747 {
2748 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2749 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2750 }
2751
2752 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2753 {
2754 TCGv tmp = tcg_temp_new();
2755 gen_qemu_ld32u(ctx, tmp, addr);
2756 tcg_gen_extu_tl_i64(val, tmp);
2757 tcg_temp_free(tmp);
2758 }
2759
2760 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2761 {
2762 TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
2763 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2764 }
2765
2766 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2767 {
2768 TCGv tmp = tcg_temp_new();
2769 gen_qemu_ld32s(ctx, tmp, addr);
2770 tcg_gen_ext_tl_i64(val, tmp);
2771 tcg_temp_free(tmp);
2772 }
2773
2774 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2775 {
2776 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2777 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
2778 }
2779
2780 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2781 {
2782 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2783 }
2784
2785 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2786 {
2787 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2788 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2789 }
2790
2791 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2792 {
2793 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2794 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2795 }
2796
2797 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2798 {
2799 TCGv tmp = tcg_temp_new();
2800 tcg_gen_trunc_i64_tl(tmp, val);
2801 gen_qemu_st32(ctx, tmp, addr);
2802 tcg_temp_free(tmp);
2803 }
2804
2805 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2806 {
2807 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2808 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
2809 }
2810
2811 #define GEN_LD(name, ldop, opc, type) \
2812 static void glue(gen_, name)(DisasContext *ctx) \
2813 { \
2814 TCGv EA; \
2815 gen_set_access_type(ctx, ACCESS_INT); \
2816 EA = tcg_temp_new(); \
2817 gen_addr_imm_index(ctx, EA, 0); \
2818 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2819 tcg_temp_free(EA); \
2820 }
2821
2822 #define GEN_LDU(name, ldop, opc, type) \
2823 static void glue(gen_, name##u)(DisasContext *ctx) \
2824 { \
2825 TCGv EA; \
2826 if (unlikely(rA(ctx->opcode) == 0 || \
2827 rA(ctx->opcode) == rD(ctx->opcode))) { \
2828 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2829 return; \
2830 } \
2831 gen_set_access_type(ctx, ACCESS_INT); \
2832 EA = tcg_temp_new(); \
2833 if (type == PPC_64B) \
2834 gen_addr_imm_index(ctx, EA, 0x03); \
2835 else \
2836 gen_addr_imm_index(ctx, EA, 0); \
2837 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2838 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2839 tcg_temp_free(EA); \
2840 }
2841
2842 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2843 static void glue(gen_, name##ux)(DisasContext *ctx) \
2844 { \
2845 TCGv EA; \
2846 if (unlikely(rA(ctx->opcode) == 0 || \
2847 rA(ctx->opcode) == rD(ctx->opcode))) { \
2848 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2849 return; \
2850 } \
2851 gen_set_access_type(ctx, ACCESS_INT); \
2852 EA = tcg_temp_new(); \
2853 gen_addr_reg_index(ctx, EA); \
2854 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2855 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2856 tcg_temp_free(EA); \
2857 }
2858
2859 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2860 static void glue(gen_, name##x)(DisasContext *ctx) \
2861 { \
2862 TCGv EA; \
2863 gen_set_access_type(ctx, ACCESS_INT); \
2864 EA = tcg_temp_new(); \
2865 gen_addr_reg_index(ctx, EA); \
2866 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2867 tcg_temp_free(EA); \
2868 }
2869 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2870 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2871
2872 #define GEN_LDS(name, ldop, op, type) \
2873 GEN_LD(name, ldop, op | 0x20, type); \
2874 GEN_LDU(name, ldop, op | 0x21, type); \
2875 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2876 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2877
2878 /* lbz lbzu lbzux lbzx */
2879 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2880 /* lha lhau lhaux lhax */
2881 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2882 /* lhz lhzu lhzux lhzx */
2883 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2884 /* lwz lwzu lwzux lwzx */
2885 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2886 #if defined(TARGET_PPC64)
2887 /* lwaux */
2888 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2889 /* lwax */
2890 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2891 /* ldux */
2892 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2893 /* ldx */
2894 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2895
2896 static void gen_ld(DisasContext *ctx)
2897 {
2898 TCGv EA;
2899 if (Rc(ctx->opcode)) {
2900 if (unlikely(rA(ctx->opcode) == 0 ||
2901 rA(ctx->opcode) == rD(ctx->opcode))) {
2902 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2903 return;
2904 }
2905 }
2906 gen_set_access_type(ctx, ACCESS_INT);
2907 EA = tcg_temp_new();
2908 gen_addr_imm_index(ctx, EA, 0x03);
2909 if (ctx->opcode & 0x02) {
2910 /* lwa (lwau is undefined) */
2911 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2912 } else {
2913 /* ld - ldu */
2914 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2915 }
2916 if (Rc(ctx->opcode))
2917 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2918 tcg_temp_free(EA);
2919 }
2920
2921 /* lq */
2922 static void gen_lq(DisasContext *ctx)
2923 {
2924 int ra, rd;
2925 TCGv EA;
2926
2927 /* lq is a legal user mode instruction starting in ISA 2.07 */
2928 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2929 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2930
2931 if (!legal_in_user_mode && ctx->pr) {
2932 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2933 return;
2934 }
2935
2936 if (!le_is_supported && ctx->le_mode) {
2937 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2938 return;
2939 }
2940
2941 ra = rA(ctx->opcode);
2942 rd = rD(ctx->opcode);
2943 if (unlikely((rd & 1) || rd == ra)) {
2944 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2945 return;
2946 }
2947
2948 gen_set_access_type(ctx, ACCESS_INT);
2949 EA = tcg_temp_new();
2950 gen_addr_imm_index(ctx, EA, 0x0F);
2951
2952 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2953 64-bit byteswap already. */
2954 if (unlikely(ctx->le_mode)) {
2955 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2956 gen_addr_add(ctx, EA, EA, 8);
2957 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2958 } else {
2959 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2960 gen_addr_add(ctx, EA, EA, 8);
2961 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2962 }
2963 tcg_temp_free(EA);
2964 }
2965 #endif
2966
2967 /*** Integer store ***/
2968 #define GEN_ST(name, stop, opc, type) \
2969 static void glue(gen_, name)(DisasContext *ctx) \
2970 { \
2971 TCGv EA; \
2972 gen_set_access_type(ctx, ACCESS_INT); \
2973 EA = tcg_temp_new(); \
2974 gen_addr_imm_index(ctx, EA, 0); \
2975 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2976 tcg_temp_free(EA); \
2977 }
2978
2979 #define GEN_STU(name, stop, opc, type) \
2980 static void glue(gen_, stop##u)(DisasContext *ctx) \
2981 { \
2982 TCGv EA; \
2983 if (unlikely(rA(ctx->opcode) == 0)) { \
2984 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2985 return; \
2986 } \
2987 gen_set_access_type(ctx, ACCESS_INT); \
2988 EA = tcg_temp_new(); \
2989 if (type == PPC_64B) \
2990 gen_addr_imm_index(ctx, EA, 0x03); \
2991 else \
2992 gen_addr_imm_index(ctx, EA, 0); \
2993 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2994 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2995 tcg_temp_free(EA); \
2996 }
2997
2998 #define GEN_STUX(name, stop, opc2, opc3, type) \
2999 static void glue(gen_, name##ux)(DisasContext *ctx) \
3000 { \
3001 TCGv EA; \
3002 if (unlikely(rA(ctx->opcode) == 0)) { \
3003 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3004 return; \
3005 } \
3006 gen_set_access_type(ctx, ACCESS_INT); \
3007 EA = tcg_temp_new(); \
3008 gen_addr_reg_index(ctx, EA); \
3009 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3010 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3011 tcg_temp_free(EA); \
3012 }
3013
3014 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
3015 static void glue(gen_, name##x)(DisasContext *ctx) \
3016 { \
3017 TCGv EA; \
3018 gen_set_access_type(ctx, ACCESS_INT); \
3019 EA = tcg_temp_new(); \
3020 gen_addr_reg_index(ctx, EA); \
3021 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3022 tcg_temp_free(EA); \
3023 }
3024 #define GEN_STX(name, stop, opc2, opc3, type) \
3025 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
3026
3027 #define GEN_STS(name, stop, op, type) \
3028 GEN_ST(name, stop, op | 0x20, type); \
3029 GEN_STU(name, stop, op | 0x21, type); \
3030 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
3031 GEN_STX(name, stop, 0x17, op | 0x00, type)
3032
3033 /* stb stbu stbux stbx */
3034 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
3035 /* sth sthu sthux sthx */
3036 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
3037 /* stw stwu stwux stwx */
3038 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
3039 #if defined(TARGET_PPC64)
3040 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
3041 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
3042
3043 static void gen_std(DisasContext *ctx)
3044 {
3045 int rs;
3046 TCGv EA;
3047
3048 rs = rS(ctx->opcode);
3049 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
3050 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3051 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3052
3053 if (!(ctx->insns_flags & PPC_64BX)) {
3054 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3055 }
3056
3057 if (!legal_in_user_mode && ctx->pr) {
3058 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3059 return;
3060 }
3061
3062 if (!le_is_supported && ctx->le_mode) {
3063 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3064 return;
3065 }
3066
3067 if (unlikely(rs & 1)) {
3068 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3069 return;
3070 }
3071 gen_set_access_type(ctx, ACCESS_INT);
3072 EA = tcg_temp_new();
3073 gen_addr_imm_index(ctx, EA, 0x03);
3074
3075 /* We only need to swap high and low halves. gen_qemu_st64 does
3076 necessary 64-bit byteswap already. */
3077 if (unlikely(ctx->le_mode)) {
3078 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3079 gen_addr_add(ctx, EA, EA, 8);
3080 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3081 } else {
3082 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3083 gen_addr_add(ctx, EA, EA, 8);
3084 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3085 }
3086 tcg_temp_free(EA);
3087 } else {
3088 /* std / stdu*/
3089 if (Rc(ctx->opcode)) {
3090 if (unlikely(rA(ctx->opcode) == 0)) {
3091 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3092 return;
3093 }
3094 }
3095 gen_set_access_type(ctx, ACCESS_INT);
3096 EA = tcg_temp_new();
3097 gen_addr_imm_index(ctx, EA, 0x03);
3098 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3099 if (Rc(ctx->opcode))
3100 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3101 tcg_temp_free(EA);
3102 }
3103 }
3104 #endif
3105 /*** Integer load and store with byte reverse ***/
3106
3107 /* lhbrx */
3108 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3109 {
3110 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3111 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3112 }
3113 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3114
3115 /* lwbrx */
3116 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3117 {
3118 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3119 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3120 }
3121 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3122
3123 #if defined(TARGET_PPC64)
3124 /* ldbrx */
3125 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3126 {
3127 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3128 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
3129 }
3130 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
3131 #endif /* TARGET_PPC64 */
3132
3133 /* sthbrx */
3134 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3135 {
3136 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3137 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3138 }
3139 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3140
3141 /* stwbrx */
3142 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3143 {
3144 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3145 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3146 }
3147 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3148
3149 #if defined(TARGET_PPC64)
3150 /* stdbrx */
3151 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3152 {
3153 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3154 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
3155 }
3156 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
3157 #endif /* TARGET_PPC64 */
3158
3159 /*** Integer load and store multiple ***/
3160
3161 /* lmw */
3162 static void gen_lmw(DisasContext *ctx)
3163 {
3164 TCGv t0;
3165 TCGv_i32 t1;
3166 gen_set_access_type(ctx, ACCESS_INT);
3167 /* NIP cannot be restored if the memory exception comes from an helper */
3168 gen_update_nip(ctx, ctx->nip - 4);
3169 t0 = tcg_temp_new();
3170 t1 = tcg_const_i32(rD(ctx->opcode));
3171 gen_addr_imm_index(ctx, t0, 0);
3172 gen_helper_lmw(cpu_env, t0, t1);
3173 tcg_temp_free(t0);
3174 tcg_temp_free_i32(t1);
3175 }
3176
3177 /* stmw */
3178 static void gen_stmw(DisasContext *ctx)
3179 {
3180 TCGv t0;
3181 TCGv_i32 t1;
3182 gen_set_access_type(ctx, ACCESS_INT);
3183 /* NIP cannot be restored if the memory exception comes from an helper */
3184 gen_update_nip(ctx, ctx->nip - 4);
3185 t0 = tcg_temp_new();
3186 t1 = tcg_const_i32(rS(ctx->opcode));
3187 gen_addr_imm_index(ctx, t0, 0);
3188 gen_helper_stmw(cpu_env, t0, t1);
3189 tcg_temp_free(t0);
3190 tcg_temp_free_i32(t1);
3191 }
3192
3193 /*** Integer load and store strings ***/
3194
3195 /* lswi */
3196 /* PowerPC32 specification says we must generate an exception if
3197 * rA is in the range of registers to be loaded.
3198 * In an other hand, IBM says this is valid, but rA won't be loaded.
3199 * For now, I'll follow the spec...
3200 */
3201 static void gen_lswi(DisasContext *ctx)
3202 {
3203 TCGv t0;
3204 TCGv_i32 t1, t2;
3205 int nb = NB(ctx->opcode);
3206 int start = rD(ctx->opcode);
3207 int ra = rA(ctx->opcode);
3208 int nr;
3209
3210 if (nb == 0)
3211 nb = 32;
3212 nr = (nb + 3) / 4;
3213 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
3214 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3215 return;
3216 }
3217 gen_set_access_type(ctx, ACCESS_INT);
3218 /* NIP cannot be restored if the memory exception comes from an helper */
3219 gen_update_nip(ctx, ctx->nip - 4);
3220 t0 = tcg_temp_new();
3221 gen_addr_register(ctx, t0);
3222 t1 = tcg_const_i32(nb);
3223 t2 = tcg_const_i32(start);
3224 gen_helper_lsw(cpu_env, t0, t1, t2);
3225 tcg_temp_free(t0);
3226 tcg_temp_free_i32(t1);
3227 tcg_temp_free_i32(t2);
3228 }
3229
3230 /* lswx */
3231 static void gen_lswx(DisasContext *ctx)
3232 {
3233 TCGv t0;
3234 TCGv_i32 t1, t2, t3;
3235 gen_set_access_type(ctx, ACCESS_INT);
3236 /* NIP cannot be restored if the memory exception comes from an helper */
3237 gen_update_nip(ctx, ctx->nip - 4);
3238 t0 = tcg_temp_new();
3239 gen_addr_reg_index(ctx, t0);
3240 t1 = tcg_const_i32(rD(ctx->opcode));
3241 t2 = tcg_const_i32(rA(ctx->opcode));
3242 t3 = tcg_const_i32(rB(ctx->opcode));
3243 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3244 tcg_temp_free(t0);
3245 tcg_temp_free_i32(t1);
3246 tcg_temp_free_i32(t2);
3247 tcg_temp_free_i32(t3);
3248 }
3249
3250 /* stswi */
3251 static void gen_stswi(DisasContext *ctx)
3252 {
3253 TCGv t0;
3254 TCGv_i32 t1, t2;
3255 int nb = NB(ctx->opcode);
3256 gen_set_access_type(ctx, ACCESS_INT);
3257 /* NIP cannot be restored if the memory exception comes from an helper */
3258 gen_update_nip(ctx, ctx->nip - 4);
3259 t0 = tcg_temp_new();
3260 gen_addr_register(ctx, t0);
3261 if (nb == 0)
3262 nb = 32;
3263 t1 = tcg_const_i32(nb);
3264 t2 = tcg_const_i32(rS(ctx->opcode));
3265 gen_helper_stsw(cpu_env, t0, t1, t2);
3266 tcg_temp_free(t0);
3267 tcg_temp_free_i32(t1);
3268 tcg_temp_free_i32(t2);
3269 }
3270
3271 /* stswx */
3272 static void gen_stswx(DisasContext *ctx)
3273 {
3274 TCGv t0;
3275 TCGv_i32 t1, t2;
3276 gen_set_access_type(ctx, ACCESS_INT);
3277 /* NIP cannot be restored if the memory exception comes from an helper */
3278 gen_update_nip(ctx, ctx->nip - 4);
3279 t0 = tcg_temp_new();
3280 gen_addr_reg_index(ctx, t0);
3281 t1 = tcg_temp_new_i32();
3282 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3283 tcg_gen_andi_i32(t1, t1, 0x7F);
3284 t2 = tcg_const_i32(rS(ctx->opcode));
3285 gen_helper_stsw(cpu_env, t0, t1, t2);
3286 tcg_temp_free(t0);
3287 tcg_temp_free_i32(t1);
3288 tcg_temp_free_i32(t2);
3289 }
3290
3291 /*** Memory synchronisation ***/
3292 /* eieio */
3293 static void gen_eieio(DisasContext *ctx)
3294 {
3295 }
3296
3297 #if !defined(CONFIG_USER_ONLY)
3298 static inline void gen_check_tlb_flush(DisasContext *ctx)
3299 {
3300 TCGv_i32 t;
3301 TCGLabel *l;
3302
3303 if (!ctx->lazy_tlb_flush) {
3304 return;
3305 }
3306 l = gen_new_label();
3307 t = tcg_temp_new_i32();
3308 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
3309 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
3310 gen_helper_check_tlb_flush(cpu_env);
3311 gen_set_label(l);
3312 tcg_temp_free_i32(t);
3313 }
3314 #else
3315 static inline void gen_check_tlb_flush(DisasContext *ctx) { }
3316 #endif
3317
3318 /* isync */
3319 static void gen_isync(DisasContext *ctx)
3320 {
3321 /*
3322 * We need to check for a pending TLB flush. This can only happen in
3323 * kernel mode however so check MSR_PR
3324 */
3325 if (!ctx->pr) {
3326 gen_check_tlb_flush(ctx);
3327 }
3328 gen_stop_exception(ctx);
3329 }
3330
3331 #define LARX(name, len, loadop) \
3332 static void gen_##name(DisasContext *ctx) \
3333 { \
3334 TCGv t0; \
3335 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3336 gen_set_access_type(ctx, ACCESS_RES); \
3337 t0 = tcg_temp_local_new(); \
3338 gen_addr_reg_index(ctx, t0); \
3339 if ((len) > 1) { \
3340 gen_check_align(ctx, t0, (len)-1); \
3341 } \
3342 gen_qemu_##loadop(ctx, gpr, t0); \
3343 tcg_gen_mov_tl(cpu_reserve, t0); \
3344 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3345 tcg_temp_free(t0); \
3346 }
3347
3348 /* lwarx */
3349 LARX(lbarx, 1, ld8u);
3350 LARX(lharx, 2, ld16u);
3351 LARX(lwarx, 4, ld32u);
3352
3353
3354 #if defined(CONFIG_USER_ONLY)
3355 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3356 int reg, int size)
3357 {
3358 TCGv t0 = tcg_temp_new();
3359 uint32_t save_exception = ctx->exception;
3360
3361 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3362 tcg_gen_movi_tl(t0, (size << 5) | reg);
3363 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3364 tcg_temp_free(t0);
3365 gen_update_nip(ctx, ctx->nip-4);
3366 ctx->exception = POWERPC_EXCP_BRANCH;
3367 gen_exception(ctx, POWERPC_EXCP_STCX);
3368 ctx->exception = save_exception;
3369 }
3370 #else
3371 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3372 int reg, int size)
3373 {
3374 TCGLabel *l1;
3375
3376 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3377 l1 = gen_new_label();
3378 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3379 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3380 #if defined(TARGET_PPC64)
3381 if (size == 8) {
3382 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3383 } else
3384 #endif
3385 if (size == 4) {
3386 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3387 } else if (size == 2) {
3388 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3389 #if defined(TARGET_PPC64)
3390 } else if (size == 16) {
3391 TCGv gpr1, gpr2 , EA8;
3392 if (unlikely(ctx->le_mode)) {
3393 gpr1 = cpu_gpr[reg+1];
3394 gpr2 = cpu_gpr[reg];
3395 } else {
3396 gpr1 = cpu_gpr[reg];
3397 gpr2 = cpu_gpr[reg+1];
3398 }
3399 gen_qemu_st64(ctx, gpr1, EA);
3400 EA8 = tcg_temp_local_new();
3401 gen_addr_add(ctx, EA8, EA, 8);
3402 gen_qemu_st64(ctx, gpr2, EA8);
3403 tcg_temp_free(EA8);
3404 #endif
3405 } else {
3406 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3407 }
3408 gen_set_label(l1);
3409 tcg_gen_movi_tl(cpu_reserve, -1);
3410 }
3411 #endif
3412
3413 #define STCX(name, len) \
3414 static void gen_##name(DisasContext *ctx) \
3415 { \
3416 TCGv t0; \
3417 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3418 gen_inval_exception(ctx, \
3419 POWERPC_EXCP_INVAL_INVAL); \
3420 return; \
3421 } \
3422 gen_set_access_type(ctx, ACCESS_RES); \
3423 t0 = tcg_temp_local_new(); \
3424 gen_addr_reg_index(ctx, t0); \
3425 if (len > 1) { \
3426 gen_check_align(ctx, t0, (len)-1); \
3427 } \
3428 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3429 tcg_temp_free(t0); \
3430 }
3431
3432 STCX(stbcx_, 1);
3433 STCX(sthcx_, 2);
3434 STCX(stwcx_, 4);
3435
3436 #if defined(TARGET_PPC64)
3437 /* ldarx */
3438 LARX(ldarx, 8, ld64);
3439
3440 /* lqarx */
3441 static void gen_lqarx(DisasContext *ctx)
3442 {
3443 TCGv EA;
3444 int rd = rD(ctx->opcode);
3445 TCGv gpr1, gpr2;
3446
3447 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3448 (rd == rB(ctx->opcode)))) {
3449 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3450 return;
3451 }
3452
3453 gen_set_access_type(ctx, ACCESS_RES);
3454 EA = tcg_temp_local_new();
3455 gen_addr_reg_index(ctx, EA);
3456 gen_check_align(ctx, EA, 15);
3457 if (unlikely(ctx->le_mode)) {
3458 gpr1 = cpu_gpr[rd+1];
3459 gpr2 = cpu_gpr[rd];
3460 } else {
3461 gpr1 = cpu_gpr[rd];
3462 gpr2 = cpu_gpr[rd+1];
3463 }
3464 gen_qemu_ld64(ctx, gpr1, EA);
3465 tcg_gen_mov_tl(cpu_reserve, EA);
3466
3467 gen_addr_add(ctx, EA, EA, 8);
3468 gen_qemu_ld64(ctx, gpr2, EA);
3469
3470 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3471 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3472
3473 tcg_temp_free(EA);
3474 }
3475
3476 /* stdcx. */
3477 STCX(stdcx_, 8);
3478 STCX(stqcx_, 16);
3479 #endif /* defined(TARGET_PPC64) */
3480
3481 /* sync */
3482 static void gen_sync(DisasContext *ctx)
3483 {
3484 uint32_t l = (ctx->opcode >> 21) & 3;
3485
3486 /*
3487 * We may need to check for a pending TLB flush.
3488 *
3489 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3490 *
3491 * Additionally, this can only happen in kernel mode however so
3492 * check MSR_PR as well.
3493 */
3494 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
3495 gen_check_tlb_flush(ctx);
3496 }
3497 }
3498
3499 /* wait */
3500 static void gen_wait(DisasContext *ctx)
3501 {
3502 TCGv_i32 t0 = tcg_temp_new_i32();
3503 tcg_gen_st_i32(t0, cpu_env,
3504 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3505 tcg_temp_free_i32(t0);
3506 /* Stop translation, as the CPU is supposed to sleep from now */
3507 gen_exception_err(ctx, EXCP_HLT, 1);
3508 }
3509
3510 /*** Floating-point load ***/
3511 #define GEN_LDF(name, ldop, opc, type) \
3512 static void glue(gen_, name)(DisasContext *ctx) \
3513 { \
3514 TCGv EA; \
3515 if (unlikely(!ctx->fpu_enabled)) { \
3516 gen_exception(ctx, POWERPC_EXCP_FPU); \
3517 return; \
3518 } \
3519 gen_set_access_type(ctx, ACCESS_FLOAT); \
3520 EA = tcg_temp_new(); \
3521 gen_addr_imm_index(ctx, EA, 0); \
3522 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3523 tcg_temp_free(EA); \
3524 }
3525
3526 #define GEN_LDUF(name, ldop, opc, type) \
3527 static void glue(gen_, name##u)(DisasContext *ctx) \
3528 { \
3529 TCGv EA; \
3530 if (unlikely(!ctx->fpu_enabled)) { \
3531 gen_exception(ctx, POWERPC_EXCP_FPU); \
3532 return; \
3533 } \
3534 if (unlikely(rA(ctx->opcode) == 0)) { \
3535 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3536 return; \
3537 } \
3538 gen_set_access_type(ctx, ACCESS_FLOAT); \
3539 EA = tcg_temp_new(); \
3540 gen_addr_imm_index(ctx, EA, 0); \
3541 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3542 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3543 tcg_temp_free(EA); \
3544 }
3545
3546 #define GEN_LDUXF(name, ldop, opc, type) \
3547 static void glue(gen_, name##ux)(DisasContext *ctx) \
3548 { \
3549 TCGv EA; \
3550 if (unlikely(!ctx->fpu_enabled)) { \
3551 gen_exception(ctx, POWERPC_EXCP_FPU); \
3552 return; \
3553 } \
3554 if (unlikely(rA(ctx->opcode) == 0)) { \
3555 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3556 return; \
3557 } \
3558 gen_set_access_type(ctx, ACCESS_FLOAT); \
3559 EA = tcg_temp_new(); \
3560 gen_addr_reg_index(ctx, EA); \
3561 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3562 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3563 tcg_temp_free(EA); \
3564 }
3565
3566 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3567 static void glue(gen_, name##x)(DisasContext *ctx) \
3568 { \
3569 TCGv EA; \
3570 if (unlikely(!ctx->fpu_enabled)) { \
3571 gen_exception(ctx, POWERPC_EXCP_FPU); \
3572 return; \
3573 } \
3574 gen_set_access_type(ctx, ACCESS_FLOAT); \
3575 EA = tcg_temp_new(); \
3576 gen_addr_reg_index(ctx, EA); \
3577 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3578 tcg_temp_free(EA); \
3579 }
3580
3581 #define GEN_LDFS(name, ldop, op, type) \
3582 GEN_LDF(name, ldop, op | 0x20, type); \
3583 GEN_LDUF(name, ldop, op | 0x21, type); \
3584 GEN_LDUXF(name, ldop, op | 0x01, type); \
3585 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3586
3587 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3588 {
3589 TCGv t0 = tcg_temp_new();
3590 TCGv_i32 t1 = tcg_temp_new_i32();
3591 gen_qemu_ld32u(ctx, t0, arg2);
3592 tcg_gen_trunc_tl_i32(t1, t0);
3593 tcg_temp_free(t0);
3594 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3595 tcg_temp_free_i32(t1);
3596 }
3597
3598 /* lfd lfdu lfdux lfdx */
3599 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3600 /* lfs lfsu lfsux lfsx */
3601 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3602
3603 /* lfdp */
3604 static void gen_lfdp(DisasContext *ctx)
3605 {
3606 TCGv EA;
3607 if (unlikely(!ctx->fpu_enabled)) {
3608 gen_exception(ctx, POWERPC_EXCP_FPU);
3609 return;
3610 }
3611 gen_set_access_type(ctx, ACCESS_FLOAT);
3612 EA = tcg_temp_new();
3613 gen_addr_imm_index(ctx, EA, 0);
3614 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3615 64-bit byteswap already. */
3616 if (unlikely(ctx->le_mode)) {
3617 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3618 tcg_gen_addi_tl(EA, EA, 8);
3619 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3620 } else {
3621 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3622 tcg_gen_addi_tl(EA, EA, 8);
3623 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3624 }
3625 tcg_temp_free(EA);
3626 }
3627
3628 /* lfdpx */
3629 static void gen_lfdpx(DisasContext *ctx)
3630 {
3631 TCGv EA;
3632 if (unlikely(!ctx->fpu_enabled)) {
3633 gen_exception(ctx, POWERPC_EXCP_FPU);
3634 return;
3635 }
3636 gen_set_access_type(ctx, ACCESS_FLOAT);
3637 EA = tcg_temp_new();
3638 gen_addr_reg_index(ctx, EA);
3639 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3640 64-bit byteswap already. */
3641 if (unlikely(ctx->le_mode)) {
3642 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3643 tcg_gen_addi_tl(EA, EA, 8);
3644 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3645 } else {
3646 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3647 tcg_gen_addi_tl(EA, EA, 8);
3648 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3649 }
3650 tcg_temp_free(EA);
3651 }
3652
3653 /* lfiwax */
3654 static void gen_lfiwax(DisasContext *ctx)
3655 {
3656 TCGv EA;
3657 TCGv t0;
3658 if (unlikely(!ctx->fpu_enabled)) {
3659 gen_exception(ctx, POWERPC_EXCP_FPU);
3660 return;
3661 }
3662 gen_set_access_type(ctx, ACCESS_FLOAT);
3663 EA = tcg_temp_new();
3664 t0 = tcg_temp_new();
3665 gen_addr_reg_index(ctx, EA);
3666 gen_qemu_ld32s(ctx, t0, EA);
3667 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
3668 tcg_temp_free(EA);
3669 tcg_temp_free(t0);
3670 }
3671
3672 /* lfiwzx */
3673 static void gen_lfiwzx(DisasContext *ctx)
3674 {
3675 TCGv EA;
3676 if (unlikely(!ctx->fpu_enabled)) {
3677 gen_exception(ctx, POWERPC_EXCP_FPU);
3678 return;
3679 }
3680 gen_set_access_type(ctx, ACCESS_FLOAT);
3681 EA = tcg_temp_new();
3682 gen_addr_reg_index(ctx, EA);
3683 gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3684 tcg_temp_free(EA);
3685 }
3686 /*** Floating-point store ***/
3687 #define GEN_STF(name, stop, opc, type) \
3688 static void glue(gen_, name)(DisasContext *ctx) \
3689 { \
3690 TCGv EA; \
3691 if (unlikely(!ctx->fpu_enabled)) { \
3692 gen_exception(ctx, POWERPC_EXCP_FPU); \
3693 return; \
3694 } \
3695 gen_set_access_type(ctx, ACCESS_FLOAT); \
3696 EA = tcg_temp_new(); \
3697 gen_addr_imm_index(ctx, EA, 0); \
3698 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3699 tcg_temp_free(EA); \
3700 }
3701
3702 #define GEN_STUF(name, stop, opc, type) \
3703 static void glue(gen_, name##u)(DisasContext *ctx) \
3704 { \
3705 TCGv EA; \
3706 if (unlikely(!ctx->fpu_enabled)) { \
3707 gen_exception(ctx, POWERPC_EXCP_FPU); \
3708 return; \
3709 } \
3710 if (unlikely(rA(ctx->opcode) == 0)) { \
3711 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3712 return; \
3713 } \
3714 gen_set_access_type(ctx, ACCESS_FLOAT); \
3715 EA = tcg_temp_new(); \
3716 gen_addr_imm_index(ctx, EA, 0); \
3717 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3718 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3719 tcg_temp_free(EA); \
3720 }
3721
3722 #define GEN_STUXF(name, stop, opc, type) \
3723 static void glue(gen_, name##ux)(DisasContext *ctx) \
3724 { \
3725 TCGv EA; \
3726 if (unlikely(!ctx->fpu_enabled)) { \
3727 gen_exception(ctx, POWERPC_EXCP_FPU); \
3728 return; \
3729 } \
3730 if (unlikely(rA(ctx->opcode) == 0)) { \
3731 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3732 return; \
3733 } \
3734 gen_set_access_type(ctx, ACCESS_FLOAT); \
3735 EA = tcg_temp_new(); \
3736 gen_addr_reg_index(ctx, EA); \
3737 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3738 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3739 tcg_temp_free(EA); \
3740 }
3741
3742 #define GEN_STXF(name, stop, opc2, opc3, type) \
3743 static void glue(gen_, name##x)(DisasContext *ctx) \
3744 { \
3745 TCGv EA; \
3746 if (unlikely(!ctx->fpu_enabled)) { \
3747 gen_exception(ctx, POWERPC_EXCP_FPU); \
3748 return; \
3749 } \
3750 gen_set_access_type(ctx, ACCESS_FLOAT); \
3751 EA = tcg_temp_new(); \
3752 gen_addr_reg_index(ctx, EA); \
3753 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3754 tcg_temp_free(EA); \
3755 }
3756
3757 #define GEN_STFS(name, stop, op, type) \
3758 GEN_STF(name, stop, op | 0x20, type); \
3759 GEN_STUF(name, stop, op | 0x21, type); \
3760 GEN_STUXF(name, stop, op | 0x01, type); \
3761 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3762
3763 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3764 {
3765 TCGv_i32 t0 = tcg_temp_new_i32();
3766 TCGv t1 = tcg_temp_new();
3767 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3768 tcg_gen_extu_i32_tl(t1, t0);
3769 tcg_temp_free_i32(t0);
3770 gen_qemu_st32(ctx, t1, arg2);
3771 tcg_temp_free(t1);
3772 }
3773
3774 /* stfd stfdu stfdux stfdx */
3775 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3776 /* stfs stfsu stfsux stfsx */
3777 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3778
3779 /* stfdp */
3780 static void gen_stfdp(DisasContext *ctx)
3781 {
3782 TCGv EA;
3783 if (unlikely(!ctx->fpu_enabled)) {
3784 gen_exception(ctx, POWERPC_EXCP_FPU);
3785 return;
3786 }
3787 gen_set_access_type(ctx, ACCESS_FLOAT);
3788 EA = tcg_temp_new();
3789 gen_addr_imm_index(ctx, EA, 0);
3790 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3791 64-bit byteswap already. */
3792 if (unlikely(ctx->le_mode)) {
3793 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3794 tcg_gen_addi_tl(EA, EA, 8);
3795 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3796 } else {
3797 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3798 tcg_gen_addi_tl(EA, EA, 8);
3799 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3800 }
3801 tcg_temp_free(EA);
3802 }
3803
3804 /* stfdpx */
3805 static void gen_stfdpx(DisasContext *ctx)
3806 {
3807 TCGv EA;
3808 if (unlikely(!ctx->fpu_enabled)) {
3809 gen_exception(ctx, POWERPC_EXCP_FPU);
3810 return;
3811 }
3812 gen_set_access_type(ctx, ACCESS_FLOAT);
3813 EA = tcg_temp_new();
3814 gen_addr_reg_index(ctx, EA);
3815 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3816 64-bit byteswap already. */
3817 if (unlikely(ctx->le_mode)) {
3818 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3819 tcg_gen_addi_tl(EA, EA, 8);
3820 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3821 } else {
3822 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3823 tcg_gen_addi_tl(EA, EA, 8);
3824 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3825 }
3826 tcg_temp_free(EA);
3827 }
3828
3829 /* Optional: */
3830 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3831 {
3832 TCGv t0 = tcg_temp_new();
3833 tcg_gen_trunc_i64_tl(t0, arg1),
3834 gen_qemu_st32(ctx, t0, arg2);
3835 tcg_temp_free(t0);
3836 }
3837 /* stfiwx */
3838 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3839
3840 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3841 {
3842 #if defined(TARGET_PPC64)
3843 if (ctx->has_cfar)
3844 tcg_gen_movi_tl(cpu_cfar, nip);
3845 #endif
3846 }
3847
3848 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3849 {
3850 if (unlikely(ctx->singlestep_enabled)) {
3851 return false;
3852 }
3853
3854 #ifndef CONFIG_USER_ONLY
3855 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3856 #else
3857 return true;
3858 #endif
3859 }
3860
3861 /*** Branch ***/
3862 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3863 {
3864 if (NARROW_MODE(ctx)) {
3865 dest = (uint32_t) dest;
3866 }
3867 if (use_goto_tb(ctx, dest)) {
3868 tcg_gen_goto_tb(n);
3869 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3870 tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
3871 } else {
3872 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3873 if (unlikely(ctx->singlestep_enabled)) {
3874 if ((ctx->singlestep_enabled &
3875 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3876 (ctx->exception == POWERPC_EXCP_BRANCH ||
3877 ctx->exception == POWERPC_EXCP_TRACE)) {
3878 target_ulong tmp = ctx->nip;
3879 ctx->nip = dest;
3880 gen_exception(ctx, POWERPC_EXCP_TRACE);
3881 ctx->nip = tmp;
3882 }
3883 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3884 gen_debug_exception(ctx);
3885 }
3886 }
3887 tcg_gen_exit_tb(0);
3888 }
3889 }
3890
3891 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3892 {
3893 if (NARROW_MODE(ctx)) {
3894 nip = (uint32_t)nip;
3895 }
3896 tcg_gen_movi_tl(cpu_lr, nip);
3897 }
3898
3899 /* b ba bl bla */
3900 static void gen_b(DisasContext *ctx)
3901 {
3902 target_ulong li, target;
3903
3904 ctx->exception = POWERPC_EXCP_BRANCH;
3905 /* sign extend LI */
3906 li = LI(ctx->opcode);
3907 li = (li ^ 0x02000000) - 0x02000000;
3908 if (likely(AA(ctx->opcode) == 0)) {
3909 target = ctx->nip + li - 4;
3910 } else {
3911 target = li;
3912 }
3913 if (LK(ctx->opcode)) {
3914 gen_setlr(ctx, ctx->nip);
3915 }
3916 gen_update_cfar(ctx, ctx->nip);
3917 gen_goto_tb(ctx, 0, target);
3918 }
3919
3920 #define BCOND_IM 0
3921 #define BCOND_LR 1
3922 #define BCOND_CTR 2
3923 #define BCOND_TAR 3
3924
3925 static inline void gen_bcond(DisasContext *ctx, int type)
3926 {
3927 uint32_t bo = BO(ctx->opcode);
3928 TCGLabel *l1;
3929 TCGv target;
3930
3931 ctx->exception = POWERPC_EXCP_BRANCH;
3932 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3933 target = tcg_temp_local_new();
3934 if (type == BCOND_CTR)
3935 tcg_gen_mov_tl(target, cpu_ctr);
3936 else if (type == BCOND_TAR)
3937 gen_load_spr(target, SPR_TAR);
3938 else
3939 tcg_gen_mov_tl(target, cpu_lr);
3940 } else {
3941 TCGV_UNUSED(target);
3942 }
3943 if (LK(ctx->opcode))
3944 gen_setlr(ctx, ctx->nip);
3945 l1 = gen_new_label();
3946 if ((bo & 0x4) == 0) {
3947 /* Decrement and test CTR */
3948 TCGv temp = tcg_temp_new();
3949 if (unlikely(type == BCOND_CTR)) {
3950 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3951 return;
3952 }
3953 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3954 if (NARROW_MODE(ctx)) {
3955 tcg_gen_ext32u_tl(temp, cpu_ctr);
3956 } else {
3957 tcg_gen_mov_tl(temp, cpu_ctr);
3958 }
3959 if (bo & 0x2) {
3960 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3961 } else {
3962 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3963 }
3964 tcg_temp_free(temp);
3965 }
3966 if ((bo & 0x10) == 0) {
3967 /* Test CR */
3968 uint32_t bi = BI(ctx->opcode);
3969 uint32_t mask = 0x08 >> (bi & 0x03);
3970 TCGv_i32 temp = tcg_temp_new_i32();
3971
3972 if (bo & 0x8) {
3973 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3974 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3975 } else {
3976 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3977 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3978 }
3979 tcg_temp_free_i32(temp);
3980 }
3981 gen_update_cfar(ctx, ctx->nip);
3982 if (type == BCOND_IM) {
3983 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3984 if (likely(AA(ctx->opcode) == 0)) {
3985 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3986 } else {
3987 gen_goto_tb(ctx, 0, li);
3988 }
3989 gen_set_label(l1);
3990 gen_goto_tb(ctx, 1, ctx->nip);
3991 } else {
3992 if (NARROW_MODE(ctx)) {
3993 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3994 } else {
3995 tcg_gen_andi_tl(cpu_nip, target, ~3);
3996 }
3997 tcg_gen_exit_tb(0);
3998 gen_set_label(l1);
3999 gen_update_nip(ctx, ctx->nip);
4000 tcg_gen_exit_tb(0);
4001 }
4002 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
4003 tcg_temp_free(target);
4004 }
4005 }
4006
4007 static void gen_bc(DisasContext *ctx)
4008 {
4009 gen_bcond(ctx, BCOND_IM);
4010 }
4011
4012 static void gen_bcctr(DisasContext *ctx)
4013 {
4014 gen_bcond(ctx, BCOND_CTR);
4015 }
4016
4017 static void gen_bclr(DisasContext *ctx)
4018 {
4019 gen_bcond(ctx, BCOND_LR);
4020 }
4021
4022 static void gen_bctar(DisasContext *ctx)
4023 {
4024 gen_bcond(ctx, BCOND_TAR);
4025 }
4026
4027 /*** Condition register logical ***/
4028 #define GEN_CRLOGIC(name, tcg_op, opc) \
4029 static void glue(gen_, name)(DisasContext *ctx) \
4030 { \
4031 uint8_t bitmask; \
4032 int sh; \
4033 TCGv_i32 t0, t1; \
4034 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
4035 t0 = tcg_temp_new_i32(); \
4036 if (sh > 0) \
4037 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
4038 else if (sh < 0) \
4039 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
4040 else \
4041 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
4042 t1 = tcg_temp_new_i32(); \
4043 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
4044 if (sh > 0) \
4045 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
4046 else if (sh < 0) \
4047 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
4048 else \
4049 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
4050 tcg_op(t0, t0, t1); \
4051 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
4052 tcg_gen_andi_i32(t0, t0, bitmask); \
4053 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
4054 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
4055 tcg_temp_free_i32(t0); \
4056 tcg_temp_free_i32(t1); \
4057 }
4058
4059 /* crand */
4060 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
4061 /* crandc */
4062 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
4063 /* creqv */
4064 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
4065 /* crnand */
4066 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
4067 /* crnor */
4068 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
4069 /* cror */
4070 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
4071 /* crorc */
4072 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
4073 /* crxor */
4074 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
4075
4076 /* mcrf */
4077 static void gen_mcrf(DisasContext *ctx)
4078 {
4079 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
4080 }
4081
4082 /*** System linkage ***/
4083
4084 /* rfi (supervisor only) */
4085 static void gen_rfi(DisasContext *ctx)
4086 {
4087 #if defined(CONFIG_USER_ONLY)
4088 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4089 #else
4090 /* Restore CPU state */
4091 if (unlikely(ctx->pr)) {
4092 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4093 return;
4094 }
4095 gen_update_cfar(ctx, ctx->nip);
4096 gen_helper_rfi(cpu_env);
4097 gen_sync_exception(ctx);
4098 #endif
4099 }
4100
4101 #if defined(TARGET_PPC64)
4102 static void gen_rfid(DisasContext *ctx)
4103 {
4104 #if defined(CONFIG_USER_ONLY)
4105 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4106 #else
4107 /* Restore CPU state */
4108 if (unlikely(ctx->pr)) {
4109 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4110 return;
4111 }
4112 gen_update_cfar(ctx, ctx->nip);
4113 gen_helper_rfid(cpu_env);
4114 gen_sync_exception(ctx);
4115 #endif
4116 }
4117
4118 static void gen_hrfid(DisasContext *ctx)
4119 {
4120 #if defined(CONFIG_USER_ONLY)
4121 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4122 #else
4123 /* Restore CPU state */
4124 if (unlikely(ctx->pr || !ctx->hv)) {
4125 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4126 return;
4127 }
4128 gen_helper_hrfid(cpu_env);
4129 gen_sync_exception(ctx);
4130 #endif
4131 }
4132 #endif
4133
4134 /* sc */
4135 #if defined(CONFIG_USER_ONLY)
4136 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4137 #else
4138 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4139 #endif
4140 static void gen_sc(DisasContext *ctx)
4141 {
4142 uint32_t lev;
4143
4144 lev = (ctx->opcode >> 5) & 0x7F;
4145 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
4146 }
4147
4148 /*** Trap ***/
4149
4150 /* tw */
4151 static void gen_tw(DisasContext *ctx)
4152 {
4153 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4154 /* Update the nip since this might generate a trap exception */
4155 gen_update_nip(ctx, ctx->nip);
4156 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4157 t0);
4158 tcg_temp_free_i32(t0);
4159 }
4160
4161 /* twi */
4162 static void gen_twi(DisasContext *ctx)
4163 {
4164 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4165 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4166 /* Update the nip since this might generate a trap exception */
4167 gen_update_nip(ctx, ctx->nip);
4168 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4169 tcg_temp_free(t0);
4170 tcg_temp_free_i32(t1);
4171 }
4172
4173 #if defined(TARGET_PPC64)
4174 /* td */
4175 static void gen_td(DisasContext *ctx)
4176 {
4177 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4178 /* Update the nip since this might generate a trap exception */
4179 gen_update_nip(ctx, ctx->nip);
4180 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4181 t0);
4182 tcg_temp_free_i32(t0);
4183 }
4184
4185 /* tdi */
4186 static void gen_tdi(DisasContext *ctx)
4187 {
4188 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4189 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4190 /* Update the nip since this might generate a trap exception */
4191 gen_update_nip(ctx, ctx->nip);
4192 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4193 tcg_temp_free(t0);
4194 tcg_temp_free_i32(t1);
4195 }
4196 #endif
4197
4198 /*** Processor control ***/
4199
4200 static void gen_read_xer(TCGv dst)
4201 {
4202 TCGv t0 = tcg_temp_new();
4203 TCGv t1 = tcg_temp_new();
4204 TCGv t2 = tcg_temp_new();
4205 tcg_gen_mov_tl(dst, cpu_xer);
4206 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4207 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4208 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4209 tcg_gen_or_tl(t0, t0, t1);
4210 tcg_gen_or_tl(dst, dst, t2);
4211 tcg_gen_or_tl(dst, dst, t0);
4212 tcg_temp_free(t0);
4213 tcg_temp_free(t1);
4214 tcg_temp_free(t2);
4215 }
4216
4217 static void gen_write_xer(TCGv src)
4218 {
4219 tcg_gen_andi_tl(cpu_xer, src,
4220 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
4221 tcg_gen_shri_tl(cpu_so, src, XER_SO);
4222 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
4223 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
4224 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
4225 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
4226 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
4227 }
4228
4229 /* mcrxr */
4230 static void gen_mcrxr(DisasContext *ctx)
4231 {
4232 TCGv_i32 t0 = tcg_temp_new_i32();
4233 TCGv_i32 t1 = tcg_temp_new_i32();
4234 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4235
4236 tcg_gen_trunc_tl_i32(t0, cpu_so);
4237 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4238 tcg_gen_trunc_tl_i32(dst, cpu_ca);
4239 tcg_gen_shli_i32(t0, t0, 3);
4240 tcg_gen_shli_i32(t1, t1, 2);
4241 tcg_gen_shli_i32(dst, dst, 1);
4242 tcg_gen_or_i32(dst, dst, t0);
4243 tcg_gen_or_i32(dst, dst, t1);
4244 tcg_temp_free_i32(t0);
4245 tcg_temp_free_i32(t1);
4246
4247 tcg_gen_movi_tl(cpu_so, 0);
4248 tcg_gen_movi_tl(cpu_ov, 0);
4249 tcg_gen_movi_tl(cpu_ca, 0);
4250 }
4251
4252 /* mfcr mfocrf */
4253 static void gen_mfcr(DisasContext *ctx)
4254 {
4255 uint32_t crm, crn;
4256
4257 if (likely(ctx->opcode & 0x00100000)) {
4258 crm = CRM(ctx->opcode);
4259 if (likely(crm && ((crm & (crm - 1)) == 0))) {
4260 crn = ctz32 (crm);
4261 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4262 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4263 cpu_gpr[rD(ctx->opcode)], crn * 4);
4264 }
4265 } else {
4266 TCGv_i32 t0 = tcg_temp_new_i32();
4267 tcg_gen_mov_i32(t0, cpu_crf[0]);
4268 tcg_gen_shli_i32(t0, t0, 4);
4269 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4270 tcg_gen_shli_i32(t0, t0, 4);
4271 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4272 tcg_gen_shli_i32(t0, t0, 4);
4273 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4274 tcg_gen_shli_i32(t0, t0, 4);
4275 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4276 tcg_gen_shli_i32(t0, t0, 4);
4277 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4278 tcg_gen_shli_i32(t0, t0, 4);
4279 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4280 tcg_gen_shli_i32(t0, t0, 4);
4281 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4282 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4283 tcg_temp_free_i32(t0);
4284 }
4285 }
4286
4287 /* mfmsr */
4288 static void gen_mfmsr(DisasContext *ctx)
4289 {
4290 #if defined(CONFIG_USER_ONLY)
4291 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4292 #else
4293 if (unlikely(ctx->pr)) {
4294 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4295 return;
4296 }
4297 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4298 #endif
4299 }
4300
4301 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
4302 {
4303 #if 0
4304 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4305 printf("ERROR: try to access SPR %d !\n", sprn);
4306 #endif
4307 }
4308 #define SPR_NOACCESS (&spr_noaccess)
4309
4310 /* mfspr */
4311 static inline void gen_op_mfspr(DisasContext *ctx)
4312 {
4313 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
4314 uint32_t sprn = SPR(ctx->opcode);
4315
4316 #if defined(CONFIG_USER_ONLY)
4317 read_cb = ctx->spr_cb[sprn].uea_read;
4318 #else
4319 if (ctx->pr) {
4320 read_cb = ctx->spr_cb[sprn].uea_read;
4321 } else if (ctx->hv) {
4322 read_cb = ctx->spr_cb[sprn].hea_read;
4323 } else {
4324 read_cb = ctx->spr_cb[sprn].oea_read;
4325 }
4326 #endif
4327 if (likely(read_cb != NULL)) {
4328 if (likely(read_cb != SPR_NOACCESS)) {
4329 (*read_cb)(ctx, rD(ctx->opcode), sprn);
4330 } else {
4331 /* Privilege exception */
4332 /* This is a hack to avoid warnings when running Linux:
4333 * this OS breaks the PowerPC virtualisation model,
4334 * allowing userland application to read the PVR
4335 */
4336 if (sprn != SPR_PVR) {
4337 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
4338 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4339 if (qemu_log_separate()) {
4340 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4341 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4342 }
4343 }
4344 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4345 }
4346 } else {
4347 /* Not defined */
4348 fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at "
4349 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4350 if (qemu_log_separate()) {
4351 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4352 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4353 }
4354 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4355 }
4356 }
4357
4358 static void gen_mfspr(DisasContext *ctx)
4359 {
4360 gen_op_mfspr(ctx);
4361 }
4362
4363 /* mftb */
4364 static void gen_mftb(DisasContext *ctx)
4365 {
4366 gen_op_mfspr(ctx);
4367 }
4368
4369 /* mtcrf mtocrf*/
4370 static void gen_mtcrf(DisasContext *ctx)
4371 {
4372 uint32_t crm, crn;
4373
4374 crm = CRM(ctx->opcode);
4375 if (likely((ctx->opcode & 0x00100000))) {
4376 if (crm && ((crm & (crm - 1)) == 0)) {
4377 TCGv_i32 temp = tcg_temp_new_i32();
4378 crn = ctz32 (crm);
4379 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4380 tcg_gen_shri_i32(temp, temp, crn * 4);
4381 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4382 tcg_temp_free_i32(temp);
4383 }
4384 } else {
4385 TCGv_i32 temp = tcg_temp_new_i32();
4386 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4387 for (crn = 0 ; crn < 8 ; crn++) {
4388 if (crm & (1 << crn)) {
4389 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4390 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4391 }
4392 }
4393 tcg_temp_free_i32(temp);
4394 }
4395 }
4396
4397 /* mtmsr */
4398 #if defined(TARGET_PPC64)
4399 static void gen_mtmsrd(DisasContext *ctx)
4400 {
4401 #if defined(CONFIG_USER_ONLY)
4402 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4403 #else
4404 if (unlikely(ctx->pr)) {
4405 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4406 return;
4407 }
4408 if (ctx->opcode & 0x00010000) {
4409 /* Special form that does not need any synchronisation */
4410 TCGv t0 = tcg_temp_new();
4411 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4412 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4413 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4414 tcg_temp_free(t0);
4415 } else {
4416 /* XXX: we need to update nip before the store
4417 * if we enter power saving mode, we will exit the loop
4418 * directly from ppc_store_msr
4419 */
4420 gen_update_nip(ctx, ctx->nip);
4421 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4422 /* Must stop the translation as machine state (may have) changed */
4423 /* Note that mtmsr is not always defined as context-synchronizing */
4424 gen_stop_exception(ctx);
4425 }
4426 #endif
4427 }
4428 #endif
4429
4430 static void gen_mtmsr(DisasContext *ctx)
4431 {
4432 #if defined(CONFIG_USER_ONLY)
4433 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4434 #else
4435 if (unlikely(ctx->pr)) {
4436 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4437 return;
4438 }
4439 if (ctx->opcode & 0x00010000) {
4440 /* Special form that does not need any synchronisation */
4441 TCGv t0 = tcg_temp_new();
4442 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4443 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4444 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4445 tcg_temp_free(t0);
4446 } else {
4447 TCGv msr = tcg_temp_new();
4448
4449 /* XXX: we need to update nip before the store
4450 * if we enter power saving mode, we will exit the loop
4451 * directly from ppc_store_msr
4452 */
4453 gen_update_nip(ctx, ctx->nip);
4454 #if defined(TARGET_PPC64)
4455 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4456 #else
4457 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4458 #endif
4459 gen_helper_store_msr(cpu_env, msr);
4460 tcg_temp_free(msr);
4461 /* Must stop the translation as machine state (may have) changed */
4462 /* Note that mtmsr is not always defined as context-synchronizing */
4463 gen_stop_exception(ctx);
4464 }
4465 #endif
4466 }
4467
4468 /* mtspr */
4469 static void gen_mtspr(DisasContext *ctx)
4470 {
4471 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
4472 uint32_t sprn = SPR(ctx->opcode);
4473
4474 #if defined(CONFIG_USER_ONLY)
4475 write_cb = ctx->spr_cb[sprn].uea_write;
4476 #else
4477 if (ctx->pr) {
4478 write_cb = ctx->spr_cb[sprn].uea_write;
4479 } else if (ctx->hv) {
4480 write_cb = ctx->spr_cb[sprn].hea_write;
4481 } else {
4482 write_cb = ctx->spr_cb[sprn].oea_write;
4483 }
4484 #endif
4485 if (likely(write_cb != NULL)) {
4486 if (likely(write_cb != SPR_NOACCESS)) {
4487 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4488 } else {
4489 /* Privilege exception */
4490 fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at "
4491 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4492 if (qemu_log_separate()) {
4493 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4494 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4495 }
4496 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4497 }
4498 } else {
4499 /* Not defined */
4500 if (qemu_log_separate()) {
4501 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4502 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4503 }
4504 fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
4505 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4506 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4507 }
4508 }
4509
4510 /*** Cache management ***/
4511
4512 /* dcbf */
4513 static void gen_dcbf(DisasContext *ctx)
4514 {
4515 /* XXX: specification says this is treated as a load by the MMU */
4516 TCGv t0;
4517 gen_set_access_type(ctx, ACCESS_CACHE);
4518 t0 = tcg_temp_new();
4519 gen_addr_reg_index(ctx, t0);
4520 gen_qemu_ld8u(ctx, t0, t0);
4521 tcg_temp_free(t0);
4522 }
4523
4524 /* dcbi (Supervisor only) */
4525 static void gen_dcbi(DisasContext *ctx)
4526 {
4527 #if defined(CONFIG_USER_ONLY)
4528 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4529 #else
4530 TCGv EA, val;
4531 if (unlikely(ctx->pr)) {
4532 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4533 return;
4534 }
4535 EA = tcg_temp_new();
4536 gen_set_access_type(ctx, ACCESS_CACHE);
4537 gen_addr_reg_index(ctx, EA);
4538 val = tcg_temp_new();
4539 /* XXX: specification says this should be treated as a store by the MMU */
4540 gen_qemu_ld8u(ctx, val, EA);
4541 gen_qemu_st8(ctx, val, EA);
4542 tcg_temp_free(val);
4543 tcg_temp_free(EA);
4544 #endif
4545 }
4546
4547 /* dcdst */
4548 static void gen_dcbst(DisasContext *ctx)
4549 {
4550 /* XXX: specification say this is treated as a load by the MMU */
4551 TCGv t0;
4552 gen_set_access_type(ctx, ACCESS_CACHE);
4553 t0 = tcg_temp_new();
4554 gen_addr_reg_index(ctx, t0);
4555 gen_qemu_ld8u(ctx, t0, t0);
4556 tcg_temp_free(t0);
4557 }
4558
4559 /* dcbt */
4560 static void gen_dcbt(DisasContext *ctx)
4561 {
4562 /* interpreted as no-op */
4563 /* XXX: specification say this is treated as a load by the MMU
4564 * but does not generate any exception
4565 */
4566 }
4567
4568 /* dcbtst */
4569 static void gen_dcbtst(DisasContext *ctx)
4570 {
4571 /* interpreted as no-op */
4572 /* XXX: specification say this is treated as a load by the MMU
4573 * but does not generate any exception
4574 */
4575 }
4576
4577 /* dcbtls */
4578 static void gen_dcbtls(DisasContext *ctx)
4579 {
4580 /* Always fails locking the cache */
4581 TCGv t0 = tcg_temp_new();
4582 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4583 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4584 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4585 tcg_temp_free(t0);
4586 }
4587
4588 /* dcbz */
4589 static void gen_dcbz(DisasContext *ctx)
4590 {
4591 TCGv tcgv_addr;
4592 TCGv_i32 tcgv_is_dcbzl;
4593 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4594
4595 gen_set_access_type(ctx, ACCESS_CACHE);
4596 /* NIP cannot be restored if the memory exception comes from an helper */
4597 gen_update_nip(ctx, ctx->nip - 4);
4598 tcgv_addr = tcg_temp_new();
4599 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4600
4601 gen_addr_reg_index(ctx, tcgv_addr);
4602 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4603
4604 tcg_temp_free(tcgv_addr);
4605 tcg_temp_free_i32(tcgv_is_dcbzl);
4606 }
4607
4608 /* dst / dstt */
4609 static void gen_dst(DisasContext *ctx)
4610 {
4611 if (rA(ctx->opcode) == 0) {
4612 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4613 } else {
4614 /* interpreted as no-op */
4615 }
4616 }
4617
4618 /* dstst /dststt */
4619 static void gen_dstst(DisasContext *ctx)
4620 {
4621 if (rA(ctx->opcode) == 0) {
4622 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4623 } else {
4624 /* interpreted as no-op */
4625 }
4626
4627 }
4628
4629 /* dss / dssall */
4630 static void gen_dss(DisasContext *ctx)
4631 {
4632 /* interpreted as no-op */
4633 }
4634
4635 /* icbi */
4636 static void gen_icbi(DisasContext *ctx)
4637 {
4638 TCGv t0;
4639 gen_set_access_type(ctx, ACCESS_CACHE);
4640 /* NIP cannot be restored if the memory exception comes from an helper */
4641 gen_update_nip(ctx, ctx->nip - 4);
4642 t0 = tcg_temp_new();
4643 gen_addr_reg_index(ctx, t0);
4644 gen_helper_icbi(cpu_env, t0);
4645 tcg_temp_free(t0);
4646 }
4647
4648 /* Optional: */
4649 /* dcba */
4650 static void gen_dcba(DisasContext *ctx)
4651 {
4652 /* interpreted as no-op */
4653 /* XXX: specification say this is treated as a store by the MMU
4654 * but does not generate any exception
4655 */
4656 }
4657
4658 /*** Segment register manipulation ***/
4659 /* Supervisor only: */
4660
4661 /* mfsr */
4662 static void gen_mfsr(DisasContext *ctx)
4663 {
4664 #if defined(CONFIG_USER_ONLY)
4665 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4666 #else
4667 TCGv t0;
4668 if (unlikely(ctx->pr)) {
4669 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4670 return;
4671 }
4672 t0 = tcg_const_tl(SR(ctx->opcode));
4673 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4674 tcg_temp_free(t0);
4675 #endif
4676 }
4677
4678 /* mfsrin */
4679 static void gen_mfsrin(DisasContext *ctx)
4680 {
4681 #if defined(CONFIG_USER_ONLY)
4682 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4683 #else
4684 TCGv t0;
4685 if (unlikely(ctx->pr)) {
4686 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4687 return;
4688 }
4689 t0 = tcg_temp_new();
4690 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4691 tcg_gen_andi_tl(t0, t0, 0xF);
4692 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4693 tcg_temp_free(t0);
4694 #endif
4695 }
4696
4697 /* mtsr */
4698 static void gen_mtsr(DisasContext *ctx)
4699 {
4700 #if defined(CONFIG_USER_ONLY)
4701 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4702 #else
4703 TCGv t0;
4704 if (unlikely(ctx->pr)) {
4705 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4706 return;
4707 }
4708 t0 = tcg_const_tl(SR(ctx->opcode));
4709 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4710 tcg_temp_free(t0);
4711 #endif
4712 }
4713
4714 /* mtsrin */
4715 static void gen_mtsrin(DisasContext *ctx)
4716 {
4717 #if defined(CONFIG_USER_ONLY)
4718 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4719 #else
4720 TCGv t0;
4721 if (unlikely(ctx->pr)) {
4722 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4723 return;
4724 }
4725 t0 = tcg_temp_new();
4726 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4727 tcg_gen_andi_tl(t0, t0, 0xF);
4728 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4729 tcg_temp_free(t0);
4730 #endif
4731 }
4732
4733 #if defined(TARGET_PPC64)
4734 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4735
4736 /* mfsr */
4737 static void gen_mfsr_64b(DisasContext *ctx)
4738 {
4739 #if defined(CONFIG_USER_ONLY)
4740 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4741 #else
4742 TCGv t0;
4743 if (unlikely(ctx->pr)) {
4744 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4745 return;
4746 }
4747 t0 = tcg_const_tl(SR(ctx->opcode));
4748 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4749 tcg_temp_free(t0);
4750 #endif
4751 }
4752
4753 /* mfsrin */
4754 static void gen_mfsrin_64b(DisasContext *ctx)
4755 {
4756 #if defined(CONFIG_USER_ONLY)
4757 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4758 #else
4759 TCGv t0;
4760 if (unlikely(ctx->pr)) {
4761 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4762 return;
4763 }
4764 t0 = tcg_temp_new();
4765 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4766 tcg_gen_andi_tl(t0, t0, 0xF);
4767 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4768 tcg_temp_free(t0);
4769 #endif
4770 }
4771
4772 /* mtsr */
4773 static void gen_mtsr_64b(DisasContext *ctx)
4774 {
4775 #if defined(CONFIG_USER_ONLY)
4776 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4777 #else
4778 TCGv t0;
4779 if (unlikely(ctx->pr)) {
4780 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4781 return;
4782 }
4783 t0 = tcg_const_tl(SR(ctx->opcode));
4784 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4785 tcg_temp_free(t0);
4786 #endif
4787 }
4788
4789 /* mtsrin */
4790 static void gen_mtsrin_64b(DisasContext *ctx)
4791 {
4792 #if defined(CONFIG_USER_ONLY)
4793 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4794 #else
4795 TCGv t0;
4796 if (unlikely(ctx->pr)) {
4797 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4798 return;
4799 }
4800 t0 = tcg_temp_new();
4801 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4802 tcg_gen_andi_tl(t0, t0, 0xF);
4803 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4804 tcg_temp_free(t0);
4805 #endif
4806 }
4807
4808 /* slbmte */
4809 static void gen_slbmte(DisasContext *ctx)
4810 {
4811 #if defined(CONFIG_USER_ONLY)
4812 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4813 #else
4814 if (unlikely(ctx->pr)) {
4815 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4816 return;
4817 }
4818 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4819 cpu_gpr[rS(ctx->opcode)]);
4820 #endif
4821 }
4822
4823 static void gen_slbmfee(DisasContext *ctx)
4824 {
4825 #if defined(CONFIG_USER_ONLY)
4826 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4827 #else
4828 if (unlikely(ctx->pr)) {
4829 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4830 return;
4831 }
4832 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4833 cpu_gpr[rB(ctx->opcode)]);
4834 #endif
4835 }
4836
4837 static void gen_slbmfev(DisasContext *ctx)
4838 {
4839 #if defined(CONFIG_USER_ONLY)
4840 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4841 #else
4842 if (unlikely(ctx->pr)) {
4843 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4844 return;
4845 }
4846 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4847 cpu_gpr[rB(ctx->opcode)]);
4848 #endif
4849 }
4850 #endif /* defined(TARGET_PPC64) */
4851
4852 /*** Lookaside buffer management ***/
4853 /* Optional & supervisor only: */
4854
4855 /* tlbia */
4856 static void gen_tlbia(DisasContext *ctx)
4857 {
4858 #if defined(CONFIG_USER_ONLY)
4859 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4860 #else
4861 if (unlikely(ctx->pr || !ctx->hv)) {
4862 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4863 return;
4864 }
4865 gen_helper_tlbia(cpu_env);
4866 #endif
4867 }
4868
4869 /* tlbiel */
4870 static void gen_tlbiel(DisasContext *ctx)
4871 {
4872 #if defined(CONFIG_USER_ONLY)
4873 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4874 #else
4875 if (unlikely(ctx->pr)) {
4876 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4877 return;
4878 }
4879 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4880 #endif
4881 }
4882
4883 /* tlbie */
4884 static void gen_tlbie(DisasContext *ctx)
4885 {
4886 #if defined(CONFIG_USER_ONLY)
4887 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4888 #else
4889 if (unlikely(ctx->pr || !ctx->hv)) {
4890 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4891 return;
4892 }
4893 if (NARROW_MODE(ctx)) {
4894 TCGv t0 = tcg_temp_new();
4895 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4896 gen_helper_tlbie(cpu_env, t0);
4897 tcg_temp_free(t0);
4898 } else {
4899 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4900 }
4901 #endif
4902 }
4903
4904 /* tlbsync */
4905 static void gen_tlbsync(DisasContext *ctx)
4906 {
4907 #if defined(CONFIG_USER_ONLY)
4908 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4909 #else
4910 if (unlikely(ctx->pr || !ctx->hv)) {
4911 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4912 return;
4913 }
4914 /* tlbsync is a nop for server, ptesync handles delayed tlb flush,
4915 * embedded however needs to deal with tlbsync. We don't try to be
4916 * fancy and swallow the overhead of checking for both.
4917 */
4918 gen_check_tlb_flush(ctx);
4919 #endif
4920 }
4921
4922 #if defined(TARGET_PPC64)
4923 /* slbia */
4924 static void gen_slbia(DisasContext *ctx)
4925 {
4926 #if defined(CONFIG_USER_ONLY)
4927 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4928 #else
4929 if (unlikely(ctx->pr)) {
4930 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4931 return;
4932 }
4933 gen_helper_slbia(cpu_env);
4934 #endif
4935 }
4936
4937 /* slbie */
4938 static void gen_slbie(DisasContext *ctx)
4939 {
4940 #if defined(CONFIG_USER_ONLY)
4941 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4942 #else
4943 if (unlikely(ctx->pr)) {
4944 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4945 return;
4946 }
4947 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4948 #endif
4949 }
4950 #endif
4951
4952 /*** External control ***/
4953 /* Optional: */
4954
4955 /* eciwx */
4956 static void gen_eciwx(DisasContext *ctx)
4957 {
4958 TCGv t0;
4959 /* Should check EAR[E] ! */
4960 gen_set_access_type(ctx, ACCESS_EXT);
4961 t0 = tcg_temp_new();
4962 gen_addr_reg_index(ctx, t0);
4963 gen_check_align(ctx, t0, 0x03);
4964 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4965 tcg_temp_free(t0);
4966 }
4967
4968 /* ecowx */
4969 static void gen_ecowx(DisasContext *ctx)
4970 {
4971 TCGv t0;
4972 /* Should check EAR[E] ! */
4973 gen_set_access_type(ctx, ACCESS_EXT);
4974 t0 = tcg_temp_new();
4975 gen_addr_reg_index(ctx, t0);
4976 gen_check_align(ctx, t0, 0x03);
4977 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4978 tcg_temp_free(t0);
4979 }
4980
4981 /* PowerPC 601 specific instructions */
4982
4983 /* abs - abs. */
4984 static void gen_abs(DisasContext *ctx)
4985 {
4986 TCGLabel *l1 = gen_new_label();
4987 TCGLabel *l2 = gen_new_label();
4988 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4989 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4990 tcg_gen_br(l2);
4991 gen_set_label(l1);
4992 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4993 gen_set_label(l2);
4994 if (unlikely(Rc(ctx->opcode) != 0))
4995 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4996 }
4997
4998 /* abso - abso. */
4999 static void gen_abso(DisasContext *ctx)
5000 {
5001 TCGLabel *l1 = gen_new_label();
5002 TCGLabel *l2 = gen_new_label();
5003 TCGLabel *l3 = gen_new_label();
5004 /* Start with XER OV disabled, the most likely case */
5005 tcg_gen_movi_tl(cpu_ov, 0);
5006 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
5007 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
5008 tcg_gen_movi_tl(cpu_ov, 1);
5009 tcg_gen_movi_tl(cpu_so, 1);
5010 tcg_gen_br(l2);
5011 gen_set_label(l1);
5012 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5013 tcg_gen_br(l3);
5014 gen_set_label(l2);
5015 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5016 gen_set_label(l3);
5017 if (unlikely(Rc(ctx->opcode) != 0))
5018 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5019 }
5020
5021 /* clcs */
5022 static void gen_clcs(DisasContext *ctx)
5023 {
5024 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
5025 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5026 tcg_temp_free_i32(t0);
5027 /* Rc=1 sets CR0 to an undefined state */
5028 }
5029
5030 /* div - div. */
5031 static void gen_div(DisasContext *ctx)
5032 {
5033 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5034 cpu_gpr[rB(ctx->opcode)]);
5035 if (unlikely(Rc(ctx->opcode) != 0))
5036 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5037 }
5038
5039 /* divo - divo. */
5040 static void gen_divo(DisasContext *ctx)
5041 {
5042 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5043 cpu_gpr[rB(ctx->opcode)]);
5044 if (unlikely(Rc(ctx->opcode) != 0))
5045 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5046 }
5047
5048 /* divs - divs. */
5049 static void gen_divs(DisasContext *ctx)
5050 {
5051 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5052 cpu_gpr[rB(ctx->opcode)]);
5053 if (unlikely(Rc(ctx->opcode) != 0))
5054 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5055 }
5056
5057 /* divso - divso. */
5058 static void gen_divso(DisasContext *ctx)
5059 {
5060 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
5061 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5062 if (unlikely(Rc(ctx->opcode) != 0))
5063 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5064 }
5065
5066 /* doz - doz. */
5067 static void gen_doz(DisasContext *ctx)
5068 {
5069 TCGLabel *l1 = gen_new_label();
5070 TCGLabel *l2 = gen_new_label();
5071 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5072 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5073 tcg_gen_br(l2);
5074 gen_set_label(l1);
5075 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5076 gen_set_label(l2);
5077 if (unlikely(Rc(ctx->opcode) != 0))
5078 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5079 }
5080
5081 /* dozo - dozo. */
5082 static void gen_dozo(DisasContext *ctx)
5083 {
5084 TCGLabel *l1 = gen_new_label();
5085 TCGLabel *l2 = gen_new_label();
5086 TCGv t0 = tcg_temp_new();
5087 TCGv t1 = tcg_temp_new();
5088 TCGv t2 = tcg_temp_new();
5089 /* Start with XER OV disabled, the most likely case */
5090 tcg_gen_movi_tl(cpu_ov, 0);
5091 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5092 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5093 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5094 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
5095 tcg_gen_andc_tl(t1, t1, t2);
5096 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
5097 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5098 tcg_gen_movi_tl(cpu_ov, 1);
5099 tcg_gen_movi_tl(cpu_so, 1);
5100 tcg_gen_br(l2);
5101 gen_set_label(l1);
5102 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5103 gen_set_label(l2);
5104 tcg_temp_free(t0);
5105 tcg_temp_free(t1);
5106 tcg_temp_free(t2);
5107 if (unlikely(Rc(ctx->opcode) != 0))
5108 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5109 }
5110
5111 /* dozi */
5112 static void gen_dozi(DisasContext *ctx)
5113 {
5114 target_long simm = SIMM(ctx->opcode);
5115 TCGLabel *l1 = gen_new_label();
5116 TCGLabel *l2 = gen_new_label();
5117 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
5118 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
5119 tcg_gen_br(l2);
5120 gen_set_label(l1);
5121 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5122 gen_set_label(l2);
5123 if (unlikely(Rc(ctx->opcode) != 0))
5124 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5125 }
5126
5127 /* lscbx - lscbx. */
5128 static void gen_lscbx(DisasContext *ctx)
5129 {
5130 TCGv t0 = tcg_temp_new();
5131 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
5132 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
5133 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
5134
5135 gen_addr_reg_index(ctx, t0);
5136 /* NIP cannot be restored if the memory exception comes from an helper */
5137 gen_update_nip(ctx, ctx->nip - 4);
5138 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
5139 tcg_temp_free_i32(t1);
5140 tcg_temp_free_i32(t2);
5141 tcg_temp_free_i32(t3);
5142 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5143 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
5144 if (unlikely(Rc(ctx->opcode) != 0))
5145 gen_set_Rc0(ctx, t0);
5146 tcg_temp_free(t0);
5147 }
5148
5149 /* maskg - maskg. */
5150 static void gen_maskg(DisasContext *ctx)
5151 {
5152 TCGLabel *l1 = gen_new_label();
5153 TCGv t0 = tcg_temp_new();
5154 TCGv t1 = tcg_temp_new();
5155 TCGv t2 = tcg_temp_new();
5156 TCGv t3 = tcg_temp_new();
5157 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5158 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5159 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5160 tcg_gen_addi_tl(t2, t0, 1);
5161 tcg_gen_shr_tl(t2, t3, t2);
5162 tcg_gen_shr_tl(t3, t3, t1);
5163 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5164 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5165 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5166 gen_set_label(l1);
5167 tcg_temp_free(t0);
5168 tcg_temp_free(t1);
5169 tcg_temp_free(t2);
5170 tcg_temp_free(t3);
5171 if (unlikely(Rc(ctx->opcode) != 0))
5172 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5173 }
5174
5175 /* maskir - maskir. */
5176 static void gen_maskir(DisasContext *ctx)
5177 {
5178 TCGv t0 = tcg_temp_new();
5179 TCGv t1 = tcg_temp_new();
5180 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5181 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5182 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5183 tcg_temp_free(t0);
5184 tcg_temp_free(t1);
5185 if (unlikely(Rc(ctx->opcode) != 0))
5186 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5187 }
5188
5189 /* mul - mul. */
5190 static void gen_mul(DisasContext *ctx)
5191 {
5192 TCGv_i64 t0 = tcg_temp_new_i64();
5193 TCGv_i64 t1 = tcg_temp_new_i64();
5194 TCGv t2 = tcg_temp_new();
5195 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5196 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5197 tcg_gen_mul_i64(t0, t0, t1);
5198 tcg_gen_trunc_i64_tl(t2, t0);
5199 gen_store_spr(SPR_MQ, t2);
5200 tcg_gen_shri_i64(t1, t0, 32);
5201 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5202 tcg_temp_free_i64(t0);
5203 tcg_temp_free_i64(t1);
5204 tcg_temp_free(t2);
5205 if (unlikely(Rc(ctx->opcode) != 0))
5206 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5207 }
5208
5209 /* mulo - mulo. */
5210 static void gen_mulo(DisasContext *ctx)
5211 {
5212 TCGLabel *l1 = gen_new_label();
5213 TCGv_i64 t0 = tcg_temp_new_i64();
5214 TCGv_i64 t1 = tcg_temp_new_i64();
5215 TCGv t2 = tcg_temp_new();
5216 /* Start with XER OV disabled, the most likely case */
5217 tcg_gen_movi_tl(cpu_ov, 0);
5218 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5219 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5220 tcg_gen_mul_i64(t0, t0, t1);
5221 tcg_gen_trunc_i64_tl(t2, t0);
5222 gen_store_spr(SPR_MQ, t2);
5223 tcg_gen_shri_i64(t1, t0, 32);
5224 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5225 tcg_gen_ext32s_i64(t1, t0);
5226 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
5227 tcg_gen_movi_tl(cpu_ov, 1);
5228 tcg_gen_movi_tl(cpu_so, 1);
5229 gen_set_label(l1);
5230 tcg_temp_free_i64(t0);
5231 tcg_temp_free_i64(t1);
5232 tcg_temp_free(t2);
5233 if (unlikely(Rc(ctx->opcode) != 0))
5234 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5235 }
5236
5237 /* nabs - nabs. */
5238 static void gen_nabs(DisasContext *ctx)
5239 {
5240 TCGLabel *l1 = gen_new_label();
5241 TCGLabel *l2 = gen_new_label();
5242 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5243 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5244 tcg_gen_br(l2);
5245 gen_set_label(l1);
5246 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5247 gen_set_label(l2);
5248 if (unlikely(Rc(ctx->opcode) != 0))
5249 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5250 }
5251
5252 /* nabso - nabso. */
5253 static void gen_nabso(DisasContext *ctx)
5254 {
5255 TCGLabel *l1 = gen_new_label();
5256 TCGLabel *l2 = gen_new_label();
5257 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5258 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5259 tcg_gen_br(l2);
5260 gen_set_label(l1);
5261 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5262 gen_set_label(l2);
5263 /* nabs never overflows */
5264 tcg_gen_movi_tl(cpu_ov, 0);
5265 if (unlikely(Rc(ctx->opcode) != 0))
5266 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5267 }
5268
5269 /* rlmi - rlmi. */
5270 static void gen_rlmi(DisasContext *ctx)
5271 {
5272 uint32_t mb = MB(ctx->opcode);
5273 uint32_t me = ME(ctx->opcode);
5274 TCGv t0 = tcg_temp_new();
5275 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5276 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5277 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5278 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5279 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5280 tcg_temp_free(t0);
5281 if (unlikely(Rc(ctx->opcode) != 0))
5282 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5283 }
5284
5285 /* rrib - rrib. */
5286 static void gen_rrib(DisasContext *ctx)
5287 {
5288 TCGv t0 = tcg_temp_new();
5289 TCGv t1 = tcg_temp_new();
5290 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5291 tcg_gen_movi_tl(t1, 0x80000000);
5292 tcg_gen_shr_tl(t1, t1, t0);
5293 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5294 tcg_gen_and_tl(t0, t0, t1);
5295 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5296 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5297 tcg_temp_free(t0);
5298 tcg_temp_free(t1);
5299 if (unlikely(Rc(ctx->opcode) != 0))
5300 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5301 }
5302
5303 /* sle - sle. */
5304 static void gen_sle(DisasContext *ctx)
5305 {
5306 TCGv t0 = tcg_temp_new();
5307 TCGv t1 = tcg_temp_new();
5308 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5309 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5310 tcg_gen_subfi_tl(t1, 32, t1);
5311 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5312 tcg_gen_or_tl(t1, t0, t1);
5313 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5314 gen_store_spr(SPR_MQ, t1);
5315 tcg_temp_free(t0);
5316 tcg_temp_free(t1);
5317 if (unlikely(Rc(ctx->opcode) != 0))
5318 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5319 }
5320
5321 /* sleq - sleq. */
5322 static void gen_sleq(DisasContext *ctx)
5323 {
5324 TCGv t0 = tcg_temp_new();
5325 TCGv t1 = tcg_temp_new();
5326 TCGv t2 = tcg_temp_new();
5327 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5328 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5329 tcg_gen_shl_tl(t2, t2, t0);
5330 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5331 gen_load_spr(t1, SPR_MQ);
5332 gen_store_spr(SPR_MQ, t0);
5333 tcg_gen_and_tl(t0, t0, t2);
5334 tcg_gen_andc_tl(t1, t1, t2);
5335 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5336 tcg_temp_free(t0);
5337 tcg_temp_free(t1);
5338 tcg_temp_free(t2);
5339 if (unlikely(Rc(ctx->opcode) != 0))
5340 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5341 }
5342
5343 /* sliq - sliq. */
5344 static void gen_sliq(DisasContext *ctx)
5345 {
5346 int sh = SH(ctx->opcode);
5347 TCGv t0 = tcg_temp_new();
5348 TCGv t1 = tcg_temp_new();
5349 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5350 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5351 tcg_gen_or_tl(t1, t0, t1);
5352 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5353 gen_store_spr(SPR_MQ, t1);
5354 tcg_temp_free(t0);
5355 tcg_temp_free(t1);
5356 if (unlikely(Rc(ctx->opcode) != 0))
5357 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5358 }
5359
5360 /* slliq - slliq. */
5361 static void gen_slliq(DisasContext *ctx)
5362 {
5363 int sh = SH(ctx->opcode);
5364 TCGv t0 = tcg_temp_new();
5365 TCGv t1 = tcg_temp_new();
5366 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5367 gen_load_spr(t1, SPR_MQ);
5368 gen_store_spr(SPR_MQ, t0);
5369 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5370 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5371 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5372 tcg_temp_free(t0);
5373 tcg_temp_free(t1);
5374 if (unlikely(Rc(ctx->opcode) != 0))
5375 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5376 }
5377
5378 /* sllq - sllq. */
5379 static void gen_sllq(DisasContext *ctx)
5380 {
5381 TCGLabel *l1 = gen_new_label();
5382 TCGLabel *l2 = gen_new_label();
5383 TCGv t0 = tcg_temp_local_new();
5384 TCGv t1 = tcg_temp_local_new();
5385 TCGv t2 = tcg_temp_local_new();
5386 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5387 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5388 tcg_gen_shl_tl(t1, t1, t2);
5389 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5390 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5391 gen_load_spr(t0, SPR_MQ);
5392 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5393 tcg_gen_br(l2);
5394 gen_set_label(l1);
5395 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5396 gen_load_spr(t2, SPR_MQ);
5397 tcg_gen_andc_tl(t1, t2, t1);
5398 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5399 gen_set_label(l2);
5400 tcg_temp_free(t0);
5401 tcg_temp_free(t1);
5402 tcg_temp_free(t2);
5403 if (unlikely(Rc(ctx->opcode) != 0))
5404 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5405 }
5406
5407 /* slq - slq. */
5408 static void gen_slq(DisasContext *ctx)
5409 {
5410 TCGLabel *l1 = gen_new_label();
5411 TCGv t0 = tcg_temp_new();
5412 TCGv t1 = tcg_temp_new();
5413 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5414 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5415 tcg_gen_subfi_tl(t1, 32, t1);
5416 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5417 tcg_gen_or_tl(t1, t0, t1);
5418 gen_store_spr(SPR_MQ, t1);
5419 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5420 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5421 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5422 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5423 gen_set_label(l1);
5424 tcg_temp_free(t0);
5425 tcg_temp_free(t1);
5426 if (unlikely(Rc(ctx->opcode) != 0))
5427 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5428 }
5429
5430 /* sraiq - sraiq. */
5431 static void gen_sraiq(DisasContext *ctx)
5432 {
5433 int sh = SH(ctx->opcode);
5434 TCGLabel *l1 = gen_new_label();
5435 TCGv t0 = tcg_temp_new();
5436 TCGv t1 = tcg_temp_new();
5437 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5438 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5439 tcg_gen_or_tl(t0, t0, t1);
5440 gen_store_spr(SPR_MQ, t0);
5441 tcg_gen_movi_tl(cpu_ca, 0);
5442 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5443 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5444 tcg_gen_movi_tl(cpu_ca, 1);
5445 gen_set_label(l1);
5446 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5447 tcg_temp_free(t0);
5448 tcg_temp_free(t1);
5449 if (unlikely(Rc(ctx->opcode) != 0))
5450 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5451 }
5452
5453 /* sraq - sraq. */
5454 static void gen_sraq(DisasContext *ctx)
5455 {
5456 TCGLabel *l1 = gen_new_label();
5457 TCGLabel *l2 = gen_new_label();
5458 TCGv t0 = tcg_temp_new();
5459 TCGv t1 = tcg_temp_local_new();
5460 TCGv t2 = tcg_temp_local_new();
5461 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5462 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5463 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5464 tcg_gen_subfi_tl(t2, 32, t2);
5465 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5466 tcg_gen_or_tl(t0, t0, t2);
5467 gen_store_spr(SPR_MQ, t0);
5468 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5469 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5470 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5471 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5472 gen_set_label(l1);
5473 tcg_temp_free(t0);
5474 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5475 tcg_gen_movi_tl(cpu_ca, 0);
5476 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5477 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5478 tcg_gen_movi_tl(cpu_ca, 1);
5479 gen_set_label(l2);
5480 tcg_temp_free(t1);
5481 tcg_temp_free(t2);
5482 if (unlikely(Rc(ctx->opcode) != 0))
5483 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5484 }
5485
5486 /* sre - sre. */
5487 static void gen_sre(DisasContext *ctx)
5488 {
5489 TCGv t0 = tcg_temp_new();
5490 TCGv t1 = tcg_temp_new();
5491 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5492 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5493 tcg_gen_subfi_tl(t1, 32, t1);
5494 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5495 tcg_gen_or_tl(t1, t0, t1);
5496 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5497 gen_store_spr(SPR_MQ, t1);
5498 tcg_temp_free(t0);
5499 tcg_temp_free(t1);
5500 if (unlikely(Rc(ctx->opcode) != 0))
5501 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5502 }
5503
5504 /* srea - srea. */
5505 static void gen_srea(DisasContext *ctx)
5506 {
5507 TCGv t0 = tcg_temp_new();
5508 TCGv t1 = tcg_temp_new();
5509 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5510 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5511 gen_store_spr(SPR_MQ, t0);
5512 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5513 tcg_temp_free(t0);
5514 tcg_temp_free(t1);
5515 if (unlikely(Rc(ctx->opcode) != 0))
5516 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5517 }
5518
5519 /* sreq */
5520 static void gen_sreq(DisasContext *ctx)
5521 {
5522 TCGv t0 = tcg_temp_new();
5523 TCGv t1 = tcg_temp_new();
5524 TCGv t2 = tcg_temp_new();
5525 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5526 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5527 tcg_gen_shr_tl(t1, t1, t0);
5528 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5529 gen_load_spr(t2, SPR_MQ);
5530 gen_store_spr(SPR_MQ, t0);
5531 tcg_gen_and_tl(t0, t0, t1);
5532 tcg_gen_andc_tl(t2, t2, t1);
5533 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5534 tcg_temp_free(t0);
5535 tcg_temp_free(t1);
5536 tcg_temp_free(t2);
5537 if (unlikely(Rc(ctx->opcode) != 0))
5538 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5539 }
5540
5541 /* sriq */
5542 static void gen_sriq(DisasContext *ctx)
5543 {
5544 int sh = SH(ctx->opcode);
5545 TCGv t0 = tcg_temp_new();
5546 TCGv t1 = tcg_temp_new();
5547 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5548 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5549 tcg_gen_or_tl(t1, t0, t1);
5550 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5551 gen_store_spr(SPR_MQ, t1);
5552 tcg_temp_free(t0);
5553 tcg_temp_free(t1);
5554 if (unlikely(Rc(ctx->opcode) != 0))
5555 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5556 }
5557
5558 /* srliq */
5559 static void gen_srliq(DisasContext *ctx)
5560 {
5561 int sh = SH(ctx->opcode);
5562 TCGv t0 = tcg_temp_new();
5563 TCGv t1 = tcg_temp_new();
5564 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5565 gen_load_spr(t1, SPR_MQ);
5566 gen_store_spr(SPR_MQ, t0);
5567 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5568 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5569 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5570 tcg_temp_free(t0);
5571 tcg_temp_free(t1);
5572 if (unlikely(Rc(ctx->opcode) != 0))
5573 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5574 }
5575
5576 /* srlq */
5577 static void gen_srlq(DisasContext *ctx)
5578 {
5579 TCGLabel *l1 = gen_new_label();
5580 TCGLabel *l2 = gen_new_label();
5581 TCGv t0 = tcg_temp_local_new();
5582 TCGv t1 = tcg_temp_local_new();
5583 TCGv t2 = tcg_temp_local_new();
5584 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5585 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5586 tcg_gen_shr_tl(t2, t1, t2);
5587 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5588 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5589 gen_load_spr(t0, SPR_MQ);
5590 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5591 tcg_gen_br(l2);
5592 gen_set_label(l1);
5593 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5594 tcg_gen_and_tl(t0, t0, t2);
5595 gen_load_spr(t1, SPR_MQ);
5596 tcg_gen_andc_tl(t1, t1, t2);
5597 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5598 gen_set_label(l2);
5599 tcg_temp_free(t0);
5600 tcg_temp_free(t1);
5601 tcg_temp_free(t2);
5602 if (unlikely(Rc(ctx->opcode) != 0))
5603 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5604 }
5605
5606 /* srq */
5607 static void gen_srq(DisasContext *ctx)
5608 {
5609 TCGLabel *l1 = gen_new_label();
5610 TCGv t0 = tcg_temp_new();
5611 TCGv t1 = tcg_temp_new();
5612 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5613 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5614 tcg_gen_subfi_tl(t1, 32, t1);
5615 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5616 tcg_gen_or_tl(t1, t0, t1);
5617 gen_store_spr(SPR_MQ, t1);
5618 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5619 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5620 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5621 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5622 gen_set_label(l1);
5623 tcg_temp_free(t0);
5624 tcg_temp_free(t1);
5625 if (unlikely(Rc(ctx->opcode) != 0))
5626 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5627 }
5628
5629 /* PowerPC 602 specific instructions */
5630
5631 /* dsa */
5632 static void gen_dsa(DisasContext *ctx)
5633 {
5634 /* XXX: TODO */
5635 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5636 }
5637
5638 /* esa */
5639 static void gen_esa(DisasContext *ctx)
5640 {
5641 /* XXX: TODO */
5642 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5643 }
5644
5645 /* mfrom */
5646 static void gen_mfrom(DisasContext *ctx)
5647 {
5648 #if defined(CONFIG_USER_ONLY)
5649 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5650 #else
5651 if (unlikely(ctx->pr)) {
5652 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5653 return;
5654 }
5655 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5656 #endif
5657 }
5658
5659 /* 602 - 603 - G2 TLB management */
5660
5661 /* tlbld */
5662 static void gen_tlbld_6xx(DisasContext *ctx)
5663 {
5664 #if defined(CONFIG_USER_ONLY)
5665 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5666 #else
5667 if (unlikely(ctx->pr)) {
5668 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5669 return;
5670 }
5671 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5672 #endif
5673 }
5674
5675 /* tlbli */
5676 static void gen_tlbli_6xx(DisasContext *ctx)
5677 {
5678 #if defined(CONFIG_USER_ONLY)
5679 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5680 #else
5681 if (unlikely(ctx->pr)) {
5682 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5683 return;
5684 }
5685 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5686 #endif
5687 }
5688
5689 /* 74xx TLB management */
5690
5691 /* tlbld */
5692 static void gen_tlbld_74xx(DisasContext *ctx)
5693 {
5694 #if defined(CONFIG_USER_ONLY)
5695 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5696 #else
5697 if (unlikely(ctx->pr)) {
5698 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5699 return;
5700 }
5701 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5702 #endif
5703 }
5704
5705 /* tlbli */
5706 static void gen_tlbli_74xx(DisasContext *ctx)
5707 {
5708 #if defined(CONFIG_USER_ONLY)
5709 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5710 #else
5711 if (unlikely(ctx->pr)) {
5712 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5713 return;
5714 }
5715 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5716 #endif
5717 }
5718
5719 /* POWER instructions not in PowerPC 601 */
5720
5721 /* clf */
5722 static void gen_clf(DisasContext *ctx)
5723 {
5724 /* Cache line flush: implemented as no-op */
5725 }
5726
5727 /* cli */
5728 static void gen_cli(DisasContext *ctx)
5729 {
5730 /* Cache line invalidate: privileged and treated as no-op */
5731 #if defined(CONFIG_USER_ONLY)
5732 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5733 #else
5734 if (unlikely(ctx->pr)) {
5735 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5736 return;
5737 }
5738 #endif
5739 }
5740
5741 /* dclst */
5742 static void gen_dclst(DisasContext *ctx)
5743 {
5744 /* Data cache line store: treated as no-op */
5745 }
5746
5747 static void gen_mfsri(DisasContext *ctx)
5748 {
5749 #if defined(CONFIG_USER_ONLY)
5750 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5751 #else
5752 int ra = rA(ctx->opcode);
5753 int rd = rD(ctx->opcode);
5754 TCGv t0;
5755 if (unlikely(ctx->pr)) {
5756 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5757 return;
5758 }
5759 t0 = tcg_temp_new();
5760 gen_addr_reg_index(ctx, t0);
5761 tcg_gen_shri_tl(t0, t0, 28);
5762 tcg_gen_andi_tl(t0, t0, 0xF);
5763 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5764 tcg_temp_free(t0);
5765 if (ra != 0 && ra != rd)
5766 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5767 #endif
5768 }
5769
5770 static void gen_rac(DisasContext *ctx)
5771 {
5772 #if defined(CONFIG_USER_ONLY)
5773 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5774 #else
5775 TCGv t0;
5776 if (unlikely(ctx->pr)) {
5777 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5778 return;
5779 }
5780 t0 = tcg_temp_new();
5781 gen_addr_reg_index(ctx, t0);
5782 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5783 tcg_temp_free(t0);
5784 #endif
5785 }
5786
5787 static void gen_rfsvc(DisasContext *ctx)
5788 {
5789 #if defined(CONFIG_USER_ONLY)
5790 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5791 #else
5792 if (unlikely(ctx->pr)) {
5793 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5794 return;
5795 }
5796 gen_helper_rfsvc(cpu_env);
5797 gen_sync_exception(ctx);
5798 #endif
5799 }
5800
5801 /* svc is not implemented for now */
5802
5803 /* POWER2 specific instructions */
5804 /* Quad manipulation (load/store two floats at a time) */
5805
5806 /* lfq */
5807 static void gen_lfq(DisasContext *ctx)
5808 {
5809 int rd = rD(ctx->opcode);
5810 TCGv t0;
5811 gen_set_access_type(ctx, ACCESS_FLOAT);
5812 t0 = tcg_temp_new();
5813 gen_addr_imm_index(ctx, t0, 0);
5814 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5815 gen_addr_add(ctx, t0, t0, 8);
5816 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5817 tcg_temp_free(t0);
5818 }
5819
5820 /* lfqu */
5821 static void gen_lfqu(DisasContext *ctx)
5822 {
5823 int ra = rA(ctx->opcode);
5824 int rd = rD(ctx->opcode);
5825 TCGv t0, t1;
5826 gen_set_access_type(ctx, ACCESS_FLOAT);
5827 t0 = tcg_temp_new();
5828 t1 = tcg_temp_new();
5829 gen_addr_imm_index(ctx, t0, 0);
5830 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5831 gen_addr_add(ctx, t1, t0, 8);
5832 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5833 if (ra != 0)
5834 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5835 tcg_temp_free(t0);
5836 tcg_temp_free(t1);
5837 }
5838
5839 /* lfqux */
5840 static void gen_lfqux(DisasContext *ctx)
5841 {
5842 int ra = rA(ctx->opcode);
5843 int rd = rD(ctx->opcode);
5844 gen_set_access_type(ctx, ACCESS_FLOAT);
5845 TCGv t0, t1;
5846 t0 = tcg_temp_new();
5847 gen_addr_reg_index(ctx, t0);
5848 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5849 t1 = tcg_temp_new();
5850 gen_addr_add(ctx, t1, t0, 8);
5851 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5852 tcg_temp_free(t1);
5853 if (ra != 0)
5854 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5855 tcg_temp_free(t0);
5856 }
5857
5858 /* lfqx */
5859 static void gen_lfqx(DisasContext *ctx)
5860 {
5861 int rd = rD(ctx->opcode);
5862 TCGv t0;
5863 gen_set_access_type(ctx, ACCESS_FLOAT);
5864 t0 = tcg_temp_new();
5865 gen_addr_reg_index(ctx, t0);
5866 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5867 gen_addr_add(ctx, t0, t0, 8);
5868 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5869 tcg_temp_free(t0);
5870 }
5871
5872 /* stfq */
5873 static void gen_stfq(DisasContext *ctx)
5874 {
5875 int rd = rD(ctx->opcode);
5876 TCGv t0;
5877 gen_set_access_type(ctx, ACCESS_FLOAT);
5878 t0 = tcg_temp_new();
5879 gen_addr_imm_index(ctx, t0, 0);
5880 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5881 gen_addr_add(ctx, t0, t0, 8);
5882 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5883 tcg_temp_free(t0);
5884 }
5885
5886 /* stfqu */
5887 static void gen_stfqu(DisasContext *ctx)
5888 {
5889 int ra = rA(ctx->opcode);
5890 int rd = rD(ctx->opcode);
5891 TCGv t0, t1;
5892 gen_set_access_type(ctx, ACCESS_FLOAT);
5893 t0 = tcg_temp_new();
5894 gen_addr_imm_index(ctx, t0, 0);
5895 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5896 t1 = tcg_temp_new();
5897 gen_addr_add(ctx, t1, t0, 8);
5898 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5899 tcg_temp_free(t1);
5900 if (ra != 0)
5901 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5902 tcg_temp_free(t0);
5903 }
5904
5905 /* stfqux */
5906 static void gen_stfqux(DisasContext *ctx)
5907 {
5908 int ra = rA(ctx->opcode);
5909 int rd = rD(ctx->opcode);
5910 TCGv t0, t1;
5911 gen_set_access_type(ctx, ACCESS_FLOAT);
5912 t0 = tcg_temp_new();
5913 gen_addr_reg_index(ctx, t0);
5914 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5915 t1 = tcg_temp_new();
5916 gen_addr_add(ctx, t1, t0, 8);
5917 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5918 tcg_temp_free(t1);
5919 if (ra != 0)
5920 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5921 tcg_temp_free(t0);
5922 }
5923
5924 /* stfqx */
5925 static void gen_stfqx(DisasContext *ctx)
5926 {
5927 int rd = rD(ctx->opcode);
5928 TCGv t0;
5929 gen_set_access_type(ctx, ACCESS_FLOAT);
5930 t0 = tcg_temp_new();
5931 gen_addr_reg_index(ctx, t0);
5932 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5933 gen_addr_add(ctx, t0, t0, 8);
5934 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5935 tcg_temp_free(t0);
5936 }
5937
5938 /* BookE specific instructions */
5939
5940 /* XXX: not implemented on 440 ? */
5941 static void gen_mfapidi(DisasContext *ctx)
5942 {
5943 /* XXX: TODO */
5944 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5945 }
5946
5947 /* XXX: not implemented on 440 ? */
5948 static void gen_tlbiva(DisasContext *ctx)
5949 {
5950 #if defined(CONFIG_USER_ONLY)
5951 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5952 #else
5953 TCGv t0;
5954 if (unlikely(ctx->pr)) {
5955 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5956 return;
5957 }
5958 t0 = tcg_temp_new();
5959 gen_addr_reg_index(ctx, t0);
5960 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5961 tcg_temp_free(t0);
5962 #endif
5963 }
5964
5965 /* All 405 MAC instructions are translated here */
5966 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5967 int ra, int rb, int rt, int Rc)
5968 {
5969 TCGv t0, t1;
5970
5971 t0 = tcg_temp_local_new();
5972 t1 = tcg_temp_local_new();
5973
5974 switch (opc3 & 0x0D) {
5975 case 0x05:
5976 /* macchw - macchw. - macchwo - macchwo. */
5977 /* macchws - macchws. - macchwso - macchwso. */
5978 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5979 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5980 /* mulchw - mulchw. */
5981 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5982 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5983 tcg_gen_ext16s_tl(t1, t1);
5984 break;
5985 case 0x04:
5986 /* macchwu - macchwu. - macchwuo - macchwuo. */
5987 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5988 /* mulchwu - mulchwu. */
5989 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5990 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5991 tcg_gen_ext16u_tl(t1, t1);
5992 break;
5993 case 0x01:
5994 /* machhw - machhw. - machhwo - machhwo. */
5995 /* machhws - machhws. - machhwso - machhwso. */
5996 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5997 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5998 /* mulhhw - mulhhw. */
5999 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
6000 tcg_gen_ext16s_tl(t0, t0);
6001 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
6002 tcg_gen_ext16s_tl(t1, t1);
6003 break;
6004 case 0x00:
6005 /* machhwu - machhwu. - machhwuo - machhwuo. */
6006 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
6007 /* mulhhwu - mulhhwu. */
6008 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
6009 tcg_gen_ext16u_tl(t0, t0);
6010 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
6011 tcg_gen_ext16u_tl(t1, t1);
6012 break;
6013 case 0x0D:
6014 /* maclhw - maclhw. - maclhwo - maclhwo. */
6015 /* maclhws - maclhws. - maclhwso - maclhwso. */
6016 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
6017 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
6018 /* mullhw - mullhw. */
6019 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
6020 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
6021 break;
6022 case 0x0C:
6023 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
6024 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
6025 /* mullhwu - mullhwu. */
6026 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
6027 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
6028 break;
6029 }
6030 if (opc2 & 0x04) {
6031 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
6032 tcg_gen_mul_tl(t1, t0, t1);
6033 if (opc2 & 0x02) {
6034 /* nmultiply-and-accumulate (0x0E) */
6035 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
6036 } else {
6037 /* multiply-and-accumulate (0x0C) */
6038 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
6039 }
6040
6041 if (opc3 & 0x12) {
6042 /* Check overflow and/or saturate */
6043 TCGLabel *l1 = gen_new_label();
6044
6045 if (opc3 & 0x10) {
6046 /* Start with XER OV disabled, the most likely case */
6047 tcg_gen_movi_tl(cpu_ov, 0);
6048 }
6049 if (opc3 & 0x01) {
6050 /* Signed */
6051 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
6052 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
6053 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
6054 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
6055 if (opc3 & 0x02) {
6056 /* Saturate */
6057 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
6058 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
6059 }
6060 } else {
6061 /* Unsigned */
6062 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
6063 if (opc3 & 0x02) {
6064 /* Saturate */
6065 tcg_gen_movi_tl(t0, UINT32_MAX);
6066 }
6067 }
6068 if (opc3 & 0x10) {
6069 /* Check overflow */
6070 tcg_gen_movi_tl(cpu_ov, 1);
6071 tcg_gen_movi_tl(cpu_so, 1);
6072 }
6073 gen_set_label(l1);
6074 tcg_gen_mov_tl(cpu_gpr[rt], t0);
6075 }
6076 } else {
6077 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
6078 }
6079 tcg_temp_free(t0);
6080 tcg_temp_free(t1);
6081 if (unlikely(Rc) != 0) {
6082 /* Update Rc0 */
6083 gen_set_Rc0(ctx, cpu_gpr[rt]);
6084 }
6085 }
6086
6087 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6088 static void glue(gen_, name)(DisasContext *ctx) \
6089 { \
6090 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
6091 rD(ctx->opcode), Rc(ctx->opcode)); \
6092 }
6093
6094 /* macchw - macchw. */
6095 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
6096 /* macchwo - macchwo. */
6097 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
6098 /* macchws - macchws. */
6099 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
6100 /* macchwso - macchwso. */
6101 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
6102 /* macchwsu - macchwsu. */
6103 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
6104 /* macchwsuo - macchwsuo. */
6105 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
6106 /* macchwu - macchwu. */
6107 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
6108 /* macchwuo - macchwuo. */
6109 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
6110 /* machhw - machhw. */
6111 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
6112 /* machhwo - machhwo. */
6113 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
6114 /* machhws - machhws. */
6115 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
6116 /* machhwso - machhwso. */
6117 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
6118 /* machhwsu - machhwsu. */
6119 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
6120 /* machhwsuo - machhwsuo. */
6121 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
6122 /* machhwu - machhwu. */
6123 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
6124 /* machhwuo - machhwuo. */
6125 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
6126 /* maclhw - maclhw. */
6127 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
6128 /* maclhwo - maclhwo. */
6129 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
6130 /* maclhws - maclhws. */
6131 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
6132 /* maclhwso - maclhwso. */
6133 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
6134 /* maclhwu - maclhwu. */
6135 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
6136 /* maclhwuo - maclhwuo. */
6137 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
6138 /* maclhwsu - maclhwsu. */
6139 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
6140 /* maclhwsuo - maclhwsuo. */
6141 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
6142 /* nmacchw - nmacchw. */
6143 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
6144 /* nmacchwo - nmacchwo. */
6145 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
6146 /* nmacchws - nmacchws. */
6147 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
6148 /* nmacchwso - nmacchwso. */
6149 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
6150 /* nmachhw - nmachhw. */
6151 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
6152 /* nmachhwo - nmachhwo. */
6153 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
6154 /* nmachhws - nmachhws. */
6155 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
6156 /* nmachhwso - nmachhwso. */
6157 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
6158 /* nmaclhw - nmaclhw. */
6159 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
6160 /* nmaclhwo - nmaclhwo. */
6161 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
6162 /* nmaclhws - nmaclhws. */
6163 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
6164 /* nmaclhwso - nmaclhwso. */
6165 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
6166
6167 /* mulchw - mulchw. */
6168 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
6169 /* mulchwu - mulchwu. */
6170 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
6171 /* mulhhw - mulhhw. */
6172 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
6173 /* mulhhwu - mulhhwu. */
6174 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
6175 /* mullhw - mullhw. */
6176 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
6177 /* mullhwu - mullhwu. */
6178 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
6179
6180 /* mfdcr */
6181 static void gen_mfdcr(DisasContext *ctx)
6182 {
6183 #if defined(CONFIG_USER_ONLY)
6184 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6185 #else
6186 TCGv dcrn;
6187 if (unlikely(ctx->pr)) {
6188 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6189 return;
6190 }
6191 /* NIP cannot be restored if the memory exception comes from an helper */
6192 gen_update_nip(ctx, ctx->nip - 4);
6193 dcrn = tcg_const_tl(SPR(ctx->opcode));
6194 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
6195 tcg_temp_free(dcrn);
6196 #endif
6197 }
6198
6199 /* mtdcr */
6200 static void gen_mtdcr(DisasContext *ctx)
6201 {
6202 #if defined(CONFIG_USER_ONLY)
6203 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6204 #else
6205 TCGv dcrn;
6206 if (unlikely(ctx->pr)) {
6207 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6208 return;
6209 }
6210 /* NIP cannot be restored if the memory exception comes from an helper */
6211 gen_update_nip(ctx, ctx->nip - 4);
6212 dcrn = tcg_const_tl(SPR(ctx->opcode));
6213 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
6214 tcg_temp_free(dcrn);
6215 #endif
6216 }
6217
6218 /* mfdcrx */
6219 /* XXX: not implemented on 440 ? */
6220 static void gen_mfdcrx(DisasContext *ctx)
6221 {
6222 #if defined(CONFIG_USER_ONLY)
6223 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6224 #else
6225 if (unlikely(ctx->pr)) {
6226 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6227 return;
6228 }
6229 /* NIP cannot be restored if the memory exception comes from an helper */
6230 gen_update_nip(ctx, ctx->nip - 4);
6231 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6232 cpu_gpr[rA(ctx->opcode)]);
6233 /* Note: Rc update flag set leads to undefined state of Rc0 */
6234 #endif
6235 }
6236
6237 /* mtdcrx */
6238 /* XXX: not implemented on 440 ? */
6239 static void gen_mtdcrx(DisasContext *ctx)
6240 {
6241 #if defined(CONFIG_USER_ONLY)
6242 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6243 #else
6244 if (unlikely(ctx->pr)) {
6245 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6246 return;
6247 }
6248 /* NIP cannot be restored if the memory exception comes from an helper */
6249 gen_update_nip(ctx, ctx->nip - 4);
6250 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6251 cpu_gpr[rS(ctx->opcode)]);
6252 /* Note: Rc update flag set leads to undefined state of Rc0 */
6253 #endif
6254 }
6255
6256 /* mfdcrux (PPC 460) : user-mode access to DCR */
6257 static void gen_mfdcrux(DisasContext *ctx)
6258 {
6259 /* NIP cannot be restored if the memory exception comes from an helper */
6260 gen_update_nip(ctx, ctx->nip - 4);
6261 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6262 cpu_gpr[rA(ctx->opcode)]);
6263 /* Note: Rc update flag set leads to undefined state of Rc0 */
6264 }
6265
6266 /* mtdcrux (PPC 460) : user-mode access to DCR */
6267 static void gen_mtdcrux(DisasContext *ctx)
6268 {
6269 /* NIP cannot be restored if the memory exception comes from an helper */
6270 gen_update_nip(ctx, ctx->nip - 4);
6271 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6272 cpu_gpr[rS(ctx->opcode)]);
6273 /* Note: Rc update flag set leads to undefined state of Rc0 */
6274 }
6275
6276 /* dccci */
6277 static void gen_dccci(DisasContext *ctx)
6278 {
6279 #if defined(CONFIG_USER_ONLY)
6280 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6281 #else
6282 if (unlikely(ctx->pr)) {
6283 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6284 return;
6285 }
6286 /* interpreted as no-op */
6287 #endif
6288 }
6289
6290 /* dcread */
6291 static void gen_dcread(DisasContext *ctx)
6292 {
6293 #if defined(CONFIG_USER_ONLY)
6294 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6295 #else
6296 TCGv EA, val;
6297 if (unlikely(ctx->pr)) {
6298 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6299 return;
6300 }
6301 gen_set_access_type(ctx, ACCESS_CACHE);
6302 EA = tcg_temp_new();
6303 gen_addr_reg_index(ctx, EA);
6304 val = tcg_temp_new();
6305 gen_qemu_ld32u(ctx, val, EA);
6306 tcg_temp_free(val);
6307 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6308 tcg_temp_free(EA);
6309 #endif
6310 }
6311
6312 /* icbt */
6313 static void gen_icbt_40x(DisasContext *ctx)
6314 {
6315 /* interpreted as no-op */
6316 /* XXX: specification say this is treated as a load by the MMU
6317 * but does not generate any exception
6318 */
6319 }
6320
6321 /* iccci */
6322 static void gen_iccci(DisasContext *ctx)
6323 {
6324 #if defined(CONFIG_USER_ONLY)
6325 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6326 #else
6327 if (unlikely(ctx->pr)) {
6328 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6329 return;
6330 }
6331 /* interpreted as no-op */
6332 #endif
6333 }
6334
6335 /* icread */
6336 static void gen_icread(DisasContext *ctx)
6337 {
6338 #if defined(CONFIG_USER_ONLY)
6339 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6340 #else
6341 if (unlikely(ctx->pr)) {
6342 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6343 return;
6344 }
6345 /* interpreted as no-op */
6346 #endif
6347 }
6348
6349 /* rfci (supervisor only) */
6350 static void gen_rfci_40x(DisasContext *ctx)
6351 {
6352 #if defined(CONFIG_USER_ONLY)
6353 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6354 #else
6355 if (unlikely(ctx->pr)) {
6356 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6357 return;
6358 }
6359 /* Restore CPU state */
6360 gen_helper_40x_rfci(cpu_env);
6361 gen_sync_exception(ctx);
6362 #endif
6363 }
6364
6365 static void gen_rfci(DisasContext *ctx)
6366 {
6367 #if defined(CONFIG_USER_ONLY)
6368 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6369 #else
6370 if (unlikely(ctx->pr)) {
6371 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6372 return;
6373 }
6374 /* Restore CPU state */
6375 gen_helper_rfci(cpu_env);
6376 gen_sync_exception(ctx);
6377 #endif
6378 }
6379
6380 /* BookE specific */
6381
6382 /* XXX: not implemented on 440 ? */
6383 static void gen_rfdi(DisasContext *ctx)
6384 {
6385 #if defined(CONFIG_USER_ONLY)
6386 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6387 #else
6388 if (unlikely(ctx->pr)) {
6389 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6390 return;
6391 }
6392 /* Restore CPU state */
6393 gen_helper_rfdi(cpu_env);
6394 gen_sync_exception(ctx);
6395 #endif
6396 }
6397
6398 /* XXX: not implemented on 440 ? */
6399 static void gen_rfmci(DisasContext *ctx)
6400 {
6401 #if defined(CONFIG_USER_ONLY)
6402 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6403 #else
6404 if (unlikely(ctx->pr)) {
6405 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6406 return;
6407 }
6408 /* Restore CPU state */
6409 gen_helper_rfmci(cpu_env);
6410 gen_sync_exception(ctx);
6411 #endif
6412 }
6413
6414 /* TLB management - PowerPC 405 implementation */
6415
6416 /* tlbre */
6417 static void gen_tlbre_40x(DisasContext *ctx)
6418 {
6419 #if defined(CONFIG_USER_ONLY)
6420 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6421 #else
6422 if (unlikely(ctx->pr)) {
6423 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6424 return;
6425 }
6426 switch (rB(ctx->opcode)) {
6427 case 0:
6428 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6429 cpu_gpr[rA(ctx->opcode)]);
6430 break;
6431 case 1:
6432 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6433 cpu_gpr[rA(ctx->opcode)]);
6434 break;
6435 default:
6436 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6437 break;
6438 }
6439 #endif
6440 }
6441
6442 /* tlbsx - tlbsx. */
6443 static void gen_tlbsx_40x(DisasContext *ctx)
6444 {
6445 #if defined(CONFIG_USER_ONLY)
6446 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6447 #else
6448 TCGv t0;
6449 if (unlikely(ctx->pr)) {
6450 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6451 return;
6452 }
6453 t0 = tcg_temp_new();
6454 gen_addr_reg_index(ctx, t0);
6455 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6456 tcg_temp_free(t0);
6457 if (Rc(ctx->opcode)) {
6458 TCGLabel *l1 = gen_new_label();
6459 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6460 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6461 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6462 gen_set_label(l1);
6463 }
6464 #endif
6465 }
6466
6467 /* tlbwe */
6468 static void gen_tlbwe_40x(DisasContext *ctx)
6469 {
6470 #if defined(CONFIG_USER_ONLY)
6471 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6472 #else
6473 if (unlikely(ctx->pr)) {
6474 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6475 return;
6476 }
6477 switch (rB(ctx->opcode)) {
6478 case 0:
6479 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6480 cpu_gpr[rS(ctx->opcode)]);
6481 break;
6482 case 1:
6483 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6484 cpu_gpr[rS(ctx->opcode)]);
6485 break;
6486 default:
6487 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6488 break;
6489 }
6490 #endif
6491 }
6492
6493 /* TLB management - PowerPC 440 implementation */
6494
6495 /* tlbre */
6496 static void gen_tlbre_440(DisasContext *ctx)
6497 {
6498 #if defined(CONFIG_USER_ONLY)
6499 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6500 #else
6501 if (unlikely(ctx->pr)) {
6502 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6503 return;
6504 }
6505 switch (rB(ctx->opcode)) {
6506 case 0:
6507 case 1:
6508 case 2:
6509 {
6510 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6511 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6512 t0, cpu_gpr[rA(ctx->opcode)]);
6513 tcg_temp_free_i32(t0);
6514 }
6515 break;
6516 default:
6517 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6518 break;
6519 }
6520 #endif
6521 }
6522
6523 /* tlbsx - tlbsx. */
6524 static void gen_tlbsx_440(DisasContext *ctx)
6525 {
6526 #if defined(CONFIG_USER_ONLY)
6527 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6528 #else
6529 TCGv t0;
6530 if (unlikely(ctx->pr)) {
6531 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6532 return;
6533 }
6534 t0 = tcg_temp_new();
6535 gen_addr_reg_index(ctx, t0);
6536 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6537 tcg_temp_free(t0);
6538 if (Rc(ctx->opcode)) {
6539 TCGLabel *l1 = gen_new_label();
6540 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6541 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6542 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6543 gen_set_label(l1);
6544 }
6545 #endif
6546 }
6547
6548 /* tlbwe */
6549 static void gen_tlbwe_440(DisasContext *ctx)
6550 {
6551 #if defined(CONFIG_USER_ONLY)
6552 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6553 #else
6554 if (unlikely(ctx->pr)) {
6555 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6556 return;
6557 }
6558 switch (rB(ctx->opcode)) {
6559 case 0:
6560 case 1:
6561 case 2:
6562 {
6563 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6564 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6565 cpu_gpr[rS(ctx->opcode)]);
6566 tcg_temp_free_i32(t0);
6567 }
6568 break;
6569 default:
6570 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6571 break;
6572 }
6573 #endif
6574 }
6575
6576 /* TLB management - PowerPC BookE 2.06 implementation */
6577
6578 /* tlbre */
6579 static void gen_tlbre_booke206(DisasContext *ctx)
6580 {
6581 #if defined(CONFIG_USER_ONLY)
6582 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6583 #else
6584 if (unlikely(ctx->pr)) {
6585 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6586 return;
6587 }
6588
6589 gen_helper_booke206_tlbre(cpu_env);
6590 #endif
6591 }
6592
6593 /* tlbsx - tlbsx. */
6594 static void gen_tlbsx_booke206(DisasContext *ctx)
6595 {
6596 #if defined(CONFIG_USER_ONLY)
6597 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6598 #else
6599 TCGv t0;
6600 if (unlikely(ctx->pr)) {
6601 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6602 return;
6603 }
6604
6605 if (rA(ctx->opcode)) {
6606 t0 = tcg_temp_new();
6607 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6608 } else {
6609 t0 = tcg_const_tl(0);
6610 }
6611
6612 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6613 gen_helper_booke206_tlbsx(cpu_env, t0);
6614 tcg_temp_free(t0);
6615 #endif
6616 }
6617
6618 /* tlbwe */
6619 static void gen_tlbwe_booke206(DisasContext *ctx)
6620 {
6621 #if defined(CONFIG_USER_ONLY)
6622 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6623 #else
6624 if (unlikely(ctx->pr)) {
6625 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6626 return;
6627 }
6628 gen_update_nip(ctx, ctx->nip - 4);
6629 gen_helper_booke206_tlbwe(cpu_env);
6630 #endif
6631 }
6632
6633 static void gen_tlbivax_booke206(DisasContext *ctx)
6634 {
6635 #if defined(CONFIG_USER_ONLY)
6636 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6637 #else
6638 TCGv t0;
6639 if (unlikely(ctx->pr)) {
6640 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6641 return;
6642 }
6643
6644 t0 = tcg_temp_new();
6645 gen_addr_reg_index(ctx, t0);
6646
6647 gen_helper_booke206_tlbivax(cpu_env, t0);
6648 tcg_temp_free(t0);
6649 #endif
6650 }
6651
6652 static void gen_tlbilx_booke206(DisasContext *ctx)
6653 {
6654 #if defined(CONFIG_USER_ONLY)
6655 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6656 #else
6657 TCGv t0;
6658 if (unlikely(ctx->pr)) {
6659 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6660 return;
6661 }
6662
6663 t0 = tcg_temp_new();
6664 gen_addr_reg_index(ctx, t0);
6665
6666 switch((ctx->opcode >> 21) & 0x3) {
6667 case 0:
6668 gen_helper_booke206_tlbilx0(cpu_env, t0);
6669 break;
6670 case 1:
6671 gen_helper_booke206_tlbilx1(cpu_env, t0);
6672 break;
6673 case 3:
6674 gen_helper_booke206_tlbilx3(cpu_env, t0);
6675 break;
6676 default:
6677 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6678 break;
6679 }
6680
6681 tcg_temp_free(t0);
6682 #endif
6683 }
6684
6685
6686 /* wrtee */
6687 static void gen_wrtee(DisasContext *ctx)
6688 {
6689 #if defined(CONFIG_USER_ONLY)
6690 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6691 #else
6692 TCGv t0;
6693 if (unlikely(ctx->pr)) {
6694 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6695 return;
6696 }
6697 t0 = tcg_temp_new();
6698 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6699 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6700 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6701 tcg_temp_free(t0);
6702 /* Stop translation to have a chance to raise an exception
6703 * if we just set msr_ee to 1
6704 */
6705 gen_stop_exception(ctx);
6706 #endif
6707 }
6708
6709 /* wrteei */
6710 static void gen_wrteei(DisasContext *ctx)
6711 {
6712 #if defined(CONFIG_USER_ONLY)
6713 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6714 #else
6715 if (unlikely(ctx->pr)) {
6716 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6717 return;
6718 }
6719 if (ctx->opcode & 0x00008000) {
6720 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6721 /* Stop translation to have a chance to raise an exception */
6722 gen_stop_exception(ctx);
6723 } else {
6724 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6725 }
6726 #endif
6727 }
6728
6729 /* PowerPC 440 specific instructions */
6730
6731 /* dlmzb */
6732 static void gen_dlmzb(DisasContext *ctx)
6733 {
6734 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6735 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6736 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6737 tcg_temp_free_i32(t0);
6738 }
6739
6740 /* mbar replaces eieio on 440 */
6741 static void gen_mbar(DisasContext *ctx)
6742 {
6743 /* interpreted as no-op */
6744 }
6745
6746 /* msync replaces sync on 440 */
6747 static void gen_msync_4xx(DisasContext *ctx)
6748 {
6749 /* interpreted as no-op */
6750 }
6751
6752 /* icbt */
6753 static void gen_icbt_440(DisasContext *ctx)
6754 {
6755 /* interpreted as no-op */
6756 /* XXX: specification say this is treated as a load by the MMU
6757 * but does not generate any exception
6758 */
6759 }
6760
6761 /* Embedded.Processor Control */
6762
6763 static void gen_msgclr(DisasContext *ctx)
6764 {
6765 #if defined(CONFIG_USER_ONLY)
6766 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6767 #else
6768 if (unlikely(ctx->pr)) {
6769 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6770 return;
6771 }
6772
6773 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6774 #endif
6775 }
6776
6777 static void gen_msgsnd(DisasContext *ctx)
6778 {
6779 #if defined(CONFIG_USER_ONLY)
6780 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6781 #else
6782 if (unlikely(ctx->pr)) {
6783 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6784 return;
6785 }
6786
6787 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6788 #endif
6789 }
6790
6791 /*** Altivec vector extension ***/
6792 /* Altivec registers moves */
6793
6794 static inline TCGv_ptr gen_avr_ptr(int reg)
6795 {
6796 TCGv_ptr r = tcg_temp_new_ptr();
6797 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6798 return r;
6799 }
6800
6801 #define GEN_VR_LDX(name, opc2, opc3) \
6802 static void glue(gen_, name)(DisasContext *ctx) \
6803 { \
6804 TCGv EA; \
6805 if (unlikely(!ctx->altivec_enabled)) { \
6806 gen_exception(ctx, POWERPC_EXCP_VPU); \
6807 return; \
6808 } \
6809 gen_set_access_type(ctx, ACCESS_INT); \
6810 EA = tcg_temp_new(); \
6811 gen_addr_reg_index(ctx, EA); \
6812 tcg_gen_andi_tl(EA, EA, ~0xf); \
6813 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
6814 64-bit byteswap already. */ \
6815 if (ctx->le_mode) { \
6816 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6817 tcg_gen_addi_tl(EA, EA, 8); \
6818 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6819 } else { \
6820 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6821 tcg_gen_addi_tl(EA, EA, 8); \
6822 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6823 } \
6824 tcg_temp_free(EA); \
6825 }
6826
6827 #define GEN_VR_STX(name, opc2, opc3) \
6828 static void gen_st##name(DisasContext *ctx) \
6829 { \
6830 TCGv EA; \
6831 if (unlikely(!ctx->altivec_enabled)) { \
6832 gen_exception(ctx, POWERPC_EXCP_VPU); \
6833 return; \
6834 } \
6835 gen_set_access_type(ctx, ACCESS_INT); \
6836 EA = tcg_temp_new(); \
6837 gen_addr_reg_index(ctx, EA); \
6838 tcg_gen_andi_tl(EA, EA, ~0xf); \
6839 /* We only need to swap high and low halves. gen_qemu_st64 does necessary \
6840 64-bit byteswap already. */ \
6841 if (ctx->le_mode) { \
6842 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6843 tcg_gen_addi_tl(EA, EA, 8); \
6844 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6845 } else { \
6846 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6847 tcg_gen_addi_tl(EA, EA, 8); \
6848 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6849 } \
6850 tcg_temp_free(EA); \
6851 }
6852
6853 #define GEN_VR_LVE(name, opc2, opc3, size) \
6854 static void gen_lve##name(DisasContext *ctx) \
6855 { \
6856 TCGv EA; \
6857 TCGv_ptr rs; \
6858 if (unlikely(!ctx->altivec_enabled)) { \
6859 gen_exception(ctx, POWERPC_EXCP_VPU); \
6860 return; \
6861 } \
6862 gen_set_access_type(ctx, ACCESS_INT); \
6863 EA = tcg_temp_new(); \
6864 gen_addr_reg_index(ctx, EA); \
6865 if (size > 1) { \
6866 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6867 } \
6868 rs = gen_avr_ptr(rS(ctx->opcode)); \
6869 gen_helper_lve##name(cpu_env, rs, EA); \
6870 tcg_temp_free(EA); \
6871 tcg_temp_free_ptr(rs); \
6872 }
6873
6874 #define GEN_VR_STVE(name, opc2, opc3, size) \
6875 static void gen_stve##name(DisasContext *ctx) \
6876 { \
6877 TCGv EA; \
6878 TCGv_ptr rs; \
6879 if (unlikely(!ctx->altivec_enabled)) { \
6880 gen_exception(ctx, POWERPC_EXCP_VPU); \
6881 return; \
6882 } \
6883 gen_set_access_type(ctx, ACCESS_INT); \
6884 EA = tcg_temp_new(); \
6885 gen_addr_reg_index(ctx, EA); \
6886 if (size > 1) { \
6887 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6888 } \
6889 rs = gen_avr_ptr(rS(ctx->opcode)); \
6890 gen_helper_stve##name(cpu_env, rs, EA); \
6891 tcg_temp_free(EA); \
6892 tcg_temp_free_ptr(rs); \
6893 }
6894
6895 GEN_VR_LDX(lvx, 0x07, 0x03);
6896 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6897 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6898
6899 GEN_VR_LVE(bx, 0x07, 0x00, 1);
6900 GEN_VR_LVE(hx, 0x07, 0x01, 2);
6901 GEN_VR_LVE(wx, 0x07, 0x02, 4);
6902
6903 GEN_VR_STX(svx, 0x07, 0x07);
6904 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6905 GEN_VR_STX(svxl, 0x07, 0x0F);
6906
6907 GEN_VR_STVE(bx, 0x07, 0x04, 1);
6908 GEN_VR_STVE(hx, 0x07, 0x05, 2);
6909 GEN_VR_STVE(wx, 0x07, 0x06, 4);
6910
6911 static void gen_lvsl(DisasContext *ctx)
6912 {
6913 TCGv_ptr rd;
6914 TCGv EA;
6915 if (unlikely(!ctx->altivec_enabled)) {
6916 gen_exception(ctx, POWERPC_EXCP_VPU);
6917 return;
6918 }
6919 EA = tcg_temp_new();
6920 gen_addr_reg_index(ctx, EA);
6921 rd = gen_avr_ptr(rD(ctx->opcode));
6922 gen_helper_lvsl(rd, EA);
6923 tcg_temp_free(EA);
6924 tcg_temp_free_ptr(rd);
6925 }
6926
6927 static void gen_lvsr(DisasContext *ctx)
6928 {
6929 TCGv_ptr rd;
6930 TCGv EA;
6931 if (unlikely(!ctx->altivec_enabled)) {
6932 gen_exception(ctx, POWERPC_EXCP_VPU);
6933 return;
6934 }
6935 EA = tcg_temp_new();
6936 gen_addr_reg_index(ctx, EA);
6937 rd = gen_avr_ptr(rD(ctx->opcode));
6938 gen_helper_lvsr(rd, EA);
6939 tcg_temp_free(EA);
6940 tcg_temp_free_ptr(rd);
6941 }
6942
6943 static void gen_mfvscr(DisasContext *ctx)
6944 {
6945 TCGv_i32 t;
6946 if (unlikely(!ctx->altivec_enabled)) {
6947 gen_exception(ctx, POWERPC_EXCP_VPU);
6948 return;
6949 }
6950 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6951 t = tcg_temp_new_i32();
6952 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6953 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6954 tcg_temp_free_i32(t);
6955 }
6956
6957 static void gen_mtvscr(DisasContext *ctx)
6958 {
6959 TCGv_ptr p;
6960 if (unlikely(!ctx->altivec_enabled)) {
6961 gen_exception(ctx, POWERPC_EXCP_VPU);
6962 return;
6963 }
6964 p = gen_avr_ptr(rB(ctx->opcode));
6965 gen_helper_mtvscr(cpu_env, p);
6966 tcg_temp_free_ptr(p);
6967 }
6968
6969 /* Logical operations */
6970 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6971 static void glue(gen_, name)(DisasContext *ctx) \
6972 { \
6973 if (unlikely(!ctx->altivec_enabled)) { \
6974 gen_exception(ctx, POWERPC_EXCP_VPU); \
6975 return; \
6976 } \
6977 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6978 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6979 }
6980
6981 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6982 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6983 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6984 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6985 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6986 GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
6987 GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
6988 GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
6989
6990 #define GEN_VXFORM(name, opc2, opc3) \
6991 static void glue(gen_, name)(DisasContext *ctx) \
6992 { \
6993 TCGv_ptr ra, rb, rd; \
6994 if (unlikely(!ctx->altivec_enabled)) { \
6995 gen_exception(ctx, POWERPC_EXCP_VPU); \
6996 return; \
6997 } \
6998 ra = gen_avr_ptr(rA(ctx->opcode)); \
6999 rb = gen_avr_ptr(rB(ctx->opcode)); \
7000 rd = gen_avr_ptr(rD(ctx->opcode)); \
7001 gen_helper_##name (rd, ra, rb); \
7002 tcg_temp_free_ptr(ra); \
7003 tcg_temp_free_ptr(rb); \
7004 tcg_temp_free_ptr(rd); \
7005 }
7006
7007 #define GEN_VXFORM_ENV(name, opc2, opc3) \
7008 static void glue(gen_, name)(DisasContext *ctx) \
7009 { \
7010 TCGv_ptr ra, rb, rd; \
7011 if (unlikely(!ctx->altivec_enabled)) { \
7012 gen_exception(ctx, POWERPC_EXCP_VPU); \
7013 return; \
7014 } \
7015 ra = gen_avr_ptr(rA(ctx->opcode)); \
7016 rb = gen_avr_ptr(rB(ctx->opcode)); \
7017 rd = gen_avr_ptr(rD(ctx->opcode)); \
7018 gen_helper_##name(cpu_env, rd, ra, rb); \
7019 tcg_temp_free_ptr(ra); \
7020 tcg_temp_free_ptr(rb); \
7021 tcg_temp_free_ptr(rd); \
7022 }
7023
7024 #define GEN_VXFORM3(name, opc2, opc3) \
7025 static void glue(gen_, name)(DisasContext *ctx) \
7026 { \
7027 TCGv_ptr ra, rb, rc, rd; \
7028 if (unlikely(!ctx->altivec_enabled)) { \
7029 gen_exception(ctx, POWERPC_EXCP_VPU); \
7030 return; \
7031 } \
7032 ra = gen_avr_ptr(rA(ctx->opcode)); \
7033 rb = gen_avr_ptr(rB(ctx->opcode)); \
7034 rc = gen_avr_ptr(rC(ctx->opcode)); \
7035 rd = gen_avr_ptr(rD(ctx->opcode)); \
7036 gen_helper_##name(rd, ra, rb, rc); \
7037 tcg_temp_free_ptr(ra); \
7038 tcg_temp_free_ptr(rb); \
7039 tcg_temp_free_ptr(rc); \
7040 tcg_temp_free_ptr(rd); \
7041 }
7042
7043 /*
7044 * Support for Altivec instruction pairs that use bit 31 (Rc) as
7045 * an opcode bit. In general, these pairs come from different
7046 * versions of the ISA, so we must also support a pair of flags for
7047 * each instruction.
7048 */
7049 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7050 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7051 { \
7052 if ((Rc(ctx->opcode) == 0) && \
7053 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7054 gen_##name0(ctx); \
7055 } else if ((Rc(ctx->opcode) == 1) && \
7056 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7057 gen_##name1(ctx); \
7058 } else { \
7059 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7060 } \
7061 }
7062
7063 GEN_VXFORM(vaddubm, 0, 0);
7064 GEN_VXFORM(vadduhm, 0, 1);
7065 GEN_VXFORM(vadduwm, 0, 2);
7066 GEN_VXFORM(vaddudm, 0, 3);
7067 GEN_VXFORM(vsububm, 0, 16);
7068 GEN_VXFORM(vsubuhm, 0, 17);
7069 GEN_VXFORM(vsubuwm, 0, 18);
7070 GEN_VXFORM(vsubudm, 0, 19);
7071 GEN_VXFORM(vmaxub, 1, 0);
7072 GEN_VXFORM(vmaxuh, 1, 1);
7073 GEN_VXFORM(vmaxuw, 1, 2);
7074 GEN_VXFORM(vmaxud, 1, 3);
7075 GEN_VXFORM(vmaxsb, 1, 4);
7076 GEN_VXFORM(vmaxsh, 1, 5);
7077 GEN_VXFORM(vmaxsw, 1, 6);
7078 GEN_VXFORM(vmaxsd, 1, 7);
7079 GEN_VXFORM(vminub, 1, 8);
7080 GEN_VXFORM(vminuh, 1, 9);
7081 GEN_VXFORM(vminuw, 1, 10);
7082 GEN_VXFORM(vminud, 1, 11);
7083 GEN_VXFORM(vminsb, 1, 12);
7084 GEN_VXFORM(vminsh, 1, 13);
7085 GEN_VXFORM(vminsw, 1, 14);
7086 GEN_VXFORM(vminsd, 1, 15);
7087 GEN_VXFORM(vavgub, 1, 16);
7088 GEN_VXFORM(vavguh, 1, 17);
7089 GEN_VXFORM(vavguw, 1, 18);
7090 GEN_VXFORM(vavgsb, 1, 20);
7091 GEN_VXFORM(vavgsh, 1, 21);
7092 GEN_VXFORM(vavgsw, 1, 22);
7093 GEN_VXFORM(vmrghb, 6, 0);
7094 GEN_VXFORM(vmrghh, 6, 1);
7095 GEN_VXFORM(vmrghw, 6, 2);
7096 GEN_VXFORM(vmrglb, 6, 4);
7097 GEN_VXFORM(vmrglh, 6, 5);
7098 GEN_VXFORM(vmrglw, 6, 6);
7099
7100 static void gen_vmrgew(DisasContext *ctx)
7101 {
7102 TCGv_i64 tmp;
7103 int VT, VA, VB;
7104 if (unlikely(!ctx->altivec_enabled)) {
7105 gen_exception(ctx, POWERPC_EXCP_VPU);
7106 return;
7107 }
7108 VT = rD(ctx->opcode);
7109 VA = rA(ctx->opcode);
7110 VB = rB(ctx->opcode);
7111 tmp = tcg_temp_new_i64();
7112 tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32);
7113 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32);
7114 tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32);
7115 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32);
7116 tcg_temp_free_i64(tmp);
7117 }
7118
7119 static void gen_vmrgow(DisasContext *ctx)
7120 {
7121 int VT, VA, VB;
7122 if (unlikely(!ctx->altivec_enabled)) {
7123 gen_exception(ctx, POWERPC_EXCP_VPU);
7124 return;
7125 }
7126 VT = rD(ctx->opcode);
7127 VA = rA(ctx->opcode);
7128 VB = rB(ctx->opcode);
7129
7130 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32);
7131 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32);
7132 }
7133
7134 GEN_VXFORM(vmuloub, 4, 0);
7135 GEN_VXFORM(vmulouh, 4, 1);
7136 GEN_VXFORM(vmulouw, 4, 2);
7137 GEN_VXFORM(vmuluwm, 4, 2);
7138 GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
7139 vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
7140 GEN_VXFORM(vmulosb, 4, 4);
7141 GEN_VXFORM(vmulosh, 4, 5);
7142 GEN_VXFORM(vmulosw, 4, 6);
7143 GEN_VXFORM(vmuleub, 4, 8);
7144 GEN_VXFORM(vmuleuh, 4, 9);
7145 GEN_VXFORM(vmuleuw, 4, 10);
7146 GEN_VXFORM(vmulesb, 4, 12);
7147 GEN_VXFORM(vmulesh, 4, 13);
7148 GEN_VXFORM(vmulesw, 4, 14);
7149 GEN_VXFORM(vslb, 2, 4);
7150 GEN_VXFORM(vslh, 2, 5);
7151 GEN_VXFORM(vslw, 2, 6);
7152 GEN_VXFORM(vsld, 2, 23);
7153 GEN_VXFORM(vsrb, 2, 8);
7154 GEN_VXFORM(vsrh, 2, 9);
7155 GEN_VXFORM(vsrw, 2, 10);
7156 GEN_VXFORM(vsrd, 2, 27);
7157 GEN_VXFORM(vsrab, 2, 12);
7158 GEN_VXFORM(vsrah, 2, 13);
7159 GEN_VXFORM(vsraw, 2, 14);
7160 GEN_VXFORM(vsrad, 2, 15);
7161 GEN_VXFORM(vslo, 6, 16);
7162 GEN_VXFORM(vsro, 6, 17);
7163 GEN_VXFORM(vaddcuw, 0, 6);
7164 GEN_VXFORM(vsubcuw, 0, 22);
7165 GEN_VXFORM_ENV(vaddubs, 0, 8);
7166 GEN_VXFORM_ENV(vadduhs, 0, 9);
7167 GEN_VXFORM_ENV(vadduws, 0, 10);
7168 GEN_VXFORM_ENV(vaddsbs, 0, 12);
7169 GEN_VXFORM_ENV(vaddshs, 0, 13);
7170 GEN_VXFORM_ENV(vaddsws, 0, 14);
7171 GEN_VXFORM_ENV(vsububs, 0, 24);
7172 GEN_VXFORM_ENV(vsubuhs, 0, 25);
7173 GEN_VXFORM_ENV(vsubuws, 0, 26);
7174 GEN_VXFORM_ENV(vsubsbs, 0, 28);
7175 GEN_VXFORM_ENV(vsubshs, 0, 29);
7176 GEN_VXFORM_ENV(vsubsws, 0, 30);
7177 GEN_VXFORM(vadduqm, 0, 4);
7178 GEN_VXFORM(vaddcuq, 0, 5);
7179 GEN_VXFORM3(vaddeuqm, 30, 0);
7180 GEN_VXFORM3(vaddecuq, 30, 0);
7181 GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7182 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
7183 GEN_VXFORM(vsubuqm, 0, 20);
7184 GEN_VXFORM(vsubcuq, 0, 21);
7185 GEN_VXFORM3(vsubeuqm, 31, 0);
7186 GEN_VXFORM3(vsubecuq, 31, 0);
7187 GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7188 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
7189 GEN_VXFORM(vrlb, 2, 0);
7190 GEN_VXFORM(vrlh, 2, 1);
7191 GEN_VXFORM(vrlw, 2, 2);
7192 GEN_VXFORM(vrld, 2, 3);
7193 GEN_VXFORM(vsl, 2, 7);
7194 GEN_VXFORM(vsr, 2, 11);
7195 GEN_VXFORM_ENV(vpkuhum, 7, 0);
7196 GEN_VXFORM_ENV(vpkuwum, 7, 1);
7197 GEN_VXFORM_ENV(vpkudum, 7, 17);
7198 GEN_VXFORM_ENV(vpkuhus, 7, 2);
7199 GEN_VXFORM_ENV(vpkuwus, 7, 3);
7200 GEN_VXFORM_ENV(vpkudus, 7, 19);
7201 GEN_VXFORM_ENV(vpkshus, 7, 4);
7202 GEN_VXFORM_ENV(vpkswus, 7, 5);
7203 GEN_VXFORM_ENV(vpksdus, 7, 21);
7204 GEN_VXFORM_ENV(vpkshss, 7, 6);
7205 GEN_VXFORM_ENV(vpkswss, 7, 7);
7206 GEN_VXFORM_ENV(vpksdss, 7, 23);
7207 GEN_VXFORM(vpkpx, 7, 12);
7208 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
7209 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
7210 GEN_VXFORM_ENV(vsum4shs, 4, 25);
7211 GEN_VXFORM_ENV(vsum2sws, 4, 26);
7212 GEN_VXFORM_ENV(vsumsws, 4, 30);
7213 GEN_VXFORM_ENV(vaddfp, 5, 0);
7214 GEN_VXFORM_ENV(vsubfp, 5, 1);
7215 GEN_VXFORM_ENV(vmaxfp, 5, 16);
7216 GEN_VXFORM_ENV(vminfp, 5, 17);
7217
7218 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
7219 static void glue(gen_, name)(DisasContext *ctx) \
7220 { \
7221 TCGv_ptr ra, rb, rd; \
7222 if (unlikely(!ctx->altivec_enabled)) { \
7223 gen_exception(ctx, POWERPC_EXCP_VPU); \
7224 return; \
7225 } \
7226 ra = gen_avr_ptr(rA(ctx->opcode)); \
7227 rb = gen_avr_ptr(rB(ctx->opcode)); \
7228 rd = gen_avr_ptr(rD(ctx->opcode)); \
7229 gen_helper_##opname(cpu_env, rd, ra, rb); \
7230 tcg_temp_free_ptr(ra); \
7231 tcg_temp_free_ptr(rb); \
7232 tcg_temp_free_ptr(rd); \
7233 }
7234
7235 #define GEN_VXRFORM(name, opc2, opc3) \
7236 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
7237 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
7238
7239 /*
7240 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
7241 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
7242 * come from different versions of the ISA, so we must also support a
7243 * pair of flags for each instruction.
7244 */
7245 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7246 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7247 { \
7248 if ((Rc(ctx->opcode) == 0) && \
7249 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7250 if (Rc21(ctx->opcode) == 0) { \
7251 gen_##name0(ctx); \
7252 } else { \
7253 gen_##name0##_(ctx); \
7254 } \
7255 } else if ((Rc(ctx->opcode) == 1) && \
7256 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7257 if (Rc21(ctx->opcode) == 0) { \
7258 gen_##name1(ctx); \
7259 } else { \
7260 gen_##name1##_(ctx); \
7261 } \
7262 } else { \
7263 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7264 } \
7265 }
7266
7267 GEN_VXRFORM(vcmpequb, 3, 0)
7268 GEN_VXRFORM(vcmpequh, 3, 1)
7269 GEN_VXRFORM(vcmpequw, 3, 2)
7270 GEN_VXRFORM(vcmpequd, 3, 3)
7271 GEN_VXRFORM(vcmpgtsb, 3, 12)
7272 GEN_VXRFORM(vcmpgtsh, 3, 13)
7273 GEN_VXRFORM(vcmpgtsw, 3, 14)
7274 GEN_VXRFORM(vcmpgtsd, 3, 15)
7275 GEN_VXRFORM(vcmpgtub, 3, 8)
7276 GEN_VXRFORM(vcmpgtuh, 3, 9)
7277 GEN_VXRFORM(vcmpgtuw, 3, 10)
7278 GEN_VXRFORM(vcmpgtud, 3, 11)
7279 GEN_VXRFORM(vcmpeqfp, 3, 3)
7280 GEN_VXRFORM(vcmpgefp, 3, 7)
7281 GEN_VXRFORM(vcmpgtfp, 3, 11)
7282 GEN_VXRFORM(vcmpbfp, 3, 15)
7283
7284 GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
7285 vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
7286 GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
7287 vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
7288 GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
7289 vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
7290
7291 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7292 static void glue(gen_, name)(DisasContext *ctx) \
7293 { \
7294 TCGv_ptr rd; \
7295 TCGv_i32 simm; \
7296 if (unlikely(!ctx->altivec_enabled)) { \
7297 gen_exception(ctx, POWERPC_EXCP_VPU); \
7298 return; \
7299 } \
7300 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7301 rd = gen_avr_ptr(rD(ctx->opcode)); \
7302 gen_helper_##name (rd, simm); \
7303 tcg_temp_free_i32(simm); \
7304 tcg_temp_free_ptr(rd); \
7305 }
7306
7307 GEN_VXFORM_SIMM(vspltisb, 6, 12);
7308 GEN_VXFORM_SIMM(vspltish, 6, 13);
7309 GEN_VXFORM_SIMM(vspltisw, 6, 14);
7310
7311 #define GEN_VXFORM_NOA(name, opc2, opc3) \
7312 static void glue(gen_, name)(DisasContext *ctx) \
7313 { \
7314 TCGv_ptr rb, rd; \
7315 if (unlikely(!ctx->altivec_enabled)) { \
7316 gen_exception(ctx, POWERPC_EXCP_VPU); \
7317 return; \
7318 } \
7319 rb = gen_avr_ptr(rB(ctx->opcode)); \
7320 rd = gen_avr_ptr(rD(ctx->opcode)); \
7321 gen_helper_##name (rd, rb); \
7322 tcg_temp_free_ptr(rb); \
7323 tcg_temp_free_ptr(rd); \
7324 }
7325
7326 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
7327 static void glue(gen_, name)(DisasContext *ctx) \
7328 { \
7329 TCGv_ptr rb, rd; \
7330 \
7331 if (unlikely(!ctx->altivec_enabled)) { \
7332 gen_exception(ctx, POWERPC_EXCP_VPU); \
7333 return; \
7334 } \
7335 rb = gen_avr_ptr(rB(ctx->opcode)); \
7336 rd = gen_avr_ptr(rD(ctx->opcode)); \
7337 gen_helper_##name(cpu_env, rd, rb); \
7338 tcg_temp_free_ptr(rb); \
7339 tcg_temp_free_ptr(rd); \
7340 }
7341
7342 GEN_VXFORM_NOA(vupkhsb, 7, 8);
7343 GEN_VXFORM_NOA(vupkhsh, 7, 9);
7344 GEN_VXFORM_NOA(vupkhsw, 7, 25);
7345 GEN_VXFORM_NOA(vupklsb, 7, 10);
7346 GEN_VXFORM_NOA(vupklsh, 7, 11);
7347 GEN_VXFORM_NOA(vupklsw, 7, 27);
7348 GEN_VXFORM_NOA(vupkhpx, 7, 13);
7349 GEN_VXFORM_NOA(vupklpx, 7, 15);
7350 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
7351 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
7352 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
7353 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
7354 GEN_VXFORM_NOA_ENV(vrfim, 5, 11);
7355 GEN_VXFORM_NOA_ENV(vrfin, 5, 8);
7356 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
7357 GEN_VXFORM_NOA_ENV(vrfiz, 5, 9);
7358
7359 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7360 static void glue(gen_, name)(DisasContext *ctx) \
7361 { \
7362 TCGv_ptr rd; \
7363 TCGv_i32 simm; \
7364 if (unlikely(!ctx->altivec_enabled)) { \
7365 gen_exception(ctx, POWERPC_EXCP_VPU); \
7366 return; \
7367 } \
7368 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7369 rd = gen_avr_ptr(rD(ctx->opcode)); \
7370 gen_helper_##name (rd, simm); \
7371 tcg_temp_free_i32(simm); \
7372 tcg_temp_free_ptr(rd); \
7373 }
7374
7375 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
7376 static void glue(gen_, name)(DisasContext *ctx) \
7377 { \
7378 TCGv_ptr rb, rd; \
7379 TCGv_i32 uimm; \
7380 if (unlikely(!ctx->altivec_enabled)) { \
7381 gen_exception(ctx, POWERPC_EXCP_VPU); \
7382 return; \
7383 } \
7384 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7385 rb = gen_avr_ptr(rB(ctx->opcode)); \
7386 rd = gen_avr_ptr(rD(ctx->opcode)); \
7387 gen_helper_##name (rd, rb, uimm); \
7388 tcg_temp_free_i32(uimm); \
7389 tcg_temp_free_ptr(rb); \
7390 tcg_temp_free_ptr(rd); \
7391 }
7392
7393 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7394 static void glue(gen_, name)(DisasContext *ctx) \
7395 { \
7396 TCGv_ptr rb, rd; \
7397 TCGv_i32 uimm; \
7398 \
7399 if (unlikely(!ctx->altivec_enabled)) { \
7400 gen_exception(ctx, POWERPC_EXCP_VPU); \
7401 return; \
7402 } \
7403 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7404 rb = gen_avr_ptr(rB(ctx->opcode)); \
7405 rd = gen_avr_ptr(rD(ctx->opcode)); \
7406 gen_helper_##name(cpu_env, rd, rb, uimm); \
7407 tcg_temp_free_i32(uimm); \
7408 tcg_temp_free_ptr(rb); \
7409 tcg_temp_free_ptr(rd); \
7410 }
7411
7412 GEN_VXFORM_UIMM(vspltb, 6, 8);
7413 GEN_VXFORM_UIMM(vsplth, 6, 9);
7414 GEN_VXFORM_UIMM(vspltw, 6, 10);
7415 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
7416 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
7417 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
7418 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
7419
7420 static void gen_vsldoi(DisasContext *ctx)
7421 {
7422 TCGv_ptr ra, rb, rd;
7423 TCGv_i32 sh;
7424 if (unlikely(!ctx->altivec_enabled)) {
7425 gen_exception(ctx, POWERPC_EXCP_VPU);
7426 return;
7427 }
7428 ra = gen_avr_ptr(rA(ctx->opcode));
7429 rb = gen_avr_ptr(rB(ctx->opcode));
7430 rd = gen_avr_ptr(rD(ctx->opcode));
7431 sh = tcg_const_i32(VSH(ctx->opcode));
7432 gen_helper_vsldoi (rd, ra, rb, sh);
7433 tcg_temp_free_ptr(ra);
7434 tcg_temp_free_ptr(rb);
7435 tcg_temp_free_ptr(rd);
7436 tcg_temp_free_i32(sh);
7437 }
7438
7439 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
7440 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7441 { \
7442 TCGv_ptr ra, rb, rc, rd; \
7443 if (unlikely(!ctx->altivec_enabled)) { \
7444 gen_exception(ctx, POWERPC_EXCP_VPU); \
7445 return; \
7446 } \
7447 ra = gen_avr_ptr(rA(ctx->opcode)); \
7448 rb = gen_avr_ptr(rB(ctx->opcode)); \
7449 rc = gen_avr_ptr(rC(ctx->opcode)); \
7450 rd = gen_avr_ptr(rD(ctx->opcode)); \
7451 if (Rc(ctx->opcode)) { \
7452 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
7453 } else { \
7454 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
7455 } \
7456 tcg_temp_free_ptr(ra); \
7457 tcg_temp_free_ptr(rb); \
7458 tcg_temp_free_ptr(rc); \
7459 tcg_temp_free_ptr(rd); \
7460 }
7461
7462 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
7463
7464 static void gen_vmladduhm(DisasContext *ctx)
7465 {
7466 TCGv_ptr ra, rb, rc, rd;
7467 if (unlikely(!ctx->altivec_enabled)) {
7468 gen_exception(ctx, POWERPC_EXCP_VPU);
7469 return;
7470 }
7471 ra = gen_avr_ptr(rA(ctx->opcode));
7472 rb = gen_avr_ptr(rB(ctx->opcode));
7473 rc = gen_avr_ptr(rC(ctx->opcode));
7474 rd = gen_avr_ptr(rD(ctx->opcode));
7475 gen_helper_vmladduhm(rd, ra, rb, rc);
7476 tcg_temp_free_ptr(ra);
7477 tcg_temp_free_ptr(rb);
7478 tcg_temp_free_ptr(rc);
7479 tcg_temp_free_ptr(rd);
7480 }
7481
7482 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
7483 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
7484 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
7485 GEN_VAFORM_PAIRED(vsel, vperm, 21)
7486 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
7487
7488 GEN_VXFORM_NOA(vclzb, 1, 28)
7489 GEN_VXFORM_NOA(vclzh, 1, 29)
7490 GEN_VXFORM_NOA(vclzw, 1, 30)
7491 GEN_VXFORM_NOA(vclzd, 1, 31)
7492 GEN_VXFORM_NOA(vpopcntb, 1, 28)
7493 GEN_VXFORM_NOA(vpopcnth, 1, 29)
7494 GEN_VXFORM_NOA(vpopcntw, 1, 30)
7495 GEN_VXFORM_NOA(vpopcntd, 1, 31)
7496 GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
7497 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
7498 GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
7499 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
7500 GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
7501 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
7502 GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
7503 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
7504 GEN_VXFORM(vbpermq, 6, 21);
7505 GEN_VXFORM_NOA(vgbbd, 6, 20);
7506 GEN_VXFORM(vpmsumb, 4, 16)
7507 GEN_VXFORM(vpmsumh, 4, 17)
7508 GEN_VXFORM(vpmsumw, 4, 18)
7509 GEN_VXFORM(vpmsumd, 4, 19)
7510
7511 #define GEN_BCD(op) \
7512 static void gen_##op(DisasContext *ctx) \
7513 { \
7514 TCGv_ptr ra, rb, rd; \
7515 TCGv_i32 ps; \
7516 \
7517 if (unlikely(!ctx->altivec_enabled)) { \
7518 gen_exception(ctx, POWERPC_EXCP_VPU); \
7519 return; \
7520 } \
7521 \
7522 ra = gen_avr_ptr(rA(ctx->opcode)); \
7523 rb = gen_avr_ptr(rB(ctx->opcode)); \
7524 rd = gen_avr_ptr(rD(ctx->opcode)); \
7525 \
7526 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
7527 \
7528 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
7529 \
7530 tcg_temp_free_ptr(ra); \
7531 tcg_temp_free_ptr(rb); \
7532 tcg_temp_free_ptr(rd); \
7533 tcg_temp_free_i32(ps); \
7534 }
7535
7536 GEN_BCD(bcdadd)
7537 GEN_BCD(bcdsub)
7538
7539 GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
7540 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7541 GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
7542 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7543 GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
7544 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7545 GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
7546 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7547
7548 static void gen_vsbox(DisasContext *ctx)
7549 {
7550 TCGv_ptr ra, rd;
7551 if (unlikely(!ctx->altivec_enabled)) {
7552 gen_exception(ctx, POWERPC_EXCP_VPU);
7553 return;
7554 }
7555 ra = gen_avr_ptr(rA(ctx->opcode));
7556 rd = gen_avr_ptr(rD(ctx->opcode));
7557 gen_helper_vsbox(rd, ra);
7558 tcg_temp_free_ptr(ra);
7559 tcg_temp_free_ptr(rd);
7560 }
7561
7562 GEN_VXFORM(vcipher, 4, 20)
7563 GEN_VXFORM(vcipherlast, 4, 20)
7564 GEN_VXFORM(vncipher, 4, 21)
7565 GEN_VXFORM(vncipherlast, 4, 21)
7566
7567 GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
7568 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7569 GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
7570 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7571
7572 #define VSHASIGMA(op) \
7573 static void gen_##op(DisasContext *ctx) \
7574 { \
7575 TCGv_ptr ra, rd; \
7576 TCGv_i32 st_six; \
7577 if (unlikely(!ctx->altivec_enabled)) { \
7578 gen_exception(ctx, POWERPC_EXCP_VPU); \
7579 return; \
7580 } \
7581 ra = gen_avr_ptr(rA(ctx->opcode)); \
7582 rd = gen_avr_ptr(rD(ctx->opcode)); \
7583 st_six = tcg_const_i32(rB(ctx->opcode)); \
7584 gen_helper_##op(rd, ra, st_six); \
7585 tcg_temp_free_ptr(ra); \
7586 tcg_temp_free_ptr(rd); \
7587 tcg_temp_free_i32(st_six); \
7588 }
7589
7590 VSHASIGMA(vshasigmaw)
7591 VSHASIGMA(vshasigmad)
7592
7593 GEN_VXFORM3(vpermxor, 22, 0xFF)
7594 GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
7595 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
7596
7597 /*** VSX extension ***/
7598
7599 static inline TCGv_i64 cpu_vsrh(int n)
7600 {
7601 if (n < 32) {
7602 return cpu_fpr[n];
7603 } else {
7604 return cpu_avrh[n-32];
7605 }
7606 }
7607
7608 static inline TCGv_i64 cpu_vsrl(int n)
7609 {
7610 if (n < 32) {
7611 return cpu_vsr[n];
7612 } else {
7613 return cpu_avrl[n-32];
7614 }
7615 }
7616
7617 #define VSX_LOAD_SCALAR(name, operation) \
7618 static void gen_##name(DisasContext *ctx) \
7619 { \
7620 TCGv EA; \
7621 if (unlikely(!ctx->vsx_enabled)) { \
7622 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7623 return; \
7624 } \
7625 gen_set_access_type(ctx, ACCESS_INT); \
7626 EA = tcg_temp_new(); \
7627 gen_addr_reg_index(ctx, EA); \
7628 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7629 /* NOTE: cpu_vsrl is undefined */ \
7630 tcg_temp_free(EA); \
7631 }
7632
7633 VSX_LOAD_SCALAR(lxsdx, ld64)
7634 VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
7635 VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
7636 VSX_LOAD_SCALAR(lxsspx, ld32fs)
7637
7638 static void gen_lxvd2x(DisasContext *ctx)
7639 {
7640 TCGv EA;
7641 if (unlikely(!ctx->vsx_enabled)) {
7642 gen_exception(ctx, POWERPC_EXCP_VSXU);
7643 return;
7644 }
7645 gen_set_access_type(ctx, ACCESS_INT);
7646 EA = tcg_temp_new();
7647 gen_addr_reg_index(ctx, EA);
7648 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7649 tcg_gen_addi_tl(EA, EA, 8);
7650 gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
7651 tcg_temp_free(EA);
7652 }
7653
7654 static void gen_lxvdsx(DisasContext *ctx)
7655 {
7656 TCGv EA;
7657 if (unlikely(!ctx->vsx_enabled)) {
7658 gen_exception(ctx, POWERPC_EXCP_VSXU);
7659 return;
7660 }
7661 gen_set_access_type(ctx, ACCESS_INT);
7662 EA = tcg_temp_new();
7663 gen_addr_reg_index(ctx, EA);
7664 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7665 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
7666 tcg_temp_free(EA);
7667 }
7668
7669 static void gen_lxvw4x(DisasContext *ctx)
7670 {
7671 TCGv EA;
7672 TCGv_i64 tmp;
7673 TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
7674 TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
7675 if (unlikely(!ctx->vsx_enabled)) {
7676 gen_exception(ctx, POWERPC_EXCP_VSXU);
7677 return;
7678 }
7679 gen_set_access_type(ctx, ACCESS_INT);
7680 EA = tcg_temp_new();
7681 tmp = tcg_temp_new_i64();
7682
7683 gen_addr_reg_index(ctx, EA);
7684 gen_qemu_ld32u_i64(ctx, tmp, EA);
7685 tcg_gen_addi_tl(EA, EA, 4);
7686 gen_qemu_ld32u_i64(ctx, xth, EA);
7687 tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
7688
7689 tcg_gen_addi_tl(EA, EA, 4);
7690 gen_qemu_ld32u_i64(ctx, tmp, EA);
7691 tcg_gen_addi_tl(EA, EA, 4);
7692 gen_qemu_ld32u_i64(ctx, xtl, EA);
7693 tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
7694
7695 tcg_temp_free(EA);
7696 tcg_temp_free_i64(tmp);
7697 }
7698
7699 #define VSX_STORE_SCALAR(name, operation) \
7700 static void gen_##name(DisasContext *ctx) \
7701 { \
7702 TCGv EA; \
7703 if (unlikely(!ctx->vsx_enabled)) { \
7704 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7705 return; \
7706 } \
7707 gen_set_access_type(ctx, ACCESS_INT); \
7708 EA = tcg_temp_new(); \
7709 gen_addr_reg_index(ctx, EA); \
7710 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7711 tcg_temp_free(EA); \
7712 }
7713
7714 VSX_STORE_SCALAR(stxsdx, st64)
7715 VSX_STORE_SCALAR(stxsiwx, st32_i64)
7716 VSX_STORE_SCALAR(stxsspx, st32fs)
7717
7718 static void gen_stxvd2x(DisasContext *ctx)
7719 {
7720 TCGv EA;
7721 if (unlikely(!ctx->vsx_enabled)) {
7722 gen_exception(ctx, POWERPC_EXCP_VSXU);
7723 return;
7724 }
7725 gen_set_access_type(ctx, ACCESS_INT);
7726 EA = tcg_temp_new();
7727 gen_addr_reg_index(ctx, EA);
7728 gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7729 tcg_gen_addi_tl(EA, EA, 8);
7730 gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7731 tcg_temp_free(EA);
7732 }
7733
7734 static void gen_stxvw4x(DisasContext *ctx)
7735 {
7736 TCGv_i64 tmp;
7737 TCGv EA;
7738 if (unlikely(!ctx->vsx_enabled)) {
7739 gen_exception(ctx, POWERPC_EXCP_VSXU);
7740 return;
7741 }
7742 gen_set_access_type(ctx, ACCESS_INT);
7743 EA = tcg_temp_new();
7744 gen_addr_reg_index(ctx, EA);
7745 tmp = tcg_temp_new_i64();
7746
7747 tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
7748 gen_qemu_st32_i64(ctx, tmp, EA);
7749 tcg_gen_addi_tl(EA, EA, 4);
7750 gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7751
7752 tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
7753 tcg_gen_addi_tl(EA, EA, 4);
7754 gen_qemu_st32_i64(ctx, tmp, EA);
7755 tcg_gen_addi_tl(EA, EA, 4);
7756 gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7757
7758 tcg_temp_free(EA);
7759 tcg_temp_free_i64(tmp);
7760 }
7761
7762 #define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7763 static void gen_##name(DisasContext *ctx) \
7764 { \
7765 if (xS(ctx->opcode) < 32) { \
7766 if (unlikely(!ctx->fpu_enabled)) { \
7767 gen_exception(ctx, POWERPC_EXCP_FPU); \
7768 return; \
7769 } \
7770 } else { \
7771 if (unlikely(!ctx->altivec_enabled)) { \
7772 gen_exception(ctx, POWERPC_EXCP_VPU); \
7773 return; \
7774 } \
7775 } \
7776 TCGv_i64 tmp = tcg_temp_new_i64(); \
7777 tcg_gen_##tcgop1(tmp, source); \
7778 tcg_gen_##tcgop2(target, tmp); \
7779 tcg_temp_free_i64(tmp); \
7780 }
7781
7782
7783 MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
7784 cpu_vsrh(xS(ctx->opcode)))
7785 MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
7786 cpu_gpr[rA(ctx->opcode)])
7787 MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
7788 cpu_gpr[rA(ctx->opcode)])
7789
7790 #if defined(TARGET_PPC64)
7791 #define MV_VSRD(name, target, source) \
7792 static void gen_##name(DisasContext *ctx) \
7793 { \
7794 if (xS(ctx->opcode) < 32) { \
7795 if (unlikely(!ctx->fpu_enabled)) { \
7796 gen_exception(ctx, POWERPC_EXCP_FPU); \
7797 return; \
7798 } \
7799 } else { \
7800 if (unlikely(!ctx->altivec_enabled)) { \
7801 gen_exception(ctx, POWERPC_EXCP_VPU); \
7802 return; \
7803 } \
7804 } \
7805 tcg_gen_mov_i64(target, source); \
7806 }
7807
7808 MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
7809 MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
7810
7811 #endif
7812
7813 static void gen_xxpermdi(DisasContext *ctx)
7814 {
7815 if (unlikely(!ctx->vsx_enabled)) {
7816 gen_exception(ctx, POWERPC_EXCP_VSXU);
7817 return;
7818 }
7819
7820 if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
7821 (xT(ctx->opcode) == xB(ctx->opcode)))) {
7822 TCGv_i64 xh, xl;
7823
7824 xh = tcg_temp_new_i64();
7825 xl = tcg_temp_new_i64();
7826
7827 if ((DM(ctx->opcode) & 2) == 0) {
7828 tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode)));
7829 } else {
7830 tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode)));
7831 }
7832 if ((DM(ctx->opcode) & 1) == 0) {
7833 tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode)));
7834 } else {
7835 tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode)));
7836 }
7837
7838 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh);
7839 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl);
7840
7841 tcg_temp_free_i64(xh);
7842 tcg_temp_free_i64(xl);
7843 } else {
7844 if ((DM(ctx->opcode) & 2) == 0) {
7845 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
7846 } else {
7847 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
7848 }
7849 if ((DM(ctx->opcode) & 1) == 0) {
7850 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
7851 } else {
7852 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
7853 }
7854 }
7855 }
7856
7857 #define OP_ABS 1
7858 #define OP_NABS 2
7859 #define OP_NEG 3
7860 #define OP_CPSGN 4
7861 #define SGN_MASK_DP 0x8000000000000000ull
7862 #define SGN_MASK_SP 0x8000000080000000ull
7863
7864 #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7865 static void glue(gen_, name)(DisasContext * ctx) \
7866 { \
7867 TCGv_i64 xb, sgm; \
7868 if (unlikely(!ctx->vsx_enabled)) { \
7869 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7870 return; \
7871 } \
7872 xb = tcg_temp_new_i64(); \
7873 sgm = tcg_temp_new_i64(); \
7874 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7875 tcg_gen_movi_i64(sgm, sgn_mask); \
7876 switch (op) { \
7877 case OP_ABS: { \
7878 tcg_gen_andc_i64(xb, xb, sgm); \
7879 break; \
7880 } \
7881 case OP_NABS: { \
7882 tcg_gen_or_i64(xb, xb, sgm); \
7883 break; \
7884 } \
7885 case OP_NEG: { \
7886 tcg_gen_xor_i64(xb, xb, sgm); \
7887 break; \
7888 } \
7889 case OP_CPSGN: { \
7890 TCGv_i64 xa = tcg_temp_new_i64(); \
7891 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7892 tcg_gen_and_i64(xa, xa, sgm); \
7893 tcg_gen_andc_i64(xb, xb, sgm); \
7894 tcg_gen_or_i64(xb, xb, xa); \
7895 tcg_temp_free_i64(xa); \
7896 break; \
7897 } \
7898 } \
7899 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
7900 tcg_temp_free_i64(xb); \
7901 tcg_temp_free_i64(sgm); \
7902 }
7903
7904 VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
7905 VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
7906 VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
7907 VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
7908
7909 #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7910 static void glue(gen_, name)(DisasContext * ctx) \
7911 { \
7912 TCGv_i64 xbh, xbl, sgm; \
7913 if (unlikely(!ctx->vsx_enabled)) { \
7914 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7915 return; \
7916 } \
7917 xbh = tcg_temp_new_i64(); \
7918 xbl = tcg_temp_new_i64(); \
7919 sgm = tcg_temp_new_i64(); \
7920 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7921 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7922 tcg_gen_movi_i64(sgm, sgn_mask); \
7923 switch (op) { \
7924 case OP_ABS: { \
7925 tcg_gen_andc_i64(xbh, xbh, sgm); \
7926 tcg_gen_andc_i64(xbl, xbl, sgm); \
7927 break; \
7928 } \
7929 case OP_NABS: { \
7930 tcg_gen_or_i64(xbh, xbh, sgm); \
7931 tcg_gen_or_i64(xbl, xbl, sgm); \
7932 break; \
7933 } \
7934 case OP_NEG: { \
7935 tcg_gen_xor_i64(xbh, xbh, sgm); \
7936 tcg_gen_xor_i64(xbl, xbl, sgm); \
7937 break; \
7938 } \
7939 case OP_CPSGN: { \
7940 TCGv_i64 xah = tcg_temp_new_i64(); \
7941 TCGv_i64 xal = tcg_temp_new_i64(); \
7942 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
7943 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
7944 tcg_gen_and_i64(xah, xah, sgm); \
7945 tcg_gen_and_i64(xal, xal, sgm); \
7946 tcg_gen_andc_i64(xbh, xbh, sgm); \
7947 tcg_gen_andc_i64(xbl, xbl, sgm); \
7948 tcg_gen_or_i64(xbh, xbh, xah); \
7949 tcg_gen_or_i64(xbl, xbl, xal); \
7950 tcg_temp_free_i64(xah); \
7951 tcg_temp_free_i64(xal); \
7952 break; \
7953 } \
7954 } \
7955 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
7956 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
7957 tcg_temp_free_i64(xbh); \
7958 tcg_temp_free_i64(xbl); \
7959 tcg_temp_free_i64(sgm); \
7960 }
7961
7962 VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
7963 VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
7964 VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
7965 VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
7966 VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
7967 VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
7968 VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
7969 VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
7970
7971 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
7972 static void gen_##name(DisasContext * ctx) \
7973 { \
7974 TCGv_i32 opc; \
7975 if (unlikely(!ctx->vsx_enabled)) { \
7976 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7977 return; \
7978 } \
7979 /* NIP cannot be restored if the memory exception comes from an helper */ \
7980 gen_update_nip(ctx, ctx->nip - 4); \
7981 opc = tcg_const_i32(ctx->opcode); \
7982 gen_helper_##name(cpu_env, opc); \
7983 tcg_temp_free_i32(opc); \
7984 }
7985
7986 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
7987 static void gen_##name(DisasContext * ctx) \
7988 { \
7989 if (unlikely(!ctx->vsx_enabled)) { \
7990 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7991 return; \
7992 } \
7993 /* NIP cannot be restored if the exception comes */ \
7994 /* from a helper. */ \
7995 gen_update_nip(ctx, ctx->nip - 4); \
7996 \
7997 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
7998 cpu_vsrh(xB(ctx->opcode))); \
7999 }
8000
8001 GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
8002 GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
8003 GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
8004 GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
8005 GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
8006 GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
8007 GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
8008 GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
8009 GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
8010 GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
8011 GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
8012 GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
8013 GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
8014 GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
8015 GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
8016 GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
8017 GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
8018 GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
8019 GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
8020 GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
8021 GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
8022 GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
8023 GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
8024 GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
8025 GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
8026 GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
8027 GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
8028 GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
8029 GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
8030 GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
8031 GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
8032 GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
8033 GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
8034 GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
8035 GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
8036 GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
8037 GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
8038
8039 GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
8040 GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
8041 GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
8042 GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
8043 GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
8044 GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
8045 GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
8046 GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
8047 GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207)
8048 GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207)
8049 GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207)
8050 GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
8051 GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
8052 GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
8053 GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
8054 GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
8055 GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
8056
8057 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
8058 GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
8059 GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
8060 GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
8061 GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
8062 GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
8063 GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
8064 GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
8065 GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
8066 GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
8067 GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
8068 GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
8069 GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
8070 GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
8071 GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
8072 GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
8073 GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
8074 GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
8075 GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
8076 GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
8077 GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
8078 GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
8079 GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
8080 GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
8081 GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
8082 GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
8083 GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
8084 GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
8085 GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
8086 GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
8087 GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
8088 GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
8089 GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
8090 GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
8091 GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
8092 GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
8093
8094 GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
8095 GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
8096 GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
8097 GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
8098 GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
8099 GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
8100 GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
8101 GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
8102 GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
8103 GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
8104 GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
8105 GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
8106 GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
8107 GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
8108 GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
8109 GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
8110 GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
8111 GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
8112 GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
8113 GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
8114 GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
8115 GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
8116 GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
8117 GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
8118 GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
8119 GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
8120 GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
8121 GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
8122 GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
8123 GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
8124 GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
8125 GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
8126 GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
8127 GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
8128 GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
8129 GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
8130
8131 #define VSX_LOGICAL(name, tcg_op) \
8132 static void glue(gen_, name)(DisasContext * ctx) \
8133 { \
8134 if (unlikely(!ctx->vsx_enabled)) { \
8135 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8136 return; \
8137 } \
8138 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
8139 cpu_vsrh(xB(ctx->opcode))); \
8140 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
8141 cpu_vsrl(xB(ctx->opcode))); \
8142 }
8143
8144 VSX_LOGICAL(xxland, tcg_gen_and_i64)
8145 VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
8146 VSX_LOGICAL(xxlor, tcg_gen_or_i64)
8147 VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
8148 VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
8149 VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
8150 VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
8151 VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
8152
8153 #define VSX_XXMRG(name, high) \
8154 static void glue(gen_, name)(DisasContext * ctx) \
8155 { \
8156 TCGv_i64 a0, a1, b0, b1; \
8157 if (unlikely(!ctx->vsx_enabled)) { \
8158 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8159 return; \
8160 } \
8161 a0 = tcg_temp_new_i64(); \
8162 a1 = tcg_temp_new_i64(); \
8163 b0 = tcg_temp_new_i64(); \
8164 b1 = tcg_temp_new_i64(); \
8165 if (high) { \
8166 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
8167 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
8168 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
8169 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
8170 } else { \
8171 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
8172 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
8173 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
8174 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
8175 } \
8176 tcg_gen_shri_i64(a0, a0, 32); \
8177 tcg_gen_shri_i64(b0, b0, 32); \
8178 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
8179 b0, a0, 32, 32); \
8180 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
8181 b1, a1, 32, 32); \
8182 tcg_temp_free_i64(a0); \
8183 tcg_temp_free_i64(a1); \
8184 tcg_temp_free_i64(b0); \
8185 tcg_temp_free_i64(b1); \
8186 }
8187
8188 VSX_XXMRG(xxmrghw, 1)
8189 VSX_XXMRG(xxmrglw, 0)
8190
8191 static void gen_xxsel(DisasContext * ctx)
8192 {
8193 TCGv_i64 a, b, c;
8194 if (unlikely(!ctx->vsx_enabled)) {
8195 gen_exception(ctx, POWERPC_EXCP_VSXU);
8196 return;
8197 }
8198 a = tcg_temp_new_i64();
8199 b = tcg_temp_new_i64();
8200 c = tcg_temp_new_i64();
8201
8202 tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
8203 tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
8204 tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
8205
8206 tcg_gen_and_i64(b, b, c);
8207 tcg_gen_andc_i64(a, a, c);
8208 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
8209
8210 tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
8211 tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
8212 tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
8213
8214 tcg_gen_and_i64(b, b, c);
8215 tcg_gen_andc_i64(a, a, c);
8216 tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
8217
8218 tcg_temp_free_i64(a);
8219 tcg_temp_free_i64(b);
8220 tcg_temp_free_i64(c);
8221 }
8222
8223 static void gen_xxspltw(DisasContext *ctx)
8224 {
8225 TCGv_i64 b, b2;
8226 TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
8227 cpu_vsrl(xB(ctx->opcode)) :
8228 cpu_vsrh(xB(ctx->opcode));
8229
8230 if (unlikely(!ctx->vsx_enabled)) {
8231 gen_exception(ctx, POWERPC_EXCP_VSXU);
8232 return;
8233 }
8234
8235 b = tcg_temp_new_i64();
8236 b2 = tcg_temp_new_i64();
8237
8238 if (UIM(ctx->opcode) & 1) {
8239 tcg_gen_ext32u_i64(b, vsr);
8240 } else {
8241 tcg_gen_shri_i64(b, vsr, 32);
8242 }
8243
8244 tcg_gen_shli_i64(b2, b, 32);
8245 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
8246 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
8247
8248 tcg_temp_free_i64(b);
8249 tcg_temp_free_i64(b2);
8250 }
8251
8252 static void gen_xxsldwi(DisasContext *ctx)
8253 {
8254 TCGv_i64 xth, xtl;
8255 if (unlikely(!ctx->vsx_enabled)) {
8256 gen_exception(ctx, POWERPC_EXCP_VSXU);
8257 return;
8258 }
8259 xth = tcg_temp_new_i64();
8260 xtl = tcg_temp_new_i64();
8261
8262 switch (SHW(ctx->opcode)) {
8263 case 0: {
8264 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8265 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8266 break;
8267 }
8268 case 1: {
8269 TCGv_i64 t0 = tcg_temp_new_i64();
8270 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8271 tcg_gen_shli_i64(xth, xth, 32);
8272 tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
8273 tcg_gen_shri_i64(t0, t0, 32);
8274 tcg_gen_or_i64(xth, xth, t0);
8275 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8276 tcg_gen_shli_i64(xtl, xtl, 32);
8277 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8278 tcg_gen_shri_i64(t0, t0, 32);
8279 tcg_gen_or_i64(xtl, xtl, t0);
8280 tcg_temp_free_i64(t0);
8281 break;
8282 }
8283 case 2: {
8284 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8285 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8286 break;
8287 }
8288 case 3: {
8289 TCGv_i64 t0 = tcg_temp_new_i64();
8290 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8291 tcg_gen_shli_i64(xth, xth, 32);
8292 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8293 tcg_gen_shri_i64(t0, t0, 32);
8294 tcg_gen_or_i64(xth, xth, t0);
8295 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8296 tcg_gen_shli_i64(xtl, xtl, 32);
8297 tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
8298 tcg_gen_shri_i64(t0, t0, 32);
8299 tcg_gen_or_i64(xtl, xtl, t0);
8300 tcg_temp_free_i64(t0);
8301 break;
8302 }
8303 }
8304
8305 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
8306 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
8307
8308 tcg_temp_free_i64(xth);
8309 tcg_temp_free_i64(xtl);
8310 }
8311
8312 /*** Decimal Floating Point ***/
8313
8314 static inline TCGv_ptr gen_fprp_ptr(int reg)
8315 {
8316 TCGv_ptr r = tcg_temp_new_ptr();
8317 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, fpr[reg]));
8318 return r;
8319 }
8320
8321 #define GEN_DFP_T_A_B_Rc(name) \
8322 static void gen_##name(DisasContext *ctx) \
8323 { \
8324 TCGv_ptr rd, ra, rb; \
8325 if (unlikely(!ctx->fpu_enabled)) { \
8326 gen_exception(ctx, POWERPC_EXCP_FPU); \
8327 return; \
8328 } \
8329 gen_update_nip(ctx, ctx->nip - 4); \
8330 rd = gen_fprp_ptr(rD(ctx->opcode)); \
8331 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8332 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8333 gen_helper_##name(cpu_env, rd, ra, rb); \
8334 if (unlikely(Rc(ctx->opcode) != 0)) { \
8335 gen_set_cr1_from_fpscr(ctx); \
8336 } \
8337 tcg_temp_free_ptr(rd); \
8338 tcg_temp_free_ptr(ra); \
8339 tcg_temp_free_ptr(rb); \
8340 }
8341
8342 #define GEN_DFP_BF_A_B(name) \
8343 static void gen_##name(DisasContext *ctx) \
8344 { \
8345 TCGv_ptr ra, rb; \
8346 if (unlikely(!ctx->fpu_enabled)) { \
8347 gen_exception(ctx, POWERPC_EXCP_FPU); \
8348 return; \
8349 } \
8350 gen_update_nip(ctx, ctx->nip - 4); \
8351 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8352 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8353 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8354 cpu_env, ra, rb); \
8355 tcg_temp_free_ptr(ra); \
8356 tcg_temp_free_ptr(rb); \
8357 }
8358
8359 #define GEN_DFP_BF_A_DCM(name) \
8360 static void gen_##name(DisasContext *ctx) \
8361 { \
8362 TCGv_ptr ra; \
8363 TCGv_i32 dcm; \
8364 if (unlikely(!ctx->fpu_enabled)) { \
8365 gen_exception(ctx, POWERPC_EXCP_FPU); \
8366 return; \
8367 } \
8368 gen_update_nip(ctx, ctx->nip - 4); \
8369 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8370 dcm = tcg_const_i32(DCM(ctx->opcode)); \
8371 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8372 cpu_env, ra, dcm); \
8373 tcg_temp_free_ptr(ra); \
8374 tcg_temp_free_i32(dcm); \
8375 }
8376
8377 #define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
8378 static void gen_##name(DisasContext *ctx) \
8379 { \
8380 TCGv_ptr rt, rb; \
8381 TCGv_i32 u32_1, u32_2; \
8382 if (unlikely(!ctx->fpu_enabled)) { \
8383 gen_exception(ctx, POWERPC_EXCP_FPU); \
8384 return; \
8385 } \
8386 gen_update_nip(ctx, ctx->nip - 4); \
8387 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8388 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8389 u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
8390 u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
8391 gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
8392 if (unlikely(Rc(ctx->opcode) != 0)) { \
8393 gen_set_cr1_from_fpscr(ctx); \
8394 } \
8395 tcg_temp_free_ptr(rt); \
8396 tcg_temp_free_ptr(rb); \
8397 tcg_temp_free_i32(u32_1); \
8398 tcg_temp_free_i32(u32_2); \
8399 }
8400
8401 #define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
8402 static void gen_##name(DisasContext *ctx) \
8403 { \
8404 TCGv_ptr rt, ra, rb; \
8405 TCGv_i32 i32; \
8406 if (unlikely(!ctx->fpu_enabled)) { \
8407 gen_exception(ctx, POWERPC_EXCP_FPU); \
8408 return; \
8409 } \
8410 gen_update_nip(ctx, ctx->nip - 4); \
8411 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8412 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8413 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8414 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8415 gen_helper_##name(cpu_env, rt, ra, rb, i32); \
8416 if (unlikely(Rc(ctx->opcode) != 0)) { \
8417 gen_set_cr1_from_fpscr(ctx); \
8418 } \
8419 tcg_temp_free_ptr(rt); \
8420 tcg_temp_free_ptr(rb); \
8421 tcg_temp_free_ptr(ra); \
8422 tcg_temp_free_i32(i32); \
8423 }
8424
8425 #define GEN_DFP_T_B_Rc(name) \
8426 static void gen_##name(DisasContext *ctx) \
8427 { \
8428 TCGv_ptr rt, rb; \
8429 if (unlikely(!ctx->fpu_enabled)) { \
8430 gen_exception(ctx, POWERPC_EXCP_FPU); \
8431 return; \
8432 } \
8433 gen_update_nip(ctx, ctx->nip - 4); \
8434 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8435 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8436 gen_helper_##name(cpu_env, rt, rb); \
8437 if (unlikely(Rc(ctx->opcode) != 0)) { \
8438 gen_set_cr1_from_fpscr(ctx); \
8439 } \
8440 tcg_temp_free_ptr(rt); \
8441 tcg_temp_free_ptr(rb); \
8442 }
8443
8444 #define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
8445 static void gen_##name(DisasContext *ctx) \
8446 { \
8447 TCGv_ptr rt, rs; \
8448 TCGv_i32 i32; \
8449 if (unlikely(!ctx->fpu_enabled)) { \
8450 gen_exception(ctx, POWERPC_EXCP_FPU); \
8451 return; \
8452 } \
8453 gen_update_nip(ctx, ctx->nip - 4); \
8454 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8455 rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
8456 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8457 gen_helper_##name(cpu_env, rt, rs, i32); \
8458 if (unlikely(Rc(ctx->opcode) != 0)) { \
8459 gen_set_cr1_from_fpscr(ctx); \
8460 } \
8461 tcg_temp_free_ptr(rt); \
8462 tcg_temp_free_ptr(rs); \
8463 tcg_temp_free_i32(i32); \
8464 }
8465
8466 GEN_DFP_T_A_B_Rc(dadd)
8467 GEN_DFP_T_A_B_Rc(daddq)
8468 GEN_DFP_T_A_B_Rc(dsub)
8469 GEN_DFP_T_A_B_Rc(dsubq)
8470 GEN_DFP_T_A_B_Rc(dmul)
8471 GEN_DFP_T_A_B_Rc(dmulq)
8472 GEN_DFP_T_A_B_Rc(ddiv)
8473 GEN_DFP_T_A_B_Rc(ddivq)
8474 GEN_DFP_BF_A_B(dcmpu)
8475 GEN_DFP_BF_A_B(dcmpuq)
8476 GEN_DFP_BF_A_B(dcmpo)
8477 GEN_DFP_BF_A_B(dcmpoq)
8478 GEN_DFP_BF_A_DCM(dtstdc)
8479 GEN_DFP_BF_A_DCM(dtstdcq)
8480 GEN_DFP_BF_A_DCM(dtstdg)
8481 GEN_DFP_BF_A_DCM(dtstdgq)
8482 GEN_DFP_BF_A_B(dtstex)
8483 GEN_DFP_BF_A_B(dtstexq)
8484 GEN_DFP_BF_A_B(dtstsf)
8485 GEN_DFP_BF_A_B(dtstsfq)
8486 GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
8487 GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
8488 GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
8489 GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
8490 GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
8491 GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
8492 GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
8493 GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
8494 GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
8495 GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
8496 GEN_DFP_T_B_Rc(dctdp)
8497 GEN_DFP_T_B_Rc(dctqpq)
8498 GEN_DFP_T_B_Rc(drsp)
8499 GEN_DFP_T_B_Rc(drdpq)
8500 GEN_DFP_T_B_Rc(dcffix)
8501 GEN_DFP_T_B_Rc(dcffixq)
8502 GEN_DFP_T_B_Rc(dctfix)
8503 GEN_DFP_T_B_Rc(dctfixq)
8504 GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP)
8505 GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP)
8506 GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
8507 GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
8508 GEN_DFP_T_B_Rc(dxex)
8509 GEN_DFP_T_B_Rc(dxexq)
8510 GEN_DFP_T_A_B_Rc(diex)
8511 GEN_DFP_T_A_B_Rc(diexq)
8512 GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
8513 GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
8514 GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
8515 GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
8516
8517 /*** SPE extension ***/
8518 /* Register moves */
8519
8520 static inline void gen_evmra(DisasContext *ctx)
8521 {
8522
8523 if (unlikely(!ctx->spe_enabled)) {
8524 gen_exception(ctx, POWERPC_EXCP_SPEU);
8525 return;
8526 }
8527
8528 TCGv_i64 tmp = tcg_temp_new_i64();
8529
8530 /* tmp := rA_lo + rA_hi << 32 */
8531 tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8532
8533 /* spe_acc := tmp */
8534 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8535 tcg_temp_free_i64(tmp);
8536
8537 /* rD := rA */
8538 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8539 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8540 }
8541
8542 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
8543 {
8544 tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
8545 }
8546
8547 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
8548 {
8549 tcg_gen_extr_i64_tl(cpu_gpr[reg], cpu_gprh[reg], t);
8550 }
8551
8552 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
8553 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
8554 { \
8555 if (Rc(ctx->opcode)) \
8556 gen_##name1(ctx); \
8557 else \
8558 gen_##name0(ctx); \
8559 }
8560
8561 /* Handler for undefined SPE opcodes */
8562 static inline void gen_speundef(DisasContext *ctx)
8563 {
8564 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
8565 }
8566
8567 /* SPE logic */
8568 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
8569 static inline void gen_##name(DisasContext *ctx) \
8570 { \
8571 if (unlikely(!ctx->spe_enabled)) { \
8572 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8573 return; \
8574 } \
8575 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8576 cpu_gpr[rB(ctx->opcode)]); \
8577 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8578 cpu_gprh[rB(ctx->opcode)]); \
8579 }
8580
8581 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
8582 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
8583 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
8584 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
8585 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
8586 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
8587 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
8588 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
8589
8590 /* SPE logic immediate */
8591 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
8592 static inline void gen_##name(DisasContext *ctx) \
8593 { \
8594 TCGv_i32 t0; \
8595 if (unlikely(!ctx->spe_enabled)) { \
8596 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8597 return; \
8598 } \
8599 t0 = tcg_temp_new_i32(); \
8600 \
8601 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8602 tcg_opi(t0, t0, rB(ctx->opcode)); \
8603 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8604 \
8605 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8606 tcg_opi(t0, t0, rB(ctx->opcode)); \
8607 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8608 \
8609 tcg_temp_free_i32(t0); \
8610 }
8611 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
8612 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
8613 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
8614 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
8615
8616 /* SPE arithmetic */
8617 #define GEN_SPEOP_ARITH1(name, tcg_op) \
8618 static inline void gen_##name(DisasContext *ctx) \
8619 { \
8620 TCGv_i32 t0; \
8621 if (unlikely(!ctx->spe_enabled)) { \
8622 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8623 return; \
8624 } \
8625 t0 = tcg_temp_new_i32(); \
8626 \
8627 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8628 tcg_op(t0, t0); \
8629 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8630 \
8631 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8632 tcg_op(t0, t0); \
8633 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8634 \
8635 tcg_temp_free_i32(t0); \
8636 }
8637
8638 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
8639 {
8640 TCGLabel *l1 = gen_new_label();
8641 TCGLabel *l2 = gen_new_label();
8642
8643 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
8644 tcg_gen_neg_i32(ret, arg1);
8645 tcg_gen_br(l2);
8646 gen_set_label(l1);
8647 tcg_gen_mov_i32(ret, arg1);
8648 gen_set_label(l2);
8649 }
8650 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
8651 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
8652 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
8653 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
8654 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
8655 {
8656 tcg_gen_addi_i32(ret, arg1, 0x8000);
8657 tcg_gen_ext16u_i32(ret, ret);
8658 }
8659 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
8660 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
8661 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
8662
8663 #define GEN_SPEOP_ARITH2(name, tcg_op) \
8664 static inline void gen_##name(DisasContext *ctx) \
8665 { \
8666 TCGv_i32 t0, t1; \
8667 if (unlikely(!ctx->spe_enabled)) { \
8668 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8669 return; \
8670 } \
8671 t0 = tcg_temp_new_i32(); \
8672 t1 = tcg_temp_new_i32(); \
8673 \
8674 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8675 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8676 tcg_op(t0, t0, t1); \
8677 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8678 \
8679 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8680 tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \
8681 tcg_op(t0, t0, t1); \
8682 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8683 \
8684 tcg_temp_free_i32(t0); \
8685 tcg_temp_free_i32(t1); \
8686 }
8687
8688 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8689 {
8690 TCGLabel *l1 = gen_new_label();
8691 TCGLabel *l2 = gen_new_label();
8692 TCGv_i32 t0 = tcg_temp_local_new_i32();
8693
8694 /* No error here: 6 bits are used */
8695 tcg_gen_andi_i32(t0, arg2, 0x3F);
8696 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8697 tcg_gen_shr_i32(ret, arg1, t0);
8698 tcg_gen_br(l2);
8699 gen_set_label(l1);
8700 tcg_gen_movi_i32(ret, 0);
8701 gen_set_label(l2);
8702 tcg_temp_free_i32(t0);
8703 }
8704 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
8705 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8706 {
8707 TCGLabel *l1 = gen_new_label();
8708 TCGLabel *l2 = gen_new_label();
8709 TCGv_i32 t0 = tcg_temp_local_new_i32();
8710
8711 /* No error here: 6 bits are used */
8712 tcg_gen_andi_i32(t0, arg2, 0x3F);
8713 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8714 tcg_gen_sar_i32(ret, arg1, t0);
8715 tcg_gen_br(l2);
8716 gen_set_label(l1);
8717 tcg_gen_movi_i32(ret, 0);
8718 gen_set_label(l2);
8719 tcg_temp_free_i32(t0);
8720 }
8721 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
8722 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8723 {
8724 TCGLabel *l1 = gen_new_label();
8725 TCGLabel *l2 = gen_new_label();
8726 TCGv_i32 t0 = tcg_temp_local_new_i32();
8727
8728 /* No error here: 6 bits are used */
8729 tcg_gen_andi_i32(t0, arg2, 0x3F);
8730 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8731 tcg_gen_shl_i32(ret, arg1, t0);
8732 tcg_gen_br(l2);
8733 gen_set_label(l1);
8734 tcg_gen_movi_i32(ret, 0);
8735 gen_set_label(l2);
8736 tcg_temp_free_i32(t0);
8737 }
8738 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
8739 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8740 {
8741 TCGv_i32 t0 = tcg_temp_new_i32();
8742 tcg_gen_andi_i32(t0, arg2, 0x1F);
8743 tcg_gen_rotl_i32(ret, arg1, t0);
8744 tcg_temp_free_i32(t0);
8745 }
8746 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
8747 static inline void gen_evmergehi(DisasContext *ctx)
8748 {
8749 if (unlikely(!ctx->spe_enabled)) {
8750 gen_exception(ctx, POWERPC_EXCP_SPEU);
8751 return;
8752 }
8753 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8754 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8755 }
8756 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
8757 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8758 {
8759 tcg_gen_sub_i32(ret, arg2, arg1);
8760 }
8761 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
8762
8763 /* SPE arithmetic immediate */
8764 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8765 static inline void gen_##name(DisasContext *ctx) \
8766 { \
8767 TCGv_i32 t0; \
8768 if (unlikely(!ctx->spe_enabled)) { \
8769 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8770 return; \
8771 } \
8772 t0 = tcg_temp_new_i32(); \
8773 \
8774 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8775 tcg_op(t0, t0, rA(ctx->opcode)); \
8776 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8777 \
8778 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \
8779 tcg_op(t0, t0, rA(ctx->opcode)); \
8780 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8781 \
8782 tcg_temp_free_i32(t0); \
8783 }
8784 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
8785 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
8786
8787 /* SPE comparison */
8788 #define GEN_SPEOP_COMP(name, tcg_cond) \
8789 static inline void gen_##name(DisasContext *ctx) \
8790 { \
8791 if (unlikely(!ctx->spe_enabled)) { \
8792 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8793 return; \
8794 } \
8795 TCGLabel *l1 = gen_new_label(); \
8796 TCGLabel *l2 = gen_new_label(); \
8797 TCGLabel *l3 = gen_new_label(); \
8798 TCGLabel *l4 = gen_new_label(); \
8799 \
8800 tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
8801 tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8802 tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
8803 tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \
8804 \
8805 tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
8806 cpu_gpr[rB(ctx->opcode)], l1); \
8807 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
8808 tcg_gen_br(l2); \
8809 gen_set_label(l1); \
8810 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8811 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8812 gen_set_label(l2); \
8813 tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
8814 cpu_gprh[rB(ctx->opcode)], l3); \
8815 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8816 ~(CRF_CH | CRF_CH_AND_CL)); \
8817 tcg_gen_br(l4); \
8818 gen_set_label(l3); \
8819 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8820 CRF_CH | CRF_CH_OR_CL); \
8821 gen_set_label(l4); \
8822 }
8823 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
8824 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
8825 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
8826 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
8827 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
8828
8829 /* SPE misc */
8830 static inline void gen_brinc(DisasContext *ctx)
8831 {
8832 /* Note: brinc is usable even if SPE is disabled */
8833 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
8834 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8835 }
8836 static inline void gen_evmergelo(DisasContext *ctx)
8837 {
8838 if (unlikely(!ctx->spe_enabled)) {
8839 gen_exception(ctx, POWERPC_EXCP_SPEU);
8840 return;
8841 }
8842 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8843 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8844 }
8845 static inline void gen_evmergehilo(DisasContext *ctx)
8846 {
8847 if (unlikely(!ctx->spe_enabled)) {
8848 gen_exception(ctx, POWERPC_EXCP_SPEU);
8849 return;
8850 }
8851 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8852 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8853 }
8854 static inline void gen_evmergelohi(DisasContext *ctx)
8855 {
8856 if (unlikely(!ctx->spe_enabled)) {
8857 gen_exception(ctx, POWERPC_EXCP_SPEU);
8858 return;
8859 }
8860 if (rD(ctx->opcode) == rA(ctx->opcode)) {
8861 TCGv tmp = tcg_temp_new();
8862 tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]);
8863 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8864 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp);
8865 tcg_temp_free(tmp);
8866 } else {
8867 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8868 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8869 }
8870 }
8871 static inline void gen_evsplati(DisasContext *ctx)
8872 {
8873 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
8874
8875 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8876 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8877 }
8878 static inline void gen_evsplatfi(DisasContext *ctx)
8879 {
8880 uint64_t imm = rA(ctx->opcode) << 27;
8881
8882 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8883 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8884 }
8885
8886 static inline void gen_evsel(DisasContext *ctx)
8887 {
8888 TCGLabel *l1 = gen_new_label();
8889 TCGLabel *l2 = gen_new_label();
8890 TCGLabel *l3 = gen_new_label();
8891 TCGLabel *l4 = gen_new_label();
8892 TCGv_i32 t0 = tcg_temp_local_new_i32();
8893
8894 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
8895 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
8896 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8897 tcg_gen_br(l2);
8898 gen_set_label(l1);
8899 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8900 gen_set_label(l2);
8901 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
8902 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
8903 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8904 tcg_gen_br(l4);
8905 gen_set_label(l3);
8906 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8907 gen_set_label(l4);
8908 tcg_temp_free_i32(t0);
8909 }
8910
8911 static void gen_evsel0(DisasContext *ctx)
8912 {
8913 gen_evsel(ctx);
8914 }
8915
8916 static void gen_evsel1(DisasContext *ctx)
8917 {
8918 gen_evsel(ctx);
8919 }
8920
8921 static void gen_evsel2(DisasContext *ctx)
8922 {
8923 gen_evsel(ctx);
8924 }
8925
8926 static void gen_evsel3(DisasContext *ctx)
8927 {
8928 gen_evsel(ctx);
8929 }
8930
8931 /* Multiply */
8932
8933 static inline void gen_evmwumi(DisasContext *ctx)
8934 {
8935 TCGv_i64 t0, t1;
8936
8937 if (unlikely(!ctx->spe_enabled)) {
8938 gen_exception(ctx, POWERPC_EXCP_SPEU);
8939 return;
8940 }
8941
8942 t0 = tcg_temp_new_i64();
8943 t1 = tcg_temp_new_i64();
8944
8945 /* t0 := rA; t1 := rB */
8946 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8947 tcg_gen_ext32u_i64(t0, t0);
8948 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8949 tcg_gen_ext32u_i64(t1, t1);
8950
8951 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8952
8953 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8954
8955 tcg_temp_free_i64(t0);
8956 tcg_temp_free_i64(t1);
8957 }
8958
8959 static inline void gen_evmwumia(DisasContext *ctx)
8960 {
8961 TCGv_i64 tmp;
8962
8963 if (unlikely(!ctx->spe_enabled)) {
8964 gen_exception(ctx, POWERPC_EXCP_SPEU);
8965 return;
8966 }
8967
8968 gen_evmwumi(ctx); /* rD := rA * rB */
8969
8970 tmp = tcg_temp_new_i64();
8971
8972 /* acc := rD */
8973 gen_load_gpr64(tmp, rD(ctx->opcode));
8974 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8975 tcg_temp_free_i64(tmp);
8976 }
8977
8978 static inline void gen_evmwumiaa(DisasContext *ctx)
8979 {
8980 TCGv_i64 acc;
8981 TCGv_i64 tmp;
8982
8983 if (unlikely(!ctx->spe_enabled)) {
8984 gen_exception(ctx, POWERPC_EXCP_SPEU);
8985 return;
8986 }
8987
8988 gen_evmwumi(ctx); /* rD := rA * rB */
8989
8990 acc = tcg_temp_new_i64();
8991 tmp = tcg_temp_new_i64();
8992
8993 /* tmp := rD */
8994 gen_load_gpr64(tmp, rD(ctx->opcode));
8995
8996 /* Load acc */
8997 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8998
8999 /* acc := tmp + acc */
9000 tcg_gen_add_i64(acc, acc, tmp);
9001
9002 /* Store acc */
9003 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9004
9005 /* rD := acc */
9006 gen_store_gpr64(rD(ctx->opcode), acc);
9007
9008 tcg_temp_free_i64(acc);
9009 tcg_temp_free_i64(tmp);
9010 }
9011
9012 static inline void gen_evmwsmi(DisasContext *ctx)
9013 {
9014 TCGv_i64 t0, t1;
9015
9016 if (unlikely(!ctx->spe_enabled)) {
9017 gen_exception(ctx, POWERPC_EXCP_SPEU);
9018 return;
9019 }
9020
9021 t0 = tcg_temp_new_i64();
9022 t1 = tcg_temp_new_i64();
9023
9024 /* t0 := rA; t1 := rB */
9025 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
9026 tcg_gen_ext32s_i64(t0, t0);
9027 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
9028 tcg_gen_ext32s_i64(t1, t1);
9029
9030 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
9031
9032 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
9033
9034 tcg_temp_free_i64(t0);
9035 tcg_temp_free_i64(t1);
9036 }
9037
9038 static inline void gen_evmwsmia(DisasContext *ctx)
9039 {
9040 TCGv_i64 tmp;
9041
9042 gen_evmwsmi(ctx); /* rD := rA * rB */
9043
9044 tmp = tcg_temp_new_i64();
9045
9046 /* acc := rD */
9047 gen_load_gpr64(tmp, rD(ctx->opcode));
9048 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
9049
9050 tcg_temp_free_i64(tmp);
9051 }
9052
9053 static inline void gen_evmwsmiaa(DisasContext *ctx)
9054 {
9055 TCGv_i64 acc = tcg_temp_new_i64();
9056 TCGv_i64 tmp = tcg_temp_new_i64();
9057
9058 gen_evmwsmi(ctx); /* rD := rA * rB */
9059
9060 acc = tcg_temp_new_i64();
9061 tmp = tcg_temp_new_i64();
9062
9063 /* tmp := rD */
9064 gen_load_gpr64(tmp, rD(ctx->opcode));
9065
9066 /* Load acc */
9067 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9068
9069 /* acc := tmp + acc */
9070 tcg_gen_add_i64(acc, acc, tmp);
9071
9072 /* Store acc */
9073 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9074
9075 /* rD := acc */
9076 gen_store_gpr64(rD(ctx->opcode), acc);
9077
9078 tcg_temp_free_i64(acc);
9079 tcg_temp_free_i64(tmp);
9080 }
9081
9082 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9083 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9084 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9085 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9086 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9087 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9088 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9089 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
9090 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
9091 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9092 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9093 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9094 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9095 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9096 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9097 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9098 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9099 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9100 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9101 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
9102 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9103 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9104 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
9105 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
9106 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9107 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9108 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9109 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9110 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
9111
9112 /* SPE load and stores */
9113 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
9114 {
9115 target_ulong uimm = rB(ctx->opcode);
9116
9117 if (rA(ctx->opcode) == 0) {
9118 tcg_gen_movi_tl(EA, uimm << sh);
9119 } else {
9120 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
9121 if (NARROW_MODE(ctx)) {
9122 tcg_gen_ext32u_tl(EA, EA);
9123 }
9124 }
9125 }
9126
9127 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
9128 {
9129 TCGv_i64 t0 = tcg_temp_new_i64();
9130 gen_qemu_ld64(ctx, t0, addr);
9131 gen_store_gpr64(rD(ctx->opcode), t0);
9132 tcg_temp_free_i64(t0);
9133 }
9134
9135 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
9136 {
9137 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9138 gen_addr_add(ctx, addr, addr, 4);
9139 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9140 }
9141
9142 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
9143 {
9144 TCGv t0 = tcg_temp_new();
9145 gen_qemu_ld16u(ctx, t0, addr);
9146 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9147 gen_addr_add(ctx, addr, addr, 2);
9148 gen_qemu_ld16u(ctx, t0, addr);
9149 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9150 gen_addr_add(ctx, addr, addr, 2);
9151 gen_qemu_ld16u(ctx, t0, addr);
9152 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9153 gen_addr_add(ctx, addr, addr, 2);
9154 gen_qemu_ld16u(ctx, t0, addr);
9155 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9156 tcg_temp_free(t0);
9157 }
9158
9159 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
9160 {
9161 TCGv t0 = tcg_temp_new();
9162 gen_qemu_ld16u(ctx, t0, addr);
9163 tcg_gen_shli_tl(t0, t0, 16);
9164 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9165 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9166 tcg_temp_free(t0);
9167 }
9168
9169 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
9170 {
9171 TCGv t0 = tcg_temp_new();
9172 gen_qemu_ld16u(ctx, t0, addr);
9173 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9174 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9175 tcg_temp_free(t0);
9176 }
9177
9178 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
9179 {
9180 TCGv t0 = tcg_temp_new();
9181 gen_qemu_ld16s(ctx, t0, addr);
9182 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9183 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9184 tcg_temp_free(t0);
9185 }
9186
9187 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
9188 {
9189 TCGv t0 = tcg_temp_new();
9190 gen_qemu_ld16u(ctx, t0, addr);
9191 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9192 gen_addr_add(ctx, addr, addr, 2);
9193 gen_qemu_ld16u(ctx, t0, addr);
9194 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9195 tcg_temp_free(t0);
9196 }
9197
9198 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
9199 {
9200 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9201 gen_addr_add(ctx, addr, addr, 2);
9202 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9203 }
9204
9205 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
9206 {
9207 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9208 gen_addr_add(ctx, addr, addr, 2);
9209 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9210 }
9211
9212 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
9213 {
9214 TCGv t0 = tcg_temp_new();
9215 gen_qemu_ld32u(ctx, t0, addr);
9216 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9217 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9218 tcg_temp_free(t0);
9219 }
9220
9221 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
9222 {
9223 TCGv t0 = tcg_temp_new();
9224 gen_qemu_ld16u(ctx, t0, addr);
9225 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9226 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9227 gen_addr_add(ctx, addr, addr, 2);
9228 gen_qemu_ld16u(ctx, t0, addr);
9229 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9230 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9231 tcg_temp_free(t0);
9232 }
9233
9234 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
9235 {
9236 TCGv_i64 t0 = tcg_temp_new_i64();
9237 gen_load_gpr64(t0, rS(ctx->opcode));
9238 gen_qemu_st64(ctx, t0, addr);
9239 tcg_temp_free_i64(t0);
9240 }
9241
9242 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
9243 {
9244 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9245 gen_addr_add(ctx, addr, addr, 4);
9246 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9247 }
9248
9249 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
9250 {
9251 TCGv t0 = tcg_temp_new();
9252 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9253 gen_qemu_st16(ctx, t0, addr);
9254 gen_addr_add(ctx, addr, addr, 2);
9255 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9256 gen_addr_add(ctx, addr, addr, 2);
9257 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9258 gen_qemu_st16(ctx, t0, addr);
9259 tcg_temp_free(t0);
9260 gen_addr_add(ctx, addr, addr, 2);
9261 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9262 }
9263
9264 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
9265 {
9266 TCGv t0 = tcg_temp_new();
9267 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9268 gen_qemu_st16(ctx, t0, addr);
9269 gen_addr_add(ctx, addr, addr, 2);
9270 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9271 gen_qemu_st16(ctx, t0, addr);
9272 tcg_temp_free(t0);
9273 }
9274
9275 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
9276 {
9277 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9278 gen_addr_add(ctx, addr, addr, 2);
9279 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9280 }
9281
9282 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
9283 {
9284 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9285 }
9286
9287 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
9288 {
9289 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9290 }
9291
9292 #define GEN_SPEOP_LDST(name, opc2, sh) \
9293 static void glue(gen_, name)(DisasContext *ctx) \
9294 { \
9295 TCGv t0; \
9296 if (unlikely(!ctx->spe_enabled)) { \
9297 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9298 return; \
9299 } \
9300 gen_set_access_type(ctx, ACCESS_INT); \
9301 t0 = tcg_temp_new(); \
9302 if (Rc(ctx->opcode)) { \
9303 gen_addr_spe_imm_index(ctx, t0, sh); \
9304 } else { \
9305 gen_addr_reg_index(ctx, t0); \
9306 } \
9307 gen_op_##name(ctx, t0); \
9308 tcg_temp_free(t0); \
9309 }
9310
9311 GEN_SPEOP_LDST(evldd, 0x00, 3);
9312 GEN_SPEOP_LDST(evldw, 0x01, 3);
9313 GEN_SPEOP_LDST(evldh, 0x02, 3);
9314 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
9315 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
9316 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
9317 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
9318 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
9319 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
9320 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
9321 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
9322
9323 GEN_SPEOP_LDST(evstdd, 0x10, 3);
9324 GEN_SPEOP_LDST(evstdw, 0x11, 3);
9325 GEN_SPEOP_LDST(evstdh, 0x12, 3);
9326 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
9327 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
9328 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
9329 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
9330
9331 /* Multiply and add - TODO */
9332 #if 0
9333 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
9334 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9335 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9336 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9337 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9338 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9339 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9340 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9341 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9342 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9343 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9344 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9345
9346 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9347 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9348 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9349 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9350 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9351 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9352 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9353 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9354 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9355 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9356 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9357 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9358
9359 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9360 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9361 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9362 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9363 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
9364
9365 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9366 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9367 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9368 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9369 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9370 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9371 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9372 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9373 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9374 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9375 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9376 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9377
9378 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9379 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9380 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9381 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9382
9383 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9384 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9385 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9386 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9387 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9388 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9389 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9390 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9391 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9392 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9393 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9394 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9395
9396 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9397 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9398 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9399 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9400 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9401 #endif
9402
9403 /*** SPE floating-point extension ***/
9404 #define GEN_SPEFPUOP_CONV_32_32(name) \
9405 static inline void gen_##name(DisasContext *ctx) \
9406 { \
9407 TCGv_i32 t0 = tcg_temp_new_i32(); \
9408 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9409 gen_helper_##name(t0, cpu_env, t0); \
9410 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9411 tcg_temp_free_i32(t0); \
9412 }
9413 #define GEN_SPEFPUOP_CONV_32_64(name) \
9414 static inline void gen_##name(DisasContext *ctx) \
9415 { \
9416 TCGv_i64 t0 = tcg_temp_new_i64(); \
9417 TCGv_i32 t1 = tcg_temp_new_i32(); \
9418 gen_load_gpr64(t0, rB(ctx->opcode)); \
9419 gen_helper_##name(t1, cpu_env, t0); \
9420 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
9421 tcg_temp_free_i64(t0); \
9422 tcg_temp_free_i32(t1); \
9423 }
9424 #define GEN_SPEFPUOP_CONV_64_32(name) \
9425 static inline void gen_##name(DisasContext *ctx) \
9426 { \
9427 TCGv_i64 t0 = tcg_temp_new_i64(); \
9428 TCGv_i32 t1 = tcg_temp_new_i32(); \
9429 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9430 gen_helper_##name(t0, cpu_env, t1); \
9431 gen_store_gpr64(rD(ctx->opcode), t0); \
9432 tcg_temp_free_i64(t0); \
9433 tcg_temp_free_i32(t1); \
9434 }
9435 #define GEN_SPEFPUOP_CONV_64_64(name) \
9436 static inline void gen_##name(DisasContext *ctx) \
9437 { \
9438 TCGv_i64 t0 = tcg_temp_new_i64(); \
9439 gen_load_gpr64(t0, rB(ctx->opcode)); \
9440 gen_helper_##name(t0, cpu_env, t0); \
9441 gen_store_gpr64(rD(ctx->opcode), t0); \
9442 tcg_temp_free_i64(t0); \
9443 }
9444 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9445 static inline void gen_##name(DisasContext *ctx) \
9446 { \
9447 TCGv_i32 t0, t1; \
9448 if (unlikely(!ctx->spe_enabled)) { \
9449 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9450 return; \
9451 } \
9452 t0 = tcg_temp_new_i32(); \
9453 t1 = tcg_temp_new_i32(); \
9454 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9455 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9456 gen_helper_##name(t0, cpu_env, t0, t1); \
9457 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9458 \
9459 tcg_temp_free_i32(t0); \
9460 tcg_temp_free_i32(t1); \
9461 }
9462 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9463 static inline void gen_##name(DisasContext *ctx) \
9464 { \
9465 TCGv_i64 t0, t1; \
9466 if (unlikely(!ctx->spe_enabled)) { \
9467 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9468 return; \
9469 } \
9470 t0 = tcg_temp_new_i64(); \
9471 t1 = tcg_temp_new_i64(); \
9472 gen_load_gpr64(t0, rA(ctx->opcode)); \
9473 gen_load_gpr64(t1, rB(ctx->opcode)); \
9474 gen_helper_##name(t0, cpu_env, t0, t1); \
9475 gen_store_gpr64(rD(ctx->opcode), t0); \
9476 tcg_temp_free_i64(t0); \
9477 tcg_temp_free_i64(t1); \
9478 }
9479 #define GEN_SPEFPUOP_COMP_32(name) \
9480 static inline void gen_##name(DisasContext *ctx) \
9481 { \
9482 TCGv_i32 t0, t1; \
9483 if (unlikely(!ctx->spe_enabled)) { \
9484 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9485 return; \
9486 } \
9487 t0 = tcg_temp_new_i32(); \
9488 t1 = tcg_temp_new_i32(); \
9489 \
9490 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9491 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9492 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9493 \
9494 tcg_temp_free_i32(t0); \
9495 tcg_temp_free_i32(t1); \
9496 }
9497 #define GEN_SPEFPUOP_COMP_64(name) \
9498 static inline void gen_##name(DisasContext *ctx) \
9499 { \
9500 TCGv_i64 t0, t1; \
9501 if (unlikely(!ctx->spe_enabled)) { \
9502 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9503 return; \
9504 } \
9505 t0 = tcg_temp_new_i64(); \
9506 t1 = tcg_temp_new_i64(); \
9507 gen_load_gpr64(t0, rA(ctx->opcode)); \
9508 gen_load_gpr64(t1, rB(ctx->opcode)); \
9509 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9510 tcg_temp_free_i64(t0); \
9511 tcg_temp_free_i64(t1); \
9512 }
9513
9514 /* Single precision floating-point vectors operations */
9515 /* Arithmetic */
9516 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
9517 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
9518 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
9519 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
9520 static inline void gen_evfsabs(DisasContext *ctx)
9521 {
9522 if (unlikely(!ctx->spe_enabled)) {
9523 gen_exception(ctx, POWERPC_EXCP_SPEU);
9524 return;
9525 }
9526 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9527 ~0x80000000);
9528 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9529 ~0x80000000);
9530 }
9531 static inline void gen_evfsnabs(DisasContext *ctx)
9532 {
9533 if (unlikely(!ctx->spe_enabled)) {
9534 gen_exception(ctx, POWERPC_EXCP_SPEU);
9535 return;
9536 }
9537 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9538 0x80000000);
9539 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9540 0x80000000);
9541 }
9542 static inline void gen_evfsneg(DisasContext *ctx)
9543 {
9544 if (unlikely(!ctx->spe_enabled)) {
9545 gen_exception(ctx, POWERPC_EXCP_SPEU);
9546 return;
9547 }
9548 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9549 0x80000000);
9550 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9551 0x80000000);
9552 }
9553
9554 /* Conversion */
9555 GEN_SPEFPUOP_CONV_64_64(evfscfui);
9556 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
9557 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
9558 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
9559 GEN_SPEFPUOP_CONV_64_64(evfsctui);
9560 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
9561 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
9562 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
9563 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
9564 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
9565
9566 /* Comparison */
9567 GEN_SPEFPUOP_COMP_64(evfscmpgt);
9568 GEN_SPEFPUOP_COMP_64(evfscmplt);
9569 GEN_SPEFPUOP_COMP_64(evfscmpeq);
9570 GEN_SPEFPUOP_COMP_64(evfststgt);
9571 GEN_SPEFPUOP_COMP_64(evfststlt);
9572 GEN_SPEFPUOP_COMP_64(evfststeq);
9573
9574 /* Opcodes definitions */
9575 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9576 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9577 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9578 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9579 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9580 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9581 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9582 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9583 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9584 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9585 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9586 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9587 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9588 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9589
9590 /* Single precision floating-point operations */
9591 /* Arithmetic */
9592 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
9593 GEN_SPEFPUOP_ARITH2_32_32(efssub);
9594 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
9595 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
9596 static inline void gen_efsabs(DisasContext *ctx)
9597 {
9598 if (unlikely(!ctx->spe_enabled)) {
9599 gen_exception(ctx, POWERPC_EXCP_SPEU);
9600 return;
9601 }
9602 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
9603 }
9604 static inline void gen_efsnabs(DisasContext *ctx)
9605 {
9606 if (unlikely(!ctx->spe_enabled)) {
9607 gen_exception(ctx, POWERPC_EXCP_SPEU);
9608 return;
9609 }
9610 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9611 }
9612 static inline void gen_efsneg(DisasContext *ctx)
9613 {
9614 if (unlikely(!ctx->spe_enabled)) {
9615 gen_exception(ctx, POWERPC_EXCP_SPEU);
9616 return;
9617 }
9618 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9619 }
9620
9621 /* Conversion */
9622 GEN_SPEFPUOP_CONV_32_32(efscfui);
9623 GEN_SPEFPUOP_CONV_32_32(efscfsi);
9624 GEN_SPEFPUOP_CONV_32_32(efscfuf);
9625 GEN_SPEFPUOP_CONV_32_32(efscfsf);
9626 GEN_SPEFPUOP_CONV_32_32(efsctui);
9627 GEN_SPEFPUOP_CONV_32_32(efsctsi);
9628 GEN_SPEFPUOP_CONV_32_32(efsctuf);
9629 GEN_SPEFPUOP_CONV_32_32(efsctsf);
9630 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
9631 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
9632 GEN_SPEFPUOP_CONV_32_64(efscfd);
9633
9634 /* Comparison */
9635 GEN_SPEFPUOP_COMP_32(efscmpgt);
9636 GEN_SPEFPUOP_COMP_32(efscmplt);
9637 GEN_SPEFPUOP_COMP_32(efscmpeq);
9638 GEN_SPEFPUOP_COMP_32(efststgt);
9639 GEN_SPEFPUOP_COMP_32(efststlt);
9640 GEN_SPEFPUOP_COMP_32(efststeq);
9641
9642 /* Opcodes definitions */
9643 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9644 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9645 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9646 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9647 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9648 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
9649 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9650 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9651 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9652 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9653 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9654 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9655 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9656 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9657
9658 /* Double precision floating-point operations */
9659 /* Arithmetic */
9660 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
9661 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
9662 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
9663 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
9664 static inline void gen_efdabs(DisasContext *ctx)
9665 {
9666 if (unlikely(!ctx->spe_enabled)) {
9667 gen_exception(ctx, POWERPC_EXCP_SPEU);
9668 return;
9669 }
9670 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9671 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9672 ~0x80000000);
9673 }
9674 static inline void gen_efdnabs(DisasContext *ctx)
9675 {
9676 if (unlikely(!ctx->spe_enabled)) {
9677 gen_exception(ctx, POWERPC_EXCP_SPEU);
9678 return;
9679 }
9680 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9681 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9682 0x80000000);
9683 }
9684 static inline void gen_efdneg(DisasContext *ctx)
9685 {
9686 if (unlikely(!ctx->spe_enabled)) {
9687 gen_exception(ctx, POWERPC_EXCP_SPEU);
9688 return;
9689 }
9690 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9691 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9692 0x80000000);
9693 }
9694
9695 /* Conversion */
9696 GEN_SPEFPUOP_CONV_64_32(efdcfui);
9697 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
9698 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
9699 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
9700 GEN_SPEFPUOP_CONV_32_64(efdctui);
9701 GEN_SPEFPUOP_CONV_32_64(efdctsi);
9702 GEN_SPEFPUOP_CONV_32_64(efdctuf);
9703 GEN_SPEFPUOP_CONV_32_64(efdctsf);
9704 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
9705 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
9706 GEN_SPEFPUOP_CONV_64_32(efdcfs);
9707 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
9708 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
9709 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
9710 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
9711
9712 /* Comparison */
9713 GEN_SPEFPUOP_COMP_64(efdcmpgt);
9714 GEN_SPEFPUOP_COMP_64(efdcmplt);
9715 GEN_SPEFPUOP_COMP_64(efdcmpeq);
9716 GEN_SPEFPUOP_COMP_64(efdtstgt);
9717 GEN_SPEFPUOP_COMP_64(efdtstlt);
9718 GEN_SPEFPUOP_COMP_64(efdtsteq);
9719
9720 /* Opcodes definitions */
9721 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9722 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9723 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
9724 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9725 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9726 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9727 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9728 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
9729 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9730 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9731 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9732 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9733 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9734 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9735 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9736 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9737
9738 static void gen_tbegin(DisasContext *ctx)
9739 {
9740 if (unlikely(!ctx->tm_enabled)) {
9741 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9742 return;
9743 }
9744 gen_helper_tbegin(cpu_env);
9745 }
9746
9747 #define GEN_TM_NOOP(name) \
9748 static inline void gen_##name(DisasContext *ctx) \
9749 { \
9750 if (unlikely(!ctx->tm_enabled)) { \
9751 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9752 return; \
9753 } \
9754 /* Because tbegin always fails in QEMU, these user \
9755 * space instructions all have a simple implementation: \
9756 * \
9757 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9758 * = 0b0 || 0b00 || 0b0 \
9759 */ \
9760 tcg_gen_movi_i32(cpu_crf[0], 0); \
9761 }
9762
9763 GEN_TM_NOOP(tend);
9764 GEN_TM_NOOP(tabort);
9765 GEN_TM_NOOP(tabortwc);
9766 GEN_TM_NOOP(tabortwci);
9767 GEN_TM_NOOP(tabortdc);
9768 GEN_TM_NOOP(tabortdci);
9769 GEN_TM_NOOP(tsr);
9770
9771 static void gen_tcheck(DisasContext *ctx)
9772 {
9773 if (unlikely(!ctx->tm_enabled)) {
9774 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9775 return;
9776 }
9777 /* Because tbegin always fails, the tcheck implementation
9778 * is simple:
9779 *
9780 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
9781 * = 0b1 || 0b00 || 0b0
9782 */
9783 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
9784 }
9785
9786 #if defined(CONFIG_USER_ONLY)
9787 #define GEN_TM_PRIV_NOOP(name) \
9788 static inline void gen_##name(DisasContext *ctx) \
9789 { \
9790 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9791 }
9792
9793 #else
9794
9795 #define GEN_TM_PRIV_NOOP(name) \
9796 static inline void gen_##name(DisasContext *ctx) \
9797 { \
9798 if (unlikely(ctx->pr)) { \
9799 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9800 return; \
9801 } \
9802 if (unlikely(!ctx->tm_enabled)) { \
9803 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9804 return; \
9805 } \
9806 /* Because tbegin always fails, the implementation is \
9807 * simple: \
9808 * \
9809 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9810 * = 0b0 || 0b00 | 0b0 \
9811 */ \
9812 tcg_gen_movi_i32(cpu_crf[0], 0); \
9813 }
9814
9815 #endif
9816
9817 GEN_TM_PRIV_NOOP(treclaim);
9818 GEN_TM_PRIV_NOOP(trechkpt);
9819
9820 static opcode_t opcodes[] = {
9821 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
9822 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
9823 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9824 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
9825 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9826 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
9827 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
9828 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9829 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9830 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9831 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9832 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
9833 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
9834 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
9835 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
9836 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9837 #if defined(TARGET_PPC64)
9838 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
9839 #endif
9840 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
9841 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
9842 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9843 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9844 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9845 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
9846 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
9847 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
9848 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9849 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9850 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9851 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9852 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
9853 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
9854 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
9855 #if defined(TARGET_PPC64)
9856 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
9857 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
9858 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
9859 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
9860 #endif
9861 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9862 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9863 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9864 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
9865 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
9866 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
9867 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
9868 #if defined(TARGET_PPC64)
9869 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
9870 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
9871 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
9872 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
9873 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
9874 #endif
9875 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
9876 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9877 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9878 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
9879 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
9880 GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
9881 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
9882 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
9883 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
9884 GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
9885 GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
9886 GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
9887 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
9888 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
9889 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
9890 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
9891 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
9892 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
9893 #if defined(TARGET_PPC64)
9894 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
9895 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
9896 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
9897 #endif
9898 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9899 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9900 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
9901 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
9902 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
9903 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
9904 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
9905 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
9906 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9907 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9908 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
9909 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9910 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9911 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
9912 #if defined(TARGET_PPC64)
9913 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
9914 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
9915 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
9916 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
9917 #endif
9918 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
9919 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
9920 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9921 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9922 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
9923 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
9924 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
9925 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
9926 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
9927 #if defined(TARGET_PPC64)
9928 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
9929 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
9930 #endif
9931 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
9932 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
9933 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9934 #if defined(TARGET_PPC64)
9935 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
9936 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
9937 #endif
9938 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
9939 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
9940 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
9941 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
9942 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
9943 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
9944 #if defined(TARGET_PPC64)
9945 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
9946 #endif
9947 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
9948 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
9949 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
9950 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
9951 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
9952 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
9953 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
9954 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
9955 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
9956 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
9957 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
9958 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
9959 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
9960 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
9961 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
9962 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
9963 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
9964 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
9965 #if defined(TARGET_PPC64)
9966 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
9967 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
9968 PPC_SEGMENT_64B),
9969 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
9970 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
9971 PPC_SEGMENT_64B),
9972 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
9973 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
9974 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
9975 #endif
9976 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
9977 /* XXX Those instructions will need to be handled differently for
9978 * different ISA versions */
9979 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
9980 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
9981 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
9982 #if defined(TARGET_PPC64)
9983 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
9984 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
9985 #endif
9986 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
9987 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
9988 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
9989 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
9990 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
9991 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
9992 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
9993 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
9994 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
9995 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
9996 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
9997 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9998 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
9999 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
10000 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
10001 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
10002 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
10003 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
10004 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
10005 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
10006 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
10007 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
10008 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
10009 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
10010 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
10011 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
10012 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
10013 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
10014 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
10015 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
10016 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
10017 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
10018 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
10019 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
10020 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
10021 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
10022 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
10023 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
10024 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
10025 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
10026 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
10027 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
10028 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
10029 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
10030 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
10031 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
10032 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
10033 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
10034 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
10035 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10036 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10037 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
10038 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
10039 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10040 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10041 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
10042 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
10043 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
10044 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
10045 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
10046 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
10047 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
10048 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
10049 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
10050 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
10051 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
10052 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
10053 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
10054 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
10055 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
10056 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
10057 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
10058 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
10059 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
10060 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
10061 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
10062 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
10063 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
10064 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
10065 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
10066 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
10067 PPC_NONE, PPC2_BOOKE206),
10068 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
10069 PPC_NONE, PPC2_BOOKE206),
10070 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
10071 PPC_NONE, PPC2_BOOKE206),
10072 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
10073 PPC_NONE, PPC2_BOOKE206),
10074 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
10075 PPC_NONE, PPC2_BOOKE206),
10076 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
10077 PPC_NONE, PPC2_PRCNTL),
10078 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
10079 PPC_NONE, PPC2_PRCNTL),
10080 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
10081 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
10082 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
10083 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
10084 PPC_BOOKE, PPC2_BOOKE206),
10085 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
10086 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
10087 PPC_BOOKE, PPC2_BOOKE206),
10088 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
10089 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
10090 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
10091 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
10092 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
10093 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
10094 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
10095 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
10096 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
10097
10098 #undef GEN_INT_ARITH_ADD
10099 #undef GEN_INT_ARITH_ADD_CONST
10100 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
10101 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
10102 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
10103 add_ca, compute_ca, compute_ov) \
10104 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
10105 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
10106 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
10107 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
10108 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
10109 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
10110 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
10111 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
10112 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
10113 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
10114 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
10115
10116 #undef GEN_INT_ARITH_DIVW
10117 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
10118 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
10119 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
10120 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
10121 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
10122 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
10123 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10124 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10125 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10126 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10127
10128 #if defined(TARGET_PPC64)
10129 #undef GEN_INT_ARITH_DIVD
10130 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
10131 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10132 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
10133 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
10134 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
10135 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
10136
10137 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10138 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10139 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10140 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10141
10142 #undef GEN_INT_ARITH_MUL_HELPER
10143 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
10144 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10145 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
10146 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
10147 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
10148 #endif
10149
10150 #undef GEN_INT_ARITH_SUBF
10151 #undef GEN_INT_ARITH_SUBF_CONST
10152 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
10153 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
10154 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
10155 add_ca, compute_ca, compute_ov) \
10156 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
10157 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
10158 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
10159 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
10160 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
10161 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
10162 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
10163 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
10164 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
10165 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
10166 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
10167
10168 #undef GEN_LOGICAL1
10169 #undef GEN_LOGICAL2
10170 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
10171 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
10172 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
10173 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
10174 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
10175 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
10176 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
10177 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
10178 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
10179 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
10180 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
10181 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
10182 #if defined(TARGET_PPC64)
10183 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
10184 #endif
10185
10186 #if defined(TARGET_PPC64)
10187 #undef GEN_PPC64_R2
10188 #undef GEN_PPC64_R4
10189 #define GEN_PPC64_R2(name, opc1, opc2) \
10190 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10191 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10192 PPC_64B)
10193 #define GEN_PPC64_R4(name, opc1, opc2) \
10194 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10195 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
10196 PPC_64B), \
10197 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10198 PPC_64B), \
10199 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
10200 PPC_64B)
10201 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
10202 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
10203 GEN_PPC64_R4(rldic, 0x1E, 0x04),
10204 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
10205 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
10206 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
10207 #endif
10208
10209 #undef _GEN_FLOAT_ACB
10210 #undef GEN_FLOAT_ACB
10211 #undef _GEN_FLOAT_AB
10212 #undef GEN_FLOAT_AB
10213 #undef _GEN_FLOAT_AC
10214 #undef GEN_FLOAT_AC
10215 #undef GEN_FLOAT_B
10216 #undef GEN_FLOAT_BS
10217 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
10218 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
10219 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
10220 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
10221 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
10222 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10223 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10224 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
10225 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10226 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10227 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10228 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10229 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
10230 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10231 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10232 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
10233 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
10234 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
10235 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
10236
10237 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
10238 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
10239 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
10240 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
10241 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
10242 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
10243 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
10244 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
10245 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
10246 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
10247 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
10248 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
10249 GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10250 GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10251 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
10252 GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10253 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
10254 GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10255 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
10256 GEN_HANDLER_E(fcfid, 0x3F, 0x0E, 0x1A, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10257 GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10258 GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10259 GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10260 GEN_HANDLER_E(fctid, 0x3F, 0x0E, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10261 GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10262 GEN_HANDLER_E(fctidz, 0x3F, 0x0F, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10263 GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10264 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
10265 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
10266 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
10267 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
10268
10269 #undef GEN_LD
10270 #undef GEN_LDU
10271 #undef GEN_LDUX
10272 #undef GEN_LDX_E
10273 #undef GEN_LDS
10274 #define GEN_LD(name, ldop, opc, type) \
10275 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10276 #define GEN_LDU(name, ldop, opc, type) \
10277 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10278 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
10279 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10280 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
10281 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10282 #define GEN_LDS(name, ldop, op, type) \
10283 GEN_LD(name, ldop, op | 0x20, type) \
10284 GEN_LDU(name, ldop, op | 0x21, type) \
10285 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
10286 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
10287
10288 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
10289 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
10290 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
10291 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
10292 #if defined(TARGET_PPC64)
10293 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
10294 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
10295 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
10296 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
10297 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
10298 #endif
10299 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
10300 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
10301
10302 #undef GEN_ST
10303 #undef GEN_STU
10304 #undef GEN_STUX
10305 #undef GEN_STX_E
10306 #undef GEN_STS
10307 #define GEN_ST(name, stop, opc, type) \
10308 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10309 #define GEN_STU(name, stop, opc, type) \
10310 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
10311 #define GEN_STUX(name, stop, opc2, opc3, type) \
10312 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10313 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
10314 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10315 #define GEN_STS(name, stop, op, type) \
10316 GEN_ST(name, stop, op | 0x20, type) \
10317 GEN_STU(name, stop, op | 0x21, type) \
10318 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
10319 GEN_STX(name, stop, 0x17, op | 0x00, type)
10320
10321 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
10322 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
10323 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
10324 #if defined(TARGET_PPC64)
10325 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
10326 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
10327 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
10328 #endif
10329 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
10330 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
10331
10332 #undef GEN_LDF
10333 #undef GEN_LDUF
10334 #undef GEN_LDUXF
10335 #undef GEN_LDXF
10336 #undef GEN_LDFS
10337 #define GEN_LDF(name, ldop, opc, type) \
10338 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10339 #define GEN_LDUF(name, ldop, opc, type) \
10340 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10341 #define GEN_LDUXF(name, ldop, opc, type) \
10342 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10343 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
10344 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10345 #define GEN_LDFS(name, ldop, op, type) \
10346 GEN_LDF(name, ldop, op | 0x20, type) \
10347 GEN_LDUF(name, ldop, op | 0x21, type) \
10348 GEN_LDUXF(name, ldop, op | 0x01, type) \
10349 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10350
10351 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
10352 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
10353 GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
10354 GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
10355 GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10356 GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
10357
10358 #undef GEN_STF
10359 #undef GEN_STUF
10360 #undef GEN_STUXF
10361 #undef GEN_STXF
10362 #undef GEN_STFS
10363 #define GEN_STF(name, stop, opc, type) \
10364 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10365 #define GEN_STUF(name, stop, opc, type) \
10366 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10367 #define GEN_STUXF(name, stop, opc, type) \
10368 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10369 #define GEN_STXF(name, stop, opc2, opc3, type) \
10370 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10371 #define GEN_STFS(name, stop, op, type) \
10372 GEN_STF(name, stop, op | 0x20, type) \
10373 GEN_STUF(name, stop, op | 0x21, type) \
10374 GEN_STUXF(name, stop, op | 0x01, type) \
10375 GEN_STXF(name, stop, 0x17, op | 0x00, type)
10376
10377 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
10378 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
10379 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
10380 GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10381 GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
10382
10383 #undef GEN_CRLOGIC
10384 #define GEN_CRLOGIC(name, tcg_op, opc) \
10385 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10386 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
10387 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
10388 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
10389 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
10390 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
10391 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
10392 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
10393 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
10394
10395 #undef GEN_MAC_HANDLER
10396 #define GEN_MAC_HANDLER(name, opc2, opc3) \
10397 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10398 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
10399 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
10400 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
10401 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
10402 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
10403 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
10404 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
10405 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
10406 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
10407 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
10408 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
10409 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
10410 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
10411 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
10412 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
10413 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
10414 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
10415 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
10416 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
10417 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
10418 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
10419 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
10420 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
10421 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
10422 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
10423 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
10424 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
10425 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
10426 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
10427 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
10428 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
10429 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
10430 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
10431 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
10432 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
10433 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
10434 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
10435 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
10436 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
10437 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
10438 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
10439 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
10440
10441 #undef GEN_VR_LDX
10442 #undef GEN_VR_STX
10443 #undef GEN_VR_LVE
10444 #undef GEN_VR_STVE
10445 #define GEN_VR_LDX(name, opc2, opc3) \
10446 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10447 #define GEN_VR_STX(name, opc2, opc3) \
10448 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10449 #define GEN_VR_LVE(name, opc2, opc3) \
10450 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10451 #define GEN_VR_STVE(name, opc2, opc3) \
10452 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10453 GEN_VR_LDX(lvx, 0x07, 0x03),
10454 GEN_VR_LDX(lvxl, 0x07, 0x0B),
10455 GEN_VR_LVE(bx, 0x07, 0x00),
10456 GEN_VR_LVE(hx, 0x07, 0x01),
10457 GEN_VR_LVE(wx, 0x07, 0x02),
10458 GEN_VR_STX(svx, 0x07, 0x07),
10459 GEN_VR_STX(svxl, 0x07, 0x0F),
10460 GEN_VR_STVE(bx, 0x07, 0x04),
10461 GEN_VR_STVE(hx, 0x07, 0x05),
10462 GEN_VR_STVE(wx, 0x07, 0x06),
10463
10464 #undef GEN_VX_LOGICAL
10465 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10466 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10467
10468 #undef GEN_VX_LOGICAL_207
10469 #define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
10470 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10471
10472 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
10473 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
10474 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
10475 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
10476 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
10477 GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26),
10478 GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22),
10479 GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21),
10480
10481 #undef GEN_VXFORM
10482 #define GEN_VXFORM(name, opc2, opc3) \
10483 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10484
10485 #undef GEN_VXFORM_207
10486 #define GEN_VXFORM_207(name, opc2, opc3) \
10487 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10488
10489 #undef GEN_VXFORM_DUAL
10490 #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
10491 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
10492
10493 #undef GEN_VXRFORM_DUAL
10494 #define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
10495 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
10496 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
10497
10498 GEN_VXFORM(vaddubm, 0, 0),
10499 GEN_VXFORM(vadduhm, 0, 1),
10500 GEN_VXFORM(vadduwm, 0, 2),
10501 GEN_VXFORM_207(vaddudm, 0, 3),
10502 GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
10503 GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
10504 GEN_VXFORM(vsubuwm, 0, 18),
10505 GEN_VXFORM_207(vsubudm, 0, 19),
10506 GEN_VXFORM(vmaxub, 1, 0),
10507 GEN_VXFORM(vmaxuh, 1, 1),
10508 GEN_VXFORM(vmaxuw, 1, 2),
10509 GEN_VXFORM_207(vmaxud, 1, 3),
10510 GEN_VXFORM(vmaxsb, 1, 4),
10511 GEN_VXFORM(vmaxsh, 1, 5),
10512 GEN_VXFORM(vmaxsw, 1, 6),
10513 GEN_VXFORM_207(vmaxsd, 1, 7),
10514 GEN_VXFORM(vminub, 1, 8),
10515 GEN_VXFORM(vminuh, 1, 9),
10516 GEN_VXFORM(vminuw, 1, 10),
10517 GEN_VXFORM_207(vminud, 1, 11),
10518 GEN_VXFORM(vminsb, 1, 12),
10519 GEN_VXFORM(vminsh, 1, 13),
10520 GEN_VXFORM(vminsw, 1, 14),
10521 GEN_VXFORM_207(vminsd, 1, 15),
10522 GEN_VXFORM(vavgub, 1, 16),
10523 GEN_VXFORM(vavguh, 1, 17),
10524 GEN_VXFORM(vavguw, 1, 18),
10525 GEN_VXFORM(vavgsb, 1, 20),
10526 GEN_VXFORM(vavgsh, 1, 21),
10527 GEN_VXFORM(vavgsw, 1, 22),
10528 GEN_VXFORM(vmrghb, 6, 0),
10529 GEN_VXFORM(vmrghh, 6, 1),
10530 GEN_VXFORM(vmrghw, 6, 2),
10531 GEN_VXFORM(vmrglb, 6, 4),
10532 GEN_VXFORM(vmrglh, 6, 5),
10533 GEN_VXFORM(vmrglw, 6, 6),
10534 GEN_VXFORM_207(vmrgew, 6, 30),
10535 GEN_VXFORM_207(vmrgow, 6, 26),
10536 GEN_VXFORM(vmuloub, 4, 0),
10537 GEN_VXFORM(vmulouh, 4, 1),
10538 GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
10539 GEN_VXFORM(vmulosb, 4, 4),
10540 GEN_VXFORM(vmulosh, 4, 5),
10541 GEN_VXFORM_207(vmulosw, 4, 6),
10542 GEN_VXFORM(vmuleub, 4, 8),
10543 GEN_VXFORM(vmuleuh, 4, 9),
10544 GEN_VXFORM_207(vmuleuw, 4, 10),
10545 GEN_VXFORM(vmulesb, 4, 12),
10546 GEN_VXFORM(vmulesh, 4, 13),
10547 GEN_VXFORM_207(vmulesw, 4, 14),
10548 GEN_VXFORM(vslb, 2, 4),
10549 GEN_VXFORM(vslh, 2, 5),
10550 GEN_VXFORM(vslw, 2, 6),
10551 GEN_VXFORM_207(vsld, 2, 23),
10552 GEN_VXFORM(vsrb, 2, 8),
10553 GEN_VXFORM(vsrh, 2, 9),
10554 GEN_VXFORM(vsrw, 2, 10),
10555 GEN_VXFORM_207(vsrd, 2, 27),
10556 GEN_VXFORM(vsrab, 2, 12),
10557 GEN_VXFORM(vsrah, 2, 13),
10558 GEN_VXFORM(vsraw, 2, 14),
10559 GEN_VXFORM_207(vsrad, 2, 15),
10560 GEN_VXFORM(vslo, 6, 16),
10561 GEN_VXFORM(vsro, 6, 17),
10562 GEN_VXFORM(vaddcuw, 0, 6),
10563 GEN_VXFORM(vsubcuw, 0, 22),
10564 GEN_VXFORM(vaddubs, 0, 8),
10565 GEN_VXFORM(vadduhs, 0, 9),
10566 GEN_VXFORM(vadduws, 0, 10),
10567 GEN_VXFORM(vaddsbs, 0, 12),
10568 GEN_VXFORM(vaddshs, 0, 13),
10569 GEN_VXFORM(vaddsws, 0, 14),
10570 GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
10571 GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
10572 GEN_VXFORM(vsubuws, 0, 26),
10573 GEN_VXFORM(vsubsbs, 0, 28),
10574 GEN_VXFORM(vsubshs, 0, 29),
10575 GEN_VXFORM(vsubsws, 0, 30),
10576 GEN_VXFORM_207(vadduqm, 0, 4),
10577 GEN_VXFORM_207(vaddcuq, 0, 5),
10578 GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10579 GEN_VXFORM_207(vsubuqm, 0, 20),
10580 GEN_VXFORM_207(vsubcuq, 0, 21),
10581 GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10582 GEN_VXFORM(vrlb, 2, 0),
10583 GEN_VXFORM(vrlh, 2, 1),
10584 GEN_VXFORM(vrlw, 2, 2),
10585 GEN_VXFORM_207(vrld, 2, 3),
10586 GEN_VXFORM(vsl, 2, 7),
10587 GEN_VXFORM(vsr, 2, 11),
10588 GEN_VXFORM(vpkuhum, 7, 0),
10589 GEN_VXFORM(vpkuwum, 7, 1),
10590 GEN_VXFORM_207(vpkudum, 7, 17),
10591 GEN_VXFORM(vpkuhus, 7, 2),
10592 GEN_VXFORM(vpkuwus, 7, 3),
10593 GEN_VXFORM_207(vpkudus, 7, 19),
10594 GEN_VXFORM(vpkshus, 7, 4),
10595 GEN_VXFORM(vpkswus, 7, 5),
10596 GEN_VXFORM_207(vpksdus, 7, 21),
10597 GEN_VXFORM(vpkshss, 7, 6),
10598 GEN_VXFORM(vpkswss, 7, 7),
10599 GEN_VXFORM_207(vpksdss, 7, 23),
10600 GEN_VXFORM(vpkpx, 7, 12),
10601 GEN_VXFORM(vsum4ubs, 4, 24),
10602 GEN_VXFORM(vsum4sbs, 4, 28),
10603 GEN_VXFORM(vsum4shs, 4, 25),
10604 GEN_VXFORM(vsum2sws, 4, 26),
10605 GEN_VXFORM(vsumsws, 4, 30),
10606 GEN_VXFORM(vaddfp, 5, 0),
10607 GEN_VXFORM(vsubfp, 5, 1),
10608 GEN_VXFORM(vmaxfp, 5, 16),
10609 GEN_VXFORM(vminfp, 5, 17),
10610
10611 #undef GEN_VXRFORM1
10612 #undef GEN_VXRFORM
10613 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10614 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10615 #define GEN_VXRFORM(name, opc2, opc3) \
10616 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10617 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10618 GEN_VXRFORM(vcmpequb, 3, 0)
10619 GEN_VXRFORM(vcmpequh, 3, 1)
10620 GEN_VXRFORM(vcmpequw, 3, 2)
10621 GEN_VXRFORM(vcmpgtsb, 3, 12)
10622 GEN_VXRFORM(vcmpgtsh, 3, 13)
10623 GEN_VXRFORM(vcmpgtsw, 3, 14)
10624 GEN_VXRFORM(vcmpgtub, 3, 8)
10625 GEN_VXRFORM(vcmpgtuh, 3, 9)
10626 GEN_VXRFORM(vcmpgtuw, 3, 10)
10627 GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE)
10628 GEN_VXRFORM(vcmpgefp, 3, 7)
10629 GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE)
10630 GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE)
10631
10632 #undef GEN_VXFORM_SIMM
10633 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
10634 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10635 GEN_VXFORM_SIMM(vspltisb, 6, 12),
10636 GEN_VXFORM_SIMM(vspltish, 6, 13),
10637 GEN_VXFORM_SIMM(vspltisw, 6, 14),
10638
10639 #undef GEN_VXFORM_NOA
10640 #define GEN_VXFORM_NOA(name, opc2, opc3) \
10641 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10642 GEN_VXFORM_NOA(vupkhsb, 7, 8),
10643 GEN_VXFORM_NOA(vupkhsh, 7, 9),
10644 GEN_VXFORM_207(vupkhsw, 7, 25),
10645 GEN_VXFORM_NOA(vupklsb, 7, 10),
10646 GEN_VXFORM_NOA(vupklsh, 7, 11),
10647 GEN_VXFORM_207(vupklsw, 7, 27),
10648 GEN_VXFORM_NOA(vupkhpx, 7, 13),
10649 GEN_VXFORM_NOA(vupklpx, 7, 15),
10650 GEN_VXFORM_NOA(vrefp, 5, 4),
10651 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
10652 GEN_VXFORM_NOA(vexptefp, 5, 6),
10653 GEN_VXFORM_NOA(vlogefp, 5, 7),
10654 GEN_VXFORM_NOA(vrfim, 5, 11),
10655 GEN_VXFORM_NOA(vrfin, 5, 8),
10656 GEN_VXFORM_NOA(vrfip, 5, 10),
10657 GEN_VXFORM_NOA(vrfiz, 5, 9),
10658
10659 #undef GEN_VXFORM_UIMM
10660 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
10661 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10662 GEN_VXFORM_UIMM(vspltb, 6, 8),
10663 GEN_VXFORM_UIMM(vsplth, 6, 9),
10664 GEN_VXFORM_UIMM(vspltw, 6, 10),
10665 GEN_VXFORM_UIMM(vcfux, 5, 12),
10666 GEN_VXFORM_UIMM(vcfsx, 5, 13),
10667 GEN_VXFORM_UIMM(vctuxs, 5, 14),
10668 GEN_VXFORM_UIMM(vctsxs, 5, 15),
10669
10670 #undef GEN_VAFORM_PAIRED
10671 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10672 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10673 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
10674 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
10675 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
10676 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
10677 GEN_VAFORM_PAIRED(vsel, vperm, 21),
10678 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
10679
10680 GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
10681 GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
10682 GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
10683 GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
10684
10685 GEN_VXFORM_207(vbpermq, 6, 21),
10686 GEN_VXFORM_207(vgbbd, 6, 20),
10687 GEN_VXFORM_207(vpmsumb, 4, 16),
10688 GEN_VXFORM_207(vpmsumh, 4, 17),
10689 GEN_VXFORM_207(vpmsumw, 4, 18),
10690 GEN_VXFORM_207(vpmsumd, 4, 19),
10691
10692 GEN_VXFORM_207(vsbox, 4, 23),
10693
10694 GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207),
10695 GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
10696
10697 GEN_VXFORM_207(vshasigmaw, 1, 26),
10698 GEN_VXFORM_207(vshasigmad, 1, 27),
10699
10700 GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE),
10701
10702 GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
10703 GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
10704 GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
10705 GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
10706 GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
10707 GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
10708 GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
10709
10710 GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
10711 GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
10712 GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
10713 GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
10714 GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
10715
10716 GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
10717 GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
10718 GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
10719 #if defined(TARGET_PPC64)
10720 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
10721 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
10722 #endif
10723
10724 #undef GEN_XX2FORM
10725 #define GEN_XX2FORM(name, opc2, opc3, fl2) \
10726 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10727 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10728
10729 #undef GEN_XX3FORM
10730 #define GEN_XX3FORM(name, opc2, opc3, fl2) \
10731 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10732 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10733 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10734 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10735
10736 #undef GEN_XX2IFORM
10737 #define GEN_XX2IFORM(name, opc2, opc3, fl2) \
10738 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 1, PPC_NONE, fl2), \
10739 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 1, PPC_NONE, fl2), \
10740 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 1, PPC_NONE, fl2), \
10741 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 1, PPC_NONE, fl2)
10742
10743 #undef GEN_XX3_RC_FORM
10744 #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10745 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10746 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10747 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10748 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10749 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10750 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10751 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10752 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10753
10754 #undef GEN_XX3FORM_DM
10755 #define GEN_XX3FORM_DM(name, opc2, opc3) \
10756 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10757 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10758 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10759 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10760 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10761 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10762 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10763 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10764 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10765 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10766 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10767 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10768 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10769 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10770 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10771 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10772
10773 GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
10774 GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
10775 GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
10776 GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
10777
10778 GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
10779 GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
10780 GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
10781 GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
10782 GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
10783 GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
10784 GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
10785 GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
10786
10787 GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
10788 GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
10789 GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
10790 GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
10791 GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
10792 GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
10793 GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
10794 GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
10795 GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
10796 GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
10797 GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
10798 GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
10799 GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
10800 GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
10801 GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
10802 GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
10803 GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
10804 GEN_XX2IFORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
10805 GEN_XX2IFORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
10806 GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
10807 GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
10808 GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
10809 GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
10810 GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
10811 GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
10812 GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
10813 GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
10814 GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
10815 GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
10816 GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
10817 GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
10818 GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
10819 GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
10820 GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
10821 GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
10822 GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
10823
10824 GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
10825 GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
10826 GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
10827 GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
10828 GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
10829 GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
10830 GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
10831 GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
10832 GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
10833 GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207),
10834 GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207),
10835 GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207),
10836 GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
10837 GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
10838 GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
10839 GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
10840 GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
10841 GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
10842
10843 GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
10844 GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
10845 GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
10846 GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
10847 GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
10848 GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
10849 GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
10850 GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
10851 GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
10852 GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
10853 GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
10854 GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
10855 GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
10856 GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
10857 GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
10858 GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
10859 GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
10860 GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
10861 GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
10862 GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
10863 GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
10864 GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
10865 GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
10866 GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
10867 GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
10868 GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
10869 GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
10870 GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
10871 GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
10872 GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
10873 GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
10874 GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
10875 GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
10876 GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
10877 GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
10878 GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
10879
10880 GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
10881 GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
10882 GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
10883 GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
10884 GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
10885 GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
10886 GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
10887 GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
10888 GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
10889 GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
10890 GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
10891 GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
10892 GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
10893 GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
10894 GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
10895 GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
10896 GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
10897 GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
10898 GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
10899 GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
10900 GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
10901 GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
10902 GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
10903 GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
10904 GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
10905 GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
10906 GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
10907 GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
10908 GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
10909 GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
10910 GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
10911 GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
10912 GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
10913 GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
10914 GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
10915 GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
10916
10917 #undef VSX_LOGICAL
10918 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
10919 GEN_XX3FORM(name, opc2, opc3, fl2)
10920
10921 VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
10922 VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
10923 VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
10924 VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
10925 VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
10926 VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
10927 VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
10928 VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
10929 GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
10930 GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
10931 GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
10932 GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
10933
10934 #define GEN_XXSEL_ROW(opc3) \
10935 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
10936 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
10937 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
10938 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
10939 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
10940 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
10941 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
10942 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
10943
10944 GEN_XXSEL_ROW(0x00)
10945 GEN_XXSEL_ROW(0x01)
10946 GEN_XXSEL_ROW(0x02)
10947 GEN_XXSEL_ROW(0x03)
10948 GEN_XXSEL_ROW(0x04)
10949 GEN_XXSEL_ROW(0x05)
10950 GEN_XXSEL_ROW(0x06)
10951 GEN_XXSEL_ROW(0x07)
10952 GEN_XXSEL_ROW(0x08)
10953 GEN_XXSEL_ROW(0x09)
10954 GEN_XXSEL_ROW(0x0A)
10955 GEN_XXSEL_ROW(0x0B)
10956 GEN_XXSEL_ROW(0x0C)
10957 GEN_XXSEL_ROW(0x0D)
10958 GEN_XXSEL_ROW(0x0E)
10959 GEN_XXSEL_ROW(0x0F)
10960 GEN_XXSEL_ROW(0x10)
10961 GEN_XXSEL_ROW(0x11)
10962 GEN_XXSEL_ROW(0x12)
10963 GEN_XXSEL_ROW(0x13)
10964 GEN_XXSEL_ROW(0x14)
10965 GEN_XXSEL_ROW(0x15)
10966 GEN_XXSEL_ROW(0x16)
10967 GEN_XXSEL_ROW(0x17)
10968 GEN_XXSEL_ROW(0x18)
10969 GEN_XXSEL_ROW(0x19)
10970 GEN_XXSEL_ROW(0x1A)
10971 GEN_XXSEL_ROW(0x1B)
10972 GEN_XXSEL_ROW(0x1C)
10973 GEN_XXSEL_ROW(0x1D)
10974 GEN_XXSEL_ROW(0x1E)
10975 GEN_XXSEL_ROW(0x1F)
10976
10977 GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
10978
10979 #undef GEN_DFP_T_A_B_Rc
10980 #undef GEN_DFP_BF_A_B
10981 #undef GEN_DFP_BF_A_DCM
10982 #undef GEN_DFP_T_B_U32_U32_Rc
10983 #undef GEN_DFP_T_A_B_I32_Rc
10984 #undef GEN_DFP_T_B_Rc
10985 #undef GEN_DFP_T_FPR_I32_Rc
10986
10987 #define _GEN_DFP_LONG(name, op1, op2, mask) \
10988 GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
10989
10990 #define _GEN_DFP_LONGx2(name, op1, op2, mask) \
10991 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10992 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10993
10994 #define _GEN_DFP_LONGx4(name, op1, op2, mask) \
10995 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10996 GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10997 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10998 GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10999
11000 #define _GEN_DFP_QUAD(name, op1, op2, mask) \
11001 GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
11002
11003 #define _GEN_DFP_QUADx2(name, op1, op2, mask) \
11004 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11005 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
11006
11007 #define _GEN_DFP_QUADx4(name, op1, op2, mask) \
11008 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11009 GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
11010 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
11011 GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
11012
11013 #define GEN_DFP_T_A_B_Rc(name, op1, op2) \
11014 _GEN_DFP_LONG(name, op1, op2, 0x00000000)
11015
11016 #define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
11017 _GEN_DFP_QUAD(name, op1, op2, 0x00210800)
11018
11019 #define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
11020 _GEN_DFP_QUAD(name, op1, op2, 0x00200800)
11021
11022 #define GEN_DFP_T_B_Rc(name, op1, op2) \
11023 _GEN_DFP_LONG(name, op1, op2, 0x001F0000)
11024
11025 #define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
11026 _GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
11027
11028 #define GEN_DFP_Tp_B_Rc(name, op1, op2) \
11029 _GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
11030
11031 #define GEN_DFP_T_Bp_Rc(name, op1, op2) \
11032 _GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
11033
11034 #define GEN_DFP_BF_A_B(name, op1, op2) \
11035 _GEN_DFP_LONG(name, op1, op2, 0x00000001)
11036
11037 #define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
11038 _GEN_DFP_QUAD(name, op1, op2, 0x00610801)
11039
11040 #define GEN_DFP_BF_A_Bp(name, op1, op2) \
11041 _GEN_DFP_QUAD(name, op1, op2, 0x00600801)
11042
11043 #define GEN_DFP_BF_A_DCM(name, op1, op2) \
11044 _GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
11045
11046 #define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
11047 _GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
11048
11049 #define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
11050 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11051
11052 #define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
11053 _GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
11054
11055 #define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
11056 _GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
11057
11058 #define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
11059 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11060
11061 #define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
11062 _GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
11063
11064 #define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
11065 _GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
11066
11067 #define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
11068 _GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
11069
11070 #define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
11071 _GEN_DFP_LONG(name, op1, op2, 0x00070000)
11072
11073 #define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
11074 _GEN_DFP_QUAD(name, op1, op2, 0x00270800)
11075
11076 #define GEN_DFP_S_T_B_Rc(name, op1, op2) \
11077 _GEN_DFP_LONG(name, op1, op2, 0x000F0000)
11078
11079 #define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
11080 _GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
11081
11082 #define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
11083 _GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
11084
11085 #define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
11086 _GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
11087
11088 GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00),
11089 GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00),
11090 GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10),
11091 GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10),
11092 GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
11093 GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
11094 GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11),
11095 GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11),
11096 GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
11097 GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
11098 GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
11099 GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
11100 GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06),
11101 GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06),
11102 GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07),
11103 GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07),
11104 GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
11105 GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
11106 GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
11107 GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
11108 GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
11109 GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
11110 GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
11111 GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
11112 GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
11113 GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
11114 GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03),
11115 GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03),
11116 GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07),
11117 GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07),
11118 GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
11119 GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
11120 GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
11121 GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18),
11122 GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19),
11123 GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19),
11124 GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09),
11125 GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09),
11126 GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a),
11127 GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a),
11128 GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a),
11129 GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a),
11130 GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b),
11131 GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b),
11132 GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b),
11133 GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b),
11134 GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02),
11135 GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02),
11136 GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03),
11137 GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03),
11138
11139 #undef GEN_SPE
11140 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
11141 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
11142 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11143 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11144 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11145 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11146 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11147 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11148 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11149 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
11150 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
11151 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11152 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11153 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11154 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11155 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11156 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11157 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
11158 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11159 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11160 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11161 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11162 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11163 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11164 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11165 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11166 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11167 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11168 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11169 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11170 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
11171
11172 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11173 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11174 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11175 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11176 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11177 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11178 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11179 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11180 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11181 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11182 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11183 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11184 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11185 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11186
11187 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11188 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11189 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11190 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11191 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11192 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
11193 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11194 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11195 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11196 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11197 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11198 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11199 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11200 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11201
11202 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11203 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11204 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
11205 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11206 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11207 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11208 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11209 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
11210 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11211 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11212 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11213 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11214 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11215 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11216 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11217 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11218
11219 #undef GEN_SPEOP_LDST
11220 #define GEN_SPEOP_LDST(name, opc2, sh) \
11221 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
11222 GEN_SPEOP_LDST(evldd, 0x00, 3),
11223 GEN_SPEOP_LDST(evldw, 0x01, 3),
11224 GEN_SPEOP_LDST(evldh, 0x02, 3),
11225 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
11226 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
11227 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
11228 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
11229 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
11230 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
11231 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
11232 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
11233
11234 GEN_SPEOP_LDST(evstdd, 0x10, 3),
11235 GEN_SPEOP_LDST(evstdw, 0x11, 3),
11236 GEN_SPEOP_LDST(evstdh, 0x12, 3),
11237 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
11238 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
11239 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
11240 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
11241
11242 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
11243 PPC_NONE, PPC2_TM),
11244 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
11245 PPC_NONE, PPC2_TM),
11246 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
11247 PPC_NONE, PPC2_TM),
11248 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
11249 PPC_NONE, PPC2_TM),
11250 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
11251 PPC_NONE, PPC2_TM),
11252 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
11253 PPC_NONE, PPC2_TM),
11254 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
11255 PPC_NONE, PPC2_TM),
11256 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
11257 PPC_NONE, PPC2_TM),
11258 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
11259 PPC_NONE, PPC2_TM),
11260 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
11261 PPC_NONE, PPC2_TM),
11262 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
11263 PPC_NONE, PPC2_TM),
11264 };
11265
11266 #include "helper_regs.h"
11267 #include "translate_init.c"
11268
11269 /*****************************************************************************/
11270 /* Misc PowerPC helpers */
11271 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
11272 int flags)
11273 {
11274 #define RGPL 4
11275 #define RFPL 4
11276
11277 PowerPCCPU *cpu = POWERPC_CPU(cs);
11278 CPUPPCState *env = &cpu->env;
11279 int i;
11280
11281 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
11282 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
11283 env->nip, env->lr, env->ctr, cpu_read_xer(env),
11284 cs->cpu_index);
11285 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
11286 TARGET_FMT_lx " iidx %d didx %d\n",
11287 env->msr, env->spr[SPR_HID0],
11288 env->hflags, env->immu_idx, env->dmmu_idx);
11289 #if !defined(NO_TIMER_DUMP)
11290 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
11291 #if !defined(CONFIG_USER_ONLY)
11292 " DECR %08" PRIu32
11293 #endif
11294 "\n",
11295 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
11296 #if !defined(CONFIG_USER_ONLY)
11297 , cpu_ppc_load_decr(env)
11298 #endif
11299 );
11300 #endif
11301 for (i = 0; i < 32; i++) {
11302 if ((i & (RGPL - 1)) == 0)
11303 cpu_fprintf(f, "GPR%02d", i);
11304 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
11305 if ((i & (RGPL - 1)) == (RGPL - 1))
11306 cpu_fprintf(f, "\n");
11307 }
11308 cpu_fprintf(f, "CR ");
11309 for (i = 0; i < 8; i++)
11310 cpu_fprintf(f, "%01x", env->crf[i]);
11311 cpu_fprintf(f, " [");
11312 for (i = 0; i < 8; i++) {
11313 char a = '-';
11314 if (env->crf[i] & 0x08)
11315 a = 'L';
11316 else if (env->crf[i] & 0x04)
11317 a = 'G';
11318 else if (env->crf[i] & 0x02)
11319 a = 'E';
11320 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
11321 }
11322 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
11323 env->reserve_addr);
11324 for (i = 0; i < 32; i++) {
11325 if ((i & (RFPL - 1)) == 0)
11326 cpu_fprintf(f, "FPR%02d", i);
11327 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
11328 if ((i & (RFPL - 1)) == (RFPL - 1))
11329 cpu_fprintf(f, "\n");
11330 }
11331 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
11332 #if !defined(CONFIG_USER_ONLY)
11333 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
11334 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
11335 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
11336 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
11337
11338 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
11339 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
11340 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
11341 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
11342
11343 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
11344 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
11345 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
11346 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
11347
11348 if (env->excp_model == POWERPC_EXCP_BOOKE) {
11349 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
11350 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
11351 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
11352 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
11353
11354 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
11355 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
11356 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
11357 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
11358
11359 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
11360 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
11361 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
11362 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
11363
11364 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
11365 " EPR " TARGET_FMT_lx "\n",
11366 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
11367 env->spr[SPR_BOOKE_EPR]);
11368
11369 /* FSL-specific */
11370 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
11371 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
11372 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
11373 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
11374
11375 /*
11376 * IVORs are left out as they are large and do not change often --
11377 * they can be read with "p $ivor0", "p $ivor1", etc.
11378 */
11379 }
11380
11381 #if defined(TARGET_PPC64)
11382 if (env->flags & POWERPC_FLAG_CFAR) {
11383 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
11384 }
11385 #endif
11386
11387 switch (env->mmu_model) {
11388 case POWERPC_MMU_32B:
11389 case POWERPC_MMU_601:
11390 case POWERPC_MMU_SOFT_6xx:
11391 case POWERPC_MMU_SOFT_74xx:
11392 #if defined(TARGET_PPC64)
11393 case POWERPC_MMU_64B:
11394 case POWERPC_MMU_2_03:
11395 case POWERPC_MMU_2_06:
11396 case POWERPC_MMU_2_06a:
11397 case POWERPC_MMU_2_07:
11398 case POWERPC_MMU_2_07a:
11399 #endif
11400 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
11401 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
11402 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
11403 break;
11404 case POWERPC_MMU_BOOKE206:
11405 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
11406 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
11407 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
11408 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
11409
11410 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
11411 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
11412 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
11413 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
11414
11415 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
11416 " TLB1CFG " TARGET_FMT_lx "\n",
11417 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
11418 env->spr[SPR_BOOKE_TLB1CFG]);
11419 break;
11420 default:
11421 break;
11422 }
11423 #endif
11424
11425 #undef RGPL
11426 #undef RFPL
11427 }
11428
11429 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
11430 fprintf_function cpu_fprintf, int flags)
11431 {
11432 #if defined(DO_PPC_STATISTICS)
11433 PowerPCCPU *cpu = POWERPC_CPU(cs);
11434 opc_handler_t **t1, **t2, **t3, *handler;
11435 int op1, op2, op3;
11436
11437 t1 = cpu->env.opcodes;
11438 for (op1 = 0; op1 < 64; op1++) {
11439 handler = t1[op1];
11440 if (is_indirect_opcode(handler)) {
11441 t2 = ind_table(handler);
11442 for (op2 = 0; op2 < 32; op2++) {
11443 handler = t2[op2];
11444 if (is_indirect_opcode(handler)) {
11445 t3 = ind_table(handler);
11446 for (op3 = 0; op3 < 32; op3++) {
11447 handler = t3[op3];
11448 if (handler->count == 0)
11449 continue;
11450 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
11451 "%016" PRIx64 " %" PRId64 "\n",
11452 op1, op2, op3, op1, (op3 << 5) | op2,
11453 handler->oname,
11454 handler->count, handler->count);
11455 }
11456 } else {
11457 if (handler->count == 0)
11458 continue;
11459 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
11460 "%016" PRIx64 " %" PRId64 "\n",
11461 op1, op2, op1, op2, handler->oname,
11462 handler->count, handler->count);
11463 }
11464 }
11465 } else {
11466 if (handler->count == 0)
11467 continue;
11468 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
11469 " %" PRId64 "\n",
11470 op1, op1, handler->oname,
11471 handler->count, handler->count);
11472 }
11473 }
11474 #endif
11475 }
11476
11477 /*****************************************************************************/
11478 void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
11479 {
11480 PowerPCCPU *cpu = ppc_env_get_cpu(env);
11481 CPUState *cs = CPU(cpu);
11482 DisasContext ctx, *ctxp = &ctx;
11483 opc_handler_t **table, *handler;
11484 target_ulong pc_start;
11485 int num_insns;
11486 int max_insns;
11487
11488 pc_start = tb->pc;
11489 ctx.nip = pc_start;
11490 ctx.tb = tb;
11491 ctx.exception = POWERPC_EXCP_NONE;
11492 ctx.spr_cb = env->spr_cb;
11493 ctx.pr = msr_pr;
11494 ctx.mem_idx = env->dmmu_idx;
11495 #if !defined(CONFIG_USER_ONLY)
11496 ctx.hv = msr_hv || !env->has_hv_mode;
11497 #endif
11498 ctx.insns_flags = env->insns_flags;
11499 ctx.insns_flags2 = env->insns_flags2;
11500 ctx.access_type = -1;
11501 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
11502 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
11503 #if defined(TARGET_PPC64)
11504 ctx.sf_mode = msr_is_64bit(env, env->msr);
11505 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
11506 #endif
11507 if (env->mmu_model == POWERPC_MMU_32B ||
11508 env->mmu_model == POWERPC_MMU_601 ||
11509 (env->mmu_model & POWERPC_MMU_64B))
11510 ctx.lazy_tlb_flush = true;
11511
11512 ctx.fpu_enabled = msr_fp;
11513 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
11514 ctx.spe_enabled = msr_spe;
11515 else
11516 ctx.spe_enabled = 0;
11517 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
11518 ctx.altivec_enabled = msr_vr;
11519 else
11520 ctx.altivec_enabled = 0;
11521 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
11522 ctx.vsx_enabled = msr_vsx;
11523 } else {
11524 ctx.vsx_enabled = 0;
11525 }
11526 #if defined(TARGET_PPC64)
11527 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
11528 ctx.tm_enabled = msr_tm;
11529 } else {
11530 ctx.tm_enabled = 0;
11531 }
11532 #endif
11533 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
11534 ctx.singlestep_enabled = CPU_SINGLE_STEP;
11535 else
11536 ctx.singlestep_enabled = 0;
11537 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
11538 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
11539 if (unlikely(cs->singlestep_enabled)) {
11540 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
11541 }
11542 #if defined (DO_SINGLE_STEP) && 0
11543 /* Single step trace mode */
11544 msr_se = 1;
11545 #endif
11546 num_insns = 0;
11547 max_insns = tb->cflags & CF_COUNT_MASK;
11548 if (max_insns == 0) {
11549 max_insns = CF_COUNT_MASK;
11550 }
11551 if (max_insns > TCG_MAX_INSNS) {
11552 max_insns = TCG_MAX_INSNS;
11553 }
11554
11555 gen_tb_start(tb);
11556 tcg_clear_temp_count();
11557 /* Set env in case of segfault during code fetch */
11558 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
11559 tcg_gen_insn_start(ctx.nip);
11560 num_insns++;
11561
11562 if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
11563 gen_debug_exception(ctxp);
11564 /* The address covered by the breakpoint must be included in
11565 [tb->pc, tb->pc + tb->size) in order to for it to be
11566 properly cleared -- thus we increment the PC here so that
11567 the logic setting tb->size below does the right thing. */
11568 ctx.nip += 4;
11569 break;
11570 }
11571
11572 LOG_DISAS("----------------\n");
11573 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
11574 ctx.nip, ctx.mem_idx, (int)msr_ir);
11575 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
11576 gen_io_start();
11577 if (unlikely(need_byteswap(&ctx))) {
11578 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
11579 } else {
11580 ctx.opcode = cpu_ldl_code(env, ctx.nip);
11581 }
11582 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
11583 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
11584 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
11585 ctx.nip += 4;
11586 table = env->opcodes;
11587 handler = table[opc1(ctx.opcode)];
11588 if (is_indirect_opcode(handler)) {
11589 table = ind_table(handler);
11590 handler = table[opc2(ctx.opcode)];
11591 if (is_indirect_opcode(handler)) {
11592 table = ind_table(handler);
11593 handler = table[opc3(ctx.opcode)];
11594 }
11595 }
11596 /* Is opcode *REALLY* valid ? */
11597 if (unlikely(handler->handler == &gen_invalid)) {
11598 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
11599 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
11600 opc1(ctx.opcode), opc2(ctx.opcode),
11601 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
11602 } else {
11603 uint32_t inval;
11604
11605 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
11606 inval = handler->inval2;
11607 } else {
11608 inval = handler->inval1;
11609 }
11610
11611 if (unlikely((ctx.opcode & inval) != 0)) {
11612 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
11613 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
11614 ctx.opcode & inval, opc1(ctx.opcode),
11615 opc2(ctx.opcode), opc3(ctx.opcode),
11616 ctx.opcode, ctx.nip - 4);
11617 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
11618 break;
11619 }
11620 }
11621 (*(handler->handler))(&ctx);
11622 #if defined(DO_PPC_STATISTICS)
11623 handler->count++;
11624 #endif
11625 /* Check trace mode exceptions */
11626 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
11627 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
11628 ctx.exception != POWERPC_SYSCALL &&
11629 ctx.exception != POWERPC_EXCP_TRAP &&
11630 ctx.exception != POWERPC_EXCP_BRANCH)) {
11631 gen_exception(ctxp, POWERPC_EXCP_TRACE);
11632 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
11633 (cs->singlestep_enabled) ||
11634 singlestep ||
11635 num_insns >= max_insns)) {
11636 /* if we reach a page boundary or are single stepping, stop
11637 * generation
11638 */
11639 break;
11640 }
11641 if (tcg_check_temp_count()) {
11642 fprintf(stderr, "Opcode %02x %02x %02x (%08x) leaked temporaries\n",
11643 opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode),
11644 ctx.opcode);
11645 exit(1);
11646 }
11647 }
11648 if (tb->cflags & CF_LAST_IO)
11649 gen_io_end();
11650 if (ctx.exception == POWERPC_EXCP_NONE) {
11651 gen_goto_tb(&ctx, 0, ctx.nip);
11652 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
11653 if (unlikely(cs->singlestep_enabled)) {
11654 gen_debug_exception(ctxp);
11655 }
11656 /* Generate the return instruction */
11657 tcg_gen_exit_tb(0);
11658 }
11659 gen_tb_end(tb, num_insns);
11660
11661 tb->size = ctx.nip - pc_start;
11662 tb->icount = num_insns;
11663
11664 #if defined(DEBUG_DISAS)
11665 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
11666 && qemu_log_in_addr_range(pc_start)) {
11667 int flags;
11668 flags = env->bfd_mach;
11669 flags |= ctx.le_mode << 16;
11670 qemu_log("IN: %s\n", lookup_symbol(pc_start));
11671 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
11672 qemu_log("\n");
11673 }
11674 #endif
11675 }
11676
11677 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
11678 target_ulong *data)
11679 {
11680 env->nip = data[0];
11681 }
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