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hw/arm/allwinner: Clean up local variable shadowing
[qemu/kevin.git] / hw / arm / allwinner-r40.c
bloba0d367c60d17f61fa5c3ef545e0a71f1a809c059
1 /*
2 * Allwinner R40/A40i/T3 System on Chip emulation
3 *
4 * Copyright (C) 2023 qianfan Zhao <qianfanguijin@163.com>
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
22 #include "qemu/error-report.h"
23 #include "qemu/bswap.h"
24 #include "qemu/module.h"
25 #include "qemu/units.h"
26 #include "hw/qdev-core.h"
27 #include "hw/sysbus.h"
28 #include "hw/char/serial.h"
29 #include "hw/misc/unimp.h"
30 #include "hw/usb/hcd-ehci.h"
31 #include "hw/loader.h"
32 #include "sysemu/sysemu.h"
33 #include "hw/arm/allwinner-r40.h"
34 #include "hw/misc/allwinner-r40-dramc.h"
35
36 /* Memory map */
37 const hwaddr allwinner_r40_memmap[] = {
38 [AW_R40_DEV_SRAM_A1] = 0x00000000,
39 [AW_R40_DEV_SRAM_A2] = 0x00004000,
40 [AW_R40_DEV_SRAM_A3] = 0x00008000,
41 [AW_R40_DEV_SRAM_A4] = 0x0000b400,
42 [AW_R40_DEV_SRAMC] = 0x01c00000,
43 [AW_R40_DEV_EMAC] = 0x01c0b000,
44 [AW_R40_DEV_MMC0] = 0x01c0f000,
45 [AW_R40_DEV_MMC1] = 0x01c10000,
46 [AW_R40_DEV_MMC2] = 0x01c11000,
47 [AW_R40_DEV_MMC3] = 0x01c12000,
48 [AW_R40_DEV_CCU] = 0x01c20000,
49 [AW_R40_DEV_PIT] = 0x01c20c00,
50 [AW_R40_DEV_UART0] = 0x01c28000,
51 [AW_R40_DEV_UART1] = 0x01c28400,
52 [AW_R40_DEV_UART2] = 0x01c28800,
53 [AW_R40_DEV_UART3] = 0x01c28c00,
54 [AW_R40_DEV_UART4] = 0x01c29000,
55 [AW_R40_DEV_UART5] = 0x01c29400,
56 [AW_R40_DEV_UART6] = 0x01c29800,
57 [AW_R40_DEV_UART7] = 0x01c29c00,
58 [AW_R40_DEV_TWI0] = 0x01c2ac00,
59 [AW_R40_DEV_GMAC] = 0x01c50000,
60 [AW_R40_DEV_DRAMCOM] = 0x01c62000,
61 [AW_R40_DEV_DRAMCTL] = 0x01c63000,
62 [AW_R40_DEV_DRAMPHY] = 0x01c65000,
63 [AW_R40_DEV_GIC_DIST] = 0x01c81000,
64 [AW_R40_DEV_GIC_CPU] = 0x01c82000,
65 [AW_R40_DEV_GIC_HYP] = 0x01c84000,
66 [AW_R40_DEV_GIC_VCPU] = 0x01c86000,
67 [AW_R40_DEV_SDRAM] = 0x40000000
68 };
69
70 /* List of unimplemented devices */
71 struct AwR40Unimplemented {
72 const char *device_name;
73 hwaddr base;
74 hwaddr size;
75 };
76
77 static struct AwR40Unimplemented r40_unimplemented[] = {
78 { "d-engine", 0x01000000, 4 * MiB },
79 { "d-inter", 0x01400000, 128 * KiB },
80 { "dma", 0x01c02000, 4 * KiB },
81 { "nfdc", 0x01c03000, 4 * KiB },
82 { "ts", 0x01c04000, 4 * KiB },
83 { "spi0", 0x01c05000, 4 * KiB },
84 { "spi1", 0x01c06000, 4 * KiB },
85 { "cs0", 0x01c09000, 4 * KiB },
86 { "keymem", 0x01c0a000, 4 * KiB },
87 { "usb0-otg", 0x01c13000, 4 * KiB },
88 { "usb0-host", 0x01c14000, 4 * KiB },
89 { "crypto", 0x01c15000, 4 * KiB },
90 { "spi2", 0x01c17000, 4 * KiB },
91 { "sata", 0x01c18000, 4 * KiB },
92 { "usb1-host", 0x01c19000, 4 * KiB },
93 { "sid", 0x01c1b000, 4 * KiB },
94 { "usb2-host", 0x01c1c000, 4 * KiB },
95 { "cs1", 0x01c1d000, 4 * KiB },
96 { "spi3", 0x01c1f000, 4 * KiB },
97 { "rtc", 0x01c20400, 1 * KiB },
98 { "pio", 0x01c20800, 1 * KiB },
99 { "owa", 0x01c21000, 1 * KiB },
100 { "ac97", 0x01c21400, 1 * KiB },
101 { "cir0", 0x01c21800, 1 * KiB },
102 { "cir1", 0x01c21c00, 1 * KiB },
103 { "pcm0", 0x01c22000, 1 * KiB },
104 { "pcm1", 0x01c22400, 1 * KiB },
105 { "pcm2", 0x01c22800, 1 * KiB },
106 { "audio", 0x01c22c00, 1 * KiB },
107 { "keypad", 0x01c23000, 1 * KiB },
108 { "pwm", 0x01c23400, 1 * KiB },
109 { "keyadc", 0x01c24400, 1 * KiB },
110 { "ths", 0x01c24c00, 1 * KiB },
111 { "rtp", 0x01c25000, 1 * KiB },
112 { "pmu", 0x01c25400, 1 * KiB },
113 { "cpu-cfg", 0x01c25c00, 1 * KiB },
114 { "uart0", 0x01c28000, 1 * KiB },
115 { "uart1", 0x01c28400, 1 * KiB },
116 { "uart2", 0x01c28800, 1 * KiB },
117 { "uart3", 0x01c28c00, 1 * KiB },
118 { "uart4", 0x01c29000, 1 * KiB },
119 { "uart5", 0x01c29400, 1 * KiB },
120 { "uart6", 0x01c29800, 1 * KiB },
121 { "uart7", 0x01c29c00, 1 * KiB },
122 { "ps20", 0x01c2a000, 1 * KiB },
123 { "ps21", 0x01c2a400, 1 * KiB },
124 { "twi1", 0x01c2b000, 1 * KiB },
125 { "twi2", 0x01c2b400, 1 * KiB },
126 { "twi3", 0x01c2b800, 1 * KiB },
127 { "twi4", 0x01c2c000, 1 * KiB },
128 { "scr", 0x01c2c400, 1 * KiB },
129 { "tvd-top", 0x01c30000, 4 * KiB },
130 { "tvd0", 0x01c31000, 4 * KiB },
131 { "tvd1", 0x01c32000, 4 * KiB },
132 { "tvd2", 0x01c33000, 4 * KiB },
133 { "tvd3", 0x01c34000, 4 * KiB },
134 { "gpu", 0x01c40000, 64 * KiB },
135 { "hstmr", 0x01c60000, 4 * KiB },
136 { "tcon-top", 0x01c70000, 4 * KiB },
137 { "lcd0", 0x01c71000, 4 * KiB },
138 { "lcd1", 0x01c72000, 4 * KiB },
139 { "tv0", 0x01c73000, 4 * KiB },
140 { "tv1", 0x01c74000, 4 * KiB },
141 { "tve-top", 0x01c90000, 16 * KiB },
142 { "tve0", 0x01c94000, 16 * KiB },
143 { "tve1", 0x01c98000, 16 * KiB },
144 { "mipi_dsi", 0x01ca0000, 4 * KiB },
145 { "mipi_dphy", 0x01ca1000, 4 * KiB },
146 { "ve", 0x01d00000, 1024 * KiB },
147 { "mp", 0x01e80000, 128 * KiB },
148 { "hdmi", 0x01ee0000, 128 * KiB },
149 { "prcm", 0x01f01400, 1 * KiB },
150 { "debug", 0x3f500000, 64 * KiB },
151 { "cpubist", 0x3f501000, 4 * KiB },
152 { "dcu", 0x3fff0000, 64 * KiB },
153 { "hstmr", 0x01c60000, 4 * KiB },
154 { "brom", 0xffff0000, 36 * KiB }
155 };
156
157 /* Per Processor Interrupts */
158 enum {
159 AW_R40_GIC_PPI_MAINT = 9,
160 AW_R40_GIC_PPI_HYPTIMER = 10,
161 AW_R40_GIC_PPI_VIRTTIMER = 11,
162 AW_R40_GIC_PPI_SECTIMER = 13,
163 AW_R40_GIC_PPI_PHYSTIMER = 14
164 };
165
166 /* Shared Processor Interrupts */
167 enum {
168 AW_R40_GIC_SPI_UART0 = 1,
169 AW_R40_GIC_SPI_UART1 = 2,
170 AW_R40_GIC_SPI_UART2 = 3,
171 AW_R40_GIC_SPI_UART3 = 4,
172 AW_R40_GIC_SPI_TWI0 = 7,
173 AW_R40_GIC_SPI_UART4 = 17,
174 AW_R40_GIC_SPI_UART5 = 18,
175 AW_R40_GIC_SPI_UART6 = 19,
176 AW_R40_GIC_SPI_UART7 = 20,
177 AW_R40_GIC_SPI_TIMER0 = 22,
178 AW_R40_GIC_SPI_TIMER1 = 23,
179 AW_R40_GIC_SPI_MMC0 = 32,
180 AW_R40_GIC_SPI_MMC1 = 33,
181 AW_R40_GIC_SPI_MMC2 = 34,
182 AW_R40_GIC_SPI_MMC3 = 35,
183 AW_R40_GIC_SPI_EMAC = 55,
184 AW_R40_GIC_SPI_GMAC = 85,
185 };
186
187 /* Allwinner R40 general constants */
188 enum {
189 AW_R40_GIC_NUM_SPI = 128
190 };
191
192 #define BOOT0_MAGIC "eGON.BT0"
193
194 /* The low 8-bits of the 'boot_media' field in the SPL header */
195 #define SUNXI_BOOTED_FROM_MMC0 0
196 #define SUNXI_BOOTED_FROM_NAND 1
197 #define SUNXI_BOOTED_FROM_MMC2 2
198 #define SUNXI_BOOTED_FROM_SPI 3
199
200 struct boot_file_head {
201 uint32_t b_instruction;
202 uint8_t magic[8];
203 uint32_t check_sum;
204 uint32_t length;
205 uint32_t pub_head_size;
206 uint32_t fel_script_address;
207 uint32_t fel_uEnv_length;
208 uint32_t dt_name_offset;
209 uint32_t dram_size;
210 uint32_t boot_media;
211 uint32_t string_pool[13];
212 };
213
214 bool allwinner_r40_bootrom_setup(AwR40State *s, BlockBackend *blk, int unit)
215 {
216 const int64_t rom_size = 32 * KiB;
217 g_autofree uint8_t *buffer = g_new0(uint8_t, rom_size);
218 struct boot_file_head *head = (struct boot_file_head *)buffer;
219
220 if (blk_pread(blk, 8 * KiB, rom_size, buffer, 0) < 0) {
221 error_setg(&error_fatal, "%s: failed to read BlockBackend data",
222 __func__);
223 return false;
224 }
225
226 /* we only check the magic string here. */
227 if (memcmp(head->magic, BOOT0_MAGIC, sizeof(head->magic))) {
228 return false;
229 }
230
231 /*
232 * Simulate the behavior of the bootROM, it will change the boot_media
233 * flag to indicate where the chip is booting from. R40 can boot from
234 * mmc0 or mmc2, the default value of boot_media is zero
235 * (SUNXI_BOOTED_FROM_MMC0), let's fix this flag when it is booting from
236 * the others.
237 */
238 if (unit == 2) {
239 head->boot_media = cpu_to_le32(SUNXI_BOOTED_FROM_MMC2);
240 } else {
241 head->boot_media = cpu_to_le32(SUNXI_BOOTED_FROM_MMC0);
242 }
243
244 rom_add_blob("allwinner-r40.bootrom", buffer, rom_size,
245 rom_size, s->memmap[AW_R40_DEV_SRAM_A1],
246 NULL, NULL, NULL, NULL, false);
247 return true;
248 }
249
250 static void allwinner_r40_init(Object *obj)
251 {
252 static const char *mmc_names[AW_R40_NUM_MMCS] = {
253 "mmc0", "mmc1", "mmc2", "mmc3"
254 };
255 AwR40State *s = AW_R40(obj);
256
257 s->memmap = allwinner_r40_memmap;
258
259 for (int i = 0; i < AW_R40_NUM_CPUS; i++) {
260 object_initialize_child(obj, "cpu[*]", &s->cpus[i],
261 ARM_CPU_TYPE_NAME("cortex-a7"));
262 }
263
264 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC);
265
266 object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT);
267 object_property_add_alias(obj, "clk0-freq", OBJECT(&s->timer),
268 "clk0-freq");
269 object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer),
270 "clk1-freq");
271
272 object_initialize_child(obj, "ccu", &s->ccu, TYPE_AW_R40_CCU);
273
274 for (int i = 0; i < AW_R40_NUM_MMCS; i++) {
275 object_initialize_child(obj, mmc_names[i], &s->mmc[i],
276 TYPE_AW_SDHOST_SUN50I_A64);
277 }
278
279 object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C_SUN6I);
280
281 object_initialize_child(obj, "emac", &s->emac, TYPE_AW_EMAC);
282 object_initialize_child(obj, "gmac", &s->gmac, TYPE_AW_SUN8I_EMAC);
283 object_property_add_alias(obj, "gmac-phy-addr",
284 OBJECT(&s->gmac), "phy-addr");
285
286 object_initialize_child(obj, "dramc", &s->dramc, TYPE_AW_R40_DRAMC);
287 object_property_add_alias(obj, "ram-addr", OBJECT(&s->dramc),
288 "ram-addr");
289 object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc),
290 "ram-size");
291
292 object_initialize_child(obj, "sramc", &s->sramc, TYPE_AW_SRAMC_SUN8I_R40);
293 }
294
295 static void allwinner_r40_realize(DeviceState *dev, Error **errp)
296 {
297 const char *r40_nic_models[] = { "gmac", "emac", NULL };
298 AwR40State *s = AW_R40(dev);
299
300 /* CPUs */
301 for (unsigned i = 0; i < AW_R40_NUM_CPUS; i++) {
302
303 /*
304 * Disable secondary CPUs. Guest EL3 firmware will start
305 * them via CPU reset control registers.
306 */
307 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off",
308 i > 0);
309
310 /* All exception levels required */
311 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el3", true);
312 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el2", true);
313
314 /* Mark realized */
315 qdev_realize(DEVICE(&s->cpus[i]), NULL, &error_fatal);
316 }
317
318 /* Generic Interrupt Controller */
319 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", AW_R40_GIC_NUM_SPI +
320 GIC_INTERNAL);
321 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
322 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_R40_NUM_CPUS);
323 qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false);
324 qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true);
325 sysbus_realize(SYS_BUS_DEVICE(&s->gic), &error_fatal);
326
327 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_R40_DEV_GIC_DIST]);
328 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_R40_DEV_GIC_CPU]);
329 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_R40_DEV_GIC_HYP]);
330 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s->memmap[AW_R40_DEV_GIC_VCPU]);
331
332 /*
333 * Wire the outputs from each CPU's generic timer and the GICv2
334 * maintenance interrupt signal to the appropriate GIC PPI inputs,
335 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
336 */
337 for (unsigned i = 0; i < AW_R40_NUM_CPUS; i++) {
338 DeviceState *cpudev = DEVICE(&s->cpus[i]);
339 int ppibase = AW_R40_GIC_NUM_SPI + i * GIC_INTERNAL + GIC_NR_SGIS;
340 int irq;
341 /*
342 * Mapping from the output timer irq lines from the CPU to the
343 * GIC PPI inputs used for this board.
344 */
345 const int timer_irq[] = {
346 [GTIMER_PHYS] = AW_R40_GIC_PPI_PHYSTIMER,
347 [GTIMER_VIRT] = AW_R40_GIC_PPI_VIRTTIMER,
348 [GTIMER_HYP] = AW_R40_GIC_PPI_HYPTIMER,
349 [GTIMER_SEC] = AW_R40_GIC_PPI_SECTIMER,
350 };
351
352 /* Connect CPU timer outputs to GIC PPI inputs */
353 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
354 qdev_connect_gpio_out(cpudev, irq,
355 qdev_get_gpio_in(DEVICE(&s->gic),
356 ppibase + timer_irq[irq]));
357 }
358
359 /* Connect GIC outputs to CPU interrupt inputs */
360 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
361 qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
362 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + AW_R40_NUM_CPUS,
363 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
364 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (2 * AW_R40_NUM_CPUS),
365 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
366 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (3 * AW_R40_NUM_CPUS),
367 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
368
369 /* GIC maintenance signal */
370 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (4 * AW_R40_NUM_CPUS),
371 qdev_get_gpio_in(DEVICE(&s->gic),
372 ppibase + AW_R40_GIC_PPI_MAINT));
373 }
374
375 /* Timer */
376 sysbus_realize(SYS_BUS_DEVICE(&s->timer), &error_fatal);
377 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_R40_DEV_PIT]);
378 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0,
379 qdev_get_gpio_in(DEVICE(&s->gic),
380 AW_R40_GIC_SPI_TIMER0));
381 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 1,
382 qdev_get_gpio_in(DEVICE(&s->gic),
383 AW_R40_GIC_SPI_TIMER1));
384
385 /* SRAM */
386 sysbus_realize(SYS_BUS_DEVICE(&s->sramc), &error_fatal);
387 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sramc), 0, s->memmap[AW_R40_DEV_SRAMC]);
388
389 memory_region_init_ram(&s->sram_a1, OBJECT(dev), "sram A1",
390 16 * KiB, &error_abort);
391 memory_region_init_ram(&s->sram_a2, OBJECT(dev), "sram A2",
392 16 * KiB, &error_abort);
393 memory_region_init_ram(&s->sram_a3, OBJECT(dev), "sram A3",
394 13 * KiB, &error_abort);
395 memory_region_init_ram(&s->sram_a4, OBJECT(dev), "sram A4",
396 3 * KiB, &error_abort);
397 memory_region_add_subregion(get_system_memory(),
398 s->memmap[AW_R40_DEV_SRAM_A1], &s->sram_a1);
399 memory_region_add_subregion(get_system_memory(),
400 s->memmap[AW_R40_DEV_SRAM_A2], &s->sram_a2);
401 memory_region_add_subregion(get_system_memory(),
402 s->memmap[AW_R40_DEV_SRAM_A3], &s->sram_a3);
403 memory_region_add_subregion(get_system_memory(),
404 s->memmap[AW_R40_DEV_SRAM_A4], &s->sram_a4);
405
406 /* Clock Control Unit */
407 sysbus_realize(SYS_BUS_DEVICE(&s->ccu), &error_fatal);
408 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_R40_DEV_CCU]);
409
410 /* SD/MMC */
411 for (int i = 0; i < AW_R40_NUM_MMCS; i++) {
412 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->gic),
413 AW_R40_GIC_SPI_MMC0 + i);
414 const hwaddr addr = s->memmap[AW_R40_DEV_MMC0 + i];
415
416 object_property_set_link(OBJECT(&s->mmc[i]), "dma-memory",
417 OBJECT(get_system_memory()), &error_fatal);
418 sysbus_realize(SYS_BUS_DEVICE(&s->mmc[i]), &error_fatal);
419 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc[i]), 0, addr);
420 sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc[i]), 0, irq);
421 }
422
423 /* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
424 for (int i = 0; i < AW_R40_NUM_UARTS; i++) {
425 static const int uart_irqs[AW_R40_NUM_UARTS] = {
426 AW_R40_GIC_SPI_UART0,
427 AW_R40_GIC_SPI_UART1,
428 AW_R40_GIC_SPI_UART2,
429 AW_R40_GIC_SPI_UART3,
430 AW_R40_GIC_SPI_UART4,
431 AW_R40_GIC_SPI_UART5,
432 AW_R40_GIC_SPI_UART6,
433 AW_R40_GIC_SPI_UART7,
434 };
435 const hwaddr addr = s->memmap[AW_R40_DEV_UART0 + i];
436
437 serial_mm_init(get_system_memory(), addr, 2,
438 qdev_get_gpio_in(DEVICE(&s->gic), uart_irqs[i]),
439 115200, serial_hd(i), DEVICE_NATIVE_ENDIAN);
440 }
441
442 /* I2C */
443 sysbus_realize(SYS_BUS_DEVICE(&s->i2c0), &error_fatal);
444 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c0), 0, s->memmap[AW_R40_DEV_TWI0]);
445 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0,
446 qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_TWI0));
447
448 /* DRAMC */
449 sysbus_realize(SYS_BUS_DEVICE(&s->dramc), &error_fatal);
450 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0,
451 s->memmap[AW_R40_DEV_DRAMCOM]);
452 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1,
453 s->memmap[AW_R40_DEV_DRAMCTL]);
454 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2,
455 s->memmap[AW_R40_DEV_DRAMPHY]);
456
457 /* nic support gmac and emac */
458 for (int i = 0; i < ARRAY_SIZE(r40_nic_models) - 1; i++) {
459 NICInfo *nic = &nd_table[i];
460
461 if (!nic->used) {
462 continue;
463 }
464 if (qemu_show_nic_models(nic->model, r40_nic_models)) {
465 exit(0);
466 }
467
468 switch (qemu_find_nic_model(nic, r40_nic_models, r40_nic_models[0])) {
469 case 0: /* gmac */
470 qdev_set_nic_properties(DEVICE(&s->gmac), nic);
471 break;
472 case 1: /* emac */
473 qdev_set_nic_properties(DEVICE(&s->emac), nic);
474 break;
475 default:
476 exit(1);
477 break;
478 }
479 }
480
481 /* GMAC */
482 object_property_set_link(OBJECT(&s->gmac), "dma-memory",
483 OBJECT(get_system_memory()), &error_fatal);
484 sysbus_realize(SYS_BUS_DEVICE(&s->gmac), &error_fatal);
485 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gmac), 0, s->memmap[AW_R40_DEV_GMAC]);
486 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gmac), 0,
487 qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_GMAC));
488
489 /* EMAC */
490 sysbus_realize(SYS_BUS_DEVICE(&s->emac), &error_fatal);
491 sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_R40_DEV_EMAC]);
492 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0,
493 qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_EMAC));
494
495 /* Unimplemented devices */
496 for (unsigned i = 0; i < ARRAY_SIZE(r40_unimplemented); i++) {
497 create_unimplemented_device(r40_unimplemented[i].device_name,
498 r40_unimplemented[i].base,
499 r40_unimplemented[i].size);
500 }
501 }
502
503 static void allwinner_r40_class_init(ObjectClass *oc, void *data)
504 {
505 DeviceClass *dc = DEVICE_CLASS(oc);
506
507 dc->realize = allwinner_r40_realize;
508 /* Reason: uses serial_hd() in realize function */
509 dc->user_creatable = false;
510 }
511
512 static const TypeInfo allwinner_r40_type_info = {
513 .name = TYPE_AW_R40,
514 .parent = TYPE_DEVICE,
515 .instance_size = sizeof(AwR40State),
516 .instance_init = allwinner_r40_init,
517 .class_init = allwinner_r40_class_init,
518 };
519
520 static void allwinner_r40_register_types(void)
521 {
522 type_register_static(&allwinner_r40_type_info);
523 }
524
525 type_init(allwinner_r40_register_types)
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