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ppc: Check the availability of transactional memory
[qemu/kevin.git] / hw / ppc / spapr.c
blob82723d16cb6395e4d7aeb5c7f5eef1f6ad5b8f5b
1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
27 #include "qemu/osdep.h"
28 #include "qapi/error.h"
29 #include "sysemu/sysemu.h"
30 #include "sysemu/numa.h"
31 #include "hw/hw.h"
32 #include "qemu/log.h"
33 #include "hw/fw-path-provider.h"
34 #include "elf.h"
35 #include "net/net.h"
36 #include "sysemu/device_tree.h"
37 #include "sysemu/block-backend.h"
38 #include "sysemu/cpus.h"
39 #include "sysemu/kvm.h"
40 #include "sysemu/device_tree.h"
41 #include "kvm_ppc.h"
42 #include "migration/migration.h"
43 #include "mmu-hash64.h"
44 #include "qom/cpu.h"
45
46 #include "hw/boards.h"
47 #include "hw/ppc/ppc.h"
48 #include "hw/loader.h"
49
50 #include "hw/ppc/spapr.h"
51 #include "hw/ppc/spapr_vio.h"
52 #include "hw/pci-host/spapr.h"
53 #include "hw/ppc/xics.h"
54 #include "hw/pci/msi.h"
55
56 #include "hw/pci/pci.h"
57 #include "hw/scsi/scsi.h"
58 #include "hw/virtio/virtio-scsi.h"
59
60 #include "exec/address-spaces.h"
61 #include "hw/usb.h"
62 #include "qemu/config-file.h"
63 #include "qemu/error-report.h"
64 #include "trace.h"
65 #include "hw/nmi.h"
66
67 #include "hw/compat.h"
68 #include "qemu/cutils.h"
69 #include "hw/ppc/spapr_cpu_core.h"
70 #include "qmp-commands.h"
71
72 #include <libfdt.h>
73
74 /* SLOF memory layout:
75 *
76 * SLOF raw image loaded at 0, copies its romfs right below the flat
77 * device-tree, then position SLOF itself 31M below that
78 *
79 * So we set FW_OVERHEAD to 40MB which should account for all of that
80 * and more
81 *
82 * We load our kernel at 4M, leaving space for SLOF initial image
83 */
84 #define FDT_MAX_SIZE 0x100000
85 #define RTAS_MAX_SIZE 0x10000
86 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
87 #define FW_MAX_SIZE 0x400000
88 #define FW_FILE_NAME "slof.bin"
89 #define FW_OVERHEAD 0x2800000
90 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
91
92 #define MIN_RMA_SLOF 128UL
93
94 #define PHANDLE_XICP 0x00001111
95
96 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
97
98 static XICSState *try_create_xics(const char *type, int nr_servers,
99 int nr_irqs, Error **errp)
100 {
101 Error *err = NULL;
102 DeviceState *dev;
103
104 dev = qdev_create(NULL, type);
105 qdev_prop_set_uint32(dev, "nr_servers", nr_servers);
106 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs);
107 object_property_set_bool(OBJECT(dev), true, "realized", &err);
108 if (err) {
109 error_propagate(errp, err);
110 object_unparent(OBJECT(dev));
111 return NULL;
112 }
113 return XICS_COMMON(dev);
114 }
115
116 static XICSState *xics_system_init(MachineState *machine,
117 int nr_servers, int nr_irqs, Error **errp)
118 {
119 XICSState *xics = NULL;
120
121 if (kvm_enabled()) {
122 Error *err = NULL;
123
124 if (machine_kernel_irqchip_allowed(machine)) {
125 xics = try_create_xics(TYPE_XICS_SPAPR_KVM, nr_servers, nr_irqs,
126 &err);
127 }
128 if (machine_kernel_irqchip_required(machine) && !xics) {
129 error_reportf_err(err,
130 "kernel_irqchip requested but unavailable: ");
131 } else {
132 error_free(err);
133 }
134 }
135
136 if (!xics) {
137 xics = try_create_xics(TYPE_XICS_SPAPR, nr_servers, nr_irqs, errp);
138 }
139
140 return xics;
141 }
142
143 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
144 int smt_threads)
145 {
146 int i, ret = 0;
147 uint32_t servers_prop[smt_threads];
148 uint32_t gservers_prop[smt_threads * 2];
149 int index = ppc_get_vcpu_dt_id(cpu);
150
151 if (cpu->cpu_version) {
152 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version);
153 if (ret < 0) {
154 return ret;
155 }
156 }
157
158 /* Build interrupt servers and gservers properties */
159 for (i = 0; i < smt_threads; i++) {
160 servers_prop[i] = cpu_to_be32(index + i);
161 /* Hack, direct the group queues back to cpu 0 */
162 gservers_prop[i*2] = cpu_to_be32(index + i);
163 gservers_prop[i*2 + 1] = 0;
164 }
165 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
166 servers_prop, sizeof(servers_prop));
167 if (ret < 0) {
168 return ret;
169 }
170 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
171 gservers_prop, sizeof(gservers_prop));
172
173 return ret;
174 }
175
176 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs)
177 {
178 int ret = 0;
179 PowerPCCPU *cpu = POWERPC_CPU(cs);
180 int index = ppc_get_vcpu_dt_id(cpu);
181 uint32_t associativity[] = {cpu_to_be32(0x5),
182 cpu_to_be32(0x0),
183 cpu_to_be32(0x0),
184 cpu_to_be32(0x0),
185 cpu_to_be32(cs->numa_node),
186 cpu_to_be32(index)};
187
188 /* Advertise NUMA via ibm,associativity */
189 if (nb_numa_nodes > 1) {
190 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity,
191 sizeof(associativity));
192 }
193
194 return ret;
195 }
196
197 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
198 {
199 int ret = 0, offset, cpus_offset;
200 CPUState *cs;
201 char cpu_model[32];
202 int smt = kvmppc_smt_threads();
203 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
204
205 CPU_FOREACH(cs) {
206 PowerPCCPU *cpu = POWERPC_CPU(cs);
207 DeviceClass *dc = DEVICE_GET_CLASS(cs);
208 int index = ppc_get_vcpu_dt_id(cpu);
209
210 if ((index % smt) != 0) {
211 continue;
212 }
213
214 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
215
216 cpus_offset = fdt_path_offset(fdt, "/cpus");
217 if (cpus_offset < 0) {
218 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
219 "cpus");
220 if (cpus_offset < 0) {
221 return cpus_offset;
222 }
223 }
224 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
225 if (offset < 0) {
226 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
227 if (offset < 0) {
228 return offset;
229 }
230 }
231
232 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
233 pft_size_prop, sizeof(pft_size_prop));
234 if (ret < 0) {
235 return ret;
236 }
237
238 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs);
239 if (ret < 0) {
240 return ret;
241 }
242
243 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
244 ppc_get_compat_smt_threads(cpu));
245 if (ret < 0) {
246 return ret;
247 }
248 }
249 return ret;
250 }
251
252
253 static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop,
254 size_t maxsize)
255 {
256 size_t maxcells = maxsize / sizeof(uint32_t);
257 int i, j, count;
258 uint32_t *p = prop;
259
260 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
261 struct ppc_one_seg_page_size *sps = &env->sps.sps[i];
262
263 if (!sps->page_shift) {
264 break;
265 }
266 for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) {
267 if (sps->enc[count].page_shift == 0) {
268 break;
269 }
270 }
271 if ((p - prop) >= (maxcells - 3 - count * 2)) {
272 break;
273 }
274 *(p++) = cpu_to_be32(sps->page_shift);
275 *(p++) = cpu_to_be32(sps->slb_enc);
276 *(p++) = cpu_to_be32(count);
277 for (j = 0; j < count; j++) {
278 *(p++) = cpu_to_be32(sps->enc[j].page_shift);
279 *(p++) = cpu_to_be32(sps->enc[j].pte_enc);
280 }
281 }
282
283 return (p - prop) * sizeof(uint32_t);
284 }
285
286 static hwaddr spapr_node0_size(void)
287 {
288 MachineState *machine = MACHINE(qdev_get_machine());
289
290 if (nb_numa_nodes) {
291 int i;
292 for (i = 0; i < nb_numa_nodes; ++i) {
293 if (numa_info[i].node_mem) {
294 return MIN(pow2floor(numa_info[i].node_mem),
295 machine->ram_size);
296 }
297 }
298 }
299 return machine->ram_size;
300 }
301
302 #define _FDT(exp) \
303 do { \
304 int ret = (exp); \
305 if (ret < 0) { \
306 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
307 #exp, fdt_strerror(ret)); \
308 exit(1); \
309 } \
310 } while (0)
311
312 static void add_str(GString *s, const gchar *s1)
313 {
314 g_string_append_len(s, s1, strlen(s1) + 1);
315 }
316
317 static void *spapr_create_fdt_skel(hwaddr initrd_base,
318 hwaddr initrd_size,
319 hwaddr kernel_size,
320 bool little_endian,
321 const char *kernel_cmdline,
322 uint32_t epow_irq)
323 {
324 void *fdt;
325 uint32_t start_prop = cpu_to_be32(initrd_base);
326 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size);
327 GString *hypertas = g_string_sized_new(256);
328 GString *qemu_hypertas = g_string_sized_new(256);
329 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)};
330 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(max_cpus)};
331 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80};
332 char *buf;
333
334 add_str(hypertas, "hcall-pft");
335 add_str(hypertas, "hcall-term");
336 add_str(hypertas, "hcall-dabr");
337 add_str(hypertas, "hcall-interrupt");
338 add_str(hypertas, "hcall-tce");
339 add_str(hypertas, "hcall-vio");
340 add_str(hypertas, "hcall-splpar");
341 add_str(hypertas, "hcall-bulk");
342 add_str(hypertas, "hcall-set-mode");
343 add_str(hypertas, "hcall-sprg0");
344 add_str(hypertas, "hcall-copy");
345 add_str(hypertas, "hcall-debug");
346 add_str(qemu_hypertas, "hcall-memop1");
347
348 fdt = g_malloc0(FDT_MAX_SIZE);
349 _FDT((fdt_create(fdt, FDT_MAX_SIZE)));
350
351 if (kernel_size) {
352 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size)));
353 }
354 if (initrd_size) {
355 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size)));
356 }
357 _FDT((fdt_finish_reservemap(fdt)));
358
359 /* Root node */
360 _FDT((fdt_begin_node(fdt, "")));
361 _FDT((fdt_property_string(fdt, "device_type", "chrp")));
362 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)")));
363 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries")));
364
365 /*
366 * Add info to guest to indentify which host is it being run on
367 * and what is the uuid of the guest
368 */
369 if (kvmppc_get_host_model(&buf)) {
370 _FDT((fdt_property_string(fdt, "host-model", buf)));
371 g_free(buf);
372 }
373 if (kvmppc_get_host_serial(&buf)) {
374 _FDT((fdt_property_string(fdt, "host-serial", buf)));
375 g_free(buf);
376 }
377
378 buf = g_strdup_printf(UUID_FMT, qemu_uuid[0], qemu_uuid[1],
379 qemu_uuid[2], qemu_uuid[3], qemu_uuid[4],
380 qemu_uuid[5], qemu_uuid[6], qemu_uuid[7],
381 qemu_uuid[8], qemu_uuid[9], qemu_uuid[10],
382 qemu_uuid[11], qemu_uuid[12], qemu_uuid[13],
383 qemu_uuid[14], qemu_uuid[15]);
384
385 _FDT((fdt_property_string(fdt, "vm,uuid", buf)));
386 if (qemu_uuid_set) {
387 _FDT((fdt_property_string(fdt, "system-id", buf)));
388 }
389 g_free(buf);
390
391 if (qemu_get_vm_name()) {
392 _FDT((fdt_property_string(fdt, "ibm,partition-name",
393 qemu_get_vm_name())));
394 }
395
396 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2)));
397 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2)));
398
399 /* /chosen */
400 _FDT((fdt_begin_node(fdt, "chosen")));
401
402 /* Set Form1_affinity */
403 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5))));
404
405 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline)));
406 _FDT((fdt_property(fdt, "linux,initrd-start",
407 &start_prop, sizeof(start_prop))));
408 _FDT((fdt_property(fdt, "linux,initrd-end",
409 &end_prop, sizeof(end_prop))));
410 if (kernel_size) {
411 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
412 cpu_to_be64(kernel_size) };
413
414 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop))));
415 if (little_endian) {
416 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0)));
417 }
418 }
419 if (boot_menu) {
420 _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu)));
421 }
422 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width)));
423 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height)));
424 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth)));
425
426 _FDT((fdt_end_node(fdt)));
427
428 /* RTAS */
429 _FDT((fdt_begin_node(fdt, "rtas")));
430
431 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
432 add_str(hypertas, "hcall-multi-tce");
433 }
434 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str,
435 hypertas->len)));
436 g_string_free(hypertas, TRUE);
437 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str,
438 qemu_hypertas->len)));
439 g_string_free(qemu_hypertas, TRUE);
440
441 _FDT((fdt_property(fdt, "ibm,associativity-reference-points",
442 refpoints, sizeof(refpoints))));
443
444 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX)));
445 _FDT((fdt_property_cell(fdt, "rtas-event-scan-rate",
446 RTAS_EVENT_SCAN_RATE)));
447
448 if (msi_nonbroken) {
449 _FDT((fdt_property(fdt, "ibm,change-msix-capable", NULL, 0)));
450 }
451
452 /*
453 * According to PAPR, rtas ibm,os-term does not guarantee a return
454 * back to the guest cpu.
455 *
456 * While an additional ibm,extended-os-term property indicates that
457 * rtas call return will always occur. Set this property.
458 */
459 _FDT((fdt_property(fdt, "ibm,extended-os-term", NULL, 0)));
460
461 _FDT((fdt_end_node(fdt)));
462
463 /* interrupt controller */
464 _FDT((fdt_begin_node(fdt, "interrupt-controller")));
465
466 _FDT((fdt_property_string(fdt, "device_type",
467 "PowerPC-External-Interrupt-Presentation")));
468 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp")));
469 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
470 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",
471 interrupt_server_ranges_prop,
472 sizeof(interrupt_server_ranges_prop))));
473 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2)));
474 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP)));
475 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP)));
476
477 _FDT((fdt_end_node(fdt)));
478
479 /* vdevice */
480 _FDT((fdt_begin_node(fdt, "vdevice")));
481
482 _FDT((fdt_property_string(fdt, "device_type", "vdevice")));
483 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice")));
484 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
485 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
486 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2)));
487 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
488
489 _FDT((fdt_end_node(fdt)));
490
491 /* event-sources */
492 spapr_events_fdt_skel(fdt, epow_irq);
493
494 /* /hypervisor node */
495 if (kvm_enabled()) {
496 uint8_t hypercall[16];
497
498 /* indicate KVM hypercall interface */
499 _FDT((fdt_begin_node(fdt, "hypervisor")));
500 _FDT((fdt_property_string(fdt, "compatible", "linux,kvm")));
501 if (kvmppc_has_cap_fixup_hcalls()) {
502 /*
503 * Older KVM versions with older guest kernels were broken with the
504 * magic page, don't allow the guest to map it.
505 */
506 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
507 sizeof(hypercall))) {
508 _FDT((fdt_property(fdt, "hcall-instructions", hypercall,
509 sizeof(hypercall))));
510 }
511 }
512 _FDT((fdt_end_node(fdt)));
513 }
514
515 _FDT((fdt_end_node(fdt))); /* close root node */
516 _FDT((fdt_finish(fdt)));
517
518 return fdt;
519 }
520
521 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
522 hwaddr size)
523 {
524 uint32_t associativity[] = {
525 cpu_to_be32(0x4), /* length */
526 cpu_to_be32(0x0), cpu_to_be32(0x0),
527 cpu_to_be32(0x0), cpu_to_be32(nodeid)
528 };
529 char mem_name[32];
530 uint64_t mem_reg_property[2];
531 int off;
532
533 mem_reg_property[0] = cpu_to_be64(start);
534 mem_reg_property[1] = cpu_to_be64(size);
535
536 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
537 off = fdt_add_subnode(fdt, 0, mem_name);
538 _FDT(off);
539 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
540 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
541 sizeof(mem_reg_property))));
542 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
543 sizeof(associativity))));
544 return off;
545 }
546
547 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt)
548 {
549 MachineState *machine = MACHINE(spapr);
550 hwaddr mem_start, node_size;
551 int i, nb_nodes = nb_numa_nodes;
552 NodeInfo *nodes = numa_info;
553 NodeInfo ramnode;
554
555 /* No NUMA nodes, assume there is just one node with whole RAM */
556 if (!nb_numa_nodes) {
557 nb_nodes = 1;
558 ramnode.node_mem = machine->ram_size;
559 nodes = &ramnode;
560 }
561
562 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
563 if (!nodes[i].node_mem) {
564 continue;
565 }
566 if (mem_start >= machine->ram_size) {
567 node_size = 0;
568 } else {
569 node_size = nodes[i].node_mem;
570 if (node_size > machine->ram_size - mem_start) {
571 node_size = machine->ram_size - mem_start;
572 }
573 }
574 if (!mem_start) {
575 /* ppc_spapr_init() checks for rma_size <= node0_size already */
576 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
577 mem_start += spapr->rma_size;
578 node_size -= spapr->rma_size;
579 }
580 for ( ; node_size; ) {
581 hwaddr sizetmp = pow2floor(node_size);
582
583 /* mem_start != 0 here */
584 if (ctzl(mem_start) < ctzl(sizetmp)) {
585 sizetmp = 1ULL << ctzl(mem_start);
586 }
587
588 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
589 node_size -= sizetmp;
590 mem_start += sizetmp;
591 }
592 }
593
594 return 0;
595 }
596
597 /* Populate the "ibm,pa-features" property */
598 static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset)
599 {
600 uint8_t pa_features_206[] = { 6, 0,
601 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
602 uint8_t pa_features_207[] = { 24, 0,
603 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
604 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
605 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
606 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
607 uint8_t *pa_features;
608 size_t pa_size;
609
610 switch (env->mmu_model) {
611 case POWERPC_MMU_2_06:
612 case POWERPC_MMU_2_06a:
613 pa_features = pa_features_206;
614 pa_size = sizeof(pa_features_206);
615 break;
616 case POWERPC_MMU_2_07:
617 case POWERPC_MMU_2_07a:
618 pa_features = pa_features_207;
619 pa_size = sizeof(pa_features_207);
620 break;
621 default:
622 return;
623 }
624
625 if (env->ci_large_pages) {
626 /*
627 * Note: we keep CI large pages off by default because a 64K capable
628 * guest provisioned with large pages might otherwise try to map a qemu
629 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
630 * even if that qemu runs on a 4k host.
631 * We dd this bit back here if we are confident this is not an issue
632 */
633 pa_features[3] |= 0x20;
634 }
635 if (kvmppc_has_cap_htm() && pa_size > 24) {
636 pa_features[24] |= 0x80; /* Transactional memory support */
637 }
638
639 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
640 }
641
642 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
643 sPAPRMachineState *spapr)
644 {
645 PowerPCCPU *cpu = POWERPC_CPU(cs);
646 CPUPPCState *env = &cpu->env;
647 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
648 int index = ppc_get_vcpu_dt_id(cpu);
649 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
650 0xffffffff, 0xffffffff};
651 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
652 : SPAPR_TIMEBASE_FREQ;
653 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
654 uint32_t page_sizes_prop[64];
655 size_t page_sizes_prop_size;
656 uint32_t vcpus_per_socket = smp_threads * smp_cores;
657 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
658 sPAPRDRConnector *drc;
659 sPAPRDRConnectorClass *drck;
660 int drc_index;
661
662 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index);
663 if (drc) {
664 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
665 drc_index = drck->get_index(drc);
666 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
667 }
668
669 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
670 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
671
672 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
673 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
674 env->dcache_line_size)));
675 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
676 env->dcache_line_size)));
677 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
678 env->icache_line_size)));
679 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
680 env->icache_line_size)));
681
682 if (pcc->l1_dcache_size) {
683 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
684 pcc->l1_dcache_size)));
685 } else {
686 fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n");
687 }
688 if (pcc->l1_icache_size) {
689 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
690 pcc->l1_icache_size)));
691 } else {
692 fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n");
693 }
694
695 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
696 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
697 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr)));
698 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
699 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
700 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
701
702 if (env->spr_cb[SPR_PURR].oea_read) {
703 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
704 }
705
706 if (env->mmu_model & POWERPC_MMU_1TSEG) {
707 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
708 segs, sizeof(segs))));
709 }
710
711 /* Advertise VMX/VSX (vector extensions) if available
712 * 0 / no property == no vector extensions
713 * 1 == VMX / Altivec available
714 * 2 == VSX available */
715 if (env->insns_flags & PPC_ALTIVEC) {
716 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
717
718 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
719 }
720
721 /* Advertise DFP (Decimal Floating Point) if available
722 * 0 / no property == no DFP
723 * 1 == DFP available */
724 if (env->insns_flags2 & PPC2_DFP) {
725 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
726 }
727
728 page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop,
729 sizeof(page_sizes_prop));
730 if (page_sizes_prop_size) {
731 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
732 page_sizes_prop, page_sizes_prop_size)));
733 }
734
735 spapr_populate_pa_features(env, fdt, offset);
736
737 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
738 cs->cpu_index / vcpus_per_socket)));
739
740 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
741 pft_size_prop, sizeof(pft_size_prop))));
742
743 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs));
744
745 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
746 ppc_get_compat_smt_threads(cpu)));
747 }
748
749 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
750 {
751 CPUState *cs;
752 int cpus_offset;
753 char *nodename;
754 int smt = kvmppc_smt_threads();
755
756 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
757 _FDT(cpus_offset);
758 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
759 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
760
761 /*
762 * We walk the CPUs in reverse order to ensure that CPU DT nodes
763 * created by fdt_add_subnode() end up in the right order in FDT
764 * for the guest kernel the enumerate the CPUs correctly.
765 */
766 CPU_FOREACH_REVERSE(cs) {
767 PowerPCCPU *cpu = POWERPC_CPU(cs);
768 int index = ppc_get_vcpu_dt_id(cpu);
769 DeviceClass *dc = DEVICE_GET_CLASS(cs);
770 int offset;
771
772 if ((index % smt) != 0) {
773 continue;
774 }
775
776 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
777 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
778 g_free(nodename);
779 _FDT(offset);
780 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
781 }
782
783 }
784
785 /*
786 * Adds ibm,dynamic-reconfiguration-memory node.
787 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
788 * of this device tree node.
789 */
790 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
791 {
792 MachineState *machine = MACHINE(spapr);
793 int ret, i, offset;
794 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
795 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
796 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size;
797 uint32_t nr_lmbs = (spapr->hotplug_memory.base +
798 memory_region_size(&spapr->hotplug_memory.mr)) /
799 lmb_size;
800 uint32_t *int_buf, *cur_index, buf_len;
801 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
802
803 /*
804 * Don't create the node if there is no hotpluggable memory
805 */
806 if (machine->ram_size == machine->maxram_size) {
807 return 0;
808 }
809
810 /*
811 * Allocate enough buffer size to fit in ibm,dynamic-memory
812 * or ibm,associativity-lookup-arrays
813 */
814 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2)
815 * sizeof(uint32_t);
816 cur_index = int_buf = g_malloc0(buf_len);
817
818 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
819
820 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
821 sizeof(prop_lmb_size));
822 if (ret < 0) {
823 goto out;
824 }
825
826 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
827 if (ret < 0) {
828 goto out;
829 }
830
831 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
832 if (ret < 0) {
833 goto out;
834 }
835
836 /* ibm,dynamic-memory */
837 int_buf[0] = cpu_to_be32(nr_lmbs);
838 cur_index++;
839 for (i = 0; i < nr_lmbs; i++) {
840 uint64_t addr = i * lmb_size;
841 uint32_t *dynamic_memory = cur_index;
842
843 if (i >= hotplug_lmb_start) {
844 sPAPRDRConnector *drc;
845 sPAPRDRConnectorClass *drck;
846
847 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i);
848 g_assert(drc);
849 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
850
851 dynamic_memory[0] = cpu_to_be32(addr >> 32);
852 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
853 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc));
854 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
855 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL));
856 if (memory_region_present(get_system_memory(), addr)) {
857 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
858 } else {
859 dynamic_memory[5] = cpu_to_be32(0);
860 }
861 } else {
862 /*
863 * LMB information for RMA, boot time RAM and gap b/n RAM and
864 * hotplug memory region -- all these are marked as reserved
865 * and as having no valid DRC.
866 */
867 dynamic_memory[0] = cpu_to_be32(addr >> 32);
868 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
869 dynamic_memory[2] = cpu_to_be32(0);
870 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
871 dynamic_memory[4] = cpu_to_be32(-1);
872 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
873 SPAPR_LMB_FLAGS_DRC_INVALID);
874 }
875
876 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
877 }
878 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
879 if (ret < 0) {
880 goto out;
881 }
882
883 /* ibm,associativity-lookup-arrays */
884 cur_index = int_buf;
885 int_buf[0] = cpu_to_be32(nr_nodes);
886 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
887 cur_index += 2;
888 for (i = 0; i < nr_nodes; i++) {
889 uint32_t associativity[] = {
890 cpu_to_be32(0x0),
891 cpu_to_be32(0x0),
892 cpu_to_be32(0x0),
893 cpu_to_be32(i)
894 };
895 memcpy(cur_index, associativity, sizeof(associativity));
896 cur_index += 4;
897 }
898 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
899 (cur_index - int_buf) * sizeof(uint32_t));
900 out:
901 g_free(int_buf);
902 return ret;
903 }
904
905 int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
906 target_ulong addr, target_ulong size,
907 bool cpu_update, bool memory_update)
908 {
909 void *fdt, *fdt_skel;
910 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
911 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
912
913 size -= sizeof(hdr);
914
915 /* Create sceleton */
916 fdt_skel = g_malloc0(size);
917 _FDT((fdt_create(fdt_skel, size)));
918 _FDT((fdt_begin_node(fdt_skel, "")));
919 _FDT((fdt_end_node(fdt_skel)));
920 _FDT((fdt_finish(fdt_skel)));
921 fdt = g_malloc0(size);
922 _FDT((fdt_open_into(fdt_skel, fdt, size)));
923 g_free(fdt_skel);
924
925 /* Fixup cpu nodes */
926 if (cpu_update) {
927 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
928 }
929
930 /* Generate ibm,dynamic-reconfiguration-memory node if required */
931 if (memory_update && smc->dr_lmb_enabled) {
932 _FDT((spapr_populate_drconf_memory(spapr, fdt)));
933 }
934
935 /* Pack resulting tree */
936 _FDT((fdt_pack(fdt)));
937
938 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
939 trace_spapr_cas_failed(size);
940 return -1;
941 }
942
943 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
944 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
945 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
946 g_free(fdt);
947
948 return 0;
949 }
950
951 static void spapr_finalize_fdt(sPAPRMachineState *spapr,
952 hwaddr fdt_addr,
953 hwaddr rtas_addr,
954 hwaddr rtas_size)
955 {
956 MachineState *machine = MACHINE(qdev_get_machine());
957 MachineClass *mc = MACHINE_GET_CLASS(machine);
958 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
959 const char *boot_device = machine->boot_order;
960 int ret, i;
961 size_t cb = 0;
962 char *bootlist;
963 void *fdt;
964 sPAPRPHBState *phb;
965
966 fdt = g_malloc(FDT_MAX_SIZE);
967
968 /* open out the base tree into a temp buffer for the final tweaks */
969 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE)));
970
971 ret = spapr_populate_memory(spapr, fdt);
972 if (ret < 0) {
973 fprintf(stderr, "couldn't setup memory nodes in fdt\n");
974 exit(1);
975 }
976
977 ret = spapr_populate_vdevice(spapr->vio_bus, fdt);
978 if (ret < 0) {
979 fprintf(stderr, "couldn't setup vio devices in fdt\n");
980 exit(1);
981 }
982
983 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
984 ret = spapr_rng_populate_dt(fdt);
985 if (ret < 0) {
986 fprintf(stderr, "could not set up rng device in the fdt\n");
987 exit(1);
988 }
989 }
990
991 QLIST_FOREACH(phb, &spapr->phbs, list) {
992 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
993 if (ret < 0) {
994 error_report("couldn't setup PCI devices in fdt");
995 exit(1);
996 }
997 }
998
999 /* RTAS */
1000 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size);
1001 if (ret < 0) {
1002 fprintf(stderr, "Couldn't set up RTAS device tree properties\n");
1003 }
1004
1005 /* cpus */
1006 spapr_populate_cpus_dt_node(fdt, spapr);
1007
1008 bootlist = get_boot_devices_list(&cb, true);
1009 if (cb && bootlist) {
1010 int offset = fdt_path_offset(fdt, "/chosen");
1011 if (offset < 0) {
1012 exit(1);
1013 }
1014 for (i = 0; i < cb; i++) {
1015 if (bootlist[i] == '\n') {
1016 bootlist[i] = ' ';
1017 }
1018
1019 }
1020 ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist);
1021 }
1022
1023 if (boot_device && strlen(boot_device)) {
1024 int offset = fdt_path_offset(fdt, "/chosen");
1025
1026 if (offset < 0) {
1027 exit(1);
1028 }
1029 fdt_setprop_string(fdt, offset, "qemu,boot-device", boot_device);
1030 }
1031
1032 if (!spapr->has_graphics) {
1033 spapr_populate_chosen_stdout(fdt, spapr->vio_bus);
1034 }
1035
1036 if (smc->dr_lmb_enabled) {
1037 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
1038 }
1039
1040 if (mc->query_hotpluggable_cpus) {
1041 int offset = fdt_path_offset(fdt, "/cpus");
1042 ret = spapr_drc_populate_dt(fdt, offset, NULL,
1043 SPAPR_DR_CONNECTOR_TYPE_CPU);
1044 if (ret < 0) {
1045 error_report("Couldn't set up CPU DR device tree properties");
1046 exit(1);
1047 }
1048 }
1049
1050 _FDT((fdt_pack(fdt)));
1051
1052 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
1053 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1054 fdt_totalsize(fdt), FDT_MAX_SIZE);
1055 exit(1);
1056 }
1057
1058 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
1059 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
1060
1061 g_free(bootlist);
1062 g_free(fdt);
1063 }
1064
1065 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1066 {
1067 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1068 }
1069
1070 static void emulate_spapr_hypercall(PowerPCCPU *cpu)
1071 {
1072 CPUPPCState *env = &cpu->env;
1073
1074 if (msr_pr) {
1075 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1076 env->gpr[3] = H_PRIVILEGE;
1077 } else {
1078 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1079 }
1080 }
1081
1082 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1083 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1084 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1085 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1086 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1087
1088 /*
1089 * Get the fd to access the kernel htab, re-opening it if necessary
1090 */
1091 static int get_htab_fd(sPAPRMachineState *spapr)
1092 {
1093 if (spapr->htab_fd >= 0) {
1094 return spapr->htab_fd;
1095 }
1096
1097 spapr->htab_fd = kvmppc_get_htab_fd(false);
1098 if (spapr->htab_fd < 0) {
1099 error_report("Unable to open fd for reading hash table from KVM: %s",
1100 strerror(errno));
1101 }
1102
1103 return spapr->htab_fd;
1104 }
1105
1106 static void close_htab_fd(sPAPRMachineState *spapr)
1107 {
1108 if (spapr->htab_fd >= 0) {
1109 close(spapr->htab_fd);
1110 }
1111 spapr->htab_fd = -1;
1112 }
1113
1114 static int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1115 {
1116 int shift;
1117
1118 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1119 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1120 * that's much more than is needed for Linux guests */
1121 shift = ctz64(pow2ceil(ramsize)) - 7;
1122 shift = MAX(shift, 18); /* Minimum architected size */
1123 shift = MIN(shift, 46); /* Maximum architected size */
1124 return shift;
1125 }
1126
1127 static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
1128 Error **errp)
1129 {
1130 long rc;
1131
1132 /* Clean up any HPT info from a previous boot */
1133 g_free(spapr->htab);
1134 spapr->htab = NULL;
1135 spapr->htab_shift = 0;
1136 close_htab_fd(spapr);
1137
1138 rc = kvmppc_reset_htab(shift);
1139 if (rc < 0) {
1140 /* kernel-side HPT needed, but couldn't allocate one */
1141 error_setg_errno(errp, errno,
1142 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1143 shift);
1144 /* This is almost certainly fatal, but if the caller really
1145 * wants to carry on with shift == 0, it's welcome to try */
1146 } else if (rc > 0) {
1147 /* kernel-side HPT allocated */
1148 if (rc != shift) {
1149 error_setg(errp,
1150 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1151 shift, rc);
1152 }
1153
1154 spapr->htab_shift = shift;
1155 spapr->htab = NULL;
1156 } else {
1157 /* kernel-side HPT not needed, allocate in userspace instead */
1158 size_t size = 1ULL << shift;
1159 int i;
1160
1161 spapr->htab = qemu_memalign(size, size);
1162 if (!spapr->htab) {
1163 error_setg_errno(errp, errno,
1164 "Could not allocate HPT of order %d", shift);
1165 return;
1166 }
1167
1168 memset(spapr->htab, 0, size);
1169 spapr->htab_shift = shift;
1170
1171 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1172 DIRTY_HPTE(HPTE(spapr->htab, i));
1173 }
1174 }
1175 }
1176
1177 static int find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque)
1178 {
1179 bool matched = false;
1180
1181 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
1182 matched = true;
1183 }
1184
1185 if (!matched) {
1186 error_report("Device %s is not supported by this machine yet.",
1187 qdev_fw_name(DEVICE(sbdev)));
1188 exit(1);
1189 }
1190
1191 return 0;
1192 }
1193
1194 static void ppc_spapr_reset(void)
1195 {
1196 MachineState *machine = MACHINE(qdev_get_machine());
1197 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1198 PowerPCCPU *first_ppc_cpu;
1199 uint32_t rtas_limit;
1200
1201 /* Check for unknown sysbus devices */
1202 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL);
1203
1204 /* Allocate and/or reset the hash page table */
1205 spapr_reallocate_hpt(spapr,
1206 spapr_hpt_shift_for_ramsize(machine->maxram_size),
1207 &error_fatal);
1208
1209 /* Update the RMA size if necessary */
1210 if (spapr->vrma_adjust) {
1211 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(),
1212 spapr->htab_shift);
1213 }
1214
1215 qemu_devices_reset();
1216
1217 /*
1218 * We place the device tree and RTAS just below either the top of the RMA,
1219 * or just below 2GB, whichever is lowere, so that it can be
1220 * processed with 32-bit real mode code if necessary
1221 */
1222 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1223 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1224 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE;
1225
1226 /* Load the fdt */
1227 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr,
1228 spapr->rtas_size);
1229
1230 /* Copy RTAS over */
1231 cpu_physical_memory_write(spapr->rtas_addr, spapr->rtas_blob,
1232 spapr->rtas_size);
1233
1234 /* Set up the entry state */
1235 first_ppc_cpu = POWERPC_CPU(first_cpu);
1236 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr;
1237 first_ppc_cpu->env.gpr[5] = 0;
1238 first_cpu->halted = 0;
1239 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT;
1240
1241 }
1242
1243 static void spapr_create_nvram(sPAPRMachineState *spapr)
1244 {
1245 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
1246 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1247
1248 if (dinfo) {
1249 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1250 &error_fatal);
1251 }
1252
1253 qdev_init_nofail(dev);
1254
1255 spapr->nvram = (struct sPAPRNVRAM *)dev;
1256 }
1257
1258 static void spapr_rtc_create(sPAPRMachineState *spapr)
1259 {
1260 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC);
1261
1262 qdev_init_nofail(dev);
1263 spapr->rtc = dev;
1264
1265 object_property_add_alias(qdev_get_machine(), "rtc-time",
1266 OBJECT(spapr->rtc), "date", NULL);
1267 }
1268
1269 /* Returns whether we want to use VGA or not */
1270 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1271 {
1272 switch (vga_interface_type) {
1273 case VGA_NONE:
1274 return false;
1275 case VGA_DEVICE:
1276 return true;
1277 case VGA_STD:
1278 case VGA_VIRTIO:
1279 return pci_vga_init(pci_bus) != NULL;
1280 default:
1281 error_setg(errp,
1282 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1283 return false;
1284 }
1285 }
1286
1287 static int spapr_post_load(void *opaque, int version_id)
1288 {
1289 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1290 int err = 0;
1291
1292 /* In earlier versions, there was no separate qdev for the PAPR
1293 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1294 * So when migrating from those versions, poke the incoming offset
1295 * value into the RTC device */
1296 if (version_id < 3) {
1297 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset);
1298 }
1299
1300 return err;
1301 }
1302
1303 static bool version_before_3(void *opaque, int version_id)
1304 {
1305 return version_id < 3;
1306 }
1307
1308 static const VMStateDescription vmstate_spapr = {
1309 .name = "spapr",
1310 .version_id = 3,
1311 .minimum_version_id = 1,
1312 .post_load = spapr_post_load,
1313 .fields = (VMStateField[]) {
1314 /* used to be @next_irq */
1315 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
1316
1317 /* RTC offset */
1318 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3),
1319
1320 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2),
1321 VMSTATE_END_OF_LIST()
1322 },
1323 };
1324
1325 static int htab_save_setup(QEMUFile *f, void *opaque)
1326 {
1327 sPAPRMachineState *spapr = opaque;
1328
1329 /* "Iteration" header */
1330 qemu_put_be32(f, spapr->htab_shift);
1331
1332 if (spapr->htab) {
1333 spapr->htab_save_index = 0;
1334 spapr->htab_first_pass = true;
1335 } else {
1336 assert(kvm_enabled());
1337 }
1338
1339
1340 return 0;
1341 }
1342
1343 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr,
1344 int64_t max_ns)
1345 {
1346 bool has_timeout = max_ns != -1;
1347 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1348 int index = spapr->htab_save_index;
1349 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1350
1351 assert(spapr->htab_first_pass);
1352
1353 do {
1354 int chunkstart;
1355
1356 /* Consume invalid HPTEs */
1357 while ((index < htabslots)
1358 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1359 index++;
1360 CLEAN_HPTE(HPTE(spapr->htab, index));
1361 }
1362
1363 /* Consume valid HPTEs */
1364 chunkstart = index;
1365 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1366 && HPTE_VALID(HPTE(spapr->htab, index))) {
1367 index++;
1368 CLEAN_HPTE(HPTE(spapr->htab, index));
1369 }
1370
1371 if (index > chunkstart) {
1372 int n_valid = index - chunkstart;
1373
1374 qemu_put_be32(f, chunkstart);
1375 qemu_put_be16(f, n_valid);
1376 qemu_put_be16(f, 0);
1377 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1378 HASH_PTE_SIZE_64 * n_valid);
1379
1380 if (has_timeout &&
1381 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1382 break;
1383 }
1384 }
1385 } while ((index < htabslots) && !qemu_file_rate_limit(f));
1386
1387 if (index >= htabslots) {
1388 assert(index == htabslots);
1389 index = 0;
1390 spapr->htab_first_pass = false;
1391 }
1392 spapr->htab_save_index = index;
1393 }
1394
1395 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr,
1396 int64_t max_ns)
1397 {
1398 bool final = max_ns < 0;
1399 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1400 int examined = 0, sent = 0;
1401 int index = spapr->htab_save_index;
1402 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1403
1404 assert(!spapr->htab_first_pass);
1405
1406 do {
1407 int chunkstart, invalidstart;
1408
1409 /* Consume non-dirty HPTEs */
1410 while ((index < htabslots)
1411 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
1412 index++;
1413 examined++;
1414 }
1415
1416 chunkstart = index;
1417 /* Consume valid dirty HPTEs */
1418 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1419 && HPTE_DIRTY(HPTE(spapr->htab, index))
1420 && HPTE_VALID(HPTE(spapr->htab, index))) {
1421 CLEAN_HPTE(HPTE(spapr->htab, index));
1422 index++;
1423 examined++;
1424 }
1425
1426 invalidstart = index;
1427 /* Consume invalid dirty HPTEs */
1428 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
1429 && HPTE_DIRTY(HPTE(spapr->htab, index))
1430 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1431 CLEAN_HPTE(HPTE(spapr->htab, index));
1432 index++;
1433 examined++;
1434 }
1435
1436 if (index > chunkstart) {
1437 int n_valid = invalidstart - chunkstart;
1438 int n_invalid = index - invalidstart;
1439
1440 qemu_put_be32(f, chunkstart);
1441 qemu_put_be16(f, n_valid);
1442 qemu_put_be16(f, n_invalid);
1443 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1444 HASH_PTE_SIZE_64 * n_valid);
1445 sent += index - chunkstart;
1446
1447 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1448 break;
1449 }
1450 }
1451
1452 if (examined >= htabslots) {
1453 break;
1454 }
1455
1456 if (index >= htabslots) {
1457 assert(index == htabslots);
1458 index = 0;
1459 }
1460 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
1461
1462 if (index >= htabslots) {
1463 assert(index == htabslots);
1464 index = 0;
1465 }
1466
1467 spapr->htab_save_index = index;
1468
1469 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
1470 }
1471
1472 #define MAX_ITERATION_NS 5000000 /* 5 ms */
1473 #define MAX_KVM_BUF_SIZE 2048
1474
1475 static int htab_save_iterate(QEMUFile *f, void *opaque)
1476 {
1477 sPAPRMachineState *spapr = opaque;
1478 int fd;
1479 int rc = 0;
1480
1481 /* Iteration header */
1482 qemu_put_be32(f, 0);
1483
1484 if (!spapr->htab) {
1485 assert(kvm_enabled());
1486
1487 fd = get_htab_fd(spapr);
1488 if (fd < 0) {
1489 return fd;
1490 }
1491
1492 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
1493 if (rc < 0) {
1494 return rc;
1495 }
1496 } else if (spapr->htab_first_pass) {
1497 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
1498 } else {
1499 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
1500 }
1501
1502 /* End marker */
1503 qemu_put_be32(f, 0);
1504 qemu_put_be16(f, 0);
1505 qemu_put_be16(f, 0);
1506
1507 return rc;
1508 }
1509
1510 static int htab_save_complete(QEMUFile *f, void *opaque)
1511 {
1512 sPAPRMachineState *spapr = opaque;
1513 int fd;
1514
1515 /* Iteration header */
1516 qemu_put_be32(f, 0);
1517
1518 if (!spapr->htab) {
1519 int rc;
1520
1521 assert(kvm_enabled());
1522
1523 fd = get_htab_fd(spapr);
1524 if (fd < 0) {
1525 return fd;
1526 }
1527
1528 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
1529 if (rc < 0) {
1530 return rc;
1531 }
1532 } else {
1533 if (spapr->htab_first_pass) {
1534 htab_save_first_pass(f, spapr, -1);
1535 }
1536 htab_save_later_pass(f, spapr, -1);
1537 }
1538
1539 /* End marker */
1540 qemu_put_be32(f, 0);
1541 qemu_put_be16(f, 0);
1542 qemu_put_be16(f, 0);
1543
1544 return 0;
1545 }
1546
1547 static int htab_load(QEMUFile *f, void *opaque, int version_id)
1548 {
1549 sPAPRMachineState *spapr = opaque;
1550 uint32_t section_hdr;
1551 int fd = -1;
1552
1553 if (version_id < 1 || version_id > 1) {
1554 error_report("htab_load() bad version");
1555 return -EINVAL;
1556 }
1557
1558 section_hdr = qemu_get_be32(f);
1559
1560 if (section_hdr) {
1561 Error *local_err = NULL;
1562
1563 /* First section gives the htab size */
1564 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
1565 if (local_err) {
1566 error_report_err(local_err);
1567 return -EINVAL;
1568 }
1569 return 0;
1570 }
1571
1572 if (!spapr->htab) {
1573 assert(kvm_enabled());
1574
1575 fd = kvmppc_get_htab_fd(true);
1576 if (fd < 0) {
1577 error_report("Unable to open fd to restore KVM hash table: %s",
1578 strerror(errno));
1579 }
1580 }
1581
1582 while (true) {
1583 uint32_t index;
1584 uint16_t n_valid, n_invalid;
1585
1586 index = qemu_get_be32(f);
1587 n_valid = qemu_get_be16(f);
1588 n_invalid = qemu_get_be16(f);
1589
1590 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
1591 /* End of Stream */
1592 break;
1593 }
1594
1595 if ((index + n_valid + n_invalid) >
1596 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
1597 /* Bad index in stream */
1598 error_report(
1599 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
1600 index, n_valid, n_invalid, spapr->htab_shift);
1601 return -EINVAL;
1602 }
1603
1604 if (spapr->htab) {
1605 if (n_valid) {
1606 qemu_get_buffer(f, HPTE(spapr->htab, index),
1607 HASH_PTE_SIZE_64 * n_valid);
1608 }
1609 if (n_invalid) {
1610 memset(HPTE(spapr->htab, index + n_valid), 0,
1611 HASH_PTE_SIZE_64 * n_invalid);
1612 }
1613 } else {
1614 int rc;
1615
1616 assert(fd >= 0);
1617
1618 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
1619 if (rc < 0) {
1620 return rc;
1621 }
1622 }
1623 }
1624
1625 if (!spapr->htab) {
1626 assert(fd >= 0);
1627 close(fd);
1628 }
1629
1630 return 0;
1631 }
1632
1633 static void htab_cleanup(void *opaque)
1634 {
1635 sPAPRMachineState *spapr = opaque;
1636
1637 close_htab_fd(spapr);
1638 }
1639
1640 static SaveVMHandlers savevm_htab_handlers = {
1641 .save_live_setup = htab_save_setup,
1642 .save_live_iterate = htab_save_iterate,
1643 .save_live_complete_precopy = htab_save_complete,
1644 .cleanup = htab_cleanup,
1645 .load_state = htab_load,
1646 };
1647
1648 static void spapr_boot_set(void *opaque, const char *boot_device,
1649 Error **errp)
1650 {
1651 MachineState *machine = MACHINE(qdev_get_machine());
1652 machine->boot_order = g_strdup(boot_device);
1653 }
1654
1655 /*
1656 * Reset routine for LMB DR devices.
1657 *
1658 * Unlike PCI DR devices, LMB DR devices explicitly register this reset
1659 * routine. Reset for PCI DR devices will be handled by PHB reset routine
1660 * when it walks all its children devices. LMB devices reset occurs
1661 * as part of spapr_ppc_reset().
1662 */
1663 static void spapr_drc_reset(void *opaque)
1664 {
1665 sPAPRDRConnector *drc = opaque;
1666 DeviceState *d = DEVICE(drc);
1667
1668 if (d) {
1669 device_reset(d);
1670 }
1671 }
1672
1673 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
1674 {
1675 MachineState *machine = MACHINE(spapr);
1676 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
1677 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
1678 int i;
1679
1680 for (i = 0; i < nr_lmbs; i++) {
1681 sPAPRDRConnector *drc;
1682 uint64_t addr;
1683
1684 addr = i * lmb_size + spapr->hotplug_memory.base;
1685 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB,
1686 addr/lmb_size);
1687 qemu_register_reset(spapr_drc_reset, drc);
1688 }
1689 }
1690
1691 /*
1692 * If RAM size, maxmem size and individual node mem sizes aren't aligned
1693 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
1694 * since we can't support such unaligned sizes with DRCONF_MEMORY.
1695 */
1696 static void spapr_validate_node_memory(MachineState *machine, Error **errp)
1697 {
1698 int i;
1699
1700 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1701 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
1702 " is not aligned to %llu MiB",
1703 machine->ram_size,
1704 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1705 return;
1706 }
1707
1708 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1709 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
1710 " is not aligned to %llu MiB",
1711 machine->ram_size,
1712 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1713 return;
1714 }
1715
1716 for (i = 0; i < nb_numa_nodes; i++) {
1717 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
1718 error_setg(errp,
1719 "Node %d memory size 0x%" PRIx64
1720 " is not aligned to %llu MiB",
1721 i, numa_info[i].node_mem,
1722 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1723 return;
1724 }
1725 }
1726 }
1727
1728 /* pSeries LPAR / sPAPR hardware init */
1729 static void ppc_spapr_init(MachineState *machine)
1730 {
1731 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1732 MachineClass *mc = MACHINE_GET_CLASS(machine);
1733 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1734 const char *kernel_filename = machine->kernel_filename;
1735 const char *kernel_cmdline = machine->kernel_cmdline;
1736 const char *initrd_filename = machine->initrd_filename;
1737 PCIHostState *phb;
1738 int i;
1739 MemoryRegion *sysmem = get_system_memory();
1740 MemoryRegion *ram = g_new(MemoryRegion, 1);
1741 MemoryRegion *rma_region;
1742 void *rma = NULL;
1743 hwaddr rma_alloc_size;
1744 hwaddr node0_size = spapr_node0_size();
1745 uint32_t initrd_base = 0;
1746 long kernel_size = 0, initrd_size = 0;
1747 long load_limit, fw_size;
1748 bool kernel_le = false;
1749 char *filename;
1750 int smt = kvmppc_smt_threads();
1751 int spapr_cores = smp_cpus / smp_threads;
1752 int spapr_max_cores = max_cpus / smp_threads;
1753
1754 if (mc->query_hotpluggable_cpus) {
1755 if (smp_cpus % smp_threads) {
1756 error_report("smp_cpus (%u) must be multiple of threads (%u)",
1757 smp_cpus, smp_threads);
1758 exit(1);
1759 }
1760 if (max_cpus % smp_threads) {
1761 error_report("max_cpus (%u) must be multiple of threads (%u)",
1762 max_cpus, smp_threads);
1763 exit(1);
1764 }
1765 }
1766
1767 msi_nonbroken = true;
1768
1769 QLIST_INIT(&spapr->phbs);
1770
1771 cpu_ppc_hypercall = emulate_spapr_hypercall;
1772
1773 /* Allocate RMA if necessary */
1774 rma_alloc_size = kvmppc_alloc_rma(&rma);
1775
1776 if (rma_alloc_size == -1) {
1777 error_report("Unable to create RMA");
1778 exit(1);
1779 }
1780
1781 if (rma_alloc_size && (rma_alloc_size < node0_size)) {
1782 spapr->rma_size = rma_alloc_size;
1783 } else {
1784 spapr->rma_size = node0_size;
1785
1786 /* With KVM, we don't actually know whether KVM supports an
1787 * unbounded RMA (PR KVM) or is limited by the hash table size
1788 * (HV KVM using VRMA), so we always assume the latter
1789 *
1790 * In that case, we also limit the initial allocations for RTAS
1791 * etc... to 256M since we have no way to know what the VRMA size
1792 * is going to be as it depends on the size of the hash table
1793 * isn't determined yet.
1794 */
1795 if (kvm_enabled()) {
1796 spapr->vrma_adjust = 1;
1797 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
1798 }
1799
1800 /* Actually we don't support unbounded RMA anymore since we
1801 * added proper emulation of HV mode. The max we can get is
1802 * 16G which also happens to be what we configure for PAPR
1803 * mode so make sure we don't do anything bigger than that
1804 */
1805 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull);
1806 }
1807
1808 if (spapr->rma_size > node0_size) {
1809 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
1810 spapr->rma_size);
1811 exit(1);
1812 }
1813
1814 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
1815 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
1816
1817 /* Set up Interrupt Controller before we create the VCPUs */
1818 spapr->xics = xics_system_init(machine,
1819 DIV_ROUND_UP(max_cpus * smt, smp_threads),
1820 XICS_IRQS_SPAPR, &error_fatal);
1821
1822 if (smc->dr_lmb_enabled) {
1823 spapr_validate_node_memory(machine, &error_fatal);
1824 }
1825
1826 /* init CPUs */
1827 if (machine->cpu_model == NULL) {
1828 machine->cpu_model = kvm_enabled() ? "host" : "POWER7";
1829 }
1830
1831 ppc_cpu_parse_features(machine->cpu_model);
1832
1833 if (mc->query_hotpluggable_cpus) {
1834 char *type = spapr_get_cpu_core_type(machine->cpu_model);
1835
1836 if (type == NULL) {
1837 error_report("Unable to find sPAPR CPU Core definition");
1838 exit(1);
1839 }
1840
1841 spapr->cores = g_new0(Object *, spapr_max_cores);
1842 for (i = 0; i < spapr_max_cores; i++) {
1843 int core_id = i * smp_threads;
1844 sPAPRDRConnector *drc =
1845 spapr_dr_connector_new(OBJECT(spapr),
1846 SPAPR_DR_CONNECTOR_TYPE_CPU,
1847 (core_id / smp_threads) * smt);
1848
1849 qemu_register_reset(spapr_drc_reset, drc);
1850
1851 if (i < spapr_cores) {
1852 Object *core = object_new(type);
1853 object_property_set_int(core, smp_threads, "nr-threads",
1854 &error_fatal);
1855 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
1856 &error_fatal);
1857 object_property_set_bool(core, true, "realized", &error_fatal);
1858 }
1859 }
1860 g_free(type);
1861 } else {
1862 for (i = 0; i < smp_cpus; i++) {
1863 PowerPCCPU *cpu = cpu_ppc_init(machine->cpu_model);
1864 if (cpu == NULL) {
1865 error_report("Unable to find PowerPC CPU definition");
1866 exit(1);
1867 }
1868 spapr_cpu_init(spapr, cpu, &error_fatal);
1869 }
1870 }
1871
1872 if (kvm_enabled()) {
1873 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
1874 kvmppc_enable_logical_ci_hcalls();
1875 kvmppc_enable_set_mode_hcall();
1876 }
1877
1878 /* allocate RAM */
1879 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
1880 machine->ram_size);
1881 memory_region_add_subregion(sysmem, 0, ram);
1882
1883 if (rma_alloc_size && rma) {
1884 rma_region = g_new(MemoryRegion, 1);
1885 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma",
1886 rma_alloc_size, rma);
1887 vmstate_register_ram_global(rma_region);
1888 memory_region_add_subregion(sysmem, 0, rma_region);
1889 }
1890
1891 /* initialize hotplug memory address space */
1892 if (machine->ram_size < machine->maxram_size) {
1893 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size;
1894 /*
1895 * Limit the number of hotpluggable memory slots to half the number
1896 * slots that KVM supports, leaving the other half for PCI and other
1897 * devices. However ensure that number of slots doesn't drop below 32.
1898 */
1899 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
1900 SPAPR_MAX_RAM_SLOTS;
1901
1902 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
1903 max_memslots = SPAPR_MAX_RAM_SLOTS;
1904 }
1905 if (machine->ram_slots > max_memslots) {
1906 error_report("Specified number of memory slots %"
1907 PRIu64" exceeds max supported %d",
1908 machine->ram_slots, max_memslots);
1909 exit(1);
1910 }
1911
1912 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size,
1913 SPAPR_HOTPLUG_MEM_ALIGN);
1914 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr),
1915 "hotplug-memory", hotplug_mem_size);
1916 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base,
1917 &spapr->hotplug_memory.mr);
1918 }
1919
1920 if (smc->dr_lmb_enabled) {
1921 spapr_create_lmb_dr_connectors(spapr);
1922 }
1923
1924 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
1925 if (!filename) {
1926 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
1927 exit(1);
1928 }
1929 spapr->rtas_size = get_image_size(filename);
1930 if (spapr->rtas_size < 0) {
1931 error_report("Could not get size of LPAR rtas '%s'", filename);
1932 exit(1);
1933 }
1934 spapr->rtas_blob = g_malloc(spapr->rtas_size);
1935 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
1936 error_report("Could not load LPAR rtas '%s'", filename);
1937 exit(1);
1938 }
1939 if (spapr->rtas_size > RTAS_MAX_SIZE) {
1940 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
1941 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
1942 exit(1);
1943 }
1944 g_free(filename);
1945
1946 /* Set up EPOW events infrastructure */
1947 spapr_events_init(spapr);
1948
1949 /* Set up the RTC RTAS interfaces */
1950 spapr_rtc_create(spapr);
1951
1952 /* Set up VIO bus */
1953 spapr->vio_bus = spapr_vio_bus_init();
1954
1955 for (i = 0; i < MAX_SERIAL_PORTS; i++) {
1956 if (serial_hds[i]) {
1957 spapr_vty_create(spapr->vio_bus, serial_hds[i]);
1958 }
1959 }
1960
1961 /* We always have at least the nvram device on VIO */
1962 spapr_create_nvram(spapr);
1963
1964 /* Set up PCI */
1965 spapr_pci_rtas_init();
1966
1967 phb = spapr_create_phb(spapr, 0);
1968
1969 for (i = 0; i < nb_nics; i++) {
1970 NICInfo *nd = &nd_table[i];
1971
1972 if (!nd->model) {
1973 nd->model = g_strdup("ibmveth");
1974 }
1975
1976 if (strcmp(nd->model, "ibmveth") == 0) {
1977 spapr_vlan_create(spapr->vio_bus, nd);
1978 } else {
1979 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
1980 }
1981 }
1982
1983 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
1984 spapr_vscsi_create(spapr->vio_bus);
1985 }
1986
1987 /* Graphics */
1988 if (spapr_vga_init(phb->bus, &error_fatal)) {
1989 spapr->has_graphics = true;
1990 machine->usb |= defaults_enabled() && !machine->usb_disabled;
1991 }
1992
1993 if (machine->usb) {
1994 if (smc->use_ohci_by_default) {
1995 pci_create_simple(phb->bus, -1, "pci-ohci");
1996 } else {
1997 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
1998 }
1999
2000 if (spapr->has_graphics) {
2001 USBBus *usb_bus = usb_bus_find(-1);
2002
2003 usb_create_simple(usb_bus, "usb-kbd");
2004 usb_create_simple(usb_bus, "usb-mouse");
2005 }
2006 }
2007
2008 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
2009 error_report(
2010 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
2011 MIN_RMA_SLOF);
2012 exit(1);
2013 }
2014
2015 if (kernel_filename) {
2016 uint64_t lowaddr = 0;
2017
2018 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
2019 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE,
2020 0, 0);
2021 if (kernel_size == ELF_LOAD_WRONG_ENDIAN) {
2022 kernel_size = load_elf(kernel_filename,
2023 translate_kernel_address, NULL,
2024 NULL, &lowaddr, NULL, 0, PPC_ELF_MACHINE,
2025 0, 0);
2026 kernel_le = kernel_size > 0;
2027 }
2028 if (kernel_size < 0) {
2029 error_report("error loading %s: %s",
2030 kernel_filename, load_elf_strerror(kernel_size));
2031 exit(1);
2032 }
2033
2034 /* load initrd */
2035 if (initrd_filename) {
2036 /* Try to locate the initrd in the gap between the kernel
2037 * and the firmware. Add a bit of space just in case
2038 */
2039 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff;
2040 initrd_size = load_image_targphys(initrd_filename, initrd_base,
2041 load_limit - initrd_base);
2042 if (initrd_size < 0) {
2043 error_report("could not load initial ram disk '%s'",
2044 initrd_filename);
2045 exit(1);
2046 }
2047 } else {
2048 initrd_base = 0;
2049 initrd_size = 0;
2050 }
2051 }
2052
2053 if (bios_name == NULL) {
2054 bios_name = FW_FILE_NAME;
2055 }
2056 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
2057 if (!filename) {
2058 error_report("Could not find LPAR firmware '%s'", bios_name);
2059 exit(1);
2060 }
2061 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
2062 if (fw_size <= 0) {
2063 error_report("Could not load LPAR firmware '%s'", filename);
2064 exit(1);
2065 }
2066 g_free(filename);
2067
2068 /* FIXME: Should register things through the MachineState's qdev
2069 * interface, this is a legacy from the sPAPREnvironment structure
2070 * which predated MachineState but had a similar function */
2071 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
2072 register_savevm_live(NULL, "spapr/htab", -1, 1,
2073 &savevm_htab_handlers, spapr);
2074
2075 /* Prepare the device tree */
2076 spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size,
2077 kernel_size, kernel_le,
2078 kernel_cmdline,
2079 spapr->check_exception_irq);
2080 assert(spapr->fdt_skel != NULL);
2081
2082 /* used by RTAS */
2083 QTAILQ_INIT(&spapr->ccs_list);
2084 qemu_register_reset(spapr_ccs_reset_hook, spapr);
2085
2086 qemu_register_boot_set(spapr_boot_set, spapr);
2087 }
2088
2089 static int spapr_kvm_type(const char *vm_type)
2090 {
2091 if (!vm_type) {
2092 return 0;
2093 }
2094
2095 if (!strcmp(vm_type, "HV")) {
2096 return 1;
2097 }
2098
2099 if (!strcmp(vm_type, "PR")) {
2100 return 2;
2101 }
2102
2103 error_report("Unknown kvm-type specified '%s'", vm_type);
2104 exit(1);
2105 }
2106
2107 /*
2108 * Implementation of an interface to adjust firmware path
2109 * for the bootindex property handling.
2110 */
2111 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
2112 DeviceState *dev)
2113 {
2114 #define CAST(type, obj, name) \
2115 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2116 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
2117 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
2118
2119 if (d) {
2120 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
2121 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
2122 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
2123
2124 if (spapr) {
2125 /*
2126 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
2127 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
2128 * in the top 16 bits of the 64-bit LUN
2129 */
2130 unsigned id = 0x8000 | (d->id << 8) | d->lun;
2131 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2132 (uint64_t)id << 48);
2133 } else if (virtio) {
2134 /*
2135 * We use SRP luns of the form 01000000 | (target << 8) | lun
2136 * in the top 32 bits of the 64-bit LUN
2137 * Note: the quote above is from SLOF and it is wrong,
2138 * the actual binding is:
2139 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
2140 */
2141 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
2142 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2143 (uint64_t)id << 32);
2144 } else if (usb) {
2145 /*
2146 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
2147 * in the top 32 bits of the 64-bit LUN
2148 */
2149 unsigned usb_port = atoi(usb->port->path);
2150 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
2151 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2152 (uint64_t)id << 32);
2153 }
2154 }
2155
2156 if (phb) {
2157 /* Replace "pci" with "pci@800000020000000" */
2158 return g_strdup_printf("pci@%"PRIX64, phb->buid);
2159 }
2160
2161 return NULL;
2162 }
2163
2164 static char *spapr_get_kvm_type(Object *obj, Error **errp)
2165 {
2166 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2167
2168 return g_strdup(spapr->kvm_type);
2169 }
2170
2171 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
2172 {
2173 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2174
2175 g_free(spapr->kvm_type);
2176 spapr->kvm_type = g_strdup(value);
2177 }
2178
2179 static void spapr_machine_initfn(Object *obj)
2180 {
2181 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2182
2183 spapr->htab_fd = -1;
2184 object_property_add_str(obj, "kvm-type",
2185 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
2186 object_property_set_description(obj, "kvm-type",
2187 "Specifies the KVM virtualization mode (HV, PR)",
2188 NULL);
2189 }
2190
2191 static void spapr_machine_finalizefn(Object *obj)
2192 {
2193 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2194
2195 g_free(spapr->kvm_type);
2196 }
2197
2198 static void ppc_cpu_do_nmi_on_cpu(void *arg)
2199 {
2200 CPUState *cs = arg;
2201
2202 cpu_synchronize_state(cs);
2203 ppc_cpu_do_system_reset(cs);
2204 }
2205
2206 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
2207 {
2208 CPUState *cs;
2209
2210 CPU_FOREACH(cs) {
2211 async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, cs);
2212 }
2213 }
2214
2215 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr, uint64_t size,
2216 uint32_t node, Error **errp)
2217 {
2218 sPAPRDRConnector *drc;
2219 sPAPRDRConnectorClass *drck;
2220 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
2221 int i, fdt_offset, fdt_size;
2222 void *fdt;
2223
2224 for (i = 0; i < nr_lmbs; i++) {
2225 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2226 addr/SPAPR_MEMORY_BLOCK_SIZE);
2227 g_assert(drc);
2228
2229 fdt = create_device_tree(&fdt_size);
2230 fdt_offset = spapr_populate_memory_node(fdt, node, addr,
2231 SPAPR_MEMORY_BLOCK_SIZE);
2232
2233 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2234 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp);
2235 addr += SPAPR_MEMORY_BLOCK_SIZE;
2236 }
2237 /* send hotplug notification to the
2238 * guest only in case of hotplugged memory
2239 */
2240 if (dev->hotplugged) {
2241 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, nr_lmbs);
2242 }
2243 }
2244
2245 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2246 uint32_t node, Error **errp)
2247 {
2248 Error *local_err = NULL;
2249 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
2250 PCDIMMDevice *dimm = PC_DIMM(dev);
2251 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2252 MemoryRegion *mr = ddc->get_memory_region(dimm);
2253 uint64_t align = memory_region_get_alignment(mr);
2254 uint64_t size = memory_region_size(mr);
2255 uint64_t addr;
2256
2257 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
2258 error_setg(&local_err, "Hotplugged memory size must be a multiple of "
2259 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE);
2260 goto out;
2261 }
2262
2263 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err);
2264 if (local_err) {
2265 goto out;
2266 }
2267
2268 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err);
2269 if (local_err) {
2270 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
2271 goto out;
2272 }
2273
2274 spapr_add_lmbs(dev, addr, size, node, &error_abort);
2275
2276 out:
2277 error_propagate(errp, local_err);
2278 }
2279
2280 void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
2281 sPAPRMachineState *spapr)
2282 {
2283 PowerPCCPU *cpu = POWERPC_CPU(cs);
2284 DeviceClass *dc = DEVICE_GET_CLASS(cs);
2285 int id = ppc_get_vcpu_dt_id(cpu);
2286 void *fdt;
2287 int offset, fdt_size;
2288 char *nodename;
2289
2290 fdt = create_device_tree(&fdt_size);
2291 nodename = g_strdup_printf("%s@%x", dc->fw_name, id);
2292 offset = fdt_add_subnode(fdt, 0, nodename);
2293
2294 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
2295 g_free(nodename);
2296
2297 *fdt_offset = offset;
2298 return fdt;
2299 }
2300
2301 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
2302 DeviceState *dev, Error **errp)
2303 {
2304 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
2305
2306 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2307 int node;
2308
2309 if (!smc->dr_lmb_enabled) {
2310 error_setg(errp, "Memory hotplug not supported for this machine");
2311 return;
2312 }
2313 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp);
2314 if (*errp) {
2315 return;
2316 }
2317 if (node < 0 || node >= MAX_NODES) {
2318 error_setg(errp, "Invaild node %d", node);
2319 return;
2320 }
2321
2322 /*
2323 * Currently PowerPC kernel doesn't allow hot-adding memory to
2324 * memory-less node, but instead will silently add the memory
2325 * to the first node that has some memory. This causes two
2326 * unexpected behaviours for the user.
2327 *
2328 * - Memory gets hotplugged to a different node than what the user
2329 * specified.
2330 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs
2331 * to memory-less node, a reboot will set things accordingly
2332 * and the previously hotplugged memory now ends in the right node.
2333 * This appears as if some memory moved from one node to another.
2334 *
2335 * So until kernel starts supporting memory hotplug to memory-less
2336 * nodes, just prevent such attempts upfront in QEMU.
2337 */
2338 if (nb_numa_nodes && !numa_info[node].node_mem) {
2339 error_setg(errp, "Can't hotplug memory to memory-less node %d",
2340 node);
2341 return;
2342 }
2343
2344 spapr_memory_plug(hotplug_dev, dev, node, errp);
2345 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2346 spapr_core_plug(hotplug_dev, dev, errp);
2347 }
2348 }
2349
2350 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev,
2351 DeviceState *dev, Error **errp)
2352 {
2353 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
2354
2355 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2356 error_setg(errp, "Memory hot unplug not supported by sPAPR");
2357 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2358 if (!mc->query_hotpluggable_cpus) {
2359 error_setg(errp, "CPU hot unplug not supported on this machine");
2360 return;
2361 }
2362 spapr_core_unplug(hotplug_dev, dev, errp);
2363 }
2364 }
2365
2366 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev,
2367 DeviceState *dev, Error **errp)
2368 {
2369 if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2370 spapr_core_pre_plug(hotplug_dev, dev, errp);
2371 }
2372 }
2373
2374 static HotplugHandler *spapr_get_hotpug_handler(MachineState *machine,
2375 DeviceState *dev)
2376 {
2377 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
2378 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2379 return HOTPLUG_HANDLER(machine);
2380 }
2381 return NULL;
2382 }
2383
2384 static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index)
2385 {
2386 /* Allocate to NUMA nodes on a "socket" basis (not that concept of
2387 * socket means much for the paravirtualized PAPR platform) */
2388 return cpu_index / smp_threads / smp_cores;
2389 }
2390
2391 static HotpluggableCPUList *spapr_query_hotpluggable_cpus(MachineState *machine)
2392 {
2393 int i;
2394 HotpluggableCPUList *head = NULL;
2395 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
2396 int spapr_max_cores = max_cpus / smp_threads;
2397
2398 for (i = 0; i < spapr_max_cores; i++) {
2399 HotpluggableCPUList *list_item = g_new0(typeof(*list_item), 1);
2400 HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1);
2401 CpuInstanceProperties *cpu_props = g_new0(typeof(*cpu_props), 1);
2402
2403 cpu_item->type = spapr_get_cpu_core_type(machine->cpu_model);
2404 cpu_item->vcpus_count = smp_threads;
2405 cpu_props->has_core_id = true;
2406 cpu_props->core_id = i * smp_threads;
2407 /* TODO: add 'has_node/node' here to describe
2408 to which node core belongs */
2409
2410 cpu_item->props = cpu_props;
2411 if (spapr->cores[i]) {
2412 cpu_item->has_qom_path = true;
2413 cpu_item->qom_path = object_get_canonical_path(spapr->cores[i]);
2414 }
2415 list_item->value = cpu_item;
2416 list_item->next = head;
2417 head = list_item;
2418 }
2419 return head;
2420 }
2421
2422 static void spapr_machine_class_init(ObjectClass *oc, void *data)
2423 {
2424 MachineClass *mc = MACHINE_CLASS(oc);
2425 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
2426 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
2427 NMIClass *nc = NMI_CLASS(oc);
2428 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2429
2430 mc->desc = "pSeries Logical Partition (PAPR compliant)";
2431
2432 /*
2433 * We set up the default / latest behaviour here. The class_init
2434 * functions for the specific versioned machine types can override
2435 * these details for backwards compatibility
2436 */
2437 mc->init = ppc_spapr_init;
2438 mc->reset = ppc_spapr_reset;
2439 mc->block_default_type = IF_SCSI;
2440 mc->max_cpus = MAX_CPUMASK_BITS;
2441 mc->no_parallel = 1;
2442 mc->default_boot_order = "";
2443 mc->default_ram_size = 512 * M_BYTE;
2444 mc->kvm_type = spapr_kvm_type;
2445 mc->has_dynamic_sysbus = true;
2446 mc->pci_allow_0_address = true;
2447 mc->get_hotplug_handler = spapr_get_hotpug_handler;
2448 hc->pre_plug = spapr_machine_device_pre_plug;
2449 hc->plug = spapr_machine_device_plug;
2450 hc->unplug = spapr_machine_device_unplug;
2451 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id;
2452
2453 smc->dr_lmb_enabled = true;
2454 mc->query_hotpluggable_cpus = spapr_query_hotpluggable_cpus;
2455 fwc->get_dev_path = spapr_get_fw_dev_path;
2456 nc->nmi_monitor_handler = spapr_nmi;
2457 }
2458
2459 static const TypeInfo spapr_machine_info = {
2460 .name = TYPE_SPAPR_MACHINE,
2461 .parent = TYPE_MACHINE,
2462 .abstract = true,
2463 .instance_size = sizeof(sPAPRMachineState),
2464 .instance_init = spapr_machine_initfn,
2465 .instance_finalize = spapr_machine_finalizefn,
2466 .class_size = sizeof(sPAPRMachineClass),
2467 .class_init = spapr_machine_class_init,
2468 .interfaces = (InterfaceInfo[]) {
2469 { TYPE_FW_PATH_PROVIDER },
2470 { TYPE_NMI },
2471 { TYPE_HOTPLUG_HANDLER },
2472 { }
2473 },
2474 };
2475
2476 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
2477 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
2478 void *data) \
2479 { \
2480 MachineClass *mc = MACHINE_CLASS(oc); \
2481 spapr_machine_##suffix##_class_options(mc); \
2482 if (latest) { \
2483 mc->alias = "pseries"; \
2484 mc->is_default = 1; \
2485 } \
2486 } \
2487 static void spapr_machine_##suffix##_instance_init(Object *obj) \
2488 { \
2489 MachineState *machine = MACHINE(obj); \
2490 spapr_machine_##suffix##_instance_options(machine); \
2491 } \
2492 static const TypeInfo spapr_machine_##suffix##_info = { \
2493 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
2494 .parent = TYPE_SPAPR_MACHINE, \
2495 .class_init = spapr_machine_##suffix##_class_init, \
2496 .instance_init = spapr_machine_##suffix##_instance_init, \
2497 }; \
2498 static void spapr_machine_register_##suffix(void) \
2499 { \
2500 type_register(&spapr_machine_##suffix##_info); \
2501 } \
2502 type_init(spapr_machine_register_##suffix)
2503
2504 /*
2505 * pseries-2.7
2506 */
2507 static void spapr_machine_2_7_instance_options(MachineState *machine)
2508 {
2509 }
2510
2511 static void spapr_machine_2_7_class_options(MachineClass *mc)
2512 {
2513 /* Defaults for the latest behaviour inherited from the base class */
2514 }
2515
2516 DEFINE_SPAPR_MACHINE(2_7, "2.7", true);
2517
2518 /*
2519 * pseries-2.6
2520 */
2521 #define SPAPR_COMPAT_2_6 \
2522 HW_COMPAT_2_6 \
2523 { \
2524 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
2525 .property = "ddw",\
2526 .value = stringify(off),\
2527 },
2528
2529 static void spapr_machine_2_6_instance_options(MachineState *machine)
2530 {
2531 }
2532
2533 static void spapr_machine_2_6_class_options(MachineClass *mc)
2534 {
2535 spapr_machine_2_7_class_options(mc);
2536 mc->query_hotpluggable_cpus = NULL;
2537 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6);
2538 }
2539
2540 DEFINE_SPAPR_MACHINE(2_6, "2.6", false);
2541
2542 /*
2543 * pseries-2.5
2544 */
2545 #define SPAPR_COMPAT_2_5 \
2546 HW_COMPAT_2_5 \
2547 { \
2548 .driver = "spapr-vlan", \
2549 .property = "use-rx-buffer-pools", \
2550 .value = "off", \
2551 },
2552
2553 static void spapr_machine_2_5_instance_options(MachineState *machine)
2554 {
2555 }
2556
2557 static void spapr_machine_2_5_class_options(MachineClass *mc)
2558 {
2559 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
2560
2561 spapr_machine_2_6_class_options(mc);
2562 smc->use_ohci_by_default = true;
2563 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5);
2564 }
2565
2566 DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
2567
2568 /*
2569 * pseries-2.4
2570 */
2571 #define SPAPR_COMPAT_2_4 \
2572 HW_COMPAT_2_4
2573
2574 static void spapr_machine_2_4_instance_options(MachineState *machine)
2575 {
2576 spapr_machine_2_5_instance_options(machine);
2577 }
2578
2579 static void spapr_machine_2_4_class_options(MachineClass *mc)
2580 {
2581 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
2582
2583 spapr_machine_2_5_class_options(mc);
2584 smc->dr_lmb_enabled = false;
2585 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4);
2586 }
2587
2588 DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
2589
2590 /*
2591 * pseries-2.3
2592 */
2593 #define SPAPR_COMPAT_2_3 \
2594 HW_COMPAT_2_3 \
2595 {\
2596 .driver = "spapr-pci-host-bridge",\
2597 .property = "dynamic-reconfiguration",\
2598 .value = "off",\
2599 },
2600
2601 static void spapr_machine_2_3_instance_options(MachineState *machine)
2602 {
2603 spapr_machine_2_4_instance_options(machine);
2604 savevm_skip_section_footers();
2605 global_state_set_optional();
2606 savevm_skip_configuration();
2607 }
2608
2609 static void spapr_machine_2_3_class_options(MachineClass *mc)
2610 {
2611 spapr_machine_2_4_class_options(mc);
2612 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3);
2613 }
2614 DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
2615
2616 /*
2617 * pseries-2.2
2618 */
2619
2620 #define SPAPR_COMPAT_2_2 \
2621 HW_COMPAT_2_2 \
2622 {\
2623 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
2624 .property = "mem_win_size",\
2625 .value = "0x20000000",\
2626 },
2627
2628 static void spapr_machine_2_2_instance_options(MachineState *machine)
2629 {
2630 spapr_machine_2_3_instance_options(machine);
2631 machine->suppress_vmdesc = true;
2632 }
2633
2634 static void spapr_machine_2_2_class_options(MachineClass *mc)
2635 {
2636 spapr_machine_2_3_class_options(mc);
2637 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2);
2638 }
2639 DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
2640
2641 /*
2642 * pseries-2.1
2643 */
2644 #define SPAPR_COMPAT_2_1 \
2645 HW_COMPAT_2_1
2646
2647 static void spapr_machine_2_1_instance_options(MachineState *machine)
2648 {
2649 spapr_machine_2_2_instance_options(machine);
2650 }
2651
2652 static void spapr_machine_2_1_class_options(MachineClass *mc)
2653 {
2654 spapr_machine_2_2_class_options(mc);
2655 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1);
2656 }
2657 DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
2658
2659 static void spapr_machine_register_types(void)
2660 {
2661 type_register_static(&spapr_machine_info);
2662 }
2663
2664 type_init(spapr_machine_register_types)
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