include/hw/ppc/pnv.h

   1 /*
   2  * QEMU PowerPC PowerNV various definitions
   3  *
   4  * Copyright (c) 2014-2016 BenH, IBM Corporation.
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef PPC_PNV_H
  21 #define PPC_PNV_H
  22
  23 #include "cpu.h"
  24 #include "hw/boards.h"
  25 #include "hw/sysbus.h"
  26 #include "hw/ipmi/ipmi.h"
  27 #include "hw/ppc/pnv_pnor.h"
  28 #include "hw/pci-host/pnv_phb.h"
  29
  30 #define TYPE_PNV_CHIP "pnv-chip"
  31
  32 typedef struct PnvChip PnvChip;
  33 typedef struct Pnv8Chip Pnv8Chip;
  34 typedef struct Pnv9Chip Pnv9Chip;
  35 typedef struct Pnv10Chip Pnv10Chip;
  36
  37 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP
  38 #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX
  39
  40 #define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1")
  41 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8E,
  42                          TYPE_PNV_CHIP_POWER8E)
  43
  44 #define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0")
  45 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8,
  46                          TYPE_PNV_CHIP_POWER8)
  47
  48 #define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0")
  49 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8NVL,
  50                          TYPE_PNV_CHIP_POWER8NVL)
  51
  52 #define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0")
  53 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9,
  54                          TYPE_PNV_CHIP_POWER9)
  55
  56 #define TYPE_PNV_CHIP_POWER10 PNV_CHIP_TYPE_NAME("power10_v2.0")
  57 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10,
  58                          TYPE_PNV_CHIP_POWER10)
  59
  60 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
  61
  62 #define TYPE_PNV_MACHINE       MACHINE_TYPE_NAME("powernv")
  63 typedef struct PnvMachineClass PnvMachineClass;
  64 typedef struct PnvMachineState PnvMachineState;
  65 DECLARE_OBJ_CHECKERS(PnvMachineState, PnvMachineClass,
  66                      PNV_MACHINE, TYPE_PNV_MACHINE)
  67
  68
  69 struct PnvMachineClass {
  70     /*< private >*/
  71     MachineClass parent_class;
  72
  73     /*< public >*/
  74     const char *compat;
  75     int compat_size;
  76
  77     void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt);
  78 };
  79
  80 struct PnvMachineState {
  81     /*< private >*/
  82     MachineState parent_obj;
  83
  84     uint32_t     initrd_base;
  85     long         initrd_size;
  86
  87     uint32_t     num_chips;
  88     PnvChip      **chips;
  89
  90     ISABus       *isa_bus;
  91     uint32_t     cpld_irqstate;
  92
  93     IPMIBmc      *bmc;
  94     Notifier     powerdown_notifier;
  95
  96     PnvPnor      *pnor;
  97
  98     hwaddr       fw_load_addr;
  99 };
 100
 101 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id);
 102 Object *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb, Error **errp);
 103
 104 #define PNV_FDT_ADDR          0x01000000
 105 #define PNV_TIMEBASE_FREQ     512000000ULL
 106
 107 /*
 108  * BMC helpers
 109  */
 110 void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt);
 111 void pnv_bmc_powerdown(IPMIBmc *bmc);
 112 IPMIBmc *pnv_bmc_create(PnvPnor *pnor);
 113 IPMIBmc *pnv_bmc_find(Error **errp);
 114 void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor);
 115
 116 /*
 117  * POWER8 MMIO base addresses
 118  */
 119 #define PNV_XSCOM_SIZE        0x800000000ull
 120 #define PNV_XSCOM_BASE(chip)                                            \
 121     (0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE)
 122
 123 #define PNV_OCC_COMMON_AREA_SIZE    0x0000000000800000ull
 124 #define PNV_OCC_COMMON_AREA_BASE    0x7fff800000ull
 125 #define PNV_OCC_SENSOR_BASE(chip)   (PNV_OCC_COMMON_AREA_BASE + \
 126     PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id))
 127
 128 #define PNV_HOMER_SIZE              0x0000000000400000ull
 129 #define PNV_HOMER_BASE(chip)                                            \
 130     (0x7ffd800000ull + ((uint64_t)(chip)->chip_id) * PNV_HOMER_SIZE)
 131
 132
 133 /*
 134  * XSCOM 0x20109CA defines the ICP BAR:
 135  *
 136  * 0:29   : bits 14 to 43 of address to define 1 MB region.
 137  * 30     : 1 to enable ICP to receive loads/stores against its BAR region
 138  * 31:63  : Constant 0
 139  *
 140  * Usually defined as :
 141  *
 142  *      0xffffe00200000000 -> 0x0003ffff80000000
 143  *      0xffffe00600000000 -> 0x0003ffff80100000
 144  *      0xffffe02200000000 -> 0x0003ffff80800000
 145  *      0xffffe02600000000 -> 0x0003ffff80900000
 146  */
 147 #define PNV_ICP_SIZE         0x0000000000100000ull
 148 #define PNV_ICP_BASE(chip)                                              \
 149     (0x0003ffff80000000ull + (uint64_t) (chip)->chip_id * PNV_ICP_SIZE)
 150
 151
 152 #define PNV_PSIHB_SIZE       0x0000000000100000ull
 153 #define PNV_PSIHB_BASE(chip) \
 154     (0x0003fffe80000000ull + (uint64_t)(chip)->chip_id * PNV_PSIHB_SIZE)
 155
 156 #define PNV_PSIHB_FSP_SIZE   0x0000000100000000ull
 157 #define PNV_PSIHB_FSP_BASE(chip) \
 158     (0x0003ffe000000000ull + (uint64_t)(chip)->chip_id * \
 159      PNV_PSIHB_FSP_SIZE)
 160
 161 /*
 162  * POWER9 MMIO base addresses
 163  */
 164 #define PNV9_CHIP_BASE(chip, base)   \
 165     ((base) + ((uint64_t) (chip)->chip_id << 42))
 166
 167 #define PNV9_XIVE_VC_SIZE            0x0000008000000000ull
 168 #define PNV9_XIVE_VC_BASE(chip)      PNV9_CHIP_BASE(chip, 0x0006010000000000ull)
 169
 170 #define PNV9_XIVE_PC_SIZE            0x0000001000000000ull
 171 #define PNV9_XIVE_PC_BASE(chip)      PNV9_CHIP_BASE(chip, 0x0006018000000000ull)
 172
 173 #define PNV9_LPCM_SIZE               0x0000000100000000ull
 174 #define PNV9_LPCM_BASE(chip)         PNV9_CHIP_BASE(chip, 0x0006030000000000ull)
 175
 176 #define PNV9_PSIHB_SIZE              0x0000000000100000ull
 177 #define PNV9_PSIHB_BASE(chip)        PNV9_CHIP_BASE(chip, 0x0006030203000000ull)
 178
 179 #define PNV9_XIVE_IC_SIZE            0x0000000000080000ull
 180 #define PNV9_XIVE_IC_BASE(chip)      PNV9_CHIP_BASE(chip, 0x0006030203100000ull)
 181
 182 #define PNV9_XIVE_TM_SIZE            0x0000000000040000ull
 183 #define PNV9_XIVE_TM_BASE(chip)      PNV9_CHIP_BASE(chip, 0x0006030203180000ull)
 184
 185 #define PNV9_PSIHB_ESB_SIZE          0x0000000000010000ull
 186 #define PNV9_PSIHB_ESB_BASE(chip)    PNV9_CHIP_BASE(chip, 0x00060302031c0000ull)
 187
 188 #define PNV9_XSCOM_SIZE              0x0000000400000000ull
 189 #define PNV9_XSCOM_BASE(chip)        PNV9_CHIP_BASE(chip, 0x00603fc00000000ull)
 190
 191 #define PNV9_OCC_COMMON_AREA_SIZE    0x0000000000800000ull
 192 #define PNV9_OCC_COMMON_AREA_BASE    0x203fff800000ull
 193 #define PNV9_OCC_SENSOR_BASE(chip)   (PNV9_OCC_COMMON_AREA_BASE +       \
 194     PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id))
 195
 196 #define PNV9_HOMER_SIZE              0x0000000000400000ull
 197 #define PNV9_HOMER_BASE(chip)                                           \
 198     (0x203ffd800000ull + ((uint64_t)(chip)->chip_id) * PNV9_HOMER_SIZE)
 199
 200 /*
 201  * POWER10 MMIO base addresses - 16TB stride per chip
 202  */
 203 #define PNV10_CHIP_BASE(chip, base)   \
 204     ((base) + ((uint64_t) (chip)->chip_id << 44))
 205
 206 #define PNV10_XSCOM_SIZE             0x0000000400000000ull
 207 #define PNV10_XSCOM_BASE(chip)       PNV10_CHIP_BASE(chip, 0x00603fc00000000ull)
 208
 209 #define PNV10_LPCM_SIZE             0x0000000100000000ull
 210 #define PNV10_LPCM_BASE(chip)       PNV10_CHIP_BASE(chip, 0x0006030000000000ull)
 211
 212 #define PNV10_XIVE2_IC_SIZE         0x0000000002000000ull
 213 #define PNV10_XIVE2_IC_BASE(chip)   PNV10_CHIP_BASE(chip, 0x0006030200000000ull)
 214
 215 #define PNV10_PSIHB_ESB_SIZE        0x0000000000100000ull
 216 #define PNV10_PSIHB_ESB_BASE(chip)  PNV10_CHIP_BASE(chip, 0x0006030202000000ull)
 217
 218 #define PNV10_PSIHB_SIZE            0x0000000000100000ull
 219 #define PNV10_PSIHB_BASE(chip)      PNV10_CHIP_BASE(chip, 0x0006030203000000ull)
 220
 221 #define PNV10_XIVE2_TM_SIZE         0x0000000000040000ull
 222 #define PNV10_XIVE2_TM_BASE(chip)   PNV10_CHIP_BASE(chip, 0x0006030203180000ull)
 223
 224 #define PNV10_XIVE2_NVC_SIZE        0x0000000008000000ull
 225 #define PNV10_XIVE2_NVC_BASE(chip)  PNV10_CHIP_BASE(chip, 0x0006030208000000ull)
 226
 227 #define PNV10_XIVE2_NVPG_SIZE       0x0000010000000000ull
 228 #define PNV10_XIVE2_NVPG_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006040000000000ull)
 229
 230 #define PNV10_XIVE2_ESB_SIZE        0x0000010000000000ull
 231 #define PNV10_XIVE2_ESB_BASE(chip)  PNV10_CHIP_BASE(chip, 0x0006050000000000ull)
 232
 233 #define PNV10_XIVE2_END_SIZE        0x0000020000000000ull
 234 #define PNV10_XIVE2_END_BASE(chip)  PNV10_CHIP_BASE(chip, 0x0006060000000000ull)
 235
 236 #define PNV10_OCC_COMMON_AREA_SIZE  0x0000000000800000ull
 237 #define PNV10_OCC_COMMON_AREA_BASE  0x300fff800000ull
 238 #define PNV10_OCC_SENSOR_BASE(chip) (PNV10_OCC_COMMON_AREA_BASE +       \
 239     PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id))
 240
 241 #define PNV10_HOMER_SIZE              0x0000000000400000ull
 242 #define PNV10_HOMER_BASE(chip)                                           \
 243     (0x300ffd800000ll + ((uint64_t)(chip)->chip_id) * PNV10_HOMER_SIZE)
 244
 245 #endif /* PPC_PNV_H */