hw/misc/mips_itu.c

   1 /*
   2  * Inter-Thread Communication Unit emulation.
   3  *
   4  * Copyright (c) 2016 Imagination Technologies
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/units.h"
  22 #include "qemu/log.h"
  23 #include "qemu/module.h"
  24 #include "qapi/error.h"
  25 #include "exec/exec-all.h"
  26 #include "hw/misc/mips_itu.h"
  27 #include "hw/qdev-properties.h"
  28
  29 #define ITC_TAG_ADDRSPACE_SZ (ITC_ADDRESSMAP_NUM * 8)
  30 /* Initialize as 4kB area to fit all 32 cells with default 128B grain.
  31    Storage may be resized by the software. */
  32 #define ITC_STORAGE_ADDRSPACE_SZ 0x1000
  33
  34 #define ITC_FIFO_NUM_MAX 16
  35 #define ITC_SEMAPH_NUM_MAX 16
  36 #define ITC_AM1_NUMENTRIES_OFS 20
  37
  38 #define ITC_CELL_PV_MAX_VAL 0xFFFF
  39
  40 #define ITC_CELL_TAG_FIFO_DEPTH 28
  41 #define ITC_CELL_TAG_FIFO_PTR 18
  42 #define ITC_CELL_TAG_FIFO 17
  43 #define ITC_CELL_TAG_T 16
  44 #define ITC_CELL_TAG_F 1
  45 #define ITC_CELL_TAG_E 0
  46
  47 #define ITC_AM0_BASE_ADDRESS_MASK 0xFFFFFC00ULL
  48 #define ITC_AM0_EN_MASK 0x1
  49
  50 #define ITC_AM1_ADDR_MASK_MASK 0x1FC00
  51 #define ITC_AM1_ENTRY_GRAIN_MASK 0x7
  52
  53 typedef enum ITCView {
  54     ITCVIEW_BYPASS  = 0,
  55     ITCVIEW_CONTROL = 1,
  56     ITCVIEW_EF_SYNC = 2,
  57     ITCVIEW_EF_TRY  = 3,
  58     ITCVIEW_PV_SYNC = 4,
  59     ITCVIEW_PV_TRY  = 5,
  60     ITCVIEW_PV_ICR0 = 15,
  61 } ITCView;
  62
  63 #define ITC_ICR0_CELL_NUM        16
  64 #define ITC_ICR0_BLK_GRAIN       8
  65 #define ITC_ICR0_BLK_GRAIN_MASK  0x7
  66 #define ITC_ICR0_ERR_AXI         2
  67 #define ITC_ICR0_ERR_PARITY      1
  68 #define ITC_ICR0_ERR_EXEC        0
  69
  70 MemoryRegion *mips_itu_get_tag_region(MIPSITUState *itu)
  71 {
  72     return &itu->tag_io;
  73 }
  74
  75 static uint64_t itc_tag_read(void *opaque, hwaddr addr, unsigned size)
  76 {
  77     MIPSITUState *tag = (MIPSITUState *)opaque;
  78     uint64_t index = addr >> 3;
  79
  80     if (index >= ITC_ADDRESSMAP_NUM) {
  81         qemu_log_mask(LOG_GUEST_ERROR, "Read 0x%" PRIx64 "\n", addr);
  82         return 0;
  83     }
  84
  85     return tag->ITCAddressMap[index];
  86 }
  87
  88 void itc_reconfigure(MIPSITUState *tag)
  89 {
  90     uint64_t *am = &tag->ITCAddressMap[0];
  91     MemoryRegion *mr = &tag->storage_io;
  92     hwaddr address = am[0] & ITC_AM0_BASE_ADDRESS_MASK;
  93     uint64_t size = (1 * KiB) + (am[1] & ITC_AM1_ADDR_MASK_MASK);
  94     bool is_enabled = (am[0] & ITC_AM0_EN_MASK) != 0;
  95
  96     if (tag->saar) {
  97         address = (tag->saar[0] & 0xFFFFFFFFE000ULL) << 4;
  98         size = 1ULL << ((tag->saar[0] >> 1) & 0x1f);
  99         is_enabled = tag->saar[0] & 1;
 100     }
 101
 102     memory_region_transaction_begin();
 103     if (!(size & (size - 1))) {
 104         memory_region_set_size(mr, size);
 105     }
 106     memory_region_set_address(mr, address);
 107     memory_region_set_enabled(mr, is_enabled);
 108     memory_region_transaction_commit();
 109 }
 110
 111 static void itc_tag_write(void *opaque, hwaddr addr,
 112                           uint64_t data, unsigned size)
 113 {
 114     MIPSITUState *tag = (MIPSITUState *)opaque;
 115     uint64_t *am = &tag->ITCAddressMap[0];
 116     uint64_t am_old, mask;
 117     uint64_t index = addr >> 3;
 118
 119     switch (index) {
 120     case 0:
 121         mask = ITC_AM0_BASE_ADDRESS_MASK | ITC_AM0_EN_MASK;
 122         break;
 123     case 1:
 124         mask = ITC_AM1_ADDR_MASK_MASK | ITC_AM1_ENTRY_GRAIN_MASK;
 125         break;
 126     default:
 127         qemu_log_mask(LOG_GUEST_ERROR, "Bad write 0x%" PRIx64 "\n", addr);
 128         return;
 129     }
 130
 131     am_old = am[index];
 132     am[index] = (data & mask) | (am_old & ~mask);
 133     if (am_old != am[index]) {
 134         itc_reconfigure(tag);
 135     }
 136 }
 137
 138 static const MemoryRegionOps itc_tag_ops = {
 139     .read = itc_tag_read,
 140     .write = itc_tag_write,
 141     .impl = {
 142         .max_access_size = 8,
 143     },
 144     .endianness = DEVICE_NATIVE_ENDIAN,
 145 };
 146
 147 static inline uint32_t get_num_cells(MIPSITUState *s)
 148 {
 149     return s->num_fifo + s->num_semaphores;
 150 }
 151
 152 static inline ITCView get_itc_view(hwaddr addr)
 153 {
 154     return (addr >> 3) & 0xf;
 155 }
 156
 157 static inline int get_cell_stride_shift(const MIPSITUState *s)
 158 {
 159     /* Minimum interval (for EntryGain = 0) is 128 B */
 160     if (s->saar) {
 161         return 7 + ((s->icr0 >> ITC_ICR0_BLK_GRAIN) &
 162                     ITC_ICR0_BLK_GRAIN_MASK);
 163     } else {
 164         return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK);
 165     }
 166 }
 167
 168 static inline ITCStorageCell *get_cell(MIPSITUState *s,
 169                                        hwaddr addr)
 170 {
 171     uint32_t cell_idx = addr >> get_cell_stride_shift(s);
 172     uint32_t num_cells = get_num_cells(s);
 173
 174     if (cell_idx >= num_cells) {
 175         cell_idx = num_cells - 1;
 176     }
 177
 178     return &s->cell[cell_idx];
 179 }
 180
 181 static void wake_blocked_threads(ITCStorageCell *c)
 182 {
 183     CPUState *cs;
 184     CPU_FOREACH(cs) {
 185         if (cs->halted && (c->blocked_threads & (1ULL << cs->cpu_index))) {
 186             cpu_interrupt(cs, CPU_INTERRUPT_WAKE);
 187         }
 188     }
 189     c->blocked_threads = 0;
 190 }
 191
 192 static G_NORETURN
 193 void block_thread_and_exit(ITCStorageCell *c)
 194 {
 195     c->blocked_threads |= 1ULL << current_cpu->cpu_index;
 196     current_cpu->halted = 1;
 197     current_cpu->exception_index = EXCP_HLT;
 198     cpu_loop_exit_restore(current_cpu, current_cpu->mem_io_pc);
 199 }
 200
 201 /* ITC Bypass View */
 202
 203 static inline uint64_t view_bypass_read(ITCStorageCell *c)
 204 {
 205     if (c->tag.FIFO) {
 206         return c->data[c->fifo_out];
 207     } else {
 208         return c->data[0];
 209     }
 210 }
 211
 212 static inline void view_bypass_write(ITCStorageCell *c, uint64_t val)
 213 {
 214     if (c->tag.FIFO && (c->tag.FIFOPtr > 0)) {
 215         int idx = (c->fifo_out + c->tag.FIFOPtr - 1) % ITC_CELL_DEPTH;
 216         c->data[idx] = val;
 217     }
 218
 219     /* ignore a write to the semaphore cell */
 220 }
 221
 222 /* ITC Control View */
 223
 224 static inline uint64_t view_control_read(ITCStorageCell *c)
 225 {
 226     return ((uint64_t)c->tag.FIFODepth << ITC_CELL_TAG_FIFO_DEPTH) |
 227            (c->tag.FIFOPtr << ITC_CELL_TAG_FIFO_PTR) |
 228            (c->tag.FIFO << ITC_CELL_TAG_FIFO) |
 229            (c->tag.T << ITC_CELL_TAG_T) |
 230            (c->tag.E << ITC_CELL_TAG_E) |
 231            (c->tag.F << ITC_CELL_TAG_F);
 232 }
 233
 234 static inline void view_control_write(ITCStorageCell *c, uint64_t val)
 235 {
 236     c->tag.T = (val >> ITC_CELL_TAG_T) & 1;
 237     c->tag.E = (val >> ITC_CELL_TAG_E) & 1;
 238     c->tag.F = (val >> ITC_CELL_TAG_F) & 1;
 239
 240     if (c->tag.E) {
 241         c->tag.FIFOPtr = 0;
 242     }
 243 }
 244
 245 /* ITC Empty/Full View */
 246
 247 static uint64_t view_ef_common_read(ITCStorageCell *c, bool blocking)
 248 {
 249     uint64_t ret = 0;
 250
 251     if (!c->tag.FIFO) {
 252         return 0;
 253     }
 254
 255     c->tag.F = 0;
 256
 257     if (blocking && c->tag.E) {
 258         block_thread_and_exit(c);
 259     }
 260
 261     if (c->blocked_threads) {
 262         wake_blocked_threads(c);
 263     }
 264
 265     if (c->tag.FIFOPtr > 0) {
 266         ret = c->data[c->fifo_out];
 267         c->fifo_out = (c->fifo_out + 1) % ITC_CELL_DEPTH;
 268         c->tag.FIFOPtr--;
 269     }
 270
 271     if (c->tag.FIFOPtr == 0) {
 272         c->tag.E = 1;
 273     }
 274
 275     return ret;
 276 }
 277
 278 static uint64_t view_ef_sync_read(ITCStorageCell *c)
 279 {
 280     return view_ef_common_read(c, true);
 281 }
 282
 283 static uint64_t view_ef_try_read(ITCStorageCell *c)
 284 {
 285     return view_ef_common_read(c, false);
 286 }
 287
 288 static inline void view_ef_common_write(ITCStorageCell *c, uint64_t val,
 289                                         bool blocking)
 290 {
 291     if (!c->tag.FIFO) {
 292         return;
 293     }
 294
 295     c->tag.E = 0;
 296
 297     if (blocking && c->tag.F) {
 298         block_thread_and_exit(c);
 299     }
 300
 301     if (c->blocked_threads) {
 302         wake_blocked_threads(c);
 303     }
 304
 305     if (c->tag.FIFOPtr < ITC_CELL_DEPTH) {
 306         int idx = (c->fifo_out + c->tag.FIFOPtr) % ITC_CELL_DEPTH;
 307         c->data[idx] = val;
 308         c->tag.FIFOPtr++;
 309     }
 310
 311     if (c->tag.FIFOPtr == ITC_CELL_DEPTH) {
 312         c->tag.F = 1;
 313     }
 314 }
 315
 316 static void view_ef_sync_write(ITCStorageCell *c, uint64_t val)
 317 {
 318     view_ef_common_write(c, val, true);
 319 }
 320
 321 static void view_ef_try_write(ITCStorageCell *c, uint64_t val)
 322 {
 323     view_ef_common_write(c, val, false);
 324 }
 325
 326 /* ITC P/V View */
 327
 328 static uint64_t view_pv_common_read(ITCStorageCell *c, bool blocking)
 329 {
 330     uint64_t ret = c->data[0];
 331
 332     if (c->tag.FIFO) {
 333         return 0;
 334     }
 335
 336     if (c->data[0] > 0) {
 337         c->data[0]--;
 338     } else if (blocking) {
 339         block_thread_and_exit(c);
 340     }
 341
 342     return ret;
 343 }
 344
 345 static uint64_t view_pv_sync_read(ITCStorageCell *c)
 346 {
 347     return view_pv_common_read(c, true);
 348 }
 349
 350 static uint64_t view_pv_try_read(ITCStorageCell *c)
 351 {
 352     return view_pv_common_read(c, false);
 353 }
 354
 355 static inline void view_pv_common_write(ITCStorageCell *c)
 356 {
 357     if (c->tag.FIFO) {
 358         return;
 359     }
 360
 361     if (c->data[0] < ITC_CELL_PV_MAX_VAL) {
 362         c->data[0]++;
 363     }
 364
 365     if (c->blocked_threads) {
 366         wake_blocked_threads(c);
 367     }
 368 }
 369
 370 static void view_pv_sync_write(ITCStorageCell *c)
 371 {
 372     view_pv_common_write(c);
 373 }
 374
 375 static void view_pv_try_write(ITCStorageCell *c)
 376 {
 377     view_pv_common_write(c);
 378 }
 379
 380 static void raise_exception(int excp)
 381 {
 382     current_cpu->exception_index = excp;
 383     cpu_loop_exit(current_cpu);
 384 }
 385
 386 static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size)
 387 {
 388     MIPSITUState *s = (MIPSITUState *)opaque;
 389     ITCStorageCell *cell = get_cell(s, addr);
 390     ITCView view = get_itc_view(addr);
 391     uint64_t ret = -1;
 392
 393     switch (size) {
 394     case 1:
 395     case 2:
 396         s->icr0 |= 1 << ITC_ICR0_ERR_AXI;
 397         raise_exception(EXCP_DBE);
 398         return 0;
 399     }
 400
 401     switch (view) {
 402     case ITCVIEW_BYPASS:
 403         ret = view_bypass_read(cell);
 404         break;
 405     case ITCVIEW_CONTROL:
 406         ret = view_control_read(cell);
 407         break;
 408     case ITCVIEW_EF_SYNC:
 409         ret = view_ef_sync_read(cell);
 410         break;
 411     case ITCVIEW_EF_TRY:
 412         ret = view_ef_try_read(cell);
 413         break;
 414     case ITCVIEW_PV_SYNC:
 415         ret = view_pv_sync_read(cell);
 416         break;
 417     case ITCVIEW_PV_TRY:
 418         ret = view_pv_try_read(cell);
 419         break;
 420     case ITCVIEW_PV_ICR0:
 421         ret = s->icr0;
 422         break;
 423     default:
 424         qemu_log_mask(LOG_GUEST_ERROR,
 425                       "itc_storage_read: Bad ITC View %d\n", (int)view);
 426         break;
 427     }
 428
 429     return ret;
 430 }
 431
 432 static void itc_storage_write(void *opaque, hwaddr addr, uint64_t data,
 433                               unsigned size)
 434 {
 435     MIPSITUState *s = (MIPSITUState *)opaque;
 436     ITCStorageCell *cell = get_cell(s, addr);
 437     ITCView view = get_itc_view(addr);
 438
 439     switch (size) {
 440     case 1:
 441     case 2:
 442         s->icr0 |= 1 << ITC_ICR0_ERR_AXI;
 443         raise_exception(EXCP_DBE);
 444         return;
 445     }
 446
 447     switch (view) {
 448     case ITCVIEW_BYPASS:
 449         view_bypass_write(cell, data);
 450         break;
 451     case ITCVIEW_CONTROL:
 452         view_control_write(cell, data);
 453         break;
 454     case ITCVIEW_EF_SYNC:
 455         view_ef_sync_write(cell, data);
 456         break;
 457     case ITCVIEW_EF_TRY:
 458         view_ef_try_write(cell, data);
 459         break;
 460     case ITCVIEW_PV_SYNC:
 461         view_pv_sync_write(cell);
 462         break;
 463     case ITCVIEW_PV_TRY:
 464         view_pv_try_write(cell);
 465         break;
 466     case ITCVIEW_PV_ICR0:
 467         if (data & 0x7) {
 468             /* clear ERROR bits */
 469             s->icr0 &= ~(data & 0x7);
 470         }
 471         /* set BLK_GRAIN */
 472         s->icr0 &= ~0x700;
 473         s->icr0 |= data & 0x700;
 474         break;
 475     default:
 476         qemu_log_mask(LOG_GUEST_ERROR,
 477                       "itc_storage_write: Bad ITC View %d\n", (int)view);
 478         break;
 479     }
 480
 481 }
 482
 483 static const MemoryRegionOps itc_storage_ops = {
 484     .read = itc_storage_read,
 485     .write = itc_storage_write,
 486     .endianness = DEVICE_NATIVE_ENDIAN,
 487 };
 488
 489 static void itc_reset_cells(MIPSITUState *s)
 490 {
 491     int i;
 492
 493     memset(s->cell, 0, get_num_cells(s) * sizeof(s->cell[0]));
 494
 495     for (i = 0; i < s->num_fifo; i++) {
 496         s->cell[i].tag.E = 1;
 497         s->cell[i].tag.FIFO = 1;
 498         s->cell[i].tag.FIFODepth = ITC_CELL_DEPTH_SHIFT;
 499     }
 500 }
 501
 502 static void mips_itu_init(Object *obj)
 503 {
 504     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 505     MIPSITUState *s = MIPS_ITU(obj);
 506
 507     memory_region_init_io(&s->storage_io, OBJECT(s), &itc_storage_ops, s,
 508                           "mips-itc-storage", ITC_STORAGE_ADDRSPACE_SZ);
 509     sysbus_init_mmio(sbd, &s->storage_io);
 510
 511     memory_region_init_io(&s->tag_io, OBJECT(s), &itc_tag_ops, s,
 512                           "mips-itc-tag", ITC_TAG_ADDRSPACE_SZ);
 513 }
 514
 515 static void mips_itu_realize(DeviceState *dev, Error **errp)
 516 {
 517     MIPSITUState *s = MIPS_ITU(dev);
 518     CPUMIPSState *env;
 519
 520     if (s->num_fifo > ITC_FIFO_NUM_MAX) {
 521         error_setg(errp, "Exceed maximum number of FIFO cells: %d",
 522                    s->num_fifo);
 523         return;
 524     }
 525     if (s->num_semaphores > ITC_SEMAPH_NUM_MAX) {
 526         error_setg(errp, "Exceed maximum number of Semaphore cells: %d",
 527                    s->num_semaphores);
 528         return;
 529     }
 530     if (!s->cpu0) {
 531         error_setg(errp, "Missing 'cpu[0]' property");
 532         return;
 533     }
 534
 535     env = &MIPS_CPU(s->cpu0)->env;
 536     if (env->saarp) {
 537         s->saar = env->CP0_SAAR;
 538     }
 539
 540     s->cell = g_new(ITCStorageCell, get_num_cells(s));
 541 }
 542
 543 static void mips_itu_reset(DeviceState *dev)
 544 {
 545     MIPSITUState *s = MIPS_ITU(dev);
 546
 547     if (s->saar) {
 548         s->saar[0] = 0x11 << 1;
 549         s->icr0 = get_num_cells(s) << ITC_ICR0_CELL_NUM;
 550     } else {
 551         s->ITCAddressMap[0] = 0;
 552         s->ITCAddressMap[1] =
 553             ((ITC_STORAGE_ADDRSPACE_SZ - 1) & ITC_AM1_ADDR_MASK_MASK) |
 554             (get_num_cells(s) << ITC_AM1_NUMENTRIES_OFS);
 555     }
 556     itc_reconfigure(s);
 557
 558     itc_reset_cells(s);
 559 }
 560
 561 static Property mips_itu_properties[] = {
 562     DEFINE_PROP_UINT32("num-fifo", MIPSITUState, num_fifo,
 563                       ITC_FIFO_NUM_MAX),
 564     DEFINE_PROP_UINT32("num-semaphores", MIPSITUState, num_semaphores,
 565                       ITC_SEMAPH_NUM_MAX),
 566     DEFINE_PROP_LINK("cpu[0]", MIPSITUState, cpu0, TYPE_MIPS_CPU, ArchCPU *),
 567     DEFINE_PROP_END_OF_LIST(),
 568 };
 569
 570 static void mips_itu_class_init(ObjectClass *klass, void *data)
 571 {
 572     DeviceClass *dc = DEVICE_CLASS(klass);
 573
 574     device_class_set_props(dc, mips_itu_properties);
 575     dc->realize = mips_itu_realize;
 576     dc->reset = mips_itu_reset;
 577 }
 578
 579 static const TypeInfo mips_itu_info = {
 580     .name          = TYPE_MIPS_ITU,
 581     .parent        = TYPE_SYS_BUS_DEVICE,
 582     .instance_size = sizeof(MIPSITUState),
 583     .instance_init = mips_itu_init,
 584     .class_init    = mips_itu_class_init,
 585 };
 586
 587 static void mips_itu_register_types(void)
 588 {
 589     type_register_static(&mips_itu_info);
 590 }
 591
 592 type_init(mips_itu_register_types)