2 * ASPEED Watchdog Controller
4 * Copyright (C) 2016-2017 IBM Corp.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qapi/error.h"
14 #include "qemu/module.h"
15 #include "qemu/timer.h"
16 #include "sysemu/watchdog.h"
17 #include "hw/misc/aspeed_scu.h"
18 #include "hw/qdev-properties.h"
19 #include "hw/sysbus.h"
20 #include "hw/watchdog/wdt_aspeed.h"
21 #include "migration/vmstate.h"
24 #define WDT_STATUS (0x00 / 4)
25 #define WDT_RELOAD_VALUE (0x04 / 4)
26 #define WDT_RESTART (0x08 / 4)
27 #define WDT_CTRL (0x0C / 4)
28 #define WDT_CTRL_RESET_MODE_SOC (0x00 << 5)
29 #define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5)
30 #define WDT_CTRL_1MHZ_CLK BIT(4)
31 #define WDT_CTRL_WDT_EXT BIT(3)
32 #define WDT_CTRL_WDT_INTR BIT(2)
33 #define WDT_CTRL_RESET_SYSTEM BIT(1)
34 #define WDT_CTRL_ENABLE BIT(0)
35 #define WDT_RESET_WIDTH (0x18 / 4)
36 #define WDT_RESET_WIDTH_ACTIVE_HIGH BIT(31)
37 #define WDT_POLARITY_MASK (0xFF << 24)
38 #define WDT_ACTIVE_HIGH_MAGIC (0xA5 << 24)
39 #define WDT_ACTIVE_LOW_MAGIC (0x5A << 24)
40 #define WDT_RESET_WIDTH_PUSH_PULL BIT(30)
41 #define WDT_DRIVE_TYPE_MASK (0xFF << 24)
42 #define WDT_PUSH_PULL_MAGIC (0xA8 << 24)
43 #define WDT_OPEN_DRAIN_MAGIC (0x8A << 24)
44 #define WDT_RESET_MASK1 (0x1c / 4)
45 #define WDT_RESET_MASK2 (0x20 / 4)
47 #define WDT_SW_RESET_CTRL (0x24 / 4)
48 #define WDT_SW_RESET_MASK1 (0x28 / 4)
49 #define WDT_SW_RESET_MASK2 (0x2c / 4)
51 #define WDT_TIMEOUT_STATUS (0x10 / 4)
52 #define WDT_TIMEOUT_CLEAR (0x14 / 4)
54 #define WDT_RESTART_MAGIC 0x4755
56 #define AST2600_SCU_RESET_CONTROL1 (0x40 / 4)
57 #define SCU_RESET_CONTROL1 (0x04 / 4)
58 #define SCU_RESET_SDRAM BIT(0)
60 static bool aspeed_wdt_is_enabled(const AspeedWDTState
*s
)
62 return s
->regs
[WDT_CTRL
] & WDT_CTRL_ENABLE
;
65 static uint64_t aspeed_wdt_read(void *opaque
, hwaddr offset
, unsigned size
)
67 AspeedWDTState
*s
= ASPEED_WDT(opaque
);
69 trace_aspeed_wdt_read(offset
, size
);
75 return s
->regs
[WDT_STATUS
];
76 case WDT_RELOAD_VALUE
:
77 return s
->regs
[WDT_RELOAD_VALUE
];
79 qemu_log_mask(LOG_GUEST_ERROR
,
80 "%s: read from write-only reg at offset 0x%"
81 HWADDR_PRIx
"\n", __func__
, offset
);
84 return s
->regs
[WDT_CTRL
];
86 return s
->regs
[WDT_RESET_WIDTH
];
88 return s
->regs
[WDT_RESET_MASK1
];
89 case WDT_TIMEOUT_STATUS
:
90 case WDT_TIMEOUT_CLEAR
:
92 case WDT_SW_RESET_CTRL
:
93 case WDT_SW_RESET_MASK1
:
94 case WDT_SW_RESET_MASK2
:
95 qemu_log_mask(LOG_UNIMP
,
96 "%s: uninmplemented read at offset 0x%" HWADDR_PRIx
"\n",
100 qemu_log_mask(LOG_GUEST_ERROR
,
101 "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx
"\n",
108 static void aspeed_wdt_reload(AspeedWDTState
*s
)
112 if (!(s
->regs
[WDT_CTRL
] & WDT_CTRL_1MHZ_CLK
)) {
113 reload
= muldiv64(s
->regs
[WDT_RELOAD_VALUE
], NANOSECONDS_PER_SECOND
,
116 reload
= s
->regs
[WDT_RELOAD_VALUE
] * 1000ULL;
119 if (aspeed_wdt_is_enabled(s
)) {
120 timer_mod(s
->timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + reload
);
124 static void aspeed_wdt_reload_1mhz(AspeedWDTState
*s
)
126 uint64_t reload
= s
->regs
[WDT_RELOAD_VALUE
] * 1000ULL;
128 if (aspeed_wdt_is_enabled(s
)) {
129 timer_mod(s
->timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + reload
);
133 static uint64_t aspeed_2400_sanitize_ctrl(uint64_t data
)
135 return data
& 0xffff;
138 static uint64_t aspeed_2500_sanitize_ctrl(uint64_t data
)
140 return (data
& ~(0xfUL
<< 8)) | WDT_CTRL_1MHZ_CLK
;
143 static uint64_t aspeed_2600_sanitize_ctrl(uint64_t data
)
145 return data
& ~(0x7UL
<< 7);
148 static void aspeed_wdt_write(void *opaque
, hwaddr offset
, uint64_t data
,
151 AspeedWDTState
*s
= ASPEED_WDT(opaque
);
152 AspeedWDTClass
*awc
= ASPEED_WDT_GET_CLASS(s
);
155 trace_aspeed_wdt_write(offset
, size
, data
);
161 qemu_log_mask(LOG_GUEST_ERROR
,
162 "%s: write to read-only reg at offset 0x%"
163 HWADDR_PRIx
"\n", __func__
, offset
);
165 case WDT_RELOAD_VALUE
:
166 s
->regs
[WDT_RELOAD_VALUE
] = data
;
169 if ((data
& 0xFFFF) == WDT_RESTART_MAGIC
) {
170 s
->regs
[WDT_STATUS
] = s
->regs
[WDT_RELOAD_VALUE
];
175 data
= awc
->sanitize_ctrl(data
);
176 enable
= data
& WDT_CTRL_ENABLE
;
177 if (enable
&& !aspeed_wdt_is_enabled(s
)) {
178 s
->regs
[WDT_CTRL
] = data
;
180 } else if (!enable
&& aspeed_wdt_is_enabled(s
)) {
181 s
->regs
[WDT_CTRL
] = data
;
184 s
->regs
[WDT_CTRL
] = data
;
187 case WDT_RESET_WIDTH
:
188 if (awc
->reset_pulse
) {
189 awc
->reset_pulse(s
, data
& WDT_POLARITY_MASK
);
191 s
->regs
[WDT_RESET_WIDTH
] &= ~awc
->ext_pulse_width_mask
;
192 s
->regs
[WDT_RESET_WIDTH
] |= data
& awc
->ext_pulse_width_mask
;
195 case WDT_RESET_MASK1
:
196 /* TODO: implement */
197 s
->regs
[WDT_RESET_MASK1
] = data
;
200 case WDT_TIMEOUT_STATUS
:
201 case WDT_TIMEOUT_CLEAR
:
202 case WDT_RESET_MASK2
:
203 case WDT_SW_RESET_CTRL
:
204 case WDT_SW_RESET_MASK1
:
205 case WDT_SW_RESET_MASK2
:
206 qemu_log_mask(LOG_UNIMP
,
207 "%s: uninmplemented write at offset 0x%" HWADDR_PRIx
"\n",
211 qemu_log_mask(LOG_GUEST_ERROR
,
212 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx
"\n",
218 static const VMStateDescription vmstate_aspeed_wdt
= {
219 .name
= "vmstate_aspeed_wdt",
221 .minimum_version_id
= 0,
222 .fields
= (VMStateField
[]) {
223 VMSTATE_TIMER_PTR(timer
, AspeedWDTState
),
224 VMSTATE_UINT32_ARRAY(regs
, AspeedWDTState
, ASPEED_WDT_REGS_MAX
),
225 VMSTATE_END_OF_LIST()
229 static const MemoryRegionOps aspeed_wdt_ops
= {
230 .read
= aspeed_wdt_read
,
231 .write
= aspeed_wdt_write
,
232 .endianness
= DEVICE_LITTLE_ENDIAN
,
233 .valid
.min_access_size
= 4,
234 .valid
.max_access_size
= 4,
235 .valid
.unaligned
= false,
238 static void aspeed_wdt_reset(DeviceState
*dev
)
240 AspeedWDTState
*s
= ASPEED_WDT(dev
);
241 AspeedWDTClass
*awc
= ASPEED_WDT_GET_CLASS(s
);
243 s
->regs
[WDT_STATUS
] = awc
->default_status
;
244 s
->regs
[WDT_RELOAD_VALUE
] = awc
->default_reload_value
;
245 s
->regs
[WDT_RESTART
] = 0;
246 s
->regs
[WDT_CTRL
] = awc
->sanitize_ctrl(0);
247 s
->regs
[WDT_RESET_WIDTH
] = 0xFF;
252 static void aspeed_wdt_timer_expired(void *dev
)
254 AspeedWDTState
*s
= ASPEED_WDT(dev
);
255 uint32_t reset_ctrl_reg
= ASPEED_WDT_GET_CLASS(s
)->reset_ctrl_reg
;
257 /* Do not reset on SDRAM controller reset */
258 if (s
->scu
->regs
[reset_ctrl_reg
] & SCU_RESET_SDRAM
) {
260 s
->regs
[WDT_CTRL
] = 0;
264 qemu_log_mask(CPU_LOG_RESET
, "Watchdog timer %" HWADDR_PRIx
" expired.\n",
266 watchdog_perform_action();
270 #define PCLK_HZ 24000000
272 static void aspeed_wdt_realize(DeviceState
*dev
, Error
**errp
)
274 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
275 AspeedWDTState
*s
= ASPEED_WDT(dev
);
276 AspeedWDTClass
*awc
= ASPEED_WDT_GET_CLASS(dev
);
280 s
->timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, aspeed_wdt_timer_expired
, dev
);
282 /* FIXME: This setting should be derived from the SCU hw strapping
285 s
->pclk_freq
= PCLK_HZ
;
287 memory_region_init_io(&s
->iomem
, OBJECT(s
), &aspeed_wdt_ops
, s
,
288 TYPE_ASPEED_WDT
, awc
->iosize
);
289 sysbus_init_mmio(sbd
, &s
->iomem
);
292 static Property aspeed_wdt_properties
[] = {
293 DEFINE_PROP_LINK("scu", AspeedWDTState
, scu
, TYPE_ASPEED_SCU
,
295 DEFINE_PROP_END_OF_LIST(),
298 static void aspeed_wdt_class_init(ObjectClass
*klass
, void *data
)
300 DeviceClass
*dc
= DEVICE_CLASS(klass
);
302 dc
->desc
= "ASPEED Watchdog Controller";
303 dc
->realize
= aspeed_wdt_realize
;
304 dc
->reset
= aspeed_wdt_reset
;
305 set_bit(DEVICE_CATEGORY_WATCHDOG
, dc
->categories
);
306 dc
->vmsd
= &vmstate_aspeed_wdt
;
307 device_class_set_props(dc
, aspeed_wdt_properties
);
308 dc
->desc
= "Aspeed watchdog device";
311 static const TypeInfo aspeed_wdt_info
= {
312 .parent
= TYPE_SYS_BUS_DEVICE
,
313 .name
= TYPE_ASPEED_WDT
,
314 .instance_size
= sizeof(AspeedWDTState
),
315 .class_init
= aspeed_wdt_class_init
,
316 .class_size
= sizeof(AspeedWDTClass
),
320 static void aspeed_2400_wdt_class_init(ObjectClass
*klass
, void *data
)
322 DeviceClass
*dc
= DEVICE_CLASS(klass
);
323 AspeedWDTClass
*awc
= ASPEED_WDT_CLASS(klass
);
325 dc
->desc
= "ASPEED 2400 Watchdog Controller";
327 awc
->ext_pulse_width_mask
= 0xff;
328 awc
->reset_ctrl_reg
= SCU_RESET_CONTROL1
;
329 awc
->wdt_reload
= aspeed_wdt_reload
;
330 awc
->sanitize_ctrl
= aspeed_2400_sanitize_ctrl
;
331 awc
->default_status
= 0x03EF1480;
332 awc
->default_reload_value
= 0x03EF1480;
335 static const TypeInfo aspeed_2400_wdt_info
= {
336 .name
= TYPE_ASPEED_2400_WDT
,
337 .parent
= TYPE_ASPEED_WDT
,
338 .instance_size
= sizeof(AspeedWDTState
),
339 .class_init
= aspeed_2400_wdt_class_init
,
342 static void aspeed_2500_wdt_reset_pulse(AspeedWDTState
*s
, uint32_t property
)
345 if (property
== WDT_ACTIVE_HIGH_MAGIC
) {
346 s
->regs
[WDT_RESET_WIDTH
] |= WDT_RESET_WIDTH_ACTIVE_HIGH
;
347 } else if (property
== WDT_ACTIVE_LOW_MAGIC
) {
348 s
->regs
[WDT_RESET_WIDTH
] &= ~WDT_RESET_WIDTH_ACTIVE_HIGH
;
349 } else if (property
== WDT_PUSH_PULL_MAGIC
) {
350 s
->regs
[WDT_RESET_WIDTH
] |= WDT_RESET_WIDTH_PUSH_PULL
;
351 } else if (property
== WDT_OPEN_DRAIN_MAGIC
) {
352 s
->regs
[WDT_RESET_WIDTH
] &= ~WDT_RESET_WIDTH_PUSH_PULL
;
357 static void aspeed_2500_wdt_class_init(ObjectClass
*klass
, void *data
)
359 DeviceClass
*dc
= DEVICE_CLASS(klass
);
360 AspeedWDTClass
*awc
= ASPEED_WDT_CLASS(klass
);
362 dc
->desc
= "ASPEED 2500 Watchdog Controller";
364 awc
->ext_pulse_width_mask
= 0xfffff;
365 awc
->reset_ctrl_reg
= SCU_RESET_CONTROL1
;
366 awc
->reset_pulse
= aspeed_2500_wdt_reset_pulse
;
367 awc
->wdt_reload
= aspeed_wdt_reload_1mhz
;
368 awc
->sanitize_ctrl
= aspeed_2500_sanitize_ctrl
;
369 awc
->default_status
= 0x014FB180;
370 awc
->default_reload_value
= 0x014FB180;
373 static const TypeInfo aspeed_2500_wdt_info
= {
374 .name
= TYPE_ASPEED_2500_WDT
,
375 .parent
= TYPE_ASPEED_WDT
,
376 .instance_size
= sizeof(AspeedWDTState
),
377 .class_init
= aspeed_2500_wdt_class_init
,
380 static void aspeed_2600_wdt_class_init(ObjectClass
*klass
, void *data
)
382 DeviceClass
*dc
= DEVICE_CLASS(klass
);
383 AspeedWDTClass
*awc
= ASPEED_WDT_CLASS(klass
);
385 dc
->desc
= "ASPEED 2600 Watchdog Controller";
387 awc
->ext_pulse_width_mask
= 0xfffff; /* TODO */
388 awc
->reset_ctrl_reg
= AST2600_SCU_RESET_CONTROL1
;
389 awc
->reset_pulse
= aspeed_2500_wdt_reset_pulse
;
390 awc
->wdt_reload
= aspeed_wdt_reload_1mhz
;
391 awc
->sanitize_ctrl
= aspeed_2600_sanitize_ctrl
;
392 awc
->default_status
= 0x014FB180;
393 awc
->default_reload_value
= 0x014FB180;
396 static const TypeInfo aspeed_2600_wdt_info
= {
397 .name
= TYPE_ASPEED_2600_WDT
,
398 .parent
= TYPE_ASPEED_WDT
,
399 .instance_size
= sizeof(AspeedWDTState
),
400 .class_init
= aspeed_2600_wdt_class_init
,
403 static void aspeed_1030_wdt_class_init(ObjectClass
*klass
, void *data
)
405 DeviceClass
*dc
= DEVICE_CLASS(klass
);
406 AspeedWDTClass
*awc
= ASPEED_WDT_CLASS(klass
);
408 dc
->desc
= "ASPEED 1030 Watchdog Controller";
410 awc
->ext_pulse_width_mask
= 0xfffff; /* TODO */
411 awc
->reset_ctrl_reg
= AST2600_SCU_RESET_CONTROL1
;
412 awc
->reset_pulse
= aspeed_2500_wdt_reset_pulse
;
413 awc
->wdt_reload
= aspeed_wdt_reload_1mhz
;
414 awc
->sanitize_ctrl
= aspeed_2600_sanitize_ctrl
;
415 awc
->default_status
= 0x014FB180;
416 awc
->default_reload_value
= 0x014FB180;
419 static const TypeInfo aspeed_1030_wdt_info
= {
420 .name
= TYPE_ASPEED_1030_WDT
,
421 .parent
= TYPE_ASPEED_WDT
,
422 .instance_size
= sizeof(AspeedWDTState
),
423 .class_init
= aspeed_1030_wdt_class_init
,
426 static void wdt_aspeed_register_types(void)
428 type_register_static(&aspeed_wdt_info
);
429 type_register_static(&aspeed_2400_wdt_info
);
430 type_register_static(&aspeed_2500_wdt_info
);
431 type_register_static(&aspeed_2600_wdt_info
);
432 type_register_static(&aspeed_1030_wdt_info
);
435 type_init(wdt_aspeed_register_types
)