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qapi: Improve error message for description following section
[qemu/kevin.git] / hw / net / igb_core.c
blobd733fed6cf791101d0b57077a945e9b40a253ec5
1 /*
2 * Core code for QEMU igb emulation
3 *
4 * Datasheet:
5 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/82576eg-gbe-datasheet.pdf
6 *
7 * Copyright (c) 2020-2023 Red Hat, Inc.
8 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com)
9 * Developed by Daynix Computing LTD (http://www.daynix.com)
10 *
11 * Authors:
12 * Akihiko Odaki <akihiko.odaki@daynix.com>
13 * Gal Hammmer <gal.hammer@sap.com>
14 * Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
15 * Dmitry Fleytman <dmitry@daynix.com>
16 * Leonid Bloch <leonid@daynix.com>
17 * Yan Vugenfirer <yan@daynix.com>
18 *
19 * Based on work done by:
20 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
21 * Copyright (c) 2008 Qumranet
22 * Based on work done by:
23 * Copyright (c) 2007 Dan Aloni
24 * Copyright (c) 2004 Antony T Curtis
25 *
26 * This library is free software; you can redistribute it and/or
27 * modify it under the terms of the GNU Lesser General Public
28 * License as published by the Free Software Foundation; either
29 * version 2.1 of the License, or (at your option) any later version.
30 *
31 * This library is distributed in the hope that it will be useful,
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
34 * Lesser General Public License for more details.
35 *
36 * You should have received a copy of the GNU Lesser General Public
37 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
38 */
39
40 #include "qemu/osdep.h"
41 #include "qemu/log.h"
42 #include "net/net.h"
43 #include "net/tap.h"
44 #include "hw/net/mii.h"
45 #include "hw/pci/msi.h"
46 #include "hw/pci/msix.h"
47 #include "sysemu/runstate.h"
48
49 #include "net_tx_pkt.h"
50 #include "net_rx_pkt.h"
51
52 #include "igb_common.h"
53 #include "e1000x_common.h"
54 #include "igb_core.h"
55
56 #include "trace.h"
57
58 #define E1000E_MAX_TX_FRAGS (64)
59
60 union e1000_rx_desc_union {
61 struct e1000_rx_desc legacy;
62 union e1000_adv_rx_desc adv;
63 };
64
65 typedef struct IGBTxPktVmdqCallbackContext {
66 IGBCore *core;
67 NetClientState *nc;
68 } IGBTxPktVmdqCallbackContext;
69
70 static ssize_t
71 igb_receive_internal(IGBCore *core, const struct iovec *iov, int iovcnt,
72 bool has_vnet, bool *external_tx);
73
74 static inline void
75 igb_set_interrupt_cause(IGBCore *core, uint32_t val);
76
77 static void igb_update_interrupt_state(IGBCore *core);
78 static void igb_reset(IGBCore *core, bool sw);
79
80 static inline void
81 igb_raise_legacy_irq(IGBCore *core)
82 {
83 trace_e1000e_irq_legacy_notify(true);
84 e1000x_inc_reg_if_not_full(core->mac, IAC);
85 pci_set_irq(core->owner, 1);
86 }
87
88 static inline void
89 igb_lower_legacy_irq(IGBCore *core)
90 {
91 trace_e1000e_irq_legacy_notify(false);
92 pci_set_irq(core->owner, 0);
93 }
94
95 static void igb_msix_notify(IGBCore *core, unsigned int vector)
96 {
97 PCIDevice *dev = core->owner;
98 uint16_t vfn;
99
100 vfn = 8 - (vector + 2) / IGBVF_MSIX_VEC_NUM;
101 if (vfn < pcie_sriov_num_vfs(core->owner)) {
102 dev = pcie_sriov_get_vf_at_index(core->owner, vfn);
103 assert(dev);
104 vector = (vector + 2) % IGBVF_MSIX_VEC_NUM;
105 } else if (vector >= IGB_MSIX_VEC_NUM) {
106 qemu_log_mask(LOG_GUEST_ERROR,
107 "igb: Tried to use vector unavailable for PF");
108 return;
109 }
110
111 msix_notify(dev, vector);
112 }
113
114 static inline void
115 igb_intrmgr_rearm_timer(IGBIntrDelayTimer *timer)
116 {
117 int64_t delay_ns = (int64_t) timer->core->mac[timer->delay_reg] *
118 timer->delay_resolution_ns;
119
120 trace_e1000e_irq_rearm_timer(timer->delay_reg << 2, delay_ns);
121
122 timer_mod(timer->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + delay_ns);
123
124 timer->running = true;
125 }
126
127 static void
128 igb_intmgr_timer_resume(IGBIntrDelayTimer *timer)
129 {
130 if (timer->running) {
131 igb_intrmgr_rearm_timer(timer);
132 }
133 }
134
135 static void
136 igb_intmgr_timer_pause(IGBIntrDelayTimer *timer)
137 {
138 if (timer->running) {
139 timer_del(timer->timer);
140 }
141 }
142
143 static void
144 igb_intrmgr_on_msix_throttling_timer(void *opaque)
145 {
146 IGBIntrDelayTimer *timer = opaque;
147 int idx = timer - &timer->core->eitr[0];
148
149 timer->running = false;
150
151 trace_e1000e_irq_msix_notify_postponed_vec(idx);
152 igb_msix_notify(timer->core, idx);
153 }
154
155 static void
156 igb_intrmgr_initialize_all_timers(IGBCore *core, bool create)
157 {
158 int i;
159
160 for (i = 0; i < IGB_INTR_NUM; i++) {
161 core->eitr[i].core = core;
162 core->eitr[i].delay_reg = EITR0 + i;
163 core->eitr[i].delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
164 }
165
166 if (!create) {
167 return;
168 }
169
170 for (i = 0; i < IGB_INTR_NUM; i++) {
171 core->eitr[i].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
172 igb_intrmgr_on_msix_throttling_timer,
173 &core->eitr[i]);
174 }
175 }
176
177 static void
178 igb_intrmgr_resume(IGBCore *core)
179 {
180 int i;
181
182 for (i = 0; i < IGB_INTR_NUM; i++) {
183 igb_intmgr_timer_resume(&core->eitr[i]);
184 }
185 }
186
187 static void
188 igb_intrmgr_pause(IGBCore *core)
189 {
190 int i;
191
192 for (i = 0; i < IGB_INTR_NUM; i++) {
193 igb_intmgr_timer_pause(&core->eitr[i]);
194 }
195 }
196
197 static void
198 igb_intrmgr_reset(IGBCore *core)
199 {
200 int i;
201
202 for (i = 0; i < IGB_INTR_NUM; i++) {
203 if (core->eitr[i].running) {
204 timer_del(core->eitr[i].timer);
205 igb_intrmgr_on_msix_throttling_timer(&core->eitr[i]);
206 }
207 }
208 }
209
210 static void
211 igb_intrmgr_pci_unint(IGBCore *core)
212 {
213 int i;
214
215 for (i = 0; i < IGB_INTR_NUM; i++) {
216 timer_free(core->eitr[i].timer);
217 }
218 }
219
220 static void
221 igb_intrmgr_pci_realize(IGBCore *core)
222 {
223 igb_intrmgr_initialize_all_timers(core, true);
224 }
225
226 static inline bool
227 igb_rx_csum_enabled(IGBCore *core)
228 {
229 return (core->mac[RXCSUM] & E1000_RXCSUM_PCSD) ? false : true;
230 }
231
232 static inline bool
233 igb_rx_use_legacy_descriptor(IGBCore *core)
234 {
235 /*
236 * TODO: If SRRCTL[n],DESCTYPE = 000b, the 82576 uses the legacy Rx
237 * descriptor.
238 */
239 return false;
240 }
241
242 static inline bool
243 igb_rss_enabled(IGBCore *core)
244 {
245 return (core->mac[MRQC] & 3) == E1000_MRQC_ENABLE_RSS_MQ &&
246 !igb_rx_csum_enabled(core) &&
247 !igb_rx_use_legacy_descriptor(core);
248 }
249
250 typedef struct E1000E_RSSInfo_st {
251 bool enabled;
252 uint32_t hash;
253 uint32_t queue;
254 uint32_t type;
255 } E1000E_RSSInfo;
256
257 static uint32_t
258 igb_rss_get_hash_type(IGBCore *core, struct NetRxPkt *pkt)
259 {
260 bool hasip4, hasip6;
261 EthL4HdrProto l4hdr_proto;
262
263 assert(igb_rss_enabled(core));
264
265 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto);
266
267 if (hasip4) {
268 trace_e1000e_rx_rss_ip4(l4hdr_proto, core->mac[MRQC],
269 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC]),
270 E1000_MRQC_EN_IPV4(core->mac[MRQC]));
271
272 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP &&
273 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC])) {
274 return E1000_MRQ_RSS_TYPE_IPV4TCP;
275 }
276
277 if (E1000_MRQC_EN_IPV4(core->mac[MRQC])) {
278 return E1000_MRQ_RSS_TYPE_IPV4;
279 }
280 } else if (hasip6) {
281 eth_ip6_hdr_info *ip6info = net_rx_pkt_get_ip6_info(pkt);
282
283 bool ex_dis = core->mac[RFCTL] & E1000_RFCTL_IPV6_EX_DIS;
284 bool new_ex_dis = core->mac[RFCTL] & E1000_RFCTL_NEW_IPV6_EXT_DIS;
285
286 /*
287 * Following two traces must not be combined because resulting
288 * event will have 11 arguments totally and some trace backends
289 * (at least "ust") have limitation of maximum 10 arguments per
290 * event. Events with more arguments fail to compile for
291 * backends like these.
292 */
293 trace_e1000e_rx_rss_ip6_rfctl(core->mac[RFCTL]);
294 trace_e1000e_rx_rss_ip6(ex_dis, new_ex_dis, l4hdr_proto,
295 ip6info->has_ext_hdrs,
296 ip6info->rss_ex_dst_valid,
297 ip6info->rss_ex_src_valid,
298 core->mac[MRQC],
299 E1000_MRQC_EN_TCPIPV6(core->mac[MRQC]),
300 E1000_MRQC_EN_IPV6EX(core->mac[MRQC]),
301 E1000_MRQC_EN_IPV6(core->mac[MRQC]));
302
303 if ((!ex_dis || !ip6info->has_ext_hdrs) &&
304 (!new_ex_dis || !(ip6info->rss_ex_dst_valid ||
305 ip6info->rss_ex_src_valid))) {
306
307 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP &&
308 E1000_MRQC_EN_TCPIPV6(core->mac[MRQC])) {
309 return E1000_MRQ_RSS_TYPE_IPV6TCP;
310 }
311
312 if (E1000_MRQC_EN_IPV6EX(core->mac[MRQC])) {
313 return E1000_MRQ_RSS_TYPE_IPV6EX;
314 }
315
316 }
317
318 if (E1000_MRQC_EN_IPV6(core->mac[MRQC])) {
319 return E1000_MRQ_RSS_TYPE_IPV6;
320 }
321
322 }
323
324 return E1000_MRQ_RSS_TYPE_NONE;
325 }
326
327 static uint32_t
328 igb_rss_calc_hash(IGBCore *core, struct NetRxPkt *pkt, E1000E_RSSInfo *info)
329 {
330 NetRxPktRssType type;
331
332 assert(igb_rss_enabled(core));
333
334 switch (info->type) {
335 case E1000_MRQ_RSS_TYPE_IPV4:
336 type = NetPktRssIpV4;
337 break;
338 case E1000_MRQ_RSS_TYPE_IPV4TCP:
339 type = NetPktRssIpV4Tcp;
340 break;
341 case E1000_MRQ_RSS_TYPE_IPV6TCP:
342 type = NetPktRssIpV6TcpEx;
343 break;
344 case E1000_MRQ_RSS_TYPE_IPV6:
345 type = NetPktRssIpV6;
346 break;
347 case E1000_MRQ_RSS_TYPE_IPV6EX:
348 type = NetPktRssIpV6Ex;
349 break;
350 default:
351 assert(false);
352 return 0;
353 }
354
355 return net_rx_pkt_calc_rss_hash(pkt, type, (uint8_t *) &core->mac[RSSRK]);
356 }
357
358 static void
359 igb_rss_parse_packet(IGBCore *core, struct NetRxPkt *pkt, bool tx,
360 E1000E_RSSInfo *info)
361 {
362 trace_e1000e_rx_rss_started();
363
364 if (tx || !igb_rss_enabled(core)) {
365 info->enabled = false;
366 info->hash = 0;
367 info->queue = 0;
368 info->type = 0;
369 trace_e1000e_rx_rss_disabled();
370 return;
371 }
372
373 info->enabled = true;
374
375 info->type = igb_rss_get_hash_type(core, pkt);
376
377 trace_e1000e_rx_rss_type(info->type);
378
379 if (info->type == E1000_MRQ_RSS_TYPE_NONE) {
380 info->hash = 0;
381 info->queue = 0;
382 return;
383 }
384
385 info->hash = igb_rss_calc_hash(core, pkt, info);
386 info->queue = E1000_RSS_QUEUE(&core->mac[RETA], info->hash);
387 }
388
389 static void
390 igb_tx_insert_vlan(IGBCore *core, uint16_t qn, struct igb_tx *tx,
391 uint16_t vlan, bool insert_vlan)
392 {
393 if (core->mac[MRQC] & 1) {
394 uint16_t pool = qn % IGB_NUM_VM_POOLS;
395
396 if (core->mac[VMVIR0 + pool] & E1000_VMVIR_VLANA_DEFAULT) {
397 /* always insert default VLAN */
398 insert_vlan = true;
399 vlan = core->mac[VMVIR0 + pool] & 0xffff;
400 } else if (core->mac[VMVIR0 + pool] & E1000_VMVIR_VLANA_NEVER) {
401 insert_vlan = false;
402 }
403 }
404
405 if (insert_vlan && e1000x_vlan_enabled(core->mac)) {
406 net_tx_pkt_setup_vlan_header_ex(tx->tx_pkt, vlan,
407 core->mac[VET] & 0xffff);
408 }
409 }
410
411 static bool
412 igb_setup_tx_offloads(IGBCore *core, struct igb_tx *tx)
413 {
414 if (tx->first_cmd_type_len & E1000_ADVTXD_DCMD_TSE) {
415 uint32_t idx = (tx->first_olinfo_status >> 4) & 1;
416 uint32_t mss = tx->ctx[idx].mss_l4len_idx >> 16;
417 if (!net_tx_pkt_build_vheader(tx->tx_pkt, true, true, mss)) {
418 return false;
419 }
420
421 net_tx_pkt_update_ip_checksums(tx->tx_pkt);
422 e1000x_inc_reg_if_not_full(core->mac, TSCTC);
423 return true;
424 }
425
426 if (tx->first_olinfo_status & E1000_ADVTXD_POTS_TXSM) {
427 if (!net_tx_pkt_build_vheader(tx->tx_pkt, false, true, 0)) {
428 return false;
429 }
430 }
431
432 if (tx->first_olinfo_status & E1000_ADVTXD_POTS_IXSM) {
433 net_tx_pkt_update_ip_hdr_checksum(tx->tx_pkt);
434 }
435
436 return true;
437 }
438
439 static void igb_tx_pkt_mac_callback(void *core,
440 const struct iovec *iov,
441 int iovcnt,
442 const struct iovec *virt_iov,
443 int virt_iovcnt)
444 {
445 igb_receive_internal(core, virt_iov, virt_iovcnt, true, NULL);
446 }
447
448 static void igb_tx_pkt_vmdq_callback(void *opaque,
449 const struct iovec *iov,
450 int iovcnt,
451 const struct iovec *virt_iov,
452 int virt_iovcnt)
453 {
454 IGBTxPktVmdqCallbackContext *context = opaque;
455 bool external_tx;
456
457 igb_receive_internal(context->core, virt_iov, virt_iovcnt, true,
458 &external_tx);
459
460 if (external_tx) {
461 if (context->core->has_vnet) {
462 qemu_sendv_packet(context->nc, virt_iov, virt_iovcnt);
463 } else {
464 qemu_sendv_packet(context->nc, iov, iovcnt);
465 }
466 }
467 }
468
469 /* TX Packets Switching (7.10.3.6) */
470 static bool igb_tx_pkt_switch(IGBCore *core, struct igb_tx *tx,
471 NetClientState *nc)
472 {
473 IGBTxPktVmdqCallbackContext context;
474
475 /* TX switching is only used to serve VM to VM traffic. */
476 if (!(core->mac[MRQC] & 1)) {
477 goto send_out;
478 }
479
480 /* TX switching requires DTXSWC.Loopback_en bit enabled. */
481 if (!(core->mac[DTXSWC] & E1000_DTXSWC_VMDQ_LOOPBACK_EN)) {
482 goto send_out;
483 }
484
485 context.core = core;
486 context.nc = nc;
487
488 return net_tx_pkt_send_custom(tx->tx_pkt, false,
489 igb_tx_pkt_vmdq_callback, &context);
490
491 send_out:
492 return net_tx_pkt_send(tx->tx_pkt, nc);
493 }
494
495 static bool
496 igb_tx_pkt_send(IGBCore *core, struct igb_tx *tx, int queue_index)
497 {
498 int target_queue = MIN(core->max_queue_num, queue_index);
499 NetClientState *queue = qemu_get_subqueue(core->owner_nic, target_queue);
500
501 if (!igb_setup_tx_offloads(core, tx)) {
502 return false;
503 }
504
505 net_tx_pkt_dump(tx->tx_pkt);
506
507 if ((core->phy[MII_BMCR] & MII_BMCR_LOOPBACK) ||
508 ((core->mac[RCTL] & E1000_RCTL_LBM_MAC) == E1000_RCTL_LBM_MAC)) {
509 return net_tx_pkt_send_custom(tx->tx_pkt, false,
510 igb_tx_pkt_mac_callback, core);
511 } else {
512 return igb_tx_pkt_switch(core, tx, queue);
513 }
514 }
515
516 static void
517 igb_on_tx_done_update_stats(IGBCore *core, struct NetTxPkt *tx_pkt, int qn)
518 {
519 static const int PTCregs[6] = { PTC64, PTC127, PTC255, PTC511,
520 PTC1023, PTC1522 };
521
522 size_t tot_len = net_tx_pkt_get_total_len(tx_pkt) + 4;
523
524 e1000x_increase_size_stats(core->mac, PTCregs, tot_len);
525 e1000x_inc_reg_if_not_full(core->mac, TPT);
526 e1000x_grow_8reg_if_not_full(core->mac, TOTL, tot_len);
527
528 switch (net_tx_pkt_get_packet_type(tx_pkt)) {
529 case ETH_PKT_BCAST:
530 e1000x_inc_reg_if_not_full(core->mac, BPTC);
531 break;
532 case ETH_PKT_MCAST:
533 e1000x_inc_reg_if_not_full(core->mac, MPTC);
534 break;
535 case ETH_PKT_UCAST:
536 break;
537 default:
538 g_assert_not_reached();
539 }
540
541 core->mac[GPTC] = core->mac[TPT];
542 core->mac[GOTCL] = core->mac[TOTL];
543 core->mac[GOTCH] = core->mac[TOTH];
544
545 if (core->mac[MRQC] & 1) {
546 uint16_t pool = qn % IGB_NUM_VM_POOLS;
547
548 core->mac[PVFGOTC0 + (pool * 64)] += tot_len;
549 core->mac[PVFGPTC0 + (pool * 64)]++;
550 }
551 }
552
553 static void
554 igb_process_tx_desc(IGBCore *core,
555 PCIDevice *dev,
556 struct igb_tx *tx,
557 union e1000_adv_tx_desc *tx_desc,
558 int queue_index)
559 {
560 struct e1000_adv_tx_context_desc *tx_ctx_desc;
561 uint32_t cmd_type_len;
562 uint32_t idx;
563 uint64_t buffer_addr;
564 uint16_t length;
565
566 cmd_type_len = le32_to_cpu(tx_desc->read.cmd_type_len);
567
568 if (cmd_type_len & E1000_ADVTXD_DCMD_DEXT) {
569 if ((cmd_type_len & E1000_ADVTXD_DTYP_DATA) ==
570 E1000_ADVTXD_DTYP_DATA) {
571 /* advanced transmit data descriptor */
572 if (tx->first) {
573 tx->first_cmd_type_len = cmd_type_len;
574 tx->first_olinfo_status = le32_to_cpu(tx_desc->read.olinfo_status);
575 tx->first = false;
576 }
577 } else if ((cmd_type_len & E1000_ADVTXD_DTYP_CTXT) ==
578 E1000_ADVTXD_DTYP_CTXT) {
579 /* advanced transmit context descriptor */
580 tx_ctx_desc = (struct e1000_adv_tx_context_desc *)tx_desc;
581 idx = (le32_to_cpu(tx_ctx_desc->mss_l4len_idx) >> 4) & 1;
582 tx->ctx[idx].vlan_macip_lens = le32_to_cpu(tx_ctx_desc->vlan_macip_lens);
583 tx->ctx[idx].seqnum_seed = le32_to_cpu(tx_ctx_desc->seqnum_seed);
584 tx->ctx[idx].type_tucmd_mlhl = le32_to_cpu(tx_ctx_desc->type_tucmd_mlhl);
585 tx->ctx[idx].mss_l4len_idx = le32_to_cpu(tx_ctx_desc->mss_l4len_idx);
586 return;
587 } else {
588 /* unknown descriptor type */
589 return;
590 }
591 } else {
592 /* legacy descriptor */
593
594 /* TODO: Implement a support for legacy descriptors (7.2.2.1). */
595 }
596
597 buffer_addr = le64_to_cpu(tx_desc->read.buffer_addr);
598 length = cmd_type_len & 0xFFFF;
599
600 if (!tx->skip_cp) {
601 if (!net_tx_pkt_add_raw_fragment(tx->tx_pkt, buffer_addr, length)) {
602 tx->skip_cp = true;
603 }
604 }
605
606 if (cmd_type_len & E1000_TXD_CMD_EOP) {
607 if (!tx->skip_cp && net_tx_pkt_parse(tx->tx_pkt)) {
608 idx = (tx->first_olinfo_status >> 4) & 1;
609 igb_tx_insert_vlan(core, queue_index, tx,
610 tx->ctx[idx].vlan_macip_lens >> 16,
611 !!(cmd_type_len & E1000_TXD_CMD_VLE));
612
613 if (igb_tx_pkt_send(core, tx, queue_index)) {
614 igb_on_tx_done_update_stats(core, tx->tx_pkt, queue_index);
615 }
616 }
617
618 tx->first = true;
619 tx->skip_cp = false;
620 net_tx_pkt_reset(tx->tx_pkt, dev);
621 }
622 }
623
624 static uint32_t igb_tx_wb_eic(IGBCore *core, int queue_idx)
625 {
626 uint32_t n, ent = 0;
627
628 n = igb_ivar_entry_tx(queue_idx);
629 ent = (core->mac[IVAR0 + n / 4] >> (8 * (n % 4))) & 0xff;
630
631 return (ent & E1000_IVAR_VALID) ? BIT(ent & 0x1f) : 0;
632 }
633
634 static uint32_t igb_rx_wb_eic(IGBCore *core, int queue_idx)
635 {
636 uint32_t n, ent = 0;
637
638 n = igb_ivar_entry_rx(queue_idx);
639 ent = (core->mac[IVAR0 + n / 4] >> (8 * (n % 4))) & 0xff;
640
641 return (ent & E1000_IVAR_VALID) ? BIT(ent & 0x1f) : 0;
642 }
643
644 typedef struct E1000E_RingInfo_st {
645 int dbah;
646 int dbal;
647 int dlen;
648 int dh;
649 int dt;
650 int idx;
651 } E1000E_RingInfo;
652
653 static inline bool
654 igb_ring_empty(IGBCore *core, const E1000E_RingInfo *r)
655 {
656 return core->mac[r->dh] == core->mac[r->dt] ||
657 core->mac[r->dt] >= core->mac[r->dlen] / E1000_RING_DESC_LEN;
658 }
659
660 static inline uint64_t
661 igb_ring_base(IGBCore *core, const E1000E_RingInfo *r)
662 {
663 uint64_t bah = core->mac[r->dbah];
664 uint64_t bal = core->mac[r->dbal];
665
666 return (bah << 32) + bal;
667 }
668
669 static inline uint64_t
670 igb_ring_head_descr(IGBCore *core, const E1000E_RingInfo *r)
671 {
672 return igb_ring_base(core, r) + E1000_RING_DESC_LEN * core->mac[r->dh];
673 }
674
675 static inline void
676 igb_ring_advance(IGBCore *core, const E1000E_RingInfo *r, uint32_t count)
677 {
678 core->mac[r->dh] += count;
679
680 if (core->mac[r->dh] * E1000_RING_DESC_LEN >= core->mac[r->dlen]) {
681 core->mac[r->dh] = 0;
682 }
683 }
684
685 static inline uint32_t
686 igb_ring_free_descr_num(IGBCore *core, const E1000E_RingInfo *r)
687 {
688 trace_e1000e_ring_free_space(r->idx, core->mac[r->dlen],
689 core->mac[r->dh], core->mac[r->dt]);
690
691 if (core->mac[r->dh] <= core->mac[r->dt]) {
692 return core->mac[r->dt] - core->mac[r->dh];
693 }
694
695 if (core->mac[r->dh] > core->mac[r->dt]) {
696 return core->mac[r->dlen] / E1000_RING_DESC_LEN +
697 core->mac[r->dt] - core->mac[r->dh];
698 }
699
700 g_assert_not_reached();
701 return 0;
702 }
703
704 static inline bool
705 igb_ring_enabled(IGBCore *core, const E1000E_RingInfo *r)
706 {
707 return core->mac[r->dlen] > 0;
708 }
709
710 typedef struct IGB_TxRing_st {
711 const E1000E_RingInfo *i;
712 struct igb_tx *tx;
713 } IGB_TxRing;
714
715 static inline int
716 igb_mq_queue_idx(int base_reg_idx, int reg_idx)
717 {
718 return (reg_idx - base_reg_idx) / 16;
719 }
720
721 static inline void
722 igb_tx_ring_init(IGBCore *core, IGB_TxRing *txr, int idx)
723 {
724 static const E1000E_RingInfo i[IGB_NUM_QUEUES] = {
725 { TDBAH0, TDBAL0, TDLEN0, TDH0, TDT0, 0 },
726 { TDBAH1, TDBAL1, TDLEN1, TDH1, TDT1, 1 },
727 { TDBAH2, TDBAL2, TDLEN2, TDH2, TDT2, 2 },
728 { TDBAH3, TDBAL3, TDLEN3, TDH3, TDT3, 3 },
729 { TDBAH4, TDBAL4, TDLEN4, TDH4, TDT4, 4 },
730 { TDBAH5, TDBAL5, TDLEN5, TDH5, TDT5, 5 },
731 { TDBAH6, TDBAL6, TDLEN6, TDH6, TDT6, 6 },
732 { TDBAH7, TDBAL7, TDLEN7, TDH7, TDT7, 7 },
733 { TDBAH8, TDBAL8, TDLEN8, TDH8, TDT8, 8 },
734 { TDBAH9, TDBAL9, TDLEN9, TDH9, TDT9, 9 },
735 { TDBAH10, TDBAL10, TDLEN10, TDH10, TDT10, 10 },
736 { TDBAH11, TDBAL11, TDLEN11, TDH11, TDT11, 11 },
737 { TDBAH12, TDBAL12, TDLEN12, TDH12, TDT12, 12 },
738 { TDBAH13, TDBAL13, TDLEN13, TDH13, TDT13, 13 },
739 { TDBAH14, TDBAL14, TDLEN14, TDH14, TDT14, 14 },
740 { TDBAH15, TDBAL15, TDLEN15, TDH15, TDT15, 15 }
741 };
742
743 assert(idx < ARRAY_SIZE(i));
744
745 txr->i = &i[idx];
746 txr->tx = &core->tx[idx];
747 }
748
749 typedef struct E1000E_RxRing_st {
750 const E1000E_RingInfo *i;
751 } E1000E_RxRing;
752
753 static inline void
754 igb_rx_ring_init(IGBCore *core, E1000E_RxRing *rxr, int idx)
755 {
756 static const E1000E_RingInfo i[IGB_NUM_QUEUES] = {
757 { RDBAH0, RDBAL0, RDLEN0, RDH0, RDT0, 0 },
758 { RDBAH1, RDBAL1, RDLEN1, RDH1, RDT1, 1 },
759 { RDBAH2, RDBAL2, RDLEN2, RDH2, RDT2, 2 },
760 { RDBAH3, RDBAL3, RDLEN3, RDH3, RDT3, 3 },
761 { RDBAH4, RDBAL4, RDLEN4, RDH4, RDT4, 4 },
762 { RDBAH5, RDBAL5, RDLEN5, RDH5, RDT5, 5 },
763 { RDBAH6, RDBAL6, RDLEN6, RDH6, RDT6, 6 },
764 { RDBAH7, RDBAL7, RDLEN7, RDH7, RDT7, 7 },
765 { RDBAH8, RDBAL8, RDLEN8, RDH8, RDT8, 8 },
766 { RDBAH9, RDBAL9, RDLEN9, RDH9, RDT9, 9 },
767 { RDBAH10, RDBAL10, RDLEN10, RDH10, RDT10, 10 },
768 { RDBAH11, RDBAL11, RDLEN11, RDH11, RDT11, 11 },
769 { RDBAH12, RDBAL12, RDLEN12, RDH12, RDT12, 12 },
770 { RDBAH13, RDBAL13, RDLEN13, RDH13, RDT13, 13 },
771 { RDBAH14, RDBAL14, RDLEN14, RDH14, RDT14, 14 },
772 { RDBAH15, RDBAL15, RDLEN15, RDH15, RDT15, 15 }
773 };
774
775 assert(idx < ARRAY_SIZE(i));
776
777 rxr->i = &i[idx];
778 }
779
780 static uint32_t
781 igb_txdesc_writeback(IGBCore *core, dma_addr_t base,
782 union e1000_adv_tx_desc *tx_desc,
783 const E1000E_RingInfo *txi)
784 {
785 PCIDevice *d;
786 uint32_t cmd_type_len = le32_to_cpu(tx_desc->read.cmd_type_len);
787 uint64_t tdwba;
788
789 tdwba = core->mac[E1000_TDWBAL(txi->idx) >> 2];
790 tdwba |= (uint64_t)core->mac[E1000_TDWBAH(txi->idx) >> 2] << 32;
791
792 if (!(cmd_type_len & E1000_TXD_CMD_RS)) {
793 return 0;
794 }
795
796 d = pcie_sriov_get_vf_at_index(core->owner, txi->idx % 8);
797 if (!d) {
798 d = core->owner;
799 }
800
801 if (tdwba & 1) {
802 uint32_t buffer = cpu_to_le32(core->mac[txi->dh]);
803 pci_dma_write(d, tdwba & ~3, &buffer, sizeof(buffer));
804 } else {
805 uint32_t status = le32_to_cpu(tx_desc->wb.status) | E1000_TXD_STAT_DD;
806
807 tx_desc->wb.status = cpu_to_le32(status);
808 pci_dma_write(d, base + offsetof(union e1000_adv_tx_desc, wb),
809 &tx_desc->wb, sizeof(tx_desc->wb));
810 }
811
812 return igb_tx_wb_eic(core, txi->idx);
813 }
814
815 static inline bool
816 igb_tx_enabled(IGBCore *core, const E1000E_RingInfo *txi)
817 {
818 bool vmdq = core->mac[MRQC] & 1;
819 uint16_t qn = txi->idx;
820 uint16_t pool = qn % IGB_NUM_VM_POOLS;
821
822 return (core->mac[TCTL] & E1000_TCTL_EN) &&
823 (!vmdq || core->mac[VFTE] & BIT(pool)) &&
824 (core->mac[TXDCTL0 + (qn * 16)] & E1000_TXDCTL_QUEUE_ENABLE);
825 }
826
827 static void
828 igb_start_xmit(IGBCore *core, const IGB_TxRing *txr)
829 {
830 PCIDevice *d;
831 dma_addr_t base;
832 union e1000_adv_tx_desc desc;
833 const E1000E_RingInfo *txi = txr->i;
834 uint32_t eic = 0;
835
836 if (!igb_tx_enabled(core, txi)) {
837 trace_e1000e_tx_disabled();
838 return;
839 }
840
841 d = pcie_sriov_get_vf_at_index(core->owner, txi->idx % 8);
842 if (!d) {
843 d = core->owner;
844 }
845
846 net_tx_pkt_reset(txr->tx->tx_pkt, d);
847
848 while (!igb_ring_empty(core, txi)) {
849 base = igb_ring_head_descr(core, txi);
850
851 pci_dma_read(d, base, &desc, sizeof(desc));
852
853 trace_e1000e_tx_descr((void *)(intptr_t)desc.read.buffer_addr,
854 desc.read.cmd_type_len, desc.wb.status);
855
856 igb_process_tx_desc(core, d, txr->tx, &desc, txi->idx);
857 igb_ring_advance(core, txi, 1);
858 eic |= igb_txdesc_writeback(core, base, &desc, txi);
859 }
860
861 if (eic) {
862 core->mac[EICR] |= eic;
863 igb_set_interrupt_cause(core, E1000_ICR_TXDW);
864 }
865 }
866
867 static uint32_t
868 igb_rxbufsize(IGBCore *core, const E1000E_RingInfo *r)
869 {
870 uint32_t srrctl = core->mac[E1000_SRRCTL(r->idx) >> 2];
871 uint32_t bsizepkt = srrctl & E1000_SRRCTL_BSIZEPKT_MASK;
872 if (bsizepkt) {
873 return bsizepkt << E1000_SRRCTL_BSIZEPKT_SHIFT;
874 }
875
876 return e1000x_rxbufsize(core->mac[RCTL]);
877 }
878
879 static bool
880 igb_has_rxbufs(IGBCore *core, const E1000E_RingInfo *r, size_t total_size)
881 {
882 uint32_t bufs = igb_ring_free_descr_num(core, r);
883 uint32_t bufsize = igb_rxbufsize(core, r);
884
885 trace_e1000e_rx_has_buffers(r->idx, bufs, total_size, bufsize);
886
887 return total_size <= bufs / (core->rx_desc_len / E1000_MIN_RX_DESC_LEN) *
888 bufsize;
889 }
890
891 void
892 igb_start_recv(IGBCore *core)
893 {
894 int i;
895
896 trace_e1000e_rx_start_recv();
897
898 for (i = 0; i <= core->max_queue_num; i++) {
899 qemu_flush_queued_packets(qemu_get_subqueue(core->owner_nic, i));
900 }
901 }
902
903 bool
904 igb_can_receive(IGBCore *core)
905 {
906 int i;
907
908 if (!e1000x_rx_ready(core->owner, core->mac)) {
909 return false;
910 }
911
912 for (i = 0; i < IGB_NUM_QUEUES; i++) {
913 E1000E_RxRing rxr;
914 if (!(core->mac[RXDCTL0 + (i * 16)] & E1000_RXDCTL_QUEUE_ENABLE)) {
915 continue;
916 }
917
918 igb_rx_ring_init(core, &rxr, i);
919 if (igb_ring_enabled(core, rxr.i) && igb_has_rxbufs(core, rxr.i, 1)) {
920 trace_e1000e_rx_can_recv();
921 return true;
922 }
923 }
924
925 trace_e1000e_rx_can_recv_rings_full();
926 return false;
927 }
928
929 ssize_t
930 igb_receive(IGBCore *core, const uint8_t *buf, size_t size)
931 {
932 const struct iovec iov = {
933 .iov_base = (uint8_t *)buf,
934 .iov_len = size
935 };
936
937 return igb_receive_iov(core, &iov, 1);
938 }
939
940 static inline bool
941 igb_rx_l3_cso_enabled(IGBCore *core)
942 {
943 return !!(core->mac[RXCSUM] & E1000_RXCSUM_IPOFLD);
944 }
945
946 static inline bool
947 igb_rx_l4_cso_enabled(IGBCore *core)
948 {
949 return !!(core->mac[RXCSUM] & E1000_RXCSUM_TUOFLD);
950 }
951
952 static bool
953 igb_rx_is_oversized(IGBCore *core, uint16_t qn, size_t size)
954 {
955 uint16_t pool = qn % IGB_NUM_VM_POOLS;
956 bool lpe = !!(core->mac[VMOLR0 + pool] & E1000_VMOLR_LPE);
957 int max_ethernet_lpe_size =
958 core->mac[VMOLR0 + pool] & E1000_VMOLR_RLPML_MASK;
959 int max_ethernet_vlan_size = 1522;
960
961 return size > (lpe ? max_ethernet_lpe_size : max_ethernet_vlan_size);
962 }
963
964 static uint16_t igb_receive_assign(IGBCore *core, const struct eth_header *ehdr,
965 size_t size, E1000E_RSSInfo *rss_info,
966 bool *external_tx)
967 {
968 static const int ta_shift[] = { 4, 3, 2, 0 };
969 uint32_t f, ra[2], *macp, rctl = core->mac[RCTL];
970 uint16_t queues = 0;
971 uint16_t oversized = 0;
972 uint16_t vid = lduw_be_p(&PKT_GET_VLAN_HDR(ehdr)->h_tci) & VLAN_VID_MASK;
973 bool accepted = false;
974 int i;
975
976 memset(rss_info, 0, sizeof(E1000E_RSSInfo));
977
978 if (external_tx) {
979 *external_tx = true;
980 }
981
982 if (e1000x_is_vlan_packet(ehdr, core->mac[VET] & 0xffff) &&
983 e1000x_vlan_rx_filter_enabled(core->mac)) {
984 uint32_t vfta =
985 ldl_le_p((uint32_t *)(core->mac + VFTA) +
986 ((vid >> E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK));
987 if ((vfta & (1 << (vid & E1000_VFTA_ENTRY_BIT_SHIFT_MASK))) == 0) {
988 trace_e1000e_rx_flt_vlan_mismatch(vid);
989 return queues;
990 } else {
991 trace_e1000e_rx_flt_vlan_match(vid);
992 }
993 }
994
995 if (core->mac[MRQC] & 1) {
996 if (is_broadcast_ether_addr(ehdr->h_dest)) {
997 for (i = 0; i < IGB_NUM_VM_POOLS; i++) {
998 if (core->mac[VMOLR0 + i] & E1000_VMOLR_BAM) {
999 queues |= BIT(i);
1000 }
1001 }
1002 } else {
1003 for (macp = core->mac + RA; macp < core->mac + RA + 32; macp += 2) {
1004 if (!(macp[1] & E1000_RAH_AV)) {
1005 continue;
1006 }
1007 ra[0] = cpu_to_le32(macp[0]);
1008 ra[1] = cpu_to_le32(macp[1]);
1009 if (!memcmp(ehdr->h_dest, (uint8_t *)ra, ETH_ALEN)) {
1010 queues |= (macp[1] & E1000_RAH_POOL_MASK) / E1000_RAH_POOL_1;
1011 }
1012 }
1013
1014 for (macp = core->mac + RA2; macp < core->mac + RA2 + 16; macp += 2) {
1015 if (!(macp[1] & E1000_RAH_AV)) {
1016 continue;
1017 }
1018 ra[0] = cpu_to_le32(macp[0]);
1019 ra[1] = cpu_to_le32(macp[1]);
1020 if (!memcmp(ehdr->h_dest, (uint8_t *)ra, ETH_ALEN)) {
1021 queues |= (macp[1] & E1000_RAH_POOL_MASK) / E1000_RAH_POOL_1;
1022 }
1023 }
1024
1025 if (!queues) {
1026 macp = core->mac + (is_multicast_ether_addr(ehdr->h_dest) ? MTA : UTA);
1027
1028 f = ta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3];
1029 f = (((ehdr->h_dest[5] << 8) | ehdr->h_dest[4]) >> f) & 0xfff;
1030 if (macp[f >> 5] & (1 << (f & 0x1f))) {
1031 for (i = 0; i < IGB_NUM_VM_POOLS; i++) {
1032 if (core->mac[VMOLR0 + i] & E1000_VMOLR_ROMPE) {
1033 queues |= BIT(i);
1034 }
1035 }
1036 }
1037 } else if (is_unicast_ether_addr(ehdr->h_dest) && external_tx) {
1038 *external_tx = false;
1039 }
1040 }
1041
1042 if (e1000x_vlan_rx_filter_enabled(core->mac)) {
1043 uint16_t mask = 0;
1044
1045 if (e1000x_is_vlan_packet(ehdr, core->mac[VET] & 0xffff)) {
1046 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
1047 if ((core->mac[VLVF0 + i] & E1000_VLVF_VLANID_MASK) == vid &&
1048 (core->mac[VLVF0 + i] & E1000_VLVF_VLANID_ENABLE)) {
1049 uint32_t poolsel = core->mac[VLVF0 + i] & E1000_VLVF_POOLSEL_MASK;
1050 mask |= poolsel >> E1000_VLVF_POOLSEL_SHIFT;
1051 }
1052 }
1053 } else {
1054 for (i = 0; i < IGB_NUM_VM_POOLS; i++) {
1055 if (core->mac[VMOLR0 + i] & E1000_VMOLR_AUPE) {
1056 mask |= BIT(i);
1057 }
1058 }
1059 }
1060
1061 queues &= mask;
1062 }
1063
1064 if (is_unicast_ether_addr(ehdr->h_dest) && !queues && !external_tx &&
1065 !(core->mac[VT_CTL] & E1000_VT_CTL_DISABLE_DEF_POOL)) {
1066 uint32_t def_pl = core->mac[VT_CTL] & E1000_VT_CTL_DEFAULT_POOL_MASK;
1067 queues = BIT(def_pl >> E1000_VT_CTL_DEFAULT_POOL_SHIFT);
1068 }
1069
1070 queues &= core->mac[VFRE];
1071 if (queues) {
1072 for (i = 0; i < IGB_NUM_VM_POOLS; i++) {
1073 if ((queues & BIT(i)) && igb_rx_is_oversized(core, i, size)) {
1074 oversized |= BIT(i);
1075 }
1076 }
1077 /* 8.19.37 increment ROC if packet is oversized for all queues */
1078 if (oversized == queues) {
1079 trace_e1000x_rx_oversized(size);
1080 e1000x_inc_reg_if_not_full(core->mac, ROC);
1081 }
1082 queues &= ~oversized;
1083 }
1084
1085 if (queues) {
1086 igb_rss_parse_packet(core, core->rx_pkt,
1087 external_tx != NULL, rss_info);
1088 /* Sec 8.26.1: PQn = VFn + VQn*8 */
1089 if (rss_info->queue & 1) {
1090 for (i = 0; i < IGB_NUM_VM_POOLS; i++) {
1091 if ((queues & BIT(i)) &&
1092 (core->mac[VMOLR0 + i] & E1000_VMOLR_RSSE)) {
1093 queues |= BIT(i + IGB_NUM_VM_POOLS);
1094 queues &= ~BIT(i);
1095 }
1096 }
1097 }
1098 }
1099 } else {
1100 switch (net_rx_pkt_get_packet_type(core->rx_pkt)) {
1101 case ETH_PKT_UCAST:
1102 if (rctl & E1000_RCTL_UPE) {
1103 accepted = true; /* promiscuous ucast */
1104 }
1105 break;
1106
1107 case ETH_PKT_BCAST:
1108 if (rctl & E1000_RCTL_BAM) {
1109 accepted = true; /* broadcast enabled */
1110 }
1111 break;
1112
1113 case ETH_PKT_MCAST:
1114 if (rctl & E1000_RCTL_MPE) {
1115 accepted = true; /* promiscuous mcast */
1116 }
1117 break;
1118
1119 default:
1120 g_assert_not_reached();
1121 }
1122
1123 if (!accepted) {
1124 accepted = e1000x_rx_group_filter(core->mac, ehdr->h_dest);
1125 }
1126
1127 if (!accepted) {
1128 for (macp = core->mac + RA2; macp < core->mac + RA2 + 16; macp += 2) {
1129 if (!(macp[1] & E1000_RAH_AV)) {
1130 continue;
1131 }
1132 ra[0] = cpu_to_le32(macp[0]);
1133 ra[1] = cpu_to_le32(macp[1]);
1134 if (!memcmp(ehdr->h_dest, (uint8_t *)ra, ETH_ALEN)) {
1135 trace_e1000x_rx_flt_ucast_match((int)(macp - core->mac - RA2) / 2,
1136 MAC_ARG(ehdr->h_dest));
1137
1138 accepted = true;
1139 break;
1140 }
1141 }
1142 }
1143
1144 if (accepted) {
1145 igb_rss_parse_packet(core, core->rx_pkt, false, rss_info);
1146 queues = BIT(rss_info->queue);
1147 }
1148 }
1149
1150 return queues;
1151 }
1152
1153 static inline void
1154 igb_read_lgcy_rx_descr(IGBCore *core, struct e1000_rx_desc *desc,
1155 hwaddr *buff_addr)
1156 {
1157 *buff_addr = le64_to_cpu(desc->buffer_addr);
1158 }
1159
1160 static inline void
1161 igb_read_adv_rx_descr(IGBCore *core, union e1000_adv_rx_desc *desc,
1162 hwaddr *buff_addr)
1163 {
1164 *buff_addr = le64_to_cpu(desc->read.pkt_addr);
1165 }
1166
1167 static inline void
1168 igb_read_rx_descr(IGBCore *core, union e1000_rx_desc_union *desc,
1169 hwaddr *buff_addr)
1170 {
1171 if (igb_rx_use_legacy_descriptor(core)) {
1172 igb_read_lgcy_rx_descr(core, &desc->legacy, buff_addr);
1173 } else {
1174 igb_read_adv_rx_descr(core, &desc->adv, buff_addr);
1175 }
1176 }
1177
1178 static void
1179 igb_verify_csum_in_sw(IGBCore *core,
1180 struct NetRxPkt *pkt,
1181 uint32_t *status_flags,
1182 EthL4HdrProto l4hdr_proto)
1183 {
1184 bool csum_valid;
1185 uint32_t csum_error;
1186
1187 if (igb_rx_l3_cso_enabled(core)) {
1188 if (!net_rx_pkt_validate_l3_csum(pkt, &csum_valid)) {
1189 trace_e1000e_rx_metadata_l3_csum_validation_failed();
1190 } else {
1191 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_IPE;
1192 *status_flags |= E1000_RXD_STAT_IPCS | csum_error;
1193 }
1194 } else {
1195 trace_e1000e_rx_metadata_l3_cso_disabled();
1196 }
1197
1198 if (!igb_rx_l4_cso_enabled(core)) {
1199 trace_e1000e_rx_metadata_l4_cso_disabled();
1200 return;
1201 }
1202
1203 if (!net_rx_pkt_validate_l4_csum(pkt, &csum_valid)) {
1204 trace_e1000e_rx_metadata_l4_csum_validation_failed();
1205 return;
1206 }
1207
1208 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_TCPE;
1209 *status_flags |= E1000_RXD_STAT_TCPCS | csum_error;
1210
1211 if (l4hdr_proto == ETH_L4_HDR_PROTO_UDP) {
1212 *status_flags |= E1000_RXD_STAT_UDPCS;
1213 }
1214 }
1215
1216 static void
1217 igb_build_rx_metadata(IGBCore *core,
1218 struct NetRxPkt *pkt,
1219 bool is_eop,
1220 const E1000E_RSSInfo *rss_info,
1221 uint16_t *pkt_info, uint16_t *hdr_info,
1222 uint32_t *rss,
1223 uint32_t *status_flags,
1224 uint16_t *ip_id,
1225 uint16_t *vlan_tag)
1226 {
1227 struct virtio_net_hdr *vhdr;
1228 bool hasip4, hasip6;
1229 EthL4HdrProto l4hdr_proto;
1230 uint32_t pkt_type;
1231
1232 *status_flags = E1000_RXD_STAT_DD;
1233
1234 /* No additional metadata needed for non-EOP descriptors */
1235 /* TODO: EOP apply only to status so don't skip whole function. */
1236 if (!is_eop) {
1237 goto func_exit;
1238 }
1239
1240 *status_flags |= E1000_RXD_STAT_EOP;
1241
1242 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto);
1243 trace_e1000e_rx_metadata_protocols(hasip4, hasip6, l4hdr_proto);
1244
1245 /* VLAN state */
1246 if (net_rx_pkt_is_vlan_stripped(pkt)) {
1247 *status_flags |= E1000_RXD_STAT_VP;
1248 *vlan_tag = cpu_to_le16(net_rx_pkt_get_vlan_tag(pkt));
1249 trace_e1000e_rx_metadata_vlan(*vlan_tag);
1250 }
1251
1252 /* Packet parsing results */
1253 if ((core->mac[RXCSUM] & E1000_RXCSUM_PCSD) != 0) {
1254 if (rss_info->enabled) {
1255 *rss = cpu_to_le32(rss_info->hash);
1256 trace_igb_rx_metadata_rss(*rss);
1257 }
1258 } else if (hasip4) {
1259 *status_flags |= E1000_RXD_STAT_IPIDV;
1260 *ip_id = cpu_to_le16(net_rx_pkt_get_ip_id(pkt));
1261 trace_e1000e_rx_metadata_ip_id(*ip_id);
1262 }
1263
1264 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && net_rx_pkt_is_tcp_ack(pkt)) {
1265 *status_flags |= E1000_RXD_STAT_ACK;
1266 trace_e1000e_rx_metadata_ack();
1267 }
1268
1269 if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_DIS)) {
1270 trace_e1000e_rx_metadata_ipv6_filtering_disabled();
1271 pkt_type = E1000_RXD_PKT_MAC;
1272 } else if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP ||
1273 l4hdr_proto == ETH_L4_HDR_PROTO_UDP) {
1274 pkt_type = hasip4 ? E1000_RXD_PKT_IP4_XDP : E1000_RXD_PKT_IP6_XDP;
1275 } else if (hasip4 || hasip6) {
1276 pkt_type = hasip4 ? E1000_RXD_PKT_IP4 : E1000_RXD_PKT_IP6;
1277 } else {
1278 pkt_type = E1000_RXD_PKT_MAC;
1279 }
1280
1281 trace_e1000e_rx_metadata_pkt_type(pkt_type);
1282
1283 if (pkt_info) {
1284 if (rss_info->enabled) {
1285 *pkt_info = rss_info->type;
1286 }
1287
1288 *pkt_info |= (pkt_type << 4);
1289 } else {
1290 *status_flags |= E1000_RXD_PKT_TYPE(pkt_type);
1291 }
1292
1293 if (hdr_info) {
1294 *hdr_info = 0;
1295 }
1296
1297 /* RX CSO information */
1298 if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_XSUM_DIS)) {
1299 trace_e1000e_rx_metadata_ipv6_sum_disabled();
1300 goto func_exit;
1301 }
1302
1303 vhdr = net_rx_pkt_get_vhdr(pkt);
1304
1305 if (!(vhdr->flags & VIRTIO_NET_HDR_F_DATA_VALID) &&
1306 !(vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM)) {
1307 trace_e1000e_rx_metadata_virthdr_no_csum_info();
1308 igb_verify_csum_in_sw(core, pkt, status_flags, l4hdr_proto);
1309 goto func_exit;
1310 }
1311
1312 if (igb_rx_l3_cso_enabled(core)) {
1313 *status_flags |= hasip4 ? E1000_RXD_STAT_IPCS : 0;
1314 } else {
1315 trace_e1000e_rx_metadata_l3_cso_disabled();
1316 }
1317
1318 if (igb_rx_l4_cso_enabled(core)) {
1319 switch (l4hdr_proto) {
1320 case ETH_L4_HDR_PROTO_TCP:
1321 *status_flags |= E1000_RXD_STAT_TCPCS;
1322 break;
1323
1324 case ETH_L4_HDR_PROTO_UDP:
1325 *status_flags |= E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS;
1326 break;
1327
1328 default:
1329 goto func_exit;
1330 }
1331 } else {
1332 trace_e1000e_rx_metadata_l4_cso_disabled();
1333 }
1334
1335 trace_e1000e_rx_metadata_status_flags(*status_flags);
1336
1337 func_exit:
1338 *status_flags = cpu_to_le32(*status_flags);
1339 }
1340
1341 static inline void
1342 igb_write_lgcy_rx_descr(IGBCore *core, struct e1000_rx_desc *desc,
1343 struct NetRxPkt *pkt,
1344 const E1000E_RSSInfo *rss_info,
1345 uint16_t length)
1346 {
1347 uint32_t status_flags, rss;
1348 uint16_t ip_id;
1349
1350 assert(!rss_info->enabled);
1351 desc->length = cpu_to_le16(length);
1352 desc->csum = 0;
1353
1354 igb_build_rx_metadata(core, pkt, pkt != NULL,
1355 rss_info,
1356 NULL, NULL, &rss,
1357 &status_flags, &ip_id,
1358 &desc->special);
1359 desc->errors = (uint8_t) (le32_to_cpu(status_flags) >> 24);
1360 desc->status = (uint8_t) le32_to_cpu(status_flags);
1361 }
1362
1363 static inline void
1364 igb_write_adv_rx_descr(IGBCore *core, union e1000_adv_rx_desc *desc,
1365 struct NetRxPkt *pkt,
1366 const E1000E_RSSInfo *rss_info,
1367 uint16_t length)
1368 {
1369 memset(&desc->wb, 0, sizeof(desc->wb));
1370
1371 desc->wb.upper.length = cpu_to_le16(length);
1372
1373 igb_build_rx_metadata(core, pkt, pkt != NULL,
1374 rss_info,
1375 &desc->wb.lower.lo_dword.pkt_info,
1376 &desc->wb.lower.lo_dword.hdr_info,
1377 &desc->wb.lower.hi_dword.rss,
1378 &desc->wb.upper.status_error,
1379 &desc->wb.lower.hi_dword.csum_ip.ip_id,
1380 &desc->wb.upper.vlan);
1381 }
1382
1383 static inline void
1384 igb_write_rx_descr(IGBCore *core, union e1000_rx_desc_union *desc,
1385 struct NetRxPkt *pkt, const E1000E_RSSInfo *rss_info, uint16_t length)
1386 {
1387 if (igb_rx_use_legacy_descriptor(core)) {
1388 igb_write_lgcy_rx_descr(core, &desc->legacy, pkt, rss_info, length);
1389 } else {
1390 igb_write_adv_rx_descr(core, &desc->adv, pkt, rss_info, length);
1391 }
1392 }
1393
1394 static inline void
1395 igb_pci_dma_write_rx_desc(IGBCore *core, PCIDevice *dev, dma_addr_t addr,
1396 union e1000_rx_desc_union *desc, dma_addr_t len)
1397 {
1398 if (igb_rx_use_legacy_descriptor(core)) {
1399 struct e1000_rx_desc *d = &desc->legacy;
1400 size_t offset = offsetof(struct e1000_rx_desc, status);
1401 uint8_t status = d->status;
1402
1403 d->status &= ~E1000_RXD_STAT_DD;
1404 pci_dma_write(dev, addr, desc, len);
1405
1406 if (status & E1000_RXD_STAT_DD) {
1407 d->status = status;
1408 pci_dma_write(dev, addr + offset, &status, sizeof(status));
1409 }
1410 } else {
1411 union e1000_adv_rx_desc *d = &desc->adv;
1412 size_t offset =
1413 offsetof(union e1000_adv_rx_desc, wb.upper.status_error);
1414 uint32_t status = d->wb.upper.status_error;
1415
1416 d->wb.upper.status_error &= ~E1000_RXD_STAT_DD;
1417 pci_dma_write(dev, addr, desc, len);
1418
1419 if (status & E1000_RXD_STAT_DD) {
1420 d->wb.upper.status_error = status;
1421 pci_dma_write(dev, addr + offset, &status, sizeof(status));
1422 }
1423 }
1424 }
1425
1426 static void
1427 igb_write_to_rx_buffers(IGBCore *core,
1428 PCIDevice *d,
1429 hwaddr ba,
1430 uint16_t *written,
1431 const char *data,
1432 dma_addr_t data_len)
1433 {
1434 trace_igb_rx_desc_buff_write(ba, *written, data, data_len);
1435 pci_dma_write(d, ba + *written, data, data_len);
1436 *written += data_len;
1437 }
1438
1439 static void
1440 igb_update_rx_stats(IGBCore *core, const E1000E_RingInfo *rxi,
1441 size_t data_size, size_t data_fcs_size)
1442 {
1443 e1000x_update_rx_total_stats(core->mac, data_size, data_fcs_size);
1444
1445 switch (net_rx_pkt_get_packet_type(core->rx_pkt)) {
1446 case ETH_PKT_BCAST:
1447 e1000x_inc_reg_if_not_full(core->mac, BPRC);
1448 break;
1449
1450 case ETH_PKT_MCAST:
1451 e1000x_inc_reg_if_not_full(core->mac, MPRC);
1452 break;
1453
1454 default:
1455 break;
1456 }
1457
1458 if (core->mac[MRQC] & 1) {
1459 uint16_t pool = rxi->idx % IGB_NUM_VM_POOLS;
1460
1461 core->mac[PVFGORC0 + (pool * 64)] += data_size + 4;
1462 core->mac[PVFGPRC0 + (pool * 64)]++;
1463 if (net_rx_pkt_get_packet_type(core->rx_pkt) == ETH_PKT_MCAST) {
1464 core->mac[PVFMPRC0 + (pool * 64)]++;
1465 }
1466 }
1467 }
1468
1469 static inline bool
1470 igb_rx_descr_threshold_hit(IGBCore *core, const E1000E_RingInfo *rxi)
1471 {
1472 return igb_ring_free_descr_num(core, rxi) ==
1473 ((core->mac[E1000_SRRCTL(rxi->idx) >> 2] >> 20) & 31) * 16;
1474 }
1475
1476 static void
1477 igb_write_packet_to_guest(IGBCore *core, struct NetRxPkt *pkt,
1478 const E1000E_RxRing *rxr,
1479 const E1000E_RSSInfo *rss_info)
1480 {
1481 PCIDevice *d;
1482 dma_addr_t base;
1483 union e1000_rx_desc_union desc;
1484 size_t desc_size;
1485 size_t desc_offset = 0;
1486 size_t iov_ofs = 0;
1487
1488 struct iovec *iov = net_rx_pkt_get_iovec(pkt);
1489 size_t size = net_rx_pkt_get_total_len(pkt);
1490 size_t total_size = size + e1000x_fcs_len(core->mac);
1491 const E1000E_RingInfo *rxi = rxr->i;
1492 size_t bufsize = igb_rxbufsize(core, rxi);
1493
1494 d = pcie_sriov_get_vf_at_index(core->owner, rxi->idx % 8);
1495 if (!d) {
1496 d = core->owner;
1497 }
1498
1499 do {
1500 hwaddr ba;
1501 uint16_t written = 0;
1502 bool is_last = false;
1503
1504 desc_size = total_size - desc_offset;
1505
1506 if (desc_size > bufsize) {
1507 desc_size = bufsize;
1508 }
1509
1510 if (igb_ring_empty(core, rxi)) {
1511 return;
1512 }
1513
1514 base = igb_ring_head_descr(core, rxi);
1515
1516 pci_dma_read(d, base, &desc, core->rx_desc_len);
1517
1518 trace_e1000e_rx_descr(rxi->idx, base, core->rx_desc_len);
1519
1520 igb_read_rx_descr(core, &desc, &ba);
1521
1522 if (ba) {
1523 if (desc_offset < size) {
1524 static const uint32_t fcs_pad;
1525 size_t iov_copy;
1526 size_t copy_size = size - desc_offset;
1527 if (copy_size > bufsize) {
1528 copy_size = bufsize;
1529 }
1530
1531 /* Copy packet payload */
1532 while (copy_size) {
1533 iov_copy = MIN(copy_size, iov->iov_len - iov_ofs);
1534
1535 igb_write_to_rx_buffers(core, d, ba, &written,
1536 iov->iov_base + iov_ofs, iov_copy);
1537
1538 copy_size -= iov_copy;
1539 iov_ofs += iov_copy;
1540 if (iov_ofs == iov->iov_len) {
1541 iov++;
1542 iov_ofs = 0;
1543 }
1544 }
1545
1546 if (desc_offset + desc_size >= total_size) {
1547 /* Simulate FCS checksum presence in the last descriptor */
1548 igb_write_to_rx_buffers(core, d, ba, &written,
1549 (const char *) &fcs_pad, e1000x_fcs_len(core->mac));
1550 }
1551 }
1552 } else { /* as per intel docs; skip descriptors with null buf addr */
1553 trace_e1000e_rx_null_descriptor();
1554 }
1555 desc_offset += desc_size;
1556 if (desc_offset >= total_size) {
1557 is_last = true;
1558 }
1559
1560 igb_write_rx_descr(core, &desc, is_last ? core->rx_pkt : NULL,
1561 rss_info, written);
1562 igb_pci_dma_write_rx_desc(core, d, base, &desc, core->rx_desc_len);
1563
1564 igb_ring_advance(core, rxi, core->rx_desc_len / E1000_MIN_RX_DESC_LEN);
1565
1566 } while (desc_offset < total_size);
1567
1568 igb_update_rx_stats(core, rxi, size, total_size);
1569 }
1570
1571 static bool
1572 igb_rx_strip_vlan(IGBCore *core, const E1000E_RingInfo *rxi)
1573 {
1574 if (core->mac[MRQC] & 1) {
1575 uint16_t pool = rxi->idx % IGB_NUM_VM_POOLS;
1576 /* Sec 7.10.3.8: CTRL.VME is ignored, only VMOLR/RPLOLR is used */
1577 return (net_rx_pkt_get_packet_type(core->rx_pkt) == ETH_PKT_MCAST) ?
1578 core->mac[RPLOLR] & E1000_RPLOLR_STRVLAN :
1579 core->mac[VMOLR0 + pool] & E1000_VMOLR_STRVLAN;
1580 }
1581
1582 return e1000x_vlan_enabled(core->mac);
1583 }
1584
1585 static inline void
1586 igb_rx_fix_l4_csum(IGBCore *core, struct NetRxPkt *pkt)
1587 {
1588 struct virtio_net_hdr *vhdr = net_rx_pkt_get_vhdr(pkt);
1589
1590 if (vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM) {
1591 net_rx_pkt_fix_l4_csum(pkt);
1592 }
1593 }
1594
1595 ssize_t
1596 igb_receive_iov(IGBCore *core, const struct iovec *iov, int iovcnt)
1597 {
1598 return igb_receive_internal(core, iov, iovcnt, core->has_vnet, NULL);
1599 }
1600
1601 static ssize_t
1602 igb_receive_internal(IGBCore *core, const struct iovec *iov, int iovcnt,
1603 bool has_vnet, bool *external_tx)
1604 {
1605 static const int maximum_ethernet_hdr_len = (ETH_HLEN + 4);
1606
1607 uint16_t queues = 0;
1608 uint32_t n = 0;
1609 uint8_t min_buf[ETH_ZLEN];
1610 struct iovec min_iov;
1611 struct eth_header *ehdr;
1612 uint8_t *filter_buf;
1613 size_t size, orig_size;
1614 size_t iov_ofs = 0;
1615 E1000E_RxRing rxr;
1616 E1000E_RSSInfo rss_info;
1617 size_t total_size;
1618 int i;
1619
1620 trace_e1000e_rx_receive_iov(iovcnt);
1621
1622 if (external_tx) {
1623 *external_tx = true;
1624 }
1625
1626 if (!e1000x_hw_rx_enabled(core->mac)) {
1627 return -1;
1628 }
1629
1630 /* Pull virtio header in */
1631 if (has_vnet) {
1632 net_rx_pkt_set_vhdr_iovec(core->rx_pkt, iov, iovcnt);
1633 iov_ofs = sizeof(struct virtio_net_hdr);
1634 } else {
1635 net_rx_pkt_unset_vhdr(core->rx_pkt);
1636 }
1637
1638 filter_buf = iov->iov_base + iov_ofs;
1639 orig_size = iov_size(iov, iovcnt);
1640 size = orig_size - iov_ofs;
1641
1642 /* Pad to minimum Ethernet frame length */
1643 if (size < sizeof(min_buf)) {
1644 iov_to_buf(iov, iovcnt, iov_ofs, min_buf, size);
1645 memset(&min_buf[size], 0, sizeof(min_buf) - size);
1646 e1000x_inc_reg_if_not_full(core->mac, RUC);
1647 min_iov.iov_base = filter_buf = min_buf;
1648 min_iov.iov_len = size = sizeof(min_buf);
1649 iovcnt = 1;
1650 iov = &min_iov;
1651 iov_ofs = 0;
1652 } else if (iov->iov_len < maximum_ethernet_hdr_len) {
1653 /* This is very unlikely, but may happen. */
1654 iov_to_buf(iov, iovcnt, iov_ofs, min_buf, maximum_ethernet_hdr_len);
1655 filter_buf = min_buf;
1656 }
1657
1658 /* Discard oversized packets if !LPE and !SBP. */
1659 if (e1000x_is_oversized(core->mac, size)) {
1660 return orig_size;
1661 }
1662
1663 ehdr = PKT_GET_ETH_HDR(filter_buf);
1664 net_rx_pkt_set_packet_type(core->rx_pkt, get_eth_packet_type(ehdr));
1665 net_rx_pkt_set_protocols(core->rx_pkt, filter_buf, size);
1666
1667 queues = igb_receive_assign(core, ehdr, size, &rss_info, external_tx);
1668 if (!queues) {
1669 trace_e1000e_rx_flt_dropped();
1670 return orig_size;
1671 }
1672
1673 for (i = 0; i < IGB_NUM_QUEUES; i++) {
1674 if (!(queues & BIT(i)) ||
1675 !(core->mac[RXDCTL0 + (i * 16)] & E1000_RXDCTL_QUEUE_ENABLE)) {
1676 continue;
1677 }
1678
1679 igb_rx_ring_init(core, &rxr, i);
1680
1681 net_rx_pkt_attach_iovec_ex(core->rx_pkt, iov, iovcnt, iov_ofs,
1682 igb_rx_strip_vlan(core, rxr.i),
1683 core->mac[VET] & 0xffff);
1684
1685 total_size = net_rx_pkt_get_total_len(core->rx_pkt) +
1686 e1000x_fcs_len(core->mac);
1687
1688 if (!igb_has_rxbufs(core, rxr.i, total_size)) {
1689 n |= E1000_ICS_RXO;
1690 trace_e1000e_rx_not_written_to_guest(rxr.i->idx);
1691 continue;
1692 }
1693
1694 n |= E1000_ICR_RXDW;
1695
1696 igb_rx_fix_l4_csum(core, core->rx_pkt);
1697 igb_write_packet_to_guest(core, core->rx_pkt, &rxr, &rss_info);
1698
1699 /* Check if receive descriptor minimum threshold hit */
1700 if (igb_rx_descr_threshold_hit(core, rxr.i)) {
1701 n |= E1000_ICS_RXDMT0;
1702 }
1703
1704 core->mac[EICR] |= igb_rx_wb_eic(core, rxr.i->idx);
1705
1706 trace_e1000e_rx_written_to_guest(rxr.i->idx);
1707 }
1708
1709 trace_e1000e_rx_interrupt_set(n);
1710 igb_set_interrupt_cause(core, n);
1711
1712 return orig_size;
1713 }
1714
1715 static inline bool
1716 igb_have_autoneg(IGBCore *core)
1717 {
1718 return core->phy[MII_BMCR] & MII_BMCR_AUTOEN;
1719 }
1720
1721 static void igb_update_flowctl_status(IGBCore *core)
1722 {
1723 if (igb_have_autoneg(core) && core->phy[MII_BMSR] & MII_BMSR_AN_COMP) {
1724 trace_e1000e_link_autoneg_flowctl(true);
1725 core->mac[CTRL] |= E1000_CTRL_TFCE | E1000_CTRL_RFCE;
1726 } else {
1727 trace_e1000e_link_autoneg_flowctl(false);
1728 }
1729 }
1730
1731 static inline void
1732 igb_link_down(IGBCore *core)
1733 {
1734 e1000x_update_regs_on_link_down(core->mac, core->phy);
1735 igb_update_flowctl_status(core);
1736 }
1737
1738 static inline void
1739 igb_set_phy_ctrl(IGBCore *core, uint16_t val)
1740 {
1741 /* bits 0-5 reserved; MII_BMCR_[ANRESTART,RESET] are self clearing */
1742 core->phy[MII_BMCR] = val & ~(0x3f | MII_BMCR_RESET | MII_BMCR_ANRESTART);
1743
1744 if ((val & MII_BMCR_ANRESTART) && igb_have_autoneg(core)) {
1745 e1000x_restart_autoneg(core->mac, core->phy, core->autoneg_timer);
1746 }
1747 }
1748
1749 void igb_core_set_link_status(IGBCore *core)
1750 {
1751 NetClientState *nc = qemu_get_queue(core->owner_nic);
1752 uint32_t old_status = core->mac[STATUS];
1753
1754 trace_e1000e_link_status_changed(nc->link_down ? false : true);
1755
1756 if (nc->link_down) {
1757 e1000x_update_regs_on_link_down(core->mac, core->phy);
1758 } else {
1759 if (igb_have_autoneg(core) &&
1760 !(core->phy[MII_BMSR] & MII_BMSR_AN_COMP)) {
1761 e1000x_restart_autoneg(core->mac, core->phy,
1762 core->autoneg_timer);
1763 } else {
1764 e1000x_update_regs_on_link_up(core->mac, core->phy);
1765 igb_start_recv(core);
1766 }
1767 }
1768
1769 if (core->mac[STATUS] != old_status) {
1770 igb_set_interrupt_cause(core, E1000_ICR_LSC);
1771 }
1772 }
1773
1774 static void
1775 igb_set_ctrl(IGBCore *core, int index, uint32_t val)
1776 {
1777 trace_e1000e_core_ctrl_write(index, val);
1778
1779 /* RST is self clearing */
1780 core->mac[CTRL] = val & ~E1000_CTRL_RST;
1781 core->mac[CTRL_DUP] = core->mac[CTRL];
1782
1783 trace_e1000e_link_set_params(
1784 !!(val & E1000_CTRL_ASDE),
1785 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT,
1786 !!(val & E1000_CTRL_FRCSPD),
1787 !!(val & E1000_CTRL_FRCDPX),
1788 !!(val & E1000_CTRL_RFCE),
1789 !!(val & E1000_CTRL_TFCE));
1790
1791 if (val & E1000_CTRL_RST) {
1792 trace_e1000e_core_ctrl_sw_reset();
1793 igb_reset(core, true);
1794 }
1795
1796 if (val & E1000_CTRL_PHY_RST) {
1797 trace_e1000e_core_ctrl_phy_reset();
1798 core->mac[STATUS] |= E1000_STATUS_PHYRA;
1799 }
1800 }
1801
1802 static void
1803 igb_set_rfctl(IGBCore *core, int index, uint32_t val)
1804 {
1805 trace_e1000e_rx_set_rfctl(val);
1806
1807 if (!(val & E1000_RFCTL_ISCSI_DIS)) {
1808 trace_e1000e_wrn_iscsi_filtering_not_supported();
1809 }
1810
1811 if (!(val & E1000_RFCTL_NFSW_DIS)) {
1812 trace_e1000e_wrn_nfsw_filtering_not_supported();
1813 }
1814
1815 if (!(val & E1000_RFCTL_NFSR_DIS)) {
1816 trace_e1000e_wrn_nfsr_filtering_not_supported();
1817 }
1818
1819 core->mac[RFCTL] = val;
1820 }
1821
1822 static void
1823 igb_calc_rxdesclen(IGBCore *core)
1824 {
1825 if (igb_rx_use_legacy_descriptor(core)) {
1826 core->rx_desc_len = sizeof(struct e1000_rx_desc);
1827 } else {
1828 core->rx_desc_len = sizeof(union e1000_adv_rx_desc);
1829 }
1830 trace_e1000e_rx_desc_len(core->rx_desc_len);
1831 }
1832
1833 static void
1834 igb_set_rx_control(IGBCore *core, int index, uint32_t val)
1835 {
1836 core->mac[RCTL] = val;
1837 trace_e1000e_rx_set_rctl(core->mac[RCTL]);
1838
1839 if (val & E1000_RCTL_DTYP_MASK) {
1840 qemu_log_mask(LOG_GUEST_ERROR,
1841 "igb: RCTL.DTYP must be zero for compatibility");
1842 }
1843
1844 if (val & E1000_RCTL_EN) {
1845 igb_calc_rxdesclen(core);
1846 igb_start_recv(core);
1847 }
1848 }
1849
1850 static inline void
1851 igb_clear_ims_bits(IGBCore *core, uint32_t bits)
1852 {
1853 trace_e1000e_irq_clear_ims(bits, core->mac[IMS], core->mac[IMS] & ~bits);
1854 core->mac[IMS] &= ~bits;
1855 }
1856
1857 static inline bool
1858 igb_postpone_interrupt(IGBIntrDelayTimer *timer)
1859 {
1860 if (timer->running) {
1861 trace_e1000e_irq_postponed_by_xitr(timer->delay_reg << 2);
1862
1863 return true;
1864 }
1865
1866 if (timer->core->mac[timer->delay_reg] != 0) {
1867 igb_intrmgr_rearm_timer(timer);
1868 }
1869
1870 return false;
1871 }
1872
1873 static inline bool
1874 igb_eitr_should_postpone(IGBCore *core, int idx)
1875 {
1876 return igb_postpone_interrupt(&core->eitr[idx]);
1877 }
1878
1879 static void igb_send_msix(IGBCore *core)
1880 {
1881 uint32_t causes = core->mac[EICR] & core->mac[EIMS];
1882 uint32_t effective_eiac;
1883 int vector;
1884
1885 for (vector = 0; vector < IGB_INTR_NUM; ++vector) {
1886 if ((causes & BIT(vector)) && !igb_eitr_should_postpone(core, vector)) {
1887
1888 trace_e1000e_irq_msix_notify_vec(vector);
1889 igb_msix_notify(core, vector);
1890
1891 trace_e1000e_irq_icr_clear_eiac(core->mac[EICR], core->mac[EIAC]);
1892 effective_eiac = core->mac[EIAC] & BIT(vector);
1893 core->mac[EICR] &= ~effective_eiac;
1894 }
1895 }
1896 }
1897
1898 static inline void
1899 igb_fix_icr_asserted(IGBCore *core)
1900 {
1901 core->mac[ICR] &= ~E1000_ICR_ASSERTED;
1902 if (core->mac[ICR]) {
1903 core->mac[ICR] |= E1000_ICR_ASSERTED;
1904 }
1905
1906 trace_e1000e_irq_fix_icr_asserted(core->mac[ICR]);
1907 }
1908
1909 static void
1910 igb_update_interrupt_state(IGBCore *core)
1911 {
1912 uint32_t icr;
1913 uint32_t causes;
1914 uint32_t int_alloc;
1915
1916 icr = core->mac[ICR] & core->mac[IMS];
1917
1918 if (msix_enabled(core->owner)) {
1919 if (icr) {
1920 causes = 0;
1921 if (icr & E1000_ICR_DRSTA) {
1922 int_alloc = core->mac[IVAR_MISC] & 0xff;
1923 if (int_alloc & E1000_IVAR_VALID) {
1924 causes |= BIT(int_alloc & 0x1f);
1925 }
1926 }
1927 /* Check if other bits (excluding the TCP Timer) are enabled. */
1928 if (icr & ~E1000_ICR_DRSTA) {
1929 int_alloc = (core->mac[IVAR_MISC] >> 8) & 0xff;
1930 if (int_alloc & E1000_IVAR_VALID) {
1931 causes |= BIT(int_alloc & 0x1f);
1932 }
1933 trace_e1000e_irq_add_msi_other(core->mac[EICR]);
1934 }
1935 core->mac[EICR] |= causes;
1936 }
1937
1938 if ((core->mac[EICR] & core->mac[EIMS])) {
1939 igb_send_msix(core);
1940 }
1941 } else {
1942 igb_fix_icr_asserted(core);
1943
1944 if (icr) {
1945 core->mac[EICR] |= (icr & E1000_ICR_DRSTA) | E1000_EICR_OTHER;
1946 } else {
1947 core->mac[EICR] &= ~E1000_EICR_OTHER;
1948 }
1949
1950 trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS],
1951 core->mac[ICR], core->mac[IMS]);
1952
1953 if (msi_enabled(core->owner)) {
1954 if (icr) {
1955 msi_notify(core->owner, 0);
1956 }
1957 } else {
1958 if (icr) {
1959 igb_raise_legacy_irq(core);
1960 } else {
1961 igb_lower_legacy_irq(core);
1962 }
1963 }
1964 }
1965 }
1966
1967 static void
1968 igb_set_interrupt_cause(IGBCore *core, uint32_t val)
1969 {
1970 trace_e1000e_irq_set_cause_entry(val, core->mac[ICR]);
1971
1972 core->mac[ICR] |= val;
1973
1974 trace_e1000e_irq_set_cause_exit(val, core->mac[ICR]);
1975
1976 igb_update_interrupt_state(core);
1977 }
1978
1979 static void igb_set_eics(IGBCore *core, int index, uint32_t val)
1980 {
1981 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE);
1982
1983 trace_igb_irq_write_eics(val, msix);
1984
1985 core->mac[EICS] |=
1986 val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK);
1987
1988 /*
1989 * TODO: Move to igb_update_interrupt_state if EICS is modified in other
1990 * places.
1991 */
1992 core->mac[EICR] = core->mac[EICS];
1993
1994 igb_update_interrupt_state(core);
1995 }
1996
1997 static void igb_set_eims(IGBCore *core, int index, uint32_t val)
1998 {
1999 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE);
2000
2001 trace_igb_irq_write_eims(val, msix);
2002
2003 core->mac[EIMS] |=
2004 val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK);
2005
2006 igb_update_interrupt_state(core);
2007 }
2008
2009 static void mailbox_interrupt_to_vf(IGBCore *core, uint16_t vfn)
2010 {
2011 uint32_t ent = core->mac[VTIVAR_MISC + vfn];
2012
2013 if ((ent & E1000_IVAR_VALID)) {
2014 core->mac[EICR] |= (ent & 0x3) << (22 - vfn * IGBVF_MSIX_VEC_NUM);
2015 igb_update_interrupt_state(core);
2016 }
2017 }
2018
2019 static void mailbox_interrupt_to_pf(IGBCore *core)
2020 {
2021 igb_set_interrupt_cause(core, E1000_ICR_VMMB);
2022 }
2023
2024 static void igb_set_pfmailbox(IGBCore *core, int index, uint32_t val)
2025 {
2026 uint16_t vfn = index - P2VMAILBOX0;
2027
2028 trace_igb_set_pfmailbox(vfn, val);
2029
2030 if (val & E1000_P2VMAILBOX_STS) {
2031 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_PFSTS;
2032 mailbox_interrupt_to_vf(core, vfn);
2033 }
2034
2035 if (val & E1000_P2VMAILBOX_ACK) {
2036 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_PFACK;
2037 mailbox_interrupt_to_vf(core, vfn);
2038 }
2039
2040 /* Buffer Taken by PF (can be set only if the VFU is cleared). */
2041 if (val & E1000_P2VMAILBOX_PFU) {
2042 if (!(core->mac[index] & E1000_P2VMAILBOX_VFU)) {
2043 core->mac[index] |= E1000_P2VMAILBOX_PFU;
2044 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_PFU;
2045 }
2046 } else {
2047 core->mac[index] &= ~E1000_P2VMAILBOX_PFU;
2048 core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_PFU;
2049 }
2050
2051 if (val & E1000_P2VMAILBOX_RVFU) {
2052 core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_VFU;
2053 core->mac[MBVFICR] &= ~((E1000_MBVFICR_VFACK_VF1 << vfn) |
2054 (E1000_MBVFICR_VFREQ_VF1 << vfn));
2055 }
2056 }
2057
2058 static void igb_set_vfmailbox(IGBCore *core, int index, uint32_t val)
2059 {
2060 uint16_t vfn = index - V2PMAILBOX0;
2061
2062 trace_igb_set_vfmailbox(vfn, val);
2063
2064 if (val & E1000_V2PMAILBOX_REQ) {
2065 core->mac[MBVFICR] |= E1000_MBVFICR_VFREQ_VF1 << vfn;
2066 mailbox_interrupt_to_pf(core);
2067 }
2068
2069 if (val & E1000_V2PMAILBOX_ACK) {
2070 core->mac[MBVFICR] |= E1000_MBVFICR_VFACK_VF1 << vfn;
2071 mailbox_interrupt_to_pf(core);
2072 }
2073
2074 /* Buffer Taken by VF (can be set only if the PFU is cleared). */
2075 if (val & E1000_V2PMAILBOX_VFU) {
2076 if (!(core->mac[index] & E1000_V2PMAILBOX_PFU)) {
2077 core->mac[index] |= E1000_V2PMAILBOX_VFU;
2078 core->mac[P2VMAILBOX0 + vfn] |= E1000_P2VMAILBOX_VFU;
2079 }
2080 } else {
2081 core->mac[index] &= ~E1000_V2PMAILBOX_VFU;
2082 core->mac[P2VMAILBOX0 + vfn] &= ~E1000_P2VMAILBOX_VFU;
2083 }
2084 }
2085
2086 static void igb_vf_reset(IGBCore *core, uint16_t vfn)
2087 {
2088 uint16_t qn0 = vfn;
2089 uint16_t qn1 = vfn + IGB_NUM_VM_POOLS;
2090
2091 /* disable Rx and Tx for the VF*/
2092 core->mac[RXDCTL0 + (qn0 * 16)] &= ~E1000_RXDCTL_QUEUE_ENABLE;
2093 core->mac[RXDCTL0 + (qn1 * 16)] &= ~E1000_RXDCTL_QUEUE_ENABLE;
2094 core->mac[TXDCTL0 + (qn0 * 16)] &= ~E1000_TXDCTL_QUEUE_ENABLE;
2095 core->mac[TXDCTL0 + (qn1 * 16)] &= ~E1000_TXDCTL_QUEUE_ENABLE;
2096 core->mac[VFRE] &= ~BIT(vfn);
2097 core->mac[VFTE] &= ~BIT(vfn);
2098 /* indicate VF reset to PF */
2099 core->mac[VFLRE] |= BIT(vfn);
2100 /* VFLRE and mailbox use the same interrupt cause */
2101 mailbox_interrupt_to_pf(core);
2102 }
2103
2104 static void igb_w1c(IGBCore *core, int index, uint32_t val)
2105 {
2106 core->mac[index] &= ~val;
2107 }
2108
2109 static void igb_set_eimc(IGBCore *core, int index, uint32_t val)
2110 {
2111 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE);
2112
2113 /* Interrupts are disabled via a write to EIMC and reflected in EIMS. */
2114 core->mac[EIMS] &=
2115 ~(val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK));
2116
2117 trace_igb_irq_write_eimc(val, core->mac[EIMS], msix);
2118 igb_update_interrupt_state(core);
2119 }
2120
2121 static void igb_set_eiac(IGBCore *core, int index, uint32_t val)
2122 {
2123 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE);
2124
2125 if (msix) {
2126 trace_igb_irq_write_eiac(val);
2127
2128 /*
2129 * TODO: When using IOV, the bits that correspond to MSI-X vectors
2130 * that are assigned to a VF are read-only.
2131 */
2132 core->mac[EIAC] |= (val & E1000_EICR_MSIX_MASK);
2133 }
2134 }
2135
2136 static void igb_set_eiam(IGBCore *core, int index, uint32_t val)
2137 {
2138 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE);
2139
2140 /*
2141 * TODO: When using IOV, the bits that correspond to MSI-X vectors that
2142 * are assigned to a VF are read-only.
2143 */
2144 core->mac[EIAM] |=
2145 ~(val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK));
2146
2147 trace_igb_irq_write_eiam(val, msix);
2148 }
2149
2150 static void igb_set_eicr(IGBCore *core, int index, uint32_t val)
2151 {
2152 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE);
2153
2154 /*
2155 * TODO: In IOV mode, only bit zero of this vector is available for the PF
2156 * function.
2157 */
2158 core->mac[EICR] &=
2159 ~(val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK));
2160
2161 trace_igb_irq_write_eicr(val, msix);
2162 igb_update_interrupt_state(core);
2163 }
2164
2165 static void igb_set_vtctrl(IGBCore *core, int index, uint32_t val)
2166 {
2167 uint16_t vfn;
2168
2169 if (val & E1000_CTRL_RST) {
2170 vfn = (index - PVTCTRL0) / 0x40;
2171 igb_vf_reset(core, vfn);
2172 }
2173 }
2174
2175 static void igb_set_vteics(IGBCore *core, int index, uint32_t val)
2176 {
2177 uint16_t vfn = (index - PVTEICS0) / 0x40;
2178
2179 core->mac[index] = val;
2180 igb_set_eics(core, EICS, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM));
2181 }
2182
2183 static void igb_set_vteims(IGBCore *core, int index, uint32_t val)
2184 {
2185 uint16_t vfn = (index - PVTEIMS0) / 0x40;
2186
2187 core->mac[index] = val;
2188 igb_set_eims(core, EIMS, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM));
2189 }
2190
2191 static void igb_set_vteimc(IGBCore *core, int index, uint32_t val)
2192 {
2193 uint16_t vfn = (index - PVTEIMC0) / 0x40;
2194
2195 core->mac[index] = val;
2196 igb_set_eimc(core, EIMC, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM));
2197 }
2198
2199 static void igb_set_vteiac(IGBCore *core, int index, uint32_t val)
2200 {
2201 uint16_t vfn = (index - PVTEIAC0) / 0x40;
2202
2203 core->mac[index] = val;
2204 igb_set_eiac(core, EIAC, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM));
2205 }
2206
2207 static void igb_set_vteiam(IGBCore *core, int index, uint32_t val)
2208 {
2209 uint16_t vfn = (index - PVTEIAM0) / 0x40;
2210
2211 core->mac[index] = val;
2212 igb_set_eiam(core, EIAM, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM));
2213 }
2214
2215 static void igb_set_vteicr(IGBCore *core, int index, uint32_t val)
2216 {
2217 uint16_t vfn = (index - PVTEICR0) / 0x40;
2218
2219 core->mac[index] = val;
2220 igb_set_eicr(core, EICR, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM));
2221 }
2222
2223 static void igb_set_vtivar(IGBCore *core, int index, uint32_t val)
2224 {
2225 uint16_t vfn = (index - VTIVAR);
2226 uint16_t qn = vfn;
2227 uint8_t ent;
2228 int n;
2229
2230 core->mac[index] = val;
2231
2232 /* Get assigned vector associated with queue Rx#0. */
2233 if ((val & E1000_IVAR_VALID)) {
2234 n = igb_ivar_entry_rx(qn);
2235 ent = E1000_IVAR_VALID | (24 - vfn * IGBVF_MSIX_VEC_NUM - (2 - (val & 0x7)));
2236 core->mac[IVAR0 + n / 4] |= ent << 8 * (n % 4);
2237 }
2238
2239 /* Get assigned vector associated with queue Tx#0 */
2240 ent = val >> 8;
2241 if ((ent & E1000_IVAR_VALID)) {
2242 n = igb_ivar_entry_tx(qn);
2243 ent = E1000_IVAR_VALID | (24 - vfn * IGBVF_MSIX_VEC_NUM - (2 - (ent & 0x7)));
2244 core->mac[IVAR0 + n / 4] |= ent << 8 * (n % 4);
2245 }
2246
2247 /*
2248 * Ignoring assigned vectors associated with queues Rx#1 and Tx#1 for now.
2249 */
2250 }
2251
2252 static inline void
2253 igb_autoneg_timer(void *opaque)
2254 {
2255 IGBCore *core = opaque;
2256 if (!qemu_get_queue(core->owner_nic)->link_down) {
2257 e1000x_update_regs_on_autoneg_done(core->mac, core->phy);
2258 igb_start_recv(core);
2259
2260 igb_update_flowctl_status(core);
2261 /* signal link status change to the guest */
2262 igb_set_interrupt_cause(core, E1000_ICR_LSC);
2263 }
2264 }
2265
2266 static inline uint16_t
2267 igb_get_reg_index_with_offset(const uint16_t *mac_reg_access, hwaddr addr)
2268 {
2269 uint16_t index = (addr & 0x1ffff) >> 2;
2270 return index + (mac_reg_access[index] & 0xfffe);
2271 }
2272
2273 static const char igb_phy_regcap[MAX_PHY_REG_ADDRESS + 1] = {
2274 [MII_BMCR] = PHY_RW,
2275 [MII_BMSR] = PHY_R,
2276 [MII_PHYID1] = PHY_R,
2277 [MII_PHYID2] = PHY_R,
2278 [MII_ANAR] = PHY_RW,
2279 [MII_ANLPAR] = PHY_R,
2280 [MII_ANER] = PHY_R,
2281 [MII_ANNP] = PHY_RW,
2282 [MII_ANLPRNP] = PHY_R,
2283 [MII_CTRL1000] = PHY_RW,
2284 [MII_STAT1000] = PHY_R,
2285 [MII_EXTSTAT] = PHY_R,
2286
2287 [IGP01E1000_PHY_PORT_CONFIG] = PHY_RW,
2288 [IGP01E1000_PHY_PORT_STATUS] = PHY_R,
2289 [IGP01E1000_PHY_PORT_CTRL] = PHY_RW,
2290 [IGP01E1000_PHY_LINK_HEALTH] = PHY_R,
2291 [IGP02E1000_PHY_POWER_MGMT] = PHY_RW,
2292 [IGP01E1000_PHY_PAGE_SELECT] = PHY_W
2293 };
2294
2295 static void
2296 igb_phy_reg_write(IGBCore *core, uint32_t addr, uint16_t data)
2297 {
2298 assert(addr <= MAX_PHY_REG_ADDRESS);
2299
2300 if (addr == MII_BMCR) {
2301 igb_set_phy_ctrl(core, data);
2302 } else {
2303 core->phy[addr] = data;
2304 }
2305 }
2306
2307 static void
2308 igb_set_mdic(IGBCore *core, int index, uint32_t val)
2309 {
2310 uint32_t data = val & E1000_MDIC_DATA_MASK;
2311 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
2312
2313 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) { /* phy # */
2314 val = core->mac[MDIC] | E1000_MDIC_ERROR;
2315 } else if (val & E1000_MDIC_OP_READ) {
2316 if (!(igb_phy_regcap[addr] & PHY_R)) {
2317 trace_igb_core_mdic_read_unhandled(addr);
2318 val |= E1000_MDIC_ERROR;
2319 } else {
2320 val = (val ^ data) | core->phy[addr];
2321 trace_igb_core_mdic_read(addr, val);
2322 }
2323 } else if (val & E1000_MDIC_OP_WRITE) {
2324 if (!(igb_phy_regcap[addr] & PHY_W)) {
2325 trace_igb_core_mdic_write_unhandled(addr);
2326 val |= E1000_MDIC_ERROR;
2327 } else {
2328 trace_igb_core_mdic_write(addr, data);
2329 igb_phy_reg_write(core, addr, data);
2330 }
2331 }
2332 core->mac[MDIC] = val | E1000_MDIC_READY;
2333
2334 if (val & E1000_MDIC_INT_EN) {
2335 igb_set_interrupt_cause(core, E1000_ICR_MDAC);
2336 }
2337 }
2338
2339 static void
2340 igb_set_rdt(IGBCore *core, int index, uint32_t val)
2341 {
2342 core->mac[index] = val & 0xffff;
2343 trace_e1000e_rx_set_rdt(igb_mq_queue_idx(RDT0, index), val);
2344 igb_start_recv(core);
2345 }
2346
2347 static void
2348 igb_set_status(IGBCore *core, int index, uint32_t val)
2349 {
2350 if ((val & E1000_STATUS_PHYRA) == 0) {
2351 core->mac[index] &= ~E1000_STATUS_PHYRA;
2352 }
2353 }
2354
2355 static void
2356 igb_set_ctrlext(IGBCore *core, int index, uint32_t val)
2357 {
2358 trace_igb_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK),
2359 !!(val & E1000_CTRL_EXT_SPD_BYPS),
2360 !!(val & E1000_CTRL_EXT_PFRSTD));
2361
2362 /* Zero self-clearing bits */
2363 val &= ~(E1000_CTRL_EXT_ASDCHK | E1000_CTRL_EXT_EE_RST);
2364 core->mac[CTRL_EXT] = val;
2365
2366 if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_PFRSTD) {
2367 for (int vfn = 0; vfn < IGB_MAX_VF_FUNCTIONS; vfn++) {
2368 core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_RSTI;
2369 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_RSTD;
2370 }
2371 }
2372 }
2373
2374 static void
2375 igb_set_pbaclr(IGBCore *core, int index, uint32_t val)
2376 {
2377 int i;
2378
2379 core->mac[PBACLR] = val & E1000_PBACLR_VALID_MASK;
2380
2381 if (!msix_enabled(core->owner)) {
2382 return;
2383 }
2384
2385 for (i = 0; i < IGB_INTR_NUM; i++) {
2386 if (core->mac[PBACLR] & BIT(i)) {
2387 msix_clr_pending(core->owner, i);
2388 }
2389 }
2390 }
2391
2392 static void
2393 igb_set_fcrth(IGBCore *core, int index, uint32_t val)
2394 {
2395 core->mac[FCRTH] = val & 0xFFF8;
2396 }
2397
2398 static void
2399 igb_set_fcrtl(IGBCore *core, int index, uint32_t val)
2400 {
2401 core->mac[FCRTL] = val & 0x8000FFF8;
2402 }
2403
2404 #define IGB_LOW_BITS_SET_FUNC(num) \
2405 static void \
2406 igb_set_##num##bit(IGBCore *core, int index, uint32_t val) \
2407 { \
2408 core->mac[index] = val & (BIT(num) - 1); \
2409 }
2410
2411 IGB_LOW_BITS_SET_FUNC(4)
2412 IGB_LOW_BITS_SET_FUNC(13)
2413 IGB_LOW_BITS_SET_FUNC(16)
2414
2415 static void
2416 igb_set_dlen(IGBCore *core, int index, uint32_t val)
2417 {
2418 core->mac[index] = val & 0xffff0;
2419 }
2420
2421 static void
2422 igb_set_dbal(IGBCore *core, int index, uint32_t val)
2423 {
2424 core->mac[index] = val & E1000_XDBAL_MASK;
2425 }
2426
2427 static void
2428 igb_set_tdt(IGBCore *core, int index, uint32_t val)
2429 {
2430 IGB_TxRing txr;
2431 int qn = igb_mq_queue_idx(TDT0, index);
2432
2433 core->mac[index] = val & 0xffff;
2434
2435 igb_tx_ring_init(core, &txr, qn);
2436 igb_start_xmit(core, &txr);
2437 }
2438
2439 static void
2440 igb_set_ics(IGBCore *core, int index, uint32_t val)
2441 {
2442 trace_e1000e_irq_write_ics(val);
2443 igb_set_interrupt_cause(core, val);
2444 }
2445
2446 static void
2447 igb_set_imc(IGBCore *core, int index, uint32_t val)
2448 {
2449 trace_e1000e_irq_ims_clear_set_imc(val);
2450 igb_clear_ims_bits(core, val);
2451 igb_update_interrupt_state(core);
2452 }
2453
2454 static void
2455 igb_set_ims(IGBCore *core, int index, uint32_t val)
2456 {
2457 uint32_t valid_val = val & 0x77D4FBFD;
2458
2459 trace_e1000e_irq_set_ims(val, core->mac[IMS], core->mac[IMS] | valid_val);
2460 core->mac[IMS] |= valid_val;
2461 igb_update_interrupt_state(core);
2462 }
2463
2464 static void igb_commit_icr(IGBCore *core)
2465 {
2466 /*
2467 * If GPIE.NSICR = 0, then the copy of IAM to IMS will occur only if at
2468 * least one bit is set in the IMS and there is a true interrupt as
2469 * reflected in ICR.INTA.
2470 */
2471 if ((core->mac[GPIE] & E1000_GPIE_NSICR) ||
2472 (core->mac[IMS] && (core->mac[ICR] & E1000_ICR_INT_ASSERTED))) {
2473 igb_set_ims(core, IMS, core->mac[IAM]);
2474 } else {
2475 igb_update_interrupt_state(core);
2476 }
2477 }
2478
2479 static void igb_set_icr(IGBCore *core, int index, uint32_t val)
2480 {
2481 uint32_t icr = core->mac[ICR] & ~val;
2482
2483 trace_igb_irq_icr_write(val, core->mac[ICR], icr);
2484 core->mac[ICR] = icr;
2485 igb_commit_icr(core);
2486 }
2487
2488 static uint32_t
2489 igb_mac_readreg(IGBCore *core, int index)
2490 {
2491 return core->mac[index];
2492 }
2493
2494 static uint32_t
2495 igb_mac_ics_read(IGBCore *core, int index)
2496 {
2497 trace_e1000e_irq_read_ics(core->mac[ICS]);
2498 return core->mac[ICS];
2499 }
2500
2501 static uint32_t
2502 igb_mac_ims_read(IGBCore *core, int index)
2503 {
2504 trace_e1000e_irq_read_ims(core->mac[IMS]);
2505 return core->mac[IMS];
2506 }
2507
2508 static uint32_t
2509 igb_mac_swsm_read(IGBCore *core, int index)
2510 {
2511 uint32_t val = core->mac[SWSM];
2512 core->mac[SWSM] = val | E1000_SWSM_SMBI;
2513 return val;
2514 }
2515
2516 static uint32_t
2517 igb_mac_eitr_read(IGBCore *core, int index)
2518 {
2519 return core->eitr_guest_value[index - EITR0];
2520 }
2521
2522 static uint32_t igb_mac_vfmailbox_read(IGBCore *core, int index)
2523 {
2524 uint32_t val = core->mac[index];
2525
2526 core->mac[index] &= ~(E1000_V2PMAILBOX_PFSTS | E1000_V2PMAILBOX_PFACK |
2527 E1000_V2PMAILBOX_RSTD);
2528
2529 return val;
2530 }
2531
2532 static uint32_t
2533 igb_mac_icr_read(IGBCore *core, int index)
2534 {
2535 uint32_t ret = core->mac[ICR];
2536 trace_e1000e_irq_icr_read_entry(ret);
2537
2538 if (core->mac[GPIE] & E1000_GPIE_NSICR) {
2539 trace_igb_irq_icr_clear_gpie_nsicr();
2540 core->mac[ICR] = 0;
2541 } else if (core->mac[IMS] == 0) {
2542 trace_e1000e_irq_icr_clear_zero_ims();
2543 core->mac[ICR] = 0;
2544 } else if (!msix_enabled(core->owner)) {
2545 trace_e1000e_irq_icr_clear_nonmsix_icr_read();
2546 core->mac[ICR] = 0;
2547 }
2548
2549 trace_e1000e_irq_icr_read_exit(core->mac[ICR]);
2550 igb_commit_icr(core);
2551 return ret;
2552 }
2553
2554 static uint32_t
2555 igb_mac_read_clr4(IGBCore *core, int index)
2556 {
2557 uint32_t ret = core->mac[index];
2558
2559 core->mac[index] = 0;
2560 return ret;
2561 }
2562
2563 static uint32_t
2564 igb_mac_read_clr8(IGBCore *core, int index)
2565 {
2566 uint32_t ret = core->mac[index];
2567
2568 core->mac[index] = 0;
2569 core->mac[index - 1] = 0;
2570 return ret;
2571 }
2572
2573 static uint32_t
2574 igb_get_ctrl(IGBCore *core, int index)
2575 {
2576 uint32_t val = core->mac[CTRL];
2577
2578 trace_e1000e_link_read_params(
2579 !!(val & E1000_CTRL_ASDE),
2580 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT,
2581 !!(val & E1000_CTRL_FRCSPD),
2582 !!(val & E1000_CTRL_FRCDPX),
2583 !!(val & E1000_CTRL_RFCE),
2584 !!(val & E1000_CTRL_TFCE));
2585
2586 return val;
2587 }
2588
2589 static uint32_t igb_get_status(IGBCore *core, int index)
2590 {
2591 uint32_t res = core->mac[STATUS];
2592 uint16_t num_vfs = pcie_sriov_num_vfs(core->owner);
2593
2594 if (core->mac[CTRL] & E1000_CTRL_FRCDPX) {
2595 res |= (core->mac[CTRL] & E1000_CTRL_FD) ? E1000_STATUS_FD : 0;
2596 } else {
2597 res |= E1000_STATUS_FD;
2598 }
2599
2600 if ((core->mac[CTRL] & E1000_CTRL_FRCSPD) ||
2601 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_SPD_BYPS)) {
2602 switch (core->mac[CTRL] & E1000_CTRL_SPD_SEL) {
2603 case E1000_CTRL_SPD_10:
2604 res |= E1000_STATUS_SPEED_10;
2605 break;
2606 case E1000_CTRL_SPD_100:
2607 res |= E1000_STATUS_SPEED_100;
2608 break;
2609 case E1000_CTRL_SPD_1000:
2610 default:
2611 res |= E1000_STATUS_SPEED_1000;
2612 break;
2613 }
2614 } else {
2615 res |= E1000_STATUS_SPEED_1000;
2616 }
2617
2618 if (num_vfs) {
2619 res |= num_vfs << E1000_STATUS_NUM_VFS_SHIFT;
2620 res |= E1000_STATUS_IOV_MODE;
2621 }
2622
2623 /*
2624 * Windows driver 12.18.9.23 resets if E1000_STATUS_GIO_MASTER_ENABLE is
2625 * left set after E1000_CTRL_LRST is set.
2626 */
2627 if (!(core->mac[CTRL] & E1000_CTRL_GIO_MASTER_DISABLE) &&
2628 !(core->mac[CTRL] & E1000_CTRL_LRST)) {
2629 res |= E1000_STATUS_GIO_MASTER_ENABLE;
2630 }
2631
2632 return res;
2633 }
2634
2635 static void
2636 igb_mac_writereg(IGBCore *core, int index, uint32_t val)
2637 {
2638 core->mac[index] = val;
2639 }
2640
2641 static void
2642 igb_mac_setmacaddr(IGBCore *core, int index, uint32_t val)
2643 {
2644 uint32_t macaddr[2];
2645
2646 core->mac[index] = val;
2647
2648 macaddr[0] = cpu_to_le32(core->mac[RA]);
2649 macaddr[1] = cpu_to_le32(core->mac[RA + 1]);
2650 qemu_format_nic_info_str(qemu_get_queue(core->owner_nic),
2651 (uint8_t *) macaddr);
2652
2653 trace_e1000e_mac_set_sw(MAC_ARG(macaddr));
2654 }
2655
2656 static void
2657 igb_set_eecd(IGBCore *core, int index, uint32_t val)
2658 {
2659 static const uint32_t ro_bits = E1000_EECD_PRES |
2660 E1000_EECD_AUTO_RD |
2661 E1000_EECD_SIZE_EX_MASK;
2662
2663 core->mac[EECD] = (core->mac[EECD] & ro_bits) | (val & ~ro_bits);
2664 }
2665
2666 static void
2667 igb_set_eerd(IGBCore *core, int index, uint32_t val)
2668 {
2669 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK;
2670 uint32_t flags = 0;
2671 uint32_t data = 0;
2672
2673 if ((addr < IGB_EEPROM_SIZE) && (val & E1000_EERW_START)) {
2674 data = core->eeprom[addr];
2675 flags = E1000_EERW_DONE;
2676 }
2677
2678 core->mac[EERD] = flags |
2679 (addr << E1000_EERW_ADDR_SHIFT) |
2680 (data << E1000_EERW_DATA_SHIFT);
2681 }
2682
2683 static void
2684 igb_set_eitr(IGBCore *core, int index, uint32_t val)
2685 {
2686 uint32_t eitr_num = index - EITR0;
2687
2688 trace_igb_irq_eitr_set(eitr_num, val);
2689
2690 core->eitr_guest_value[eitr_num] = val & ~E1000_EITR_CNT_IGNR;
2691 core->mac[index] = val & 0x7FFE;
2692 }
2693
2694 static void
2695 igb_update_rx_offloads(IGBCore *core)
2696 {
2697 int cso_state = igb_rx_l4_cso_enabled(core);
2698
2699 trace_e1000e_rx_set_cso(cso_state);
2700
2701 if (core->has_vnet) {
2702 qemu_set_offload(qemu_get_queue(core->owner_nic)->peer,
2703 cso_state, 0, 0, 0, 0);
2704 }
2705 }
2706
2707 static void
2708 igb_set_rxcsum(IGBCore *core, int index, uint32_t val)
2709 {
2710 core->mac[RXCSUM] = val;
2711 igb_update_rx_offloads(core);
2712 }
2713
2714 static void
2715 igb_set_gcr(IGBCore *core, int index, uint32_t val)
2716 {
2717 uint32_t ro_bits = core->mac[GCR] & E1000_GCR_RO_BITS;
2718 core->mac[GCR] = (val & ~E1000_GCR_RO_BITS) | ro_bits;
2719 }
2720
2721 static uint32_t igb_get_systiml(IGBCore *core, int index)
2722 {
2723 e1000x_timestamp(core->mac, core->timadj, SYSTIML, SYSTIMH);
2724 return core->mac[SYSTIML];
2725 }
2726
2727 static uint32_t igb_get_rxsatrh(IGBCore *core, int index)
2728 {
2729 core->mac[TSYNCRXCTL] &= ~E1000_TSYNCRXCTL_VALID;
2730 return core->mac[RXSATRH];
2731 }
2732
2733 static uint32_t igb_get_txstmph(IGBCore *core, int index)
2734 {
2735 core->mac[TSYNCTXCTL] &= ~E1000_TSYNCTXCTL_VALID;
2736 return core->mac[TXSTMPH];
2737 }
2738
2739 static void igb_set_timinca(IGBCore *core, int index, uint32_t val)
2740 {
2741 e1000x_set_timinca(core->mac, &core->timadj, val);
2742 }
2743
2744 static void igb_set_timadjh(IGBCore *core, int index, uint32_t val)
2745 {
2746 core->mac[TIMADJH] = val;
2747 core->timadj += core->mac[TIMADJL] | ((int64_t)core->mac[TIMADJH] << 32);
2748 }
2749
2750 #define igb_getreg(x) [x] = igb_mac_readreg
2751 typedef uint32_t (*readops)(IGBCore *, int);
2752 static const readops igb_macreg_readops[] = {
2753 igb_getreg(WUFC),
2754 igb_getreg(MANC),
2755 igb_getreg(TOTL),
2756 igb_getreg(RDT0),
2757 igb_getreg(RDT1),
2758 igb_getreg(RDT2),
2759 igb_getreg(RDT3),
2760 igb_getreg(RDT4),
2761 igb_getreg(RDT5),
2762 igb_getreg(RDT6),
2763 igb_getreg(RDT7),
2764 igb_getreg(RDT8),
2765 igb_getreg(RDT9),
2766 igb_getreg(RDT10),
2767 igb_getreg(RDT11),
2768 igb_getreg(RDT12),
2769 igb_getreg(RDT13),
2770 igb_getreg(RDT14),
2771 igb_getreg(RDT15),
2772 igb_getreg(RDBAH0),
2773 igb_getreg(RDBAH1),
2774 igb_getreg(RDBAH2),
2775 igb_getreg(RDBAH3),
2776 igb_getreg(RDBAH4),
2777 igb_getreg(RDBAH5),
2778 igb_getreg(RDBAH6),
2779 igb_getreg(RDBAH7),
2780 igb_getreg(RDBAH8),
2781 igb_getreg(RDBAH9),
2782 igb_getreg(RDBAH10),
2783 igb_getreg(RDBAH11),
2784 igb_getreg(RDBAH12),
2785 igb_getreg(RDBAH13),
2786 igb_getreg(RDBAH14),
2787 igb_getreg(RDBAH15),
2788 igb_getreg(TDBAL0),
2789 igb_getreg(TDBAL1),
2790 igb_getreg(TDBAL2),
2791 igb_getreg(TDBAL3),
2792 igb_getreg(TDBAL4),
2793 igb_getreg(TDBAL5),
2794 igb_getreg(TDBAL6),
2795 igb_getreg(TDBAL7),
2796 igb_getreg(TDBAL8),
2797 igb_getreg(TDBAL9),
2798 igb_getreg(TDBAL10),
2799 igb_getreg(TDBAL11),
2800 igb_getreg(TDBAL12),
2801 igb_getreg(TDBAL13),
2802 igb_getreg(TDBAL14),
2803 igb_getreg(TDBAL15),
2804 igb_getreg(RDLEN0),
2805 igb_getreg(RDLEN1),
2806 igb_getreg(RDLEN2),
2807 igb_getreg(RDLEN3),
2808 igb_getreg(RDLEN4),
2809 igb_getreg(RDLEN5),
2810 igb_getreg(RDLEN6),
2811 igb_getreg(RDLEN7),
2812 igb_getreg(RDLEN8),
2813 igb_getreg(RDLEN9),
2814 igb_getreg(RDLEN10),
2815 igb_getreg(RDLEN11),
2816 igb_getreg(RDLEN12),
2817 igb_getreg(RDLEN13),
2818 igb_getreg(RDLEN14),
2819 igb_getreg(RDLEN15),
2820 igb_getreg(SRRCTL0),
2821 igb_getreg(SRRCTL1),
2822 igb_getreg(SRRCTL2),
2823 igb_getreg(SRRCTL3),
2824 igb_getreg(SRRCTL4),
2825 igb_getreg(SRRCTL5),
2826 igb_getreg(SRRCTL6),
2827 igb_getreg(SRRCTL7),
2828 igb_getreg(SRRCTL8),
2829 igb_getreg(SRRCTL9),
2830 igb_getreg(SRRCTL10),
2831 igb_getreg(SRRCTL11),
2832 igb_getreg(SRRCTL12),
2833 igb_getreg(SRRCTL13),
2834 igb_getreg(SRRCTL14),
2835 igb_getreg(SRRCTL15),
2836 igb_getreg(LATECOL),
2837 igb_getreg(XONTXC),
2838 igb_getreg(TDFH),
2839 igb_getreg(TDFT),
2840 igb_getreg(TDFHS),
2841 igb_getreg(TDFTS),
2842 igb_getreg(TDFPC),
2843 igb_getreg(WUS),
2844 igb_getreg(RDFH),
2845 igb_getreg(RDFT),
2846 igb_getreg(RDFHS),
2847 igb_getreg(RDFTS),
2848 igb_getreg(RDFPC),
2849 igb_getreg(GORCL),
2850 igb_getreg(MGTPRC),
2851 igb_getreg(EERD),
2852 igb_getreg(EIAC),
2853 igb_getreg(MANC2H),
2854 igb_getreg(RXCSUM),
2855 igb_getreg(GSCL_3),
2856 igb_getreg(GSCN_2),
2857 igb_getreg(FCAH),
2858 igb_getreg(FCRTH),
2859 igb_getreg(FLOP),
2860 igb_getreg(RXSTMPH),
2861 igb_getreg(TXSTMPL),
2862 igb_getreg(TIMADJL),
2863 igb_getreg(RDH0),
2864 igb_getreg(RDH1),
2865 igb_getreg(RDH2),
2866 igb_getreg(RDH3),
2867 igb_getreg(RDH4),
2868 igb_getreg(RDH5),
2869 igb_getreg(RDH6),
2870 igb_getreg(RDH7),
2871 igb_getreg(RDH8),
2872 igb_getreg(RDH9),
2873 igb_getreg(RDH10),
2874 igb_getreg(RDH11),
2875 igb_getreg(RDH12),
2876 igb_getreg(RDH13),
2877 igb_getreg(RDH14),
2878 igb_getreg(RDH15),
2879 igb_getreg(TDT0),
2880 igb_getreg(TDT1),
2881 igb_getreg(TDT2),
2882 igb_getreg(TDT3),
2883 igb_getreg(TDT4),
2884 igb_getreg(TDT5),
2885 igb_getreg(TDT6),
2886 igb_getreg(TDT7),
2887 igb_getreg(TDT8),
2888 igb_getreg(TDT9),
2889 igb_getreg(TDT10),
2890 igb_getreg(TDT11),
2891 igb_getreg(TDT12),
2892 igb_getreg(TDT13),
2893 igb_getreg(TDT14),
2894 igb_getreg(TDT15),
2895 igb_getreg(TNCRS),
2896 igb_getreg(RJC),
2897 igb_getreg(IAM),
2898 igb_getreg(GSCL_2),
2899 igb_getreg(TIPG),
2900 igb_getreg(FLMNGCTL),
2901 igb_getreg(FLMNGCNT),
2902 igb_getreg(TSYNCTXCTL),
2903 igb_getreg(EEMNGDATA),
2904 igb_getreg(CTRL_EXT),
2905 igb_getreg(SYSTIMH),
2906 igb_getreg(EEMNGCTL),
2907 igb_getreg(FLMNGDATA),
2908 igb_getreg(TSYNCRXCTL),
2909 igb_getreg(LEDCTL),
2910 igb_getreg(TCTL),
2911 igb_getreg(TCTL_EXT),
2912 igb_getreg(DTXCTL),
2913 igb_getreg(RXPBS),
2914 igb_getreg(TDH0),
2915 igb_getreg(TDH1),
2916 igb_getreg(TDH2),
2917 igb_getreg(TDH3),
2918 igb_getreg(TDH4),
2919 igb_getreg(TDH5),
2920 igb_getreg(TDH6),
2921 igb_getreg(TDH7),
2922 igb_getreg(TDH8),
2923 igb_getreg(TDH9),
2924 igb_getreg(TDH10),
2925 igb_getreg(TDH11),
2926 igb_getreg(TDH12),
2927 igb_getreg(TDH13),
2928 igb_getreg(TDH14),
2929 igb_getreg(TDH15),
2930 igb_getreg(ECOL),
2931 igb_getreg(DC),
2932 igb_getreg(RLEC),
2933 igb_getreg(XOFFTXC),
2934 igb_getreg(RFC),
2935 igb_getreg(RNBC),
2936 igb_getreg(MGTPTC),
2937 igb_getreg(TIMINCA),
2938 igb_getreg(FACTPS),
2939 igb_getreg(GSCL_1),
2940 igb_getreg(GSCN_0),
2941 igb_getreg(PBACLR),
2942 igb_getreg(FCTTV),
2943 igb_getreg(RXSATRL),
2944 igb_getreg(TORL),
2945 igb_getreg(TDLEN0),
2946 igb_getreg(TDLEN1),
2947 igb_getreg(TDLEN2),
2948 igb_getreg(TDLEN3),
2949 igb_getreg(TDLEN4),
2950 igb_getreg(TDLEN5),
2951 igb_getreg(TDLEN6),
2952 igb_getreg(TDLEN7),
2953 igb_getreg(TDLEN8),
2954 igb_getreg(TDLEN9),
2955 igb_getreg(TDLEN10),
2956 igb_getreg(TDLEN11),
2957 igb_getreg(TDLEN12),
2958 igb_getreg(TDLEN13),
2959 igb_getreg(TDLEN14),
2960 igb_getreg(TDLEN15),
2961 igb_getreg(MCC),
2962 igb_getreg(WUC),
2963 igb_getreg(EECD),
2964 igb_getreg(FCRTV),
2965 igb_getreg(TXDCTL0),
2966 igb_getreg(TXDCTL1),
2967 igb_getreg(TXDCTL2),
2968 igb_getreg(TXDCTL3),
2969 igb_getreg(TXDCTL4),
2970 igb_getreg(TXDCTL5),
2971 igb_getreg(TXDCTL6),
2972 igb_getreg(TXDCTL7),
2973 igb_getreg(TXDCTL8),
2974 igb_getreg(TXDCTL9),
2975 igb_getreg(TXDCTL10),
2976 igb_getreg(TXDCTL11),
2977 igb_getreg(TXDCTL12),
2978 igb_getreg(TXDCTL13),
2979 igb_getreg(TXDCTL14),
2980 igb_getreg(TXDCTL15),
2981 igb_getreg(TXCTL0),
2982 igb_getreg(TXCTL1),
2983 igb_getreg(TXCTL2),
2984 igb_getreg(TXCTL3),
2985 igb_getreg(TXCTL4),
2986 igb_getreg(TXCTL5),
2987 igb_getreg(TXCTL6),
2988 igb_getreg(TXCTL7),
2989 igb_getreg(TXCTL8),
2990 igb_getreg(TXCTL9),
2991 igb_getreg(TXCTL10),
2992 igb_getreg(TXCTL11),
2993 igb_getreg(TXCTL12),
2994 igb_getreg(TXCTL13),
2995 igb_getreg(TXCTL14),
2996 igb_getreg(TXCTL15),
2997 igb_getreg(TDWBAL0),
2998 igb_getreg(TDWBAL1),
2999 igb_getreg(TDWBAL2),
3000 igb_getreg(TDWBAL3),
3001 igb_getreg(TDWBAL4),
3002 igb_getreg(TDWBAL5),
3003 igb_getreg(TDWBAL6),
3004 igb_getreg(TDWBAL7),
3005 igb_getreg(TDWBAL8),
3006 igb_getreg(TDWBAL9),
3007 igb_getreg(TDWBAL10),
3008 igb_getreg(TDWBAL11),
3009 igb_getreg(TDWBAL12),
3010 igb_getreg(TDWBAL13),
3011 igb_getreg(TDWBAL14),
3012 igb_getreg(TDWBAL15),
3013 igb_getreg(TDWBAH0),
3014 igb_getreg(TDWBAH1),
3015 igb_getreg(TDWBAH2),
3016 igb_getreg(TDWBAH3),
3017 igb_getreg(TDWBAH4),
3018 igb_getreg(TDWBAH5),
3019 igb_getreg(TDWBAH6),
3020 igb_getreg(TDWBAH7),
3021 igb_getreg(TDWBAH8),
3022 igb_getreg(TDWBAH9),
3023 igb_getreg(TDWBAH10),
3024 igb_getreg(TDWBAH11),
3025 igb_getreg(TDWBAH12),
3026 igb_getreg(TDWBAH13),
3027 igb_getreg(TDWBAH14),
3028 igb_getreg(TDWBAH15),
3029 igb_getreg(PVTCTRL0),
3030 igb_getreg(PVTCTRL1),
3031 igb_getreg(PVTCTRL2),
3032 igb_getreg(PVTCTRL3),
3033 igb_getreg(PVTCTRL4),
3034 igb_getreg(PVTCTRL5),
3035 igb_getreg(PVTCTRL6),
3036 igb_getreg(PVTCTRL7),
3037 igb_getreg(PVTEIMS0),
3038 igb_getreg(PVTEIMS1),
3039 igb_getreg(PVTEIMS2),
3040 igb_getreg(PVTEIMS3),
3041 igb_getreg(PVTEIMS4),
3042 igb_getreg(PVTEIMS5),
3043 igb_getreg(PVTEIMS6),
3044 igb_getreg(PVTEIMS7),
3045 igb_getreg(PVTEIAC0),
3046 igb_getreg(PVTEIAC1),
3047 igb_getreg(PVTEIAC2),
3048 igb_getreg(PVTEIAC3),
3049 igb_getreg(PVTEIAC4),
3050 igb_getreg(PVTEIAC5),
3051 igb_getreg(PVTEIAC6),
3052 igb_getreg(PVTEIAC7),
3053 igb_getreg(PVTEIAM0),
3054 igb_getreg(PVTEIAM1),
3055 igb_getreg(PVTEIAM2),
3056 igb_getreg(PVTEIAM3),
3057 igb_getreg(PVTEIAM4),
3058 igb_getreg(PVTEIAM5),
3059 igb_getreg(PVTEIAM6),
3060 igb_getreg(PVTEIAM7),
3061 igb_getreg(PVFGPRC0),
3062 igb_getreg(PVFGPRC1),
3063 igb_getreg(PVFGPRC2),
3064 igb_getreg(PVFGPRC3),
3065 igb_getreg(PVFGPRC4),
3066 igb_getreg(PVFGPRC5),
3067 igb_getreg(PVFGPRC6),
3068 igb_getreg(PVFGPRC7),
3069 igb_getreg(PVFGPTC0),
3070 igb_getreg(PVFGPTC1),
3071 igb_getreg(PVFGPTC2),
3072 igb_getreg(PVFGPTC3),
3073 igb_getreg(PVFGPTC4),
3074 igb_getreg(PVFGPTC5),
3075 igb_getreg(PVFGPTC6),
3076 igb_getreg(PVFGPTC7),
3077 igb_getreg(PVFGORC0),
3078 igb_getreg(PVFGORC1),
3079 igb_getreg(PVFGORC2),
3080 igb_getreg(PVFGORC3),
3081 igb_getreg(PVFGORC4),
3082 igb_getreg(PVFGORC5),
3083 igb_getreg(PVFGORC6),
3084 igb_getreg(PVFGORC7),
3085 igb_getreg(PVFGOTC0),
3086 igb_getreg(PVFGOTC1),
3087 igb_getreg(PVFGOTC2),
3088 igb_getreg(PVFGOTC3),
3089 igb_getreg(PVFGOTC4),
3090 igb_getreg(PVFGOTC5),
3091 igb_getreg(PVFGOTC6),
3092 igb_getreg(PVFGOTC7),
3093 igb_getreg(PVFMPRC0),
3094 igb_getreg(PVFMPRC1),
3095 igb_getreg(PVFMPRC2),
3096 igb_getreg(PVFMPRC3),
3097 igb_getreg(PVFMPRC4),
3098 igb_getreg(PVFMPRC5),
3099 igb_getreg(PVFMPRC6),
3100 igb_getreg(PVFMPRC7),
3101 igb_getreg(PVFGPRLBC0),
3102 igb_getreg(PVFGPRLBC1),
3103 igb_getreg(PVFGPRLBC2),
3104 igb_getreg(PVFGPRLBC3),
3105 igb_getreg(PVFGPRLBC4),
3106 igb_getreg(PVFGPRLBC5),
3107 igb_getreg(PVFGPRLBC6),
3108 igb_getreg(PVFGPRLBC7),
3109 igb_getreg(PVFGPTLBC0),
3110 igb_getreg(PVFGPTLBC1),
3111 igb_getreg(PVFGPTLBC2),
3112 igb_getreg(PVFGPTLBC3),
3113 igb_getreg(PVFGPTLBC4),
3114 igb_getreg(PVFGPTLBC5),
3115 igb_getreg(PVFGPTLBC6),
3116 igb_getreg(PVFGPTLBC7),
3117 igb_getreg(PVFGORLBC0),
3118 igb_getreg(PVFGORLBC1),
3119 igb_getreg(PVFGORLBC2),
3120 igb_getreg(PVFGORLBC3),
3121 igb_getreg(PVFGORLBC4),
3122 igb_getreg(PVFGORLBC5),
3123 igb_getreg(PVFGORLBC6),
3124 igb_getreg(PVFGORLBC7),
3125 igb_getreg(PVFGOTLBC0),
3126 igb_getreg(PVFGOTLBC1),
3127 igb_getreg(PVFGOTLBC2),
3128 igb_getreg(PVFGOTLBC3),
3129 igb_getreg(PVFGOTLBC4),
3130 igb_getreg(PVFGOTLBC5),
3131 igb_getreg(PVFGOTLBC6),
3132 igb_getreg(PVFGOTLBC7),
3133 igb_getreg(RCTL),
3134 igb_getreg(MDIC),
3135 igb_getreg(FCRUC),
3136 igb_getreg(VET),
3137 igb_getreg(RDBAL0),
3138 igb_getreg(RDBAL1),
3139 igb_getreg(RDBAL2),
3140 igb_getreg(RDBAL3),
3141 igb_getreg(RDBAL4),
3142 igb_getreg(RDBAL5),
3143 igb_getreg(RDBAL6),
3144 igb_getreg(RDBAL7),
3145 igb_getreg(RDBAL8),
3146 igb_getreg(RDBAL9),
3147 igb_getreg(RDBAL10),
3148 igb_getreg(RDBAL11),
3149 igb_getreg(RDBAL12),
3150 igb_getreg(RDBAL13),
3151 igb_getreg(RDBAL14),
3152 igb_getreg(RDBAL15),
3153 igb_getreg(TDBAH0),
3154 igb_getreg(TDBAH1),
3155 igb_getreg(TDBAH2),
3156 igb_getreg(TDBAH3),
3157 igb_getreg(TDBAH4),
3158 igb_getreg(TDBAH5),
3159 igb_getreg(TDBAH6),
3160 igb_getreg(TDBAH7),
3161 igb_getreg(TDBAH8),
3162 igb_getreg(TDBAH9),
3163 igb_getreg(TDBAH10),
3164 igb_getreg(TDBAH11),
3165 igb_getreg(TDBAH12),
3166 igb_getreg(TDBAH13),
3167 igb_getreg(TDBAH14),
3168 igb_getreg(TDBAH15),
3169 igb_getreg(SCC),
3170 igb_getreg(COLC),
3171 igb_getreg(XOFFRXC),
3172 igb_getreg(IPAV),
3173 igb_getreg(GOTCL),
3174 igb_getreg(MGTPDC),
3175 igb_getreg(GCR),
3176 igb_getreg(MFVAL),
3177 igb_getreg(FUNCTAG),
3178 igb_getreg(GSCL_4),
3179 igb_getreg(GSCN_3),
3180 igb_getreg(MRQC),
3181 igb_getreg(FCT),
3182 igb_getreg(FLA),
3183 igb_getreg(RXDCTL0),
3184 igb_getreg(RXDCTL1),
3185 igb_getreg(RXDCTL2),
3186 igb_getreg(RXDCTL3),
3187 igb_getreg(RXDCTL4),
3188 igb_getreg(RXDCTL5),
3189 igb_getreg(RXDCTL6),
3190 igb_getreg(RXDCTL7),
3191 igb_getreg(RXDCTL8),
3192 igb_getreg(RXDCTL9),
3193 igb_getreg(RXDCTL10),
3194 igb_getreg(RXDCTL11),
3195 igb_getreg(RXDCTL12),
3196 igb_getreg(RXDCTL13),
3197 igb_getreg(RXDCTL14),
3198 igb_getreg(RXDCTL15),
3199 igb_getreg(RXSTMPL),
3200 igb_getreg(TIMADJH),
3201 igb_getreg(FCRTL),
3202 igb_getreg(XONRXC),
3203 igb_getreg(RFCTL),
3204 igb_getreg(GSCN_1),
3205 igb_getreg(FCAL),
3206 igb_getreg(GPIE),
3207 igb_getreg(TXPBS),
3208 igb_getreg(RLPML),
3209
3210 [TOTH] = igb_mac_read_clr8,
3211 [GOTCH] = igb_mac_read_clr8,
3212 [PRC64] = igb_mac_read_clr4,
3213 [PRC255] = igb_mac_read_clr4,
3214 [PRC1023] = igb_mac_read_clr4,
3215 [PTC64] = igb_mac_read_clr4,
3216 [PTC255] = igb_mac_read_clr4,
3217 [PTC1023] = igb_mac_read_clr4,
3218 [GPRC] = igb_mac_read_clr4,
3219 [TPT] = igb_mac_read_clr4,
3220 [RUC] = igb_mac_read_clr4,
3221 [BPRC] = igb_mac_read_clr4,
3222 [MPTC] = igb_mac_read_clr4,
3223 [IAC] = igb_mac_read_clr4,
3224 [ICR] = igb_mac_icr_read,
3225 [STATUS] = igb_get_status,
3226 [ICS] = igb_mac_ics_read,
3227 /*
3228 * 8.8.10: Reading the IMC register returns the value of the IMS register.
3229 */
3230 [IMC] = igb_mac_ims_read,
3231 [TORH] = igb_mac_read_clr8,
3232 [GORCH] = igb_mac_read_clr8,
3233 [PRC127] = igb_mac_read_clr4,
3234 [PRC511] = igb_mac_read_clr4,
3235 [PRC1522] = igb_mac_read_clr4,
3236 [PTC127] = igb_mac_read_clr4,
3237 [PTC511] = igb_mac_read_clr4,
3238 [PTC1522] = igb_mac_read_clr4,
3239 [GPTC] = igb_mac_read_clr4,
3240 [TPR] = igb_mac_read_clr4,
3241 [ROC] = igb_mac_read_clr4,
3242 [MPRC] = igb_mac_read_clr4,
3243 [BPTC] = igb_mac_read_clr4,
3244 [TSCTC] = igb_mac_read_clr4,
3245 [CTRL] = igb_get_ctrl,
3246 [SWSM] = igb_mac_swsm_read,
3247 [IMS] = igb_mac_ims_read,
3248 [SYSTIML] = igb_get_systiml,
3249 [RXSATRH] = igb_get_rxsatrh,
3250 [TXSTMPH] = igb_get_txstmph,
3251
3252 [CRCERRS ... MPC] = igb_mac_readreg,
3253 [IP6AT ... IP6AT + 3] = igb_mac_readreg,
3254 [IP4AT ... IP4AT + 6] = igb_mac_readreg,
3255 [RA ... RA + 31] = igb_mac_readreg,
3256 [RA2 ... RA2 + 31] = igb_mac_readreg,
3257 [WUPM ... WUPM + 31] = igb_mac_readreg,
3258 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = igb_mac_readreg,
3259 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = igb_mac_readreg,
3260 [FFMT ... FFMT + 254] = igb_mac_readreg,
3261 [MDEF ... MDEF + 7] = igb_mac_readreg,
3262 [FTFT ... FTFT + 254] = igb_mac_readreg,
3263 [RETA ... RETA + 31] = igb_mac_readreg,
3264 [RSSRK ... RSSRK + 9] = igb_mac_readreg,
3265 [MAVTV0 ... MAVTV3] = igb_mac_readreg,
3266 [EITR0 ... EITR0 + IGB_INTR_NUM - 1] = igb_mac_eitr_read,
3267 [PVTEICR0] = igb_mac_read_clr4,
3268 [PVTEICR1] = igb_mac_read_clr4,
3269 [PVTEICR2] = igb_mac_read_clr4,
3270 [PVTEICR3] = igb_mac_read_clr4,
3271 [PVTEICR4] = igb_mac_read_clr4,
3272 [PVTEICR5] = igb_mac_read_clr4,
3273 [PVTEICR6] = igb_mac_read_clr4,
3274 [PVTEICR7] = igb_mac_read_clr4,
3275
3276 /* IGB specific: */
3277 [FWSM] = igb_mac_readreg,
3278 [SW_FW_SYNC] = igb_mac_readreg,
3279 [HTCBDPC] = igb_mac_read_clr4,
3280 [EICR] = igb_mac_read_clr4,
3281 [EIMS] = igb_mac_readreg,
3282 [EIAM] = igb_mac_readreg,
3283 [IVAR0 ... IVAR0 + 7] = igb_mac_readreg,
3284 igb_getreg(IVAR_MISC),
3285 igb_getreg(VT_CTL),
3286 [P2VMAILBOX0 ... P2VMAILBOX7] = igb_mac_readreg,
3287 [V2PMAILBOX0 ... V2PMAILBOX7] = igb_mac_vfmailbox_read,
3288 igb_getreg(MBVFICR),
3289 [VMBMEM0 ... VMBMEM0 + 127] = igb_mac_readreg,
3290 igb_getreg(MBVFIMR),
3291 igb_getreg(VFLRE),
3292 igb_getreg(VFRE),
3293 igb_getreg(VFTE),
3294 igb_getreg(QDE),
3295 igb_getreg(DTXSWC),
3296 igb_getreg(RPLOLR),
3297 [VLVF0 ... VLVF0 + E1000_VLVF_ARRAY_SIZE - 1] = igb_mac_readreg,
3298 [VMVIR0 ... VMVIR7] = igb_mac_readreg,
3299 [VMOLR0 ... VMOLR7] = igb_mac_readreg,
3300 [WVBR] = igb_mac_read_clr4,
3301 [RQDPC0] = igb_mac_read_clr4,
3302 [RQDPC1] = igb_mac_read_clr4,
3303 [RQDPC2] = igb_mac_read_clr4,
3304 [RQDPC3] = igb_mac_read_clr4,
3305 [RQDPC4] = igb_mac_read_clr4,
3306 [RQDPC5] = igb_mac_read_clr4,
3307 [RQDPC6] = igb_mac_read_clr4,
3308 [RQDPC7] = igb_mac_read_clr4,
3309 [RQDPC8] = igb_mac_read_clr4,
3310 [RQDPC9] = igb_mac_read_clr4,
3311 [RQDPC10] = igb_mac_read_clr4,
3312 [RQDPC11] = igb_mac_read_clr4,
3313 [RQDPC12] = igb_mac_read_clr4,
3314 [RQDPC13] = igb_mac_read_clr4,
3315 [RQDPC14] = igb_mac_read_clr4,
3316 [RQDPC15] = igb_mac_read_clr4,
3317 [VTIVAR ... VTIVAR + 7] = igb_mac_readreg,
3318 [VTIVAR_MISC ... VTIVAR_MISC + 7] = igb_mac_readreg,
3319 };
3320 enum { IGB_NREADOPS = ARRAY_SIZE(igb_macreg_readops) };
3321
3322 #define igb_putreg(x) [x] = igb_mac_writereg
3323 typedef void (*writeops)(IGBCore *, int, uint32_t);
3324 static const writeops igb_macreg_writeops[] = {
3325 igb_putreg(SWSM),
3326 igb_putreg(WUFC),
3327 igb_putreg(RDBAH0),
3328 igb_putreg(RDBAH1),
3329 igb_putreg(RDBAH2),
3330 igb_putreg(RDBAH3),
3331 igb_putreg(RDBAH4),
3332 igb_putreg(RDBAH5),
3333 igb_putreg(RDBAH6),
3334 igb_putreg(RDBAH7),
3335 igb_putreg(RDBAH8),
3336 igb_putreg(RDBAH9),
3337 igb_putreg(RDBAH10),
3338 igb_putreg(RDBAH11),
3339 igb_putreg(RDBAH12),
3340 igb_putreg(RDBAH13),
3341 igb_putreg(RDBAH14),
3342 igb_putreg(RDBAH15),
3343 igb_putreg(SRRCTL0),
3344 igb_putreg(SRRCTL1),
3345 igb_putreg(SRRCTL2),
3346 igb_putreg(SRRCTL3),
3347 igb_putreg(SRRCTL4),
3348 igb_putreg(SRRCTL5),
3349 igb_putreg(SRRCTL6),
3350 igb_putreg(SRRCTL7),
3351 igb_putreg(SRRCTL8),
3352 igb_putreg(SRRCTL9),
3353 igb_putreg(SRRCTL10),
3354 igb_putreg(SRRCTL11),
3355 igb_putreg(SRRCTL12),
3356 igb_putreg(SRRCTL13),
3357 igb_putreg(SRRCTL14),
3358 igb_putreg(SRRCTL15),
3359 igb_putreg(RXDCTL0),
3360 igb_putreg(RXDCTL1),
3361 igb_putreg(RXDCTL2),
3362 igb_putreg(RXDCTL3),
3363 igb_putreg(RXDCTL4),
3364 igb_putreg(RXDCTL5),
3365 igb_putreg(RXDCTL6),
3366 igb_putreg(RXDCTL7),
3367 igb_putreg(RXDCTL8),
3368 igb_putreg(RXDCTL9),
3369 igb_putreg(RXDCTL10),
3370 igb_putreg(RXDCTL11),
3371 igb_putreg(RXDCTL12),
3372 igb_putreg(RXDCTL13),
3373 igb_putreg(RXDCTL14),
3374 igb_putreg(RXDCTL15),
3375 igb_putreg(LEDCTL),
3376 igb_putreg(TCTL),
3377 igb_putreg(TCTL_EXT),
3378 igb_putreg(DTXCTL),
3379 igb_putreg(RXPBS),
3380 igb_putreg(RQDPC0),
3381 igb_putreg(FCAL),
3382 igb_putreg(FCRUC),
3383 igb_putreg(WUC),
3384 igb_putreg(WUS),
3385 igb_putreg(IPAV),
3386 igb_putreg(TDBAH0),
3387 igb_putreg(TDBAH1),
3388 igb_putreg(TDBAH2),
3389 igb_putreg(TDBAH3),
3390 igb_putreg(TDBAH4),
3391 igb_putreg(TDBAH5),
3392 igb_putreg(TDBAH6),
3393 igb_putreg(TDBAH7),
3394 igb_putreg(TDBAH8),
3395 igb_putreg(TDBAH9),
3396 igb_putreg(TDBAH10),
3397 igb_putreg(TDBAH11),
3398 igb_putreg(TDBAH12),
3399 igb_putreg(TDBAH13),
3400 igb_putreg(TDBAH14),
3401 igb_putreg(TDBAH15),
3402 igb_putreg(IAM),
3403 igb_putreg(MANC),
3404 igb_putreg(MANC2H),
3405 igb_putreg(MFVAL),
3406 igb_putreg(FACTPS),
3407 igb_putreg(FUNCTAG),
3408 igb_putreg(GSCL_1),
3409 igb_putreg(GSCL_2),
3410 igb_putreg(GSCL_3),
3411 igb_putreg(GSCL_4),
3412 igb_putreg(GSCN_0),
3413 igb_putreg(GSCN_1),
3414 igb_putreg(GSCN_2),
3415 igb_putreg(GSCN_3),
3416 igb_putreg(MRQC),
3417 igb_putreg(FLOP),
3418 igb_putreg(FLA),
3419 igb_putreg(TXDCTL0),
3420 igb_putreg(TXDCTL1),
3421 igb_putreg(TXDCTL2),
3422 igb_putreg(TXDCTL3),
3423 igb_putreg(TXDCTL4),
3424 igb_putreg(TXDCTL5),
3425 igb_putreg(TXDCTL6),
3426 igb_putreg(TXDCTL7),
3427 igb_putreg(TXDCTL8),
3428 igb_putreg(TXDCTL9),
3429 igb_putreg(TXDCTL10),
3430 igb_putreg(TXDCTL11),
3431 igb_putreg(TXDCTL12),
3432 igb_putreg(TXDCTL13),
3433 igb_putreg(TXDCTL14),
3434 igb_putreg(TXDCTL15),
3435 igb_putreg(TXCTL0),
3436 igb_putreg(TXCTL1),
3437 igb_putreg(TXCTL2),
3438 igb_putreg(TXCTL3),
3439 igb_putreg(TXCTL4),
3440 igb_putreg(TXCTL5),
3441 igb_putreg(TXCTL6),
3442 igb_putreg(TXCTL7),
3443 igb_putreg(TXCTL8),
3444 igb_putreg(TXCTL9),
3445 igb_putreg(TXCTL10),
3446 igb_putreg(TXCTL11),
3447 igb_putreg(TXCTL12),
3448 igb_putreg(TXCTL13),
3449 igb_putreg(TXCTL14),
3450 igb_putreg(TXCTL15),
3451 igb_putreg(TDWBAL0),
3452 igb_putreg(TDWBAL1),
3453 igb_putreg(TDWBAL2),
3454 igb_putreg(TDWBAL3),
3455 igb_putreg(TDWBAL4),
3456 igb_putreg(TDWBAL5),
3457 igb_putreg(TDWBAL6),
3458 igb_putreg(TDWBAL7),
3459 igb_putreg(TDWBAL8),
3460 igb_putreg(TDWBAL9),
3461 igb_putreg(TDWBAL10),
3462 igb_putreg(TDWBAL11),
3463 igb_putreg(TDWBAL12),
3464 igb_putreg(TDWBAL13),
3465 igb_putreg(TDWBAL14),
3466 igb_putreg(TDWBAL15),
3467 igb_putreg(TDWBAH0),
3468 igb_putreg(TDWBAH1),
3469 igb_putreg(TDWBAH2),
3470 igb_putreg(TDWBAH3),
3471 igb_putreg(TDWBAH4),
3472 igb_putreg(TDWBAH5),
3473 igb_putreg(TDWBAH6),
3474 igb_putreg(TDWBAH7),
3475 igb_putreg(TDWBAH8),
3476 igb_putreg(TDWBAH9),
3477 igb_putreg(TDWBAH10),
3478 igb_putreg(TDWBAH11),
3479 igb_putreg(TDWBAH12),
3480 igb_putreg(TDWBAH13),
3481 igb_putreg(TDWBAH14),
3482 igb_putreg(TDWBAH15),
3483 igb_putreg(TIPG),
3484 igb_putreg(RXSTMPH),
3485 igb_putreg(RXSTMPL),
3486 igb_putreg(RXSATRL),
3487 igb_putreg(RXSATRH),
3488 igb_putreg(TXSTMPL),
3489 igb_putreg(TXSTMPH),
3490 igb_putreg(SYSTIML),
3491 igb_putreg(SYSTIMH),
3492 igb_putreg(TIMADJL),
3493 igb_putreg(TSYNCRXCTL),
3494 igb_putreg(TSYNCTXCTL),
3495 igb_putreg(EEMNGCTL),
3496 igb_putreg(GPIE),
3497 igb_putreg(TXPBS),
3498 igb_putreg(RLPML),
3499 igb_putreg(VET),
3500
3501 [TDH0] = igb_set_16bit,
3502 [TDH1] = igb_set_16bit,
3503 [TDH2] = igb_set_16bit,
3504 [TDH3] = igb_set_16bit,
3505 [TDH4] = igb_set_16bit,
3506 [TDH5] = igb_set_16bit,
3507 [TDH6] = igb_set_16bit,
3508 [TDH7] = igb_set_16bit,
3509 [TDH8] = igb_set_16bit,
3510 [TDH9] = igb_set_16bit,
3511 [TDH10] = igb_set_16bit,
3512 [TDH11] = igb_set_16bit,
3513 [TDH12] = igb_set_16bit,
3514 [TDH13] = igb_set_16bit,
3515 [TDH14] = igb_set_16bit,
3516 [TDH15] = igb_set_16bit,
3517 [TDT0] = igb_set_tdt,
3518 [TDT1] = igb_set_tdt,
3519 [TDT2] = igb_set_tdt,
3520 [TDT3] = igb_set_tdt,
3521 [TDT4] = igb_set_tdt,
3522 [TDT5] = igb_set_tdt,
3523 [TDT6] = igb_set_tdt,
3524 [TDT7] = igb_set_tdt,
3525 [TDT8] = igb_set_tdt,
3526 [TDT9] = igb_set_tdt,
3527 [TDT10] = igb_set_tdt,
3528 [TDT11] = igb_set_tdt,
3529 [TDT12] = igb_set_tdt,
3530 [TDT13] = igb_set_tdt,
3531 [TDT14] = igb_set_tdt,
3532 [TDT15] = igb_set_tdt,
3533 [MDIC] = igb_set_mdic,
3534 [ICS] = igb_set_ics,
3535 [RDH0] = igb_set_16bit,
3536 [RDH1] = igb_set_16bit,
3537 [RDH2] = igb_set_16bit,
3538 [RDH3] = igb_set_16bit,
3539 [RDH4] = igb_set_16bit,
3540 [RDH5] = igb_set_16bit,
3541 [RDH6] = igb_set_16bit,
3542 [RDH7] = igb_set_16bit,
3543 [RDH8] = igb_set_16bit,
3544 [RDH9] = igb_set_16bit,
3545 [RDH10] = igb_set_16bit,
3546 [RDH11] = igb_set_16bit,
3547 [RDH12] = igb_set_16bit,
3548 [RDH13] = igb_set_16bit,
3549 [RDH14] = igb_set_16bit,
3550 [RDH15] = igb_set_16bit,
3551 [RDT0] = igb_set_rdt,
3552 [RDT1] = igb_set_rdt,
3553 [RDT2] = igb_set_rdt,
3554 [RDT3] = igb_set_rdt,
3555 [RDT4] = igb_set_rdt,
3556 [RDT5] = igb_set_rdt,
3557 [RDT6] = igb_set_rdt,
3558 [RDT7] = igb_set_rdt,
3559 [RDT8] = igb_set_rdt,
3560 [RDT9] = igb_set_rdt,
3561 [RDT10] = igb_set_rdt,
3562 [RDT11] = igb_set_rdt,
3563 [RDT12] = igb_set_rdt,
3564 [RDT13] = igb_set_rdt,
3565 [RDT14] = igb_set_rdt,
3566 [RDT15] = igb_set_rdt,
3567 [IMC] = igb_set_imc,
3568 [IMS] = igb_set_ims,
3569 [ICR] = igb_set_icr,
3570 [EECD] = igb_set_eecd,
3571 [RCTL] = igb_set_rx_control,
3572 [CTRL] = igb_set_ctrl,
3573 [EERD] = igb_set_eerd,
3574 [TDFH] = igb_set_13bit,
3575 [TDFT] = igb_set_13bit,
3576 [TDFHS] = igb_set_13bit,
3577 [TDFTS] = igb_set_13bit,
3578 [TDFPC] = igb_set_13bit,
3579 [RDFH] = igb_set_13bit,
3580 [RDFT] = igb_set_13bit,
3581 [RDFHS] = igb_set_13bit,
3582 [RDFTS] = igb_set_13bit,
3583 [RDFPC] = igb_set_13bit,
3584 [GCR] = igb_set_gcr,
3585 [RXCSUM] = igb_set_rxcsum,
3586 [TDLEN0] = igb_set_dlen,
3587 [TDLEN1] = igb_set_dlen,
3588 [TDLEN2] = igb_set_dlen,
3589 [TDLEN3] = igb_set_dlen,
3590 [TDLEN4] = igb_set_dlen,
3591 [TDLEN5] = igb_set_dlen,
3592 [TDLEN6] = igb_set_dlen,
3593 [TDLEN7] = igb_set_dlen,
3594 [TDLEN8] = igb_set_dlen,
3595 [TDLEN9] = igb_set_dlen,
3596 [TDLEN10] = igb_set_dlen,
3597 [TDLEN11] = igb_set_dlen,
3598 [TDLEN12] = igb_set_dlen,
3599 [TDLEN13] = igb_set_dlen,
3600 [TDLEN14] = igb_set_dlen,
3601 [TDLEN15] = igb_set_dlen,
3602 [RDLEN0] = igb_set_dlen,
3603 [RDLEN1] = igb_set_dlen,
3604 [RDLEN2] = igb_set_dlen,
3605 [RDLEN3] = igb_set_dlen,
3606 [RDLEN4] = igb_set_dlen,
3607 [RDLEN5] = igb_set_dlen,
3608 [RDLEN6] = igb_set_dlen,
3609 [RDLEN7] = igb_set_dlen,
3610 [RDLEN8] = igb_set_dlen,
3611 [RDLEN9] = igb_set_dlen,
3612 [RDLEN10] = igb_set_dlen,
3613 [RDLEN11] = igb_set_dlen,
3614 [RDLEN12] = igb_set_dlen,
3615 [RDLEN13] = igb_set_dlen,
3616 [RDLEN14] = igb_set_dlen,
3617 [RDLEN15] = igb_set_dlen,
3618 [TDBAL0] = igb_set_dbal,
3619 [TDBAL1] = igb_set_dbal,
3620 [TDBAL2] = igb_set_dbal,
3621 [TDBAL3] = igb_set_dbal,
3622 [TDBAL4] = igb_set_dbal,
3623 [TDBAL5] = igb_set_dbal,
3624 [TDBAL6] = igb_set_dbal,
3625 [TDBAL7] = igb_set_dbal,
3626 [TDBAL8] = igb_set_dbal,
3627 [TDBAL9] = igb_set_dbal,
3628 [TDBAL10] = igb_set_dbal,
3629 [TDBAL11] = igb_set_dbal,
3630 [TDBAL12] = igb_set_dbal,
3631 [TDBAL13] = igb_set_dbal,
3632 [TDBAL14] = igb_set_dbal,
3633 [TDBAL15] = igb_set_dbal,
3634 [RDBAL0] = igb_set_dbal,
3635 [RDBAL1] = igb_set_dbal,
3636 [RDBAL2] = igb_set_dbal,
3637 [RDBAL3] = igb_set_dbal,
3638 [RDBAL4] = igb_set_dbal,
3639 [RDBAL5] = igb_set_dbal,
3640 [RDBAL6] = igb_set_dbal,
3641 [RDBAL7] = igb_set_dbal,
3642 [RDBAL8] = igb_set_dbal,
3643 [RDBAL9] = igb_set_dbal,
3644 [RDBAL10] = igb_set_dbal,
3645 [RDBAL11] = igb_set_dbal,
3646 [RDBAL12] = igb_set_dbal,
3647 [RDBAL13] = igb_set_dbal,
3648 [RDBAL14] = igb_set_dbal,
3649 [RDBAL15] = igb_set_dbal,
3650 [STATUS] = igb_set_status,
3651 [PBACLR] = igb_set_pbaclr,
3652 [CTRL_EXT] = igb_set_ctrlext,
3653 [FCAH] = igb_set_16bit,
3654 [FCT] = igb_set_16bit,
3655 [FCTTV] = igb_set_16bit,
3656 [FCRTV] = igb_set_16bit,
3657 [FCRTH] = igb_set_fcrth,
3658 [FCRTL] = igb_set_fcrtl,
3659 [CTRL_DUP] = igb_set_ctrl,
3660 [RFCTL] = igb_set_rfctl,
3661 [TIMINCA] = igb_set_timinca,
3662 [TIMADJH] = igb_set_timadjh,
3663
3664 [IP6AT ... IP6AT + 3] = igb_mac_writereg,
3665 [IP4AT ... IP4AT + 6] = igb_mac_writereg,
3666 [RA] = igb_mac_writereg,
3667 [RA + 1] = igb_mac_setmacaddr,
3668 [RA + 2 ... RA + 31] = igb_mac_writereg,
3669 [RA2 ... RA2 + 31] = igb_mac_writereg,
3670 [WUPM ... WUPM + 31] = igb_mac_writereg,
3671 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = igb_mac_writereg,
3672 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = igb_mac_writereg,
3673 [FFMT ... FFMT + 254] = igb_set_4bit,
3674 [MDEF ... MDEF + 7] = igb_mac_writereg,
3675 [FTFT ... FTFT + 254] = igb_mac_writereg,
3676 [RETA ... RETA + 31] = igb_mac_writereg,
3677 [RSSRK ... RSSRK + 9] = igb_mac_writereg,
3678 [MAVTV0 ... MAVTV3] = igb_mac_writereg,
3679 [EITR0 ... EITR0 + IGB_INTR_NUM - 1] = igb_set_eitr,
3680
3681 /* IGB specific: */
3682 [FWSM] = igb_mac_writereg,
3683 [SW_FW_SYNC] = igb_mac_writereg,
3684 [EICR] = igb_set_eicr,
3685 [EICS] = igb_set_eics,
3686 [EIAC] = igb_set_eiac,
3687 [EIAM] = igb_set_eiam,
3688 [EIMC] = igb_set_eimc,
3689 [EIMS] = igb_set_eims,
3690 [IVAR0 ... IVAR0 + 7] = igb_mac_writereg,
3691 igb_putreg(IVAR_MISC),
3692 igb_putreg(VT_CTL),
3693 [P2VMAILBOX0 ... P2VMAILBOX7] = igb_set_pfmailbox,
3694 [V2PMAILBOX0 ... V2PMAILBOX7] = igb_set_vfmailbox,
3695 [MBVFICR] = igb_w1c,
3696 [VMBMEM0 ... VMBMEM0 + 127] = igb_mac_writereg,
3697 igb_putreg(MBVFIMR),
3698 [VFLRE] = igb_w1c,
3699 igb_putreg(VFRE),
3700 igb_putreg(VFTE),
3701 igb_putreg(QDE),
3702 igb_putreg(DTXSWC),
3703 igb_putreg(RPLOLR),
3704 [VLVF0 ... VLVF0 + E1000_VLVF_ARRAY_SIZE - 1] = igb_mac_writereg,
3705 [VMVIR0 ... VMVIR7] = igb_mac_writereg,
3706 [VMOLR0 ... VMOLR7] = igb_mac_writereg,
3707 [UTA ... UTA + E1000_MC_TBL_SIZE - 1] = igb_mac_writereg,
3708 [PVTCTRL0] = igb_set_vtctrl,
3709 [PVTCTRL1] = igb_set_vtctrl,
3710 [PVTCTRL2] = igb_set_vtctrl,
3711 [PVTCTRL3] = igb_set_vtctrl,
3712 [PVTCTRL4] = igb_set_vtctrl,
3713 [PVTCTRL5] = igb_set_vtctrl,
3714 [PVTCTRL6] = igb_set_vtctrl,
3715 [PVTCTRL7] = igb_set_vtctrl,
3716 [PVTEICS0] = igb_set_vteics,
3717 [PVTEICS1] = igb_set_vteics,
3718 [PVTEICS2] = igb_set_vteics,
3719 [PVTEICS3] = igb_set_vteics,
3720 [PVTEICS4] = igb_set_vteics,
3721 [PVTEICS5] = igb_set_vteics,
3722 [PVTEICS6] = igb_set_vteics,
3723 [PVTEICS7] = igb_set_vteics,
3724 [PVTEIMS0] = igb_set_vteims,
3725 [PVTEIMS1] = igb_set_vteims,
3726 [PVTEIMS2] = igb_set_vteims,
3727 [PVTEIMS3] = igb_set_vteims,
3728 [PVTEIMS4] = igb_set_vteims,
3729 [PVTEIMS5] = igb_set_vteims,
3730 [PVTEIMS6] = igb_set_vteims,
3731 [PVTEIMS7] = igb_set_vteims,
3732 [PVTEIMC0] = igb_set_vteimc,
3733 [PVTEIMC1] = igb_set_vteimc,
3734 [PVTEIMC2] = igb_set_vteimc,
3735 [PVTEIMC3] = igb_set_vteimc,
3736 [PVTEIMC4] = igb_set_vteimc,
3737 [PVTEIMC5] = igb_set_vteimc,
3738 [PVTEIMC6] = igb_set_vteimc,
3739 [PVTEIMC7] = igb_set_vteimc,
3740 [PVTEIAC0] = igb_set_vteiac,
3741 [PVTEIAC1] = igb_set_vteiac,
3742 [PVTEIAC2] = igb_set_vteiac,
3743 [PVTEIAC3] = igb_set_vteiac,
3744 [PVTEIAC4] = igb_set_vteiac,
3745 [PVTEIAC5] = igb_set_vteiac,
3746 [PVTEIAC6] = igb_set_vteiac,
3747 [PVTEIAC7] = igb_set_vteiac,
3748 [PVTEIAM0] = igb_set_vteiam,
3749 [PVTEIAM1] = igb_set_vteiam,
3750 [PVTEIAM2] = igb_set_vteiam,
3751 [PVTEIAM3] = igb_set_vteiam,
3752 [PVTEIAM4] = igb_set_vteiam,
3753 [PVTEIAM5] = igb_set_vteiam,
3754 [PVTEIAM6] = igb_set_vteiam,
3755 [PVTEIAM7] = igb_set_vteiam,
3756 [PVTEICR0] = igb_set_vteicr,
3757 [PVTEICR1] = igb_set_vteicr,
3758 [PVTEICR2] = igb_set_vteicr,
3759 [PVTEICR3] = igb_set_vteicr,
3760 [PVTEICR4] = igb_set_vteicr,
3761 [PVTEICR5] = igb_set_vteicr,
3762 [PVTEICR6] = igb_set_vteicr,
3763 [PVTEICR7] = igb_set_vteicr,
3764 [VTIVAR ... VTIVAR + 7] = igb_set_vtivar,
3765 [VTIVAR_MISC ... VTIVAR_MISC + 7] = igb_mac_writereg
3766 };
3767 enum { IGB_NWRITEOPS = ARRAY_SIZE(igb_macreg_writeops) };
3768
3769 enum { MAC_ACCESS_PARTIAL = 1 };
3770
3771 /*
3772 * The array below combines alias offsets of the index values for the
3773 * MAC registers that have aliases, with the indication of not fully
3774 * implemented registers (lowest bit). This combination is possible
3775 * because all of the offsets are even.
3776 */
3777 static const uint16_t mac_reg_access[E1000E_MAC_SIZE] = {
3778 /* Alias index offsets */
3779 [FCRTL_A] = 0x07fe,
3780 [RDFH_A] = 0xe904, [RDFT_A] = 0xe904,
3781 [TDFH_A] = 0xed00, [TDFT_A] = 0xed00,
3782 [RA_A ... RA_A + 31] = 0x14f0,
3783 [VFTA_A ... VFTA_A + E1000_VLAN_FILTER_TBL_SIZE - 1] = 0x1400,
3784
3785 [RDBAL0_A] = 0x2600,
3786 [RDBAH0_A] = 0x2600,
3787 [RDLEN0_A] = 0x2600,
3788 [SRRCTL0_A] = 0x2600,
3789 [RDH0_A] = 0x2600,
3790 [RDT0_A] = 0x2600,
3791 [RXDCTL0_A] = 0x2600,
3792 [RXCTL0_A] = 0x2600,
3793 [RQDPC0_A] = 0x2600,
3794 [RDBAL1_A] = 0x25D0,
3795 [RDBAL2_A] = 0x25A0,
3796 [RDBAL3_A] = 0x2570,
3797 [RDBAH1_A] = 0x25D0,
3798 [RDBAH2_A] = 0x25A0,
3799 [RDBAH3_A] = 0x2570,
3800 [RDLEN1_A] = 0x25D0,
3801 [RDLEN2_A] = 0x25A0,
3802 [RDLEN3_A] = 0x2570,
3803 [SRRCTL1_A] = 0x25D0,
3804 [SRRCTL2_A] = 0x25A0,
3805 [SRRCTL3_A] = 0x2570,
3806 [RDH1_A] = 0x25D0,
3807 [RDH2_A] = 0x25A0,
3808 [RDH3_A] = 0x2570,
3809 [RDT1_A] = 0x25D0,
3810 [RDT2_A] = 0x25A0,
3811 [RDT3_A] = 0x2570,
3812 [RXDCTL1_A] = 0x25D0,
3813 [RXDCTL2_A] = 0x25A0,
3814 [RXDCTL3_A] = 0x2570,
3815 [RXCTL1_A] = 0x25D0,
3816 [RXCTL2_A] = 0x25A0,
3817 [RXCTL3_A] = 0x2570,
3818 [RQDPC1_A] = 0x25D0,
3819 [RQDPC2_A] = 0x25A0,
3820 [RQDPC3_A] = 0x2570,
3821 [TDBAL0_A] = 0x2A00,
3822 [TDBAH0_A] = 0x2A00,
3823 [TDLEN0_A] = 0x2A00,
3824 [TDH0_A] = 0x2A00,
3825 [TDT0_A] = 0x2A00,
3826 [TXCTL0_A] = 0x2A00,
3827 [TDWBAL0_A] = 0x2A00,
3828 [TDWBAH0_A] = 0x2A00,
3829 [TDBAL1_A] = 0x29D0,
3830 [TDBAL2_A] = 0x29A0,
3831 [TDBAL3_A] = 0x2970,
3832 [TDBAH1_A] = 0x29D0,
3833 [TDBAH2_A] = 0x29A0,
3834 [TDBAH3_A] = 0x2970,
3835 [TDLEN1_A] = 0x29D0,
3836 [TDLEN2_A] = 0x29A0,
3837 [TDLEN3_A] = 0x2970,
3838 [TDH1_A] = 0x29D0,
3839 [TDH2_A] = 0x29A0,
3840 [TDH3_A] = 0x2970,
3841 [TDT1_A] = 0x29D0,
3842 [TDT2_A] = 0x29A0,
3843 [TDT3_A] = 0x2970,
3844 [TXDCTL0_A] = 0x2A00,
3845 [TXDCTL1_A] = 0x29D0,
3846 [TXDCTL2_A] = 0x29A0,
3847 [TXDCTL3_A] = 0x2970,
3848 [TXCTL1_A] = 0x29D0,
3849 [TXCTL2_A] = 0x29A0,
3850 [TXCTL3_A] = 0x29D0,
3851 [TDWBAL1_A] = 0x29D0,
3852 [TDWBAL2_A] = 0x29A0,
3853 [TDWBAL3_A] = 0x2970,
3854 [TDWBAH1_A] = 0x29D0,
3855 [TDWBAH2_A] = 0x29A0,
3856 [TDWBAH3_A] = 0x2970,
3857
3858 /* Access options */
3859 [RDFH] = MAC_ACCESS_PARTIAL, [RDFT] = MAC_ACCESS_PARTIAL,
3860 [RDFHS] = MAC_ACCESS_PARTIAL, [RDFTS] = MAC_ACCESS_PARTIAL,
3861 [RDFPC] = MAC_ACCESS_PARTIAL,
3862 [TDFH] = MAC_ACCESS_PARTIAL, [TDFT] = MAC_ACCESS_PARTIAL,
3863 [TDFHS] = MAC_ACCESS_PARTIAL, [TDFTS] = MAC_ACCESS_PARTIAL,
3864 [TDFPC] = MAC_ACCESS_PARTIAL, [EECD] = MAC_ACCESS_PARTIAL,
3865 [FLA] = MAC_ACCESS_PARTIAL,
3866 [FCAL] = MAC_ACCESS_PARTIAL, [FCAH] = MAC_ACCESS_PARTIAL,
3867 [FCT] = MAC_ACCESS_PARTIAL, [FCTTV] = MAC_ACCESS_PARTIAL,
3868 [FCRTV] = MAC_ACCESS_PARTIAL, [FCRTL] = MAC_ACCESS_PARTIAL,
3869 [FCRTH] = MAC_ACCESS_PARTIAL,
3870 [MAVTV0 ... MAVTV3] = MAC_ACCESS_PARTIAL
3871 };
3872
3873 void
3874 igb_core_write(IGBCore *core, hwaddr addr, uint64_t val, unsigned size)
3875 {
3876 uint16_t index = igb_get_reg_index_with_offset(mac_reg_access, addr);
3877
3878 if (index < IGB_NWRITEOPS && igb_macreg_writeops[index]) {
3879 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) {
3880 trace_e1000e_wrn_regs_write_trivial(index << 2);
3881 }
3882 trace_e1000e_core_write(index << 2, size, val);
3883 igb_macreg_writeops[index](core, index, val);
3884 } else if (index < IGB_NREADOPS && igb_macreg_readops[index]) {
3885 trace_e1000e_wrn_regs_write_ro(index << 2, size, val);
3886 } else {
3887 trace_e1000e_wrn_regs_write_unknown(index << 2, size, val);
3888 }
3889 }
3890
3891 uint64_t
3892 igb_core_read(IGBCore *core, hwaddr addr, unsigned size)
3893 {
3894 uint64_t val;
3895 uint16_t index = igb_get_reg_index_with_offset(mac_reg_access, addr);
3896
3897 if (index < IGB_NREADOPS && igb_macreg_readops[index]) {
3898 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) {
3899 trace_e1000e_wrn_regs_read_trivial(index << 2);
3900 }
3901 val = igb_macreg_readops[index](core, index);
3902 trace_e1000e_core_read(index << 2, size, val);
3903 return val;
3904 } else {
3905 trace_e1000e_wrn_regs_read_unknown(index << 2, size);
3906 }
3907 return 0;
3908 }
3909
3910 static inline void
3911 igb_autoneg_pause(IGBCore *core)
3912 {
3913 timer_del(core->autoneg_timer);
3914 }
3915
3916 static void
3917 igb_autoneg_resume(IGBCore *core)
3918 {
3919 if (igb_have_autoneg(core) &&
3920 !(core->phy[MII_BMSR] & MII_BMSR_AN_COMP)) {
3921 qemu_get_queue(core->owner_nic)->link_down = false;
3922 timer_mod(core->autoneg_timer,
3923 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500);
3924 }
3925 }
3926
3927 static void
3928 igb_vm_state_change(void *opaque, bool running, RunState state)
3929 {
3930 IGBCore *core = opaque;
3931
3932 if (running) {
3933 trace_e1000e_vm_state_running();
3934 igb_intrmgr_resume(core);
3935 igb_autoneg_resume(core);
3936 } else {
3937 trace_e1000e_vm_state_stopped();
3938 igb_autoneg_pause(core);
3939 igb_intrmgr_pause(core);
3940 }
3941 }
3942
3943 void
3944 igb_core_pci_realize(IGBCore *core,
3945 const uint16_t *eeprom_templ,
3946 uint32_t eeprom_size,
3947 const uint8_t *macaddr)
3948 {
3949 int i;
3950
3951 core->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL,
3952 igb_autoneg_timer, core);
3953 igb_intrmgr_pci_realize(core);
3954
3955 core->vmstate = qemu_add_vm_change_state_handler(igb_vm_state_change, core);
3956
3957 for (i = 0; i < IGB_NUM_QUEUES; i++) {
3958 net_tx_pkt_init(&core->tx[i].tx_pkt, NULL, E1000E_MAX_TX_FRAGS);
3959 }
3960
3961 net_rx_pkt_init(&core->rx_pkt);
3962
3963 e1000x_core_prepare_eeprom(core->eeprom,
3964 eeprom_templ,
3965 eeprom_size,
3966 PCI_DEVICE_GET_CLASS(core->owner)->device_id,
3967 macaddr);
3968 igb_update_rx_offloads(core);
3969 }
3970
3971 void
3972 igb_core_pci_uninit(IGBCore *core)
3973 {
3974 int i;
3975
3976 timer_free(core->autoneg_timer);
3977
3978 igb_intrmgr_pci_unint(core);
3979
3980 qemu_del_vm_change_state_handler(core->vmstate);
3981
3982 for (i = 0; i < IGB_NUM_QUEUES; i++) {
3983 net_tx_pkt_reset(core->tx[i].tx_pkt, NULL);
3984 net_tx_pkt_uninit(core->tx[i].tx_pkt);
3985 }
3986
3987 net_rx_pkt_uninit(core->rx_pkt);
3988 }
3989
3990 static const uint16_t
3991 igb_phy_reg_init[] = {
3992 [MII_BMCR] = MII_BMCR_SPEED1000 |
3993 MII_BMCR_FD |
3994 MII_BMCR_AUTOEN,
3995
3996 [MII_BMSR] = MII_BMSR_EXTCAP |
3997 MII_BMSR_LINK_ST |
3998 MII_BMSR_AUTONEG |
3999 MII_BMSR_MFPS |
4000 MII_BMSR_EXTSTAT |
4001 MII_BMSR_10T_HD |
4002 MII_BMSR_10T_FD |
4003 MII_BMSR_100TX_HD |
4004 MII_BMSR_100TX_FD,
4005
4006 [MII_PHYID1] = IGP03E1000_E_PHY_ID >> 16,
4007 [MII_PHYID2] = (IGP03E1000_E_PHY_ID & 0xfff0) | 1,
4008 [MII_ANAR] = MII_ANAR_CSMACD | MII_ANAR_10 |
4009 MII_ANAR_10FD | MII_ANAR_TX |
4010 MII_ANAR_TXFD | MII_ANAR_PAUSE |
4011 MII_ANAR_PAUSE_ASYM,
4012 [MII_ANLPAR] = MII_ANLPAR_10 | MII_ANLPAR_10FD |
4013 MII_ANLPAR_TX | MII_ANLPAR_TXFD |
4014 MII_ANLPAR_T4 | MII_ANLPAR_PAUSE,
4015 [MII_ANER] = MII_ANER_NP | MII_ANER_NWAY,
4016 [MII_ANNP] = 0x1 | MII_ANNP_MP,
4017 [MII_CTRL1000] = MII_CTRL1000_HALF | MII_CTRL1000_FULL |
4018 MII_CTRL1000_PORT | MII_CTRL1000_MASTER,
4019 [MII_STAT1000] = MII_STAT1000_HALF | MII_STAT1000_FULL |
4020 MII_STAT1000_ROK | MII_STAT1000_LOK,
4021 [MII_EXTSTAT] = MII_EXTSTAT_1000T_HD | MII_EXTSTAT_1000T_FD,
4022
4023 [IGP01E1000_PHY_PORT_CONFIG] = BIT(5) | BIT(8),
4024 [IGP01E1000_PHY_PORT_STATUS] = IGP01E1000_PSSR_SPEED_1000MBPS,
4025 [IGP02E1000_PHY_POWER_MGMT] = BIT(0) | BIT(3) | IGP02E1000_PM_D3_LPLU |
4026 IGP01E1000_PSCFR_SMART_SPEED
4027 };
4028
4029 static const uint32_t igb_mac_reg_init[] = {
4030 [LEDCTL] = 2 | (3 << 8) | BIT(15) | (6 << 16) | (7 << 24),
4031 [EEMNGCTL] = BIT(31),
4032 [TXDCTL0] = E1000_TXDCTL_QUEUE_ENABLE,
4033 [RXDCTL0] = E1000_RXDCTL_QUEUE_ENABLE | (1 << 16),
4034 [RXDCTL1] = 1 << 16,
4035 [RXDCTL2] = 1 << 16,
4036 [RXDCTL3] = 1 << 16,
4037 [RXDCTL4] = 1 << 16,
4038 [RXDCTL5] = 1 << 16,
4039 [RXDCTL6] = 1 << 16,
4040 [RXDCTL7] = 1 << 16,
4041 [RXDCTL8] = 1 << 16,
4042 [RXDCTL9] = 1 << 16,
4043 [RXDCTL10] = 1 << 16,
4044 [RXDCTL11] = 1 << 16,
4045 [RXDCTL12] = 1 << 16,
4046 [RXDCTL13] = 1 << 16,
4047 [RXDCTL14] = 1 << 16,
4048 [RXDCTL15] = 1 << 16,
4049 [TIPG] = 0x08 | (0x04 << 10) | (0x06 << 20),
4050 [CTRL] = E1000_CTRL_FD | E1000_CTRL_LRST | E1000_CTRL_SPD_1000 |
4051 E1000_CTRL_ADVD3WUC,
4052 [STATUS] = E1000_STATUS_PHYRA | BIT(31),
4053 [EECD] = E1000_EECD_FWE_DIS | E1000_EECD_PRES |
4054 (2 << E1000_EECD_SIZE_EX_SHIFT),
4055 [GCR] = E1000_L0S_ADJUST |
4056 E1000_GCR_CMPL_TMOUT_RESEND |
4057 E1000_GCR_CAP_VER2 |
4058 E1000_L1_ENTRY_LATENCY_MSB |
4059 E1000_L1_ENTRY_LATENCY_LSB,
4060 [RXCSUM] = E1000_RXCSUM_IPOFLD | E1000_RXCSUM_TUOFLD,
4061 [TXPBS] = 0x28,
4062 [RXPBS] = 0x40,
4063 [TCTL] = E1000_TCTL_PSP | (0xF << E1000_CT_SHIFT) |
4064 (0x40 << E1000_COLD_SHIFT) | (0x1 << 26) | (0xA << 28),
4065 [TCTL_EXT] = 0x40 | (0x42 << 10),
4066 [DTXCTL] = E1000_DTXCTL_8023LL | E1000_DTXCTL_SPOOF_INT,
4067 [VET] = ETH_P_VLAN | (ETH_P_VLAN << 16),
4068
4069 [V2PMAILBOX0 ... V2PMAILBOX0 + IGB_MAX_VF_FUNCTIONS - 1] = E1000_V2PMAILBOX_RSTI,
4070 [MBVFIMR] = 0xFF,
4071 [VFRE] = 0xFF,
4072 [VFTE] = 0xFF,
4073 [VMOLR0 ... VMOLR0 + 7] = 0x2600 | E1000_VMOLR_STRCRC,
4074 [RPLOLR] = E1000_RPLOLR_STRCRC,
4075 [RLPML] = 0x2600,
4076 [TXCTL0] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4077 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4078 E1000_DCA_TXCTRL_DESC_RRO_EN,
4079 [TXCTL1] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4080 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4081 E1000_DCA_TXCTRL_DESC_RRO_EN,
4082 [TXCTL2] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4083 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4084 E1000_DCA_TXCTRL_DESC_RRO_EN,
4085 [TXCTL3] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4086 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4087 E1000_DCA_TXCTRL_DESC_RRO_EN,
4088 [TXCTL4] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4089 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4090 E1000_DCA_TXCTRL_DESC_RRO_EN,
4091 [TXCTL5] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4092 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4093 E1000_DCA_TXCTRL_DESC_RRO_EN,
4094 [TXCTL6] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4095 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4096 E1000_DCA_TXCTRL_DESC_RRO_EN,
4097 [TXCTL7] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4098 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4099 E1000_DCA_TXCTRL_DESC_RRO_EN,
4100 [TXCTL8] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4101 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4102 E1000_DCA_TXCTRL_DESC_RRO_EN,
4103 [TXCTL9] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4104 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4105 E1000_DCA_TXCTRL_DESC_RRO_EN,
4106 [TXCTL10] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4107 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4108 E1000_DCA_TXCTRL_DESC_RRO_EN,
4109 [TXCTL11] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4110 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4111 E1000_DCA_TXCTRL_DESC_RRO_EN,
4112 [TXCTL12] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4113 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4114 E1000_DCA_TXCTRL_DESC_RRO_EN,
4115 [TXCTL13] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4116 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4117 E1000_DCA_TXCTRL_DESC_RRO_EN,
4118 [TXCTL14] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4119 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4120 E1000_DCA_TXCTRL_DESC_RRO_EN,
4121 [TXCTL15] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4122 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4123 E1000_DCA_TXCTRL_DESC_RRO_EN,
4124 };
4125
4126 static void igb_reset(IGBCore *core, bool sw)
4127 {
4128 struct igb_tx *tx;
4129 int i;
4130
4131 timer_del(core->autoneg_timer);
4132
4133 igb_intrmgr_reset(core);
4134
4135 memset(core->phy, 0, sizeof core->phy);
4136 memcpy(core->phy, igb_phy_reg_init, sizeof igb_phy_reg_init);
4137
4138 for (i = 0; i < E1000E_MAC_SIZE; i++) {
4139 if (sw &&
4140 (i == RXPBS || i == TXPBS ||
4141 (i >= EITR0 && i < EITR0 + IGB_INTR_NUM))) {
4142 continue;
4143 }
4144
4145 core->mac[i] = i < ARRAY_SIZE(igb_mac_reg_init) ?
4146 igb_mac_reg_init[i] : 0;
4147 }
4148
4149 if (qemu_get_queue(core->owner_nic)->link_down) {
4150 igb_link_down(core);
4151 }
4152
4153 e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac);
4154
4155 for (int vfn = 0; vfn < IGB_MAX_VF_FUNCTIONS; vfn++) {
4156 /* Set RSTI, so VF can identify a PF reset is in progress */
4157 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_RSTI;
4158 }
4159
4160 for (i = 0; i < ARRAY_SIZE(core->tx); i++) {
4161 tx = &core->tx[i];
4162 net_tx_pkt_reset(tx->tx_pkt, NULL);
4163 memset(tx->ctx, 0, sizeof(tx->ctx));
4164 tx->first = true;
4165 tx->skip_cp = false;
4166 }
4167 }
4168
4169 void
4170 igb_core_reset(IGBCore *core)
4171 {
4172 igb_reset(core, false);
4173 }
4174
4175 void igb_core_pre_save(IGBCore *core)
4176 {
4177 int i;
4178 NetClientState *nc = qemu_get_queue(core->owner_nic);
4179
4180 /*
4181 * If link is down and auto-negotiation is supported and ongoing,
4182 * complete auto-negotiation immediately. This allows us to look
4183 * at MII_BMSR_AN_COMP to infer link status on load.
4184 */
4185 if (nc->link_down && igb_have_autoneg(core)) {
4186 core->phy[MII_BMSR] |= MII_BMSR_AN_COMP;
4187 igb_update_flowctl_status(core);
4188 }
4189
4190 for (i = 0; i < ARRAY_SIZE(core->tx); i++) {
4191 if (net_tx_pkt_has_fragments(core->tx[i].tx_pkt)) {
4192 core->tx[i].skip_cp = true;
4193 }
4194 }
4195 }
4196
4197 int
4198 igb_core_post_load(IGBCore *core)
4199 {
4200 NetClientState *nc = qemu_get_queue(core->owner_nic);
4201
4202 /*
4203 * nc.link_down can't be migrated, so infer link_down according
4204 * to link status bit in core.mac[STATUS].
4205 */
4206 nc->link_down = (core->mac[STATUS] & E1000_STATUS_LU) == 0;
4207
4208 return 0;
4209 }
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