hw/arm/mps2-tz.c

   1 /*
   2  * ARM V2M MPS2 board emulation, trustzone aware FPGA images
   3  *
   4  * Copyright (c) 2017 Linaro Limited
   5  * Written by Peter Maydell
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License version 2 or
   9  *  (at your option) any later version.
  10  */
  11
  12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger
  13  * FPGA but is otherwise the same as the 2). Since the CPU itself
  14  * and most of the devices are in the FPGA, the details of the board
  15  * as seen by the guest depend significantly on the FPGA image.
  16  * This source file covers the following FPGA images, for TrustZone cores:
  17  *  "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505
  18  *
  19  * Links to the TRM for the board itself and to the various Application
  20  * Notes which document the FPGA images can be found here:
  21  * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2
  22  *
  23  * Board TRM:
  24  * http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_06_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_06_en.pdf
  25  * Application Note AN505:
  26  * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html
  27  *
  28  * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide
  29  * (ARM ECM0601256) for the details of some of the device layout:
  30  *   http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
  31  */
  32
  33 #include "qemu/osdep.h"
  34 #include "qapi/error.h"
  35 #include "qemu/error-report.h"
  36 #include "hw/arm/arm.h"
  37 #include "hw/arm/armv7m.h"
  38 #include "hw/or-irq.h"
  39 #include "hw/boards.h"
  40 #include "exec/address-spaces.h"
  41 #include "sysemu/sysemu.h"
  42 #include "hw/misc/unimp.h"
  43 #include "hw/char/cmsdk-apb-uart.h"
  44 #include "hw/timer/cmsdk-apb-timer.h"
  45 #include "hw/misc/mps2-scc.h"
  46 #include "hw/misc/mps2-fpgaio.h"
  47 #include "hw/misc/tz-mpc.h"
  48 #include "hw/misc/tz-msc.h"
  49 #include "hw/arm/iotkit.h"
  50 #include "hw/dma/pl080.h"
  51 #include "hw/devices.h"
  52 #include "net/net.h"
  53 #include "hw/core/split-irq.h"
  54
  55 typedef enum MPS2TZFPGAType {
  56     FPGA_AN505,
  57 } MPS2TZFPGAType;
  58
  59 typedef struct {
  60     MachineClass parent;
  61     MPS2TZFPGAType fpga_type;
  62     uint32_t scc_id;
  63 } MPS2TZMachineClass;
  64
  65 typedef struct {
  66     MachineState parent;
  67
  68     IoTKit iotkit;
  69     MemoryRegion psram;
  70     MemoryRegion ssram[3];
  71     MemoryRegion ssram1_m;
  72     MPS2SCC scc;
  73     MPS2FPGAIO fpgaio;
  74     TZPPC ppc[5];
  75     TZMPC ssram_mpc[3];
  76     UnimplementedDeviceState spi[5];
  77     UnimplementedDeviceState i2c[4];
  78     UnimplementedDeviceState i2s_audio;
  79     UnimplementedDeviceState gpio[4];
  80     UnimplementedDeviceState gfx;
  81     PL080State dma[4];
  82     TZMSC msc[4];
  83     CMSDKAPBUART uart[5];
  84     SplitIRQ sec_resp_splitter;
  85     qemu_or_irq uart_irq_orgate;
  86     DeviceState *lan9118;
  87 } MPS2TZMachineState;
  88
  89 #define TYPE_MPS2TZ_MACHINE "mps2tz"
  90 #define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505")
  91
  92 #define MPS2TZ_MACHINE(obj) \
  93     OBJECT_CHECK(MPS2TZMachineState, obj, TYPE_MPS2TZ_MACHINE)
  94 #define MPS2TZ_MACHINE_GET_CLASS(obj) \
  95     OBJECT_GET_CLASS(MPS2TZMachineClass, obj, TYPE_MPS2TZ_MACHINE)
  96 #define MPS2TZ_MACHINE_CLASS(klass) \
  97     OBJECT_CLASS_CHECK(MPS2TZMachineClass, klass, TYPE_MPS2TZ_MACHINE)
  98
  99 /* Main SYSCLK frequency in Hz */
 100 #define SYSCLK_FRQ 20000000
 101
 102 /* Create an alias of an entire original MemoryRegion @orig
 103  * located at @base in the memory map.
 104  */
 105 static void make_ram_alias(MemoryRegion *mr, const char *name,
 106                            MemoryRegion *orig, hwaddr base)
 107 {
 108     memory_region_init_alias(mr, NULL, name, orig, 0,
 109                              memory_region_size(orig));
 110     memory_region_add_subregion(get_system_memory(), base, mr);
 111 }
 112
 113 /* Most of the devices in the AN505 FPGA image sit behind
 114  * Peripheral Protection Controllers. These data structures
 115  * define the layout of which devices sit behind which PPCs.
 116  * The devfn for each port is a function which creates, configures
 117  * and initializes the device, returning the MemoryRegion which
 118  * needs to be plugged into the downstream end of the PPC port.
 119  */
 120 typedef MemoryRegion *MakeDevFn(MPS2TZMachineState *mms, void *opaque,
 121                                 const char *name, hwaddr size);
 122
 123 typedef struct PPCPortInfo {
 124     const char *name;
 125     MakeDevFn *devfn;
 126     void *opaque;
 127     hwaddr addr;
 128     hwaddr size;
 129 } PPCPortInfo;
 130
 131 typedef struct PPCInfo {
 132     const char *name;
 133     PPCPortInfo ports[TZ_NUM_PORTS];
 134 } PPCInfo;
 135
 136 static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms,
 137                                        void *opaque,
 138                                        const char *name, hwaddr size)
 139 {
 140     /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE,
 141      * and return a pointer to its MemoryRegion.
 142      */
 143     UnimplementedDeviceState *uds = opaque;
 144
 145     sysbus_init_child_obj(OBJECT(mms), name, uds,
 146                           sizeof(UnimplementedDeviceState),
 147                           TYPE_UNIMPLEMENTED_DEVICE);
 148     qdev_prop_set_string(DEVICE(uds), "name", name);
 149     qdev_prop_set_uint64(DEVICE(uds), "size", size);
 150     object_property_set_bool(OBJECT(uds), true, "realized", &error_fatal);
 151     return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0);
 152 }
 153
 154 static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque,
 155                                const char *name, hwaddr size)
 156 {
 157     CMSDKAPBUART *uart = opaque;
 158     int i = uart - &mms->uart[0];
 159     int rxirqno = i * 2;
 160     int txirqno = i * 2 + 1;
 161     int combirqno = i + 10;
 162     SysBusDevice *s;
 163     DeviceState *iotkitdev = DEVICE(&mms->iotkit);
 164     DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate);
 165
 166     sysbus_init_child_obj(OBJECT(mms), name, uart, sizeof(mms->uart[0]),
 167                           TYPE_CMSDK_APB_UART);
 168     qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i));
 169     qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ);
 170     object_property_set_bool(OBJECT(uart), true, "realized", &error_fatal);
 171     s = SYS_BUS_DEVICE(uart);
 172     sysbus_connect_irq(s, 0, qdev_get_gpio_in_named(iotkitdev,
 173                                                     "EXP_IRQ", txirqno));
 174     sysbus_connect_irq(s, 1, qdev_get_gpio_in_named(iotkitdev,
 175                                                     "EXP_IRQ", rxirqno));
 176     sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2));
 177     sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1));
 178     sysbus_connect_irq(s, 4, qdev_get_gpio_in_named(iotkitdev,
 179                                                     "EXP_IRQ", combirqno));
 180     return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0);
 181 }
 182
 183 static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque,
 184                               const char *name, hwaddr size)
 185 {
 186     MPS2SCC *scc = opaque;
 187     DeviceState *sccdev;
 188     MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
 189
 190     object_initialize(scc, sizeof(mms->scc), TYPE_MPS2_SCC);
 191     sccdev = DEVICE(scc);
 192     qdev_set_parent_bus(sccdev, sysbus_get_default());
 193     qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2);
 194     qdev_prop_set_uint32(sccdev, "scc-aid", 0x02000008);
 195     qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id);
 196     object_property_set_bool(OBJECT(scc), true, "realized", &error_fatal);
 197     return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0);
 198 }
 199
 200 static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque,
 201                                  const char *name, hwaddr size)
 202 {
 203     MPS2FPGAIO *fpgaio = opaque;
 204
 205     object_initialize(fpgaio, sizeof(mms->fpgaio), TYPE_MPS2_FPGAIO);
 206     qdev_set_parent_bus(DEVICE(fpgaio), sysbus_get_default());
 207     object_property_set_bool(OBJECT(fpgaio), true, "realized", &error_fatal);
 208     return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0);
 209 }
 210
 211 static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque,
 212                                   const char *name, hwaddr size)
 213 {
 214     SysBusDevice *s;
 215     DeviceState *iotkitdev = DEVICE(&mms->iotkit);
 216     NICInfo *nd = &nd_table[0];
 217
 218     /* In hardware this is a LAN9220; the LAN9118 is software compatible
 219      * except that it doesn't support the checksum-offload feature.
 220      */
 221     qemu_check_nic_model(nd, "lan9118");
 222     mms->lan9118 = qdev_create(NULL, "lan9118");
 223     qdev_set_nic_properties(mms->lan9118, nd);
 224     qdev_init_nofail(mms->lan9118);
 225
 226     s = SYS_BUS_DEVICE(mms->lan9118);
 227     sysbus_connect_irq(s, 0, qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", 16));
 228     return sysbus_mmio_get_region(s, 0);
 229 }
 230
 231 static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque,
 232                               const char *name, hwaddr size)
 233 {
 234     TZMPC *mpc = opaque;
 235     int i = mpc - &mms->ssram_mpc[0];
 236     MemoryRegion *ssram = &mms->ssram[i];
 237     MemoryRegion *upstream;
 238     char *mpcname = g_strdup_printf("%s-mpc", name);
 239     static uint32_t ramsize[] = { 0x00400000, 0x00200000, 0x00200000 };
 240     static uint32_t rambase[] = { 0x00000000, 0x28000000, 0x28200000 };
 241
 242     memory_region_init_ram(ssram, NULL, name, ramsize[i], &error_fatal);
 243
 244     sysbus_init_child_obj(OBJECT(mms), mpcname, mpc, sizeof(mms->ssram_mpc[0]),
 245                           TYPE_TZ_MPC);
 246     object_property_set_link(OBJECT(mpc), OBJECT(ssram),
 247                              "downstream", &error_fatal);
 248     object_property_set_bool(OBJECT(mpc), true, "realized", &error_fatal);
 249     /* Map the upstream end of the MPC into system memory */
 250     upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1);
 251     memory_region_add_subregion(get_system_memory(), rambase[i], upstream);
 252     /* and connect its interrupt to the IoTKit */
 253     qdev_connect_gpio_out_named(DEVICE(mpc), "irq", 0,
 254                                 qdev_get_gpio_in_named(DEVICE(&mms->iotkit),
 255                                                        "mpcexp_status", i));
 256
 257     /* The first SSRAM is a special case as it has an alias; accesses to
 258      * the alias region at 0x00400000 must also go to the MPC upstream.
 259      */
 260     if (i == 0) {
 261         make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", upstream, 0x00400000);
 262     }
 263
 264     g_free(mpcname);
 265     /* Return the register interface MR for our caller to map behind the PPC */
 266     return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0);
 267 }
 268
 269 static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque,
 270                               const char *name, hwaddr size)
 271 {
 272     PL080State *dma = opaque;
 273     int i = dma - &mms->dma[0];
 274     SysBusDevice *s;
 275     char *mscname = g_strdup_printf("%s-msc", name);
 276     TZMSC *msc = &mms->msc[i];
 277     DeviceState *iotkitdev = DEVICE(&mms->iotkit);
 278     MemoryRegion *msc_upstream;
 279     MemoryRegion *msc_downstream;
 280
 281     /*
 282      * Each DMA device is a PL081 whose transaction master interface
 283      * is guarded by a Master Security Controller. The downstream end of
 284      * the MSC connects to the IoTKit AHB Slave Expansion port, so the
 285      * DMA devices can see all devices and memory that the CPU does.
 286      */
 287     sysbus_init_child_obj(OBJECT(mms), mscname, msc, sizeof(*msc), TYPE_TZ_MSC);
 288     msc_downstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(&mms->iotkit), 0);
 289     object_property_set_link(OBJECT(msc), OBJECT(msc_downstream),
 290                              "downstream", &error_fatal);
 291     object_property_set_link(OBJECT(msc), OBJECT(mms),
 292                              "idau", &error_fatal);
 293     object_property_set_bool(OBJECT(msc), true, "realized", &error_fatal);
 294
 295     qdev_connect_gpio_out_named(DEVICE(msc), "irq", 0,
 296                                 qdev_get_gpio_in_named(iotkitdev,
 297                                                        "mscexp_status", i));
 298     qdev_connect_gpio_out_named(iotkitdev, "mscexp_clear", i,
 299                                 qdev_get_gpio_in_named(DEVICE(msc),
 300                                                        "irq_clear", 0));
 301     qdev_connect_gpio_out_named(iotkitdev, "mscexp_ns", i,
 302                                 qdev_get_gpio_in_named(DEVICE(msc),
 303                                                        "cfg_nonsec", 0));
 304     qdev_connect_gpio_out(DEVICE(&mms->sec_resp_splitter),
 305                           ARRAY_SIZE(mms->ppc) + i,
 306                           qdev_get_gpio_in_named(DEVICE(msc),
 307                                                  "cfg_sec_resp", 0));
 308     msc_upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(msc), 0);
 309
 310     sysbus_init_child_obj(OBJECT(mms), name, dma, sizeof(*dma), TYPE_PL081);
 311     object_property_set_link(OBJECT(dma), OBJECT(msc_upstream),
 312                              "downstream", &error_fatal);
 313     object_property_set_bool(OBJECT(dma), true, "realized", &error_fatal);
 314
 315     s = SYS_BUS_DEVICE(dma);
 316     /* Wire up DMACINTR, DMACINTERR, DMACINTTC */
 317     sysbus_connect_irq(s, 0, qdev_get_gpio_in_named(iotkitdev,
 318                                                     "EXP_IRQ", 58 + i * 3));
 319     sysbus_connect_irq(s, 1, qdev_get_gpio_in_named(iotkitdev,
 320                                                     "EXP_IRQ", 56 + i * 3));
 321     sysbus_connect_irq(s, 2, qdev_get_gpio_in_named(iotkitdev,
 322                                                     "EXP_IRQ", 57 + i * 3));
 323
 324     return sysbus_mmio_get_region(s, 0);
 325 }
 326
 327 static void mps2tz_common_init(MachineState *machine)
 328 {
 329     MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine);
 330     MachineClass *mc = MACHINE_GET_CLASS(machine);
 331     MemoryRegion *system_memory = get_system_memory();
 332     DeviceState *iotkitdev;
 333     DeviceState *dev_splitter;
 334     int i;
 335
 336     if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
 337         error_report("This board can only be used with CPU %s",
 338                      mc->default_cpu_type);
 339         exit(1);
 340     }
 341
 342     sysbus_init_child_obj(OBJECT(machine), "iotkit", &mms->iotkit,
 343                           sizeof(mms->iotkit), TYPE_IOTKIT);
 344     iotkitdev = DEVICE(&mms->iotkit);
 345     object_property_set_link(OBJECT(&mms->iotkit), OBJECT(system_memory),
 346                              "memory", &error_abort);
 347     qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", 92);
 348     qdev_prop_set_uint32(iotkitdev, "MAINCLK", SYSCLK_FRQ);
 349     object_property_set_bool(OBJECT(&mms->iotkit), true, "realized",
 350                              &error_fatal);
 351
 352     /* The sec_resp_cfg output from the IoTKit must be split into multiple
 353      * lines, one for each of the PPCs we create here, plus one per MSC.
 354      */
 355     object_initialize(&mms->sec_resp_splitter, sizeof(mms->sec_resp_splitter),
 356                       TYPE_SPLIT_IRQ);
 357     object_property_add_child(OBJECT(machine), "sec-resp-splitter",
 358                               OBJECT(&mms->sec_resp_splitter), &error_abort);
 359     object_property_set_int(OBJECT(&mms->sec_resp_splitter),
 360                             ARRAY_SIZE(mms->ppc) + ARRAY_SIZE(mms->msc),
 361                             "num-lines", &error_fatal);
 362     object_property_set_bool(OBJECT(&mms->sec_resp_splitter), true,
 363                              "realized", &error_fatal);
 364     dev_splitter = DEVICE(&mms->sec_resp_splitter);
 365     qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0,
 366                                 qdev_get_gpio_in(dev_splitter, 0));
 367
 368     /* The IoTKit sets up much of the memory layout, including
 369      * the aliases between secure and non-secure regions in the
 370      * address space. The FPGA itself contains:
 371      *
 372      * 0x00000000..0x003fffff  SSRAM1
 373      * 0x00400000..0x007fffff  alias of SSRAM1
 374      * 0x28000000..0x283fffff  4MB SSRAM2 + SSRAM3
 375      * 0x40100000..0x4fffffff  AHB Master Expansion 1 interface devices
 376      * 0x80000000..0x80ffffff  16MB PSRAM
 377      */
 378
 379     /* The FPGA images have an odd combination of different RAMs,
 380      * because in hardware they are different implementations and
 381      * connected to different buses, giving varying performance/size
 382      * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily
 383      * call the 16MB our "system memory", as it's the largest lump.
 384      */
 385     memory_region_allocate_system_memory(&mms->psram,
 386                                          NULL, "mps.ram", 0x01000000);
 387     memory_region_add_subregion(system_memory, 0x80000000, &mms->psram);
 388
 389     /* The overflow IRQs for all UARTs are ORed together.
 390      * Tx, Rx and "combined" IRQs are sent to the NVIC separately.
 391      * Create the OR gate for this.
 392      */
 393     object_initialize(&mms->uart_irq_orgate, sizeof(mms->uart_irq_orgate),
 394                       TYPE_OR_IRQ);
 395     object_property_add_child(OBJECT(mms), "uart-irq-orgate",
 396                               OBJECT(&mms->uart_irq_orgate), &error_abort);
 397     object_property_set_int(OBJECT(&mms->uart_irq_orgate), 10, "num-lines",
 398                             &error_fatal);
 399     object_property_set_bool(OBJECT(&mms->uart_irq_orgate), true,
 400                              "realized", &error_fatal);
 401     qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0,
 402                           qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", 15));
 403
 404     /* Most of the devices in the FPGA are behind Peripheral Protection
 405      * Controllers. The required order for initializing things is:
 406      *  + initialize the PPC
 407      *  + initialize, configure and realize downstream devices
 408      *  + connect downstream device MemoryRegions to the PPC
 409      *  + realize the PPC
 410      *  + map the PPC's MemoryRegions to the places in the address map
 411      *    where the downstream devices should appear
 412      *  + wire up the PPC's control lines to the IoTKit object
 413      */
 414
 415     const PPCInfo ppcs[] = { {
 416             .name = "apb_ppcexp0",
 417             .ports = {
 418                 { "ssram-0", make_mpc, &mms->ssram_mpc[0], 0x58007000, 0x1000 },
 419                 { "ssram-1", make_mpc, &mms->ssram_mpc[1], 0x58008000, 0x1000 },
 420                 { "ssram-2", make_mpc, &mms->ssram_mpc[2], 0x58009000, 0x1000 },
 421             },
 422         }, {
 423             .name = "apb_ppcexp1",
 424             .ports = {
 425                 { "spi0", make_unimp_dev, &mms->spi[0], 0x40205000, 0x1000 },
 426                 { "spi1", make_unimp_dev, &mms->spi[1], 0x40206000, 0x1000 },
 427                 { "spi2", make_unimp_dev, &mms->spi[2], 0x40209000, 0x1000 },
 428                 { "spi3", make_unimp_dev, &mms->spi[3], 0x4020a000, 0x1000 },
 429                 { "spi4", make_unimp_dev, &mms->spi[4], 0x4020b000, 0x1000 },
 430                 { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000 },
 431                 { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000 },
 432                 { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000 },
 433                 { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000 },
 434                 { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000 },
 435                 { "i2c0", make_unimp_dev, &mms->i2c[0], 0x40207000, 0x1000 },
 436                 { "i2c1", make_unimp_dev, &mms->i2c[1], 0x40208000, 0x1000 },
 437                 { "i2c2", make_unimp_dev, &mms->i2c[2], 0x4020c000, 0x1000 },
 438                 { "i2c3", make_unimp_dev, &mms->i2c[3], 0x4020d000, 0x1000 },
 439             },
 440         }, {
 441             .name = "apb_ppcexp2",
 442             .ports = {
 443                 { "scc", make_scc, &mms->scc, 0x40300000, 0x1000 },
 444                 { "i2s-audio", make_unimp_dev, &mms->i2s_audio,
 445                   0x40301000, 0x1000 },
 446                 { "fpgaio", make_fpgaio, &mms->fpgaio, 0x40302000, 0x1000 },
 447             },
 448         }, {
 449             .name = "ahb_ppcexp0",
 450             .ports = {
 451                 { "gfx", make_unimp_dev, &mms->gfx, 0x41000000, 0x140000 },
 452                 { "gpio0", make_unimp_dev, &mms->gpio[0], 0x40100000, 0x1000 },
 453                 { "gpio1", make_unimp_dev, &mms->gpio[1], 0x40101000, 0x1000 },
 454                 { "gpio2", make_unimp_dev, &mms->gpio[2], 0x40102000, 0x1000 },
 455                 { "gpio3", make_unimp_dev, &mms->gpio[3], 0x40103000, 0x1000 },
 456                 { "eth", make_eth_dev, NULL, 0x42000000, 0x100000 },
 457             },
 458         }, {
 459             .name = "ahb_ppcexp1",
 460             .ports = {
 461                 { "dma0", make_dma, &mms->dma[0], 0x40110000, 0x1000 },
 462                 { "dma1", make_dma, &mms->dma[1], 0x40111000, 0x1000 },
 463                 { "dma2", make_dma, &mms->dma[2], 0x40112000, 0x1000 },
 464                 { "dma3", make_dma, &mms->dma[3], 0x40113000, 0x1000 },
 465             },
 466         },
 467     };
 468
 469     for (i = 0; i < ARRAY_SIZE(ppcs); i++) {
 470         const PPCInfo *ppcinfo = &ppcs[i];
 471         TZPPC *ppc = &mms->ppc[i];
 472         DeviceState *ppcdev;
 473         int port;
 474         char *gpioname;
 475
 476         sysbus_init_child_obj(OBJECT(machine), ppcinfo->name, ppc,
 477                               sizeof(TZPPC), TYPE_TZ_PPC);
 478         ppcdev = DEVICE(ppc);
 479
 480         for (port = 0; port < TZ_NUM_PORTS; port++) {
 481             const PPCPortInfo *pinfo = &ppcinfo->ports[port];
 482             MemoryRegion *mr;
 483             char *portname;
 484
 485             if (!pinfo->devfn) {
 486                 continue;
 487             }
 488
 489             mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size);
 490             portname = g_strdup_printf("port[%d]", port);
 491             object_property_set_link(OBJECT(ppc), OBJECT(mr),
 492                                      portname, &error_fatal);
 493             g_free(portname);
 494         }
 495
 496         object_property_set_bool(OBJECT(ppc), true, "realized", &error_fatal);
 497
 498         for (port = 0; port < TZ_NUM_PORTS; port++) {
 499             const PPCPortInfo *pinfo = &ppcinfo->ports[port];
 500
 501             if (!pinfo->devfn) {
 502                 continue;
 503             }
 504             sysbus_mmio_map(SYS_BUS_DEVICE(ppc), port, pinfo->addr);
 505
 506             gpioname = g_strdup_printf("%s_nonsec", ppcinfo->name);
 507             qdev_connect_gpio_out_named(iotkitdev, gpioname, port,
 508                                         qdev_get_gpio_in_named(ppcdev,
 509                                                                "cfg_nonsec",
 510                                                                port));
 511             g_free(gpioname);
 512             gpioname = g_strdup_printf("%s_ap", ppcinfo->name);
 513             qdev_connect_gpio_out_named(iotkitdev, gpioname, port,
 514                                         qdev_get_gpio_in_named(ppcdev,
 515                                                                "cfg_ap", port));
 516             g_free(gpioname);
 517         }
 518
 519         gpioname = g_strdup_printf("%s_irq_enable", ppcinfo->name);
 520         qdev_connect_gpio_out_named(iotkitdev, gpioname, 0,
 521                                     qdev_get_gpio_in_named(ppcdev,
 522                                                            "irq_enable", 0));
 523         g_free(gpioname);
 524         gpioname = g_strdup_printf("%s_irq_clear", ppcinfo->name);
 525         qdev_connect_gpio_out_named(iotkitdev, gpioname, 0,
 526                                     qdev_get_gpio_in_named(ppcdev,
 527                                                            "irq_clear", 0));
 528         g_free(gpioname);
 529         gpioname = g_strdup_printf("%s_irq_status", ppcinfo->name);
 530         qdev_connect_gpio_out_named(ppcdev, "irq", 0,
 531                                     qdev_get_gpio_in_named(iotkitdev,
 532                                                            gpioname, 0));
 533         g_free(gpioname);
 534
 535         qdev_connect_gpio_out(dev_splitter, i,
 536                               qdev_get_gpio_in_named(ppcdev,
 537                                                      "cfg_sec_resp", 0));
 538     }
 539
 540     create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000);
 541
 542     armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400000);
 543 }
 544
 545 static void mps2_tz_idau_check(IDAUInterface *ii, uint32_t address,
 546                                int *iregion, bool *exempt, bool *ns, bool *nsc)
 547 {
 548     /*
 549      * The MPS2 TZ FPGA images have IDAUs in them which are connected to
 550      * the Master Security Controllers. Thes have the same logic as
 551      * is used by the IoTKit for the IDAU connected to the CPU, except
 552      * that MSCs don't care about the NSC attribute.
 553      */
 554     int region = extract32(address, 28, 4);
 555
 556     *ns = !(region & 1);
 557     *nsc = false;
 558     /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */
 559     *exempt = (address & 0xeff00000) == 0xe0000000;
 560     *iregion = region;
 561 }
 562
 563 static void mps2tz_class_init(ObjectClass *oc, void *data)
 564 {
 565     MachineClass *mc = MACHINE_CLASS(oc);
 566     IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc);
 567
 568     mc->init = mps2tz_common_init;
 569     mc->max_cpus = 1;
 570     iic->check = mps2_tz_idau_check;
 571 }
 572
 573 static void mps2tz_an505_class_init(ObjectClass *oc, void *data)
 574 {
 575     MachineClass *mc = MACHINE_CLASS(oc);
 576     MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
 577
 578     mc->desc = "ARM MPS2 with AN505 FPGA image for Cortex-M33";
 579     mmc->fpga_type = FPGA_AN505;
 580     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33");
 581     mmc->scc_id = 0x41040000 | (505 << 4);
 582 }
 583
 584 static const TypeInfo mps2tz_info = {
 585     .name = TYPE_MPS2TZ_MACHINE,
 586     .parent = TYPE_MACHINE,
 587     .abstract = true,
 588     .instance_size = sizeof(MPS2TZMachineState),
 589     .class_size = sizeof(MPS2TZMachineClass),
 590     .class_init = mps2tz_class_init,
 591     .interfaces = (InterfaceInfo[]) {
 592         { TYPE_IDAU_INTERFACE },
 593         { }
 594     },
 595 };
 596
 597 static const TypeInfo mps2tz_an505_info = {
 598     .name = TYPE_MPS2TZ_AN505_MACHINE,
 599     .parent = TYPE_MPS2TZ_MACHINE,
 600     .class_init = mps2tz_an505_class_init,
 601 };
 602
 603 static void mps2tz_machine_init(void)
 604 {
 605     type_register_static(&mps2tz_info);
 606     type_register_static(&mps2tz_an505_info);
 607 }
 608
 609 type_init(mps2tz_machine_init);