hw/ppc/e500.c

   1 /*
   2  * QEMU PowerPC e500-based platforms
   3  *
   4  * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
   5  *
   6  * Author: Yu Liu,     <yu.liu@freescale.com>
   7  *
   8  * This file is derived from hw/ppc440_bamboo.c,
   9  * the copyright for that material belongs to the original owners.
  10  *
  11  * This is free software; you can redistribute it and/or modify
  12  * it under the terms of  the GNU General  Public License as published by
  13  * the Free Software Foundation;  either version 2 of the  License, or
  14  * (at your option) any later version.
  15  */
  16
  17 #include "config.h"
  18 #include "qemu-common.h"
  19 #include "e500.h"
  20 #include "e500-ccsr.h"
  21 #include "net/net.h"
  22 #include "qemu/config-file.h"
  23 #include "hw/hw.h"
  24 #include "hw/char/serial.h"
  25 #include "hw/pci/pci.h"
  26 #include "hw/boards.h"
  27 #include "sysemu/sysemu.h"
  28 #include "sysemu/kvm.h"
  29 #include "kvm_ppc.h"
  30 #include "sysemu/device_tree.h"
  31 #include "hw/ppc/openpic.h"
  32 #include "hw/ppc/ppc.h"
  33 #include "hw/loader.h"
  34 #include "elf.h"
  35 #include "hw/sysbus.h"
  36 #include "exec/address-spaces.h"
  37 #include "qemu/host-utils.h"
  38 #include "hw/pci-host/ppce500.h"
  39
  40 #define EPAPR_MAGIC                (0x45504150)
  41 #define BINARY_DEVICE_TREE_FILE    "mpc8544ds.dtb"
  42 #define UIMAGE_LOAD_BASE           0
  43 #define DTC_LOAD_PAD               0x1800000
  44 #define DTC_PAD_MASK               0xFFFFF
  45 #define DTB_MAX_SIZE               (8 * 1024 * 1024)
  46 #define INITRD_LOAD_PAD            0x2000000
  47 #define INITRD_PAD_MASK            0xFFFFFF
  48
  49 #define RAM_SIZES_ALIGN            (64UL << 20)
  50
  51 /* TODO: parameterize */
  52 #define MPC8544_CCSRBAR_BASE       0xE0000000ULL
  53 #define MPC8544_CCSRBAR_SIZE       0x00100000ULL
  54 #define MPC8544_MPIC_REGS_OFFSET   0x40000ULL
  55 #define MPC8544_MSI_REGS_OFFSET   0x41600ULL
  56 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL
  57 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
  58 #define MPC8544_PCI_REGS_OFFSET    0x8000ULL
  59 #define MPC8544_PCI_REGS_BASE      (MPC8544_CCSRBAR_BASE + \
  60                                     MPC8544_PCI_REGS_OFFSET)
  61 #define MPC8544_PCI_REGS_SIZE      0x1000ULL
  62 #define MPC8544_PCI_IO             0xE1000000ULL
  63 #define MPC8544_UTIL_OFFSET        0xe0000ULL
  64 #define MPC8544_SPIN_BASE          0xEF000000ULL
  65
  66 struct boot_info
  67 {
  68     uint32_t dt_base;
  69     uint32_t dt_size;
  70     uint32_t entry;
  71 };
  72
  73 static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot,
  74                                 int nr_slots, int *len)
  75 {
  76     int i = 0;
  77     int slot;
  78     int pci_irq;
  79     int host_irq;
  80     int last_slot = first_slot + nr_slots;
  81     uint32_t *pci_map;
  82
  83     *len = nr_slots * 4 * 7 * sizeof(uint32_t);
  84     pci_map = g_malloc(*len);
  85
  86     for (slot = first_slot; slot < last_slot; slot++) {
  87         for (pci_irq = 0; pci_irq < 4; pci_irq++) {
  88             pci_map[i++] = cpu_to_be32(slot << 11);
  89             pci_map[i++] = cpu_to_be32(0x0);
  90             pci_map[i++] = cpu_to_be32(0x0);
  91             pci_map[i++] = cpu_to_be32(pci_irq + 1);
  92             pci_map[i++] = cpu_to_be32(mpic);
  93             host_irq = ppce500_pci_map_irq_slot(slot, pci_irq);
  94             pci_map[i++] = cpu_to_be32(host_irq + 1);
  95             pci_map[i++] = cpu_to_be32(0x1);
  96         }
  97     }
  98
  99     assert((i * sizeof(uint32_t)) == *len);
 100
 101     return pci_map;
 102 }
 103
 104 static void dt_serial_create(void *fdt, unsigned long long offset,
 105                              const char *soc, const char *mpic,
 106                              const char *alias, int idx, bool defcon)
 107 {
 108     char ser[128];
 109
 110     snprintf(ser, sizeof(ser), "%s/serial@%llx", soc, offset);
 111     qemu_devtree_add_subnode(fdt, ser);
 112     qemu_devtree_setprop_string(fdt, ser, "device_type", "serial");
 113     qemu_devtree_setprop_string(fdt, ser, "compatible", "ns16550");
 114     qemu_devtree_setprop_cells(fdt, ser, "reg", offset, 0x100);
 115     qemu_devtree_setprop_cell(fdt, ser, "cell-index", idx);
 116     qemu_devtree_setprop_cell(fdt, ser, "clock-frequency", 0);
 117     qemu_devtree_setprop_cells(fdt, ser, "interrupts", 42, 2);
 118     qemu_devtree_setprop_phandle(fdt, ser, "interrupt-parent", mpic);
 119     qemu_devtree_setprop_string(fdt, "/aliases", alias, ser);
 120
 121     if (defcon) {
 122         qemu_devtree_setprop_string(fdt, "/chosen", "linux,stdout-path", ser);
 123     }
 124 }
 125
 126 static int ppce500_load_device_tree(QEMUMachineInitArgs *args,
 127                                     PPCE500Params *params,
 128                                     hwaddr addr,
 129                                     hwaddr initrd_base,
 130                                     hwaddr initrd_size,
 131                                     bool dry_run)
 132 {
 133     CPUPPCState *env = first_cpu->env_ptr;
 134     int ret = -1;
 135     uint64_t mem_reg_property[] = { 0, cpu_to_be64(args->ram_size) };
 136     int fdt_size;
 137     void *fdt;
 138     uint8_t hypercall[16];
 139     uint32_t clock_freq = 400000000;
 140     uint32_t tb_freq = 400000000;
 141     int i;
 142     char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus";
 143     char soc[128];
 144     char mpic[128];
 145     uint32_t mpic_ph;
 146     uint32_t msi_ph;
 147     char gutil[128];
 148     char pci[128];
 149     char msi[128];
 150     uint32_t *pci_map = NULL;
 151     int len;
 152     uint32_t pci_ranges[14] =
 153         {
 154             0x2000000, 0x0, 0xc0000000,
 155             0x0, 0xc0000000,
 156             0x0, 0x20000000,
 157
 158             0x1000000, 0x0, 0x0,
 159             0x0, 0xe1000000,
 160             0x0, 0x10000,
 161         };
 162     QemuOpts *machine_opts = qemu_get_machine_opts();
 163     const char *dtb_file = qemu_opt_get(machine_opts, "dtb");
 164     const char *toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible");
 165
 166     if (dtb_file) {
 167         char *filename;
 168         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file);
 169         if (!filename) {
 170             goto out;
 171         }
 172
 173         fdt = load_device_tree(filename, &fdt_size);
 174         if (!fdt) {
 175             goto out;
 176         }
 177         goto done;
 178     }
 179
 180     fdt = create_device_tree(&fdt_size);
 181     if (fdt == NULL) {
 182         goto out;
 183     }
 184
 185     /* Manipulate device tree in memory. */
 186     qemu_devtree_setprop_cell(fdt, "/", "#address-cells", 2);
 187     qemu_devtree_setprop_cell(fdt, "/", "#size-cells", 2);
 188
 189     qemu_devtree_add_subnode(fdt, "/memory");
 190     qemu_devtree_setprop_string(fdt, "/memory", "device_type", "memory");
 191     qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property,
 192                          sizeof(mem_reg_property));
 193
 194     qemu_devtree_add_subnode(fdt, "/chosen");
 195     if (initrd_size) {
 196         ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start",
 197                                         initrd_base);
 198         if (ret < 0) {
 199             fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
 200         }
 201
 202         ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end",
 203                                         (initrd_base + initrd_size));
 204         if (ret < 0) {
 205             fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
 206         }
 207     }
 208
 209     ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs",
 210                                       args->kernel_cmdline);
 211     if (ret < 0)
 212         fprintf(stderr, "couldn't set /chosen/bootargs\n");
 213
 214     if (kvm_enabled()) {
 215         /* Read out host's frequencies */
 216         clock_freq = kvmppc_get_clockfreq();
 217         tb_freq = kvmppc_get_tbfreq();
 218
 219         /* indicate KVM hypercall interface */
 220         qemu_devtree_add_subnode(fdt, "/hypervisor");
 221         qemu_devtree_setprop_string(fdt, "/hypervisor", "compatible",
 222                                     "linux,kvm");
 223         kvmppc_get_hypercall(env, hypercall, sizeof(hypercall));
 224         qemu_devtree_setprop(fdt, "/hypervisor", "hcall-instructions",
 225                              hypercall, sizeof(hypercall));
 226         /* if KVM supports the idle hcall, set property indicating this */
 227         if (kvmppc_get_hasidle(env)) {
 228             qemu_devtree_setprop(fdt, "/hypervisor", "has-idle", NULL, 0);
 229         }
 230     }
 231
 232     /* Create CPU nodes */
 233     qemu_devtree_add_subnode(fdt, "/cpus");
 234     qemu_devtree_setprop_cell(fdt, "/cpus", "#address-cells", 1);
 235     qemu_devtree_setprop_cell(fdt, "/cpus", "#size-cells", 0);
 236
 237     /* We need to generate the cpu nodes in reverse order, so Linux can pick
 238        the first node as boot node and be happy */
 239     for (i = smp_cpus - 1; i >= 0; i--) {
 240         CPUState *cpu;
 241         char cpu_name[128];
 242         uint64_t cpu_release_addr = MPC8544_SPIN_BASE + (i * 0x20);
 243
 244         cpu = qemu_get_cpu(i);
 245         if (cpu == NULL) {
 246             continue;
 247         }
 248         env = cpu->env_ptr;
 249
 250         snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x",
 251                  cpu->cpu_index);
 252         qemu_devtree_add_subnode(fdt, cpu_name);
 253         qemu_devtree_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq);
 254         qemu_devtree_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);
 255         qemu_devtree_setprop_string(fdt, cpu_name, "device_type", "cpu");
 256         qemu_devtree_setprop_cell(fdt, cpu_name, "reg", cpu->cpu_index);
 257         qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-line-size",
 258                                   env->dcache_line_size);
 259         qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-line-size",
 260                                   env->icache_line_size);
 261         qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000);
 262         qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000);
 263         qemu_devtree_setprop_cell(fdt, cpu_name, "bus-frequency", 0);
 264         if (cpu->cpu_index) {
 265             qemu_devtree_setprop_string(fdt, cpu_name, "status", "disabled");
 266             qemu_devtree_setprop_string(fdt, cpu_name, "enable-method", "spin-table");
 267             qemu_devtree_setprop_u64(fdt, cpu_name, "cpu-release-addr",
 268                                      cpu_release_addr);
 269         } else {
 270             qemu_devtree_setprop_string(fdt, cpu_name, "status", "okay");
 271         }
 272     }
 273
 274     qemu_devtree_add_subnode(fdt, "/aliases");
 275     /* XXX These should go into their respective devices' code */
 276     snprintf(soc, sizeof(soc), "/soc@%llx", MPC8544_CCSRBAR_BASE);
 277     qemu_devtree_add_subnode(fdt, soc);
 278     qemu_devtree_setprop_string(fdt, soc, "device_type", "soc");
 279     qemu_devtree_setprop(fdt, soc, "compatible", compatible_sb,
 280                          sizeof(compatible_sb));
 281     qemu_devtree_setprop_cell(fdt, soc, "#address-cells", 1);
 282     qemu_devtree_setprop_cell(fdt, soc, "#size-cells", 1);
 283     qemu_devtree_setprop_cells(fdt, soc, "ranges", 0x0,
 284                                MPC8544_CCSRBAR_BASE >> 32, MPC8544_CCSRBAR_BASE,
 285                                MPC8544_CCSRBAR_SIZE);
 286     /* XXX should contain a reasonable value */
 287     qemu_devtree_setprop_cell(fdt, soc, "bus-frequency", 0);
 288
 289     snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET);
 290     qemu_devtree_add_subnode(fdt, mpic);
 291     qemu_devtree_setprop_string(fdt, mpic, "device_type", "open-pic");
 292     qemu_devtree_setprop_string(fdt, mpic, "compatible", "fsl,mpic");
 293     qemu_devtree_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET,
 294                                0x40000);
 295     qemu_devtree_setprop_cell(fdt, mpic, "#address-cells", 0);
 296     qemu_devtree_setprop_cell(fdt, mpic, "#interrupt-cells", 2);
 297     mpic_ph = qemu_devtree_alloc_phandle(fdt);
 298     qemu_devtree_setprop_cell(fdt, mpic, "phandle", mpic_ph);
 299     qemu_devtree_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph);
 300     qemu_devtree_setprop(fdt, mpic, "interrupt-controller", NULL, 0);
 301
 302     /*
 303      * We have to generate ser1 first, because Linux takes the first
 304      * device it finds in the dt as serial output device. And we generate
 305      * devices in reverse order to the dt.
 306      */
 307     dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET,
 308                      soc, mpic, "serial1", 1, false);
 309     dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET,
 310                      soc, mpic, "serial0", 0, true);
 311
 312     snprintf(gutil, sizeof(gutil), "%s/global-utilities@%llx", soc,
 313              MPC8544_UTIL_OFFSET);
 314     qemu_devtree_add_subnode(fdt, gutil);
 315     qemu_devtree_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts");
 316     qemu_devtree_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000);
 317     qemu_devtree_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0);
 318
 319     snprintf(msi, sizeof(msi), "/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET);
 320     qemu_devtree_add_subnode(fdt, msi);
 321     qemu_devtree_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi");
 322     qemu_devtree_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200);
 323     msi_ph = qemu_devtree_alloc_phandle(fdt);
 324     qemu_devtree_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100);
 325     qemu_devtree_setprop_phandle(fdt, msi, "interrupt-parent", mpic);
 326     qemu_devtree_setprop_cells(fdt, msi, "interrupts",
 327         0xe0, 0x0,
 328         0xe1, 0x0,
 329         0xe2, 0x0,
 330         0xe3, 0x0,
 331         0xe4, 0x0,
 332         0xe5, 0x0,
 333         0xe6, 0x0,
 334         0xe7, 0x0);
 335     qemu_devtree_setprop_cell(fdt, msi, "phandle", msi_ph);
 336     qemu_devtree_setprop_cell(fdt, msi, "linux,phandle", msi_ph);
 337
 338     snprintf(pci, sizeof(pci), "/pci@%llx", MPC8544_PCI_REGS_BASE);
 339     qemu_devtree_add_subnode(fdt, pci);
 340     qemu_devtree_setprop_cell(fdt, pci, "cell-index", 0);
 341     qemu_devtree_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci");
 342     qemu_devtree_setprop_string(fdt, pci, "device_type", "pci");
 343     qemu_devtree_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0,
 344                                0x0, 0x7);
 345     pci_map = pci_map_create(fdt, qemu_devtree_get_phandle(fdt, mpic),
 346                              params->pci_first_slot, params->pci_nr_slots,
 347                              &len);
 348     qemu_devtree_setprop(fdt, pci, "interrupt-map", pci_map, len);
 349     qemu_devtree_setprop_phandle(fdt, pci, "interrupt-parent", mpic);
 350     qemu_devtree_setprop_cells(fdt, pci, "interrupts", 24, 2);
 351     qemu_devtree_setprop_cells(fdt, pci, "bus-range", 0, 255);
 352     for (i = 0; i < 14; i++) {
 353         pci_ranges[i] = cpu_to_be32(pci_ranges[i]);
 354     }
 355     qemu_devtree_setprop_cell(fdt, pci, "fsl,msi", msi_ph);
 356     qemu_devtree_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges));
 357     qemu_devtree_setprop_cells(fdt, pci, "reg", MPC8544_PCI_REGS_BASE >> 32,
 358                                MPC8544_PCI_REGS_BASE, 0, 0x1000);
 359     qemu_devtree_setprop_cell(fdt, pci, "clock-frequency", 66666666);
 360     qemu_devtree_setprop_cell(fdt, pci, "#interrupt-cells", 1);
 361     qemu_devtree_setprop_cell(fdt, pci, "#size-cells", 2);
 362     qemu_devtree_setprop_cell(fdt, pci, "#address-cells", 3);
 363     qemu_devtree_setprop_string(fdt, "/aliases", "pci0", pci);
 364
 365     params->fixup_devtree(params, fdt);
 366
 367     if (toplevel_compat) {
 368         qemu_devtree_setprop(fdt, "/", "compatible", toplevel_compat,
 369                              strlen(toplevel_compat) + 1);
 370     }
 371
 372 done:
 373     if (!dry_run) {
 374         qemu_devtree_dumpdtb(fdt, fdt_size);
 375         cpu_physical_memory_write(addr, fdt, fdt_size);
 376     }
 377     ret = fdt_size;
 378
 379 out:
 380     g_free(pci_map);
 381
 382     return ret;
 383 }
 384
 385 typedef struct DeviceTreeParams {
 386     QEMUMachineInitArgs args;
 387     PPCE500Params params;
 388     hwaddr addr;
 389     hwaddr initrd_base;
 390     hwaddr initrd_size;
 391 } DeviceTreeParams;
 392
 393 static void ppce500_reset_device_tree(void *opaque)
 394 {
 395     DeviceTreeParams *p = opaque;
 396     ppce500_load_device_tree(&p->args, &p->params, p->addr, p->initrd_base,
 397                              p->initrd_size, false);
 398 }
 399
 400 static int ppce500_prep_device_tree(QEMUMachineInitArgs *args,
 401                                     PPCE500Params *params,
 402                                     hwaddr addr,
 403                                     hwaddr initrd_base,
 404                                     hwaddr initrd_size)
 405 {
 406     DeviceTreeParams *p = g_new(DeviceTreeParams, 1);
 407     p->args = *args;
 408     p->params = *params;
 409     p->addr = addr;
 410     p->initrd_base = initrd_base;
 411     p->initrd_size = initrd_size;
 412
 413     qemu_register_reset(ppce500_reset_device_tree, p);
 414
 415     /* Issue the device tree loader once, so that we get the size of the blob */
 416     return ppce500_load_device_tree(args, params, addr, initrd_base,
 417                                     initrd_size, true);
 418 }
 419
 420 /* Create -kernel TLB entries for BookE.  */
 421 static inline hwaddr booke206_page_size_to_tlb(uint64_t size)
 422 {
 423     return 63 - clz64(size >> 10);
 424 }
 425
 426 static int booke206_initial_map_tsize(CPUPPCState *env)
 427 {
 428     struct boot_info *bi = env->load_info;
 429     hwaddr dt_end;
 430     int ps;
 431
 432     /* Our initial TLB entry needs to cover everything from 0 to
 433        the device tree top */
 434     dt_end = bi->dt_base + bi->dt_size;
 435     ps = booke206_page_size_to_tlb(dt_end) + 1;
 436     if (ps & 1) {
 437         /* e500v2 can only do even TLB size bits */
 438         ps++;
 439     }
 440     return ps;
 441 }
 442
 443 static uint64_t mmubooke_initial_mapsize(CPUPPCState *env)
 444 {
 445     int tsize;
 446
 447     tsize = booke206_initial_map_tsize(env);
 448     return (1ULL << 10 << tsize);
 449 }
 450
 451 static void mmubooke_create_initial_mapping(CPUPPCState *env)
 452 {
 453     ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0);
 454     hwaddr size;
 455     int ps;
 456
 457     ps = booke206_initial_map_tsize(env);
 458     size = (ps << MAS1_TSIZE_SHIFT);
 459     tlb->mas1 = MAS1_VALID | size;
 460     tlb->mas2 = 0;
 461     tlb->mas7_3 = 0;
 462     tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
 463
 464     env->tlb_dirty = true;
 465 }
 466
 467 static void ppce500_cpu_reset_sec(void *opaque)
 468 {
 469     PowerPCCPU *cpu = opaque;
 470     CPUState *cs = CPU(cpu);
 471     CPUPPCState *env = &cpu->env;
 472
 473     cpu_reset(cs);
 474
 475     /* Secondary CPU starts in halted state for now. Needs to change when
 476        implementing non-kernel boot. */
 477     cs->halted = 1;
 478     env->exception_index = EXCP_HLT;
 479 }
 480
 481 static void ppce500_cpu_reset(void *opaque)
 482 {
 483     PowerPCCPU *cpu = opaque;
 484     CPUState *cs = CPU(cpu);
 485     CPUPPCState *env = &cpu->env;
 486     struct boot_info *bi = env->load_info;
 487
 488     cpu_reset(cs);
 489
 490     /* Set initial guest state. */
 491     cs->halted = 0;
 492     env->gpr[1] = (16<<20) - 8;
 493     env->gpr[3] = bi->dt_base;
 494     env->gpr[4] = 0;
 495     env->gpr[5] = 0;
 496     env->gpr[6] = EPAPR_MAGIC;
 497     env->gpr[7] = mmubooke_initial_mapsize(env);
 498     env->gpr[8] = 0;
 499     env->gpr[9] = 0;
 500     env->nip = bi->entry;
 501     mmubooke_create_initial_mapping(env);
 502 }
 503
 504 static DeviceState *ppce500_init_mpic_qemu(PPCE500Params *params,
 505                                            qemu_irq **irqs)
 506 {
 507     DeviceState *dev;
 508     SysBusDevice *s;
 509     int i, j, k;
 510
 511     dev = qdev_create(NULL, TYPE_OPENPIC);
 512     qdev_prop_set_uint32(dev, "model", params->mpic_version);
 513     qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus);
 514
 515     qdev_init_nofail(dev);
 516     s = SYS_BUS_DEVICE(dev);
 517
 518     k = 0;
 519     for (i = 0; i < smp_cpus; i++) {
 520         for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
 521             sysbus_connect_irq(s, k++, irqs[i][j]);
 522         }
 523     }
 524
 525     return dev;
 526 }
 527
 528 static DeviceState *ppce500_init_mpic_kvm(PPCE500Params *params,
 529                                           qemu_irq **irqs)
 530 {
 531     DeviceState *dev;
 532     CPUState *cs;
 533     int r;
 534
 535     dev = qdev_create(NULL, TYPE_KVM_OPENPIC);
 536     qdev_prop_set_uint32(dev, "model", params->mpic_version);
 537
 538     r = qdev_init(dev);
 539     if (r) {
 540         return NULL;
 541     }
 542
 543     for (cs = first_cpu; cs != NULL; cs = cs->next_cpu) {
 544         if (kvm_openpic_connect_vcpu(dev, cs)) {
 545             fprintf(stderr, "%s: failed to connect vcpu to irqchip\n",
 546                     __func__);
 547             abort();
 548         }
 549     }
 550
 551     return dev;
 552 }
 553
 554 static qemu_irq *ppce500_init_mpic(PPCE500Params *params, MemoryRegion *ccsr,
 555                                    qemu_irq **irqs)
 556 {
 557     qemu_irq *mpic;
 558     DeviceState *dev = NULL;
 559     SysBusDevice *s;
 560     int i;
 561
 562     mpic = g_new(qemu_irq, 256);
 563
 564     if (kvm_enabled()) {
 565         QemuOpts *machine_opts = qemu_get_machine_opts();
 566         bool irqchip_allowed = qemu_opt_get_bool(machine_opts,
 567                                                 "kernel_irqchip", true);
 568         bool irqchip_required = qemu_opt_get_bool(machine_opts,
 569                                                   "kernel_irqchip", false);
 570
 571         if (irqchip_allowed) {
 572             dev = ppce500_init_mpic_kvm(params, irqs);
 573         }
 574
 575         if (irqchip_required && !dev) {
 576             fprintf(stderr, "%s: irqchip requested but unavailable\n",
 577                     __func__);
 578             abort();
 579         }
 580     }
 581
 582     if (!dev) {
 583         dev = ppce500_init_mpic_qemu(params, irqs);
 584     }
 585
 586     for (i = 0; i < 256; i++) {
 587         mpic[i] = qdev_get_gpio_in(dev, i);
 588     }
 589
 590     s = SYS_BUS_DEVICE(dev);
 591     memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET,
 592                                 s->mmio[0].memory);
 593
 594     return mpic;
 595 }
 596
 597 void ppce500_init(QEMUMachineInitArgs *args, PPCE500Params *params)
 598 {
 599     MemoryRegion *address_space_mem = get_system_memory();
 600     MemoryRegion *ram = g_new(MemoryRegion, 1);
 601     PCIBus *pci_bus;
 602     CPUPPCState *env = NULL;
 603     uint64_t elf_entry;
 604     uint64_t elf_lowaddr;
 605     hwaddr entry=0;
 606     hwaddr loadaddr=UIMAGE_LOAD_BASE;
 607     target_long kernel_size=0;
 608     target_ulong dt_base = 0;
 609     target_ulong initrd_base = 0;
 610     target_long initrd_size = 0;
 611     target_ulong cur_base = 0;
 612     int i;
 613     unsigned int pci_irq_nrs[4] = {1, 2, 3, 4};
 614     qemu_irq **irqs, *mpic;
 615     DeviceState *dev;
 616     CPUPPCState *firstenv = NULL;
 617     MemoryRegion *ccsr_addr_space;
 618     SysBusDevice *s;
 619     PPCE500CCSRState *ccsr;
 620
 621     /* Setup CPUs */
 622     if (args->cpu_model == NULL) {
 623         args->cpu_model = "e500v2_v30";
 624     }
 625
 626     irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
 627     irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
 628     for (i = 0; i < smp_cpus; i++) {
 629         PowerPCCPU *cpu;
 630         CPUState *cs;
 631         qemu_irq *input;
 632
 633         cpu = cpu_ppc_init(args->cpu_model);
 634         if (cpu == NULL) {
 635             fprintf(stderr, "Unable to initialize CPU!\n");
 636             exit(1);
 637         }
 638         env = &cpu->env;
 639         cs = CPU(cpu);
 640
 641         if (!firstenv) {
 642             firstenv = env;
 643         }
 644
 645         irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB);
 646         input = (qemu_irq *)env->irq_inputs;
 647         irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT];
 648         irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT];
 649         env->spr[SPR_BOOKE_PIR] = cs->cpu_index = i;
 650         env->mpic_iack = MPC8544_CCSRBAR_BASE +
 651                          MPC8544_MPIC_REGS_OFFSET + 0xa0;
 652
 653         ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500);
 654
 655         /* Register reset handler */
 656         if (!i) {
 657             /* Primary CPU */
 658             struct boot_info *boot_info;
 659             boot_info = g_malloc0(sizeof(struct boot_info));
 660             qemu_register_reset(ppce500_cpu_reset, cpu);
 661             env->load_info = boot_info;
 662         } else {
 663             /* Secondary CPUs */
 664             qemu_register_reset(ppce500_cpu_reset_sec, cpu);
 665         }
 666     }
 667
 668     env = firstenv;
 669
 670     /* Fixup Memory size on a alignment boundary */
 671     ram_size &= ~(RAM_SIZES_ALIGN - 1);
 672     args->ram_size = ram_size;
 673
 674     /* Register Memory */
 675     memory_region_init_ram(ram, NULL, "mpc8544ds.ram", ram_size);
 676     vmstate_register_ram_global(ram);
 677     memory_region_add_subregion(address_space_mem, 0, ram);
 678
 679     dev = qdev_create(NULL, "e500-ccsr");
 680     object_property_add_child(qdev_get_machine(), "e500-ccsr",
 681                               OBJECT(dev), NULL);
 682     qdev_init_nofail(dev);
 683     ccsr = CCSR(dev);
 684     ccsr_addr_space = &ccsr->ccsr_space;
 685     memory_region_add_subregion(address_space_mem, MPC8544_CCSRBAR_BASE,
 686                                 ccsr_addr_space);
 687
 688     mpic = ppce500_init_mpic(params, ccsr_addr_space, irqs);
 689
 690     /* Serial */
 691     if (serial_hds[0]) {
 692         serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET,
 693                        0, mpic[42], 399193,
 694                        serial_hds[0], DEVICE_BIG_ENDIAN);
 695     }
 696
 697     if (serial_hds[1]) {
 698         serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET,
 699                        0, mpic[42], 399193,
 700                        serial_hds[1], DEVICE_BIG_ENDIAN);
 701     }
 702
 703     /* General Utility device */
 704     dev = qdev_create(NULL, "mpc8544-guts");
 705     qdev_init_nofail(dev);
 706     s = SYS_BUS_DEVICE(dev);
 707     memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET,
 708                                 sysbus_mmio_get_region(s, 0));
 709
 710     /* PCI */
 711     dev = qdev_create(NULL, "e500-pcihost");
 712     qdev_prop_set_uint32(dev, "first_slot", params->pci_first_slot);
 713     qdev_init_nofail(dev);
 714     s = SYS_BUS_DEVICE(dev);
 715     sysbus_connect_irq(s, 0, mpic[pci_irq_nrs[0]]);
 716     sysbus_connect_irq(s, 1, mpic[pci_irq_nrs[1]]);
 717     sysbus_connect_irq(s, 2, mpic[pci_irq_nrs[2]]);
 718     sysbus_connect_irq(s, 3, mpic[pci_irq_nrs[3]]);
 719     memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET,
 720                                 sysbus_mmio_get_region(s, 0));
 721
 722     pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
 723     if (!pci_bus)
 724         printf("couldn't create PCI controller!\n");
 725
 726     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, MPC8544_PCI_IO);
 727
 728     if (pci_bus) {
 729         /* Register network interfaces. */
 730         for (i = 0; i < nb_nics; i++) {
 731             pci_nic_init_nofail(&nd_table[i], pci_bus, "virtio", NULL);
 732         }
 733     }
 734
 735     /* Register spinning region */
 736     sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE, NULL);
 737
 738     /* Load kernel. */
 739     if (args->kernel_filename) {
 740         kernel_size = load_uimage(args->kernel_filename, &entry,
 741                                   &loadaddr, NULL);
 742         if (kernel_size < 0) {
 743             kernel_size = load_elf(args->kernel_filename, NULL, NULL,
 744                                    &elf_entry, &elf_lowaddr, NULL, 1,
 745                                    ELF_MACHINE, 0);
 746             entry = elf_entry;
 747             loadaddr = elf_lowaddr;
 748         }
 749         /* XXX try again as binary */
 750         if (kernel_size < 0) {
 751             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 752                     args->kernel_filename);
 753             exit(1);
 754         }
 755
 756         cur_base = loadaddr + kernel_size;
 757
 758         /* Reserve space for dtb */
 759         dt_base = (cur_base + DTC_LOAD_PAD) & ~DTC_PAD_MASK;
 760         cur_base += DTB_MAX_SIZE;
 761     }
 762
 763     /* Load initrd. */
 764     if (args->initrd_filename) {
 765         initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK;
 766         initrd_size = load_image_targphys(args->initrd_filename, initrd_base,
 767                                           ram_size - initrd_base);
 768
 769         if (initrd_size < 0) {
 770             fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 771                     args->initrd_filename);
 772             exit(1);
 773         }
 774
 775         cur_base = initrd_base + initrd_size;
 776     }
 777
 778     /* If we're loading a kernel directly, we must load the device tree too. */
 779     if (args->kernel_filename) {
 780         struct boot_info *boot_info;
 781         int dt_size;
 782
 783         dt_size = ppce500_prep_device_tree(args, params, dt_base,
 784                                            initrd_base, initrd_size);
 785         if (dt_size < 0) {
 786             fprintf(stderr, "couldn't load device tree\n");
 787             exit(1);
 788         }
 789         assert(dt_size < DTB_MAX_SIZE);
 790
 791         boot_info = env->load_info;
 792         boot_info->entry = entry;
 793         boot_info->dt_base = dt_base;
 794         boot_info->dt_size = dt_size;
 795     }
 796
 797     if (kvm_enabled()) {
 798         kvmppc_init();
 799     }
 800 }
 801
 802 static int e500_ccsr_initfn(SysBusDevice *dev)
 803 {
 804     PPCE500CCSRState *ccsr;
 805
 806     ccsr = CCSR(dev);
 807     memory_region_init(&ccsr->ccsr_space, OBJECT(ccsr), "e500-ccsr",
 808                        MPC8544_CCSRBAR_SIZE);
 809     return 0;
 810 }
 811
 812 static void e500_ccsr_class_init(ObjectClass *klass, void *data)
 813 {
 814     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 815     k->init = e500_ccsr_initfn;
 816 }
 817
 818 static const TypeInfo e500_ccsr_info = {
 819     .name          = TYPE_CCSR,
 820     .parent        = TYPE_SYS_BUS_DEVICE,
 821     .instance_size = sizeof(PPCE500CCSRState),
 822     .class_init    = e500_ccsr_class_init,
 823 };
 824
 825 static void e500_register_types(void)
 826 {
 827     type_register_static(&e500_ccsr_info);
 828 }
 829
 830 type_init(e500_register_types)