migration/savevm: release gslist after dump_vmstate_json
[qemu/kevin.git] / target / mips / mips-defs.h
bloba831bb43844eaa16712664a477065d5b63787010
1 #ifndef QEMU_MIPS_DEFS_H
2 #define QEMU_MIPS_DEFS_H
4 /*
5 * If we want to use host float regs...
7 * #define USE_HOST_FLOAT_REGS
8 */
10 /* Real pages are variable size... */
11 #define MIPS_TLB_MAX 128
14 * bit definitions for insn_flags (ISAs/ASEs flags)
15 * ------------------------------------------------
18 * bits 0-31: MIPS base instruction sets
20 #define ISA_MIPS1 0x0000000000000001ULL
21 #define ISA_MIPS2 0x0000000000000002ULL
22 #define ISA_MIPS3 0x0000000000000004ULL
23 #define ISA_MIPS4 0x0000000000000008ULL
24 #define ISA_MIPS5 0x0000000000000010ULL
25 #define ISA_MIPS32 0x0000000000000020ULL
26 #define ISA_MIPS32R2 0x0000000000000040ULL
27 #define ISA_MIPS64 0x0000000000000080ULL
28 #define ISA_MIPS64R2 0x0000000000000100ULL
29 #define ISA_MIPS32R3 0x0000000000000200ULL
30 #define ISA_MIPS64R3 0x0000000000000400ULL
31 #define ISA_MIPS32R5 0x0000000000000800ULL
32 #define ISA_MIPS64R5 0x0000000000001000ULL
33 #define ISA_MIPS32R6 0x0000000000002000ULL
34 #define ISA_MIPS64R6 0x0000000000004000ULL
35 #define ISA_NANOMIPS32 0x0000000000008000ULL
37 * bits 32-47: MIPS ASEs
39 #define ASE_MIPS16 0x0000000100000000ULL
40 #define ASE_MIPS3D 0x0000000200000000ULL
41 #define ASE_MDMX 0x0000000400000000ULL
42 #define ASE_DSP 0x0000000800000000ULL
43 #define ASE_DSP_R2 0x0000001000000000ULL
44 #define ASE_DSP_R3 0x0000002000000000ULL
45 #define ASE_MT 0x0000004000000000ULL
46 #define ASE_SMARTMIPS 0x0000008000000000ULL
47 #define ASE_MICROMIPS 0x0000010000000000ULL
48 #define ASE_MSA 0x0000020000000000ULL
50 * bits 48-55: vendor-specific base instruction sets
52 #define INSN_LOONGSON2E 0x0001000000000000ULL
53 #define INSN_LOONGSON2F 0x0002000000000000ULL
54 #define INSN_VR54XX 0x0004000000000000ULL
55 #define INSN_R5900 0x0008000000000000ULL
57 * bits 56-63: vendor-specific ASEs
59 #define ASE_MMI 0x0100000000000000ULL
60 #define ASE_MXU 0x0200000000000000ULL
62 /* MIPS CPU defines. */
63 #define CPU_MIPS1 (ISA_MIPS1)
64 #define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2)
65 #define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3)
66 #define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4)
67 #define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX)
68 #define CPU_R5900 (CPU_MIPS3 | INSN_R5900)
69 #define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E)
70 #define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F)
72 #define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5)
74 /* MIPS Technologies "Release 1" */
75 #define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32)
76 #define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64)
78 /* MIPS Technologies "Release 2" */
79 #define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2)
80 #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
82 /* MIPS Technologies "Release 3" */
83 #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
84 #define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3)
86 /* MIPS Technologies "Release 5" */
87 #define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
88 #define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5 | ISA_MIPS64R5)
90 /* MIPS Technologies "Release 6" */
91 #define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6)
92 #define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6)
94 /* Wave Computing: "nanoMIPS" */
95 #define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32)
98 * Strictly follow the architecture standard:
99 * - Disallow "special" instruction handling for PMON/SPIM.
100 * Note that we still maintain Count/Compare to match the host clock.
102 * #define MIPS_STRICT_STANDARD 1
105 #endif /* QEMU_MIPS_DEFS_H */