target-i386/smm_helper.c

   1 /*
   2  *  x86 SMM helpers
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "cpu.h"
  21 #include "helper.h"
  22
  23 /* SMM support */
  24
  25 #if defined(CONFIG_USER_ONLY)
  26
  27 void do_smm_enter(X86CPU *cpu)
  28 {
  29 }
  30
  31 void helper_rsm(CPUX86State *env)
  32 {
  33 }
  34
  35 #else
  36
  37 #ifdef TARGET_X86_64
  38 #define SMM_REVISION_ID 0x00020064
  39 #else
  40 #define SMM_REVISION_ID 0x00020000
  41 #endif
  42
  43 void do_smm_enter(X86CPU *cpu)
  44 {
  45     CPUX86State *env = &cpu->env;
  46     target_ulong sm_state;
  47     SegmentCache *dt;
  48     int i, offset;
  49
  50     qemu_log_mask(CPU_LOG_INT, "SMM: enter\n");
  51     log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP);
  52
  53     env->hflags |= HF_SMM_MASK;
  54     cpu_smm_update(env);
  55
  56     sm_state = env->smbase + 0x8000;
  57
  58 #ifdef TARGET_X86_64
  59     for (i = 0; i < 6; i++) {
  60         dt = &env->segs[i];
  61         offset = 0x7e00 + i * 16;
  62         stw_phys(sm_state + offset, dt->selector);
  63         stw_phys(sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff);
  64         stl_phys(sm_state + offset + 4, dt->limit);
  65         stq_phys(sm_state + offset + 8, dt->base);
  66     }
  67
  68     stq_phys(sm_state + 0x7e68, env->gdt.base);
  69     stl_phys(sm_state + 0x7e64, env->gdt.limit);
  70
  71     stw_phys(sm_state + 0x7e70, env->ldt.selector);
  72     stq_phys(sm_state + 0x7e78, env->ldt.base);
  73     stl_phys(sm_state + 0x7e74, env->ldt.limit);
  74     stw_phys(sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff);
  75
  76     stq_phys(sm_state + 0x7e88, env->idt.base);
  77     stl_phys(sm_state + 0x7e84, env->idt.limit);
  78
  79     stw_phys(sm_state + 0x7e90, env->tr.selector);
  80     stq_phys(sm_state + 0x7e98, env->tr.base);
  81     stl_phys(sm_state + 0x7e94, env->tr.limit);
  82     stw_phys(sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff);
  83
  84     stq_phys(sm_state + 0x7ed0, env->efer);
  85
  86     stq_phys(sm_state + 0x7ff8, env->regs[R_EAX]);
  87     stq_phys(sm_state + 0x7ff0, env->regs[R_ECX]);
  88     stq_phys(sm_state + 0x7fe8, env->regs[R_EDX]);
  89     stq_phys(sm_state + 0x7fe0, env->regs[R_EBX]);
  90     stq_phys(sm_state + 0x7fd8, env->regs[R_ESP]);
  91     stq_phys(sm_state + 0x7fd0, env->regs[R_EBP]);
  92     stq_phys(sm_state + 0x7fc8, env->regs[R_ESI]);
  93     stq_phys(sm_state + 0x7fc0, env->regs[R_EDI]);
  94     for (i = 8; i < 16; i++) {
  95         stq_phys(sm_state + 0x7ff8 - i * 8, env->regs[i]);
  96     }
  97     stq_phys(sm_state + 0x7f78, env->eip);
  98     stl_phys(sm_state + 0x7f70, cpu_compute_eflags(env));
  99     stl_phys(sm_state + 0x7f68, env->dr[6]);
 100     stl_phys(sm_state + 0x7f60, env->dr[7]);
 101
 102     stl_phys(sm_state + 0x7f48, env->cr[4]);
 103     stl_phys(sm_state + 0x7f50, env->cr[3]);
 104     stl_phys(sm_state + 0x7f58, env->cr[0]);
 105
 106     stl_phys(sm_state + 0x7efc, SMM_REVISION_ID);
 107     stl_phys(sm_state + 0x7f00, env->smbase);
 108 #else
 109     stl_phys(sm_state + 0x7ffc, env->cr[0]);
 110     stl_phys(sm_state + 0x7ff8, env->cr[3]);
 111     stl_phys(sm_state + 0x7ff4, cpu_compute_eflags(env));
 112     stl_phys(sm_state + 0x7ff0, env->eip);
 113     stl_phys(sm_state + 0x7fec, env->regs[R_EDI]);
 114     stl_phys(sm_state + 0x7fe8, env->regs[R_ESI]);
 115     stl_phys(sm_state + 0x7fe4, env->regs[R_EBP]);
 116     stl_phys(sm_state + 0x7fe0, env->regs[R_ESP]);
 117     stl_phys(sm_state + 0x7fdc, env->regs[R_EBX]);
 118     stl_phys(sm_state + 0x7fd8, env->regs[R_EDX]);
 119     stl_phys(sm_state + 0x7fd4, env->regs[R_ECX]);
 120     stl_phys(sm_state + 0x7fd0, env->regs[R_EAX]);
 121     stl_phys(sm_state + 0x7fcc, env->dr[6]);
 122     stl_phys(sm_state + 0x7fc8, env->dr[7]);
 123
 124     stl_phys(sm_state + 0x7fc4, env->tr.selector);
 125     stl_phys(sm_state + 0x7f64, env->tr.base);
 126     stl_phys(sm_state + 0x7f60, env->tr.limit);
 127     stl_phys(sm_state + 0x7f5c, (env->tr.flags >> 8) & 0xf0ff);
 128
 129     stl_phys(sm_state + 0x7fc0, env->ldt.selector);
 130     stl_phys(sm_state + 0x7f80, env->ldt.base);
 131     stl_phys(sm_state + 0x7f7c, env->ldt.limit);
 132     stl_phys(sm_state + 0x7f78, (env->ldt.flags >> 8) & 0xf0ff);
 133
 134     stl_phys(sm_state + 0x7f74, env->gdt.base);
 135     stl_phys(sm_state + 0x7f70, env->gdt.limit);
 136
 137     stl_phys(sm_state + 0x7f58, env->idt.base);
 138     stl_phys(sm_state + 0x7f54, env->idt.limit);
 139
 140     for (i = 0; i < 6; i++) {
 141         dt = &env->segs[i];
 142         if (i < 3) {
 143             offset = 0x7f84 + i * 12;
 144         } else {
 145             offset = 0x7f2c + (i - 3) * 12;
 146         }
 147         stl_phys(sm_state + 0x7fa8 + i * 4, dt->selector);
 148         stl_phys(sm_state + offset + 8, dt->base);
 149         stl_phys(sm_state + offset + 4, dt->limit);
 150         stl_phys(sm_state + offset, (dt->flags >> 8) & 0xf0ff);
 151     }
 152     stl_phys(sm_state + 0x7f14, env->cr[4]);
 153
 154     stl_phys(sm_state + 0x7efc, SMM_REVISION_ID);
 155     stl_phys(sm_state + 0x7ef8, env->smbase);
 156 #endif
 157     /* init SMM cpu state */
 158
 159 #ifdef TARGET_X86_64
 160     cpu_load_efer(env, 0);
 161 #endif
 162     cpu_load_eflags(env, 0, ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C |
 163                               DF_MASK));
 164     env->eip = 0x00008000;
 165     cpu_x86_load_seg_cache(env, R_CS, (env->smbase >> 4) & 0xffff, env->smbase,
 166                            0xffffffff, 0);
 167     cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffffffff, 0);
 168     cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffffffff, 0);
 169     cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffffffff, 0);
 170     cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffffffff, 0);
 171     cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffffffff, 0);
 172
 173     cpu_x86_update_cr0(env,
 174                        env->cr[0] & ~(CR0_PE_MASK | CR0_EM_MASK | CR0_TS_MASK |
 175                                       CR0_PG_MASK));
 176     cpu_x86_update_cr4(env, 0);
 177     env->dr[7] = 0x00000400;
 178     CC_OP = CC_OP_EFLAGS;
 179 }
 180
 181 void helper_rsm(CPUX86State *env)
 182 {
 183     X86CPU *cpu = x86_env_get_cpu(env);
 184     target_ulong sm_state;
 185     int i, offset;
 186     uint32_t val;
 187
 188     sm_state = env->smbase + 0x8000;
 189 #ifdef TARGET_X86_64
 190     cpu_load_efer(env, ldq_phys(sm_state + 0x7ed0));
 191
 192     for (i = 0; i < 6; i++) {
 193         offset = 0x7e00 + i * 16;
 194         cpu_x86_load_seg_cache(env, i,
 195                                lduw_phys(sm_state + offset),
 196                                ldq_phys(sm_state + offset + 8),
 197                                ldl_phys(sm_state + offset + 4),
 198                                (lduw_phys(sm_state + offset + 2) &
 199                                 0xf0ff) << 8);
 200     }
 201
 202     env->gdt.base = ldq_phys(sm_state + 0x7e68);
 203     env->gdt.limit = ldl_phys(sm_state + 0x7e64);
 204
 205     env->ldt.selector = lduw_phys(sm_state + 0x7e70);
 206     env->ldt.base = ldq_phys(sm_state + 0x7e78);
 207     env->ldt.limit = ldl_phys(sm_state + 0x7e74);
 208     env->ldt.flags = (lduw_phys(sm_state + 0x7e72) & 0xf0ff) << 8;
 209
 210     env->idt.base = ldq_phys(sm_state + 0x7e88);
 211     env->idt.limit = ldl_phys(sm_state + 0x7e84);
 212
 213     env->tr.selector = lduw_phys(sm_state + 0x7e90);
 214     env->tr.base = ldq_phys(sm_state + 0x7e98);
 215     env->tr.limit = ldl_phys(sm_state + 0x7e94);
 216     env->tr.flags = (lduw_phys(sm_state + 0x7e92) & 0xf0ff) << 8;
 217
 218     env->regs[R_EAX] = ldq_phys(sm_state + 0x7ff8);
 219     env->regs[R_ECX] = ldq_phys(sm_state + 0x7ff0);
 220     env->regs[R_EDX] = ldq_phys(sm_state + 0x7fe8);
 221     env->regs[R_EBX] = ldq_phys(sm_state + 0x7fe0);
 222     env->regs[R_ESP] = ldq_phys(sm_state + 0x7fd8);
 223     env->regs[R_EBP] = ldq_phys(sm_state + 0x7fd0);
 224     env->regs[R_ESI] = ldq_phys(sm_state + 0x7fc8);
 225     env->regs[R_EDI] = ldq_phys(sm_state + 0x7fc0);
 226     for (i = 8; i < 16; i++) {
 227         env->regs[i] = ldq_phys(sm_state + 0x7ff8 - i * 8);
 228     }
 229     env->eip = ldq_phys(sm_state + 0x7f78);
 230     cpu_load_eflags(env, ldl_phys(sm_state + 0x7f70),
 231                     ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
 232     env->dr[6] = ldl_phys(sm_state + 0x7f68);
 233     env->dr[7] = ldl_phys(sm_state + 0x7f60);
 234
 235     cpu_x86_update_cr4(env, ldl_phys(sm_state + 0x7f48));
 236     cpu_x86_update_cr3(env, ldl_phys(sm_state + 0x7f50));
 237     cpu_x86_update_cr0(env, ldl_phys(sm_state + 0x7f58));
 238
 239     val = ldl_phys(sm_state + 0x7efc); /* revision ID */
 240     if (val & 0x20000) {
 241         env->smbase = ldl_phys(sm_state + 0x7f00) & ~0x7fff;
 242     }
 243 #else
 244     cpu_x86_update_cr0(env, ldl_phys(sm_state + 0x7ffc));
 245     cpu_x86_update_cr3(env, ldl_phys(sm_state + 0x7ff8));
 246     cpu_load_eflags(env, ldl_phys(sm_state + 0x7ff4),
 247                     ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
 248     env->eip = ldl_phys(sm_state + 0x7ff0);
 249     env->regs[R_EDI] = ldl_phys(sm_state + 0x7fec);
 250     env->regs[R_ESI] = ldl_phys(sm_state + 0x7fe8);
 251     env->regs[R_EBP] = ldl_phys(sm_state + 0x7fe4);
 252     env->regs[R_ESP] = ldl_phys(sm_state + 0x7fe0);
 253     env->regs[R_EBX] = ldl_phys(sm_state + 0x7fdc);
 254     env->regs[R_EDX] = ldl_phys(sm_state + 0x7fd8);
 255     env->regs[R_ECX] = ldl_phys(sm_state + 0x7fd4);
 256     env->regs[R_EAX] = ldl_phys(sm_state + 0x7fd0);
 257     env->dr[6] = ldl_phys(sm_state + 0x7fcc);
 258     env->dr[7] = ldl_phys(sm_state + 0x7fc8);
 259
 260     env->tr.selector = ldl_phys(sm_state + 0x7fc4) & 0xffff;
 261     env->tr.base = ldl_phys(sm_state + 0x7f64);
 262     env->tr.limit = ldl_phys(sm_state + 0x7f60);
 263     env->tr.flags = (ldl_phys(sm_state + 0x7f5c) & 0xf0ff) << 8;
 264
 265     env->ldt.selector = ldl_phys(sm_state + 0x7fc0) & 0xffff;
 266     env->ldt.base = ldl_phys(sm_state + 0x7f80);
 267     env->ldt.limit = ldl_phys(sm_state + 0x7f7c);
 268     env->ldt.flags = (ldl_phys(sm_state + 0x7f78) & 0xf0ff) << 8;
 269
 270     env->gdt.base = ldl_phys(sm_state + 0x7f74);
 271     env->gdt.limit = ldl_phys(sm_state + 0x7f70);
 272
 273     env->idt.base = ldl_phys(sm_state + 0x7f58);
 274     env->idt.limit = ldl_phys(sm_state + 0x7f54);
 275
 276     for (i = 0; i < 6; i++) {
 277         if (i < 3) {
 278             offset = 0x7f84 + i * 12;
 279         } else {
 280             offset = 0x7f2c + (i - 3) * 12;
 281         }
 282         cpu_x86_load_seg_cache(env, i,
 283                                ldl_phys(sm_state + 0x7fa8 + i * 4) & 0xffff,
 284                                ldl_phys(sm_state + offset + 8),
 285                                ldl_phys(sm_state + offset + 4),
 286                                (ldl_phys(sm_state + offset) & 0xf0ff) << 8);
 287     }
 288     cpu_x86_update_cr4(env, ldl_phys(sm_state + 0x7f14));
 289
 290     val = ldl_phys(sm_state + 0x7efc); /* revision ID */
 291     if (val & 0x20000) {
 292         env->smbase = ldl_phys(sm_state + 0x7ef8) & ~0x7fff;
 293     }
 294 #endif
 295     CC_OP = CC_OP_EFLAGS;
 296     env->hflags &= ~HF_SMM_MASK;
 297     cpu_smm_update(env);
 298
 299     qemu_log_mask(CPU_LOG_INT, "SMM: after RSM\n");
 300     log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP);
 301 }
 302
 303 #endif /* !CONFIG_USER_ONLY */