2 * QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 * PCI bus layout on a real G5 (U3 based):
27 * 0000:f0:0b.0 Host bridge [0600]: Apple Computer Inc. U3 AGP [106b:004b]
28 * 0000:f0:10.0 VGA compatible controller [0300]: ATI Technologies Inc RV350 AP [Radeon 9600] [1002:4150]
29 * 0001:00:00.0 Host bridge [0600]: Apple Computer Inc. CPC945 HT Bridge [106b:004a]
30 * 0001:00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12)
31 * 0001:00:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12)
32 * 0001:00:03.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0045]
33 * 0001:00:04.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0046]
34 * 0001:00:05.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0047]
35 * 0001:00:06.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0048]
36 * 0001:00:07.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0049]
37 * 0001:01:07.0 Class [ff00]: Apple Computer Inc. K2 KeyLargo Mac/IO [106b:0041] (rev 20)
38 * 0001:01:08.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040]
39 * 0001:01:09.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040]
40 * 0001:02:0b.0 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43)
41 * 0001:02:0b.1 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43)
42 * 0001:02:0b.2 USB Controller [0c03]: NEC Corporation USB 2.0 [1033:00e0] (rev 04)
43 * 0001:03:0d.0 Class [ff00]: Apple Computer Inc. K2 ATA/100 [106b:0043]
44 * 0001:03:0e.0 FireWire (IEEE 1394) [0c00]: Apple Computer Inc. K2 FireWire [106b:0042]
45 * 0001:04:0f.0 Ethernet controller [0200]: Apple Computer Inc. K2 GMAC (Sun GEM) [106b:004c]
46 * 0001:05:0c.0 IDE interface [0101]: Broadcom K2 SATA [1166:0240]
50 #include "hw/ppc/ppc.h"
51 #include "hw/ppc/mac.h"
52 #include "hw/input/adb.h"
53 #include "hw/ppc/mac_dbdma.h"
54 #include "hw/timer/m48t59.h"
55 #include "hw/pci/pci.h"
57 #include "sysemu/sysemu.h"
58 #include "hw/boards.h"
59 #include "hw/nvram/fw_cfg.h"
60 #include "hw/char/escc.h"
61 #include "hw/ppc/openpic.h"
63 #include "hw/loader.h"
65 #include "sysemu/kvm.h"
68 #include "sysemu/blockdev.h"
69 #include "exec/address-spaces.h"
70 #include "hw/sysbus.h"
73 #define CFG_ADDR 0xf0000510
74 #define TBFREQ (100UL * 1000UL * 1000UL)
75 #define CLOCKFREQ (266UL * 1000UL * 1000UL)
76 #define BUSFREQ (100UL * 1000UL * 1000UL)
82 #define UNIN_DPRINTF(fmt, ...) \
83 do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
85 #define UNIN_DPRINTF(fmt, ...)
89 static void unin_write(void *opaque
, hwaddr addr
, uint64_t value
,
92 UNIN_DPRINTF("write addr " TARGET_FMT_plx
" val %"PRIx64
"\n", addr
, value
);
94 *(int*)opaque
= value
;
98 static uint64_t unin_read(void *opaque
, hwaddr addr
, unsigned size
)
105 value
= *(int*)opaque
;
108 UNIN_DPRINTF("readl addr " TARGET_FMT_plx
" val %x\n", addr
, value
);
113 static const MemoryRegionOps unin_ops
= {
116 .endianness
= DEVICE_NATIVE_ENDIAN
,
119 static int fw_cfg_boot_set(void *opaque
, const char *boot_device
)
121 fw_cfg_add_i16(opaque
, FW_CFG_BOOT_DEVICE
, boot_device
[0]);
125 static uint64_t translate_kernel_address(void *opaque
, uint64_t addr
)
127 return (addr
& 0x0fffffff) + KERNEL_LOAD_ADDR
;
130 static hwaddr
round_page(hwaddr addr
)
132 return (addr
+ TARGET_PAGE_SIZE
- 1) & TARGET_PAGE_MASK
;
135 static void ppc_core99_reset(void *opaque
)
137 PowerPCCPU
*cpu
= opaque
;
140 /* 970 CPUs want to get their initial IP as part of their boot protocol */
141 cpu
->env
.nip
= PROM_ADDR
+ 0x100;
144 /* PowerPC Mac99 hardware initialisation */
145 static void ppc_core99_init(MachineState
*machine
)
147 ram_addr_t ram_size
= machine
->ram_size
;
148 const char *cpu_model
= machine
->cpu_model
;
149 const char *kernel_filename
= machine
->kernel_filename
;
150 const char *kernel_cmdline
= machine
->kernel_cmdline
;
151 const char *initrd_filename
= machine
->initrd_filename
;
152 const char *boot_device
= machine
->boot_order
;
153 PowerPCCPU
*cpu
= NULL
;
154 CPUPPCState
*env
= NULL
;
156 qemu_irq
*pic
, **openpic_irqs
;
157 MemoryRegion
*isa
= g_new(MemoryRegion
, 1);
158 MemoryRegion
*unin_memory
= g_new(MemoryRegion
, 1);
159 MemoryRegion
*unin2_memory
= g_new(MemoryRegion
, 1);
160 int linux_boot
, i
, j
, k
;
161 MemoryRegion
*ram
= g_new(MemoryRegion
, 1), *bios
= g_new(MemoryRegion
, 1);
162 hwaddr kernel_base
, initrd_base
, cmdline_base
= 0;
163 long kernel_size
, initrd_size
;
166 MACIOIDEState
*macio_ide
;
168 MacIONVRAMState
*nvr
;
170 MemoryRegion
*pic_mem
, *escc_mem
;
171 MemoryRegion
*escc_bar
= g_new(MemoryRegion
, 1);
173 DriveInfo
*hd
[MAX_IDE_BUS
* MAX_IDE_DEVS
];
178 int *token
= g_new(int, 1);
180 linux_boot
= (kernel_filename
!= NULL
);
183 if (cpu_model
== NULL
)
189 for (i
= 0; i
< smp_cpus
; i
++) {
190 cpu
= cpu_ppc_init(cpu_model
);
192 fprintf(stderr
, "Unable to find PowerPC CPU definition\n");
197 /* Set time-base frequency to 100 Mhz */
198 cpu_ppc_tb_init(env
, TBFREQ
);
199 qemu_register_reset(ppc_core99_reset
, cpu
);
203 memory_region_init_ram(ram
, NULL
, "ppc_core99.ram", ram_size
);
204 vmstate_register_ram_global(ram
);
205 memory_region_add_subregion(get_system_memory(), 0, ram
);
207 /* allocate and load BIOS */
208 memory_region_init_ram(bios
, NULL
, "ppc_core99.bios", BIOS_SIZE
);
209 vmstate_register_ram_global(bios
);
210 if (bios_name
== NULL
)
211 bios_name
= PROM_FILENAME
;
212 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
213 memory_region_set_readonly(bios
, true);
214 memory_region_add_subregion(get_system_memory(), PROM_ADDR
, bios
);
216 /* Load OpenBIOS (ELF) */
218 bios_size
= load_elf(filename
, NULL
, NULL
, NULL
,
219 NULL
, NULL
, 1, ELF_MACHINE
, 0);
225 if (bios_size
< 0 || bios_size
> BIOS_SIZE
) {
226 hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name
);
231 uint64_t lowaddr
= 0;
239 kernel_base
= KERNEL_LOAD_ADDR
;
241 kernel_size
= load_elf(kernel_filename
, translate_kernel_address
, NULL
,
242 NULL
, &lowaddr
, NULL
, 1, ELF_MACHINE
, 0);
244 kernel_size
= load_aout(kernel_filename
, kernel_base
,
245 ram_size
- kernel_base
, bswap_needed
,
248 kernel_size
= load_image_targphys(kernel_filename
,
250 ram_size
- kernel_base
);
251 if (kernel_size
< 0) {
252 hw_error("qemu: could not load kernel '%s'\n", kernel_filename
);
256 if (initrd_filename
) {
257 initrd_base
= round_page(kernel_base
+ kernel_size
+ KERNEL_GAP
);
258 initrd_size
= load_image_targphys(initrd_filename
, initrd_base
,
259 ram_size
- initrd_base
);
260 if (initrd_size
< 0) {
261 hw_error("qemu: could not load initial ram disk '%s'\n",
265 cmdline_base
= round_page(initrd_base
+ initrd_size
);
269 cmdline_base
= round_page(kernel_base
+ kernel_size
+ KERNEL_GAP
);
271 ppc_boot_device
= 'm';
277 ppc_boot_device
= '\0';
278 /* We consider that NewWorld PowerMac never have any floppy drive
279 * For now, OHW cannot boot from the network.
281 for (i
= 0; boot_device
[i
] != '\0'; i
++) {
282 if (boot_device
[i
] >= 'c' && boot_device
[i
] <= 'f') {
283 ppc_boot_device
= boot_device
[i
];
287 if (ppc_boot_device
== '\0') {
288 fprintf(stderr
, "No valid boot device for Mac99 machine\n");
293 /* Register 8 MB of ISA IO space */
294 memory_region_init_alias(isa
, NULL
, "isa_mmio",
295 get_system_io(), 0, 0x00800000);
296 memory_region_add_subregion(get_system_memory(), 0xf2000000, isa
);
298 /* UniN init: XXX should be a real device */
299 memory_region_init_io(unin_memory
, NULL
, &unin_ops
, token
, "unin", 0x1000);
300 memory_region_add_subregion(get_system_memory(), 0xf8000000, unin_memory
);
302 memory_region_init_io(unin2_memory
, NULL
, &unin_ops
, token
, "unin", 0x1000);
303 memory_region_add_subregion(get_system_memory(), 0xf3000000, unin2_memory
);
305 openpic_irqs
= g_malloc0(smp_cpus
* sizeof(qemu_irq
*));
307 g_malloc0(smp_cpus
* sizeof(qemu_irq
) * OPENPIC_OUTPUT_NB
);
308 for (i
= 0; i
< smp_cpus
; i
++) {
309 /* Mac99 IRQ connection between OpenPIC outputs pins
310 * and PowerPC input pins
312 switch (PPC_INPUT(env
)) {
313 case PPC_FLAGS_INPUT_6xx
:
314 openpic_irqs
[i
] = openpic_irqs
[0] + (i
* OPENPIC_OUTPUT_NB
);
315 openpic_irqs
[i
][OPENPIC_OUTPUT_INT
] =
316 ((qemu_irq
*)env
->irq_inputs
)[PPC6xx_INPUT_INT
];
317 openpic_irqs
[i
][OPENPIC_OUTPUT_CINT
] =
318 ((qemu_irq
*)env
->irq_inputs
)[PPC6xx_INPUT_INT
];
319 openpic_irqs
[i
][OPENPIC_OUTPUT_MCK
] =
320 ((qemu_irq
*)env
->irq_inputs
)[PPC6xx_INPUT_MCP
];
321 /* Not connected ? */
322 openpic_irqs
[i
][OPENPIC_OUTPUT_DEBUG
] = NULL
;
324 openpic_irqs
[i
][OPENPIC_OUTPUT_RESET
] =
325 ((qemu_irq
*)env
->irq_inputs
)[PPC6xx_INPUT_HRESET
];
327 #if defined(TARGET_PPC64)
328 case PPC_FLAGS_INPUT_970
:
329 openpic_irqs
[i
] = openpic_irqs
[0] + (i
* OPENPIC_OUTPUT_NB
);
330 openpic_irqs
[i
][OPENPIC_OUTPUT_INT
] =
331 ((qemu_irq
*)env
->irq_inputs
)[PPC970_INPUT_INT
];
332 openpic_irqs
[i
][OPENPIC_OUTPUT_CINT
] =
333 ((qemu_irq
*)env
->irq_inputs
)[PPC970_INPUT_INT
];
334 openpic_irqs
[i
][OPENPIC_OUTPUT_MCK
] =
335 ((qemu_irq
*)env
->irq_inputs
)[PPC970_INPUT_MCP
];
336 /* Not connected ? */
337 openpic_irqs
[i
][OPENPIC_OUTPUT_DEBUG
] = NULL
;
339 openpic_irqs
[i
][OPENPIC_OUTPUT_RESET
] =
340 ((qemu_irq
*)env
->irq_inputs
)[PPC970_INPUT_HRESET
];
342 #endif /* defined(TARGET_PPC64) */
344 hw_error("Bus model not supported on mac99 machine\n");
349 pic
= g_new(qemu_irq
, 64);
351 dev
= qdev_create(NULL
, TYPE_OPENPIC
);
352 qdev_prop_set_uint32(dev
, "model", OPENPIC_MODEL_RAVEN
);
353 qdev_init_nofail(dev
);
354 s
= SYS_BUS_DEVICE(dev
);
355 pic_mem
= s
->mmio
[0].memory
;
357 for (i
= 0; i
< smp_cpus
; i
++) {
358 for (j
= 0; j
< OPENPIC_OUTPUT_NB
; j
++) {
359 sysbus_connect_irq(s
, k
++, openpic_irqs
[i
][j
]);
363 for (i
= 0; i
< 64; i
++) {
364 pic
[i
] = qdev_get_gpio_in(dev
, i
);
367 if (PPC_INPUT(env
) == PPC_FLAGS_INPUT_970
) {
368 /* 970 gets a U3 bus */
369 pci_bus
= pci_pmac_u3_init(pic
, get_system_memory(), get_system_io());
370 machine_arch
= ARCH_MAC99_U3
;
372 pci_bus
= pci_pmac_init(pic
, get_system_memory(), get_system_io());
373 machine_arch
= ARCH_MAC99
;
375 /* init basic PC hardware */
376 pci_vga_init(pci_bus
);
378 escc_mem
= escc_init(0, pic
[0x25], pic
[0x24],
379 serial_hds
[0], serial_hds
[1], ESCC_CLOCK
, 4);
380 memory_region_init_alias(escc_bar
, NULL
, "escc-bar",
381 escc_mem
, 0, memory_region_size(escc_mem
));
383 for(i
= 0; i
< nb_nics
; i
++)
384 pci_nic_init_nofail(&nd_table
[i
], pci_bus
, "ne2k_pci", NULL
);
386 ide_drive_get(hd
, MAX_IDE_BUS
);
388 macio
= pci_create(pci_bus
, -1, TYPE_NEWWORLD_MACIO
);
390 qdev_connect_gpio_out(dev
, 0, pic
[0x19]); /* CUDA */
391 qdev_connect_gpio_out(dev
, 1, pic
[0x0d]); /* IDE */
392 qdev_connect_gpio_out(dev
, 2, pic
[0x02]); /* IDE DMA */
393 qdev_connect_gpio_out(dev
, 3, pic
[0x0e]); /* IDE */
394 qdev_connect_gpio_out(dev
, 4, pic
[0x03]); /* IDE DMA */
395 macio_init(macio
, pic_mem
, escc_bar
);
397 /* We only emulate 2 out of 3 IDE controllers for now */
398 macio_ide
= MACIO_IDE(object_resolve_path_component(OBJECT(macio
),
400 macio_ide_init_drives(macio_ide
, hd
);
402 macio_ide
= MACIO_IDE(object_resolve_path_component(OBJECT(macio
),
404 macio_ide_init_drives(macio_ide
, &hd
[MAX_IDE_DEVS
]);
406 dev
= DEVICE(object_resolve_path_component(OBJECT(macio
), "cuda"));
407 adb_bus
= qdev_get_child_bus(dev
, "adb.0");
408 dev
= qdev_create(adb_bus
, TYPE_ADB_KEYBOARD
);
409 qdev_init_nofail(dev
);
410 dev
= qdev_create(adb_bus
, TYPE_ADB_MOUSE
);
411 qdev_init_nofail(dev
);
413 if (usb_enabled(machine_arch
== ARCH_MAC99_U3
)) {
414 pci_create_simple(pci_bus
, -1, "pci-ohci");
415 /* U3 needs to use USB for input because Linux doesn't support via-cuda
417 if (machine_arch
== ARCH_MAC99_U3
) {
418 usbdevice_create("keyboard");
419 usbdevice_create("mouse");
423 if (graphic_depth
!= 15 && graphic_depth
!= 32 && graphic_depth
!= 8)
426 /* The NewWorld NVRAM is not located in the MacIO device */
427 dev
= qdev_create(NULL
, TYPE_MACIO_NVRAM
);
428 qdev_prop_set_uint32(dev
, "size", 0x2000);
429 qdev_prop_set_uint32(dev
, "it_shift", 1);
430 qdev_init_nofail(dev
);
431 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, 0xFFF04000);
432 nvr
= MACIO_NVRAM(dev
);
433 pmac_format_nvram_partition(nvr
, 0x2000);
434 /* No PCI init: the BIOS will do it */
436 fw_cfg
= fw_cfg_init(0, 0, CFG_ADDR
, CFG_ADDR
+ 2);
437 fw_cfg_add_i16(fw_cfg
, FW_CFG_MAX_CPUS
, (uint16_t)max_cpus
);
438 fw_cfg_add_i32(fw_cfg
, FW_CFG_ID
, 1);
439 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
440 fw_cfg_add_i16(fw_cfg
, FW_CFG_MACHINE_ID
, machine_arch
);
441 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, kernel_base
);
442 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
443 if (kernel_cmdline
) {
444 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, cmdline_base
);
445 pstrcpy_targphys("cmdline", cmdline_base
, TARGET_PAGE_SIZE
, kernel_cmdline
);
447 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, 0);
449 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, initrd_base
);
450 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, initrd_size
);
451 fw_cfg_add_i16(fw_cfg
, FW_CFG_BOOT_DEVICE
, ppc_boot_device
);
453 fw_cfg_add_i16(fw_cfg
, FW_CFG_PPC_WIDTH
, graphic_width
);
454 fw_cfg_add_i16(fw_cfg
, FW_CFG_PPC_HEIGHT
, graphic_height
);
455 fw_cfg_add_i16(fw_cfg
, FW_CFG_PPC_DEPTH
, graphic_depth
);
457 fw_cfg_add_i32(fw_cfg
, FW_CFG_PPC_IS_KVM
, kvm_enabled());
462 fw_cfg_add_i32(fw_cfg
, FW_CFG_PPC_TBFREQ
, kvmppc_get_tbfreq());
463 hypercall
= g_malloc(16);
464 kvmppc_get_hypercall(env
, hypercall
, 16);
465 fw_cfg_add_bytes(fw_cfg
, FW_CFG_PPC_KVM_HC
, hypercall
, 16);
466 fw_cfg_add_i32(fw_cfg
, FW_CFG_PPC_KVM_PID
, getpid());
469 fw_cfg_add_i32(fw_cfg
, FW_CFG_PPC_TBFREQ
, TBFREQ
);
471 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */
472 fw_cfg_add_i32(fw_cfg
, FW_CFG_PPC_CLOCKFREQ
, CLOCKFREQ
);
473 fw_cfg_add_i32(fw_cfg
, FW_CFG_PPC_BUSFREQ
, BUSFREQ
);
475 qemu_register_boot_set(fw_cfg_boot_set
, fw_cfg
);
478 static QEMUMachine core99_machine
= {
480 .desc
= "Mac99 based PowerMAC",
481 .init
= ppc_core99_init
,
482 .max_cpus
= MAX_CPUS
,
483 .default_boot_order
= "cd",
486 static void core99_machine_init(void)
488 qemu_register_machine(&core99_machine
);
491 machine_init(core99_machine_init
);