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hw/arm/xlnx-versal: Use qdev_prop_set_array()
[qemu/kevin.git] / hw / arm / xlnx-versal.c
blob9600551c442255b564f5b77021ff693b494d8817
1 /*
2 * Xilinx Versal SoC model.
3 *
4 * Copyright (c) 2018 Xilinx Inc.
5 * Written by Edgar E. Iglesias
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
10 */
11
12 #include "qemu/osdep.h"
13 #include "qemu/units.h"
14 #include "qapi/error.h"
15 #include "qapi/qmp/qlist.h"
16 #include "qemu/module.h"
17 #include "hw/sysbus.h"
18 #include "net/net.h"
19 #include "sysemu/sysemu.h"
20 #include "sysemu/kvm.h"
21 #include "hw/arm/boot.h"
22 #include "kvm_arm.h"
23 #include "hw/misc/unimp.h"
24 #include "hw/arm/xlnx-versal.h"
25 #include "qemu/log.h"
26
27 #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
28 #define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f")
29 #define GEM_REVISION 0x40070106
30
31 #define VERSAL_NUM_PMC_APB_IRQS 18
32 #define NUM_OSPI_IRQ_LINES 3
33
34 static void versal_create_apu_cpus(Versal *s)
35 {
36 int i;
37
38 object_initialize_child(OBJECT(s), "apu-cluster", &s->fpd.apu.cluster,
39 TYPE_CPU_CLUSTER);
40 qdev_prop_set_uint32(DEVICE(&s->fpd.apu.cluster), "cluster-id", 0);
41
42 for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) {
43 Object *obj;
44
45 object_initialize_child(OBJECT(&s->fpd.apu.cluster),
46 "apu-cpu[*]", &s->fpd.apu.cpu[i],
47 XLNX_VERSAL_ACPU_TYPE);
48 obj = OBJECT(&s->fpd.apu.cpu[i]);
49 if (i) {
50 /* Secondary CPUs start in powered-down state */
51 object_property_set_bool(obj, "start-powered-off", true,
52 &error_abort);
53 }
54
55 object_property_set_int(obj, "core-count", ARRAY_SIZE(s->fpd.apu.cpu),
56 &error_abort);
57 object_property_set_link(obj, "memory", OBJECT(&s->fpd.apu.mr),
58 &error_abort);
59 qdev_realize(DEVICE(obj), NULL, &error_fatal);
60 }
61
62 qdev_realize(DEVICE(&s->fpd.apu.cluster), NULL, &error_fatal);
63 }
64
65 static void versal_create_apu_gic(Versal *s, qemu_irq *pic)
66 {
67 static const uint64_t addrs[] = {
68 MM_GIC_APU_DIST_MAIN,
69 MM_GIC_APU_REDIST_0
70 };
71 SysBusDevice *gicbusdev;
72 DeviceState *gicdev;
73 QList *redist_region_count;
74 int nr_apu_cpus = ARRAY_SIZE(s->fpd.apu.cpu);
75 int i;
76
77 object_initialize_child(OBJECT(s), "apu-gic", &s->fpd.apu.gic,
78 gicv3_class_name());
79 gicbusdev = SYS_BUS_DEVICE(&s->fpd.apu.gic);
80 gicdev = DEVICE(&s->fpd.apu.gic);
81 qdev_prop_set_uint32(gicdev, "revision", 3);
82 qdev_prop_set_uint32(gicdev, "num-cpu", nr_apu_cpus);
83 qdev_prop_set_uint32(gicdev, "num-irq", XLNX_VERSAL_NR_IRQS + 32);
84
85 redist_region_count = qlist_new();
86 qlist_append_int(redist_region_count, nr_apu_cpus);
87 qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count);
88
89 qdev_prop_set_bit(gicdev, "has-security-extensions", true);
90
91 sysbus_realize(SYS_BUS_DEVICE(&s->fpd.apu.gic), &error_fatal);
92
93 for (i = 0; i < ARRAY_SIZE(addrs); i++) {
94 MemoryRegion *mr;
95
96 mr = sysbus_mmio_get_region(gicbusdev, i);
97 memory_region_add_subregion(&s->fpd.apu.mr, addrs[i], mr);
98 }
99
100 for (i = 0; i < nr_apu_cpus; i++) {
101 DeviceState *cpudev = DEVICE(&s->fpd.apu.cpu[i]);
102 int ppibase = XLNX_VERSAL_NR_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
103 qemu_irq maint_irq;
104 int ti;
105 /* Mapping from the output timer irq lines from the CPU to the
106 * GIC PPI inputs.
107 */
108 const int timer_irq[] = {
109 [GTIMER_PHYS] = VERSAL_TIMER_NS_EL1_IRQ,
110 [GTIMER_VIRT] = VERSAL_TIMER_VIRT_IRQ,
111 [GTIMER_HYP] = VERSAL_TIMER_NS_EL2_IRQ,
112 [GTIMER_SEC] = VERSAL_TIMER_S_EL1_IRQ,
113 };
114
115 for (ti = 0; ti < ARRAY_SIZE(timer_irq); ti++) {
116 qdev_connect_gpio_out(cpudev, ti,
117 qdev_get_gpio_in(gicdev,
118 ppibase + timer_irq[ti]));
119 }
120 maint_irq = qdev_get_gpio_in(gicdev,
121 ppibase + VERSAL_GIC_MAINT_IRQ);
122 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
123 0, maint_irq);
124 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
125 sysbus_connect_irq(gicbusdev, i + nr_apu_cpus,
126 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
127 sysbus_connect_irq(gicbusdev, i + 2 * nr_apu_cpus,
128 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
129 sysbus_connect_irq(gicbusdev, i + 3 * nr_apu_cpus,
130 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
131 }
132
133 for (i = 0; i < XLNX_VERSAL_NR_IRQS; i++) {
134 pic[i] = qdev_get_gpio_in(gicdev, i);
135 }
136 }
137
138 static void versal_create_rpu_cpus(Versal *s)
139 {
140 int i;
141
142 object_initialize_child(OBJECT(s), "rpu-cluster", &s->lpd.rpu.cluster,
143 TYPE_CPU_CLUSTER);
144 qdev_prop_set_uint32(DEVICE(&s->lpd.rpu.cluster), "cluster-id", 1);
145
146 for (i = 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) {
147 Object *obj;
148
149 object_initialize_child(OBJECT(&s->lpd.rpu.cluster),
150 "rpu-cpu[*]", &s->lpd.rpu.cpu[i],
151 XLNX_VERSAL_RCPU_TYPE);
152 obj = OBJECT(&s->lpd.rpu.cpu[i]);
153 object_property_set_bool(obj, "start-powered-off", true,
154 &error_abort);
155
156 object_property_set_int(obj, "mp-affinity", 0x100 | i, &error_abort);
157 object_property_set_int(obj, "core-count", ARRAY_SIZE(s->lpd.rpu.cpu),
158 &error_abort);
159 object_property_set_link(obj, "memory", OBJECT(&s->lpd.rpu.mr),
160 &error_abort);
161 qdev_realize(DEVICE(obj), NULL, &error_fatal);
162 }
163
164 qdev_realize(DEVICE(&s->lpd.rpu.cluster), NULL, &error_fatal);
165 }
166
167 static void versal_create_uarts(Versal *s, qemu_irq *pic)
168 {
169 int i;
170
171 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) {
172 static const int irqs[] = { VERSAL_UART0_IRQ_0, VERSAL_UART1_IRQ_0};
173 static const uint64_t addrs[] = { MM_UART0, MM_UART1 };
174 char *name = g_strdup_printf("uart%d", i);
175 DeviceState *dev;
176 MemoryRegion *mr;
177
178 object_initialize_child(OBJECT(s), name, &s->lpd.iou.uart[i],
179 TYPE_PL011);
180 dev = DEVICE(&s->lpd.iou.uart[i]);
181 qdev_prop_set_chr(dev, "chardev", serial_hd(i));
182 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
183
184 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
185 memory_region_add_subregion(&s->mr_ps, addrs[i], mr);
186
187 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]);
188 g_free(name);
189 }
190 }
191
192 static void versal_create_canfds(Versal *s, qemu_irq *pic)
193 {
194 int i;
195 uint32_t irqs[] = { VERSAL_CANFD0_IRQ_0, VERSAL_CANFD1_IRQ_0};
196 uint64_t addrs[] = { MM_CANFD0, MM_CANFD1 };
197
198 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.canfd); i++) {
199 char *name = g_strdup_printf("canfd%d", i);
200 SysBusDevice *sbd;
201 MemoryRegion *mr;
202
203 object_initialize_child(OBJECT(s), name, &s->lpd.iou.canfd[i],
204 TYPE_XILINX_CANFD);
205 sbd = SYS_BUS_DEVICE(&s->lpd.iou.canfd[i]);
206
207 object_property_set_int(OBJECT(&s->lpd.iou.canfd[i]), "ext_clk_freq",
208 XLNX_VERSAL_CANFD_REF_CLK , &error_abort);
209
210 object_property_set_link(OBJECT(&s->lpd.iou.canfd[i]), "canfdbus",
211 OBJECT(s->lpd.iou.canbus[i]),
212 &error_abort);
213
214 sysbus_realize(sbd, &error_fatal);
215
216 mr = sysbus_mmio_get_region(sbd, 0);
217 memory_region_add_subregion(&s->mr_ps, addrs[i], mr);
218
219 sysbus_connect_irq(sbd, 0, pic[irqs[i]]);
220 g_free(name);
221 }
222 }
223
224 static void versal_create_usbs(Versal *s, qemu_irq *pic)
225 {
226 DeviceState *dev;
227 MemoryRegion *mr;
228
229 object_initialize_child(OBJECT(s), "usb2", &s->lpd.iou.usb,
230 TYPE_XILINX_VERSAL_USB2);
231 dev = DEVICE(&s->lpd.iou.usb);
232
233 object_property_set_link(OBJECT(dev), "dma", OBJECT(&s->mr_ps),
234 &error_abort);
235 qdev_prop_set_uint32(dev, "intrs", 1);
236 qdev_prop_set_uint32(dev, "slots", 2);
237
238 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
239
240 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
241 memory_region_add_subregion(&s->mr_ps, MM_USB_0, mr);
242
243 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[VERSAL_USB0_IRQ_0]);
244
245 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
246 memory_region_add_subregion(&s->mr_ps, MM_USB2_CTRL_REGS, mr);
247 }
248
249 static void versal_create_gems(Versal *s, qemu_irq *pic)
250 {
251 int i;
252
253 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) {
254 static const int irqs[] = { VERSAL_GEM0_IRQ_0, VERSAL_GEM1_IRQ_0};
255 static const uint64_t addrs[] = { MM_GEM0, MM_GEM1 };
256 char *name = g_strdup_printf("gem%d", i);
257 NICInfo *nd = &nd_table[i];
258 DeviceState *dev;
259 MemoryRegion *mr;
260
261 object_initialize_child(OBJECT(s), name, &s->lpd.iou.gem[i],
262 TYPE_CADENCE_GEM);
263 dev = DEVICE(&s->lpd.iou.gem[i]);
264 /* FIXME use qdev NIC properties instead of nd_table[] */
265 if (nd->used) {
266 qemu_check_nic_model(nd, "cadence_gem");
267 qdev_set_nic_properties(dev, nd);
268 }
269 object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort);
270 object_property_set_int(OBJECT(dev), "num-priority-queues", 2,
271 &error_abort);
272 object_property_set_link(OBJECT(dev), "dma", OBJECT(&s->mr_ps),
273 &error_abort);
274 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
275
276 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
277 memory_region_add_subregion(&s->mr_ps, addrs[i], mr);
278
279 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]);
280 g_free(name);
281 }
282 }
283
284 static void versal_create_admas(Versal *s, qemu_irq *pic)
285 {
286 int i;
287
288 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) {
289 char *name = g_strdup_printf("adma%d", i);
290 DeviceState *dev;
291 MemoryRegion *mr;
292
293 object_initialize_child(OBJECT(s), name, &s->lpd.iou.adma[i],
294 TYPE_XLNX_ZDMA);
295 dev = DEVICE(&s->lpd.iou.adma[i]);
296 object_property_set_int(OBJECT(dev), "bus-width", 128, &error_abort);
297 object_property_set_link(OBJECT(dev), "dma",
298 OBJECT(get_system_memory()), &error_fatal);
299 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
300
301 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
302 memory_region_add_subregion(&s->mr_ps,
303 MM_ADMA_CH0 + i * MM_ADMA_CH0_SIZE, mr);
304
305 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[VERSAL_ADMA_IRQ_0 + i]);
306 g_free(name);
307 }
308 }
309
310 #define SDHCI_CAPABILITIES 0x280737ec6481 /* Same as on ZynqMP. */
311 static void versal_create_sds(Versal *s, qemu_irq *pic)
312 {
313 int i;
314
315 for (i = 0; i < ARRAY_SIZE(s->pmc.iou.sd); i++) {
316 DeviceState *dev;
317 MemoryRegion *mr;
318
319 object_initialize_child(OBJECT(s), "sd[*]", &s->pmc.iou.sd[i],
320 TYPE_SYSBUS_SDHCI);
321 dev = DEVICE(&s->pmc.iou.sd[i]);
322
323 object_property_set_uint(OBJECT(dev), "sd-spec-version", 3,
324 &error_fatal);
325 object_property_set_uint(OBJECT(dev), "capareg", SDHCI_CAPABILITIES,
326 &error_fatal);
327 object_property_set_uint(OBJECT(dev), "uhs", UHS_I, &error_fatal);
328 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
329
330 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
331 memory_region_add_subregion(&s->mr_ps,
332 MM_PMC_SD0 + i * MM_PMC_SD0_SIZE, mr);
333
334 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
335 pic[VERSAL_SD0_IRQ_0 + i * 2]);
336 }
337 }
338
339 static void versal_create_pmc_apb_irq_orgate(Versal *s, qemu_irq *pic)
340 {
341 DeviceState *orgate;
342
343 /*
344 * The VERSAL_PMC_APB_IRQ is an 'or' of the interrupts from the following
345 * models:
346 * - RTC
347 * - BBRAM
348 * - PMC SLCR
349 * - CFRAME regs (input 3 - 17 to the orgate)
350 */
351 object_initialize_child(OBJECT(s), "pmc-apb-irq-orgate",
352 &s->pmc.apb_irq_orgate, TYPE_OR_IRQ);
353 orgate = DEVICE(&s->pmc.apb_irq_orgate);
354 object_property_set_int(OBJECT(orgate),
355 "num-lines", VERSAL_NUM_PMC_APB_IRQS, &error_fatal);
356 qdev_realize(orgate, NULL, &error_fatal);
357 qdev_connect_gpio_out(orgate, 0, pic[VERSAL_PMC_APB_IRQ]);
358 }
359
360 static void versal_create_rtc(Versal *s, qemu_irq *pic)
361 {
362 SysBusDevice *sbd;
363 MemoryRegion *mr;
364
365 object_initialize_child(OBJECT(s), "rtc", &s->pmc.rtc,
366 TYPE_XLNX_ZYNQMP_RTC);
367 sbd = SYS_BUS_DEVICE(&s->pmc.rtc);
368 sysbus_realize(sbd, &error_fatal);
369
370 mr = sysbus_mmio_get_region(sbd, 0);
371 memory_region_add_subregion(&s->mr_ps, MM_PMC_RTC, mr);
372
373 /*
374 * TODO: Connect the ALARM and SECONDS interrupts once our RTC model
375 * supports them.
376 */
377 sysbus_connect_irq(sbd, 1,
378 qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 0));
379 }
380
381 static void versal_create_trng(Versal *s, qemu_irq *pic)
382 {
383 SysBusDevice *sbd;
384 MemoryRegion *mr;
385
386 object_initialize_child(OBJECT(s), "trng", &s->pmc.trng,
387 TYPE_XLNX_VERSAL_TRNG);
388 sbd = SYS_BUS_DEVICE(&s->pmc.trng);
389 sysbus_realize(sbd, &error_fatal);
390
391 mr = sysbus_mmio_get_region(sbd, 0);
392 memory_region_add_subregion(&s->mr_ps, MM_PMC_TRNG, mr);
393 sysbus_connect_irq(sbd, 0, pic[VERSAL_TRNG_IRQ]);
394 }
395
396 static void versal_create_xrams(Versal *s, qemu_irq *pic)
397 {
398 int nr_xrams = ARRAY_SIZE(s->lpd.xram.ctrl);
399 DeviceState *orgate;
400 int i;
401
402 /* XRAM IRQs get ORed into a single line. */
403 object_initialize_child(OBJECT(s), "xram-irq-orgate",
404 &s->lpd.xram.irq_orgate, TYPE_OR_IRQ);
405 orgate = DEVICE(&s->lpd.xram.irq_orgate);
406 object_property_set_int(OBJECT(orgate),
407 "num-lines", nr_xrams, &error_fatal);
408 qdev_realize(orgate, NULL, &error_fatal);
409 qdev_connect_gpio_out(orgate, 0, pic[VERSAL_XRAM_IRQ_0]);
410
411 for (i = 0; i < ARRAY_SIZE(s->lpd.xram.ctrl); i++) {
412 SysBusDevice *sbd;
413 MemoryRegion *mr;
414
415 object_initialize_child(OBJECT(s), "xram[*]", &s->lpd.xram.ctrl[i],
416 TYPE_XLNX_XRAM_CTRL);
417 sbd = SYS_BUS_DEVICE(&s->lpd.xram.ctrl[i]);
418 sysbus_realize(sbd, &error_fatal);
419
420 mr = sysbus_mmio_get_region(sbd, 0);
421 memory_region_add_subregion(&s->mr_ps,
422 MM_XRAMC + i * MM_XRAMC_SIZE, mr);
423 mr = sysbus_mmio_get_region(sbd, 1);
424 memory_region_add_subregion(&s->mr_ps, MM_XRAM + i * MiB, mr);
425
426 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(orgate, i));
427 }
428 }
429
430 static void versal_create_bbram(Versal *s, qemu_irq *pic)
431 {
432 SysBusDevice *sbd;
433
434 object_initialize_child_with_props(OBJECT(s), "bbram", &s->pmc.bbram,
435 sizeof(s->pmc.bbram), TYPE_XLNX_BBRAM,
436 &error_fatal,
437 "crc-zpads", "0",
438 NULL);
439 sbd = SYS_BUS_DEVICE(&s->pmc.bbram);
440
441 sysbus_realize(sbd, &error_fatal);
442 memory_region_add_subregion(&s->mr_ps, MM_PMC_BBRAM_CTRL,
443 sysbus_mmio_get_region(sbd, 0));
444 sysbus_connect_irq(sbd, 0,
445 qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 1));
446 }
447
448 static void versal_realize_efuse_part(Versal *s, Object *dev, hwaddr base)
449 {
450 SysBusDevice *part = SYS_BUS_DEVICE(dev);
451
452 object_property_set_link(OBJECT(part), "efuse",
453 OBJECT(&s->pmc.efuse), &error_abort);
454
455 sysbus_realize(part, &error_abort);
456 memory_region_add_subregion(&s->mr_ps, base,
457 sysbus_mmio_get_region(part, 0));
458 }
459
460 static void versal_create_efuse(Versal *s, qemu_irq *pic)
461 {
462 Object *bits = OBJECT(&s->pmc.efuse);
463 Object *ctrl = OBJECT(&s->pmc.efuse_ctrl);
464 Object *cache = OBJECT(&s->pmc.efuse_cache);
465
466 object_initialize_child(OBJECT(s), "efuse-ctrl", &s->pmc.efuse_ctrl,
467 TYPE_XLNX_VERSAL_EFUSE_CTRL);
468
469 object_initialize_child(OBJECT(s), "efuse-cache", &s->pmc.efuse_cache,
470 TYPE_XLNX_VERSAL_EFUSE_CACHE);
471
472 object_initialize_child_with_props(ctrl, "xlnx-efuse@0", bits,
473 sizeof(s->pmc.efuse),
474 TYPE_XLNX_EFUSE, &error_abort,
475 "efuse-nr", "3",
476 "efuse-size", "8192",
477 NULL);
478
479 qdev_realize(DEVICE(bits), NULL, &error_abort);
480 versal_realize_efuse_part(s, ctrl, MM_PMC_EFUSE_CTRL);
481 versal_realize_efuse_part(s, cache, MM_PMC_EFUSE_CACHE);
482
483 sysbus_connect_irq(SYS_BUS_DEVICE(ctrl), 0, pic[VERSAL_EFUSE_IRQ]);
484 }
485
486 static void versal_create_pmc_iou_slcr(Versal *s, qemu_irq *pic)
487 {
488 SysBusDevice *sbd;
489
490 object_initialize_child(OBJECT(s), "versal-pmc-iou-slcr", &s->pmc.iou.slcr,
491 TYPE_XILINX_VERSAL_PMC_IOU_SLCR);
492
493 sbd = SYS_BUS_DEVICE(&s->pmc.iou.slcr);
494 sysbus_realize(sbd, &error_fatal);
495
496 memory_region_add_subregion(&s->mr_ps, MM_PMC_PMC_IOU_SLCR,
497 sysbus_mmio_get_region(sbd, 0));
498
499 sysbus_connect_irq(sbd, 0,
500 qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 2));
501 }
502
503 static void versal_create_ospi(Versal *s, qemu_irq *pic)
504 {
505 SysBusDevice *sbd;
506 MemoryRegion *mr_dac;
507 qemu_irq ospi_mux_sel;
508 DeviceState *orgate;
509
510 memory_region_init(&s->pmc.iou.ospi.linear_mr, OBJECT(s),
511 "versal-ospi-linear-mr" , MM_PMC_OSPI_DAC_SIZE);
512
513 object_initialize_child(OBJECT(s), "versal-ospi", &s->pmc.iou.ospi.ospi,
514 TYPE_XILINX_VERSAL_OSPI);
515
516 mr_dac = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->pmc.iou.ospi.ospi), 1);
517 memory_region_add_subregion(&s->pmc.iou.ospi.linear_mr, 0x0, mr_dac);
518
519 /* Create the OSPI destination DMA */
520 object_initialize_child(OBJECT(s), "versal-ospi-dma-dst",
521 &s->pmc.iou.ospi.dma_dst,
522 TYPE_XLNX_CSU_DMA);
523
524 object_property_set_link(OBJECT(&s->pmc.iou.ospi.dma_dst),
525 "dma", OBJECT(get_system_memory()),
526 &error_abort);
527
528 sbd = SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_dst);
529 sysbus_realize(sbd, &error_fatal);
530
531 memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI_DMA_DST,
532 sysbus_mmio_get_region(sbd, 0));
533
534 /* Create the OSPI source DMA */
535 object_initialize_child(OBJECT(s), "versal-ospi-dma-src",
536 &s->pmc.iou.ospi.dma_src,
537 TYPE_XLNX_CSU_DMA);
538
539 object_property_set_bool(OBJECT(&s->pmc.iou.ospi.dma_src), "is-dst",
540 false, &error_abort);
541
542 object_property_set_link(OBJECT(&s->pmc.iou.ospi.dma_src),
543 "dma", OBJECT(mr_dac), &error_abort);
544
545 object_property_set_link(OBJECT(&s->pmc.iou.ospi.dma_src),
546 "stream-connected-dma",
547 OBJECT(&s->pmc.iou.ospi.dma_dst),
548 &error_abort);
549
550 sbd = SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_src);
551 sysbus_realize(sbd, &error_fatal);
552
553 memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI_DMA_SRC,
554 sysbus_mmio_get_region(sbd, 0));
555
556 /* Realize the OSPI */
557 object_property_set_link(OBJECT(&s->pmc.iou.ospi.ospi), "dma-src",
558 OBJECT(&s->pmc.iou.ospi.dma_src), &error_abort);
559
560 sbd = SYS_BUS_DEVICE(&s->pmc.iou.ospi.ospi);
561 sysbus_realize(sbd, &error_fatal);
562
563 memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI,
564 sysbus_mmio_get_region(sbd, 0));
565
566 memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI_DAC,
567 &s->pmc.iou.ospi.linear_mr);
568
569 /* ospi_mux_sel */
570 ospi_mux_sel = qdev_get_gpio_in_named(DEVICE(&s->pmc.iou.ospi.ospi),
571 "ospi-mux-sel", 0);
572 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), "ospi-mux-sel", 0,
573 ospi_mux_sel);
574
575 /* OSPI irq */
576 object_initialize_child(OBJECT(s), "ospi-irq-orgate",
577 &s->pmc.iou.ospi.irq_orgate, TYPE_OR_IRQ);
578 object_property_set_int(OBJECT(&s->pmc.iou.ospi.irq_orgate),
579 "num-lines", NUM_OSPI_IRQ_LINES, &error_fatal);
580
581 orgate = DEVICE(&s->pmc.iou.ospi.irq_orgate);
582 qdev_realize(orgate, NULL, &error_fatal);
583
584 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pmc.iou.ospi.ospi), 0,
585 qdev_get_gpio_in(orgate, 0));
586 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_src), 0,
587 qdev_get_gpio_in(orgate, 1));
588 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_dst), 0,
589 qdev_get_gpio_in(orgate, 2));
590
591 qdev_connect_gpio_out(orgate, 0, pic[VERSAL_OSPI_IRQ]);
592 }
593
594 static void versal_create_cfu(Versal *s, qemu_irq *pic)
595 {
596 SysBusDevice *sbd;
597 DeviceState *dev;
598 int i;
599 const struct {
600 uint64_t reg_base;
601 uint64_t fdri_base;
602 } cframe_addr[] = {
603 { MM_PMC_CFRAME0_REG, MM_PMC_CFRAME0_FDRI },
604 { MM_PMC_CFRAME1_REG, MM_PMC_CFRAME1_FDRI },
605 { MM_PMC_CFRAME2_REG, MM_PMC_CFRAME2_FDRI },
606 { MM_PMC_CFRAME3_REG, MM_PMC_CFRAME3_FDRI },
607 { MM_PMC_CFRAME4_REG, MM_PMC_CFRAME4_FDRI },
608 { MM_PMC_CFRAME5_REG, MM_PMC_CFRAME5_FDRI },
609 { MM_PMC_CFRAME6_REG, MM_PMC_CFRAME6_FDRI },
610 { MM_PMC_CFRAME7_REG, MM_PMC_CFRAME7_FDRI },
611 { MM_PMC_CFRAME8_REG, MM_PMC_CFRAME8_FDRI },
612 { MM_PMC_CFRAME9_REG, MM_PMC_CFRAME9_FDRI },
613 { MM_PMC_CFRAME10_REG, MM_PMC_CFRAME10_FDRI },
614 { MM_PMC_CFRAME11_REG, MM_PMC_CFRAME11_FDRI },
615 { MM_PMC_CFRAME12_REG, MM_PMC_CFRAME12_FDRI },
616 { MM_PMC_CFRAME13_REG, MM_PMC_CFRAME13_FDRI },
617 { MM_PMC_CFRAME14_REG, MM_PMC_CFRAME14_FDRI },
618 };
619 const struct {
620 uint32_t blktype0_frames;
621 uint32_t blktype1_frames;
622 uint32_t blktype2_frames;
623 uint32_t blktype3_frames;
624 uint32_t blktype4_frames;
625 uint32_t blktype5_frames;
626 uint32_t blktype6_frames;
627 } cframe_cfg[] = {
628 [0] = { 34111, 3528, 12800, 11, 5, 1, 1 },
629 [1] = { 38498, 3841, 15361, 13, 7, 3, 1 },
630 [2] = { 38498, 3841, 15361, 13, 7, 3, 1 },
631 [3] = { 38498, 3841, 15361, 13, 7, 3, 1 },
632 };
633
634 /* CFU FDRO */
635 object_initialize_child(OBJECT(s), "cfu-fdro", &s->pmc.cfu_fdro,
636 TYPE_XLNX_VERSAL_CFU_FDRO);
637 sbd = SYS_BUS_DEVICE(&s->pmc.cfu_fdro);
638
639 sysbus_realize(sbd, &error_fatal);
640 memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_FDRO,
641 sysbus_mmio_get_region(sbd, 0));
642
643 /* CFRAME REG */
644 for (i = 0; i < ARRAY_SIZE(s->pmc.cframe); i++) {
645 g_autofree char *name = g_strdup_printf("cframe%d", i);
646
647 object_initialize_child(OBJECT(s), name, &s->pmc.cframe[i],
648 TYPE_XLNX_VERSAL_CFRAME_REG);
649
650 sbd = SYS_BUS_DEVICE(&s->pmc.cframe[i]);
651 dev = DEVICE(&s->pmc.cframe[i]);
652
653 if (i < ARRAY_SIZE(cframe_cfg)) {
654 object_property_set_int(OBJECT(dev), "blktype0-frames",
655 cframe_cfg[i].blktype0_frames,
656 &error_abort);
657 object_property_set_int(OBJECT(dev), "blktype1-frames",
658 cframe_cfg[i].blktype1_frames,
659 &error_abort);
660 object_property_set_int(OBJECT(dev), "blktype2-frames",
661 cframe_cfg[i].blktype2_frames,
662 &error_abort);
663 object_property_set_int(OBJECT(dev), "blktype3-frames",
664 cframe_cfg[i].blktype3_frames,
665 &error_abort);
666 object_property_set_int(OBJECT(dev), "blktype4-frames",
667 cframe_cfg[i].blktype4_frames,
668 &error_abort);
669 object_property_set_int(OBJECT(dev), "blktype5-frames",
670 cframe_cfg[i].blktype5_frames,
671 &error_abort);
672 object_property_set_int(OBJECT(dev), "blktype6-frames",
673 cframe_cfg[i].blktype6_frames,
674 &error_abort);
675 }
676 object_property_set_link(OBJECT(dev), "cfu-fdro",
677 OBJECT(&s->pmc.cfu_fdro), &error_fatal);
678
679 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
680
681 memory_region_add_subregion(&s->mr_ps, cframe_addr[i].reg_base,
682 sysbus_mmio_get_region(sbd, 0));
683 memory_region_add_subregion(&s->mr_ps, cframe_addr[i].fdri_base,
684 sysbus_mmio_get_region(sbd, 1));
685 sysbus_connect_irq(sbd, 0,
686 qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate),
687 3 + i));
688 }
689
690 /* CFRAME BCAST */
691 object_initialize_child(OBJECT(s), "cframe_bcast", &s->pmc.cframe_bcast,
692 TYPE_XLNX_VERSAL_CFRAME_BCAST_REG);
693
694 sbd = SYS_BUS_DEVICE(&s->pmc.cframe_bcast);
695 dev = DEVICE(&s->pmc.cframe_bcast);
696
697 for (i = 0; i < ARRAY_SIZE(s->pmc.cframe); i++) {
698 g_autofree char *propname = g_strdup_printf("cframe%d", i);
699 object_property_set_link(OBJECT(dev), propname,
700 OBJECT(&s->pmc.cframe[i]), &error_fatal);
701 }
702
703 sysbus_realize(sbd, &error_fatal);
704
705 memory_region_add_subregion(&s->mr_ps, MM_PMC_CFRAME_BCAST_REG,
706 sysbus_mmio_get_region(sbd, 0));
707 memory_region_add_subregion(&s->mr_ps, MM_PMC_CFRAME_BCAST_FDRI,
708 sysbus_mmio_get_region(sbd, 1));
709
710 /* CFU APB */
711 object_initialize_child(OBJECT(s), "cfu-apb", &s->pmc.cfu_apb,
712 TYPE_XLNX_VERSAL_CFU_APB);
713 sbd = SYS_BUS_DEVICE(&s->pmc.cfu_apb);
714 dev = DEVICE(&s->pmc.cfu_apb);
715
716 for (i = 0; i < ARRAY_SIZE(s->pmc.cframe); i++) {
717 g_autofree char *propname = g_strdup_printf("cframe%d", i);
718 object_property_set_link(OBJECT(dev), propname,
719 OBJECT(&s->pmc.cframe[i]), &error_fatal);
720 }
721
722 sysbus_realize(sbd, &error_fatal);
723 memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_APB,
724 sysbus_mmio_get_region(sbd, 0));
725 memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_STREAM,
726 sysbus_mmio_get_region(sbd, 1));
727 memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_STREAM_2,
728 sysbus_mmio_get_region(sbd, 2));
729 sysbus_connect_irq(sbd, 0, pic[VERSAL_CFU_IRQ_0]);
730
731 /* CFU SFR */
732 object_initialize_child(OBJECT(s), "cfu-sfr", &s->pmc.cfu_sfr,
733 TYPE_XLNX_VERSAL_CFU_SFR);
734
735 sbd = SYS_BUS_DEVICE(&s->pmc.cfu_sfr);
736
737 object_property_set_link(OBJECT(&s->pmc.cfu_sfr),
738 "cfu", OBJECT(&s->pmc.cfu_apb), &error_abort);
739
740 sysbus_realize(sbd, &error_fatal);
741 memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_SFR,
742 sysbus_mmio_get_region(sbd, 0));
743 }
744
745 static void versal_create_crl(Versal *s, qemu_irq *pic)
746 {
747 SysBusDevice *sbd;
748 int i;
749
750 object_initialize_child(OBJECT(s), "crl", &s->lpd.crl,
751 TYPE_XLNX_VERSAL_CRL);
752 sbd = SYS_BUS_DEVICE(&s->lpd.crl);
753
754 for (i = 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) {
755 g_autofree gchar *name = g_strdup_printf("cpu_r5[%d]", i);
756
757 object_property_set_link(OBJECT(&s->lpd.crl),
758 name, OBJECT(&s->lpd.rpu.cpu[i]),
759 &error_abort);
760 }
761
762 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) {
763 g_autofree gchar *name = g_strdup_printf("gem[%d]", i);
764
765 object_property_set_link(OBJECT(&s->lpd.crl),
766 name, OBJECT(&s->lpd.iou.gem[i]),
767 &error_abort);
768 }
769
770 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) {
771 g_autofree gchar *name = g_strdup_printf("adma[%d]", i);
772
773 object_property_set_link(OBJECT(&s->lpd.crl),
774 name, OBJECT(&s->lpd.iou.adma[i]),
775 &error_abort);
776 }
777
778 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) {
779 g_autofree gchar *name = g_strdup_printf("uart[%d]", i);
780
781 object_property_set_link(OBJECT(&s->lpd.crl),
782 name, OBJECT(&s->lpd.iou.uart[i]),
783 &error_abort);
784 }
785
786 object_property_set_link(OBJECT(&s->lpd.crl),
787 "usb", OBJECT(&s->lpd.iou.usb),
788 &error_abort);
789
790 sysbus_realize(sbd, &error_fatal);
791 memory_region_add_subregion(&s->mr_ps, MM_CRL,
792 sysbus_mmio_get_region(sbd, 0));
793 sysbus_connect_irq(sbd, 0, pic[VERSAL_CRL_IRQ]);
794 }
795
796 /* This takes the board allocated linear DDR memory and creates aliases
797 * for each split DDR range/aperture on the Versal address map.
798 */
799 static void versal_map_ddr(Versal *s)
800 {
801 uint64_t size = memory_region_size(s->cfg.mr_ddr);
802 /* Describes the various split DDR access regions. */
803 static const struct {
804 uint64_t base;
805 uint64_t size;
806 } addr_ranges[] = {
807 { MM_TOP_DDR, MM_TOP_DDR_SIZE },
808 { MM_TOP_DDR_2, MM_TOP_DDR_2_SIZE },
809 { MM_TOP_DDR_3, MM_TOP_DDR_3_SIZE },
810 { MM_TOP_DDR_4, MM_TOP_DDR_4_SIZE }
811 };
812 uint64_t offset = 0;
813 int i;
814
815 assert(ARRAY_SIZE(addr_ranges) == ARRAY_SIZE(s->noc.mr_ddr_ranges));
816 for (i = 0; i < ARRAY_SIZE(addr_ranges) && size; i++) {
817 char *name;
818 uint64_t mapsize;
819
820 mapsize = size < addr_ranges[i].size ? size : addr_ranges[i].size;
821 name = g_strdup_printf("noc-ddr-range%d", i);
822 /* Create the MR alias. */
823 memory_region_init_alias(&s->noc.mr_ddr_ranges[i], OBJECT(s),
824 name, s->cfg.mr_ddr,
825 offset, mapsize);
826
827 /* Map it onto the NoC MR. */
828 memory_region_add_subregion(&s->mr_ps, addr_ranges[i].base,
829 &s->noc.mr_ddr_ranges[i]);
830 offset += mapsize;
831 size -= mapsize;
832 g_free(name);
833 }
834 }
835
836 static void versal_unimp_area(Versal *s, const char *name,
837 MemoryRegion *mr,
838 hwaddr base, hwaddr size)
839 {
840 DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
841 MemoryRegion *mr_dev;
842
843 qdev_prop_set_string(dev, "name", name);
844 qdev_prop_set_uint64(dev, "size", size);
845 object_property_add_child(OBJECT(s), name, OBJECT(dev));
846 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
847
848 mr_dev = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
849 memory_region_add_subregion(mr, base, mr_dev);
850 }
851
852 static void versal_unimp_sd_emmc_sel(void *opaque, int n, int level)
853 {
854 qemu_log_mask(LOG_UNIMP,
855 "Selecting between enabling SD mode or eMMC mode on "
856 "controller %d is not yet implemented\n", n);
857 }
858
859 static void versal_unimp_qspi_ospi_mux_sel(void *opaque, int n, int level)
860 {
861 qemu_log_mask(LOG_UNIMP,
862 "Selecting between enabling the QSPI or OSPI linear address "
863 "region is not yet implemented\n");
864 }
865
866 static void versal_unimp_irq_parity_imr(void *opaque, int n, int level)
867 {
868 qemu_log_mask(LOG_UNIMP,
869 "PMC SLCR parity interrupt behaviour "
870 "is not yet implemented\n");
871 }
872
873 static void versal_unimp(Versal *s)
874 {
875 qemu_irq gpio_in;
876
877 versal_unimp_area(s, "psm", &s->mr_ps,
878 MM_PSM_START, MM_PSM_END - MM_PSM_START);
879 versal_unimp_area(s, "crf", &s->mr_ps,
880 MM_FPD_CRF, MM_FPD_CRF_SIZE);
881 versal_unimp_area(s, "apu", &s->mr_ps,
882 MM_FPD_FPD_APU, MM_FPD_FPD_APU_SIZE);
883 versal_unimp_area(s, "crp", &s->mr_ps,
884 MM_PMC_CRP, MM_PMC_CRP_SIZE);
885 versal_unimp_area(s, "iou-scntr", &s->mr_ps,
886 MM_IOU_SCNTR, MM_IOU_SCNTR_SIZE);
887 versal_unimp_area(s, "iou-scntr-seucre", &s->mr_ps,
888 MM_IOU_SCNTRS, MM_IOU_SCNTRS_SIZE);
889
890 qdev_init_gpio_in_named(DEVICE(s), versal_unimp_sd_emmc_sel,
891 "sd-emmc-sel-dummy", 2);
892 qdev_init_gpio_in_named(DEVICE(s), versal_unimp_qspi_ospi_mux_sel,
893 "qspi-ospi-mux-sel-dummy", 1);
894 qdev_init_gpio_in_named(DEVICE(s), versal_unimp_irq_parity_imr,
895 "irq-parity-imr-dummy", 1);
896
897 gpio_in = qdev_get_gpio_in_named(DEVICE(s), "sd-emmc-sel-dummy", 0);
898 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), "sd-emmc-sel", 0,
899 gpio_in);
900
901 gpio_in = qdev_get_gpio_in_named(DEVICE(s), "sd-emmc-sel-dummy", 1);
902 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), "sd-emmc-sel", 1,
903 gpio_in);
904
905 gpio_in = qdev_get_gpio_in_named(DEVICE(s), "qspi-ospi-mux-sel-dummy", 0);
906 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr),
907 "qspi-ospi-mux-sel", 0,
908 gpio_in);
909
910 gpio_in = qdev_get_gpio_in_named(DEVICE(s), "irq-parity-imr-dummy", 0);
911 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr),
912 SYSBUS_DEVICE_GPIO_IRQ, 0,
913 gpio_in);
914 }
915
916 static void versal_realize(DeviceState *dev, Error **errp)
917 {
918 Versal *s = XLNX_VERSAL(dev);
919 qemu_irq pic[XLNX_VERSAL_NR_IRQS];
920
921 versal_create_apu_cpus(s);
922 versal_create_apu_gic(s, pic);
923 versal_create_rpu_cpus(s);
924 versal_create_uarts(s, pic);
925 versal_create_canfds(s, pic);
926 versal_create_usbs(s, pic);
927 versal_create_gems(s, pic);
928 versal_create_admas(s, pic);
929 versal_create_sds(s, pic);
930 versal_create_pmc_apb_irq_orgate(s, pic);
931 versal_create_rtc(s, pic);
932 versal_create_trng(s, pic);
933 versal_create_xrams(s, pic);
934 versal_create_bbram(s, pic);
935 versal_create_efuse(s, pic);
936 versal_create_pmc_iou_slcr(s, pic);
937 versal_create_ospi(s, pic);
938 versal_create_crl(s, pic);
939 versal_create_cfu(s, pic);
940 versal_map_ddr(s);
941 versal_unimp(s);
942
943 /* Create the On Chip Memory (OCM). */
944 memory_region_init_ram(&s->lpd.mr_ocm, OBJECT(s), "ocm",
945 MM_OCM_SIZE, &error_fatal);
946
947 memory_region_add_subregion_overlap(&s->mr_ps, MM_OCM, &s->lpd.mr_ocm, 0);
948 memory_region_add_subregion_overlap(&s->fpd.apu.mr, 0, &s->mr_ps, 0);
949 memory_region_add_subregion_overlap(&s->lpd.rpu.mr, 0,
950 &s->lpd.rpu.mr_ps_alias, 0);
951 }
952
953 static void versal_init(Object *obj)
954 {
955 Versal *s = XLNX_VERSAL(obj);
956
957 memory_region_init(&s->fpd.apu.mr, obj, "mr-apu", UINT64_MAX);
958 memory_region_init(&s->lpd.rpu.mr, obj, "mr-rpu", UINT64_MAX);
959 memory_region_init(&s->mr_ps, obj, "mr-ps-switch", UINT64_MAX);
960 memory_region_init_alias(&s->lpd.rpu.mr_ps_alias, OBJECT(s),
961 "mr-rpu-ps-alias", &s->mr_ps, 0, UINT64_MAX);
962 }
963
964 static Property versal_properties[] = {
965 DEFINE_PROP_LINK("ddr", Versal, cfg.mr_ddr, TYPE_MEMORY_REGION,
966 MemoryRegion *),
967 DEFINE_PROP_LINK("canbus0", Versal, lpd.iou.canbus[0],
968 TYPE_CAN_BUS, CanBusState *),
969 DEFINE_PROP_LINK("canbus1", Versal, lpd.iou.canbus[1],
970 TYPE_CAN_BUS, CanBusState *),
971 DEFINE_PROP_END_OF_LIST()
972 };
973
974 static void versal_class_init(ObjectClass *klass, void *data)
975 {
976 DeviceClass *dc = DEVICE_CLASS(klass);
977
978 dc->realize = versal_realize;
979 device_class_set_props(dc, versal_properties);
980 /* No VMSD since we haven't got any top-level SoC state to save. */
981 }
982
983 static const TypeInfo versal_info = {
984 .name = TYPE_XLNX_VERSAL,
985 .parent = TYPE_SYS_BUS_DEVICE,
986 .instance_size = sizeof(Versal),
987 .instance_init = versal_init,
988 .class_init = versal_class_init,
989 };
990
991 static void versal_register_types(void)
992 {
993 type_register_static(&versal_info);
994 }
995
996 type_init(versal_register_types);
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