disas/libvixl/a64/cpu-a64.h

   1 // Copyright 2013, ARM Limited
   2 // All rights reserved.
   3 //
   4 // Redistribution and use in source and binary forms, with or without
   5 // modification, are permitted provided that the following conditions are met:
   6 //
   7 //   * Redistributions of source code must retain the above copyright notice,
   8 //     this list of conditions and the following disclaimer.
   9 //   * Redistributions in binary form must reproduce the above copyright notice,
  10 //     this list of conditions and the following disclaimer in the documentation
  11 //     and/or other materials provided with the distribution.
  12 //   * Neither the name of ARM Limited nor the names of its contributors may be
  13 //     used to endorse or promote products derived from this software without
  14 //     specific prior written permission.
  15 //
  16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
  17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
  20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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  25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26
  27 #ifndef VIXL_CPU_A64_H
  28 #define VIXL_CPU_A64_H
  29
  30 #include "globals.h"
  31
  32 namespace vixl {
  33
  34 class CPU {
  35  public:
  36   // Initialise CPU support.
  37   static void SetUp();
  38
  39   // Ensures the data at a given address and with a given size is the same for
  40   // the I and D caches. I and D caches are not automatically coherent on ARM
  41   // so this operation is required before any dynamically generated code can
  42   // safely run.
  43   static void EnsureIAndDCacheCoherency(void *address, size_t length);
  44
  45  private:
  46   // Return the content of the cache type register.
  47   static uint32_t GetCacheType();
  48
  49   // I and D cache line size in bytes.
  50   static unsigned icache_line_size_;
  51   static unsigned dcache_line_size_;
  52 };
  53
  54 }  // namespace vixl
  55
  56 #endif  // VIXL_CPU_A64_H