cpu-common.h

   1 #ifndef CPU_COMMON_H
   2 #define CPU_COMMON_H 1
   3
   4 /* CPU interfaces that are target indpendent.  */
   5
   6 #if defined(__arm__) || defined(__sparc__) || defined(__mips__) || defined(__hppa__) || defined(__ia64__)
   7 #define WORDS_ALIGNED
   8 #endif
   9
  10 #ifdef TARGET_PHYS_ADDR_BITS
  11 #include "targphys.h"
  12 #endif
  13
  14 #ifndef NEED_CPU_H
  15 #include "poison.h"
  16 #endif
  17
  18 #include "bswap.h"
  19 #include "qemu-queue.h"
  20
  21 #if !defined(CONFIG_USER_ONLY)
  22
  23 /* address in the RAM (different from a physical address) */
  24 typedef unsigned long ram_addr_t;
  25
  26 /* memory API */
  27
  28 typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
  29 typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
  30
  31 void cpu_register_physical_memory_offset(target_phys_addr_t start_addr,
  32                                          ram_addr_t size,
  33                                          ram_addr_t phys_offset,
  34                                          ram_addr_t region_offset);
  35 static inline void cpu_register_physical_memory(target_phys_addr_t start_addr,
  36                                                 ram_addr_t size,
  37                                                 ram_addr_t phys_offset)
  38 {
  39     cpu_register_physical_memory_offset(start_addr, size, phys_offset, 0);
  40 }
  41
  42 ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr);
  43 ram_addr_t qemu_ram_alloc(DeviceState *dev, const char *name, ram_addr_t size);
  44 void qemu_ram_free(ram_addr_t addr);
  45 /* This should only be used for ram local to a device.  */
  46 void *qemu_get_ram_ptr(ram_addr_t addr);
  47 /* This should not be used by devices.  */
  48 ram_addr_t qemu_ram_addr_from_host(void *ptr);
  49
  50 int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read,
  51                            CPUWriteMemoryFunc * const *mem_write,
  52                            void *opaque);
  53 void cpu_unregister_io_memory(int table_address);
  54
  55 void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
  56                             int len, int is_write);
  57 static inline void cpu_physical_memory_read(target_phys_addr_t addr,
  58                                             uint8_t *buf, int len)
  59 {
  60     cpu_physical_memory_rw(addr, buf, len, 0);
  61 }
  62 static inline void cpu_physical_memory_write(target_phys_addr_t addr,
  63                                              const uint8_t *buf, int len)
  64 {
  65     cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1);
  66 }
  67 void *cpu_physical_memory_map(target_phys_addr_t addr,
  68                               target_phys_addr_t *plen,
  69                               int is_write);
  70 void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
  71                                int is_write, target_phys_addr_t access_len);
  72 void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque));
  73 void cpu_unregister_map_client(void *cookie);
  74
  75 struct CPUPhysMemoryClient;
  76 typedef struct CPUPhysMemoryClient CPUPhysMemoryClient;
  77 struct CPUPhysMemoryClient {
  78     void (*set_memory)(struct CPUPhysMemoryClient *client,
  79                        target_phys_addr_t start_addr,
  80                        ram_addr_t size,
  81                        ram_addr_t phys_offset);
  82     int (*sync_dirty_bitmap)(struct CPUPhysMemoryClient *client,
  83                              target_phys_addr_t start_addr,
  84                              target_phys_addr_t end_addr);
  85     int (*migration_log)(struct CPUPhysMemoryClient *client,
  86                          int enable);
  87     QLIST_ENTRY(CPUPhysMemoryClient) list;
  88 };
  89
  90 void cpu_register_phys_memory_client(CPUPhysMemoryClient *);
  91 void cpu_unregister_phys_memory_client(CPUPhysMemoryClient *);
  92
  93 /* Coalesced MMIO regions are areas where write operations can be reordered.
  94  * This usually implies that write operations are side-effect free.  This allows
  95  * batching which can make a major impact on performance when using
  96  * virtualization.
  97  */
  98 void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
  99
 100 void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
 101
 102 void qemu_flush_coalesced_mmio_buffer(void);
 103
 104 uint32_t ldub_phys(target_phys_addr_t addr);
 105 uint32_t lduw_phys(target_phys_addr_t addr);
 106 uint32_t ldl_phys(target_phys_addr_t addr);
 107 uint64_t ldq_phys(target_phys_addr_t addr);
 108 void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
 109 void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val);
 110 void stb_phys(target_phys_addr_t addr, uint32_t val);
 111 void stw_phys(target_phys_addr_t addr, uint32_t val);
 112 void stl_phys(target_phys_addr_t addr, uint32_t val);
 113 void stq_phys(target_phys_addr_t addr, uint64_t val);
 114
 115 void cpu_physical_memory_write_rom(target_phys_addr_t addr,
 116                                    const uint8_t *buf, int len);
 117
 118 #define IO_MEM_SHIFT       3
 119
 120 #define IO_MEM_RAM         (0 << IO_MEM_SHIFT) /* hardcoded offset */
 121 #define IO_MEM_ROM         (1 << IO_MEM_SHIFT) /* hardcoded offset */
 122 #define IO_MEM_UNASSIGNED  (2 << IO_MEM_SHIFT)
 123 #define IO_MEM_NOTDIRTY    (3 << IO_MEM_SHIFT)
 124
 125 /* Acts like a ROM when read and like a device when written.  */
 126 #define IO_MEM_ROMD        (1)
 127 #define IO_MEM_SUBPAGE     (2)
 128
 129 #endif
 130
 131 #endif /* !CPU_COMMON_H */