2 * Alpha emulation cpu definitions for qemu.
4 * Copyright (c) 2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu-common.h"
26 #define TARGET_LONG_BITS 64
29 #define CPUArchState struct CPUAlphaState
31 #include "exec/cpu-defs.h"
33 #include "fpu/softfloat.h"
35 #define ICACHE_LINE_SIZE 32
36 #define DCACHE_LINE_SIZE 32
38 #define TARGET_PAGE_BITS 13
40 #ifdef CONFIG_USER_ONLY
41 /* ??? The kernel likes to give addresses in high memory. If the host has
42 more virtual address space than the guest, this can lead to impossible
43 allocations. Honor the long-standing assumption that only kernel addrs
44 are negative, but otherwise allow allocations anywhere. This could lead
45 to tricky emulation problems for programs doing tagged addressing, but
46 that's far fewer than encounter the impossible allocation problem. */
47 #define TARGET_PHYS_ADDR_SPACE_BITS 63
48 #define TARGET_VIRT_ADDR_SPACE_BITS 63
50 /* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44. */
51 #define TARGET_PHYS_ADDR_SPACE_BITS 44
52 #define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS)
55 /* Alpha major type */
61 ALPHA_EV5
= 5, /* 21164 */
62 ALPHA_EV45
= 6, /* 21064A */
63 ALPHA_EV56
= 7, /* 21164A */
74 ALPHA_LCA_1
= 1, /* 21066 */
75 ALPHA_LCA_2
= 2, /* 20166 */
76 ALPHA_LCA_3
= 3, /* 21068 */
77 ALPHA_LCA_4
= 4, /* 21068 */
78 ALPHA_LCA_5
= 5, /* 21066A */
79 ALPHA_LCA_6
= 6, /* 21068A */
84 ALPHA_EV5_1
= 1, /* Rev BA, CA */
85 ALPHA_EV5_2
= 2, /* Rev DA, EA */
86 ALPHA_EV5_3
= 3, /* Pass 3 */
87 ALPHA_EV5_4
= 4, /* Pass 3.2 */
88 ALPHA_EV5_5
= 5, /* Pass 4 */
93 ALPHA_EV45_1
= 1, /* Pass 1 */
94 ALPHA_EV45_2
= 2, /* Pass 1.1 */
95 ALPHA_EV45_3
= 3, /* Pass 2 */
100 ALPHA_EV56_1
= 1, /* Pass 1 */
101 ALPHA_EV56_2
= 2, /* Pass 2 */
105 IMPLVER_2106x
= 0, /* EV4, EV45 & LCA45 */
106 IMPLVER_21164
= 1, /* EV5, EV56 & PCA45 */
107 IMPLVER_21264
= 2, /* EV6, EV67 & EV68x */
108 IMPLVER_21364
= 3, /* EV7 & EV79 */
112 AMASK_BWX
= 0x00000001,
113 AMASK_FIX
= 0x00000002,
114 AMASK_CIX
= 0x00000004,
115 AMASK_MVI
= 0x00000100,
116 AMASK_TRAP
= 0x00000200,
117 AMASK_PREFETCH
= 0x00001000,
121 VAX_ROUND_NORMAL
= 0,
126 IEEE_ROUND_NORMAL
= 0,
133 /* IEEE floating-point operations encoding */
145 FP_ROUND_CHOPPED
= 0x0,
146 FP_ROUND_MINUS
= 0x1,
147 FP_ROUND_NORMAL
= 0x2,
148 FP_ROUND_DYNAMIC
= 0x3,
151 /* FPCR bits -- right-shifted 32 so we can use a uint32_t. */
152 #define FPCR_SUM (1U << (63 - 32))
153 #define FPCR_INED (1U << (62 - 32))
154 #define FPCR_UNFD (1U << (61 - 32))
155 #define FPCR_UNDZ (1U << (60 - 32))
156 #define FPCR_DYN_SHIFT (58 - 32)
157 #define FPCR_DYN_CHOPPED (0U << FPCR_DYN_SHIFT)
158 #define FPCR_DYN_MINUS (1U << FPCR_DYN_SHIFT)
159 #define FPCR_DYN_NORMAL (2U << FPCR_DYN_SHIFT)
160 #define FPCR_DYN_PLUS (3U << FPCR_DYN_SHIFT)
161 #define FPCR_DYN_MASK (3U << FPCR_DYN_SHIFT)
162 #define FPCR_IOV (1U << (57 - 32))
163 #define FPCR_INE (1U << (56 - 32))
164 #define FPCR_UNF (1U << (55 - 32))
165 #define FPCR_OVF (1U << (54 - 32))
166 #define FPCR_DZE (1U << (53 - 32))
167 #define FPCR_INV (1U << (52 - 32))
168 #define FPCR_OVFD (1U << (51 - 32))
169 #define FPCR_DZED (1U << (50 - 32))
170 #define FPCR_INVD (1U << (49 - 32))
171 #define FPCR_DNZ (1U << (48 - 32))
172 #define FPCR_DNOD (1U << (47 - 32))
173 #define FPCR_STATUS_MASK (FPCR_IOV | FPCR_INE | FPCR_UNF \
174 | FPCR_OVF | FPCR_DZE | FPCR_INV)
176 /* The silly software trap enables implemented by the kernel emulation.
177 These are more or less architecturally required, since the real hardware
178 has read-as-zero bits in the FPCR when the features aren't implemented.
179 For the purposes of QEMU, we pretend the FPCR can hold everything. */
180 #define SWCR_TRAP_ENABLE_INV (1U << 1)
181 #define SWCR_TRAP_ENABLE_DZE (1U << 2)
182 #define SWCR_TRAP_ENABLE_OVF (1U << 3)
183 #define SWCR_TRAP_ENABLE_UNF (1U << 4)
184 #define SWCR_TRAP_ENABLE_INE (1U << 5)
185 #define SWCR_TRAP_ENABLE_DNO (1U << 6)
186 #define SWCR_TRAP_ENABLE_MASK ((1U << 7) - (1U << 1))
188 #define SWCR_MAP_DMZ (1U << 12)
189 #define SWCR_MAP_UMZ (1U << 13)
190 #define SWCR_MAP_MASK (SWCR_MAP_DMZ | SWCR_MAP_UMZ)
192 #define SWCR_STATUS_INV (1U << 17)
193 #define SWCR_STATUS_DZE (1U << 18)
194 #define SWCR_STATUS_OVF (1U << 19)
195 #define SWCR_STATUS_UNF (1U << 20)
196 #define SWCR_STATUS_INE (1U << 21)
197 #define SWCR_STATUS_DNO (1U << 22)
198 #define SWCR_STATUS_MASK ((1U << 23) - (1U << 17))
200 #define SWCR_MASK (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK | SWCR_STATUS_MASK)
202 /* MMU modes definitions */
204 /* Alpha has 5 MMU modes: PALcode, Kernel, Executive, Supervisor, and User.
205 The Unix PALcode only exposes the kernel and user modes; presumably
206 executive and supervisor are used by VMS.
208 PALcode itself uses physical mode for code and kernel mode for data;
209 there are PALmode instructions that can access data via physical mode
210 or via an os-installed "alternate mode", which is one of the 4 above.
212 That said, we're only emulating Unix PALcode, and not attempting VMS,
213 so we don't need to implement Executive and Supervisor. QEMU's own
214 PALcode cheats and usees the KSEG mapping for its code+data rather than
215 physical addresses. */
217 #define NB_MMU_MODES 3
219 #define MMU_MODE0_SUFFIX _kernel
220 #define MMU_MODE1_SUFFIX _user
221 #define MMU_KERNEL_IDX 0
222 #define MMU_USER_IDX 1
223 #define MMU_PHYS_IDX 2
225 typedef struct CPUAlphaState CPUAlphaState
;
227 struct CPUAlphaState
{
235 /* The FPCR, and disassembled portions thereof. */
237 uint32_t fpcr_exc_enable
;
238 float_status fp_status
;
239 uint8_t fpcr_dyn_round
;
240 uint8_t fpcr_flush_to_zero
;
242 /* The Internal Processor Registers. Some of these we assume always
243 exist for use in user-mode. */
251 /* These pass data from the exception logic in the translator and
252 helpers to the OS entry point. This is used for both system
253 emulation and user-mode. */
258 #if !defined(CONFIG_USER_ONLY)
259 /* The internal data required by our emulation of the Unix PALcode. */
267 uint64_t scratch
[24];
270 /* This alarm doesn't exist in real hardware; we wish it did. */
271 uint64_t alarm_expire
;
273 /* Those resources are used only in QEMU core */
285 * @env: #CPUAlphaState
296 /* This alarm doesn't exist in real hardware; we wish it did. */
297 QEMUTimer
*alarm_timer
;
300 static inline AlphaCPU
*alpha_env_get_cpu(CPUAlphaState
*env
)
302 return container_of(env
, AlphaCPU
, env
);
305 #define ENV_GET_CPU(e) CPU(alpha_env_get_cpu(e))
307 #define ENV_OFFSET offsetof(AlphaCPU, env)
309 #ifndef CONFIG_USER_ONLY
310 extern const struct VMStateDescription vmstate_alpha_cpu
;
313 void alpha_cpu_do_interrupt(CPUState
*cpu
);
314 bool alpha_cpu_exec_interrupt(CPUState
*cpu
, int int_req
);
315 void alpha_cpu_dump_state(CPUState
*cs
, FILE *f
, fprintf_function cpu_fprintf
,
317 hwaddr
alpha_cpu_get_phys_page_debug(CPUState
*cpu
, vaddr addr
);
318 int alpha_cpu_gdb_read_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
319 int alpha_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
320 void alpha_cpu_do_unaligned_access(CPUState
*cpu
, vaddr addr
,
321 MMUAccessType access_type
,
322 int mmu_idx
, uintptr_t retaddr
);
324 #define cpu_list alpha_cpu_list
325 #define cpu_signal_handler cpu_alpha_signal_handler
327 #include "exec/cpu-all.h"
330 FEATURE_ASN
= 0x00000001,
331 FEATURE_SPS
= 0x00000002,
332 FEATURE_VIRBND
= 0x00000004,
333 FEATURE_TBCHK
= 0x00000008,
350 /* Alpha-specific interrupt pending bits. */
351 #define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_EXT_0
352 #define CPU_INTERRUPT_SMP CPU_INTERRUPT_TGT_EXT_1
353 #define CPU_INTERRUPT_MCHK CPU_INTERRUPT_TGT_EXT_2
355 /* OSF/1 Page table bits. */
358 PTE_FOR
= 0x0002, /* used for page protection (fault on read) */
359 PTE_FOW
= 0x0004, /* used for page protection (fault on write) */
360 PTE_FOE
= 0x0008, /* used for page protection (fault on exec) */
368 /* Hardware interrupt (entInt) constants. */
377 /* Memory management (entMM) constants. */
386 /* Arithmetic exception (entArith) constants. */
388 EXC_M_SWC
= 1, /* Software completion */
389 EXC_M_INV
= 2, /* Invalid operation */
390 EXC_M_DZE
= 4, /* Division by zero */
391 EXC_M_FOV
= 8, /* Overflow */
392 EXC_M_UNF
= 16, /* Underflow */
393 EXC_M_INE
= 32, /* Inexact result */
394 EXC_M_IOV
= 64 /* Integer Overflow */
397 /* Processor status constants. */
399 /* Low 3 bits are interrupt mask level. */
402 /* Bits 4 and 5 are the mmu mode. The VMS PALcode uses all 4 modes;
403 The Unix PALcode only uses bit 4. */
407 static inline int cpu_mmu_index(CPUAlphaState
*env
, bool ifetch
)
410 return MMU_KERNEL_IDX
;
411 } else if (env
->ps
& PS_USER_MODE
) {
414 return MMU_KERNEL_IDX
;
455 void alpha_translate_init(void);
457 AlphaCPU
*cpu_alpha_init(const char *cpu_model
);
459 #define cpu_init(cpu_model) CPU(cpu_alpha_init(cpu_model))
461 void alpha_cpu_list(FILE *f
, fprintf_function cpu_fprintf
);
462 /* you can call this signal handler from your SIGBUS and SIGSEGV
463 signal handlers to inform the virtual CPU of exceptions. non zero
464 is returned if the signal was handled by the virtual CPU. */
465 int cpu_alpha_signal_handler(int host_signum
, void *pinfo
,
467 int alpha_cpu_handle_mmu_fault(CPUState
*cpu
, vaddr address
, int rw
,
469 void QEMU_NORETURN
dynamic_excp(CPUAlphaState
*, uintptr_t, int, int);
470 void QEMU_NORETURN
arith_excp(CPUAlphaState
*, uintptr_t, int, uint64_t);
472 uint64_t cpu_alpha_load_fpcr (CPUAlphaState
*env
);
473 void cpu_alpha_store_fpcr (CPUAlphaState
*env
, uint64_t val
);
474 uint64_t cpu_alpha_load_gr(CPUAlphaState
*env
, unsigned reg
);
475 void cpu_alpha_store_gr(CPUAlphaState
*env
, unsigned reg
, uint64_t val
);
476 #ifndef CONFIG_USER_ONLY
477 QEMU_NORETURN
void alpha_cpu_unassigned_access(CPUState
*cpu
, hwaddr addr
,
478 bool is_write
, bool is_exec
,
479 int unused
, unsigned size
);
482 /* Bits in TB->FLAGS that control how translation is processed. */
484 TB_FLAGS_PAL_MODE
= 1,
486 TB_FLAGS_USER_MODE
= 8,
488 TB_FLAGS_AMASK_SHIFT
= 4,
489 TB_FLAGS_AMASK_BWX
= AMASK_BWX
<< TB_FLAGS_AMASK_SHIFT
,
490 TB_FLAGS_AMASK_FIX
= AMASK_FIX
<< TB_FLAGS_AMASK_SHIFT
,
491 TB_FLAGS_AMASK_CIX
= AMASK_CIX
<< TB_FLAGS_AMASK_SHIFT
,
492 TB_FLAGS_AMASK_MVI
= AMASK_MVI
<< TB_FLAGS_AMASK_SHIFT
,
493 TB_FLAGS_AMASK_TRAP
= AMASK_TRAP
<< TB_FLAGS_AMASK_SHIFT
,
494 TB_FLAGS_AMASK_PREFETCH
= AMASK_PREFETCH
<< TB_FLAGS_AMASK_SHIFT
,
497 static inline void cpu_get_tb_cpu_state(CPUAlphaState
*env
, target_ulong
*pc
,
498 target_ulong
*cs_base
, uint32_t *pflags
)
506 flags
= TB_FLAGS_PAL_MODE
;
508 flags
= env
->ps
& PS_USER_MODE
;
511 flags
|= TB_FLAGS_FEN
;
513 flags
|= env
->amask
<< TB_FLAGS_AMASK_SHIFT
;
518 #endif /* ALPHA_CPU_H */