2 * PowerPC emulation for qemu: main translation routines.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
24 #include "disas/disas.h"
25 #include "exec/exec-all.h"
26 #include "tcg/tcg-op.h"
27 #include "tcg/tcg-op-gvec.h"
28 #include "qemu/host-utils.h"
29 #include "qemu/main-loop.h"
30 #include "exec/cpu_ldst.h"
32 #include "exec/helper-proto.h"
33 #include "exec/helper-gen.h"
35 #include "trace-tcg.h"
36 #include "exec/translator.h"
38 #include "qemu/atomic128.h"
41 #include "qemu/qemu-print.h"
42 #include "qapi/error.h"
44 #define CPU_SINGLE_STEP 0x1
45 #define CPU_BRANCH_STEP 0x2
46 #define GDBSTUB_SINGLE_STEP 0x4
48 /* Include definitions for instructions classes and implementations flags */
49 /* #define PPC_DEBUG_DISAS */
51 #ifdef PPC_DEBUG_DISAS
52 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
54 # define LOG_DISAS(...) do { } while (0)
56 /*****************************************************************************/
57 /* Code translation helpers */
59 /* global register indexes */
60 static char cpu_reg_names
[10 * 3 + 22 * 4 /* GPR */
61 + 10 * 4 + 22 * 5 /* SPE GPRh */
63 static TCGv cpu_gpr
[32];
64 static TCGv cpu_gprh
[32];
65 static TCGv_i32 cpu_crf
[8];
70 #if defined(TARGET_PPC64)
73 static TCGv cpu_xer
, cpu_so
, cpu_ov
, cpu_ca
, cpu_ov32
, cpu_ca32
;
74 static TCGv cpu_reserve
;
75 static TCGv cpu_reserve_val
;
76 static TCGv cpu_fpscr
;
77 static TCGv_i32 cpu_access_type
;
79 #include "exec/gen-icount.h"
81 void ppc_translate_init(void)
85 size_t cpu_reg_names_size
;
88 cpu_reg_names_size
= sizeof(cpu_reg_names
);
90 for (i
= 0; i
< 8; i
++) {
91 snprintf(p
, cpu_reg_names_size
, "crf%d", i
);
92 cpu_crf
[i
] = tcg_global_mem_new_i32(cpu_env
,
93 offsetof(CPUPPCState
, crf
[i
]), p
);
95 cpu_reg_names_size
-= 5;
98 for (i
= 0; i
< 32; i
++) {
99 snprintf(p
, cpu_reg_names_size
, "r%d", i
);
100 cpu_gpr
[i
] = tcg_global_mem_new(cpu_env
,
101 offsetof(CPUPPCState
, gpr
[i
]), p
);
102 p
+= (i
< 10) ? 3 : 4;
103 cpu_reg_names_size
-= (i
< 10) ? 3 : 4;
104 snprintf(p
, cpu_reg_names_size
, "r%dH", i
);
105 cpu_gprh
[i
] = tcg_global_mem_new(cpu_env
,
106 offsetof(CPUPPCState
, gprh
[i
]), p
);
107 p
+= (i
< 10) ? 4 : 5;
108 cpu_reg_names_size
-= (i
< 10) ? 4 : 5;
111 cpu_nip
= tcg_global_mem_new(cpu_env
,
112 offsetof(CPUPPCState
, nip
), "nip");
114 cpu_msr
= tcg_global_mem_new(cpu_env
,
115 offsetof(CPUPPCState
, msr
), "msr");
117 cpu_ctr
= tcg_global_mem_new(cpu_env
,
118 offsetof(CPUPPCState
, ctr
), "ctr");
120 cpu_lr
= tcg_global_mem_new(cpu_env
,
121 offsetof(CPUPPCState
, lr
), "lr");
123 #if defined(TARGET_PPC64)
124 cpu_cfar
= tcg_global_mem_new(cpu_env
,
125 offsetof(CPUPPCState
, cfar
), "cfar");
128 cpu_xer
= tcg_global_mem_new(cpu_env
,
129 offsetof(CPUPPCState
, xer
), "xer");
130 cpu_so
= tcg_global_mem_new(cpu_env
,
131 offsetof(CPUPPCState
, so
), "SO");
132 cpu_ov
= tcg_global_mem_new(cpu_env
,
133 offsetof(CPUPPCState
, ov
), "OV");
134 cpu_ca
= tcg_global_mem_new(cpu_env
,
135 offsetof(CPUPPCState
, ca
), "CA");
136 cpu_ov32
= tcg_global_mem_new(cpu_env
,
137 offsetof(CPUPPCState
, ov32
), "OV32");
138 cpu_ca32
= tcg_global_mem_new(cpu_env
,
139 offsetof(CPUPPCState
, ca32
), "CA32");
141 cpu_reserve
= tcg_global_mem_new(cpu_env
,
142 offsetof(CPUPPCState
, reserve_addr
),
144 cpu_reserve_val
= tcg_global_mem_new(cpu_env
,
145 offsetof(CPUPPCState
, reserve_val
),
148 cpu_fpscr
= tcg_global_mem_new(cpu_env
,
149 offsetof(CPUPPCState
, fpscr
), "fpscr");
151 cpu_access_type
= tcg_global_mem_new_i32(cpu_env
,
152 offsetof(CPUPPCState
, access_type
),
156 /* internal defines */
157 struct DisasContext
{
158 DisasContextBase base
;
159 target_ulong cia
; /* current instruction address */
161 /* Routine used to access memory */
162 bool pr
, hv
, dr
, le_mode
;
164 bool need_access_type
;
167 /* Translation flags */
168 MemOp default_tcg_memop_mask
;
169 #if defined(TARGET_PPC64)
174 bool altivec_enabled
;
179 ppc_spr_t
*spr_cb
; /* Needed to check rights for mfspr/mtspr */
180 int singlestep_enabled
;
182 uint64_t insns_flags
;
183 uint64_t insns_flags2
;
186 #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */
187 #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */
188 #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */
189 #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */
191 /* Return true iff byteswap is needed in a scalar memop */
192 static inline bool need_byteswap(const DisasContext
*ctx
)
194 #if defined(TARGET_WORDS_BIGENDIAN)
197 return !ctx
->le_mode
;
201 /* True when active word size < size of target_long. */
203 # define NARROW_MODE(C) (!(C)->sf_mode)
205 # define NARROW_MODE(C) 0
208 struct opc_handler_t
{
209 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
211 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
213 /* instruction type */
215 /* extended instruction type */
218 void (*handler
)(DisasContext
*ctx
);
221 /* SPR load/store helpers */
222 static inline void gen_load_spr(TCGv t
, int reg
)
224 tcg_gen_ld_tl(t
, cpu_env
, offsetof(CPUPPCState
, spr
[reg
]));
227 static inline void gen_store_spr(int reg
, TCGv t
)
229 tcg_gen_st_tl(t
, cpu_env
, offsetof(CPUPPCState
, spr
[reg
]));
232 static inline void gen_set_access_type(DisasContext
*ctx
, int access_type
)
234 if (ctx
->need_access_type
&& ctx
->access_type
!= access_type
) {
235 tcg_gen_movi_i32(cpu_access_type
, access_type
);
236 ctx
->access_type
= access_type
;
240 static inline void gen_update_nip(DisasContext
*ctx
, target_ulong nip
)
242 if (NARROW_MODE(ctx
)) {
245 tcg_gen_movi_tl(cpu_nip
, nip
);
248 static void gen_exception_err(DisasContext
*ctx
, uint32_t excp
, uint32_t error
)
253 * These are all synchronous exceptions, we set the PC back to the
254 * faulting instruction
256 gen_update_nip(ctx
, ctx
->cia
);
257 t0
= tcg_const_i32(excp
);
258 t1
= tcg_const_i32(error
);
259 gen_helper_raise_exception_err(cpu_env
, t0
, t1
);
260 tcg_temp_free_i32(t0
);
261 tcg_temp_free_i32(t1
);
262 ctx
->base
.is_jmp
= DISAS_NORETURN
;
265 static void gen_exception(DisasContext
*ctx
, uint32_t excp
)
270 * These are all synchronous exceptions, we set the PC back to the
271 * faulting instruction
273 gen_update_nip(ctx
, ctx
->cia
);
274 t0
= tcg_const_i32(excp
);
275 gen_helper_raise_exception(cpu_env
, t0
);
276 tcg_temp_free_i32(t0
);
277 ctx
->base
.is_jmp
= DISAS_NORETURN
;
280 static void gen_exception_nip(DisasContext
*ctx
, uint32_t excp
,
285 gen_update_nip(ctx
, nip
);
286 t0
= tcg_const_i32(excp
);
287 gen_helper_raise_exception(cpu_env
, t0
);
288 tcg_temp_free_i32(t0
);
289 ctx
->base
.is_jmp
= DISAS_NORETURN
;
292 static void gen_icount_io_start(DisasContext
*ctx
)
294 if (tb_cflags(ctx
->base
.tb
) & CF_USE_ICOUNT
) {
297 * An I/O instruction must be last in the TB.
298 * Chain to the next TB, and let the code from gen_tb_start
299 * decide if we need to return to the main loop.
300 * Doing this first also allows this value to be overridden.
302 ctx
->base
.is_jmp
= DISAS_TOO_MANY
;
307 * Tells the caller what is the appropriate exception to generate and prepares
308 * SPR registers for this exception.
310 * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or
311 * POWERPC_EXCP_DEBUG (on BookE).
313 static uint32_t gen_prep_dbgex(DisasContext
*ctx
)
315 if (ctx
->flags
& POWERPC_FLAG_DE
) {
316 target_ulong dbsr
= 0;
317 if (ctx
->singlestep_enabled
& CPU_SINGLE_STEP
) {
320 /* Must have been branch */
323 TCGv t0
= tcg_temp_new();
324 gen_load_spr(t0
, SPR_BOOKE_DBSR
);
325 tcg_gen_ori_tl(t0
, t0
, dbsr
);
326 gen_store_spr(SPR_BOOKE_DBSR
, t0
);
328 return POWERPC_EXCP_DEBUG
;
330 return POWERPC_EXCP_TRACE
;
334 static void gen_debug_exception(DisasContext
*ctx
)
336 gen_helper_raise_exception(cpu_env
, tcg_constant_i32(EXCP_DEBUG
));
337 ctx
->base
.is_jmp
= DISAS_NORETURN
;
340 static inline void gen_inval_exception(DisasContext
*ctx
, uint32_t error
)
342 /* Will be converted to program check if needed */
343 gen_exception_err(ctx
, POWERPC_EXCP_HV_EMU
, POWERPC_EXCP_INVAL
| error
);
346 static inline void gen_priv_exception(DisasContext
*ctx
, uint32_t error
)
348 gen_exception_err(ctx
, POWERPC_EXCP_PROGRAM
, POWERPC_EXCP_PRIV
| error
);
351 static inline void gen_hvpriv_exception(DisasContext
*ctx
, uint32_t error
)
353 /* Will be converted to program check if needed */
354 gen_exception_err(ctx
, POWERPC_EXCP_HV_EMU
, POWERPC_EXCP_PRIV
| error
);
357 /*****************************************************************************/
358 /* SPR READ/WRITE CALLBACKS */
360 void spr_noaccess(DisasContext
*ctx
, int gprn
, int sprn
)
363 sprn
= ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
364 printf("ERROR: try to access SPR %d !\n", sprn
);
368 /* #define PPC_DUMP_SPR_ACCESSES */
372 * do nothing but store/retrieve spr value
374 static void spr_load_dump_spr(int sprn
)
376 #ifdef PPC_DUMP_SPR_ACCESSES
377 TCGv_i32 t0
= tcg_const_i32(sprn
);
378 gen_helper_load_dump_spr(cpu_env
, t0
);
379 tcg_temp_free_i32(t0
);
383 void spr_read_generic(DisasContext
*ctx
, int gprn
, int sprn
)
385 gen_load_spr(cpu_gpr
[gprn
], sprn
);
386 spr_load_dump_spr(sprn
);
389 static void spr_store_dump_spr(int sprn
)
391 #ifdef PPC_DUMP_SPR_ACCESSES
392 TCGv_i32 t0
= tcg_const_i32(sprn
);
393 gen_helper_store_dump_spr(cpu_env
, t0
);
394 tcg_temp_free_i32(t0
);
398 void spr_write_generic(DisasContext
*ctx
, int sprn
, int gprn
)
400 gen_store_spr(sprn
, cpu_gpr
[gprn
]);
401 spr_store_dump_spr(sprn
);
404 #if !defined(CONFIG_USER_ONLY)
405 void spr_write_generic32(DisasContext
*ctx
, int sprn
, int gprn
)
408 TCGv t0
= tcg_temp_new();
409 tcg_gen_ext32u_tl(t0
, cpu_gpr
[gprn
]);
410 gen_store_spr(sprn
, t0
);
412 spr_store_dump_spr(sprn
);
414 spr_write_generic(ctx
, sprn
, gprn
);
418 void spr_write_clear(DisasContext
*ctx
, int sprn
, int gprn
)
420 TCGv t0
= tcg_temp_new();
421 TCGv t1
= tcg_temp_new();
422 gen_load_spr(t0
, sprn
);
423 tcg_gen_neg_tl(t1
, cpu_gpr
[gprn
]);
424 tcg_gen_and_tl(t0
, t0
, t1
);
425 gen_store_spr(sprn
, t0
);
430 void spr_access_nop(DisasContext
*ctx
, int sprn
, int gprn
)
436 /* SPR common to all PowerPC */
438 void spr_read_xer(DisasContext
*ctx
, int gprn
, int sprn
)
440 TCGv dst
= cpu_gpr
[gprn
];
441 TCGv t0
= tcg_temp_new();
442 TCGv t1
= tcg_temp_new();
443 TCGv t2
= tcg_temp_new();
444 tcg_gen_mov_tl(dst
, cpu_xer
);
445 tcg_gen_shli_tl(t0
, cpu_so
, XER_SO
);
446 tcg_gen_shli_tl(t1
, cpu_ov
, XER_OV
);
447 tcg_gen_shli_tl(t2
, cpu_ca
, XER_CA
);
448 tcg_gen_or_tl(t0
, t0
, t1
);
449 tcg_gen_or_tl(dst
, dst
, t2
);
450 tcg_gen_or_tl(dst
, dst
, t0
);
451 if (is_isa300(ctx
)) {
452 tcg_gen_shli_tl(t0
, cpu_ov32
, XER_OV32
);
453 tcg_gen_or_tl(dst
, dst
, t0
);
454 tcg_gen_shli_tl(t0
, cpu_ca32
, XER_CA32
);
455 tcg_gen_or_tl(dst
, dst
, t0
);
462 void spr_write_xer(DisasContext
*ctx
, int sprn
, int gprn
)
464 TCGv src
= cpu_gpr
[gprn
];
465 /* Write all flags, while reading back check for isa300 */
466 tcg_gen_andi_tl(cpu_xer
, src
,
468 (1u << XER_OV
) | (1u << XER_OV32
) |
469 (1u << XER_CA
) | (1u << XER_CA32
)));
470 tcg_gen_extract_tl(cpu_ov32
, src
, XER_OV32
, 1);
471 tcg_gen_extract_tl(cpu_ca32
, src
, XER_CA32
, 1);
472 tcg_gen_extract_tl(cpu_so
, src
, XER_SO
, 1);
473 tcg_gen_extract_tl(cpu_ov
, src
, XER_OV
, 1);
474 tcg_gen_extract_tl(cpu_ca
, src
, XER_CA
, 1);
478 void spr_read_lr(DisasContext
*ctx
, int gprn
, int sprn
)
480 tcg_gen_mov_tl(cpu_gpr
[gprn
], cpu_lr
);
483 void spr_write_lr(DisasContext
*ctx
, int sprn
, int gprn
)
485 tcg_gen_mov_tl(cpu_lr
, cpu_gpr
[gprn
]);
489 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
490 void spr_read_cfar(DisasContext
*ctx
, int gprn
, int sprn
)
492 tcg_gen_mov_tl(cpu_gpr
[gprn
], cpu_cfar
);
495 void spr_write_cfar(DisasContext
*ctx
, int sprn
, int gprn
)
497 tcg_gen_mov_tl(cpu_cfar
, cpu_gpr
[gprn
]);
499 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
502 void spr_read_ctr(DisasContext
*ctx
, int gprn
, int sprn
)
504 tcg_gen_mov_tl(cpu_gpr
[gprn
], cpu_ctr
);
507 void spr_write_ctr(DisasContext
*ctx
, int sprn
, int gprn
)
509 tcg_gen_mov_tl(cpu_ctr
, cpu_gpr
[gprn
]);
512 /* User read access to SPR */
518 void spr_read_ureg(DisasContext
*ctx
, int gprn
, int sprn
)
520 gen_load_spr(cpu_gpr
[gprn
], sprn
+ 0x10);
523 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
524 void spr_write_ureg(DisasContext
*ctx
, int sprn
, int gprn
)
526 gen_store_spr(sprn
+ 0x10, cpu_gpr
[gprn
]);
530 /* SPR common to all non-embedded PowerPC */
532 #if !defined(CONFIG_USER_ONLY)
533 void spr_read_decr(DisasContext
*ctx
, int gprn
, int sprn
)
535 gen_icount_io_start(ctx
);
536 gen_helper_load_decr(cpu_gpr
[gprn
], cpu_env
);
539 void spr_write_decr(DisasContext
*ctx
, int sprn
, int gprn
)
541 gen_icount_io_start(ctx
);
542 gen_helper_store_decr(cpu_env
, cpu_gpr
[gprn
]);
546 /* SPR common to all non-embedded PowerPC, except 601 */
548 void spr_read_tbl(DisasContext
*ctx
, int gprn
, int sprn
)
550 gen_icount_io_start(ctx
);
551 gen_helper_load_tbl(cpu_gpr
[gprn
], cpu_env
);
554 void spr_read_tbu(DisasContext
*ctx
, int gprn
, int sprn
)
556 gen_icount_io_start(ctx
);
557 gen_helper_load_tbu(cpu_gpr
[gprn
], cpu_env
);
560 void spr_read_atbl(DisasContext
*ctx
, int gprn
, int sprn
)
562 gen_helper_load_atbl(cpu_gpr
[gprn
], cpu_env
);
565 void spr_read_atbu(DisasContext
*ctx
, int gprn
, int sprn
)
567 gen_helper_load_atbu(cpu_gpr
[gprn
], cpu_env
);
570 #if !defined(CONFIG_USER_ONLY)
571 void spr_write_tbl(DisasContext
*ctx
, int sprn
, int gprn
)
573 gen_icount_io_start(ctx
);
574 gen_helper_store_tbl(cpu_env
, cpu_gpr
[gprn
]);
577 void spr_write_tbu(DisasContext
*ctx
, int sprn
, int gprn
)
579 gen_icount_io_start(ctx
);
580 gen_helper_store_tbu(cpu_env
, cpu_gpr
[gprn
]);
583 void spr_write_atbl(DisasContext
*ctx
, int sprn
, int gprn
)
585 gen_helper_store_atbl(cpu_env
, cpu_gpr
[gprn
]);
588 void spr_write_atbu(DisasContext
*ctx
, int sprn
, int gprn
)
590 gen_helper_store_atbu(cpu_env
, cpu_gpr
[gprn
]);
593 #if defined(TARGET_PPC64)
594 void spr_read_purr(DisasContext
*ctx
, int gprn
, int sprn
)
596 gen_icount_io_start(ctx
);
597 gen_helper_load_purr(cpu_gpr
[gprn
], cpu_env
);
600 void spr_write_purr(DisasContext
*ctx
, int sprn
, int gprn
)
602 gen_icount_io_start(ctx
);
603 gen_helper_store_purr(cpu_env
, cpu_gpr
[gprn
]);
607 void spr_read_hdecr(DisasContext
*ctx
, int gprn
, int sprn
)
609 gen_icount_io_start(ctx
);
610 gen_helper_load_hdecr(cpu_gpr
[gprn
], cpu_env
);
613 void spr_write_hdecr(DisasContext
*ctx
, int sprn
, int gprn
)
615 gen_icount_io_start(ctx
);
616 gen_helper_store_hdecr(cpu_env
, cpu_gpr
[gprn
]);
619 void spr_read_vtb(DisasContext
*ctx
, int gprn
, int sprn
)
621 gen_icount_io_start(ctx
);
622 gen_helper_load_vtb(cpu_gpr
[gprn
], cpu_env
);
625 void spr_write_vtb(DisasContext
*ctx
, int sprn
, int gprn
)
627 gen_icount_io_start(ctx
);
628 gen_helper_store_vtb(cpu_env
, cpu_gpr
[gprn
]);
631 void spr_write_tbu40(DisasContext
*ctx
, int sprn
, int gprn
)
633 gen_icount_io_start(ctx
);
634 gen_helper_store_tbu40(cpu_env
, cpu_gpr
[gprn
]);
640 #if !defined(CONFIG_USER_ONLY)
641 /* IBAT0U...IBAT0U */
642 /* IBAT0L...IBAT7L */
643 void spr_read_ibat(DisasContext
*ctx
, int gprn
, int sprn
)
645 tcg_gen_ld_tl(cpu_gpr
[gprn
], cpu_env
,
646 offsetof(CPUPPCState
,
647 IBAT
[sprn
& 1][(sprn
- SPR_IBAT0U
) / 2]));
650 void spr_read_ibat_h(DisasContext
*ctx
, int gprn
, int sprn
)
652 tcg_gen_ld_tl(cpu_gpr
[gprn
], cpu_env
,
653 offsetof(CPUPPCState
,
654 IBAT
[sprn
& 1][((sprn
- SPR_IBAT4U
) / 2) + 4]));
657 void spr_write_ibatu(DisasContext
*ctx
, int sprn
, int gprn
)
659 TCGv_i32 t0
= tcg_const_i32((sprn
- SPR_IBAT0U
) / 2);
660 gen_helper_store_ibatu(cpu_env
, t0
, cpu_gpr
[gprn
]);
661 tcg_temp_free_i32(t0
);
664 void spr_write_ibatu_h(DisasContext
*ctx
, int sprn
, int gprn
)
666 TCGv_i32 t0
= tcg_const_i32(((sprn
- SPR_IBAT4U
) / 2) + 4);
667 gen_helper_store_ibatu(cpu_env
, t0
, cpu_gpr
[gprn
]);
668 tcg_temp_free_i32(t0
);
671 void spr_write_ibatl(DisasContext
*ctx
, int sprn
, int gprn
)
673 TCGv_i32 t0
= tcg_const_i32((sprn
- SPR_IBAT0L
) / 2);
674 gen_helper_store_ibatl(cpu_env
, t0
, cpu_gpr
[gprn
]);
675 tcg_temp_free_i32(t0
);
678 void spr_write_ibatl_h(DisasContext
*ctx
, int sprn
, int gprn
)
680 TCGv_i32 t0
= tcg_const_i32(((sprn
- SPR_IBAT4L
) / 2) + 4);
681 gen_helper_store_ibatl(cpu_env
, t0
, cpu_gpr
[gprn
]);
682 tcg_temp_free_i32(t0
);
685 /* DBAT0U...DBAT7U */
686 /* DBAT0L...DBAT7L */
687 void spr_read_dbat(DisasContext
*ctx
, int gprn
, int sprn
)
689 tcg_gen_ld_tl(cpu_gpr
[gprn
], cpu_env
,
690 offsetof(CPUPPCState
,
691 DBAT
[sprn
& 1][(sprn
- SPR_DBAT0U
) / 2]));
694 void spr_read_dbat_h(DisasContext
*ctx
, int gprn
, int sprn
)
696 tcg_gen_ld_tl(cpu_gpr
[gprn
], cpu_env
,
697 offsetof(CPUPPCState
,
698 DBAT
[sprn
& 1][((sprn
- SPR_DBAT4U
) / 2) + 4]));
701 void spr_write_dbatu(DisasContext
*ctx
, int sprn
, int gprn
)
703 TCGv_i32 t0
= tcg_const_i32((sprn
- SPR_DBAT0U
) / 2);
704 gen_helper_store_dbatu(cpu_env
, t0
, cpu_gpr
[gprn
]);
705 tcg_temp_free_i32(t0
);
708 void spr_write_dbatu_h(DisasContext
*ctx
, int sprn
, int gprn
)
710 TCGv_i32 t0
= tcg_const_i32(((sprn
- SPR_DBAT4U
) / 2) + 4);
711 gen_helper_store_dbatu(cpu_env
, t0
, cpu_gpr
[gprn
]);
712 tcg_temp_free_i32(t0
);
715 void spr_write_dbatl(DisasContext
*ctx
, int sprn
, int gprn
)
717 TCGv_i32 t0
= tcg_const_i32((sprn
- SPR_DBAT0L
) / 2);
718 gen_helper_store_dbatl(cpu_env
, t0
, cpu_gpr
[gprn
]);
719 tcg_temp_free_i32(t0
);
722 void spr_write_dbatl_h(DisasContext
*ctx
, int sprn
, int gprn
)
724 TCGv_i32 t0
= tcg_const_i32(((sprn
- SPR_DBAT4L
) / 2) + 4);
725 gen_helper_store_dbatl(cpu_env
, t0
, cpu_gpr
[gprn
]);
726 tcg_temp_free_i32(t0
);
730 void spr_write_sdr1(DisasContext
*ctx
, int sprn
, int gprn
)
732 gen_helper_store_sdr1(cpu_env
, cpu_gpr
[gprn
]);
735 #if defined(TARGET_PPC64)
736 /* 64 bits PowerPC specific SPRs */
738 void spr_write_pidr(DisasContext
*ctx
, int sprn
, int gprn
)
740 gen_helper_store_pidr(cpu_env
, cpu_gpr
[gprn
]);
743 void spr_write_lpidr(DisasContext
*ctx
, int sprn
, int gprn
)
745 gen_helper_store_lpidr(cpu_env
, cpu_gpr
[gprn
]);
748 void spr_read_hior(DisasContext
*ctx
, int gprn
, int sprn
)
750 tcg_gen_ld_tl(cpu_gpr
[gprn
], cpu_env
, offsetof(CPUPPCState
, excp_prefix
));
753 void spr_write_hior(DisasContext
*ctx
, int sprn
, int gprn
)
755 TCGv t0
= tcg_temp_new();
756 tcg_gen_andi_tl(t0
, cpu_gpr
[gprn
], 0x3FFFFF00000ULL
);
757 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUPPCState
, excp_prefix
));
760 void spr_write_ptcr(DisasContext
*ctx
, int sprn
, int gprn
)
762 gen_helper_store_ptcr(cpu_env
, cpu_gpr
[gprn
]);
765 void spr_write_pcr(DisasContext
*ctx
, int sprn
, int gprn
)
767 gen_helper_store_pcr(cpu_env
, cpu_gpr
[gprn
]);
771 void spr_read_dpdes(DisasContext
*ctx
, int gprn
, int sprn
)
773 gen_helper_load_dpdes(cpu_gpr
[gprn
], cpu_env
);
776 void spr_write_dpdes(DisasContext
*ctx
, int sprn
, int gprn
)
778 gen_helper_store_dpdes(cpu_env
, cpu_gpr
[gprn
]);
783 /* PowerPC 601 specific registers */
785 void spr_read_601_rtcl(DisasContext
*ctx
, int gprn
, int sprn
)
787 gen_helper_load_601_rtcl(cpu_gpr
[gprn
], cpu_env
);
790 void spr_read_601_rtcu(DisasContext
*ctx
, int gprn
, int sprn
)
792 gen_helper_load_601_rtcu(cpu_gpr
[gprn
], cpu_env
);
795 #if !defined(CONFIG_USER_ONLY)
796 void spr_write_601_rtcu(DisasContext
*ctx
, int sprn
, int gprn
)
798 gen_helper_store_601_rtcu(cpu_env
, cpu_gpr
[gprn
]);
801 void spr_write_601_rtcl(DisasContext
*ctx
, int sprn
, int gprn
)
803 gen_helper_store_601_rtcl(cpu_env
, cpu_gpr
[gprn
]);
806 void spr_write_hid0_601(DisasContext
*ctx
, int sprn
, int gprn
)
808 gen_helper_store_hid0_601(cpu_env
, cpu_gpr
[gprn
]);
809 /* Must stop the translation as endianness may have changed */
810 ctx
->base
.is_jmp
= DISAS_EXIT_UPDATE
;
815 #if !defined(CONFIG_USER_ONLY)
816 void spr_read_601_ubat(DisasContext
*ctx
, int gprn
, int sprn
)
818 tcg_gen_ld_tl(cpu_gpr
[gprn
], cpu_env
,
819 offsetof(CPUPPCState
,
820 IBAT
[sprn
& 1][(sprn
- SPR_IBAT0U
) / 2]));
823 void spr_write_601_ubatu(DisasContext
*ctx
, int sprn
, int gprn
)
825 TCGv_i32 t0
= tcg_const_i32((sprn
- SPR_IBAT0U
) / 2);
826 gen_helper_store_601_batl(cpu_env
, t0
, cpu_gpr
[gprn
]);
827 tcg_temp_free_i32(t0
);
830 void spr_write_601_ubatl(DisasContext
*ctx
, int sprn
, int gprn
)
832 TCGv_i32 t0
= tcg_const_i32((sprn
- SPR_IBAT0U
) / 2);
833 gen_helper_store_601_batu(cpu_env
, t0
, cpu_gpr
[gprn
]);
834 tcg_temp_free_i32(t0
);
838 /* PowerPC 40x specific registers */
839 #if !defined(CONFIG_USER_ONLY)
840 void spr_read_40x_pit(DisasContext
*ctx
, int gprn
, int sprn
)
842 gen_icount_io_start(ctx
);
843 gen_helper_load_40x_pit(cpu_gpr
[gprn
], cpu_env
);
846 void spr_write_40x_pit(DisasContext
*ctx
, int sprn
, int gprn
)
848 gen_icount_io_start(ctx
);
849 gen_helper_store_40x_pit(cpu_env
, cpu_gpr
[gprn
]);
852 void spr_write_40x_dbcr0(DisasContext
*ctx
, int sprn
, int gprn
)
854 gen_icount_io_start(ctx
);
855 gen_store_spr(sprn
, cpu_gpr
[gprn
]);
856 gen_helper_store_40x_dbcr0(cpu_env
, cpu_gpr
[gprn
]);
857 /* We must stop translation as we may have rebooted */
858 ctx
->base
.is_jmp
= DISAS_EXIT_UPDATE
;
861 void spr_write_40x_sler(DisasContext
*ctx
, int sprn
, int gprn
)
863 gen_icount_io_start(ctx
);
864 gen_helper_store_40x_sler(cpu_env
, cpu_gpr
[gprn
]);
867 void spr_write_booke_tcr(DisasContext
*ctx
, int sprn
, int gprn
)
869 gen_icount_io_start(ctx
);
870 gen_helper_store_booke_tcr(cpu_env
, cpu_gpr
[gprn
]);
873 void spr_write_booke_tsr(DisasContext
*ctx
, int sprn
, int gprn
)
875 gen_icount_io_start(ctx
);
876 gen_helper_store_booke_tsr(cpu_env
, cpu_gpr
[gprn
]);
880 /* PowerPC 403 specific registers */
881 /* PBL1 / PBU1 / PBL2 / PBU2 */
882 #if !defined(CONFIG_USER_ONLY)
883 void spr_read_403_pbr(DisasContext
*ctx
, int gprn
, int sprn
)
885 tcg_gen_ld_tl(cpu_gpr
[gprn
], cpu_env
,
886 offsetof(CPUPPCState
, pb
[sprn
- SPR_403_PBL1
]));
889 void spr_write_403_pbr(DisasContext
*ctx
, int sprn
, int gprn
)
891 TCGv_i32 t0
= tcg_const_i32(sprn
- SPR_403_PBL1
);
892 gen_helper_store_403_pbr(cpu_env
, t0
, cpu_gpr
[gprn
]);
893 tcg_temp_free_i32(t0
);
896 void spr_write_pir(DisasContext
*ctx
, int sprn
, int gprn
)
898 TCGv t0
= tcg_temp_new();
899 tcg_gen_andi_tl(t0
, cpu_gpr
[gprn
], 0xF);
900 gen_store_spr(SPR_PIR
, t0
);
905 /* SPE specific registers */
906 void spr_read_spefscr(DisasContext
*ctx
, int gprn
, int sprn
)
908 TCGv_i32 t0
= tcg_temp_new_i32();
909 tcg_gen_ld_i32(t0
, cpu_env
, offsetof(CPUPPCState
, spe_fscr
));
910 tcg_gen_extu_i32_tl(cpu_gpr
[gprn
], t0
);
911 tcg_temp_free_i32(t0
);
914 void spr_write_spefscr(DisasContext
*ctx
, int sprn
, int gprn
)
916 TCGv_i32 t0
= tcg_temp_new_i32();
917 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[gprn
]);
918 tcg_gen_st_i32(t0
, cpu_env
, offsetof(CPUPPCState
, spe_fscr
));
919 tcg_temp_free_i32(t0
);
922 #if !defined(CONFIG_USER_ONLY)
923 /* Callback used to write the exception vector base */
924 void spr_write_excp_prefix(DisasContext
*ctx
, int sprn
, int gprn
)
926 TCGv t0
= tcg_temp_new();
927 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUPPCState
, ivpr_mask
));
928 tcg_gen_and_tl(t0
, t0
, cpu_gpr
[gprn
]);
929 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUPPCState
, excp_prefix
));
930 gen_store_spr(sprn
, t0
);
934 void spr_write_excp_vector(DisasContext
*ctx
, int sprn
, int gprn
)
938 if (sprn
>= SPR_BOOKE_IVOR0
&& sprn
<= SPR_BOOKE_IVOR15
) {
939 sprn_offs
= sprn
- SPR_BOOKE_IVOR0
;
940 } else if (sprn
>= SPR_BOOKE_IVOR32
&& sprn
<= SPR_BOOKE_IVOR37
) {
941 sprn_offs
= sprn
- SPR_BOOKE_IVOR32
+ 32;
942 } else if (sprn
>= SPR_BOOKE_IVOR38
&& sprn
<= SPR_BOOKE_IVOR42
) {
943 sprn_offs
= sprn
- SPR_BOOKE_IVOR38
+ 38;
945 printf("Trying to write an unknown exception vector %d %03x\n",
947 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
951 TCGv t0
= tcg_temp_new();
952 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUPPCState
, ivor_mask
));
953 tcg_gen_and_tl(t0
, t0
, cpu_gpr
[gprn
]);
954 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUPPCState
, excp_vectors
[sprn_offs
]));
955 gen_store_spr(sprn
, t0
);
961 #ifndef CONFIG_USER_ONLY
962 void spr_write_amr(DisasContext
*ctx
, int sprn
, int gprn
)
964 TCGv t0
= tcg_temp_new();
965 TCGv t1
= tcg_temp_new();
966 TCGv t2
= tcg_temp_new();
969 * Note, the HV=1 PR=0 case is handled earlier by simply using
970 * spr_write_generic for HV mode in the SPR table
973 /* Build insertion mask into t1 based on context */
975 gen_load_spr(t1
, SPR_UAMOR
);
977 gen_load_spr(t1
, SPR_AMOR
);
980 /* Mask new bits into t2 */
981 tcg_gen_and_tl(t2
, t1
, cpu_gpr
[gprn
]);
983 /* Load AMR and clear new bits in t0 */
984 gen_load_spr(t0
, SPR_AMR
);
985 tcg_gen_andc_tl(t0
, t0
, t1
);
987 /* Or'in new bits and write it out */
988 tcg_gen_or_tl(t0
, t0
, t2
);
989 gen_store_spr(SPR_AMR
, t0
);
990 spr_store_dump_spr(SPR_AMR
);
997 void spr_write_uamor(DisasContext
*ctx
, int sprn
, int gprn
)
999 TCGv t0
= tcg_temp_new();
1000 TCGv t1
= tcg_temp_new();
1001 TCGv t2
= tcg_temp_new();
1004 * Note, the HV=1 case is handled earlier by simply using
1005 * spr_write_generic for HV mode in the SPR table
1008 /* Build insertion mask into t1 based on context */
1009 gen_load_spr(t1
, SPR_AMOR
);
1011 /* Mask new bits into t2 */
1012 tcg_gen_and_tl(t2
, t1
, cpu_gpr
[gprn
]);
1014 /* Load AMR and clear new bits in t0 */
1015 gen_load_spr(t0
, SPR_UAMOR
);
1016 tcg_gen_andc_tl(t0
, t0
, t1
);
1018 /* Or'in new bits and write it out */
1019 tcg_gen_or_tl(t0
, t0
, t2
);
1020 gen_store_spr(SPR_UAMOR
, t0
);
1021 spr_store_dump_spr(SPR_UAMOR
);
1028 void spr_write_iamr(DisasContext
*ctx
, int sprn
, int gprn
)
1030 TCGv t0
= tcg_temp_new();
1031 TCGv t1
= tcg_temp_new();
1032 TCGv t2
= tcg_temp_new();
1035 * Note, the HV=1 case is handled earlier by simply using
1036 * spr_write_generic for HV mode in the SPR table
1039 /* Build insertion mask into t1 based on context */
1040 gen_load_spr(t1
, SPR_AMOR
);
1042 /* Mask new bits into t2 */
1043 tcg_gen_and_tl(t2
, t1
, cpu_gpr
[gprn
]);
1045 /* Load AMR and clear new bits in t0 */
1046 gen_load_spr(t0
, SPR_IAMR
);
1047 tcg_gen_andc_tl(t0
, t0
, t1
);
1049 /* Or'in new bits and write it out */
1050 tcg_gen_or_tl(t0
, t0
, t2
);
1051 gen_store_spr(SPR_IAMR
, t0
);
1052 spr_store_dump_spr(SPR_IAMR
);
1061 #ifndef CONFIG_USER_ONLY
1062 void spr_read_thrm(DisasContext
*ctx
, int gprn
, int sprn
)
1064 gen_helper_fixup_thrm(cpu_env
);
1065 gen_load_spr(cpu_gpr
[gprn
], sprn
);
1066 spr_load_dump_spr(sprn
);
1068 #endif /* !CONFIG_USER_ONLY */
1070 #if !defined(CONFIG_USER_ONLY)
1071 void spr_write_e500_l1csr0(DisasContext
*ctx
, int sprn
, int gprn
)
1073 TCGv t0
= tcg_temp_new();
1075 tcg_gen_andi_tl(t0
, cpu_gpr
[gprn
], L1CSR0_DCE
| L1CSR0_CPE
);
1076 gen_store_spr(sprn
, t0
);
1080 void spr_write_e500_l1csr1(DisasContext
*ctx
, int sprn
, int gprn
)
1082 TCGv t0
= tcg_temp_new();
1084 tcg_gen_andi_tl(t0
, cpu_gpr
[gprn
], L1CSR1_ICE
| L1CSR1_CPE
);
1085 gen_store_spr(sprn
, t0
);
1089 void spr_write_e500_l2csr0(DisasContext
*ctx
, int sprn
, int gprn
)
1091 TCGv t0
= tcg_temp_new();
1093 tcg_gen_andi_tl(t0
, cpu_gpr
[gprn
],
1094 ~(E500_L2CSR0_L2FI
| E500_L2CSR0_L2FL
| E500_L2CSR0_L2LFC
));
1095 gen_store_spr(sprn
, t0
);
1099 void spr_write_booke206_mmucsr0(DisasContext
*ctx
, int sprn
, int gprn
)
1101 gen_helper_booke206_tlbflush(cpu_env
, cpu_gpr
[gprn
]);
1104 void spr_write_booke_pid(DisasContext
*ctx
, int sprn
, int gprn
)
1106 TCGv_i32 t0
= tcg_const_i32(sprn
);
1107 gen_helper_booke_setpid(cpu_env
, t0
, cpu_gpr
[gprn
]);
1108 tcg_temp_free_i32(t0
);
1110 void spr_write_eplc(DisasContext
*ctx
, int sprn
, int gprn
)
1112 gen_helper_booke_set_eplc(cpu_env
, cpu_gpr
[gprn
]);
1114 void spr_write_epsc(DisasContext
*ctx
, int sprn
, int gprn
)
1116 gen_helper_booke_set_epsc(cpu_env
, cpu_gpr
[gprn
]);
1121 #if !defined(CONFIG_USER_ONLY)
1122 void spr_write_mas73(DisasContext
*ctx
, int sprn
, int gprn
)
1124 TCGv val
= tcg_temp_new();
1125 tcg_gen_ext32u_tl(val
, cpu_gpr
[gprn
]);
1126 gen_store_spr(SPR_BOOKE_MAS3
, val
);
1127 tcg_gen_shri_tl(val
, cpu_gpr
[gprn
], 32);
1128 gen_store_spr(SPR_BOOKE_MAS7
, val
);
1132 void spr_read_mas73(DisasContext
*ctx
, int gprn
, int sprn
)
1134 TCGv mas7
= tcg_temp_new();
1135 TCGv mas3
= tcg_temp_new();
1136 gen_load_spr(mas7
, SPR_BOOKE_MAS7
);
1137 tcg_gen_shli_tl(mas7
, mas7
, 32);
1138 gen_load_spr(mas3
, SPR_BOOKE_MAS3
);
1139 tcg_gen_or_tl(cpu_gpr
[gprn
], mas3
, mas7
);
1140 tcg_temp_free(mas3
);
1141 tcg_temp_free(mas7
);
1147 static void gen_fscr_facility_check(DisasContext
*ctx
, int facility_sprn
,
1148 int bit
, int sprn
, int cause
)
1150 TCGv_i32 t1
= tcg_const_i32(bit
);
1151 TCGv_i32 t2
= tcg_const_i32(sprn
);
1152 TCGv_i32 t3
= tcg_const_i32(cause
);
1154 gen_helper_fscr_facility_check(cpu_env
, t1
, t2
, t3
);
1156 tcg_temp_free_i32(t3
);
1157 tcg_temp_free_i32(t2
);
1158 tcg_temp_free_i32(t1
);
1161 static void gen_msr_facility_check(DisasContext
*ctx
, int facility_sprn
,
1162 int bit
, int sprn
, int cause
)
1164 TCGv_i32 t1
= tcg_const_i32(bit
);
1165 TCGv_i32 t2
= tcg_const_i32(sprn
);
1166 TCGv_i32 t3
= tcg_const_i32(cause
);
1168 gen_helper_msr_facility_check(cpu_env
, t1
, t2
, t3
);
1170 tcg_temp_free_i32(t3
);
1171 tcg_temp_free_i32(t2
);
1172 tcg_temp_free_i32(t1
);
1175 void spr_read_prev_upper32(DisasContext
*ctx
, int gprn
, int sprn
)
1177 TCGv spr_up
= tcg_temp_new();
1178 TCGv spr
= tcg_temp_new();
1180 gen_load_spr(spr
, sprn
- 1);
1181 tcg_gen_shri_tl(spr_up
, spr
, 32);
1182 tcg_gen_ext32u_tl(cpu_gpr
[gprn
], spr_up
);
1185 tcg_temp_free(spr_up
);
1188 void spr_write_prev_upper32(DisasContext
*ctx
, int sprn
, int gprn
)
1190 TCGv spr
= tcg_temp_new();
1192 gen_load_spr(spr
, sprn
- 1);
1193 tcg_gen_deposit_tl(spr
, spr
, cpu_gpr
[gprn
], 32, 32);
1194 gen_store_spr(sprn
- 1, spr
);
1199 #if !defined(CONFIG_USER_ONLY)
1200 void spr_write_hmer(DisasContext
*ctx
, int sprn
, int gprn
)
1202 TCGv hmer
= tcg_temp_new();
1204 gen_load_spr(hmer
, sprn
);
1205 tcg_gen_and_tl(hmer
, cpu_gpr
[gprn
], hmer
);
1206 gen_store_spr(sprn
, hmer
);
1207 spr_store_dump_spr(sprn
);
1208 tcg_temp_free(hmer
);
1211 void spr_write_lpcr(DisasContext
*ctx
, int sprn
, int gprn
)
1213 gen_helper_store_lpcr(cpu_env
, cpu_gpr
[gprn
]);
1215 #endif /* !defined(CONFIG_USER_ONLY) */
1217 void spr_read_tar(DisasContext
*ctx
, int gprn
, int sprn
)
1219 gen_fscr_facility_check(ctx
, SPR_FSCR
, FSCR_TAR
, sprn
, FSCR_IC_TAR
);
1220 spr_read_generic(ctx
, gprn
, sprn
);
1223 void spr_write_tar(DisasContext
*ctx
, int sprn
, int gprn
)
1225 gen_fscr_facility_check(ctx
, SPR_FSCR
, FSCR_TAR
, sprn
, FSCR_IC_TAR
);
1226 spr_write_generic(ctx
, sprn
, gprn
);
1229 void spr_read_tm(DisasContext
*ctx
, int gprn
, int sprn
)
1231 gen_msr_facility_check(ctx
, SPR_FSCR
, MSR_TM
, sprn
, FSCR_IC_TM
);
1232 spr_read_generic(ctx
, gprn
, sprn
);
1235 void spr_write_tm(DisasContext
*ctx
, int sprn
, int gprn
)
1237 gen_msr_facility_check(ctx
, SPR_FSCR
, MSR_TM
, sprn
, FSCR_IC_TM
);
1238 spr_write_generic(ctx
, sprn
, gprn
);
1241 void spr_read_tm_upper32(DisasContext
*ctx
, int gprn
, int sprn
)
1243 gen_msr_facility_check(ctx
, SPR_FSCR
, MSR_TM
, sprn
, FSCR_IC_TM
);
1244 spr_read_prev_upper32(ctx
, gprn
, sprn
);
1247 void spr_write_tm_upper32(DisasContext
*ctx
, int sprn
, int gprn
)
1249 gen_msr_facility_check(ctx
, SPR_FSCR
, MSR_TM
, sprn
, FSCR_IC_TM
);
1250 spr_write_prev_upper32(ctx
, sprn
, gprn
);
1253 void spr_read_ebb(DisasContext
*ctx
, int gprn
, int sprn
)
1255 gen_fscr_facility_check(ctx
, SPR_FSCR
, FSCR_EBB
, sprn
, FSCR_IC_EBB
);
1256 spr_read_generic(ctx
, gprn
, sprn
);
1259 void spr_write_ebb(DisasContext
*ctx
, int sprn
, int gprn
)
1261 gen_fscr_facility_check(ctx
, SPR_FSCR
, FSCR_EBB
, sprn
, FSCR_IC_EBB
);
1262 spr_write_generic(ctx
, sprn
, gprn
);
1265 void spr_read_ebb_upper32(DisasContext
*ctx
, int gprn
, int sprn
)
1267 gen_fscr_facility_check(ctx
, SPR_FSCR
, FSCR_EBB
, sprn
, FSCR_IC_EBB
);
1268 spr_read_prev_upper32(ctx
, gprn
, sprn
);
1271 void spr_write_ebb_upper32(DisasContext
*ctx
, int sprn
, int gprn
)
1273 gen_fscr_facility_check(ctx
, SPR_FSCR
, FSCR_EBB
, sprn
, FSCR_IC_EBB
);
1274 spr_write_prev_upper32(ctx
, sprn
, gprn
);
1278 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
1279 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
1281 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
1282 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
1284 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
1285 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
1287 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
1288 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
1290 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
1291 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
1293 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \
1294 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2)
1296 typedef struct opcode_t
{
1297 unsigned char opc1
, opc2
, opc3
, opc4
;
1298 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
1299 unsigned char pad
[4];
1301 opc_handler_t handler
;
1305 /* Helpers for priv. check */
1308 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
1311 #if defined(CONFIG_USER_ONLY)
1312 #define CHK_HV GEN_PRIV
1313 #define CHK_SV GEN_PRIV
1314 #define CHK_HVRM GEN_PRIV
1318 if (unlikely(ctx->pr || !ctx->hv)) { \
1324 if (unlikely(ctx->pr)) { \
1330 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
1338 /*****************************************************************************/
1339 /* PowerPC instructions table */
1341 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
1351 .handler = &gen_##name, \
1353 .oname = stringify(name), \
1355 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
1366 .handler = &gen_##name, \
1368 .oname = stringify(name), \
1370 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
1380 .handler = &gen_##name, \
1384 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
1394 .handler = &gen_##name, \
1396 .oname = stringify(name), \
1398 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
1408 .handler = &gen_##name, \
1413 /* Invalid instruction */
1414 static void gen_invalid(DisasContext
*ctx
)
1416 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
1419 static opc_handler_t invalid_handler
= {
1420 .inval1
= 0xFFFFFFFF,
1421 .inval2
= 0xFFFFFFFF,
1424 .handler
= gen_invalid
,
1427 /*** Integer comparison ***/
1429 static inline void gen_op_cmp(TCGv arg0
, TCGv arg1
, int s
, int crf
)
1431 TCGv t0
= tcg_temp_new();
1432 TCGv t1
= tcg_temp_new();
1433 TCGv_i32 t
= tcg_temp_new_i32();
1435 tcg_gen_movi_tl(t0
, CRF_EQ
);
1436 tcg_gen_movi_tl(t1
, CRF_LT
);
1437 tcg_gen_movcond_tl((s
? TCG_COND_LT
: TCG_COND_LTU
),
1438 t0
, arg0
, arg1
, t1
, t0
);
1439 tcg_gen_movi_tl(t1
, CRF_GT
);
1440 tcg_gen_movcond_tl((s
? TCG_COND_GT
: TCG_COND_GTU
),
1441 t0
, arg0
, arg1
, t1
, t0
);
1443 tcg_gen_trunc_tl_i32(t
, t0
);
1444 tcg_gen_trunc_tl_i32(cpu_crf
[crf
], cpu_so
);
1445 tcg_gen_or_i32(cpu_crf
[crf
], cpu_crf
[crf
], t
);
1449 tcg_temp_free_i32(t
);
1452 static inline void gen_op_cmpi(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
1454 TCGv t0
= tcg_const_tl(arg1
);
1455 gen_op_cmp(arg0
, t0
, s
, crf
);
1459 static inline void gen_op_cmp32(TCGv arg0
, TCGv arg1
, int s
, int crf
)
1462 t0
= tcg_temp_new();
1463 t1
= tcg_temp_new();
1465 tcg_gen_ext32s_tl(t0
, arg0
);
1466 tcg_gen_ext32s_tl(t1
, arg1
);
1468 tcg_gen_ext32u_tl(t0
, arg0
);
1469 tcg_gen_ext32u_tl(t1
, arg1
);
1471 gen_op_cmp(t0
, t1
, s
, crf
);
1476 static inline void gen_op_cmpi32(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
1478 TCGv t0
= tcg_const_tl(arg1
);
1479 gen_op_cmp32(arg0
, t0
, s
, crf
);
1483 static inline void gen_set_Rc0(DisasContext
*ctx
, TCGv reg
)
1485 if (NARROW_MODE(ctx
)) {
1486 gen_op_cmpi32(reg
, 0, 1, 0);
1488 gen_op_cmpi(reg
, 0, 1, 0);
1492 /* cmprb - range comparison: isupper, isaplha, islower*/
1493 static void gen_cmprb(DisasContext
*ctx
)
1495 TCGv_i32 src1
= tcg_temp_new_i32();
1496 TCGv_i32 src2
= tcg_temp_new_i32();
1497 TCGv_i32 src2lo
= tcg_temp_new_i32();
1498 TCGv_i32 src2hi
= tcg_temp_new_i32();
1499 TCGv_i32 crf
= cpu_crf
[crfD(ctx
->opcode
)];
1501 tcg_gen_trunc_tl_i32(src1
, cpu_gpr
[rA(ctx
->opcode
)]);
1502 tcg_gen_trunc_tl_i32(src2
, cpu_gpr
[rB(ctx
->opcode
)]);
1504 tcg_gen_andi_i32(src1
, src1
, 0xFF);
1505 tcg_gen_ext8u_i32(src2lo
, src2
);
1506 tcg_gen_shri_i32(src2
, src2
, 8);
1507 tcg_gen_ext8u_i32(src2hi
, src2
);
1509 tcg_gen_setcond_i32(TCG_COND_LEU
, src2lo
, src2lo
, src1
);
1510 tcg_gen_setcond_i32(TCG_COND_LEU
, src2hi
, src1
, src2hi
);
1511 tcg_gen_and_i32(crf
, src2lo
, src2hi
);
1513 if (ctx
->opcode
& 0x00200000) {
1514 tcg_gen_shri_i32(src2
, src2
, 8);
1515 tcg_gen_ext8u_i32(src2lo
, src2
);
1516 tcg_gen_shri_i32(src2
, src2
, 8);
1517 tcg_gen_ext8u_i32(src2hi
, src2
);
1518 tcg_gen_setcond_i32(TCG_COND_LEU
, src2lo
, src2lo
, src1
);
1519 tcg_gen_setcond_i32(TCG_COND_LEU
, src2hi
, src1
, src2hi
);
1520 tcg_gen_and_i32(src2lo
, src2lo
, src2hi
);
1521 tcg_gen_or_i32(crf
, crf
, src2lo
);
1523 tcg_gen_shli_i32(crf
, crf
, CRF_GT_BIT
);
1524 tcg_temp_free_i32(src1
);
1525 tcg_temp_free_i32(src2
);
1526 tcg_temp_free_i32(src2lo
);
1527 tcg_temp_free_i32(src2hi
);
1530 #if defined(TARGET_PPC64)
1532 static void gen_cmpeqb(DisasContext
*ctx
)
1534 gen_helper_cmpeqb(cpu_crf
[crfD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1535 cpu_gpr
[rB(ctx
->opcode
)]);
1539 /* isel (PowerPC 2.03 specification) */
1540 static void gen_isel(DisasContext
*ctx
)
1542 uint32_t bi
= rC(ctx
->opcode
);
1543 uint32_t mask
= 0x08 >> (bi
& 0x03);
1544 TCGv t0
= tcg_temp_new();
1547 tcg_gen_extu_i32_tl(t0
, cpu_crf
[bi
>> 2]);
1548 tcg_gen_andi_tl(t0
, t0
, mask
);
1550 zr
= tcg_const_tl(0);
1551 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_gpr
[rD(ctx
->opcode
)], t0
, zr
,
1552 rA(ctx
->opcode
) ? cpu_gpr
[rA(ctx
->opcode
)] : zr
,
1553 cpu_gpr
[rB(ctx
->opcode
)]);
1558 /* cmpb: PowerPC 2.05 specification */
1559 static void gen_cmpb(DisasContext
*ctx
)
1561 gen_helper_cmpb(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)],
1562 cpu_gpr
[rB(ctx
->opcode
)]);
1565 /*** Integer arithmetic ***/
1567 static inline void gen_op_arith_compute_ov(DisasContext
*ctx
, TCGv arg0
,
1568 TCGv arg1
, TCGv arg2
, int sub
)
1570 TCGv t0
= tcg_temp_new();
1572 tcg_gen_xor_tl(cpu_ov
, arg0
, arg2
);
1573 tcg_gen_xor_tl(t0
, arg1
, arg2
);
1575 tcg_gen_and_tl(cpu_ov
, cpu_ov
, t0
);
1577 tcg_gen_andc_tl(cpu_ov
, cpu_ov
, t0
);
1580 if (NARROW_MODE(ctx
)) {
1581 tcg_gen_extract_tl(cpu_ov
, cpu_ov
, 31, 1);
1582 if (is_isa300(ctx
)) {
1583 tcg_gen_mov_tl(cpu_ov32
, cpu_ov
);
1586 if (is_isa300(ctx
)) {
1587 tcg_gen_extract_tl(cpu_ov32
, cpu_ov
, 31, 1);
1589 tcg_gen_extract_tl(cpu_ov
, cpu_ov
, TARGET_LONG_BITS
- 1, 1);
1591 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1594 static inline void gen_op_arith_compute_ca32(DisasContext
*ctx
,
1595 TCGv res
, TCGv arg0
, TCGv arg1
,
1600 if (!is_isa300(ctx
)) {
1604 t0
= tcg_temp_new();
1606 tcg_gen_eqv_tl(t0
, arg0
, arg1
);
1608 tcg_gen_xor_tl(t0
, arg0
, arg1
);
1610 tcg_gen_xor_tl(t0
, t0
, res
);
1611 tcg_gen_extract_tl(ca32
, t0
, 32, 1);
1615 /* Common add function */
1616 static inline void gen_op_arith_add(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1617 TCGv arg2
, TCGv ca
, TCGv ca32
,
1618 bool add_ca
, bool compute_ca
,
1619 bool compute_ov
, bool compute_rc0
)
1623 if (compute_ca
|| compute_ov
) {
1624 t0
= tcg_temp_new();
1628 if (NARROW_MODE(ctx
)) {
1630 * Caution: a non-obvious corner case of the spec is that
1631 * we must produce the *entire* 64-bit addition, but
1632 * produce the carry into bit 32.
1634 TCGv t1
= tcg_temp_new();
1635 tcg_gen_xor_tl(t1
, arg1
, arg2
); /* add without carry */
1636 tcg_gen_add_tl(t0
, arg1
, arg2
);
1638 tcg_gen_add_tl(t0
, t0
, ca
);
1640 tcg_gen_xor_tl(ca
, t0
, t1
); /* bits changed w/ carry */
1642 tcg_gen_extract_tl(ca
, ca
, 32, 1);
1643 if (is_isa300(ctx
)) {
1644 tcg_gen_mov_tl(ca32
, ca
);
1647 TCGv zero
= tcg_const_tl(0);
1649 tcg_gen_add2_tl(t0
, ca
, arg1
, zero
, ca
, zero
);
1650 tcg_gen_add2_tl(t0
, ca
, t0
, ca
, arg2
, zero
);
1652 tcg_gen_add2_tl(t0
, ca
, arg1
, zero
, arg2
, zero
);
1654 gen_op_arith_compute_ca32(ctx
, t0
, arg1
, arg2
, ca32
, 0);
1655 tcg_temp_free(zero
);
1658 tcg_gen_add_tl(t0
, arg1
, arg2
);
1660 tcg_gen_add_tl(t0
, t0
, ca
);
1665 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 0);
1667 if (unlikely(compute_rc0
)) {
1668 gen_set_Rc0(ctx
, t0
);
1672 tcg_gen_mov_tl(ret
, t0
);
1676 /* Add functions with two operands */
1677 #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \
1678 static void glue(gen_, name)(DisasContext *ctx) \
1680 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
1681 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1683 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1685 /* Add functions with one operand and one immediate */
1686 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \
1687 add_ca, compute_ca, compute_ov) \
1688 static void glue(gen_, name)(DisasContext *ctx) \
1690 TCGv t0 = tcg_const_tl(const_val); \
1691 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
1692 cpu_gpr[rA(ctx->opcode)], t0, \
1694 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1695 tcg_temp_free(t0); \
1698 /* add add. addo addo. */
1699 GEN_INT_ARITH_ADD(add
, 0x08, cpu_ca
, 0, 0, 0)
1700 GEN_INT_ARITH_ADD(addo
, 0x18, cpu_ca
, 0, 0, 1)
1701 /* addc addc. addco addco. */
1702 GEN_INT_ARITH_ADD(addc
, 0x00, cpu_ca
, 0, 1, 0)
1703 GEN_INT_ARITH_ADD(addco
, 0x10, cpu_ca
, 0, 1, 1)
1704 /* adde adde. addeo addeo. */
1705 GEN_INT_ARITH_ADD(adde
, 0x04, cpu_ca
, 1, 1, 0)
1706 GEN_INT_ARITH_ADD(addeo
, 0x14, cpu_ca
, 1, 1, 1)
1707 /* addme addme. addmeo addmeo. */
1708 GEN_INT_ARITH_ADD_CONST(addme
, 0x07, -1LL, cpu_ca
, 1, 1, 0)
1709 GEN_INT_ARITH_ADD_CONST(addmeo
, 0x17, -1LL, cpu_ca
, 1, 1, 1)
1711 GEN_INT_ARITH_ADD(addex
, 0x05, cpu_ov
, 1, 1, 0);
1712 /* addze addze. addzeo addzeo.*/
1713 GEN_INT_ARITH_ADD_CONST(addze
, 0x06, 0, cpu_ca
, 1, 1, 0)
1714 GEN_INT_ARITH_ADD_CONST(addzeo
, 0x16, 0, cpu_ca
, 1, 1, 1)
1716 static inline void gen_op_addic(DisasContext
*ctx
, bool compute_rc0
)
1718 TCGv c
= tcg_const_tl(SIMM(ctx
->opcode
));
1719 gen_op_arith_add(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1720 c
, cpu_ca
, cpu_ca32
, 0, 1, 0, compute_rc0
);
1724 static void gen_addic(DisasContext
*ctx
)
1726 gen_op_addic(ctx
, 0);
1729 static void gen_addic_(DisasContext
*ctx
)
1731 gen_op_addic(ctx
, 1);
1734 static inline void gen_op_arith_divw(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1735 TCGv arg2
, int sign
, int compute_ov
)
1737 TCGv_i32 t0
= tcg_temp_new_i32();
1738 TCGv_i32 t1
= tcg_temp_new_i32();
1739 TCGv_i32 t2
= tcg_temp_new_i32();
1740 TCGv_i32 t3
= tcg_temp_new_i32();
1742 tcg_gen_trunc_tl_i32(t0
, arg1
);
1743 tcg_gen_trunc_tl_i32(t1
, arg2
);
1745 tcg_gen_setcondi_i32(TCG_COND_EQ
, t2
, t0
, INT_MIN
);
1746 tcg_gen_setcondi_i32(TCG_COND_EQ
, t3
, t1
, -1);
1747 tcg_gen_and_i32(t2
, t2
, t3
);
1748 tcg_gen_setcondi_i32(TCG_COND_EQ
, t3
, t1
, 0);
1749 tcg_gen_or_i32(t2
, t2
, t3
);
1750 tcg_gen_movi_i32(t3
, 0);
1751 tcg_gen_movcond_i32(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1752 tcg_gen_div_i32(t3
, t0
, t1
);
1753 tcg_gen_extu_i32_tl(ret
, t3
);
1755 tcg_gen_setcondi_i32(TCG_COND_EQ
, t2
, t1
, 0);
1756 tcg_gen_movi_i32(t3
, 0);
1757 tcg_gen_movcond_i32(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1758 tcg_gen_divu_i32(t3
, t0
, t1
);
1759 tcg_gen_extu_i32_tl(ret
, t3
);
1762 tcg_gen_extu_i32_tl(cpu_ov
, t2
);
1763 if (is_isa300(ctx
)) {
1764 tcg_gen_extu_i32_tl(cpu_ov32
, t2
);
1766 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1768 tcg_temp_free_i32(t0
);
1769 tcg_temp_free_i32(t1
);
1770 tcg_temp_free_i32(t2
);
1771 tcg_temp_free_i32(t3
);
1773 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1774 gen_set_Rc0(ctx
, ret
);
1778 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1779 static void glue(gen_, name)(DisasContext *ctx) \
1781 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1782 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1783 sign, compute_ov); \
1785 /* divwu divwu. divwuo divwuo. */
1786 GEN_INT_ARITH_DIVW(divwu
, 0x0E, 0, 0);
1787 GEN_INT_ARITH_DIVW(divwuo
, 0x1E, 0, 1);
1788 /* divw divw. divwo divwo. */
1789 GEN_INT_ARITH_DIVW(divw
, 0x0F, 1, 0);
1790 GEN_INT_ARITH_DIVW(divwo
, 0x1F, 1, 1);
1792 /* div[wd]eu[o][.] */
1793 #define GEN_DIVE(name, hlpr, compute_ov) \
1794 static void gen_##name(DisasContext *ctx) \
1796 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1797 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1798 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1799 tcg_temp_free_i32(t0); \
1800 if (unlikely(Rc(ctx->opcode) != 0)) { \
1801 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1805 GEN_DIVE(divweu
, divweu
, 0);
1806 GEN_DIVE(divweuo
, divweu
, 1);
1807 GEN_DIVE(divwe
, divwe
, 0);
1808 GEN_DIVE(divweo
, divwe
, 1);
1810 #if defined(TARGET_PPC64)
1811 static inline void gen_op_arith_divd(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1812 TCGv arg2
, int sign
, int compute_ov
)
1814 TCGv_i64 t0
= tcg_temp_new_i64();
1815 TCGv_i64 t1
= tcg_temp_new_i64();
1816 TCGv_i64 t2
= tcg_temp_new_i64();
1817 TCGv_i64 t3
= tcg_temp_new_i64();
1819 tcg_gen_mov_i64(t0
, arg1
);
1820 tcg_gen_mov_i64(t1
, arg2
);
1822 tcg_gen_setcondi_i64(TCG_COND_EQ
, t2
, t0
, INT64_MIN
);
1823 tcg_gen_setcondi_i64(TCG_COND_EQ
, t3
, t1
, -1);
1824 tcg_gen_and_i64(t2
, t2
, t3
);
1825 tcg_gen_setcondi_i64(TCG_COND_EQ
, t3
, t1
, 0);
1826 tcg_gen_or_i64(t2
, t2
, t3
);
1827 tcg_gen_movi_i64(t3
, 0);
1828 tcg_gen_movcond_i64(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1829 tcg_gen_div_i64(ret
, t0
, t1
);
1831 tcg_gen_setcondi_i64(TCG_COND_EQ
, t2
, t1
, 0);
1832 tcg_gen_movi_i64(t3
, 0);
1833 tcg_gen_movcond_i64(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1834 tcg_gen_divu_i64(ret
, t0
, t1
);
1837 tcg_gen_mov_tl(cpu_ov
, t2
);
1838 if (is_isa300(ctx
)) {
1839 tcg_gen_mov_tl(cpu_ov32
, t2
);
1841 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1843 tcg_temp_free_i64(t0
);
1844 tcg_temp_free_i64(t1
);
1845 tcg_temp_free_i64(t2
);
1846 tcg_temp_free_i64(t3
);
1848 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1849 gen_set_Rc0(ctx
, ret
);
1853 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1854 static void glue(gen_, name)(DisasContext *ctx) \
1856 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1857 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1858 sign, compute_ov); \
1860 /* divdu divdu. divduo divduo. */
1861 GEN_INT_ARITH_DIVD(divdu
, 0x0E, 0, 0);
1862 GEN_INT_ARITH_DIVD(divduo
, 0x1E, 0, 1);
1863 /* divd divd. divdo divdo. */
1864 GEN_INT_ARITH_DIVD(divd
, 0x0F, 1, 0);
1865 GEN_INT_ARITH_DIVD(divdo
, 0x1F, 1, 1);
1867 GEN_DIVE(divdeu
, divdeu
, 0);
1868 GEN_DIVE(divdeuo
, divdeu
, 1);
1869 GEN_DIVE(divde
, divde
, 0);
1870 GEN_DIVE(divdeo
, divde
, 1);
1873 static inline void gen_op_arith_modw(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1874 TCGv arg2
, int sign
)
1876 TCGv_i32 t0
= tcg_temp_new_i32();
1877 TCGv_i32 t1
= tcg_temp_new_i32();
1879 tcg_gen_trunc_tl_i32(t0
, arg1
);
1880 tcg_gen_trunc_tl_i32(t1
, arg2
);
1882 TCGv_i32 t2
= tcg_temp_new_i32();
1883 TCGv_i32 t3
= tcg_temp_new_i32();
1884 tcg_gen_setcondi_i32(TCG_COND_EQ
, t2
, t0
, INT_MIN
);
1885 tcg_gen_setcondi_i32(TCG_COND_EQ
, t3
, t1
, -1);
1886 tcg_gen_and_i32(t2
, t2
, t3
);
1887 tcg_gen_setcondi_i32(TCG_COND_EQ
, t3
, t1
, 0);
1888 tcg_gen_or_i32(t2
, t2
, t3
);
1889 tcg_gen_movi_i32(t3
, 0);
1890 tcg_gen_movcond_i32(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1891 tcg_gen_rem_i32(t3
, t0
, t1
);
1892 tcg_gen_ext_i32_tl(ret
, t3
);
1893 tcg_temp_free_i32(t2
);
1894 tcg_temp_free_i32(t3
);
1896 TCGv_i32 t2
= tcg_const_i32(1);
1897 TCGv_i32 t3
= tcg_const_i32(0);
1898 tcg_gen_movcond_i32(TCG_COND_EQ
, t1
, t1
, t3
, t2
, t1
);
1899 tcg_gen_remu_i32(t3
, t0
, t1
);
1900 tcg_gen_extu_i32_tl(ret
, t3
);
1901 tcg_temp_free_i32(t2
);
1902 tcg_temp_free_i32(t3
);
1904 tcg_temp_free_i32(t0
);
1905 tcg_temp_free_i32(t1
);
1908 #define GEN_INT_ARITH_MODW(name, opc3, sign) \
1909 static void glue(gen_, name)(DisasContext *ctx) \
1911 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
1912 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1916 GEN_INT_ARITH_MODW(moduw
, 0x08, 0);
1917 GEN_INT_ARITH_MODW(modsw
, 0x18, 1);
1919 #if defined(TARGET_PPC64)
1920 static inline void gen_op_arith_modd(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1921 TCGv arg2
, int sign
)
1923 TCGv_i64 t0
= tcg_temp_new_i64();
1924 TCGv_i64 t1
= tcg_temp_new_i64();
1926 tcg_gen_mov_i64(t0
, arg1
);
1927 tcg_gen_mov_i64(t1
, arg2
);
1929 TCGv_i64 t2
= tcg_temp_new_i64();
1930 TCGv_i64 t3
= tcg_temp_new_i64();
1931 tcg_gen_setcondi_i64(TCG_COND_EQ
, t2
, t0
, INT64_MIN
);
1932 tcg_gen_setcondi_i64(TCG_COND_EQ
, t3
, t1
, -1);
1933 tcg_gen_and_i64(t2
, t2
, t3
);
1934 tcg_gen_setcondi_i64(TCG_COND_EQ
, t3
, t1
, 0);
1935 tcg_gen_or_i64(t2
, t2
, t3
);
1936 tcg_gen_movi_i64(t3
, 0);
1937 tcg_gen_movcond_i64(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1938 tcg_gen_rem_i64(ret
, t0
, t1
);
1939 tcg_temp_free_i64(t2
);
1940 tcg_temp_free_i64(t3
);
1942 TCGv_i64 t2
= tcg_const_i64(1);
1943 TCGv_i64 t3
= tcg_const_i64(0);
1944 tcg_gen_movcond_i64(TCG_COND_EQ
, t1
, t1
, t3
, t2
, t1
);
1945 tcg_gen_remu_i64(ret
, t0
, t1
);
1946 tcg_temp_free_i64(t2
);
1947 tcg_temp_free_i64(t3
);
1949 tcg_temp_free_i64(t0
);
1950 tcg_temp_free_i64(t1
);
1953 #define GEN_INT_ARITH_MODD(name, opc3, sign) \
1954 static void glue(gen_, name)(DisasContext *ctx) \
1956 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
1957 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1961 GEN_INT_ARITH_MODD(modud
, 0x08, 0);
1962 GEN_INT_ARITH_MODD(modsd
, 0x18, 1);
1966 static void gen_mulhw(DisasContext
*ctx
)
1968 TCGv_i32 t0
= tcg_temp_new_i32();
1969 TCGv_i32 t1
= tcg_temp_new_i32();
1971 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1972 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1973 tcg_gen_muls2_i32(t0
, t1
, t0
, t1
);
1974 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
1975 tcg_temp_free_i32(t0
);
1976 tcg_temp_free_i32(t1
);
1977 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1978 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1982 /* mulhwu mulhwu. */
1983 static void gen_mulhwu(DisasContext
*ctx
)
1985 TCGv_i32 t0
= tcg_temp_new_i32();
1986 TCGv_i32 t1
= tcg_temp_new_i32();
1988 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1989 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1990 tcg_gen_mulu2_i32(t0
, t1
, t0
, t1
);
1991 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
1992 tcg_temp_free_i32(t0
);
1993 tcg_temp_free_i32(t1
);
1994 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1995 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
2000 static void gen_mullw(DisasContext
*ctx
)
2002 #if defined(TARGET_PPC64)
2004 t0
= tcg_temp_new_i64();
2005 t1
= tcg_temp_new_i64();
2006 tcg_gen_ext32s_tl(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
2007 tcg_gen_ext32s_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
2008 tcg_gen_mul_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
2012 tcg_gen_mul_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
2013 cpu_gpr
[rB(ctx
->opcode
)]);
2015 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2016 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
2020 /* mullwo mullwo. */
2021 static void gen_mullwo(DisasContext
*ctx
)
2023 TCGv_i32 t0
= tcg_temp_new_i32();
2024 TCGv_i32 t1
= tcg_temp_new_i32();
2026 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
2027 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
2028 tcg_gen_muls2_i32(t0
, t1
, t0
, t1
);
2029 #if defined(TARGET_PPC64)
2030 tcg_gen_concat_i32_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
2032 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], t0
);
2035 tcg_gen_sari_i32(t0
, t0
, 31);
2036 tcg_gen_setcond_i32(TCG_COND_NE
, t0
, t0
, t1
);
2037 tcg_gen_extu_i32_tl(cpu_ov
, t0
);
2038 if (is_isa300(ctx
)) {
2039 tcg_gen_mov_tl(cpu_ov32
, cpu_ov
);
2041 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
2043 tcg_temp_free_i32(t0
);
2044 tcg_temp_free_i32(t1
);
2045 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2046 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
2051 static void gen_mulli(DisasContext
*ctx
)
2053 tcg_gen_muli_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
2057 #if defined(TARGET_PPC64)
2059 static void gen_mulhd(DisasContext
*ctx
)
2061 TCGv lo
= tcg_temp_new();
2062 tcg_gen_muls2_tl(lo
, cpu_gpr
[rD(ctx
->opcode
)],
2063 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2065 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2066 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
2070 /* mulhdu mulhdu. */
2071 static void gen_mulhdu(DisasContext
*ctx
)
2073 TCGv lo
= tcg_temp_new();
2074 tcg_gen_mulu2_tl(lo
, cpu_gpr
[rD(ctx
->opcode
)],
2075 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2077 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2078 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
2083 static void gen_mulld(DisasContext
*ctx
)
2085 tcg_gen_mul_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
2086 cpu_gpr
[rB(ctx
->opcode
)]);
2087 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2088 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
2092 /* mulldo mulldo. */
2093 static void gen_mulldo(DisasContext
*ctx
)
2095 TCGv_i64 t0
= tcg_temp_new_i64();
2096 TCGv_i64 t1
= tcg_temp_new_i64();
2098 tcg_gen_muls2_i64(t0
, t1
, cpu_gpr
[rA(ctx
->opcode
)],
2099 cpu_gpr
[rB(ctx
->opcode
)]);
2100 tcg_gen_mov_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
);
2102 tcg_gen_sari_i64(t0
, t0
, 63);
2103 tcg_gen_setcond_i64(TCG_COND_NE
, cpu_ov
, t0
, t1
);
2104 if (is_isa300(ctx
)) {
2105 tcg_gen_mov_tl(cpu_ov32
, cpu_ov
);
2107 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
2109 tcg_temp_free_i64(t0
);
2110 tcg_temp_free_i64(t1
);
2112 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2113 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
2118 /* Common subf function */
2119 static inline void gen_op_arith_subf(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
2120 TCGv arg2
, bool add_ca
, bool compute_ca
,
2121 bool compute_ov
, bool compute_rc0
)
2125 if (compute_ca
|| compute_ov
) {
2126 t0
= tcg_temp_new();
2130 /* dest = ~arg1 + arg2 [+ ca]. */
2131 if (NARROW_MODE(ctx
)) {
2133 * Caution: a non-obvious corner case of the spec is that
2134 * we must produce the *entire* 64-bit addition, but
2135 * produce the carry into bit 32.
2137 TCGv inv1
= tcg_temp_new();
2138 TCGv t1
= tcg_temp_new();
2139 tcg_gen_not_tl(inv1
, arg1
);
2141 tcg_gen_add_tl(t0
, arg2
, cpu_ca
);
2143 tcg_gen_addi_tl(t0
, arg2
, 1);
2145 tcg_gen_xor_tl(t1
, arg2
, inv1
); /* add without carry */
2146 tcg_gen_add_tl(t0
, t0
, inv1
);
2147 tcg_temp_free(inv1
);
2148 tcg_gen_xor_tl(cpu_ca
, t0
, t1
); /* bits changes w/ carry */
2150 tcg_gen_extract_tl(cpu_ca
, cpu_ca
, 32, 1);
2151 if (is_isa300(ctx
)) {
2152 tcg_gen_mov_tl(cpu_ca32
, cpu_ca
);
2154 } else if (add_ca
) {
2155 TCGv zero
, inv1
= tcg_temp_new();
2156 tcg_gen_not_tl(inv1
, arg1
);
2157 zero
= tcg_const_tl(0);
2158 tcg_gen_add2_tl(t0
, cpu_ca
, arg2
, zero
, cpu_ca
, zero
);
2159 tcg_gen_add2_tl(t0
, cpu_ca
, t0
, cpu_ca
, inv1
, zero
);
2160 gen_op_arith_compute_ca32(ctx
, t0
, inv1
, arg2
, cpu_ca32
, 0);
2161 tcg_temp_free(zero
);
2162 tcg_temp_free(inv1
);
2164 tcg_gen_setcond_tl(TCG_COND_GEU
, cpu_ca
, arg2
, arg1
);
2165 tcg_gen_sub_tl(t0
, arg2
, arg1
);
2166 gen_op_arith_compute_ca32(ctx
, t0
, arg1
, arg2
, cpu_ca32
, 1);
2168 } else if (add_ca
) {
2170 * Since we're ignoring carry-out, we can simplify the
2171 * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1.
2173 tcg_gen_sub_tl(t0
, arg2
, arg1
);
2174 tcg_gen_add_tl(t0
, t0
, cpu_ca
);
2175 tcg_gen_subi_tl(t0
, t0
, 1);
2177 tcg_gen_sub_tl(t0
, arg2
, arg1
);
2181 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 1);
2183 if (unlikely(compute_rc0
)) {
2184 gen_set_Rc0(ctx
, t0
);
2188 tcg_gen_mov_tl(ret
, t0
);
2192 /* Sub functions with Two operands functions */
2193 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
2194 static void glue(gen_, name)(DisasContext *ctx) \
2196 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
2197 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
2198 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
2200 /* Sub functions with one operand and one immediate */
2201 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
2202 add_ca, compute_ca, compute_ov) \
2203 static void glue(gen_, name)(DisasContext *ctx) \
2205 TCGv t0 = tcg_const_tl(const_val); \
2206 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
2207 cpu_gpr[rA(ctx->opcode)], t0, \
2208 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
2209 tcg_temp_free(t0); \
2211 /* subf subf. subfo subfo. */
2212 GEN_INT_ARITH_SUBF(subf
, 0x01, 0, 0, 0)
2213 GEN_INT_ARITH_SUBF(subfo
, 0x11, 0, 0, 1)
2214 /* subfc subfc. subfco subfco. */
2215 GEN_INT_ARITH_SUBF(subfc
, 0x00, 0, 1, 0)
2216 GEN_INT_ARITH_SUBF(subfco
, 0x10, 0, 1, 1)
2217 /* subfe subfe. subfeo subfo. */
2218 GEN_INT_ARITH_SUBF(subfe
, 0x04, 1, 1, 0)
2219 GEN_INT_ARITH_SUBF(subfeo
, 0x14, 1, 1, 1)
2220 /* subfme subfme. subfmeo subfmeo. */
2221 GEN_INT_ARITH_SUBF_CONST(subfme
, 0x07, -1LL, 1, 1, 0)
2222 GEN_INT_ARITH_SUBF_CONST(subfmeo
, 0x17, -1LL, 1, 1, 1)
2223 /* subfze subfze. subfzeo subfzeo.*/
2224 GEN_INT_ARITH_SUBF_CONST(subfze
, 0x06, 0, 1, 1, 0)
2225 GEN_INT_ARITH_SUBF_CONST(subfzeo
, 0x16, 0, 1, 1, 1)
2228 static void gen_subfic(DisasContext
*ctx
)
2230 TCGv c
= tcg_const_tl(SIMM(ctx
->opcode
));
2231 gen_op_arith_subf(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
2236 /* neg neg. nego nego. */
2237 static inline void gen_op_arith_neg(DisasContext
*ctx
, bool compute_ov
)
2239 TCGv zero
= tcg_const_tl(0);
2240 gen_op_arith_subf(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
2241 zero
, 0, 0, compute_ov
, Rc(ctx
->opcode
));
2242 tcg_temp_free(zero
);
2245 static void gen_neg(DisasContext
*ctx
)
2247 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
2248 if (unlikely(Rc(ctx
->opcode
))) {
2249 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
2253 static void gen_nego(DisasContext
*ctx
)
2255 gen_op_arith_neg(ctx
, 1);
2258 /*** Integer logical ***/
2259 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
2260 static void glue(gen_, name)(DisasContext *ctx) \
2262 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
2263 cpu_gpr[rB(ctx->opcode)]); \
2264 if (unlikely(Rc(ctx->opcode) != 0)) \
2265 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
2268 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
2269 static void glue(gen_, name)(DisasContext *ctx) \
2271 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
2272 if (unlikely(Rc(ctx->opcode) != 0)) \
2273 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
2277 GEN_LOGICAL2(and, tcg_gen_and_tl
, 0x00, PPC_INTEGER
);
2279 GEN_LOGICAL2(andc
, tcg_gen_andc_tl
, 0x01, PPC_INTEGER
);
2282 static void gen_andi_(DisasContext
*ctx
)
2284 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)],
2286 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2290 static void gen_andis_(DisasContext
*ctx
)
2292 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)],
2293 UIMM(ctx
->opcode
) << 16);
2294 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2298 static void gen_cntlzw(DisasContext
*ctx
)
2300 TCGv_i32 t
= tcg_temp_new_i32();
2302 tcg_gen_trunc_tl_i32(t
, cpu_gpr
[rS(ctx
->opcode
)]);
2303 tcg_gen_clzi_i32(t
, t
, 32);
2304 tcg_gen_extu_i32_tl(cpu_gpr
[rA(ctx
->opcode
)], t
);
2305 tcg_temp_free_i32(t
);
2307 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2308 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2313 static void gen_cnttzw(DisasContext
*ctx
)
2315 TCGv_i32 t
= tcg_temp_new_i32();
2317 tcg_gen_trunc_tl_i32(t
, cpu_gpr
[rS(ctx
->opcode
)]);
2318 tcg_gen_ctzi_i32(t
, t
, 32);
2319 tcg_gen_extu_i32_tl(cpu_gpr
[rA(ctx
->opcode
)], t
);
2320 tcg_temp_free_i32(t
);
2322 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2323 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2328 GEN_LOGICAL2(eqv
, tcg_gen_eqv_tl
, 0x08, PPC_INTEGER
);
2329 /* extsb & extsb. */
2330 GEN_LOGICAL1(extsb
, tcg_gen_ext8s_tl
, 0x1D, PPC_INTEGER
);
2331 /* extsh & extsh. */
2332 GEN_LOGICAL1(extsh
, tcg_gen_ext16s_tl
, 0x1C, PPC_INTEGER
);
2334 GEN_LOGICAL2(nand
, tcg_gen_nand_tl
, 0x0E, PPC_INTEGER
);
2336 GEN_LOGICAL2(nor
, tcg_gen_nor_tl
, 0x03, PPC_INTEGER
);
2338 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
2339 static void gen_pause(DisasContext
*ctx
)
2341 TCGv_i32 t0
= tcg_const_i32(0);
2342 tcg_gen_st_i32(t0
, cpu_env
,
2343 -offsetof(PowerPCCPU
, env
) + offsetof(CPUState
, halted
));
2344 tcg_temp_free_i32(t0
);
2346 /* Stop translation, this gives other CPUs a chance to run */
2347 gen_exception_nip(ctx
, EXCP_HLT
, ctx
->base
.pc_next
);
2349 #endif /* defined(TARGET_PPC64) */
2352 static void gen_or(DisasContext
*ctx
)
2356 rs
= rS(ctx
->opcode
);
2357 ra
= rA(ctx
->opcode
);
2358 rb
= rB(ctx
->opcode
);
2359 /* Optimisation for mr. ri case */
2360 if (rs
!= ra
|| rs
!= rb
) {
2362 tcg_gen_or_tl(cpu_gpr
[ra
], cpu_gpr
[rs
], cpu_gpr
[rb
]);
2364 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rs
]);
2366 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2367 gen_set_Rc0(ctx
, cpu_gpr
[ra
]);
2369 } else if (unlikely(Rc(ctx
->opcode
) != 0)) {
2370 gen_set_Rc0(ctx
, cpu_gpr
[rs
]);
2371 #if defined(TARGET_PPC64)
2372 } else if (rs
!= 0) { /* 0 is nop */
2377 /* Set process priority to low */
2381 /* Set process priority to medium-low */
2385 /* Set process priority to normal */
2388 #if !defined(CONFIG_USER_ONLY)
2391 /* Set process priority to very low */
2397 /* Set process priority to medium-hight */
2403 /* Set process priority to high */
2408 if (ctx
->hv
&& !ctx
->pr
) {
2409 /* Set process priority to very high */
2418 TCGv t0
= tcg_temp_new();
2419 gen_load_spr(t0
, SPR_PPR
);
2420 tcg_gen_andi_tl(t0
, t0
, ~0x001C000000000000ULL
);
2421 tcg_gen_ori_tl(t0
, t0
, ((uint64_t)prio
) << 50);
2422 gen_store_spr(SPR_PPR
, t0
);
2425 #if !defined(CONFIG_USER_ONLY)
2427 * Pause out of TCG otherwise spin loops with smt_low eat too
2428 * much CPU and the kernel hangs. This applies to all
2429 * encodings other than no-op, e.g., miso(rs=26), yield(27),
2430 * mdoio(29), mdoom(30), and all currently undefined.
2438 GEN_LOGICAL2(orc
, tcg_gen_orc_tl
, 0x0C, PPC_INTEGER
);
2441 static void gen_xor(DisasContext
*ctx
)
2443 /* Optimisation for "set to zero" case */
2444 if (rS(ctx
->opcode
) != rB(ctx
->opcode
)) {
2445 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)],
2446 cpu_gpr
[rB(ctx
->opcode
)]);
2448 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
2450 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2451 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2456 static void gen_ori(DisasContext
*ctx
)
2458 target_ulong uimm
= UIMM(ctx
->opcode
);
2460 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
2463 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
2467 static void gen_oris(DisasContext
*ctx
)
2469 target_ulong uimm
= UIMM(ctx
->opcode
);
2471 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
2475 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)],
2480 static void gen_xori(DisasContext
*ctx
)
2482 target_ulong uimm
= UIMM(ctx
->opcode
);
2484 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
2488 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
2492 static void gen_xoris(DisasContext
*ctx
)
2494 target_ulong uimm
= UIMM(ctx
->opcode
);
2496 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
2500 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)],
2504 /* popcntb : PowerPC 2.03 specification */
2505 static void gen_popcntb(DisasContext
*ctx
)
2507 gen_helper_popcntb(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
2510 static void gen_popcntw(DisasContext
*ctx
)
2512 #if defined(TARGET_PPC64)
2513 gen_helper_popcntw(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
2515 tcg_gen_ctpop_i32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
2519 #if defined(TARGET_PPC64)
2520 /* popcntd: PowerPC 2.06 specification */
2521 static void gen_popcntd(DisasContext
*ctx
)
2523 tcg_gen_ctpop_i64(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
2527 /* prtyw: PowerPC 2.05 specification */
2528 static void gen_prtyw(DisasContext
*ctx
)
2530 TCGv ra
= cpu_gpr
[rA(ctx
->opcode
)];
2531 TCGv rs
= cpu_gpr
[rS(ctx
->opcode
)];
2532 TCGv t0
= tcg_temp_new();
2533 tcg_gen_shri_tl(t0
, rs
, 16);
2534 tcg_gen_xor_tl(ra
, rs
, t0
);
2535 tcg_gen_shri_tl(t0
, ra
, 8);
2536 tcg_gen_xor_tl(ra
, ra
, t0
);
2537 tcg_gen_andi_tl(ra
, ra
, (target_ulong
)0x100000001ULL
);
2541 #if defined(TARGET_PPC64)
2542 /* prtyd: PowerPC 2.05 specification */
2543 static void gen_prtyd(DisasContext
*ctx
)
2545 TCGv ra
= cpu_gpr
[rA(ctx
->opcode
)];
2546 TCGv rs
= cpu_gpr
[rS(ctx
->opcode
)];
2547 TCGv t0
= tcg_temp_new();
2548 tcg_gen_shri_tl(t0
, rs
, 32);
2549 tcg_gen_xor_tl(ra
, rs
, t0
);
2550 tcg_gen_shri_tl(t0
, ra
, 16);
2551 tcg_gen_xor_tl(ra
, ra
, t0
);
2552 tcg_gen_shri_tl(t0
, ra
, 8);
2553 tcg_gen_xor_tl(ra
, ra
, t0
);
2554 tcg_gen_andi_tl(ra
, ra
, 1);
2559 #if defined(TARGET_PPC64)
2561 static void gen_bpermd(DisasContext
*ctx
)
2563 gen_helper_bpermd(cpu_gpr
[rA(ctx
->opcode
)],
2564 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2568 #if defined(TARGET_PPC64)
2569 /* extsw & extsw. */
2570 GEN_LOGICAL1(extsw
, tcg_gen_ext32s_tl
, 0x1E, PPC_64B
);
2573 static void gen_cntlzd(DisasContext
*ctx
)
2575 tcg_gen_clzi_i64(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], 64);
2576 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2577 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2582 static void gen_cnttzd(DisasContext
*ctx
)
2584 tcg_gen_ctzi_i64(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], 64);
2585 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2586 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2591 static void gen_darn(DisasContext
*ctx
)
2593 int l
= L(ctx
->opcode
);
2596 tcg_gen_movi_i64(cpu_gpr
[rD(ctx
->opcode
)], -1);
2598 gen_icount_io_start(ctx
);
2600 gen_helper_darn32(cpu_gpr
[rD(ctx
->opcode
)]);
2602 /* Return 64-bit random for both CRN and RRN */
2603 gen_helper_darn64(cpu_gpr
[rD(ctx
->opcode
)]);
2609 /*** Integer rotate ***/
2611 /* rlwimi & rlwimi. */
2612 static void gen_rlwimi(DisasContext
*ctx
)
2614 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
2615 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
2616 uint32_t sh
= SH(ctx
->opcode
);
2617 uint32_t mb
= MB(ctx
->opcode
);
2618 uint32_t me
= ME(ctx
->opcode
);
2620 if (sh
== (31 - me
) && mb
<= me
) {
2621 tcg_gen_deposit_tl(t_ra
, t_ra
, t_rs
, sh
, me
- mb
+ 1);
2624 bool mask_in_32b
= true;
2627 #if defined(TARGET_PPC64)
2631 mask
= MASK(mb
, me
);
2633 #if defined(TARGET_PPC64)
2634 if (mask
> 0xffffffffu
) {
2635 mask_in_32b
= false;
2638 t1
= tcg_temp_new();
2640 TCGv_i32 t0
= tcg_temp_new_i32();
2641 tcg_gen_trunc_tl_i32(t0
, t_rs
);
2642 tcg_gen_rotli_i32(t0
, t0
, sh
);
2643 tcg_gen_extu_i32_tl(t1
, t0
);
2644 tcg_temp_free_i32(t0
);
2646 #if defined(TARGET_PPC64)
2647 tcg_gen_deposit_i64(t1
, t_rs
, t_rs
, 32, 32);
2648 tcg_gen_rotli_i64(t1
, t1
, sh
);
2650 g_assert_not_reached();
2654 tcg_gen_andi_tl(t1
, t1
, mask
);
2655 tcg_gen_andi_tl(t_ra
, t_ra
, ~mask
);
2656 tcg_gen_or_tl(t_ra
, t_ra
, t1
);
2659 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2660 gen_set_Rc0(ctx
, t_ra
);
2664 /* rlwinm & rlwinm. */
2665 static void gen_rlwinm(DisasContext
*ctx
)
2667 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
2668 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
2669 int sh
= SH(ctx
->opcode
);
2670 int mb
= MB(ctx
->opcode
);
2671 int me
= ME(ctx
->opcode
);
2672 int len
= me
- mb
+ 1;
2673 int rsh
= (32 - sh
) & 31;
2675 if (sh
!= 0 && len
> 0 && me
== (31 - sh
)) {
2676 tcg_gen_deposit_z_tl(t_ra
, t_rs
, sh
, len
);
2677 } else if (me
== 31 && rsh
+ len
<= 32) {
2678 tcg_gen_extract_tl(t_ra
, t_rs
, rsh
, len
);
2681 bool mask_in_32b
= true;
2682 #if defined(TARGET_PPC64)
2686 mask
= MASK(mb
, me
);
2687 #if defined(TARGET_PPC64)
2688 if (mask
> 0xffffffffu
) {
2689 mask_in_32b
= false;
2694 tcg_gen_andi_tl(t_ra
, t_rs
, mask
);
2696 TCGv_i32 t0
= tcg_temp_new_i32();
2697 tcg_gen_trunc_tl_i32(t0
, t_rs
);
2698 tcg_gen_rotli_i32(t0
, t0
, sh
);
2699 tcg_gen_andi_i32(t0
, t0
, mask
);
2700 tcg_gen_extu_i32_tl(t_ra
, t0
);
2701 tcg_temp_free_i32(t0
);
2704 #if defined(TARGET_PPC64)
2705 tcg_gen_deposit_i64(t_ra
, t_rs
, t_rs
, 32, 32);
2706 tcg_gen_rotli_i64(t_ra
, t_ra
, sh
);
2707 tcg_gen_andi_i64(t_ra
, t_ra
, mask
);
2709 g_assert_not_reached();
2713 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2714 gen_set_Rc0(ctx
, t_ra
);
2718 /* rlwnm & rlwnm. */
2719 static void gen_rlwnm(DisasContext
*ctx
)
2721 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
2722 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
2723 TCGv t_rb
= cpu_gpr
[rB(ctx
->opcode
)];
2724 uint32_t mb
= MB(ctx
->opcode
);
2725 uint32_t me
= ME(ctx
->opcode
);
2727 bool mask_in_32b
= true;
2729 #if defined(TARGET_PPC64)
2733 mask
= MASK(mb
, me
);
2735 #if defined(TARGET_PPC64)
2736 if (mask
> 0xffffffffu
) {
2737 mask_in_32b
= false;
2741 TCGv_i32 t0
= tcg_temp_new_i32();
2742 TCGv_i32 t1
= tcg_temp_new_i32();
2743 tcg_gen_trunc_tl_i32(t0
, t_rb
);
2744 tcg_gen_trunc_tl_i32(t1
, t_rs
);
2745 tcg_gen_andi_i32(t0
, t0
, 0x1f);
2746 tcg_gen_rotl_i32(t1
, t1
, t0
);
2747 tcg_gen_extu_i32_tl(t_ra
, t1
);
2748 tcg_temp_free_i32(t0
);
2749 tcg_temp_free_i32(t1
);
2751 #if defined(TARGET_PPC64)
2752 TCGv_i64 t0
= tcg_temp_new_i64();
2753 tcg_gen_andi_i64(t0
, t_rb
, 0x1f);
2754 tcg_gen_deposit_i64(t_ra
, t_rs
, t_rs
, 32, 32);
2755 tcg_gen_rotl_i64(t_ra
, t_ra
, t0
);
2756 tcg_temp_free_i64(t0
);
2758 g_assert_not_reached();
2762 tcg_gen_andi_tl(t_ra
, t_ra
, mask
);
2764 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2765 gen_set_Rc0(ctx
, t_ra
);
2769 #if defined(TARGET_PPC64)
2770 #define GEN_PPC64_R2(name, opc1, opc2) \
2771 static void glue(gen_, name##0)(DisasContext *ctx) \
2773 gen_##name(ctx, 0); \
2776 static void glue(gen_, name##1)(DisasContext *ctx) \
2778 gen_##name(ctx, 1); \
2780 #define GEN_PPC64_R4(name, opc1, opc2) \
2781 static void glue(gen_, name##0)(DisasContext *ctx) \
2783 gen_##name(ctx, 0, 0); \
2786 static void glue(gen_, name##1)(DisasContext *ctx) \
2788 gen_##name(ctx, 0, 1); \
2791 static void glue(gen_, name##2)(DisasContext *ctx) \
2793 gen_##name(ctx, 1, 0); \
2796 static void glue(gen_, name##3)(DisasContext *ctx) \
2798 gen_##name(ctx, 1, 1); \
2801 static void gen_rldinm(DisasContext
*ctx
, int mb
, int me
, int sh
)
2803 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
2804 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
2805 int len
= me
- mb
+ 1;
2806 int rsh
= (64 - sh
) & 63;
2808 if (sh
!= 0 && len
> 0 && me
== (63 - sh
)) {
2809 tcg_gen_deposit_z_tl(t_ra
, t_rs
, sh
, len
);
2810 } else if (me
== 63 && rsh
+ len
<= 64) {
2811 tcg_gen_extract_tl(t_ra
, t_rs
, rsh
, len
);
2813 tcg_gen_rotli_tl(t_ra
, t_rs
, sh
);
2814 tcg_gen_andi_tl(t_ra
, t_ra
, MASK(mb
, me
));
2816 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2817 gen_set_Rc0(ctx
, t_ra
);
2821 /* rldicl - rldicl. */
2822 static inline void gen_rldicl(DisasContext
*ctx
, int mbn
, int shn
)
2826 sh
= SH(ctx
->opcode
) | (shn
<< 5);
2827 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
2828 gen_rldinm(ctx
, mb
, 63, sh
);
2830 GEN_PPC64_R4(rldicl
, 0x1E, 0x00);
2832 /* rldicr - rldicr. */
2833 static inline void gen_rldicr(DisasContext
*ctx
, int men
, int shn
)
2837 sh
= SH(ctx
->opcode
) | (shn
<< 5);
2838 me
= MB(ctx
->opcode
) | (men
<< 5);
2839 gen_rldinm(ctx
, 0, me
, sh
);
2841 GEN_PPC64_R4(rldicr
, 0x1E, 0x02);
2843 /* rldic - rldic. */
2844 static inline void gen_rldic(DisasContext
*ctx
, int mbn
, int shn
)
2848 sh
= SH(ctx
->opcode
) | (shn
<< 5);
2849 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
2850 gen_rldinm(ctx
, mb
, 63 - sh
, sh
);
2852 GEN_PPC64_R4(rldic
, 0x1E, 0x04);
2854 static void gen_rldnm(DisasContext
*ctx
, int mb
, int me
)
2856 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
2857 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
2858 TCGv t_rb
= cpu_gpr
[rB(ctx
->opcode
)];
2861 t0
= tcg_temp_new();
2862 tcg_gen_andi_tl(t0
, t_rb
, 0x3f);
2863 tcg_gen_rotl_tl(t_ra
, t_rs
, t0
);
2866 tcg_gen_andi_tl(t_ra
, t_ra
, MASK(mb
, me
));
2867 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2868 gen_set_Rc0(ctx
, t_ra
);
2872 /* rldcl - rldcl. */
2873 static inline void gen_rldcl(DisasContext
*ctx
, int mbn
)
2877 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
2878 gen_rldnm(ctx
, mb
, 63);
2880 GEN_PPC64_R2(rldcl
, 0x1E, 0x08);
2882 /* rldcr - rldcr. */
2883 static inline void gen_rldcr(DisasContext
*ctx
, int men
)
2887 me
= MB(ctx
->opcode
) | (men
<< 5);
2888 gen_rldnm(ctx
, 0, me
);
2890 GEN_PPC64_R2(rldcr
, 0x1E, 0x09);
2892 /* rldimi - rldimi. */
2893 static void gen_rldimi(DisasContext
*ctx
, int mbn
, int shn
)
2895 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
2896 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
2897 uint32_t sh
= SH(ctx
->opcode
) | (shn
<< 5);
2898 uint32_t mb
= MB(ctx
->opcode
) | (mbn
<< 5);
2899 uint32_t me
= 63 - sh
;
2902 tcg_gen_deposit_tl(t_ra
, t_ra
, t_rs
, sh
, me
- mb
+ 1);
2904 target_ulong mask
= MASK(mb
, me
);
2905 TCGv t1
= tcg_temp_new();
2907 tcg_gen_rotli_tl(t1
, t_rs
, sh
);
2908 tcg_gen_andi_tl(t1
, t1
, mask
);
2909 tcg_gen_andi_tl(t_ra
, t_ra
, ~mask
);
2910 tcg_gen_or_tl(t_ra
, t_ra
, t1
);
2913 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2914 gen_set_Rc0(ctx
, t_ra
);
2917 GEN_PPC64_R4(rldimi
, 0x1E, 0x06);
2920 /*** Integer shift ***/
2923 static void gen_slw(DisasContext
*ctx
)
2927 t0
= tcg_temp_new();
2928 /* AND rS with a mask that is 0 when rB >= 0x20 */
2929 #if defined(TARGET_PPC64)
2930 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3a);
2931 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2933 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1a);
2934 tcg_gen_sari_tl(t0
, t0
, 0x1f);
2936 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2937 t1
= tcg_temp_new();
2938 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
2939 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2942 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
2943 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2944 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2949 static void gen_sraw(DisasContext
*ctx
)
2951 gen_helper_sraw(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
2952 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2953 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2954 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2958 /* srawi & srawi. */
2959 static void gen_srawi(DisasContext
*ctx
)
2961 int sh
= SH(ctx
->opcode
);
2962 TCGv dst
= cpu_gpr
[rA(ctx
->opcode
)];
2963 TCGv src
= cpu_gpr
[rS(ctx
->opcode
)];
2965 tcg_gen_ext32s_tl(dst
, src
);
2966 tcg_gen_movi_tl(cpu_ca
, 0);
2967 if (is_isa300(ctx
)) {
2968 tcg_gen_movi_tl(cpu_ca32
, 0);
2972 tcg_gen_ext32s_tl(dst
, src
);
2973 tcg_gen_andi_tl(cpu_ca
, dst
, (1ULL << sh
) - 1);
2974 t0
= tcg_temp_new();
2975 tcg_gen_sari_tl(t0
, dst
, TARGET_LONG_BITS
- 1);
2976 tcg_gen_and_tl(cpu_ca
, cpu_ca
, t0
);
2978 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_ca
, cpu_ca
, 0);
2979 if (is_isa300(ctx
)) {
2980 tcg_gen_mov_tl(cpu_ca32
, cpu_ca
);
2982 tcg_gen_sari_tl(dst
, dst
, sh
);
2984 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2985 gen_set_Rc0(ctx
, dst
);
2990 static void gen_srw(DisasContext
*ctx
)
2994 t0
= tcg_temp_new();
2995 /* AND rS with a mask that is 0 when rB >= 0x20 */
2996 #if defined(TARGET_PPC64)
2997 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3a);
2998 tcg_gen_sari_tl(t0
, t0
, 0x3f);
3000 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1a);
3001 tcg_gen_sari_tl(t0
, t0
, 0x1f);
3003 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
3004 tcg_gen_ext32u_tl(t0
, t0
);
3005 t1
= tcg_temp_new();
3006 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
3007 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
3010 if (unlikely(Rc(ctx
->opcode
) != 0)) {
3011 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
3015 #if defined(TARGET_PPC64)
3017 static void gen_sld(DisasContext
*ctx
)
3021 t0
= tcg_temp_new();
3022 /* AND rS with a mask that is 0 when rB >= 0x40 */
3023 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x39);
3024 tcg_gen_sari_tl(t0
, t0
, 0x3f);
3025 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
3026 t1
= tcg_temp_new();
3027 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
3028 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
3031 if (unlikely(Rc(ctx
->opcode
) != 0)) {
3032 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
3037 static void gen_srad(DisasContext
*ctx
)
3039 gen_helper_srad(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
3040 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
3041 if (unlikely(Rc(ctx
->opcode
) != 0)) {
3042 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
3045 /* sradi & sradi. */
3046 static inline void gen_sradi(DisasContext
*ctx
, int n
)
3048 int sh
= SH(ctx
->opcode
) + (n
<< 5);
3049 TCGv dst
= cpu_gpr
[rA(ctx
->opcode
)];
3050 TCGv src
= cpu_gpr
[rS(ctx
->opcode
)];
3052 tcg_gen_mov_tl(dst
, src
);
3053 tcg_gen_movi_tl(cpu_ca
, 0);
3054 if (is_isa300(ctx
)) {
3055 tcg_gen_movi_tl(cpu_ca32
, 0);
3059 tcg_gen_andi_tl(cpu_ca
, src
, (1ULL << sh
) - 1);
3060 t0
= tcg_temp_new();
3061 tcg_gen_sari_tl(t0
, src
, TARGET_LONG_BITS
- 1);
3062 tcg_gen_and_tl(cpu_ca
, cpu_ca
, t0
);
3064 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_ca
, cpu_ca
, 0);
3065 if (is_isa300(ctx
)) {
3066 tcg_gen_mov_tl(cpu_ca32
, cpu_ca
);
3068 tcg_gen_sari_tl(dst
, src
, sh
);
3070 if (unlikely(Rc(ctx
->opcode
) != 0)) {
3071 gen_set_Rc0(ctx
, dst
);
3075 static void gen_sradi0(DisasContext
*ctx
)
3080 static void gen_sradi1(DisasContext
*ctx
)
3085 /* extswsli & extswsli. */
3086 static inline void gen_extswsli(DisasContext
*ctx
, int n
)
3088 int sh
= SH(ctx
->opcode
) + (n
<< 5);
3089 TCGv dst
= cpu_gpr
[rA(ctx
->opcode
)];
3090 TCGv src
= cpu_gpr
[rS(ctx
->opcode
)];
3092 tcg_gen_ext32s_tl(dst
, src
);
3093 tcg_gen_shli_tl(dst
, dst
, sh
);
3094 if (unlikely(Rc(ctx
->opcode
) != 0)) {
3095 gen_set_Rc0(ctx
, dst
);
3099 static void gen_extswsli0(DisasContext
*ctx
)
3101 gen_extswsli(ctx
, 0);
3104 static void gen_extswsli1(DisasContext
*ctx
)
3106 gen_extswsli(ctx
, 1);
3110 static void gen_srd(DisasContext
*ctx
)
3114 t0
= tcg_temp_new();
3115 /* AND rS with a mask that is 0 when rB >= 0x40 */
3116 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x39);
3117 tcg_gen_sari_tl(t0
, t0
, 0x3f);
3118 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
3119 t1
= tcg_temp_new();
3120 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
3121 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
3124 if (unlikely(Rc(ctx
->opcode
) != 0)) {
3125 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
3130 /*** Addressing modes ***/
3131 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
3132 static inline void gen_addr_imm_index(DisasContext
*ctx
, TCGv EA
,
3135 target_long simm
= SIMM(ctx
->opcode
);
3138 if (rA(ctx
->opcode
) == 0) {
3139 if (NARROW_MODE(ctx
)) {
3140 simm
= (uint32_t)simm
;
3142 tcg_gen_movi_tl(EA
, simm
);
3143 } else if (likely(simm
!= 0)) {
3144 tcg_gen_addi_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], simm
);
3145 if (NARROW_MODE(ctx
)) {
3146 tcg_gen_ext32u_tl(EA
, EA
);
3149 if (NARROW_MODE(ctx
)) {
3150 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
3152 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
3157 static inline void gen_addr_reg_index(DisasContext
*ctx
, TCGv EA
)
3159 if (rA(ctx
->opcode
) == 0) {
3160 if (NARROW_MODE(ctx
)) {
3161 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
3163 tcg_gen_mov_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
3166 tcg_gen_add_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
3167 if (NARROW_MODE(ctx
)) {
3168 tcg_gen_ext32u_tl(EA
, EA
);
3173 static inline void gen_addr_register(DisasContext
*ctx
, TCGv EA
)
3175 if (rA(ctx
->opcode
) == 0) {
3176 tcg_gen_movi_tl(EA
, 0);
3177 } else if (NARROW_MODE(ctx
)) {
3178 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
3180 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
3184 static inline void gen_addr_add(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
3187 tcg_gen_addi_tl(ret
, arg1
, val
);
3188 if (NARROW_MODE(ctx
)) {
3189 tcg_gen_ext32u_tl(ret
, ret
);
3193 static inline void gen_align_no_le(DisasContext
*ctx
)
3195 gen_exception_err(ctx
, POWERPC_EXCP_ALIGN
,
3196 (ctx
->opcode
& 0x03FF0000) | POWERPC_EXCP_ALIGN_LE
);
3199 /*** Integer load ***/
3200 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask)
3201 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP))
3203 #define GEN_QEMU_LOAD_TL(ldop, op) \
3204 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \
3208 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \
3211 GEN_QEMU_LOAD_TL(ld8u
, DEF_MEMOP(MO_UB
))
3212 GEN_QEMU_LOAD_TL(ld16u
, DEF_MEMOP(MO_UW
))
3213 GEN_QEMU_LOAD_TL(ld16s
, DEF_MEMOP(MO_SW
))
3214 GEN_QEMU_LOAD_TL(ld32u
, DEF_MEMOP(MO_UL
))
3215 GEN_QEMU_LOAD_TL(ld32s
, DEF_MEMOP(MO_SL
))
3217 GEN_QEMU_LOAD_TL(ld16ur
, BSWAP_MEMOP(MO_UW
))
3218 GEN_QEMU_LOAD_TL(ld32ur
, BSWAP_MEMOP(MO_UL
))
3220 #define GEN_QEMU_LOAD_64(ldop, op) \
3221 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \
3225 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \
3228 GEN_QEMU_LOAD_64(ld8u
, DEF_MEMOP(MO_UB
))
3229 GEN_QEMU_LOAD_64(ld16u
, DEF_MEMOP(MO_UW
))
3230 GEN_QEMU_LOAD_64(ld32u
, DEF_MEMOP(MO_UL
))
3231 GEN_QEMU_LOAD_64(ld32s
, DEF_MEMOP(MO_SL
))
3232 GEN_QEMU_LOAD_64(ld64
, DEF_MEMOP(MO_Q
))
3234 #if defined(TARGET_PPC64)
3235 GEN_QEMU_LOAD_64(ld64ur
, BSWAP_MEMOP(MO_Q
))
3238 #define GEN_QEMU_STORE_TL(stop, op) \
3239 static void glue(gen_qemu_, stop)(DisasContext *ctx, \
3243 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
3246 #if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY)
3247 GEN_QEMU_STORE_TL(st8
, DEF_MEMOP(MO_UB
))
3249 GEN_QEMU_STORE_TL(st16
, DEF_MEMOP(MO_UW
))
3250 GEN_QEMU_STORE_TL(st32
, DEF_MEMOP(MO_UL
))
3252 GEN_QEMU_STORE_TL(st16r
, BSWAP_MEMOP(MO_UW
))
3253 GEN_QEMU_STORE_TL(st32r
, BSWAP_MEMOP(MO_UL
))
3255 #define GEN_QEMU_STORE_64(stop, op) \
3256 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \
3260 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \
3263 GEN_QEMU_STORE_64(st8
, DEF_MEMOP(MO_UB
))
3264 GEN_QEMU_STORE_64(st16
, DEF_MEMOP(MO_UW
))
3265 GEN_QEMU_STORE_64(st32
, DEF_MEMOP(MO_UL
))
3266 GEN_QEMU_STORE_64(st64
, DEF_MEMOP(MO_Q
))
3268 #if defined(TARGET_PPC64)
3269 GEN_QEMU_STORE_64(st64r
, BSWAP_MEMOP(MO_Q
))
3272 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
3273 static void glue(gen_, name##x)(DisasContext *ctx) \
3277 gen_set_access_type(ctx, ACCESS_INT); \
3278 EA = tcg_temp_new(); \
3279 gen_addr_reg_index(ctx, EA); \
3280 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
3281 tcg_temp_free(EA); \
3284 #define GEN_LDX(name, ldop, opc2, opc3, type) \
3285 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
3287 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
3288 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
3290 #define GEN_LDEPX(name, ldop, opc2, opc3) \
3291 static void glue(gen_, name##epx)(DisasContext *ctx) \
3295 gen_set_access_type(ctx, ACCESS_INT); \
3296 EA = tcg_temp_new(); \
3297 gen_addr_reg_index(ctx, EA); \
3298 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\
3299 tcg_temp_free(EA); \
3302 GEN_LDEPX(lb
, DEF_MEMOP(MO_UB
), 0x1F, 0x02)
3303 GEN_LDEPX(lh
, DEF_MEMOP(MO_UW
), 0x1F, 0x08)
3304 GEN_LDEPX(lw
, DEF_MEMOP(MO_UL
), 0x1F, 0x00)
3305 #if defined(TARGET_PPC64)
3306 GEN_LDEPX(ld
, DEF_MEMOP(MO_Q
), 0x1D, 0x00)
3309 #if defined(TARGET_PPC64)
3310 /* CI load/store variants */
3311 GEN_LDX_HVRM(ldcix
, ld64_i64
, 0x15, 0x1b, PPC_CILDST
)
3312 GEN_LDX_HVRM(lwzcix
, ld32u
, 0x15, 0x15, PPC_CILDST
)
3313 GEN_LDX_HVRM(lhzcix
, ld16u
, 0x15, 0x19, PPC_CILDST
)
3314 GEN_LDX_HVRM(lbzcix
, ld8u
, 0x15, 0x1a, PPC_CILDST
)
3317 static void gen_lq(DisasContext
*ctx
)
3322 /* lq is a legal user mode instruction starting in ISA 2.07 */
3323 bool legal_in_user_mode
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
3324 bool le_is_supported
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
3326 if (!legal_in_user_mode
&& ctx
->pr
) {
3327 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3331 if (!le_is_supported
&& ctx
->le_mode
) {
3332 gen_align_no_le(ctx
);
3335 ra
= rA(ctx
->opcode
);
3336 rd
= rD(ctx
->opcode
);
3337 if (unlikely((rd
& 1) || rd
== ra
)) {
3338 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3342 gen_set_access_type(ctx
, ACCESS_INT
);
3343 EA
= tcg_temp_new();
3344 gen_addr_imm_index(ctx
, EA
, 0x0F);
3346 /* Note that the low part is always in RD+1, even in LE mode. */
3347 lo
= cpu_gpr
[rd
+ 1];
3350 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
3351 if (HAVE_ATOMIC128
) {
3352 TCGv_i32 oi
= tcg_temp_new_i32();
3354 tcg_gen_movi_i32(oi
, make_memop_idx(MO_LEQ
, ctx
->mem_idx
));
3355 gen_helper_lq_le_parallel(lo
, cpu_env
, EA
, oi
);
3357 tcg_gen_movi_i32(oi
, make_memop_idx(MO_BEQ
, ctx
->mem_idx
));
3358 gen_helper_lq_be_parallel(lo
, cpu_env
, EA
, oi
);
3360 tcg_temp_free_i32(oi
);
3361 tcg_gen_ld_i64(hi
, cpu_env
, offsetof(CPUPPCState
, retxh
));
3363 /* Restart with exclusive lock. */
3364 gen_helper_exit_atomic(cpu_env
);
3365 ctx
->base
.is_jmp
= DISAS_NORETURN
;
3367 } else if (ctx
->le_mode
) {
3368 tcg_gen_qemu_ld_i64(lo
, EA
, ctx
->mem_idx
, MO_LEQ
);
3369 gen_addr_add(ctx
, EA
, EA
, 8);
3370 tcg_gen_qemu_ld_i64(hi
, EA
, ctx
->mem_idx
, MO_LEQ
);
3372 tcg_gen_qemu_ld_i64(hi
, EA
, ctx
->mem_idx
, MO_BEQ
);
3373 gen_addr_add(ctx
, EA
, EA
, 8);
3374 tcg_gen_qemu_ld_i64(lo
, EA
, ctx
->mem_idx
, MO_BEQ
);
3380 /*** Integer store ***/
3381 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
3382 static void glue(gen_, name##x)(DisasContext *ctx) \
3386 gen_set_access_type(ctx, ACCESS_INT); \
3387 EA = tcg_temp_new(); \
3388 gen_addr_reg_index(ctx, EA); \
3389 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3390 tcg_temp_free(EA); \
3392 #define GEN_STX(name, stop, opc2, opc3, type) \
3393 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
3395 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
3396 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
3398 #define GEN_STEPX(name, stop, opc2, opc3) \
3399 static void glue(gen_, name##epx)(DisasContext *ctx) \
3403 gen_set_access_type(ctx, ACCESS_INT); \
3404 EA = tcg_temp_new(); \
3405 gen_addr_reg_index(ctx, EA); \
3406 tcg_gen_qemu_st_tl( \
3407 cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \
3408 tcg_temp_free(EA); \
3411 GEN_STEPX(stb
, DEF_MEMOP(MO_UB
), 0x1F, 0x06)
3412 GEN_STEPX(sth
, DEF_MEMOP(MO_UW
), 0x1F, 0x0C)
3413 GEN_STEPX(stw
, DEF_MEMOP(MO_UL
), 0x1F, 0x04)
3414 #if defined(TARGET_PPC64)
3415 GEN_STEPX(std
, DEF_MEMOP(MO_Q
), 0x1d, 0x04)
3418 #if defined(TARGET_PPC64)
3419 GEN_STX_HVRM(stdcix
, st64_i64
, 0x15, 0x1f, PPC_CILDST
)
3420 GEN_STX_HVRM(stwcix
, st32
, 0x15, 0x1c, PPC_CILDST
)
3421 GEN_STX_HVRM(sthcix
, st16
, 0x15, 0x1d, PPC_CILDST
)
3422 GEN_STX_HVRM(stbcix
, st8
, 0x15, 0x1e, PPC_CILDST
)
3424 static void gen_std(DisasContext
*ctx
)
3429 rs
= rS(ctx
->opcode
);
3430 if ((ctx
->opcode
& 0x3) == 0x2) { /* stq */
3431 bool legal_in_user_mode
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
3432 bool le_is_supported
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
3435 if (!(ctx
->insns_flags
& PPC_64BX
)) {
3436 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3439 if (!legal_in_user_mode
&& ctx
->pr
) {
3440 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3444 if (!le_is_supported
&& ctx
->le_mode
) {
3445 gen_align_no_le(ctx
);
3449 if (unlikely(rs
& 1)) {
3450 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3453 gen_set_access_type(ctx
, ACCESS_INT
);
3454 EA
= tcg_temp_new();
3455 gen_addr_imm_index(ctx
, EA
, 0x03);
3457 /* Note that the low part is always in RS+1, even in LE mode. */
3458 lo
= cpu_gpr
[rs
+ 1];
3461 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
3462 if (HAVE_ATOMIC128
) {
3463 TCGv_i32 oi
= tcg_temp_new_i32();
3465 tcg_gen_movi_i32(oi
, make_memop_idx(MO_LEQ
, ctx
->mem_idx
));
3466 gen_helper_stq_le_parallel(cpu_env
, EA
, lo
, hi
, oi
);
3468 tcg_gen_movi_i32(oi
, make_memop_idx(MO_BEQ
, ctx
->mem_idx
));
3469 gen_helper_stq_be_parallel(cpu_env
, EA
, lo
, hi
, oi
);
3471 tcg_temp_free_i32(oi
);
3473 /* Restart with exclusive lock. */
3474 gen_helper_exit_atomic(cpu_env
);
3475 ctx
->base
.is_jmp
= DISAS_NORETURN
;
3477 } else if (ctx
->le_mode
) {
3478 tcg_gen_qemu_st_i64(lo
, EA
, ctx
->mem_idx
, MO_LEQ
);
3479 gen_addr_add(ctx
, EA
, EA
, 8);
3480 tcg_gen_qemu_st_i64(hi
, EA
, ctx
->mem_idx
, MO_LEQ
);
3482 tcg_gen_qemu_st_i64(hi
, EA
, ctx
->mem_idx
, MO_BEQ
);
3483 gen_addr_add(ctx
, EA
, EA
, 8);
3484 tcg_gen_qemu_st_i64(lo
, EA
, ctx
->mem_idx
, MO_BEQ
);
3489 if (Rc(ctx
->opcode
)) {
3490 if (unlikely(rA(ctx
->opcode
) == 0)) {
3491 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3495 gen_set_access_type(ctx
, ACCESS_INT
);
3496 EA
= tcg_temp_new();
3497 gen_addr_imm_index(ctx
, EA
, 0x03);
3498 gen_qemu_st64_i64(ctx
, cpu_gpr
[rs
], EA
);
3499 if (Rc(ctx
->opcode
)) {
3500 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
3506 /*** Integer load and store with byte reverse ***/
3509 GEN_LDX(lhbr
, ld16ur
, 0x16, 0x18, PPC_INTEGER
);
3512 GEN_LDX(lwbr
, ld32ur
, 0x16, 0x10, PPC_INTEGER
);
3514 #if defined(TARGET_PPC64)
3516 GEN_LDX_E(ldbr
, ld64ur_i64
, 0x14, 0x10, PPC_NONE
, PPC2_DBRX
, CHK_NONE
);
3518 GEN_STX_E(stdbr
, st64r_i64
, 0x14, 0x14, PPC_NONE
, PPC2_DBRX
, CHK_NONE
);
3519 #endif /* TARGET_PPC64 */
3522 GEN_STX(sthbr
, st16r
, 0x16, 0x1C, PPC_INTEGER
);
3524 GEN_STX(stwbr
, st32r
, 0x16, 0x14, PPC_INTEGER
);
3526 /*** Integer load and store multiple ***/
3529 static void gen_lmw(DisasContext
*ctx
)
3535 gen_align_no_le(ctx
);
3538 gen_set_access_type(ctx
, ACCESS_INT
);
3539 t0
= tcg_temp_new();
3540 t1
= tcg_const_i32(rD(ctx
->opcode
));
3541 gen_addr_imm_index(ctx
, t0
, 0);
3542 gen_helper_lmw(cpu_env
, t0
, t1
);
3544 tcg_temp_free_i32(t1
);
3548 static void gen_stmw(DisasContext
*ctx
)
3554 gen_align_no_le(ctx
);
3557 gen_set_access_type(ctx
, ACCESS_INT
);
3558 t0
= tcg_temp_new();
3559 t1
= tcg_const_i32(rS(ctx
->opcode
));
3560 gen_addr_imm_index(ctx
, t0
, 0);
3561 gen_helper_stmw(cpu_env
, t0
, t1
);
3563 tcg_temp_free_i32(t1
);
3566 /*** Integer load and store strings ***/
3570 * PowerPC32 specification says we must generate an exception if rA is
3571 * in the range of registers to be loaded. In an other hand, IBM says
3572 * this is valid, but rA won't be loaded. For now, I'll follow the
3575 static void gen_lswi(DisasContext
*ctx
)
3579 int nb
= NB(ctx
->opcode
);
3580 int start
= rD(ctx
->opcode
);
3581 int ra
= rA(ctx
->opcode
);
3585 gen_align_no_le(ctx
);
3591 nr
= DIV_ROUND_UP(nb
, 4);
3592 if (unlikely(lsw_reg_in_range(start
, nr
, ra
))) {
3593 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
3596 gen_set_access_type(ctx
, ACCESS_INT
);
3597 t0
= tcg_temp_new();
3598 gen_addr_register(ctx
, t0
);
3599 t1
= tcg_const_i32(nb
);
3600 t2
= tcg_const_i32(start
);
3601 gen_helper_lsw(cpu_env
, t0
, t1
, t2
);
3603 tcg_temp_free_i32(t1
);
3604 tcg_temp_free_i32(t2
);
3608 static void gen_lswx(DisasContext
*ctx
)
3611 TCGv_i32 t1
, t2
, t3
;
3614 gen_align_no_le(ctx
);
3617 gen_set_access_type(ctx
, ACCESS_INT
);
3618 t0
= tcg_temp_new();
3619 gen_addr_reg_index(ctx
, t0
);
3620 t1
= tcg_const_i32(rD(ctx
->opcode
));
3621 t2
= tcg_const_i32(rA(ctx
->opcode
));
3622 t3
= tcg_const_i32(rB(ctx
->opcode
));
3623 gen_helper_lswx(cpu_env
, t0
, t1
, t2
, t3
);
3625 tcg_temp_free_i32(t1
);
3626 tcg_temp_free_i32(t2
);
3627 tcg_temp_free_i32(t3
);
3631 static void gen_stswi(DisasContext
*ctx
)
3635 int nb
= NB(ctx
->opcode
);
3638 gen_align_no_le(ctx
);
3641 gen_set_access_type(ctx
, ACCESS_INT
);
3642 t0
= tcg_temp_new();
3643 gen_addr_register(ctx
, t0
);
3647 t1
= tcg_const_i32(nb
);
3648 t2
= tcg_const_i32(rS(ctx
->opcode
));
3649 gen_helper_stsw(cpu_env
, t0
, t1
, t2
);
3651 tcg_temp_free_i32(t1
);
3652 tcg_temp_free_i32(t2
);
3656 static void gen_stswx(DisasContext
*ctx
)
3662 gen_align_no_le(ctx
);
3665 gen_set_access_type(ctx
, ACCESS_INT
);
3666 t0
= tcg_temp_new();
3667 gen_addr_reg_index(ctx
, t0
);
3668 t1
= tcg_temp_new_i32();
3669 tcg_gen_trunc_tl_i32(t1
, cpu_xer
);
3670 tcg_gen_andi_i32(t1
, t1
, 0x7F);
3671 t2
= tcg_const_i32(rS(ctx
->opcode
));
3672 gen_helper_stsw(cpu_env
, t0
, t1
, t2
);
3674 tcg_temp_free_i32(t1
);
3675 tcg_temp_free_i32(t2
);
3678 /*** Memory synchronisation ***/
3680 static void gen_eieio(DisasContext
*ctx
)
3682 TCGBar bar
= TCG_MO_LD_ST
;
3685 * POWER9 has a eieio instruction variant using bit 6 as a hint to
3686 * tell the CPU it is a store-forwarding barrier.
3688 if (ctx
->opcode
& 0x2000000) {
3690 * ISA says that "Reserved fields in instructions are ignored
3691 * by the processor". So ignore the bit 6 on non-POWER9 CPU but
3692 * as this is not an instruction software should be using,
3693 * complain to the user.
3695 if (!(ctx
->insns_flags2
& PPC2_ISA300
)) {
3696 qemu_log_mask(LOG_GUEST_ERROR
, "invalid eieio using bit 6 at @"
3697 TARGET_FMT_lx
"\n", ctx
->cia
);
3703 tcg_gen_mb(bar
| TCG_BAR_SC
);
3706 #if !defined(CONFIG_USER_ONLY)
3707 static inline void gen_check_tlb_flush(DisasContext
*ctx
, bool global
)
3712 if (!ctx
->lazy_tlb_flush
) {
3715 l
= gen_new_label();
3716 t
= tcg_temp_new_i32();
3717 tcg_gen_ld_i32(t
, cpu_env
, offsetof(CPUPPCState
, tlb_need_flush
));
3718 tcg_gen_brcondi_i32(TCG_COND_EQ
, t
, 0, l
);
3720 gen_helper_check_tlb_flush_global(cpu_env
);
3722 gen_helper_check_tlb_flush_local(cpu_env
);
3725 tcg_temp_free_i32(t
);
3728 static inline void gen_check_tlb_flush(DisasContext
*ctx
, bool global
) { }
3732 static void gen_isync(DisasContext
*ctx
)
3735 * We need to check for a pending TLB flush. This can only happen in
3736 * kernel mode however so check MSR_PR
3739 gen_check_tlb_flush(ctx
, false);
3741 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
3742 ctx
->base
.is_jmp
= DISAS_EXIT_UPDATE
;
3745 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))
3747 static void gen_load_locked(DisasContext
*ctx
, MemOp memop
)
3749 TCGv gpr
= cpu_gpr
[rD(ctx
->opcode
)];
3750 TCGv t0
= tcg_temp_new();
3752 gen_set_access_type(ctx
, ACCESS_RES
);
3753 gen_addr_reg_index(ctx
, t0
);
3754 tcg_gen_qemu_ld_tl(gpr
, t0
, ctx
->mem_idx
, memop
| MO_ALIGN
);
3755 tcg_gen_mov_tl(cpu_reserve
, t0
);
3756 tcg_gen_mov_tl(cpu_reserve_val
, gpr
);
3757 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3761 #define LARX(name, memop) \
3762 static void gen_##name(DisasContext *ctx) \
3764 gen_load_locked(ctx, memop); \
3768 LARX(lbarx
, DEF_MEMOP(MO_UB
))
3769 LARX(lharx
, DEF_MEMOP(MO_UW
))
3770 LARX(lwarx
, DEF_MEMOP(MO_UL
))
3772 static void gen_fetch_inc_conditional(DisasContext
*ctx
, MemOp memop
,
3773 TCGv EA
, TCGCond cond
, int addend
)
3775 TCGv t
= tcg_temp_new();
3776 TCGv t2
= tcg_temp_new();
3777 TCGv u
= tcg_temp_new();
3779 tcg_gen_qemu_ld_tl(t
, EA
, ctx
->mem_idx
, memop
);
3780 tcg_gen_addi_tl(t2
, EA
, MEMOP_GET_SIZE(memop
));
3781 tcg_gen_qemu_ld_tl(t2
, t2
, ctx
->mem_idx
, memop
);
3782 tcg_gen_addi_tl(u
, t
, addend
);
3784 /* E.g. for fetch and increment bounded... */
3785 /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */
3786 tcg_gen_movcond_tl(cond
, u
, t
, t2
, u
, t
);
3787 tcg_gen_qemu_st_tl(u
, EA
, ctx
->mem_idx
, memop
);
3789 /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */
3790 tcg_gen_movi_tl(u
, 1 << (MEMOP_GET_SIZE(memop
) * 8 - 1));
3791 tcg_gen_movcond_tl(cond
, cpu_gpr
[rD(ctx
->opcode
)], t
, t2
, t
, u
);
3798 static void gen_ld_atomic(DisasContext
*ctx
, MemOp memop
)
3800 uint32_t gpr_FC
= FC(ctx
->opcode
);
3801 TCGv EA
= tcg_temp_new();
3802 int rt
= rD(ctx
->opcode
);
3806 gen_addr_register(ctx
, EA
);
3808 src
= cpu_gpr
[(rt
+ 1) & 31];
3810 need_serial
= false;
3813 case 0: /* Fetch and add */
3814 tcg_gen_atomic_fetch_add_tl(dst
, EA
, src
, ctx
->mem_idx
, memop
);
3816 case 1: /* Fetch and xor */
3817 tcg_gen_atomic_fetch_xor_tl(dst
, EA
, src
, ctx
->mem_idx
, memop
);
3819 case 2: /* Fetch and or */
3820 tcg_gen_atomic_fetch_or_tl(dst
, EA
, src
, ctx
->mem_idx
, memop
);
3822 case 3: /* Fetch and 'and' */
3823 tcg_gen_atomic_fetch_and_tl(dst
, EA
, src
, ctx
->mem_idx
, memop
);
3825 case 4: /* Fetch and max unsigned */
3826 tcg_gen_atomic_fetch_umax_tl(dst
, EA
, src
, ctx
->mem_idx
, memop
);
3828 case 5: /* Fetch and max signed */
3829 tcg_gen_atomic_fetch_smax_tl(dst
, EA
, src
, ctx
->mem_idx
, memop
);
3831 case 6: /* Fetch and min unsigned */
3832 tcg_gen_atomic_fetch_umin_tl(dst
, EA
, src
, ctx
->mem_idx
, memop
);
3834 case 7: /* Fetch and min signed */
3835 tcg_gen_atomic_fetch_smin_tl(dst
, EA
, src
, ctx
->mem_idx
, memop
);
3838 tcg_gen_atomic_xchg_tl(dst
, EA
, src
, ctx
->mem_idx
, memop
);
3841 case 16: /* Compare and swap not equal */
3842 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
3845 TCGv t0
= tcg_temp_new();
3846 TCGv t1
= tcg_temp_new();
3848 tcg_gen_qemu_ld_tl(t0
, EA
, ctx
->mem_idx
, memop
);
3849 if ((memop
& MO_SIZE
) == MO_64
|| TARGET_LONG_BITS
== 32) {
3850 tcg_gen_mov_tl(t1
, src
);
3852 tcg_gen_ext32u_tl(t1
, src
);
3854 tcg_gen_movcond_tl(TCG_COND_NE
, t1
, t0
, t1
,
3855 cpu_gpr
[(rt
+ 2) & 31], t0
);
3856 tcg_gen_qemu_st_tl(t1
, EA
, ctx
->mem_idx
, memop
);
3857 tcg_gen_mov_tl(dst
, t0
);
3864 case 24: /* Fetch and increment bounded */
3865 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
3868 gen_fetch_inc_conditional(ctx
, memop
, EA
, TCG_COND_NE
, 1);
3871 case 25: /* Fetch and increment equal */
3872 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
3875 gen_fetch_inc_conditional(ctx
, memop
, EA
, TCG_COND_EQ
, 1);
3878 case 28: /* Fetch and decrement bounded */
3879 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
3882 gen_fetch_inc_conditional(ctx
, memop
, EA
, TCG_COND_NE
, -1);
3887 /* invoke data storage error handler */
3888 gen_exception_err(ctx
, POWERPC_EXCP_DSI
, POWERPC_EXCP_INVAL
);
3893 /* Restart with exclusive lock. */
3894 gen_helper_exit_atomic(cpu_env
);
3895 ctx
->base
.is_jmp
= DISAS_NORETURN
;
3899 static void gen_lwat(DisasContext
*ctx
)
3901 gen_ld_atomic(ctx
, DEF_MEMOP(MO_UL
));
3905 static void gen_ldat(DisasContext
*ctx
)
3907 gen_ld_atomic(ctx
, DEF_MEMOP(MO_Q
));
3911 static void gen_st_atomic(DisasContext
*ctx
, MemOp memop
)
3913 uint32_t gpr_FC
= FC(ctx
->opcode
);
3914 TCGv EA
= tcg_temp_new();
3917 gen_addr_register(ctx
, EA
);
3918 src
= cpu_gpr
[rD(ctx
->opcode
)];
3919 discard
= tcg_temp_new();
3923 case 0: /* add and Store */
3924 tcg_gen_atomic_add_fetch_tl(discard
, EA
, src
, ctx
->mem_idx
, memop
);
3926 case 1: /* xor and Store */
3927 tcg_gen_atomic_xor_fetch_tl(discard
, EA
, src
, ctx
->mem_idx
, memop
);
3929 case 2: /* Or and Store */
3930 tcg_gen_atomic_or_fetch_tl(discard
, EA
, src
, ctx
->mem_idx
, memop
);
3932 case 3: /* 'and' and Store */
3933 tcg_gen_atomic_and_fetch_tl(discard
, EA
, src
, ctx
->mem_idx
, memop
);
3935 case 4: /* Store max unsigned */
3936 tcg_gen_atomic_umax_fetch_tl(discard
, EA
, src
, ctx
->mem_idx
, memop
);
3938 case 5: /* Store max signed */
3939 tcg_gen_atomic_smax_fetch_tl(discard
, EA
, src
, ctx
->mem_idx
, memop
);
3941 case 6: /* Store min unsigned */
3942 tcg_gen_atomic_umin_fetch_tl(discard
, EA
, src
, ctx
->mem_idx
, memop
);
3944 case 7: /* Store min signed */
3945 tcg_gen_atomic_smin_fetch_tl(discard
, EA
, src
, ctx
->mem_idx
, memop
);
3947 case 24: /* Store twin */
3948 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
3949 /* Restart with exclusive lock. */
3950 gen_helper_exit_atomic(cpu_env
);
3951 ctx
->base
.is_jmp
= DISAS_NORETURN
;
3953 TCGv t
= tcg_temp_new();
3954 TCGv t2
= tcg_temp_new();
3955 TCGv s
= tcg_temp_new();
3956 TCGv s2
= tcg_temp_new();
3957 TCGv ea_plus_s
= tcg_temp_new();
3959 tcg_gen_qemu_ld_tl(t
, EA
, ctx
->mem_idx
, memop
);
3960 tcg_gen_addi_tl(ea_plus_s
, EA
, MEMOP_GET_SIZE(memop
));
3961 tcg_gen_qemu_ld_tl(t2
, ea_plus_s
, ctx
->mem_idx
, memop
);
3962 tcg_gen_movcond_tl(TCG_COND_EQ
, s
, t
, t2
, src
, t
);
3963 tcg_gen_movcond_tl(TCG_COND_EQ
, s2
, t
, t2
, src
, t2
);
3964 tcg_gen_qemu_st_tl(s
, EA
, ctx
->mem_idx
, memop
);
3965 tcg_gen_qemu_st_tl(s2
, ea_plus_s
, ctx
->mem_idx
, memop
);
3967 tcg_temp_free(ea_plus_s
);
3975 /* invoke data storage error handler */
3976 gen_exception_err(ctx
, POWERPC_EXCP_DSI
, POWERPC_EXCP_INVAL
);
3978 tcg_temp_free(discard
);
3982 static void gen_stwat(DisasContext
*ctx
)
3984 gen_st_atomic(ctx
, DEF_MEMOP(MO_UL
));
3988 static void gen_stdat(DisasContext
*ctx
)
3990 gen_st_atomic(ctx
, DEF_MEMOP(MO_Q
));
3994 static void gen_conditional_store(DisasContext
*ctx
, MemOp memop
)
3996 TCGLabel
*l1
= gen_new_label();
3997 TCGLabel
*l2
= gen_new_label();
3998 TCGv t0
= tcg_temp_new();
3999 int reg
= rS(ctx
->opcode
);
4001 gen_set_access_type(ctx
, ACCESS_RES
);
4002 gen_addr_reg_index(ctx
, t0
);
4003 tcg_gen_brcond_tl(TCG_COND_NE
, t0
, cpu_reserve
, l1
);
4006 t0
= tcg_temp_new();
4007 tcg_gen_atomic_cmpxchg_tl(t0
, cpu_reserve
, cpu_reserve_val
,
4008 cpu_gpr
[reg
], ctx
->mem_idx
,
4009 DEF_MEMOP(memop
) | MO_ALIGN
);
4010 tcg_gen_setcond_tl(TCG_COND_EQ
, t0
, t0
, cpu_reserve_val
);
4011 tcg_gen_shli_tl(t0
, t0
, CRF_EQ_BIT
);
4012 tcg_gen_or_tl(t0
, t0
, cpu_so
);
4013 tcg_gen_trunc_tl_i32(cpu_crf
[0], t0
);
4020 * Address mismatch implies failure. But we still need to provide
4021 * the memory barrier semantics of the instruction.
4023 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
4024 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
4027 tcg_gen_movi_tl(cpu_reserve
, -1);
4030 #define STCX(name, memop) \
4031 static void gen_##name(DisasContext *ctx) \
4033 gen_conditional_store(ctx, memop); \
4036 STCX(stbcx_
, DEF_MEMOP(MO_UB
))
4037 STCX(sthcx_
, DEF_MEMOP(MO_UW
))
4038 STCX(stwcx_
, DEF_MEMOP(MO_UL
))
4040 #if defined(TARGET_PPC64)
4042 LARX(ldarx
, DEF_MEMOP(MO_Q
))
4044 STCX(stdcx_
, DEF_MEMOP(MO_Q
))
4047 static void gen_lqarx(DisasContext
*ctx
)
4049 int rd
= rD(ctx
->opcode
);
4052 if (unlikely((rd
& 1) || (rd
== rA(ctx
->opcode
)) ||
4053 (rd
== rB(ctx
->opcode
)))) {
4054 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
4058 gen_set_access_type(ctx
, ACCESS_RES
);
4059 EA
= tcg_temp_new();
4060 gen_addr_reg_index(ctx
, EA
);
4062 /* Note that the low part is always in RD+1, even in LE mode. */
4063 lo
= cpu_gpr
[rd
+ 1];
4066 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
4067 if (HAVE_ATOMIC128
) {
4068 TCGv_i32 oi
= tcg_temp_new_i32();
4070 tcg_gen_movi_i32(oi
, make_memop_idx(MO_LEQ
| MO_ALIGN_16
,
4072 gen_helper_lq_le_parallel(lo
, cpu_env
, EA
, oi
);
4074 tcg_gen_movi_i32(oi
, make_memop_idx(MO_BEQ
| MO_ALIGN_16
,
4076 gen_helper_lq_be_parallel(lo
, cpu_env
, EA
, oi
);
4078 tcg_temp_free_i32(oi
);
4079 tcg_gen_ld_i64(hi
, cpu_env
, offsetof(CPUPPCState
, retxh
));
4081 /* Restart with exclusive lock. */
4082 gen_helper_exit_atomic(cpu_env
);
4083 ctx
->base
.is_jmp
= DISAS_NORETURN
;
4087 } else if (ctx
->le_mode
) {
4088 tcg_gen_qemu_ld_i64(lo
, EA
, ctx
->mem_idx
, MO_LEQ
| MO_ALIGN_16
);
4089 tcg_gen_mov_tl(cpu_reserve
, EA
);
4090 gen_addr_add(ctx
, EA
, EA
, 8);
4091 tcg_gen_qemu_ld_i64(hi
, EA
, ctx
->mem_idx
, MO_LEQ
);
4093 tcg_gen_qemu_ld_i64(hi
, EA
, ctx
->mem_idx
, MO_BEQ
| MO_ALIGN_16
);
4094 tcg_gen_mov_tl(cpu_reserve
, EA
);
4095 gen_addr_add(ctx
, EA
, EA
, 8);
4096 tcg_gen_qemu_ld_i64(lo
, EA
, ctx
->mem_idx
, MO_BEQ
);
4100 tcg_gen_st_tl(hi
, cpu_env
, offsetof(CPUPPCState
, reserve_val
));
4101 tcg_gen_st_tl(lo
, cpu_env
, offsetof(CPUPPCState
, reserve_val2
));
4105 static void gen_stqcx_(DisasContext
*ctx
)
4107 int rs
= rS(ctx
->opcode
);
4110 if (unlikely(rs
& 1)) {
4111 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
4115 gen_set_access_type(ctx
, ACCESS_RES
);
4116 EA
= tcg_temp_new();
4117 gen_addr_reg_index(ctx
, EA
);
4119 /* Note that the low part is always in RS+1, even in LE mode. */
4120 lo
= cpu_gpr
[rs
+ 1];
4123 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
4124 if (HAVE_CMPXCHG128
) {
4125 TCGv_i32 oi
= tcg_const_i32(DEF_MEMOP(MO_Q
) | MO_ALIGN_16
);
4127 gen_helper_stqcx_le_parallel(cpu_crf
[0], cpu_env
,
4130 gen_helper_stqcx_be_parallel(cpu_crf
[0], cpu_env
,
4133 tcg_temp_free_i32(oi
);
4135 /* Restart with exclusive lock. */
4136 gen_helper_exit_atomic(cpu_env
);
4137 ctx
->base
.is_jmp
= DISAS_NORETURN
;
4141 TCGLabel
*lab_fail
= gen_new_label();
4142 TCGLabel
*lab_over
= gen_new_label();
4143 TCGv_i64 t0
= tcg_temp_new_i64();
4144 TCGv_i64 t1
= tcg_temp_new_i64();
4146 tcg_gen_brcond_tl(TCG_COND_NE
, EA
, cpu_reserve
, lab_fail
);
4149 gen_qemu_ld64_i64(ctx
, t0
, cpu_reserve
);
4150 tcg_gen_ld_i64(t1
, cpu_env
, (ctx
->le_mode
4151 ? offsetof(CPUPPCState
, reserve_val2
)
4152 : offsetof(CPUPPCState
, reserve_val
)));
4153 tcg_gen_brcond_i64(TCG_COND_NE
, t0
, t1
, lab_fail
);
4155 tcg_gen_addi_i64(t0
, cpu_reserve
, 8);
4156 gen_qemu_ld64_i64(ctx
, t0
, t0
);
4157 tcg_gen_ld_i64(t1
, cpu_env
, (ctx
->le_mode
4158 ? offsetof(CPUPPCState
, reserve_val
)
4159 : offsetof(CPUPPCState
, reserve_val2
)));
4160 tcg_gen_brcond_i64(TCG_COND_NE
, t0
, t1
, lab_fail
);
4163 gen_qemu_st64_i64(ctx
, ctx
->le_mode
? lo
: hi
, cpu_reserve
);
4164 tcg_gen_addi_i64(t0
, cpu_reserve
, 8);
4165 gen_qemu_st64_i64(ctx
, ctx
->le_mode
? hi
: lo
, t0
);
4167 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
4168 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], CRF_EQ
);
4169 tcg_gen_br(lab_over
);
4171 gen_set_label(lab_fail
);
4172 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
4174 gen_set_label(lab_over
);
4175 tcg_gen_movi_tl(cpu_reserve
, -1);
4176 tcg_temp_free_i64(t0
);
4177 tcg_temp_free_i64(t1
);
4180 #endif /* defined(TARGET_PPC64) */
4183 static void gen_sync(DisasContext
*ctx
)
4185 uint32_t l
= (ctx
->opcode
>> 21) & 3;
4188 * We may need to check for a pending TLB flush.
4190 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
4192 * Additionally, this can only happen in kernel mode however so
4193 * check MSR_PR as well.
4195 if (((l
== 2) || !(ctx
->insns_flags
& PPC_64B
)) && !ctx
->pr
) {
4196 gen_check_tlb_flush(ctx
, true);
4198 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
4202 static void gen_wait(DisasContext
*ctx
)
4204 TCGv_i32 t0
= tcg_const_i32(1);
4205 tcg_gen_st_i32(t0
, cpu_env
,
4206 -offsetof(PowerPCCPU
, env
) + offsetof(CPUState
, halted
));
4207 tcg_temp_free_i32(t0
);
4208 /* Stop translation, as the CPU is supposed to sleep from now */
4209 gen_exception_nip(ctx
, EXCP_HLT
, ctx
->base
.pc_next
);
4212 #if defined(TARGET_PPC64)
4213 static void gen_doze(DisasContext
*ctx
)
4215 #if defined(CONFIG_USER_ONLY)
4221 t
= tcg_const_i32(PPC_PM_DOZE
);
4222 gen_helper_pminsn(cpu_env
, t
);
4223 tcg_temp_free_i32(t
);
4224 /* Stop translation, as the CPU is supposed to sleep from now */
4225 gen_exception_nip(ctx
, EXCP_HLT
, ctx
->base
.pc_next
);
4226 #endif /* defined(CONFIG_USER_ONLY) */
4229 static void gen_nap(DisasContext
*ctx
)
4231 #if defined(CONFIG_USER_ONLY)
4237 t
= tcg_const_i32(PPC_PM_NAP
);
4238 gen_helper_pminsn(cpu_env
, t
);
4239 tcg_temp_free_i32(t
);
4240 /* Stop translation, as the CPU is supposed to sleep from now */
4241 gen_exception_nip(ctx
, EXCP_HLT
, ctx
->base
.pc_next
);
4242 #endif /* defined(CONFIG_USER_ONLY) */
4245 static void gen_stop(DisasContext
*ctx
)
4247 #if defined(CONFIG_USER_ONLY)
4253 t
= tcg_const_i32(PPC_PM_STOP
);
4254 gen_helper_pminsn(cpu_env
, t
);
4255 tcg_temp_free_i32(t
);
4256 /* Stop translation, as the CPU is supposed to sleep from now */
4257 gen_exception_nip(ctx
, EXCP_HLT
, ctx
->base
.pc_next
);
4258 #endif /* defined(CONFIG_USER_ONLY) */
4261 static void gen_sleep(DisasContext
*ctx
)
4263 #if defined(CONFIG_USER_ONLY)
4269 t
= tcg_const_i32(PPC_PM_SLEEP
);
4270 gen_helper_pminsn(cpu_env
, t
);
4271 tcg_temp_free_i32(t
);
4272 /* Stop translation, as the CPU is supposed to sleep from now */
4273 gen_exception_nip(ctx
, EXCP_HLT
, ctx
->base
.pc_next
);
4274 #endif /* defined(CONFIG_USER_ONLY) */
4277 static void gen_rvwinkle(DisasContext
*ctx
)
4279 #if defined(CONFIG_USER_ONLY)
4285 t
= tcg_const_i32(PPC_PM_RVWINKLE
);
4286 gen_helper_pminsn(cpu_env
, t
);
4287 tcg_temp_free_i32(t
);
4288 /* Stop translation, as the CPU is supposed to sleep from now */
4289 gen_exception_nip(ctx
, EXCP_HLT
, ctx
->base
.pc_next
);
4290 #endif /* defined(CONFIG_USER_ONLY) */
4292 #endif /* #if defined(TARGET_PPC64) */
4294 static inline void gen_update_cfar(DisasContext
*ctx
, target_ulong nip
)
4296 #if defined(TARGET_PPC64)
4297 if (ctx
->has_cfar
) {
4298 tcg_gen_movi_tl(cpu_cfar
, nip
);
4303 static inline bool use_goto_tb(DisasContext
*ctx
, target_ulong dest
)
4305 if (unlikely(ctx
->singlestep_enabled
)) {
4309 #ifndef CONFIG_USER_ONLY
4310 return (ctx
->base
.tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
4316 static void gen_lookup_and_goto_ptr(DisasContext
*ctx
)
4318 int sse
= ctx
->singlestep_enabled
;
4319 if (unlikely(sse
)) {
4320 if (sse
& GDBSTUB_SINGLE_STEP
) {
4321 gen_debug_exception(ctx
);
4322 } else if (sse
& (CPU_SINGLE_STEP
| CPU_BRANCH_STEP
)) {
4323 gen_helper_raise_exception(cpu_env
, tcg_constant_i32(gen_prep_dbgex(ctx
)));
4325 tcg_gen_exit_tb(NULL
, 0);
4328 tcg_gen_lookup_and_goto_ptr();
4333 static void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
4335 if (NARROW_MODE(ctx
)) {
4336 dest
= (uint32_t) dest
;
4338 if (use_goto_tb(ctx
, dest
)) {
4340 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
4341 tcg_gen_exit_tb(ctx
->base
.tb
, n
);
4343 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
4344 gen_lookup_and_goto_ptr(ctx
);
4348 static inline void gen_setlr(DisasContext
*ctx
, target_ulong nip
)
4350 if (NARROW_MODE(ctx
)) {
4351 nip
= (uint32_t)nip
;
4353 tcg_gen_movi_tl(cpu_lr
, nip
);
4357 static void gen_b(DisasContext
*ctx
)
4359 target_ulong li
, target
;
4361 /* sign extend LI */
4362 li
= LI(ctx
->opcode
);
4363 li
= (li
^ 0x02000000) - 0x02000000;
4364 if (likely(AA(ctx
->opcode
) == 0)) {
4365 target
= ctx
->cia
+ li
;
4369 if (LK(ctx
->opcode
)) {
4370 gen_setlr(ctx
, ctx
->base
.pc_next
);
4372 gen_update_cfar(ctx
, ctx
->cia
);
4373 gen_goto_tb(ctx
, 0, target
);
4374 ctx
->base
.is_jmp
= DISAS_NORETURN
;
4382 static void gen_bcond(DisasContext
*ctx
, int type
)
4384 uint32_t bo
= BO(ctx
->opcode
);
4388 if (type
== BCOND_LR
|| type
== BCOND_CTR
|| type
== BCOND_TAR
) {
4389 target
= tcg_temp_local_new();
4390 if (type
== BCOND_CTR
) {
4391 tcg_gen_mov_tl(target
, cpu_ctr
);
4392 } else if (type
== BCOND_TAR
) {
4393 gen_load_spr(target
, SPR_TAR
);
4395 tcg_gen_mov_tl(target
, cpu_lr
);
4400 if (LK(ctx
->opcode
)) {
4401 gen_setlr(ctx
, ctx
->base
.pc_next
);
4403 l1
= gen_new_label();
4404 if ((bo
& 0x4) == 0) {
4405 /* Decrement and test CTR */
4406 TCGv temp
= tcg_temp_new();
4408 if (type
== BCOND_CTR
) {
4410 * All ISAs up to v3 describe this form of bcctr as invalid but
4411 * some processors, ie. 64-bit server processors compliant with
4412 * arch 2.x, do implement a "test and decrement" logic instead,
4413 * as described in their respective UMs. This logic involves CTR
4414 * to act as both the branch target and a counter, which makes
4415 * it basically useless and thus never used in real code.
4417 * This form was hence chosen to trigger extra micro-architectural
4418 * side-effect on real HW needed for the Spectre v2 workaround.
4419 * It is up to guests that implement such workaround, ie. linux, to
4420 * use this form in a way it just triggers the side-effect without
4421 * doing anything else harmful.
4423 if (unlikely(!is_book3s_arch2x(ctx
))) {
4424 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
4425 tcg_temp_free(temp
);
4426 tcg_temp_free(target
);
4430 if (NARROW_MODE(ctx
)) {
4431 tcg_gen_ext32u_tl(temp
, cpu_ctr
);
4433 tcg_gen_mov_tl(temp
, cpu_ctr
);
4436 tcg_gen_brcondi_tl(TCG_COND_NE
, temp
, 0, l1
);
4438 tcg_gen_brcondi_tl(TCG_COND_EQ
, temp
, 0, l1
);
4440 tcg_gen_subi_tl(cpu_ctr
, cpu_ctr
, 1);
4442 tcg_gen_subi_tl(cpu_ctr
, cpu_ctr
, 1);
4443 if (NARROW_MODE(ctx
)) {
4444 tcg_gen_ext32u_tl(temp
, cpu_ctr
);
4446 tcg_gen_mov_tl(temp
, cpu_ctr
);
4449 tcg_gen_brcondi_tl(TCG_COND_NE
, temp
, 0, l1
);
4451 tcg_gen_brcondi_tl(TCG_COND_EQ
, temp
, 0, l1
);
4454 tcg_temp_free(temp
);
4456 if ((bo
& 0x10) == 0) {
4458 uint32_t bi
= BI(ctx
->opcode
);
4459 uint32_t mask
= 0x08 >> (bi
& 0x03);
4460 TCGv_i32 temp
= tcg_temp_new_i32();
4463 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
4464 tcg_gen_brcondi_i32(TCG_COND_EQ
, temp
, 0, l1
);
4466 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
4467 tcg_gen_brcondi_i32(TCG_COND_NE
, temp
, 0, l1
);
4469 tcg_temp_free_i32(temp
);
4471 gen_update_cfar(ctx
, ctx
->cia
);
4472 if (type
== BCOND_IM
) {
4473 target_ulong li
= (target_long
)((int16_t)(BD(ctx
->opcode
)));
4474 if (likely(AA(ctx
->opcode
) == 0)) {
4475 gen_goto_tb(ctx
, 0, ctx
->cia
+ li
);
4477 gen_goto_tb(ctx
, 0, li
);
4480 if (NARROW_MODE(ctx
)) {
4481 tcg_gen_andi_tl(cpu_nip
, target
, (uint32_t)~3);
4483 tcg_gen_andi_tl(cpu_nip
, target
, ~3);
4485 gen_lookup_and_goto_ptr(ctx
);
4486 tcg_temp_free(target
);
4488 if ((bo
& 0x14) != 0x14) {
4489 /* fallthrough case */
4491 gen_goto_tb(ctx
, 1, ctx
->base
.pc_next
);
4493 ctx
->base
.is_jmp
= DISAS_NORETURN
;
4496 static void gen_bc(DisasContext
*ctx
)
4498 gen_bcond(ctx
, BCOND_IM
);
4501 static void gen_bcctr(DisasContext
*ctx
)
4503 gen_bcond(ctx
, BCOND_CTR
);
4506 static void gen_bclr(DisasContext
*ctx
)
4508 gen_bcond(ctx
, BCOND_LR
);
4511 static void gen_bctar(DisasContext
*ctx
)
4513 gen_bcond(ctx
, BCOND_TAR
);
4516 /*** Condition register logical ***/
4517 #define GEN_CRLOGIC(name, tcg_op, opc) \
4518 static void glue(gen_, name)(DisasContext *ctx) \
4523 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
4524 t0 = tcg_temp_new_i32(); \
4526 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
4528 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
4530 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
4531 t1 = tcg_temp_new_i32(); \
4532 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
4534 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
4536 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
4538 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
4539 tcg_op(t0, t0, t1); \
4540 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
4541 tcg_gen_andi_i32(t0, t0, bitmask); \
4542 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
4543 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
4544 tcg_temp_free_i32(t0); \
4545 tcg_temp_free_i32(t1); \
4549 GEN_CRLOGIC(crand
, tcg_gen_and_i32
, 0x08);
4551 GEN_CRLOGIC(crandc
, tcg_gen_andc_i32
, 0x04);
4553 GEN_CRLOGIC(creqv
, tcg_gen_eqv_i32
, 0x09);
4555 GEN_CRLOGIC(crnand
, tcg_gen_nand_i32
, 0x07);
4557 GEN_CRLOGIC(crnor
, tcg_gen_nor_i32
, 0x01);
4559 GEN_CRLOGIC(cror
, tcg_gen_or_i32
, 0x0E);
4561 GEN_CRLOGIC(crorc
, tcg_gen_orc_i32
, 0x0D);
4563 GEN_CRLOGIC(crxor
, tcg_gen_xor_i32
, 0x06);
4566 static void gen_mcrf(DisasContext
*ctx
)
4568 tcg_gen_mov_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_crf
[crfS(ctx
->opcode
)]);
4571 /*** System linkage ***/
4573 /* rfi (supervisor only) */
4574 static void gen_rfi(DisasContext
*ctx
)
4576 #if defined(CONFIG_USER_ONLY)
4580 * This instruction doesn't exist anymore on 64-bit server
4581 * processors compliant with arch 2.x
4583 if (is_book3s_arch2x(ctx
)) {
4584 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
4587 /* Restore CPU state */
4589 gen_icount_io_start(ctx
);
4590 gen_update_cfar(ctx
, ctx
->cia
);
4591 gen_helper_rfi(cpu_env
);
4592 ctx
->base
.is_jmp
= DISAS_EXIT
;
4596 #if defined(TARGET_PPC64)
4597 static void gen_rfid(DisasContext
*ctx
)
4599 #if defined(CONFIG_USER_ONLY)
4602 /* Restore CPU state */
4604 gen_icount_io_start(ctx
);
4605 gen_update_cfar(ctx
, ctx
->cia
);
4606 gen_helper_rfid(cpu_env
);
4607 ctx
->base
.is_jmp
= DISAS_EXIT
;
4611 #if !defined(CONFIG_USER_ONLY)
4612 static void gen_rfscv(DisasContext
*ctx
)
4614 #if defined(CONFIG_USER_ONLY)
4617 /* Restore CPU state */
4619 gen_icount_io_start(ctx
);
4620 gen_update_cfar(ctx
, ctx
->cia
);
4621 gen_helper_rfscv(cpu_env
);
4622 ctx
->base
.is_jmp
= DISAS_EXIT
;
4627 static void gen_hrfid(DisasContext
*ctx
)
4629 #if defined(CONFIG_USER_ONLY)
4632 /* Restore CPU state */
4634 gen_helper_hrfid(cpu_env
);
4635 ctx
->base
.is_jmp
= DISAS_EXIT
;
4641 #if defined(CONFIG_USER_ONLY)
4642 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4644 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4645 #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED
4647 static void gen_sc(DisasContext
*ctx
)
4651 lev
= (ctx
->opcode
>> 5) & 0x7F;
4652 gen_exception_err(ctx
, POWERPC_SYSCALL
, lev
);
4655 #if defined(TARGET_PPC64)
4656 #if !defined(CONFIG_USER_ONLY)
4657 static void gen_scv(DisasContext
*ctx
)
4659 uint32_t lev
= (ctx
->opcode
>> 5) & 0x7F;
4661 /* Set the PC back to the faulting instruction. */
4662 gen_update_nip(ctx
, ctx
->cia
);
4663 gen_helper_scv(cpu_env
, tcg_constant_i32(lev
));
4665 ctx
->base
.is_jmp
= DISAS_NORETURN
;
4672 /* Check for unconditional traps (always or never) */
4673 static bool check_unconditional_trap(DisasContext
*ctx
)
4676 if (TO(ctx
->opcode
) == 0) {
4680 if (TO(ctx
->opcode
) == 31) {
4681 gen_exception_err(ctx
, POWERPC_EXCP_PROGRAM
, POWERPC_EXCP_TRAP
);
4688 static void gen_tw(DisasContext
*ctx
)
4692 if (check_unconditional_trap(ctx
)) {
4695 t0
= tcg_const_i32(TO(ctx
->opcode
));
4696 gen_helper_tw(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
4698 tcg_temp_free_i32(t0
);
4702 static void gen_twi(DisasContext
*ctx
)
4707 if (check_unconditional_trap(ctx
)) {
4710 t0
= tcg_const_tl(SIMM(ctx
->opcode
));
4711 t1
= tcg_const_i32(TO(ctx
->opcode
));
4712 gen_helper_tw(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4714 tcg_temp_free_i32(t1
);
4717 #if defined(TARGET_PPC64)
4719 static void gen_td(DisasContext
*ctx
)
4723 if (check_unconditional_trap(ctx
)) {
4726 t0
= tcg_const_i32(TO(ctx
->opcode
));
4727 gen_helper_td(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
4729 tcg_temp_free_i32(t0
);
4733 static void gen_tdi(DisasContext
*ctx
)
4738 if (check_unconditional_trap(ctx
)) {
4741 t0
= tcg_const_tl(SIMM(ctx
->opcode
));
4742 t1
= tcg_const_i32(TO(ctx
->opcode
));
4743 gen_helper_td(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4745 tcg_temp_free_i32(t1
);
4749 /*** Processor control ***/
4752 static void gen_mcrxr(DisasContext
*ctx
)
4754 TCGv_i32 t0
= tcg_temp_new_i32();
4755 TCGv_i32 t1
= tcg_temp_new_i32();
4756 TCGv_i32 dst
= cpu_crf
[crfD(ctx
->opcode
)];
4758 tcg_gen_trunc_tl_i32(t0
, cpu_so
);
4759 tcg_gen_trunc_tl_i32(t1
, cpu_ov
);
4760 tcg_gen_trunc_tl_i32(dst
, cpu_ca
);
4761 tcg_gen_shli_i32(t0
, t0
, 3);
4762 tcg_gen_shli_i32(t1
, t1
, 2);
4763 tcg_gen_shli_i32(dst
, dst
, 1);
4764 tcg_gen_or_i32(dst
, dst
, t0
);
4765 tcg_gen_or_i32(dst
, dst
, t1
);
4766 tcg_temp_free_i32(t0
);
4767 tcg_temp_free_i32(t1
);
4769 tcg_gen_movi_tl(cpu_so
, 0);
4770 tcg_gen_movi_tl(cpu_ov
, 0);
4771 tcg_gen_movi_tl(cpu_ca
, 0);
4776 static void gen_mcrxrx(DisasContext
*ctx
)
4778 TCGv t0
= tcg_temp_new();
4779 TCGv t1
= tcg_temp_new();
4780 TCGv_i32 dst
= cpu_crf
[crfD(ctx
->opcode
)];
4782 /* copy OV and OV32 */
4783 tcg_gen_shli_tl(t0
, cpu_ov
, 1);
4784 tcg_gen_or_tl(t0
, t0
, cpu_ov32
);
4785 tcg_gen_shli_tl(t0
, t0
, 2);
4786 /* copy CA and CA32 */
4787 tcg_gen_shli_tl(t1
, cpu_ca
, 1);
4788 tcg_gen_or_tl(t1
, t1
, cpu_ca32
);
4789 tcg_gen_or_tl(t0
, t0
, t1
);
4790 tcg_gen_trunc_tl_i32(dst
, t0
);
4797 static void gen_mfcr(DisasContext
*ctx
)
4801 if (likely(ctx
->opcode
& 0x00100000)) {
4802 crm
= CRM(ctx
->opcode
);
4803 if (likely(crm
&& ((crm
& (crm
- 1)) == 0))) {
4805 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_crf
[7 - crn
]);
4806 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)],
4807 cpu_gpr
[rD(ctx
->opcode
)], crn
* 4);
4810 TCGv_i32 t0
= tcg_temp_new_i32();
4811 tcg_gen_mov_i32(t0
, cpu_crf
[0]);
4812 tcg_gen_shli_i32(t0
, t0
, 4);
4813 tcg_gen_or_i32(t0
, t0
, cpu_crf
[1]);
4814 tcg_gen_shli_i32(t0
, t0
, 4);
4815 tcg_gen_or_i32(t0
, t0
, cpu_crf
[2]);
4816 tcg_gen_shli_i32(t0
, t0
, 4);
4817 tcg_gen_or_i32(t0
, t0
, cpu_crf
[3]);
4818 tcg_gen_shli_i32(t0
, t0
, 4);
4819 tcg_gen_or_i32(t0
, t0
, cpu_crf
[4]);
4820 tcg_gen_shli_i32(t0
, t0
, 4);
4821 tcg_gen_or_i32(t0
, t0
, cpu_crf
[5]);
4822 tcg_gen_shli_i32(t0
, t0
, 4);
4823 tcg_gen_or_i32(t0
, t0
, cpu_crf
[6]);
4824 tcg_gen_shli_i32(t0
, t0
, 4);
4825 tcg_gen_or_i32(t0
, t0
, cpu_crf
[7]);
4826 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4827 tcg_temp_free_i32(t0
);
4832 static void gen_mfmsr(DisasContext
*ctx
)
4835 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_msr
);
4839 static inline void gen_op_mfspr(DisasContext
*ctx
)
4841 void (*read_cb
)(DisasContext
*ctx
, int gprn
, int sprn
);
4842 uint32_t sprn
= SPR(ctx
->opcode
);
4844 #if defined(CONFIG_USER_ONLY)
4845 read_cb
= ctx
->spr_cb
[sprn
].uea_read
;
4848 read_cb
= ctx
->spr_cb
[sprn
].uea_read
;
4849 } else if (ctx
->hv
) {
4850 read_cb
= ctx
->spr_cb
[sprn
].hea_read
;
4852 read_cb
= ctx
->spr_cb
[sprn
].oea_read
;
4855 if (likely(read_cb
!= NULL
)) {
4856 if (likely(read_cb
!= SPR_NOACCESS
)) {
4857 (*read_cb
)(ctx
, rD(ctx
->opcode
), sprn
);
4859 /* Privilege exception */
4861 * This is a hack to avoid warnings when running Linux:
4862 * this OS breaks the PowerPC virtualisation model,
4863 * allowing userland application to read the PVR
4865 if (sprn
!= SPR_PVR
) {
4866 qemu_log_mask(LOG_GUEST_ERROR
, "Trying to read privileged spr "
4867 "%d (0x%03x) at " TARGET_FMT_lx
"\n", sprn
, sprn
,
4870 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4873 /* ISA 2.07 defines these as no-ops */
4874 if ((ctx
->insns_flags2
& PPC2_ISA207S
) &&
4875 (sprn
>= 808 && sprn
<= 811)) {
4880 qemu_log_mask(LOG_GUEST_ERROR
,
4881 "Trying to read invalid spr %d (0x%03x) at "
4882 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->cia
);
4885 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can
4886 * generate a priv, a hv emu or a no-op
4890 gen_priv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
4893 if (ctx
->pr
|| sprn
== 0 || sprn
== 4 || sprn
== 5 || sprn
== 6) {
4894 gen_hvpriv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
4900 static void gen_mfspr(DisasContext
*ctx
)
4906 static void gen_mftb(DisasContext
*ctx
)
4912 static void gen_mtcrf(DisasContext
*ctx
)
4916 crm
= CRM(ctx
->opcode
);
4917 if (likely((ctx
->opcode
& 0x00100000))) {
4918 if (crm
&& ((crm
& (crm
- 1)) == 0)) {
4919 TCGv_i32 temp
= tcg_temp_new_i32();
4921 tcg_gen_trunc_tl_i32(temp
, cpu_gpr
[rS(ctx
->opcode
)]);
4922 tcg_gen_shri_i32(temp
, temp
, crn
* 4);
4923 tcg_gen_andi_i32(cpu_crf
[7 - crn
], temp
, 0xf);
4924 tcg_temp_free_i32(temp
);
4927 TCGv_i32 temp
= tcg_temp_new_i32();
4928 tcg_gen_trunc_tl_i32(temp
, cpu_gpr
[rS(ctx
->opcode
)]);
4929 for (crn
= 0 ; crn
< 8 ; crn
++) {
4930 if (crm
& (1 << crn
)) {
4931 tcg_gen_shri_i32(cpu_crf
[7 - crn
], temp
, crn
* 4);
4932 tcg_gen_andi_i32(cpu_crf
[7 - crn
], cpu_crf
[7 - crn
], 0xf);
4935 tcg_temp_free_i32(temp
);
4940 #if defined(TARGET_PPC64)
4941 static void gen_mtmsrd(DisasContext
*ctx
)
4945 #if !defined(CONFIG_USER_ONLY)
4946 gen_icount_io_start(ctx
);
4947 if (ctx
->opcode
& 0x00010000) {
4948 /* L=1 form only updates EE and RI */
4949 TCGv t0
= tcg_temp_new();
4950 TCGv t1
= tcg_temp_new();
4951 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)],
4952 (1 << MSR_RI
) | (1 << MSR_EE
));
4953 tcg_gen_andi_tl(t1
, cpu_msr
,
4954 ~(target_ulong
)((1 << MSR_RI
) | (1 << MSR_EE
)));
4955 tcg_gen_or_tl(t1
, t1
, t0
);
4957 gen_helper_store_msr(cpu_env
, t1
);
4963 * XXX: we need to update nip before the store if we enter
4964 * power saving mode, we will exit the loop directly from
4967 gen_update_nip(ctx
, ctx
->base
.pc_next
);
4968 gen_helper_store_msr(cpu_env
, cpu_gpr
[rS(ctx
->opcode
)]);
4970 /* Must stop the translation as machine state (may have) changed */
4971 ctx
->base
.is_jmp
= DISAS_EXIT_UPDATE
;
4972 #endif /* !defined(CONFIG_USER_ONLY) */
4974 #endif /* defined(TARGET_PPC64) */
4976 static void gen_mtmsr(DisasContext
*ctx
)
4980 #if !defined(CONFIG_USER_ONLY)
4981 gen_icount_io_start(ctx
);
4982 if (ctx
->opcode
& 0x00010000) {
4983 /* L=1 form only updates EE and RI */
4984 TCGv t0
= tcg_temp_new();
4985 TCGv t1
= tcg_temp_new();
4986 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)],
4987 (1 << MSR_RI
) | (1 << MSR_EE
));
4988 tcg_gen_andi_tl(t1
, cpu_msr
,
4989 ~(target_ulong
)((1 << MSR_RI
) | (1 << MSR_EE
)));
4990 tcg_gen_or_tl(t1
, t1
, t0
);
4992 gen_helper_store_msr(cpu_env
, t1
);
4997 TCGv msr
= tcg_temp_new();
5000 * XXX: we need to update nip before the store if we enter
5001 * power saving mode, we will exit the loop directly from
5004 gen_update_nip(ctx
, ctx
->base
.pc_next
);
5005 #if defined(TARGET_PPC64)
5006 tcg_gen_deposit_tl(msr
, cpu_msr
, cpu_gpr
[rS(ctx
->opcode
)], 0, 32);
5008 tcg_gen_mov_tl(msr
, cpu_gpr
[rS(ctx
->opcode
)]);
5010 gen_helper_store_msr(cpu_env
, msr
);
5013 /* Must stop the translation as machine state (may have) changed */
5014 ctx
->base
.is_jmp
= DISAS_EXIT_UPDATE
;
5019 static void gen_mtspr(DisasContext
*ctx
)
5021 void (*write_cb
)(DisasContext
*ctx
, int sprn
, int gprn
);
5022 uint32_t sprn
= SPR(ctx
->opcode
);
5024 #if defined(CONFIG_USER_ONLY)
5025 write_cb
= ctx
->spr_cb
[sprn
].uea_write
;
5028 write_cb
= ctx
->spr_cb
[sprn
].uea_write
;
5029 } else if (ctx
->hv
) {
5030 write_cb
= ctx
->spr_cb
[sprn
].hea_write
;
5032 write_cb
= ctx
->spr_cb
[sprn
].oea_write
;
5035 if (likely(write_cb
!= NULL
)) {
5036 if (likely(write_cb
!= SPR_NOACCESS
)) {
5037 (*write_cb
)(ctx
, sprn
, rS(ctx
->opcode
));
5039 /* Privilege exception */
5040 qemu_log_mask(LOG_GUEST_ERROR
, "Trying to write privileged spr "
5041 "%d (0x%03x) at " TARGET_FMT_lx
"\n", sprn
, sprn
,
5043 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5046 /* ISA 2.07 defines these as no-ops */
5047 if ((ctx
->insns_flags2
& PPC2_ISA207S
) &&
5048 (sprn
>= 808 && sprn
<= 811)) {
5054 qemu_log_mask(LOG_GUEST_ERROR
,
5055 "Trying to write invalid spr %d (0x%03x) at "
5056 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->cia
);
5060 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can
5061 * generate a priv, a hv emu or a no-op
5065 gen_priv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
5068 if (ctx
->pr
|| sprn
== 0) {
5069 gen_hvpriv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
5075 #if defined(TARGET_PPC64)
5077 static void gen_setb(DisasContext
*ctx
)
5079 TCGv_i32 t0
= tcg_temp_new_i32();
5080 TCGv_i32 t8
= tcg_temp_new_i32();
5081 TCGv_i32 tm1
= tcg_temp_new_i32();
5082 int crf
= crfS(ctx
->opcode
);
5084 tcg_gen_setcondi_i32(TCG_COND_GEU
, t0
, cpu_crf
[crf
], 4);
5085 tcg_gen_movi_i32(t8
, 8);
5086 tcg_gen_movi_i32(tm1
, -1);
5087 tcg_gen_movcond_i32(TCG_COND_GEU
, t0
, cpu_crf
[crf
], t8
, tm1
, t0
);
5088 tcg_gen_ext_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
5090 tcg_temp_free_i32(t0
);
5091 tcg_temp_free_i32(t8
);
5092 tcg_temp_free_i32(tm1
);
5096 /*** Cache management ***/
5099 static void gen_dcbf(DisasContext
*ctx
)
5101 /* XXX: specification says this is treated as a load by the MMU */
5103 gen_set_access_type(ctx
, ACCESS_CACHE
);
5104 t0
= tcg_temp_new();
5105 gen_addr_reg_index(ctx
, t0
);
5106 gen_qemu_ld8u(ctx
, t0
, t0
);
5110 /* dcbfep (external PID dcbf) */
5111 static void gen_dcbfep(DisasContext
*ctx
)
5113 /* XXX: specification says this is treated as a load by the MMU */
5116 gen_set_access_type(ctx
, ACCESS_CACHE
);
5117 t0
= tcg_temp_new();
5118 gen_addr_reg_index(ctx
, t0
);
5119 tcg_gen_qemu_ld_tl(t0
, t0
, PPC_TLB_EPID_LOAD
, DEF_MEMOP(MO_UB
));
5123 /* dcbi (Supervisor only) */
5124 static void gen_dcbi(DisasContext
*ctx
)
5126 #if defined(CONFIG_USER_ONLY)
5132 EA
= tcg_temp_new();
5133 gen_set_access_type(ctx
, ACCESS_CACHE
);
5134 gen_addr_reg_index(ctx
, EA
);
5135 val
= tcg_temp_new();
5136 /* XXX: specification says this should be treated as a store by the MMU */
5137 gen_qemu_ld8u(ctx
, val
, EA
);
5138 gen_qemu_st8(ctx
, val
, EA
);
5141 #endif /* defined(CONFIG_USER_ONLY) */
5145 static void gen_dcbst(DisasContext
*ctx
)
5147 /* XXX: specification say this is treated as a load by the MMU */
5149 gen_set_access_type(ctx
, ACCESS_CACHE
);
5150 t0
= tcg_temp_new();
5151 gen_addr_reg_index(ctx
, t0
);
5152 gen_qemu_ld8u(ctx
, t0
, t0
);
5156 /* dcbstep (dcbstep External PID version) */
5157 static void gen_dcbstep(DisasContext
*ctx
)
5159 /* XXX: specification say this is treated as a load by the MMU */
5161 gen_set_access_type(ctx
, ACCESS_CACHE
);
5162 t0
= tcg_temp_new();
5163 gen_addr_reg_index(ctx
, t0
);
5164 tcg_gen_qemu_ld_tl(t0
, t0
, PPC_TLB_EPID_LOAD
, DEF_MEMOP(MO_UB
));
5169 static void gen_dcbt(DisasContext
*ctx
)
5172 * interpreted as no-op
5173 * XXX: specification say this is treated as a load by the MMU but
5174 * does not generate any exception
5179 static void gen_dcbtep(DisasContext
*ctx
)
5182 * interpreted as no-op
5183 * XXX: specification say this is treated as a load by the MMU but
5184 * does not generate any exception
5189 static void gen_dcbtst(DisasContext
*ctx
)
5192 * interpreted as no-op
5193 * XXX: specification say this is treated as a load by the MMU but
5194 * does not generate any exception
5199 static void gen_dcbtstep(DisasContext
*ctx
)
5202 * interpreted as no-op
5203 * XXX: specification say this is treated as a load by the MMU but
5204 * does not generate any exception
5209 static void gen_dcbtls(DisasContext
*ctx
)
5211 /* Always fails locking the cache */
5212 TCGv t0
= tcg_temp_new();
5213 gen_load_spr(t0
, SPR_Exxx_L1CSR0
);
5214 tcg_gen_ori_tl(t0
, t0
, L1CSR0_CUL
);
5215 gen_store_spr(SPR_Exxx_L1CSR0
, t0
);
5220 static void gen_dcbz(DisasContext
*ctx
)
5225 gen_set_access_type(ctx
, ACCESS_CACHE
);
5226 tcgv_addr
= tcg_temp_new();
5227 tcgv_op
= tcg_const_i32(ctx
->opcode
& 0x03FF000);
5228 gen_addr_reg_index(ctx
, tcgv_addr
);
5229 gen_helper_dcbz(cpu_env
, tcgv_addr
, tcgv_op
);
5230 tcg_temp_free(tcgv_addr
);
5231 tcg_temp_free_i32(tcgv_op
);
5235 static void gen_dcbzep(DisasContext
*ctx
)
5240 gen_set_access_type(ctx
, ACCESS_CACHE
);
5241 tcgv_addr
= tcg_temp_new();
5242 tcgv_op
= tcg_const_i32(ctx
->opcode
& 0x03FF000);
5243 gen_addr_reg_index(ctx
, tcgv_addr
);
5244 gen_helper_dcbzep(cpu_env
, tcgv_addr
, tcgv_op
);
5245 tcg_temp_free(tcgv_addr
);
5246 tcg_temp_free_i32(tcgv_op
);
5250 static void gen_dst(DisasContext
*ctx
)
5252 if (rA(ctx
->opcode
) == 0) {
5253 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5255 /* interpreted as no-op */
5260 static void gen_dstst(DisasContext
*ctx
)
5262 if (rA(ctx
->opcode
) == 0) {
5263 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5265 /* interpreted as no-op */
5271 static void gen_dss(DisasContext
*ctx
)
5273 /* interpreted as no-op */
5277 static void gen_icbi(DisasContext
*ctx
)
5280 gen_set_access_type(ctx
, ACCESS_CACHE
);
5281 t0
= tcg_temp_new();
5282 gen_addr_reg_index(ctx
, t0
);
5283 gen_helper_icbi(cpu_env
, t0
);
5288 static void gen_icbiep(DisasContext
*ctx
)
5291 gen_set_access_type(ctx
, ACCESS_CACHE
);
5292 t0
= tcg_temp_new();
5293 gen_addr_reg_index(ctx
, t0
);
5294 gen_helper_icbiep(cpu_env
, t0
);
5300 static void gen_dcba(DisasContext
*ctx
)
5303 * interpreted as no-op
5304 * XXX: specification say this is treated as a store by the MMU
5305 * but does not generate any exception
5309 /*** Segment register manipulation ***/
5310 /* Supervisor only: */
5313 static void gen_mfsr(DisasContext
*ctx
)
5315 #if defined(CONFIG_USER_ONLY)
5321 t0
= tcg_const_tl(SR(ctx
->opcode
));
5322 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
5324 #endif /* defined(CONFIG_USER_ONLY) */
5328 static void gen_mfsrin(DisasContext
*ctx
)
5330 #if defined(CONFIG_USER_ONLY)
5336 t0
= tcg_temp_new();
5337 tcg_gen_extract_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28, 4);
5338 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
5340 #endif /* defined(CONFIG_USER_ONLY) */
5344 static void gen_mtsr(DisasContext
*ctx
)
5346 #if defined(CONFIG_USER_ONLY)
5352 t0
= tcg_const_tl(SR(ctx
->opcode
));
5353 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
5355 #endif /* defined(CONFIG_USER_ONLY) */
5359 static void gen_mtsrin(DisasContext
*ctx
)
5361 #if defined(CONFIG_USER_ONLY)
5367 t0
= tcg_temp_new();
5368 tcg_gen_extract_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28, 4);
5369 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rD(ctx
->opcode
)]);
5371 #endif /* defined(CONFIG_USER_ONLY) */
5374 #if defined(TARGET_PPC64)
5375 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
5378 static void gen_mfsr_64b(DisasContext
*ctx
)
5380 #if defined(CONFIG_USER_ONLY)
5386 t0
= tcg_const_tl(SR(ctx
->opcode
));
5387 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
5389 #endif /* defined(CONFIG_USER_ONLY) */
5393 static void gen_mfsrin_64b(DisasContext
*ctx
)
5395 #if defined(CONFIG_USER_ONLY)
5401 t0
= tcg_temp_new();
5402 tcg_gen_extract_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28, 4);
5403 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
5405 #endif /* defined(CONFIG_USER_ONLY) */
5409 static void gen_mtsr_64b(DisasContext
*ctx
)
5411 #if defined(CONFIG_USER_ONLY)
5417 t0
= tcg_const_tl(SR(ctx
->opcode
));
5418 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
5420 #endif /* defined(CONFIG_USER_ONLY) */
5424 static void gen_mtsrin_64b(DisasContext
*ctx
)
5426 #if defined(CONFIG_USER_ONLY)
5432 t0
= tcg_temp_new();
5433 tcg_gen_extract_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28, 4);
5434 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
5436 #endif /* defined(CONFIG_USER_ONLY) */
5440 static void gen_slbmte(DisasContext
*ctx
)
5442 #if defined(CONFIG_USER_ONLY)
5447 gen_helper_store_slb(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)],
5448 cpu_gpr
[rS(ctx
->opcode
)]);
5449 #endif /* defined(CONFIG_USER_ONLY) */
5452 static void gen_slbmfee(DisasContext
*ctx
)
5454 #if defined(CONFIG_USER_ONLY)
5459 gen_helper_load_slb_esid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
5460 cpu_gpr
[rB(ctx
->opcode
)]);
5461 #endif /* defined(CONFIG_USER_ONLY) */
5464 static void gen_slbmfev(DisasContext
*ctx
)
5466 #if defined(CONFIG_USER_ONLY)
5471 gen_helper_load_slb_vsid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
5472 cpu_gpr
[rB(ctx
->opcode
)]);
5473 #endif /* defined(CONFIG_USER_ONLY) */
5476 static void gen_slbfee_(DisasContext
*ctx
)
5478 #if defined(CONFIG_USER_ONLY)
5479 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5483 if (unlikely(ctx
->pr
)) {
5484 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5487 gen_helper_find_slb_vsid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
5488 cpu_gpr
[rB(ctx
->opcode
)]);
5489 l1
= gen_new_label();
5490 l2
= gen_new_label();
5491 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
5492 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rS(ctx
->opcode
)], -1, l1
);
5493 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], CRF_EQ
);
5496 tcg_gen_movi_tl(cpu_gpr
[rS(ctx
->opcode
)], 0);
5500 #endif /* defined(TARGET_PPC64) */
5502 /*** Lookaside buffer management ***/
5503 /* Optional & supervisor only: */
5506 static void gen_tlbia(DisasContext
*ctx
)
5508 #if defined(CONFIG_USER_ONLY)
5513 gen_helper_tlbia(cpu_env
);
5514 #endif /* defined(CONFIG_USER_ONLY) */
5518 static void gen_tlbiel(DisasContext
*ctx
)
5520 #if defined(CONFIG_USER_ONLY)
5525 gen_helper_tlbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5526 #endif /* defined(CONFIG_USER_ONLY) */
5530 static void gen_tlbie(DisasContext
*ctx
)
5532 #if defined(CONFIG_USER_ONLY)
5538 CHK_SV
; /* If gtse is set then tlbie is supervisor privileged */
5540 CHK_HV
; /* Else hypervisor privileged */
5543 if (NARROW_MODE(ctx
)) {
5544 TCGv t0
= tcg_temp_new();
5545 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)]);
5546 gen_helper_tlbie(cpu_env
, t0
);
5549 gen_helper_tlbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5551 t1
= tcg_temp_new_i32();
5552 tcg_gen_ld_i32(t1
, cpu_env
, offsetof(CPUPPCState
, tlb_need_flush
));
5553 tcg_gen_ori_i32(t1
, t1
, TLB_NEED_GLOBAL_FLUSH
);
5554 tcg_gen_st_i32(t1
, cpu_env
, offsetof(CPUPPCState
, tlb_need_flush
));
5555 tcg_temp_free_i32(t1
);
5556 #endif /* defined(CONFIG_USER_ONLY) */
5560 static void gen_tlbsync(DisasContext
*ctx
)
5562 #if defined(CONFIG_USER_ONLY)
5567 CHK_SV
; /* If gtse is set then tlbsync is supervisor privileged */
5569 CHK_HV
; /* Else hypervisor privileged */
5572 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */
5573 if (ctx
->insns_flags
& PPC_BOOKE
) {
5574 gen_check_tlb_flush(ctx
, true);
5576 #endif /* defined(CONFIG_USER_ONLY) */
5579 #if defined(TARGET_PPC64)
5581 static void gen_slbia(DisasContext
*ctx
)
5583 #if defined(CONFIG_USER_ONLY)
5586 uint32_t ih
= (ctx
->opcode
>> 21) & 0x7;
5587 TCGv_i32 t0
= tcg_const_i32(ih
);
5591 gen_helper_slbia(cpu_env
, t0
);
5592 tcg_temp_free_i32(t0
);
5593 #endif /* defined(CONFIG_USER_ONLY) */
5597 static void gen_slbie(DisasContext
*ctx
)
5599 #if defined(CONFIG_USER_ONLY)
5604 gen_helper_slbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5605 #endif /* defined(CONFIG_USER_ONLY) */
5609 static void gen_slbieg(DisasContext
*ctx
)
5611 #if defined(CONFIG_USER_ONLY)
5616 gen_helper_slbieg(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5617 #endif /* defined(CONFIG_USER_ONLY) */
5621 static void gen_slbsync(DisasContext
*ctx
)
5623 #if defined(CONFIG_USER_ONLY)
5627 gen_check_tlb_flush(ctx
, true);
5628 #endif /* defined(CONFIG_USER_ONLY) */
5631 #endif /* defined(TARGET_PPC64) */
5633 /*** External control ***/
5637 static void gen_eciwx(DisasContext
*ctx
)
5640 /* Should check EAR[E] ! */
5641 gen_set_access_type(ctx
, ACCESS_EXT
);
5642 t0
= tcg_temp_new();
5643 gen_addr_reg_index(ctx
, t0
);
5644 tcg_gen_qemu_ld_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, ctx
->mem_idx
,
5645 DEF_MEMOP(MO_UL
| MO_ALIGN
));
5650 static void gen_ecowx(DisasContext
*ctx
)
5653 /* Should check EAR[E] ! */
5654 gen_set_access_type(ctx
, ACCESS_EXT
);
5655 t0
= tcg_temp_new();
5656 gen_addr_reg_index(ctx
, t0
);
5657 tcg_gen_qemu_st_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, ctx
->mem_idx
,
5658 DEF_MEMOP(MO_UL
| MO_ALIGN
));
5662 /* PowerPC 601 specific instructions */
5665 static void gen_abs(DisasContext
*ctx
)
5667 TCGv d
= cpu_gpr
[rD(ctx
->opcode
)];
5668 TCGv a
= cpu_gpr
[rA(ctx
->opcode
)];
5670 tcg_gen_abs_tl(d
, a
);
5671 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5672 gen_set_Rc0(ctx
, d
);
5677 static void gen_abso(DisasContext
*ctx
)
5679 TCGv d
= cpu_gpr
[rD(ctx
->opcode
)];
5680 TCGv a
= cpu_gpr
[rA(ctx
->opcode
)];
5682 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_ov
, a
, 0x80000000);
5683 tcg_gen_abs_tl(d
, a
);
5684 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
5685 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5686 gen_set_Rc0(ctx
, d
);
5691 static void gen_clcs(DisasContext
*ctx
)
5693 TCGv_i32 t0
= tcg_const_i32(rA(ctx
->opcode
));
5694 gen_helper_clcs(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
5695 tcg_temp_free_i32(t0
);
5696 /* Rc=1 sets CR0 to an undefined state */
5700 static void gen_div(DisasContext
*ctx
)
5702 gen_helper_div(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5703 cpu_gpr
[rB(ctx
->opcode
)]);
5704 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5705 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5710 static void gen_divo(DisasContext
*ctx
)
5712 gen_helper_divo(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5713 cpu_gpr
[rB(ctx
->opcode
)]);
5714 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5715 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5720 static void gen_divs(DisasContext
*ctx
)
5722 gen_helper_divs(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5723 cpu_gpr
[rB(ctx
->opcode
)]);
5724 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5725 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5729 /* divso - divso. */
5730 static void gen_divso(DisasContext
*ctx
)
5732 gen_helper_divso(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5733 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
5734 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5735 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5740 static void gen_doz(DisasContext
*ctx
)
5742 TCGLabel
*l1
= gen_new_label();
5743 TCGLabel
*l2
= gen_new_label();
5744 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)],
5745 cpu_gpr
[rA(ctx
->opcode
)], l1
);
5746 tcg_gen_sub_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
5747 cpu_gpr
[rA(ctx
->opcode
)]);
5750 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
5752 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5753 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5758 static void gen_dozo(DisasContext
*ctx
)
5760 TCGLabel
*l1
= gen_new_label();
5761 TCGLabel
*l2
= gen_new_label();
5762 TCGv t0
= tcg_temp_new();
5763 TCGv t1
= tcg_temp_new();
5764 TCGv t2
= tcg_temp_new();
5765 /* Start with XER OV disabled, the most likely case */
5766 tcg_gen_movi_tl(cpu_ov
, 0);
5767 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)],
5768 cpu_gpr
[rA(ctx
->opcode
)], l1
);
5769 tcg_gen_sub_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5770 tcg_gen_xor_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5771 tcg_gen_xor_tl(t2
, cpu_gpr
[rA(ctx
->opcode
)], t0
);
5772 tcg_gen_andc_tl(t1
, t1
, t2
);
5773 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
5774 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
5775 tcg_gen_movi_tl(cpu_ov
, 1);
5776 tcg_gen_movi_tl(cpu_so
, 1);
5779 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
5784 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5785 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5790 static void gen_dozi(DisasContext
*ctx
)
5792 target_long simm
= SIMM(ctx
->opcode
);
5793 TCGLabel
*l1
= gen_new_label();
5794 TCGLabel
*l2
= gen_new_label();
5795 tcg_gen_brcondi_tl(TCG_COND_LT
, cpu_gpr
[rA(ctx
->opcode
)], simm
, l1
);
5796 tcg_gen_subfi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
, cpu_gpr
[rA(ctx
->opcode
)]);
5799 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
5801 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5802 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5806 /* lscbx - lscbx. */
5807 static void gen_lscbx(DisasContext
*ctx
)
5809 TCGv t0
= tcg_temp_new();
5810 TCGv_i32 t1
= tcg_const_i32(rD(ctx
->opcode
));
5811 TCGv_i32 t2
= tcg_const_i32(rA(ctx
->opcode
));
5812 TCGv_i32 t3
= tcg_const_i32(rB(ctx
->opcode
));
5814 gen_addr_reg_index(ctx
, t0
);
5815 gen_helper_lscbx(t0
, cpu_env
, t0
, t1
, t2
, t3
);
5816 tcg_temp_free_i32(t1
);
5817 tcg_temp_free_i32(t2
);
5818 tcg_temp_free_i32(t3
);
5819 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~0x7F);
5820 tcg_gen_or_tl(cpu_xer
, cpu_xer
, t0
);
5821 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5822 gen_set_Rc0(ctx
, t0
);
5827 /* maskg - maskg. */
5828 static void gen_maskg(DisasContext
*ctx
)
5830 TCGLabel
*l1
= gen_new_label();
5831 TCGv t0
= tcg_temp_new();
5832 TCGv t1
= tcg_temp_new();
5833 TCGv t2
= tcg_temp_new();
5834 TCGv t3
= tcg_temp_new();
5835 tcg_gen_movi_tl(t3
, 0xFFFFFFFF);
5836 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5837 tcg_gen_andi_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 0x1F);
5838 tcg_gen_addi_tl(t2
, t0
, 1);
5839 tcg_gen_shr_tl(t2
, t3
, t2
);
5840 tcg_gen_shr_tl(t3
, t3
, t1
);
5841 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], t2
, t3
);
5842 tcg_gen_brcond_tl(TCG_COND_GE
, t0
, t1
, l1
);
5843 tcg_gen_neg_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5849 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5850 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5854 /* maskir - maskir. */
5855 static void gen_maskir(DisasContext
*ctx
)
5857 TCGv t0
= tcg_temp_new();
5858 TCGv t1
= tcg_temp_new();
5859 tcg_gen_and_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
5860 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
5861 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5864 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5865 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5870 static void gen_mul(DisasContext
*ctx
)
5872 TCGv_i64 t0
= tcg_temp_new_i64();
5873 TCGv_i64 t1
= tcg_temp_new_i64();
5874 TCGv t2
= tcg_temp_new();
5875 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
5876 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
5877 tcg_gen_mul_i64(t0
, t0
, t1
);
5878 tcg_gen_trunc_i64_tl(t2
, t0
);
5879 gen_store_spr(SPR_MQ
, t2
);
5880 tcg_gen_shri_i64(t1
, t0
, 32);
5881 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
5882 tcg_temp_free_i64(t0
);
5883 tcg_temp_free_i64(t1
);
5885 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5886 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5891 static void gen_mulo(DisasContext
*ctx
)
5893 TCGLabel
*l1
= gen_new_label();
5894 TCGv_i64 t0
= tcg_temp_new_i64();
5895 TCGv_i64 t1
= tcg_temp_new_i64();
5896 TCGv t2
= tcg_temp_new();
5897 /* Start with XER OV disabled, the most likely case */
5898 tcg_gen_movi_tl(cpu_ov
, 0);
5899 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
5900 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
5901 tcg_gen_mul_i64(t0
, t0
, t1
);
5902 tcg_gen_trunc_i64_tl(t2
, t0
);
5903 gen_store_spr(SPR_MQ
, t2
);
5904 tcg_gen_shri_i64(t1
, t0
, 32);
5905 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
5906 tcg_gen_ext32s_i64(t1
, t0
);
5907 tcg_gen_brcond_i64(TCG_COND_EQ
, t0
, t1
, l1
);
5908 tcg_gen_movi_tl(cpu_ov
, 1);
5909 tcg_gen_movi_tl(cpu_so
, 1);
5911 tcg_temp_free_i64(t0
);
5912 tcg_temp_free_i64(t1
);
5914 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5915 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5920 static void gen_nabs(DisasContext
*ctx
)
5922 TCGv d
= cpu_gpr
[rD(ctx
->opcode
)];
5923 TCGv a
= cpu_gpr
[rA(ctx
->opcode
)];
5925 tcg_gen_abs_tl(d
, a
);
5926 tcg_gen_neg_tl(d
, d
);
5927 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5928 gen_set_Rc0(ctx
, d
);
5932 /* nabso - nabso. */
5933 static void gen_nabso(DisasContext
*ctx
)
5935 TCGv d
= cpu_gpr
[rD(ctx
->opcode
)];
5936 TCGv a
= cpu_gpr
[rA(ctx
->opcode
)];
5938 tcg_gen_abs_tl(d
, a
);
5939 tcg_gen_neg_tl(d
, d
);
5940 /* nabs never overflows */
5941 tcg_gen_movi_tl(cpu_ov
, 0);
5942 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5943 gen_set_Rc0(ctx
, d
);
5948 static void gen_rlmi(DisasContext
*ctx
)
5950 uint32_t mb
= MB(ctx
->opcode
);
5951 uint32_t me
= ME(ctx
->opcode
);
5952 TCGv t0
= tcg_temp_new();
5953 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5954 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5955 tcg_gen_andi_tl(t0
, t0
, MASK(mb
, me
));
5956 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
5958 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], t0
);
5960 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5961 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5966 static void gen_rrib(DisasContext
*ctx
)
5968 TCGv t0
= tcg_temp_new();
5969 TCGv t1
= tcg_temp_new();
5970 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5971 tcg_gen_movi_tl(t1
, 0x80000000);
5972 tcg_gen_shr_tl(t1
, t1
, t0
);
5973 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5974 tcg_gen_and_tl(t0
, t0
, t1
);
5975 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], t1
);
5976 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5979 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5980 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5985 static void gen_sle(DisasContext
*ctx
)
5987 TCGv t0
= tcg_temp_new();
5988 TCGv t1
= tcg_temp_new();
5989 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5990 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5991 tcg_gen_subfi_tl(t1
, 32, t1
);
5992 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5993 tcg_gen_or_tl(t1
, t0
, t1
);
5994 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5995 gen_store_spr(SPR_MQ
, t1
);
5998 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5999 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
6004 static void gen_sleq(DisasContext
*ctx
)
6006 TCGv t0
= tcg_temp_new();
6007 TCGv t1
= tcg_temp_new();
6008 TCGv t2
= tcg_temp_new();
6009 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
6010 tcg_gen_movi_tl(t2
, 0xFFFFFFFF);
6011 tcg_gen_shl_tl(t2
, t2
, t0
);
6012 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
6013 gen_load_spr(t1
, SPR_MQ
);
6014 gen_store_spr(SPR_MQ
, t0
);
6015 tcg_gen_and_tl(t0
, t0
, t2
);
6016 tcg_gen_andc_tl(t1
, t1
, t2
);
6017 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
6021 if (unlikely(Rc(ctx
->opcode
) != 0)) {
6022 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
6027 static void gen_sliq(DisasContext
*ctx
)
6029 int sh
= SH(ctx
->opcode
);
6030 TCGv t0
= tcg_temp_new();
6031 TCGv t1
= tcg_temp_new();
6032 tcg_gen_shli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
6033 tcg_gen_shri_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
6034 tcg_gen_or_tl(t1
, t0
, t1
);
6035 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
6036 gen_store_spr(SPR_MQ
, t1
);
6039 if (unlikely(Rc(ctx
->opcode
) != 0)) {
6040 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
6044 /* slliq - slliq. */
6045 static void gen_slliq(DisasContext
*ctx
)
6047 int sh
= SH(ctx
->opcode
);
6048 TCGv t0
= tcg_temp_new();
6049 TCGv t1
= tcg_temp_new();
6050 tcg_gen_rotli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
6051 gen_load_spr(t1
, SPR_MQ
);
6052 gen_store_spr(SPR_MQ
, t0
);
6053 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
<< sh
));
6054 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
<< sh
));
6055 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
6058 if (unlikely(Rc(ctx
->opcode
) != 0)) {
6059 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
6064 static void gen_sllq(DisasContext
*ctx
)
6066 TCGLabel
*l1
= gen_new_label();
6067 TCGLabel
*l2
= gen_new_label();
6068 TCGv t0
= tcg_temp_local_new();
6069 TCGv t1
= tcg_temp_local_new();
6070 TCGv t2
= tcg_temp_local_new();
6071 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
6072 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
6073 tcg_gen_shl_tl(t1
, t1
, t2
);
6074 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
6075 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
6076 gen_load_spr(t0
, SPR_MQ
);
6077 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
6080 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
6081 gen_load_spr(t2
, SPR_MQ
);
6082 tcg_gen_andc_tl(t1
, t2
, t1
);
6083 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
6088 if (unlikely(Rc(ctx
->opcode
) != 0)) {
6089 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
6094 static void gen_slq(DisasContext
*ctx
)
6096 TCGLabel
*l1
= gen_new_label();
6097 TCGv t0
= tcg_temp_new();
6098 TCGv t1
= tcg_temp_new();
6099 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
6100 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
6101 tcg_gen_subfi_tl(t1
, 32, t1
);
6102 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
6103 tcg_gen_or_tl(t1
, t0
, t1
);
6104 gen_store_spr(SPR_MQ
, t1
);
6105 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
6106 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
6107 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
6108 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
6112 if (unlikely(Rc(ctx
->opcode
) != 0)) {
6113 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
6117 /* sraiq - sraiq. */
6118 static void gen_sraiq(DisasContext
*ctx
)
6120 int sh
= SH(ctx
->opcode
);
6121 TCGLabel
*l1
= gen_new_label();
6122 TCGv t0
= tcg_temp_new();
6123 TCGv t1
= tcg_temp_new();
6124 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
6125 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
6126 tcg_gen_or_tl(t0
, t0
, t1
);
6127 gen_store_spr(SPR_MQ
, t0
);
6128 tcg_gen_movi_tl(cpu_ca
, 0);
6129 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
6130 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rS(ctx
->opcode
)], 0, l1
);
6131 tcg_gen_movi_tl(cpu_ca
, 1);
6133 tcg_gen_sari_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], sh
);
6136 if (unlikely(Rc(ctx
->opcode
) != 0)) {
6137 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
6142 static void gen_sraq(DisasContext
*ctx
)
6144 TCGLabel
*l1
= gen_new_label();
6145 TCGLabel
*l2
= gen_new_label();
6146 TCGv t0
= tcg_temp_new();
6147 TCGv t1
= tcg_temp_local_new();
6148 TCGv t2
= tcg_temp_local_new();
6149 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
6150 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
6151 tcg_gen_sar_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
6152 tcg_gen_subfi_tl(t2
, 32, t2
);
6153 tcg_gen_shl_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
6154 tcg_gen_or_tl(t0
, t0
, t2
);
6155 gen_store_spr(SPR_MQ
, t0
);
6156 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
6157 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l1
);
6158 tcg_gen_mov_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)]);
6159 tcg_gen_sari_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 31);
6162 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t1
);
6163 tcg_gen_movi_tl(cpu_ca
, 0);
6164 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
6165 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l2
);
6166 tcg_gen_movi_tl(cpu_ca
, 1);
6170 if (unlikely(Rc(ctx
->opcode
) != 0)) {
6171 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
6176 static void gen_sre(DisasContext
*ctx
)
6178 TCGv t0
= tcg_temp_new();
6179 TCGv t1
= tcg_temp_new();
6180 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
6181 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
6182 tcg_gen_subfi_tl(t1
, 32, t1
);
6183 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
6184 tcg_gen_or_tl(t1
, t0
, t1
);
6185 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
6186 gen_store_spr(SPR_MQ
, t1
);
6189 if (unlikely(Rc(ctx
->opcode
) != 0)) {
6190 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
6195 static void gen_srea(DisasContext
*ctx
)
6197 TCGv t0
= tcg_temp_new();
6198 TCGv t1
= tcg_temp_new();
6199 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
6200 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
6201 gen_store_spr(SPR_MQ
, t0
);
6202 tcg_gen_sar_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], t1
);
6205 if (unlikely(Rc(ctx
->opcode
) != 0)) {
6206 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
6211 static void gen_sreq(DisasContext
*ctx
)
6213 TCGv t0
= tcg_temp_new();
6214 TCGv t1
= tcg_temp_new();
6215 TCGv t2
= tcg_temp_new();
6216 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
6217 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
6218 tcg_gen_shr_tl(t1
, t1
, t0
);
6219 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
6220 gen_load_spr(t2
, SPR_MQ
);
6221 gen_store_spr(SPR_MQ
, t0
);
6222 tcg_gen_and_tl(t0
, t0
, t1
);
6223 tcg_gen_andc_tl(t2
, t2
, t1
);
6224 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
6228 if (unlikely(Rc(ctx
->opcode
) != 0)) {
6229 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
6234 static void gen_sriq(DisasContext
*ctx
)
6236 int sh
= SH(ctx
->opcode
);
6237 TCGv t0
= tcg_temp_new();
6238 TCGv t1
= tcg_temp_new();
6239 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
6240 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
6241 tcg_gen_or_tl(t1
, t0
, t1
);
6242 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
6243 gen_store_spr(SPR_MQ
, t1
);
6246 if (unlikely(Rc(ctx
->opcode
) != 0)) {
6247 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
6252 static void gen_srliq(DisasContext
*ctx
)
6254 int sh
= SH(ctx
->opcode
);
6255 TCGv t0
= tcg_temp_new();
6256 TCGv t1
= tcg_temp_new();
6257 tcg_gen_rotri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
6258 gen_load_spr(t1
, SPR_MQ
);
6259 gen_store_spr(SPR_MQ
, t0
);
6260 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
>> sh
));
6261 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
>> sh
));
6262 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
6265 if (unlikely(Rc(ctx
->opcode
) != 0)) {
6266 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
6271 static void gen_srlq(DisasContext
*ctx
)
6273 TCGLabel
*l1
= gen_new_label();
6274 TCGLabel
*l2
= gen_new_label();
6275 TCGv t0
= tcg_temp_local_new();
6276 TCGv t1
= tcg_temp_local_new();
6277 TCGv t2
= tcg_temp_local_new();
6278 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
6279 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
6280 tcg_gen_shr_tl(t2
, t1
, t2
);
6281 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
6282 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
6283 gen_load_spr(t0
, SPR_MQ
);
6284 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
6287 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
6288 tcg_gen_and_tl(t0
, t0
, t2
);
6289 gen_load_spr(t1
, SPR_MQ
);
6290 tcg_gen_andc_tl(t1
, t1
, t2
);
6291 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
6296 if (unlikely(Rc(ctx
->opcode
) != 0)) {
6297 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
6302 static void gen_srq(DisasContext
*ctx
)
6304 TCGLabel
*l1
= gen_new_label();
6305 TCGv t0
= tcg_temp_new();
6306 TCGv t1
= tcg_temp_new();
6307 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
6308 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
6309 tcg_gen_subfi_tl(t1
, 32, t1
);
6310 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
6311 tcg_gen_or_tl(t1
, t0
, t1
);
6312 gen_store_spr(SPR_MQ
, t1
);
6313 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
6314 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
6315 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
6316 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
6320 if (unlikely(Rc(ctx
->opcode
) != 0)) {
6321 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
6325 /* PowerPC 602 specific instructions */
6328 static void gen_dsa(DisasContext
*ctx
)
6331 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6335 static void gen_esa(DisasContext
*ctx
)
6338 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6342 static void gen_mfrom(DisasContext
*ctx
)
6344 #if defined(CONFIG_USER_ONLY)
6348 gen_helper_602_mfrom(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
6349 #endif /* defined(CONFIG_USER_ONLY) */
6352 /* 602 - 603 - G2 TLB management */
6355 static void gen_tlbld_6xx(DisasContext
*ctx
)
6357 #if defined(CONFIG_USER_ONLY)
6361 gen_helper_6xx_tlbd(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
6362 #endif /* defined(CONFIG_USER_ONLY) */
6366 static void gen_tlbli_6xx(DisasContext
*ctx
)
6368 #if defined(CONFIG_USER_ONLY)
6372 gen_helper_6xx_tlbi(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
6373 #endif /* defined(CONFIG_USER_ONLY) */
6376 /* 74xx TLB management */
6379 static void gen_tlbld_74xx(DisasContext
*ctx
)
6381 #if defined(CONFIG_USER_ONLY)
6385 gen_helper_74xx_tlbd(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
6386 #endif /* defined(CONFIG_USER_ONLY) */
6390 static void gen_tlbli_74xx(DisasContext
*ctx
)
6392 #if defined(CONFIG_USER_ONLY)
6396 gen_helper_74xx_tlbi(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
6397 #endif /* defined(CONFIG_USER_ONLY) */
6400 /* POWER instructions not in PowerPC 601 */
6403 static void gen_clf(DisasContext
*ctx
)
6405 /* Cache line flush: implemented as no-op */
6409 static void gen_cli(DisasContext
*ctx
)
6411 #if defined(CONFIG_USER_ONLY)
6414 /* Cache line invalidate: privileged and treated as no-op */
6416 #endif /* defined(CONFIG_USER_ONLY) */
6420 static void gen_dclst(DisasContext
*ctx
)
6422 /* Data cache line store: treated as no-op */
6425 static void gen_mfsri(DisasContext
*ctx
)
6427 #if defined(CONFIG_USER_ONLY)
6430 int ra
= rA(ctx
->opcode
);
6431 int rd
= rD(ctx
->opcode
);
6435 t0
= tcg_temp_new();
6436 gen_addr_reg_index(ctx
, t0
);
6437 tcg_gen_extract_tl(t0
, t0
, 28, 4);
6438 gen_helper_load_sr(cpu_gpr
[rd
], cpu_env
, t0
);
6440 if (ra
!= 0 && ra
!= rd
) {
6441 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rd
]);
6443 #endif /* defined(CONFIG_USER_ONLY) */
6446 static void gen_rac(DisasContext
*ctx
)
6448 #if defined(CONFIG_USER_ONLY)
6454 t0
= tcg_temp_new();
6455 gen_addr_reg_index(ctx
, t0
);
6456 gen_helper_rac(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
6458 #endif /* defined(CONFIG_USER_ONLY) */
6461 static void gen_rfsvc(DisasContext
*ctx
)
6463 #if defined(CONFIG_USER_ONLY)
6468 gen_helper_rfsvc(cpu_env
);
6469 ctx
->base
.is_jmp
= DISAS_EXIT
;
6470 #endif /* defined(CONFIG_USER_ONLY) */
6473 /* svc is not implemented for now */
6475 /* BookE specific instructions */
6477 /* XXX: not implemented on 440 ? */
6478 static void gen_mfapidi(DisasContext
*ctx
)
6481 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6484 /* XXX: not implemented on 440 ? */
6485 static void gen_tlbiva(DisasContext
*ctx
)
6487 #if defined(CONFIG_USER_ONLY)
6493 t0
= tcg_temp_new();
6494 gen_addr_reg_index(ctx
, t0
);
6495 gen_helper_tlbiva(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
6497 #endif /* defined(CONFIG_USER_ONLY) */
6500 /* All 405 MAC instructions are translated here */
6501 static inline void gen_405_mulladd_insn(DisasContext
*ctx
, int opc2
, int opc3
,
6502 int ra
, int rb
, int rt
, int Rc
)
6506 t0
= tcg_temp_local_new();
6507 t1
= tcg_temp_local_new();
6509 switch (opc3
& 0x0D) {
6511 /* macchw - macchw. - macchwo - macchwo. */
6512 /* macchws - macchws. - macchwso - macchwso. */
6513 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
6514 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
6515 /* mulchw - mulchw. */
6516 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
6517 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
6518 tcg_gen_ext16s_tl(t1
, t1
);
6521 /* macchwu - macchwu. - macchwuo - macchwuo. */
6522 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
6523 /* mulchwu - mulchwu. */
6524 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
6525 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
6526 tcg_gen_ext16u_tl(t1
, t1
);
6529 /* machhw - machhw. - machhwo - machhwo. */
6530 /* machhws - machhws. - machhwso - machhwso. */
6531 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
6532 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
6533 /* mulhhw - mulhhw. */
6534 tcg_gen_sari_tl(t0
, cpu_gpr
[ra
], 16);
6535 tcg_gen_ext16s_tl(t0
, t0
);
6536 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
6537 tcg_gen_ext16s_tl(t1
, t1
);
6540 /* machhwu - machhwu. - machhwuo - machhwuo. */
6541 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
6542 /* mulhhwu - mulhhwu. */
6543 tcg_gen_shri_tl(t0
, cpu_gpr
[ra
], 16);
6544 tcg_gen_ext16u_tl(t0
, t0
);
6545 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
6546 tcg_gen_ext16u_tl(t1
, t1
);
6549 /* maclhw - maclhw. - maclhwo - maclhwo. */
6550 /* maclhws - maclhws. - maclhwso - maclhwso. */
6551 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
6552 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
6553 /* mullhw - mullhw. */
6554 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
6555 tcg_gen_ext16s_tl(t1
, cpu_gpr
[rb
]);
6558 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
6559 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
6560 /* mullhwu - mullhwu. */
6561 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
6562 tcg_gen_ext16u_tl(t1
, cpu_gpr
[rb
]);
6566 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
6567 tcg_gen_mul_tl(t1
, t0
, t1
);
6569 /* nmultiply-and-accumulate (0x0E) */
6570 tcg_gen_sub_tl(t0
, cpu_gpr
[rt
], t1
);
6572 /* multiply-and-accumulate (0x0C) */
6573 tcg_gen_add_tl(t0
, cpu_gpr
[rt
], t1
);
6577 /* Check overflow and/or saturate */
6578 TCGLabel
*l1
= gen_new_label();
6581 /* Start with XER OV disabled, the most likely case */
6582 tcg_gen_movi_tl(cpu_ov
, 0);
6586 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t1
);
6587 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
6588 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t0
);
6589 tcg_gen_brcondi_tl(TCG_COND_LT
, t1
, 0, l1
);
6592 tcg_gen_sari_tl(t0
, cpu_gpr
[rt
], 31);
6593 tcg_gen_xori_tl(t0
, t0
, 0x7fffffff);
6597 tcg_gen_brcond_tl(TCG_COND_GEU
, t0
, t1
, l1
);
6600 tcg_gen_movi_tl(t0
, UINT32_MAX
);
6604 /* Check overflow */
6605 tcg_gen_movi_tl(cpu_ov
, 1);
6606 tcg_gen_movi_tl(cpu_so
, 1);
6609 tcg_gen_mov_tl(cpu_gpr
[rt
], t0
);
6612 tcg_gen_mul_tl(cpu_gpr
[rt
], t0
, t1
);
6616 if (unlikely(Rc
) != 0) {
6618 gen_set_Rc0(ctx
, cpu_gpr
[rt
]);
6622 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6623 static void glue(gen_, name)(DisasContext *ctx) \
6625 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
6626 rD(ctx->opcode), Rc(ctx->opcode)); \
6629 /* macchw - macchw. */
6630 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05);
6631 /* macchwo - macchwo. */
6632 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15);
6633 /* macchws - macchws. */
6634 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07);
6635 /* macchwso - macchwso. */
6636 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17);
6637 /* macchwsu - macchwsu. */
6638 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06);
6639 /* macchwsuo - macchwsuo. */
6640 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16);
6641 /* macchwu - macchwu. */
6642 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04);
6643 /* macchwuo - macchwuo. */
6644 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14);
6645 /* machhw - machhw. */
6646 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01);
6647 /* machhwo - machhwo. */
6648 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11);
6649 /* machhws - machhws. */
6650 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03);
6651 /* machhwso - machhwso. */
6652 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13);
6653 /* machhwsu - machhwsu. */
6654 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02);
6655 /* machhwsuo - machhwsuo. */
6656 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12);
6657 /* machhwu - machhwu. */
6658 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00);
6659 /* machhwuo - machhwuo. */
6660 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10);
6661 /* maclhw - maclhw. */
6662 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D);
6663 /* maclhwo - maclhwo. */
6664 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D);
6665 /* maclhws - maclhws. */
6666 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F);
6667 /* maclhwso - maclhwso. */
6668 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F);
6669 /* maclhwu - maclhwu. */
6670 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C);
6671 /* maclhwuo - maclhwuo. */
6672 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C);
6673 /* maclhwsu - maclhwsu. */
6674 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E);
6675 /* maclhwsuo - maclhwsuo. */
6676 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E);
6677 /* nmacchw - nmacchw. */
6678 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05);
6679 /* nmacchwo - nmacchwo. */
6680 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15);
6681 /* nmacchws - nmacchws. */
6682 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07);
6683 /* nmacchwso - nmacchwso. */
6684 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17);
6685 /* nmachhw - nmachhw. */
6686 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01);
6687 /* nmachhwo - nmachhwo. */
6688 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11);
6689 /* nmachhws - nmachhws. */
6690 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03);
6691 /* nmachhwso - nmachhwso. */
6692 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13);
6693 /* nmaclhw - nmaclhw. */
6694 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D);
6695 /* nmaclhwo - nmaclhwo. */
6696 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D);
6697 /* nmaclhws - nmaclhws. */
6698 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F);
6699 /* nmaclhwso - nmaclhwso. */
6700 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F);
6702 /* mulchw - mulchw. */
6703 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05);
6704 /* mulchwu - mulchwu. */
6705 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04);
6706 /* mulhhw - mulhhw. */
6707 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01);
6708 /* mulhhwu - mulhhwu. */
6709 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00);
6710 /* mullhw - mullhw. */
6711 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D);
6712 /* mullhwu - mullhwu. */
6713 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C);
6716 static void gen_mfdcr(DisasContext
*ctx
)
6718 #if defined(CONFIG_USER_ONLY)
6724 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
6725 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, dcrn
);
6726 tcg_temp_free(dcrn
);
6727 #endif /* defined(CONFIG_USER_ONLY) */
6731 static void gen_mtdcr(DisasContext
*ctx
)
6733 #if defined(CONFIG_USER_ONLY)
6739 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
6740 gen_helper_store_dcr(cpu_env
, dcrn
, cpu_gpr
[rS(ctx
->opcode
)]);
6741 tcg_temp_free(dcrn
);
6742 #endif /* defined(CONFIG_USER_ONLY) */
6746 /* XXX: not implemented on 440 ? */
6747 static void gen_mfdcrx(DisasContext
*ctx
)
6749 #if defined(CONFIG_USER_ONLY)
6753 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6754 cpu_gpr
[rA(ctx
->opcode
)]);
6755 /* Note: Rc update flag set leads to undefined state of Rc0 */
6756 #endif /* defined(CONFIG_USER_ONLY) */
6760 /* XXX: not implemented on 440 ? */
6761 static void gen_mtdcrx(DisasContext
*ctx
)
6763 #if defined(CONFIG_USER_ONLY)
6767 gen_helper_store_dcr(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
6768 cpu_gpr
[rS(ctx
->opcode
)]);
6769 /* Note: Rc update flag set leads to undefined state of Rc0 */
6770 #endif /* defined(CONFIG_USER_ONLY) */
6773 /* mfdcrux (PPC 460) : user-mode access to DCR */
6774 static void gen_mfdcrux(DisasContext
*ctx
)
6776 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6777 cpu_gpr
[rA(ctx
->opcode
)]);
6778 /* Note: Rc update flag set leads to undefined state of Rc0 */
6781 /* mtdcrux (PPC 460) : user-mode access to DCR */
6782 static void gen_mtdcrux(DisasContext
*ctx
)
6784 gen_helper_store_dcr(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
6785 cpu_gpr
[rS(ctx
->opcode
)]);
6786 /* Note: Rc update flag set leads to undefined state of Rc0 */
6790 static void gen_dccci(DisasContext
*ctx
)
6793 /* interpreted as no-op */
6797 static void gen_dcread(DisasContext
*ctx
)
6799 #if defined(CONFIG_USER_ONLY)
6805 gen_set_access_type(ctx
, ACCESS_CACHE
);
6806 EA
= tcg_temp_new();
6807 gen_addr_reg_index(ctx
, EA
);
6808 val
= tcg_temp_new();
6809 gen_qemu_ld32u(ctx
, val
, EA
);
6811 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], EA
);
6813 #endif /* defined(CONFIG_USER_ONLY) */
6817 static void gen_icbt_40x(DisasContext
*ctx
)
6820 * interpreted as no-op
6821 * XXX: specification say this is treated as a load by the MMU but
6822 * does not generate any exception
6827 static void gen_iccci(DisasContext
*ctx
)
6830 /* interpreted as no-op */
6834 static void gen_icread(DisasContext
*ctx
)
6837 /* interpreted as no-op */
6840 /* rfci (supervisor only) */
6841 static void gen_rfci_40x(DisasContext
*ctx
)
6843 #if defined(CONFIG_USER_ONLY)
6847 /* Restore CPU state */
6848 gen_helper_40x_rfci(cpu_env
);
6849 ctx
->base
.is_jmp
= DISAS_EXIT
;
6850 #endif /* defined(CONFIG_USER_ONLY) */
6853 static void gen_rfci(DisasContext
*ctx
)
6855 #if defined(CONFIG_USER_ONLY)
6859 /* Restore CPU state */
6860 gen_helper_rfci(cpu_env
);
6861 ctx
->base
.is_jmp
= DISAS_EXIT
;
6862 #endif /* defined(CONFIG_USER_ONLY) */
6865 /* BookE specific */
6867 /* XXX: not implemented on 440 ? */
6868 static void gen_rfdi(DisasContext
*ctx
)
6870 #if defined(CONFIG_USER_ONLY)
6874 /* Restore CPU state */
6875 gen_helper_rfdi(cpu_env
);
6876 ctx
->base
.is_jmp
= DISAS_EXIT
;
6877 #endif /* defined(CONFIG_USER_ONLY) */
6880 /* XXX: not implemented on 440 ? */
6881 static void gen_rfmci(DisasContext
*ctx
)
6883 #if defined(CONFIG_USER_ONLY)
6887 /* Restore CPU state */
6888 gen_helper_rfmci(cpu_env
);
6889 ctx
->base
.is_jmp
= DISAS_EXIT
;
6890 #endif /* defined(CONFIG_USER_ONLY) */
6893 /* TLB management - PowerPC 405 implementation */
6896 static void gen_tlbre_40x(DisasContext
*ctx
)
6898 #if defined(CONFIG_USER_ONLY)
6902 switch (rB(ctx
->opcode
)) {
6904 gen_helper_4xx_tlbre_hi(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6905 cpu_gpr
[rA(ctx
->opcode
)]);
6908 gen_helper_4xx_tlbre_lo(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6909 cpu_gpr
[rA(ctx
->opcode
)]);
6912 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6915 #endif /* defined(CONFIG_USER_ONLY) */
6918 /* tlbsx - tlbsx. */
6919 static void gen_tlbsx_40x(DisasContext
*ctx
)
6921 #if defined(CONFIG_USER_ONLY)
6927 t0
= tcg_temp_new();
6928 gen_addr_reg_index(ctx
, t0
);
6929 gen_helper_4xx_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
6931 if (Rc(ctx
->opcode
)) {
6932 TCGLabel
*l1
= gen_new_label();
6933 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
6934 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
6935 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
6938 #endif /* defined(CONFIG_USER_ONLY) */
6942 static void gen_tlbwe_40x(DisasContext
*ctx
)
6944 #if defined(CONFIG_USER_ONLY)
6949 switch (rB(ctx
->opcode
)) {
6951 gen_helper_4xx_tlbwe_hi(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
6952 cpu_gpr
[rS(ctx
->opcode
)]);
6955 gen_helper_4xx_tlbwe_lo(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
6956 cpu_gpr
[rS(ctx
->opcode
)]);
6959 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6962 #endif /* defined(CONFIG_USER_ONLY) */
6965 /* TLB management - PowerPC 440 implementation */
6968 static void gen_tlbre_440(DisasContext
*ctx
)
6970 #if defined(CONFIG_USER_ONLY)
6975 switch (rB(ctx
->opcode
)) {
6980 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
6981 gen_helper_440_tlbre(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6982 t0
, cpu_gpr
[rA(ctx
->opcode
)]);
6983 tcg_temp_free_i32(t0
);
6987 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6990 #endif /* defined(CONFIG_USER_ONLY) */
6993 /* tlbsx - tlbsx. */
6994 static void gen_tlbsx_440(DisasContext
*ctx
)
6996 #if defined(CONFIG_USER_ONLY)
7002 t0
= tcg_temp_new();
7003 gen_addr_reg_index(ctx
, t0
);
7004 gen_helper_440_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
7006 if (Rc(ctx
->opcode
)) {
7007 TCGLabel
*l1
= gen_new_label();
7008 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
7009 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
7010 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
7013 #endif /* defined(CONFIG_USER_ONLY) */
7017 static void gen_tlbwe_440(DisasContext
*ctx
)
7019 #if defined(CONFIG_USER_ONLY)
7023 switch (rB(ctx
->opcode
)) {
7028 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
7029 gen_helper_440_tlbwe(cpu_env
, t0
, cpu_gpr
[rA(ctx
->opcode
)],
7030 cpu_gpr
[rS(ctx
->opcode
)]);
7031 tcg_temp_free_i32(t0
);
7035 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
7038 #endif /* defined(CONFIG_USER_ONLY) */
7041 /* TLB management - PowerPC BookE 2.06 implementation */
7044 static void gen_tlbre_booke206(DisasContext
*ctx
)
7046 #if defined(CONFIG_USER_ONLY)
7050 gen_helper_booke206_tlbre(cpu_env
);
7051 #endif /* defined(CONFIG_USER_ONLY) */
7054 /* tlbsx - tlbsx. */
7055 static void gen_tlbsx_booke206(DisasContext
*ctx
)
7057 #if defined(CONFIG_USER_ONLY)
7063 if (rA(ctx
->opcode
)) {
7064 t0
= tcg_temp_new();
7065 tcg_gen_mov_tl(t0
, cpu_gpr
[rD(ctx
->opcode
)]);
7067 t0
= tcg_const_tl(0);
7070 tcg_gen_add_tl(t0
, t0
, cpu_gpr
[rB(ctx
->opcode
)]);
7071 gen_helper_booke206_tlbsx(cpu_env
, t0
);
7073 #endif /* defined(CONFIG_USER_ONLY) */
7077 static void gen_tlbwe_booke206(DisasContext
*ctx
)
7079 #if defined(CONFIG_USER_ONLY)
7083 gen_helper_booke206_tlbwe(cpu_env
);
7084 #endif /* defined(CONFIG_USER_ONLY) */
7087 static void gen_tlbivax_booke206(DisasContext
*ctx
)
7089 #if defined(CONFIG_USER_ONLY)
7095 t0
= tcg_temp_new();
7096 gen_addr_reg_index(ctx
, t0
);
7097 gen_helper_booke206_tlbivax(cpu_env
, t0
);
7099 #endif /* defined(CONFIG_USER_ONLY) */
7102 static void gen_tlbilx_booke206(DisasContext
*ctx
)
7104 #if defined(CONFIG_USER_ONLY)
7110 t0
= tcg_temp_new();
7111 gen_addr_reg_index(ctx
, t0
);
7113 switch ((ctx
->opcode
>> 21) & 0x3) {
7115 gen_helper_booke206_tlbilx0(cpu_env
, t0
);
7118 gen_helper_booke206_tlbilx1(cpu_env
, t0
);
7121 gen_helper_booke206_tlbilx3(cpu_env
, t0
);
7124 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
7129 #endif /* defined(CONFIG_USER_ONLY) */
7134 static void gen_wrtee(DisasContext
*ctx
)
7136 #if defined(CONFIG_USER_ONLY)
7142 t0
= tcg_temp_new();
7143 tcg_gen_andi_tl(t0
, cpu_gpr
[rD(ctx
->opcode
)], (1 << MSR_EE
));
7144 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
7145 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
7148 * Stop translation to have a chance to raise an exception if we
7149 * just set msr_ee to 1
7151 ctx
->base
.is_jmp
= DISAS_EXIT_UPDATE
;
7152 #endif /* defined(CONFIG_USER_ONLY) */
7156 static void gen_wrteei(DisasContext
*ctx
)
7158 #if defined(CONFIG_USER_ONLY)
7162 if (ctx
->opcode
& 0x00008000) {
7163 tcg_gen_ori_tl(cpu_msr
, cpu_msr
, (1 << MSR_EE
));
7164 /* Stop translation to have a chance to raise an exception */
7165 ctx
->base
.is_jmp
= DISAS_EXIT_UPDATE
;
7167 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
7169 #endif /* defined(CONFIG_USER_ONLY) */
7172 /* PowerPC 440 specific instructions */
7175 static void gen_dlmzb(DisasContext
*ctx
)
7177 TCGv_i32 t0
= tcg_const_i32(Rc(ctx
->opcode
));
7178 gen_helper_dlmzb(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
7179 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], t0
);
7180 tcg_temp_free_i32(t0
);
7183 /* mbar replaces eieio on 440 */
7184 static void gen_mbar(DisasContext
*ctx
)
7186 /* interpreted as no-op */
7189 /* msync replaces sync on 440 */
7190 static void gen_msync_4xx(DisasContext
*ctx
)
7192 /* Only e500 seems to treat reserved bits as invalid */
7193 if ((ctx
->insns_flags2
& PPC2_BOOKE206
) &&
7194 (ctx
->opcode
& 0x03FFF801)) {
7195 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
7197 /* otherwise interpreted as no-op */
7201 static void gen_icbt_440(DisasContext
*ctx
)
7204 * interpreted as no-op
7205 * XXX: specification say this is treated as a load by the MMU but
7206 * does not generate any exception
7210 /* Embedded.Processor Control */
7212 static void gen_msgclr(DisasContext
*ctx
)
7214 #if defined(CONFIG_USER_ONLY)
7218 if (is_book3s_arch2x(ctx
)) {
7219 gen_helper_book3s_msgclr(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
7221 gen_helper_msgclr(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
7223 #endif /* defined(CONFIG_USER_ONLY) */
7226 static void gen_msgsnd(DisasContext
*ctx
)
7228 #if defined(CONFIG_USER_ONLY)
7232 if (is_book3s_arch2x(ctx
)) {
7233 gen_helper_book3s_msgsnd(cpu_gpr
[rB(ctx
->opcode
)]);
7235 gen_helper_msgsnd(cpu_gpr
[rB(ctx
->opcode
)]);
7237 #endif /* defined(CONFIG_USER_ONLY) */
7240 #if defined(TARGET_PPC64)
7241 static void gen_msgclrp(DisasContext
*ctx
)
7243 #if defined(CONFIG_USER_ONLY)
7247 gen_helper_book3s_msgclrp(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
7248 #endif /* defined(CONFIG_USER_ONLY) */
7251 static void gen_msgsndp(DisasContext
*ctx
)
7253 #if defined(CONFIG_USER_ONLY)
7257 gen_helper_book3s_msgsndp(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
7258 #endif /* defined(CONFIG_USER_ONLY) */
7262 static void gen_msgsync(DisasContext
*ctx
)
7264 #if defined(CONFIG_USER_ONLY)
7268 #endif /* defined(CONFIG_USER_ONLY) */
7269 /* interpreted as no-op */
7272 #if defined(TARGET_PPC64)
7273 static void gen_maddld(DisasContext
*ctx
)
7275 TCGv_i64 t1
= tcg_temp_new_i64();
7277 tcg_gen_mul_i64(t1
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
7278 tcg_gen_add_i64(cpu_gpr
[rD(ctx
->opcode
)], t1
, cpu_gpr
[rC(ctx
->opcode
)]);
7279 tcg_temp_free_i64(t1
);
7282 /* maddhd maddhdu */
7283 static void gen_maddhd_maddhdu(DisasContext
*ctx
)
7285 TCGv_i64 lo
= tcg_temp_new_i64();
7286 TCGv_i64 hi
= tcg_temp_new_i64();
7287 TCGv_i64 t1
= tcg_temp_new_i64();
7289 if (Rc(ctx
->opcode
)) {
7290 tcg_gen_mulu2_i64(lo
, hi
, cpu_gpr
[rA(ctx
->opcode
)],
7291 cpu_gpr
[rB(ctx
->opcode
)]);
7292 tcg_gen_movi_i64(t1
, 0);
7294 tcg_gen_muls2_i64(lo
, hi
, cpu_gpr
[rA(ctx
->opcode
)],
7295 cpu_gpr
[rB(ctx
->opcode
)]);
7296 tcg_gen_sari_i64(t1
, cpu_gpr
[rC(ctx
->opcode
)], 63);
7298 tcg_gen_add2_i64(t1
, cpu_gpr
[rD(ctx
->opcode
)], lo
, hi
,
7299 cpu_gpr
[rC(ctx
->opcode
)], t1
);
7300 tcg_temp_free_i64(lo
);
7301 tcg_temp_free_i64(hi
);
7302 tcg_temp_free_i64(t1
);
7304 #endif /* defined(TARGET_PPC64) */
7306 static void gen_tbegin(DisasContext
*ctx
)
7308 if (unlikely(!ctx
->tm_enabled
)) {
7309 gen_exception_err(ctx
, POWERPC_EXCP_FU
, FSCR_IC_TM
);
7312 gen_helper_tbegin(cpu_env
);
7315 #define GEN_TM_NOOP(name) \
7316 static inline void gen_##name(DisasContext *ctx) \
7318 if (unlikely(!ctx->tm_enabled)) { \
7319 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
7323 * Because tbegin always fails in QEMU, these user \
7324 * space instructions all have a simple implementation: \
7326 * CR[0] = 0b0 || MSR[TS] || 0b0 \
7327 * = 0b0 || 0b00 || 0b0 \
7329 tcg_gen_movi_i32(cpu_crf[0], 0); \
7333 GEN_TM_NOOP(tabort
);
7334 GEN_TM_NOOP(tabortwc
);
7335 GEN_TM_NOOP(tabortwci
);
7336 GEN_TM_NOOP(tabortdc
);
7337 GEN_TM_NOOP(tabortdci
);
7340 static inline void gen_cp_abort(DisasContext
*ctx
)
7345 #define GEN_CP_PASTE_NOOP(name) \
7346 static inline void gen_##name(DisasContext *ctx) \
7349 * Generate invalid exception until we have an \
7350 * implementation of the copy paste facility \
7355 GEN_CP_PASTE_NOOP(copy
)
7356 GEN_CP_PASTE_NOOP(paste
)
7358 static void gen_tcheck(DisasContext
*ctx
)
7360 if (unlikely(!ctx
->tm_enabled
)) {
7361 gen_exception_err(ctx
, POWERPC_EXCP_FU
, FSCR_IC_TM
);
7365 * Because tbegin always fails, the tcheck implementation is
7368 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
7369 * = 0b1 || 0b00 || 0b0
7371 tcg_gen_movi_i32(cpu_crf
[crfD(ctx
->opcode
)], 0x8);
7374 #if defined(CONFIG_USER_ONLY)
7375 #define GEN_TM_PRIV_NOOP(name) \
7376 static inline void gen_##name(DisasContext *ctx) \
7378 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
7383 #define GEN_TM_PRIV_NOOP(name) \
7384 static inline void gen_##name(DisasContext *ctx) \
7387 if (unlikely(!ctx->tm_enabled)) { \
7388 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
7392 * Because tbegin always fails, the implementation is \
7395 * CR[0] = 0b0 || MSR[TS] || 0b0 \
7396 * = 0b0 || 0b00 | 0b0 \
7398 tcg_gen_movi_i32(cpu_crf[0], 0); \
7403 GEN_TM_PRIV_NOOP(treclaim
);
7404 GEN_TM_PRIV_NOOP(trechkpt
);
7406 static inline void get_fpr(TCGv_i64 dst
, int regno
)
7408 tcg_gen_ld_i64(dst
, cpu_env
, fpr_offset(regno
));
7411 static inline void set_fpr(int regno
, TCGv_i64 src
)
7413 tcg_gen_st_i64(src
, cpu_env
, fpr_offset(regno
));
7416 static inline void get_avr64(TCGv_i64 dst
, int regno
, bool high
)
7418 tcg_gen_ld_i64(dst
, cpu_env
, avr64_offset(regno
, high
));
7421 static inline void set_avr64(int regno
, TCGv_i64 src
, bool high
)
7423 tcg_gen_st_i64(src
, cpu_env
, avr64_offset(regno
, high
));
7427 * Helpers for decodetree used by !function for decoding arguments.
7429 static int times_4(DisasContext
*ctx
, int x
)
7435 * Helpers for trans_* functions to check for specific insns flags.
7436 * Use token pasting to ensure that we use the proper flag with the
7439 #define REQUIRE_INSNS_FLAGS(CTX, NAME) \
7441 if (((CTX)->insns_flags & PPC_##NAME) == 0) { \
7446 #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \
7448 if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \
7453 /* Then special-case the check for 64-bit so that we elide code for ppc32. */
7454 #if TARGET_LONG_BITS == 32
7455 # define REQUIRE_64BIT(CTX) return false
7457 # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B)
7461 * Helpers for implementing sets of trans_* functions.
7462 * Defer the implementation of NAME to FUNC, with optional extra arguments.
7464 #define TRANS(NAME, FUNC, ...) \
7465 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
7466 { return FUNC(ctx, a, __VA_ARGS__); }
7468 #define TRANS64(NAME, FUNC, ...) \
7469 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
7470 { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); }
7472 /* TODO: More TRANS* helpers for extra insn_flags checks. */
7475 #include "decode-insn32.c.inc"
7476 #include "decode-insn64.c.inc"
7477 #include "translate/fixedpoint-impl.c.inc"
7479 #include "translate/fp-impl.c.inc"
7481 #include "translate/vmx-impl.c.inc"
7483 #include "translate/vsx-impl.c.inc"
7484 #include "translate/vector-impl.c.inc"
7486 #include "translate/dfp-impl.c.inc"
7488 #include "translate/spe-impl.c.inc"
7490 /* Handles lfdp, lxsd, lxssp */
7491 static void gen_dform39(DisasContext
*ctx
)
7493 switch (ctx
->opcode
& 0x3) {
7495 if (ctx
->insns_flags2
& PPC2_ISA205
) {
7496 return gen_lfdp(ctx
);
7500 if (ctx
->insns_flags2
& PPC2_ISA300
) {
7501 return gen_lxsd(ctx
);
7505 if (ctx
->insns_flags2
& PPC2_ISA300
) {
7506 return gen_lxssp(ctx
);
7510 return gen_invalid(ctx
);
7513 /* handles stfdp, lxv, stxsd, stxssp lxvx */
7514 static void gen_dform3D(DisasContext
*ctx
)
7516 if ((ctx
->opcode
& 3) == 1) { /* DQ-FORM */
7517 switch (ctx
->opcode
& 0x7) {
7519 if (ctx
->insns_flags2
& PPC2_ISA300
) {
7520 return gen_lxv(ctx
);
7524 if (ctx
->insns_flags2
& PPC2_ISA300
) {
7525 return gen_stxv(ctx
);
7529 } else { /* DS-FORM */
7530 switch (ctx
->opcode
& 0x3) {
7532 if (ctx
->insns_flags2
& PPC2_ISA205
) {
7533 return gen_stfdp(ctx
);
7537 if (ctx
->insns_flags2
& PPC2_ISA300
) {
7538 return gen_stxsd(ctx
);
7541 case 3: /* stxssp */
7542 if (ctx
->insns_flags2
& PPC2_ISA300
) {
7543 return gen_stxssp(ctx
);
7548 return gen_invalid(ctx
);
7551 #if defined(TARGET_PPC64)
7553 static void gen_brd(DisasContext
*ctx
)
7555 tcg_gen_bswap64_i64(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
7559 static void gen_brw(DisasContext
*ctx
)
7561 tcg_gen_bswap64_i64(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
7562 tcg_gen_rotli_i64(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 32);
7567 static void gen_brh(DisasContext
*ctx
)
7569 TCGv_i64 t0
= tcg_temp_new_i64();
7570 TCGv_i64 t1
= tcg_temp_new_i64();
7571 TCGv_i64 t2
= tcg_temp_new_i64();
7573 tcg_gen_movi_i64(t0
, 0x00ff00ff00ff00ffull
);
7574 tcg_gen_shri_i64(t1
, cpu_gpr
[rS(ctx
->opcode
)], 8);
7575 tcg_gen_and_i64(t2
, t1
, t0
);
7576 tcg_gen_and_i64(t1
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
7577 tcg_gen_shli_i64(t1
, t1
, 8);
7578 tcg_gen_or_i64(cpu_gpr
[rA(ctx
->opcode
)], t1
, t2
);
7580 tcg_temp_free_i64(t0
);
7581 tcg_temp_free_i64(t1
);
7582 tcg_temp_free_i64(t2
);
7586 static opcode_t opcodes
[] = {
7587 #if defined(TARGET_PPC64)
7588 GEN_HANDLER_E(brd
, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE
, PPC2_ISA310
),
7589 GEN_HANDLER_E(brw
, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE
, PPC2_ISA310
),
7590 GEN_HANDLER_E(brh
, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE
, PPC2_ISA310
),
7592 GEN_HANDLER(invalid
, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE
),
7593 #if defined(TARGET_PPC64)
7594 GEN_HANDLER_E(cmpeqb
, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE
, PPC2_ISA300
),
7596 GEN_HANDLER_E(cmpb
, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE
, PPC2_ISA205
),
7597 GEN_HANDLER_E(cmprb
, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE
, PPC2_ISA300
),
7598 GEN_HANDLER(isel
, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL
),
7599 GEN_HANDLER(addic
, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
7600 GEN_HANDLER2(addic_
, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
7601 GEN_HANDLER(mulhw
, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER
),
7602 GEN_HANDLER(mulhwu
, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER
),
7603 GEN_HANDLER(mullw
, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER
),
7604 GEN_HANDLER(mullwo
, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER
),
7605 GEN_HANDLER(mulli
, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
7606 #if defined(TARGET_PPC64)
7607 GEN_HANDLER(mulld
, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B
),
7609 GEN_HANDLER(neg
, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER
),
7610 GEN_HANDLER(nego
, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER
),
7611 GEN_HANDLER(subfic
, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
7612 GEN_HANDLER2(andi_
, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
7613 GEN_HANDLER2(andis_
, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
7614 GEN_HANDLER(cntlzw
, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER
),
7615 GEN_HANDLER_E(cnttzw
, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE
, PPC2_ISA300
),
7616 GEN_HANDLER_E(copy
, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE
, PPC2_ISA300
),
7617 GEN_HANDLER_E(cp_abort
, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE
, PPC2_ISA300
),
7618 GEN_HANDLER_E(paste
, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE
, PPC2_ISA300
),
7619 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER
),
7620 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER
),
7621 GEN_HANDLER(ori
, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
7622 GEN_HANDLER(oris
, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
7623 GEN_HANDLER(xori
, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
7624 GEN_HANDLER(xoris
, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
7625 GEN_HANDLER(popcntb
, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB
),
7626 GEN_HANDLER(popcntw
, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD
),
7627 GEN_HANDLER_E(prtyw
, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE
, PPC2_ISA205
),
7628 #if defined(TARGET_PPC64)
7629 GEN_HANDLER(popcntd
, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD
),
7630 GEN_HANDLER(cntlzd
, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B
),
7631 GEN_HANDLER_E(cnttzd
, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE
, PPC2_ISA300
),
7632 GEN_HANDLER_E(darn
, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE
, PPC2_ISA300
),
7633 GEN_HANDLER_E(prtyd
, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE
, PPC2_ISA205
),
7634 GEN_HANDLER_E(bpermd
, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE
, PPC2_PERM_ISA206
),
7636 GEN_HANDLER(rlwimi
, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
7637 GEN_HANDLER(rlwinm
, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
7638 GEN_HANDLER(rlwnm
, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
7639 GEN_HANDLER(slw
, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER
),
7640 GEN_HANDLER(sraw
, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER
),
7641 GEN_HANDLER(srawi
, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER
),
7642 GEN_HANDLER(srw
, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER
),
7643 #if defined(TARGET_PPC64)
7644 GEN_HANDLER(sld
, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B
),
7645 GEN_HANDLER(srad
, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B
),
7646 GEN_HANDLER2(sradi0
, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B
),
7647 GEN_HANDLER2(sradi1
, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B
),
7648 GEN_HANDLER(srd
, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B
),
7649 GEN_HANDLER2_E(extswsli0
, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
7650 PPC_NONE
, PPC2_ISA300
),
7651 GEN_HANDLER2_E(extswsli1
, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
7652 PPC_NONE
, PPC2_ISA300
),
7654 #if defined(TARGET_PPC64)
7655 GEN_HANDLER(lq
, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX
),
7656 GEN_HANDLER(std
, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B
),
7658 /* handles lfdp, lxsd, lxssp */
7659 GEN_HANDLER_E(dform39
, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE
, PPC2_ISA205
),
7660 /* handles stfdp, lxv, stxsd, stxssp, stxv */
7661 GEN_HANDLER_E(dform3D
, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE
, PPC2_ISA205
),
7662 GEN_HANDLER(lmw
, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
7663 GEN_HANDLER(stmw
, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
7664 GEN_HANDLER(lswi
, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING
),
7665 GEN_HANDLER(lswx
, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING
),
7666 GEN_HANDLER(stswi
, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING
),
7667 GEN_HANDLER(stswx
, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING
),
7668 GEN_HANDLER(eieio
, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO
),
7669 GEN_HANDLER(isync
, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM
),
7670 GEN_HANDLER_E(lbarx
, 0x1F, 0x14, 0x01, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
7671 GEN_HANDLER_E(lharx
, 0x1F, 0x14, 0x03, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
7672 GEN_HANDLER(lwarx
, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES
),
7673 GEN_HANDLER_E(lwat
, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE
, PPC2_ISA300
),
7674 GEN_HANDLER_E(stwat
, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE
, PPC2_ISA300
),
7675 GEN_HANDLER_E(stbcx_
, 0x1F, 0x16, 0x15, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
7676 GEN_HANDLER_E(sthcx_
, 0x1F, 0x16, 0x16, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
7677 GEN_HANDLER2(stwcx_
, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES
),
7678 #if defined(TARGET_PPC64)
7679 GEN_HANDLER_E(ldat
, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE
, PPC2_ISA300
),
7680 GEN_HANDLER_E(stdat
, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE
, PPC2_ISA300
),
7681 GEN_HANDLER(ldarx
, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B
),
7682 GEN_HANDLER_E(lqarx
, 0x1F, 0x14, 0x08, 0, PPC_NONE
, PPC2_LSQ_ISA207
),
7683 GEN_HANDLER2(stdcx_
, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B
),
7684 GEN_HANDLER_E(stqcx_
, 0x1F, 0x16, 0x05, 0, PPC_NONE
, PPC2_LSQ_ISA207
),
7686 GEN_HANDLER(sync
, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC
),
7687 GEN_HANDLER(wait
, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT
),
7688 GEN_HANDLER_E(wait
, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE
, PPC2_ISA300
),
7689 GEN_HANDLER(b
, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
7690 GEN_HANDLER(bc
, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
7691 GEN_HANDLER(bcctr
, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW
),
7692 GEN_HANDLER(bclr
, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW
),
7693 GEN_HANDLER_E(bctar
, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE
, PPC2_BCTAR_ISA207
),
7694 GEN_HANDLER(mcrf
, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER
),
7695 GEN_HANDLER(rfi
, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW
),
7696 #if defined(TARGET_PPC64)
7697 GEN_HANDLER(rfid
, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B
),
7698 #if !defined(CONFIG_USER_ONLY)
7699 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */
7700 GEN_HANDLER_E(scv
, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE
, PPC2_ISA300
),
7701 GEN_HANDLER_E(scv
, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE
, PPC2_ISA300
),
7702 GEN_HANDLER_E(rfscv
, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE
, PPC2_ISA300
),
7704 GEN_HANDLER_E(stop
, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE
, PPC2_ISA300
),
7705 GEN_HANDLER_E(doze
, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE
, PPC2_PM_ISA206
),
7706 GEN_HANDLER_E(nap
, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE
, PPC2_PM_ISA206
),
7707 GEN_HANDLER_E(sleep
, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE
, PPC2_PM_ISA206
),
7708 GEN_HANDLER_E(rvwinkle
, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE
, PPC2_PM_ISA206
),
7709 GEN_HANDLER(hrfid
, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H
),
7711 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */
7712 GEN_HANDLER(sc
, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW
),
7713 GEN_HANDLER(sc
, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW
),
7714 GEN_HANDLER(tw
, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW
),
7715 GEN_HANDLER(twi
, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
7716 #if defined(TARGET_PPC64)
7717 GEN_HANDLER(td
, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B
),
7718 GEN_HANDLER(tdi
, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B
),
7720 GEN_HANDLER(mcrxr
, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC
),
7721 GEN_HANDLER(mfcr
, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC
),
7722 GEN_HANDLER(mfmsr
, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC
),
7723 GEN_HANDLER(mfspr
, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC
),
7724 GEN_HANDLER(mftb
, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB
),
7725 GEN_HANDLER(mtcrf
, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC
),
7726 #if defined(TARGET_PPC64)
7727 GEN_HANDLER(mtmsrd
, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B
),
7728 GEN_HANDLER_E(setb
, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE
, PPC2_ISA300
),
7729 GEN_HANDLER_E(mcrxrx
, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE
, PPC2_ISA300
),
7731 GEN_HANDLER(mtmsr
, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC
),
7732 GEN_HANDLER(mtspr
, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC
),
7733 GEN_HANDLER(dcbf
, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE
),
7734 GEN_HANDLER_E(dcbfep
, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE
, PPC2_BOOKE206
),
7735 GEN_HANDLER(dcbi
, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE
),
7736 GEN_HANDLER(dcbst
, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE
),
7737 GEN_HANDLER_E(dcbstep
, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE
, PPC2_BOOKE206
),
7738 GEN_HANDLER(dcbt
, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE
),
7739 GEN_HANDLER_E(dcbtep
, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE
, PPC2_BOOKE206
),
7740 GEN_HANDLER(dcbtst
, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE
),
7741 GEN_HANDLER_E(dcbtstep
, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE
, PPC2_BOOKE206
),
7742 GEN_HANDLER_E(dcbtls
, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE
, PPC2_BOOKE206
),
7743 GEN_HANDLER(dcbz
, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ
),
7744 GEN_HANDLER_E(dcbzep
, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE
, PPC2_BOOKE206
),
7745 GEN_HANDLER(dst
, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC
),
7746 GEN_HANDLER(dstst
, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC
),
7747 GEN_HANDLER(dss
, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC
),
7748 GEN_HANDLER(icbi
, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI
),
7749 GEN_HANDLER_E(icbiep
, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE
, PPC2_BOOKE206
),
7750 GEN_HANDLER(dcba
, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA
),
7751 GEN_HANDLER(mfsr
, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT
),
7752 GEN_HANDLER(mfsrin
, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT
),
7753 GEN_HANDLER(mtsr
, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT
),
7754 GEN_HANDLER(mtsrin
, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT
),
7755 #if defined(TARGET_PPC64)
7756 GEN_HANDLER2(mfsr_64b
, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B
),
7757 GEN_HANDLER2(mfsrin_64b
, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
7759 GEN_HANDLER2(mtsr_64b
, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B
),
7760 GEN_HANDLER2(mtsrin_64b
, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
7762 GEN_HANDLER2(slbmte
, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B
),
7763 GEN_HANDLER2(slbmfee
, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B
),
7764 GEN_HANDLER2(slbmfev
, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B
),
7765 GEN_HANDLER2(slbfee_
, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B
),
7767 GEN_HANDLER(tlbia
, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA
),
7769 * XXX Those instructions will need to be handled differently for
7770 * different ISA versions
7772 GEN_HANDLER(tlbiel
, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE
),
7773 GEN_HANDLER(tlbie
, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE
),
7774 GEN_HANDLER_E(tlbiel
, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE
, PPC2_ISA300
),
7775 GEN_HANDLER_E(tlbie
, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE
, PPC2_ISA300
),
7776 GEN_HANDLER(tlbsync
, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC
),
7777 #if defined(TARGET_PPC64)
7778 GEN_HANDLER(slbia
, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI
),
7779 GEN_HANDLER(slbie
, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI
),
7780 GEN_HANDLER_E(slbieg
, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE
, PPC2_ISA300
),
7781 GEN_HANDLER_E(slbsync
, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE
, PPC2_ISA300
),
7783 GEN_HANDLER(eciwx
, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN
),
7784 GEN_HANDLER(ecowx
, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN
),
7785 GEN_HANDLER(abs
, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR
),
7786 GEN_HANDLER(abso
, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR
),
7787 GEN_HANDLER(clcs
, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR
),
7788 GEN_HANDLER(div
, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR
),
7789 GEN_HANDLER(divo
, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR
),
7790 GEN_HANDLER(divs
, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR
),
7791 GEN_HANDLER(divso
, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR
),
7792 GEN_HANDLER(doz
, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR
),
7793 GEN_HANDLER(dozo
, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR
),
7794 GEN_HANDLER(dozi
, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
),
7795 GEN_HANDLER(lscbx
, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR
),
7796 GEN_HANDLER(maskg
, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR
),
7797 GEN_HANDLER(maskir
, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR
),
7798 GEN_HANDLER(mul
, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR
),
7799 GEN_HANDLER(mulo
, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR
),
7800 GEN_HANDLER(nabs
, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR
),
7801 GEN_HANDLER(nabso
, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR
),
7802 GEN_HANDLER(rlmi
, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
),
7803 GEN_HANDLER(rrib
, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR
),
7804 GEN_HANDLER(sle
, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR
),
7805 GEN_HANDLER(sleq
, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR
),
7806 GEN_HANDLER(sliq
, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR
),
7807 GEN_HANDLER(slliq
, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR
),
7808 GEN_HANDLER(sllq
, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR
),
7809 GEN_HANDLER(slq
, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR
),
7810 GEN_HANDLER(sraiq
, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR
),
7811 GEN_HANDLER(sraq
, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR
),
7812 GEN_HANDLER(sre
, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR
),
7813 GEN_HANDLER(srea
, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR
),
7814 GEN_HANDLER(sreq
, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR
),
7815 GEN_HANDLER(sriq
, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR
),
7816 GEN_HANDLER(srliq
, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR
),
7817 GEN_HANDLER(srlq
, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR
),
7818 GEN_HANDLER(srq
, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR
),
7819 GEN_HANDLER(dsa
, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC
),
7820 GEN_HANDLER(esa
, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC
),
7821 GEN_HANDLER(mfrom
, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC
),
7822 GEN_HANDLER2(tlbld_6xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB
),
7823 GEN_HANDLER2(tlbli_6xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB
),
7824 GEN_HANDLER2(tlbld_74xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB
),
7825 GEN_HANDLER2(tlbli_74xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB
),
7826 GEN_HANDLER(clf
, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER
),
7827 GEN_HANDLER(cli
, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER
),
7828 GEN_HANDLER(dclst
, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER
),
7829 GEN_HANDLER(mfsri
, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER
),
7830 GEN_HANDLER(rac
, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER
),
7831 GEN_HANDLER(rfsvc
, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER
),
7832 GEN_HANDLER(lfq
, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
7833 GEN_HANDLER(lfqu
, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
7834 GEN_HANDLER(lfqux
, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2
),
7835 GEN_HANDLER(lfqx
, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2
),
7836 GEN_HANDLER(stfq
, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
7837 GEN_HANDLER(stfqu
, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
7838 GEN_HANDLER(stfqux
, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2
),
7839 GEN_HANDLER(stfqx
, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2
),
7840 GEN_HANDLER(mfapidi
, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI
),
7841 GEN_HANDLER(tlbiva
, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA
),
7842 GEN_HANDLER(mfdcr
, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR
),
7843 GEN_HANDLER(mtdcr
, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR
),
7844 GEN_HANDLER(mfdcrx
, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX
),
7845 GEN_HANDLER(mtdcrx
, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX
),
7846 GEN_HANDLER(mfdcrux
, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX
),
7847 GEN_HANDLER(mtdcrux
, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX
),
7848 GEN_HANDLER(dccci
, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON
),
7849 GEN_HANDLER(dcread
, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON
),
7850 GEN_HANDLER2(icbt_40x
, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT
),
7851 GEN_HANDLER(iccci
, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON
),
7852 GEN_HANDLER(icread
, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON
),
7853 GEN_HANDLER2(rfci_40x
, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP
),
7854 GEN_HANDLER_E(rfci
, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE
, PPC2_BOOKE206
),
7855 GEN_HANDLER(rfdi
, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI
),
7856 GEN_HANDLER(rfmci
, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI
),
7857 GEN_HANDLER2(tlbre_40x
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB
),
7858 GEN_HANDLER2(tlbsx_40x
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB
),
7859 GEN_HANDLER2(tlbwe_40x
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB
),
7860 GEN_HANDLER2(tlbre_440
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE
),
7861 GEN_HANDLER2(tlbsx_440
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE
),
7862 GEN_HANDLER2(tlbwe_440
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE
),
7863 GEN_HANDLER2_E(tlbre_booke206
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
7864 PPC_NONE
, PPC2_BOOKE206
),
7865 GEN_HANDLER2_E(tlbsx_booke206
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
7866 PPC_NONE
, PPC2_BOOKE206
),
7867 GEN_HANDLER2_E(tlbwe_booke206
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
7868 PPC_NONE
, PPC2_BOOKE206
),
7869 GEN_HANDLER2_E(tlbivax_booke206
, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
7870 PPC_NONE
, PPC2_BOOKE206
),
7871 GEN_HANDLER2_E(tlbilx_booke206
, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
7872 PPC_NONE
, PPC2_BOOKE206
),
7873 GEN_HANDLER2_E(msgsnd
, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
7874 PPC_NONE
, PPC2_PRCNTL
),
7875 GEN_HANDLER2_E(msgclr
, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
7876 PPC_NONE
, PPC2_PRCNTL
),
7877 GEN_HANDLER2_E(msgsync
, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000,
7878 PPC_NONE
, PPC2_PRCNTL
),
7879 GEN_HANDLER(wrtee
, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE
),
7880 GEN_HANDLER(wrteei
, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE
),
7881 GEN_HANDLER(dlmzb
, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC
),
7882 GEN_HANDLER_E(mbar
, 0x1F, 0x16, 0x1a, 0x001FF801,
7883 PPC_BOOKE
, PPC2_BOOKE206
),
7884 GEN_HANDLER(msync_4xx
, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE
),
7885 GEN_HANDLER2_E(icbt_440
, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
7886 PPC_BOOKE
, PPC2_BOOKE206
),
7887 GEN_HANDLER2(icbt_440
, "icbt", 0x1F, 0x06, 0x08, 0x03E00001,
7889 GEN_HANDLER(lvsl
, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC
),
7890 GEN_HANDLER(lvsr
, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC
),
7891 GEN_HANDLER(mfvscr
, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC
),
7892 GEN_HANDLER(mtvscr
, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC
),
7893 GEN_HANDLER(vmladduhm
, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC
),
7894 #if defined(TARGET_PPC64)
7895 GEN_HANDLER_E(maddhd_maddhdu
, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE
,
7897 GEN_HANDLER_E(maddld
, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE
, PPC2_ISA300
),
7898 GEN_HANDLER2_E(msgsndp
, "msgsndp", 0x1F, 0x0E, 0x04, 0x03ff0001,
7899 PPC_NONE
, PPC2_ISA207S
),
7900 GEN_HANDLER2_E(msgclrp
, "msgclrp", 0x1F, 0x0E, 0x05, 0x03ff0001,
7901 PPC_NONE
, PPC2_ISA207S
),
7904 #undef GEN_INT_ARITH_ADD
7905 #undef GEN_INT_ARITH_ADD_CONST
7906 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
7907 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
7908 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
7909 add_ca, compute_ca, compute_ov) \
7910 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
7911 GEN_INT_ARITH_ADD(add
, 0x08, 0, 0, 0)
7912 GEN_INT_ARITH_ADD(addo
, 0x18, 0, 0, 1)
7913 GEN_INT_ARITH_ADD(addc
, 0x00, 0, 1, 0)
7914 GEN_INT_ARITH_ADD(addco
, 0x10, 0, 1, 1)
7915 GEN_INT_ARITH_ADD(adde
, 0x04, 1, 1, 0)
7916 GEN_INT_ARITH_ADD(addeo
, 0x14, 1, 1, 1)
7917 GEN_INT_ARITH_ADD_CONST(addme
, 0x07, -1LL, 1, 1, 0)
7918 GEN_INT_ARITH_ADD_CONST(addmeo
, 0x17, -1LL, 1, 1, 1)
7919 GEN_HANDLER_E(addex
, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE
, PPC2_ISA300
),
7920 GEN_INT_ARITH_ADD_CONST(addze
, 0x06, 0, 1, 1, 0)
7921 GEN_INT_ARITH_ADD_CONST(addzeo
, 0x16, 0, 1, 1, 1)
7923 #undef GEN_INT_ARITH_DIVW
7924 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
7925 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
7926 GEN_INT_ARITH_DIVW(divwu
, 0x0E, 0, 0),
7927 GEN_INT_ARITH_DIVW(divwuo
, 0x1E, 0, 1),
7928 GEN_INT_ARITH_DIVW(divw
, 0x0F, 1, 0),
7929 GEN_INT_ARITH_DIVW(divwo
, 0x1F, 1, 1),
7930 GEN_HANDLER_E(divwe
, 0x1F, 0x0B, 0x0D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7931 GEN_HANDLER_E(divweo
, 0x1F, 0x0B, 0x1D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7932 GEN_HANDLER_E(divweu
, 0x1F, 0x0B, 0x0C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7933 GEN_HANDLER_E(divweuo
, 0x1F, 0x0B, 0x1C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7934 GEN_HANDLER_E(modsw
, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE
, PPC2_ISA300
),
7935 GEN_HANDLER_E(moduw
, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE
, PPC2_ISA300
),
7937 #if defined(TARGET_PPC64)
7938 #undef GEN_INT_ARITH_DIVD
7939 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
7940 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
7941 GEN_INT_ARITH_DIVD(divdu
, 0x0E, 0, 0),
7942 GEN_INT_ARITH_DIVD(divduo
, 0x1E, 0, 1),
7943 GEN_INT_ARITH_DIVD(divd
, 0x0F, 1, 0),
7944 GEN_INT_ARITH_DIVD(divdo
, 0x1F, 1, 1),
7946 GEN_HANDLER_E(divdeu
, 0x1F, 0x09, 0x0C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7947 GEN_HANDLER_E(divdeuo
, 0x1F, 0x09, 0x1C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7948 GEN_HANDLER_E(divde
, 0x1F, 0x09, 0x0D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7949 GEN_HANDLER_E(divdeo
, 0x1F, 0x09, 0x1D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7950 GEN_HANDLER_E(modsd
, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE
, PPC2_ISA300
),
7951 GEN_HANDLER_E(modud
, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE
, PPC2_ISA300
),
7953 #undef GEN_INT_ARITH_MUL_HELPER
7954 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
7955 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
7956 GEN_INT_ARITH_MUL_HELPER(mulhdu
, 0x00),
7957 GEN_INT_ARITH_MUL_HELPER(mulhd
, 0x02),
7958 GEN_INT_ARITH_MUL_HELPER(mulldo
, 0x17),
7961 #undef GEN_INT_ARITH_SUBF
7962 #undef GEN_INT_ARITH_SUBF_CONST
7963 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
7964 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
7965 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
7966 add_ca, compute_ca, compute_ov) \
7967 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
7968 GEN_INT_ARITH_SUBF(subf
, 0x01, 0, 0, 0)
7969 GEN_INT_ARITH_SUBF(subfo
, 0x11, 0, 0, 1)
7970 GEN_INT_ARITH_SUBF(subfc
, 0x00, 0, 1, 0)
7971 GEN_INT_ARITH_SUBF(subfco
, 0x10, 0, 1, 1)
7972 GEN_INT_ARITH_SUBF(subfe
, 0x04, 1, 1, 0)
7973 GEN_INT_ARITH_SUBF(subfeo
, 0x14, 1, 1, 1)
7974 GEN_INT_ARITH_SUBF_CONST(subfme
, 0x07, -1LL, 1, 1, 0)
7975 GEN_INT_ARITH_SUBF_CONST(subfmeo
, 0x17, -1LL, 1, 1, 1)
7976 GEN_INT_ARITH_SUBF_CONST(subfze
, 0x06, 0, 1, 1, 0)
7977 GEN_INT_ARITH_SUBF_CONST(subfzeo
, 0x16, 0, 1, 1, 1)
7981 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
7982 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
7983 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
7984 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
7985 GEN_LOGICAL2(and, tcg_gen_and_tl
, 0x00, PPC_INTEGER
),
7986 GEN_LOGICAL2(andc
, tcg_gen_andc_tl
, 0x01, PPC_INTEGER
),
7987 GEN_LOGICAL2(eqv
, tcg_gen_eqv_tl
, 0x08, PPC_INTEGER
),
7988 GEN_LOGICAL1(extsb
, tcg_gen_ext8s_tl
, 0x1D, PPC_INTEGER
),
7989 GEN_LOGICAL1(extsh
, tcg_gen_ext16s_tl
, 0x1C, PPC_INTEGER
),
7990 GEN_LOGICAL2(nand
, tcg_gen_nand_tl
, 0x0E, PPC_INTEGER
),
7991 GEN_LOGICAL2(nor
, tcg_gen_nor_tl
, 0x03, PPC_INTEGER
),
7992 GEN_LOGICAL2(orc
, tcg_gen_orc_tl
, 0x0C, PPC_INTEGER
),
7993 #if defined(TARGET_PPC64)
7994 GEN_LOGICAL1(extsw
, tcg_gen_ext32s_tl
, 0x1E, PPC_64B
),
7997 #if defined(TARGET_PPC64)
8000 #define GEN_PPC64_R2(name, opc1, opc2) \
8001 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8002 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8004 #define GEN_PPC64_R4(name, opc1, opc2) \
8005 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8006 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
8008 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8010 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
8012 GEN_PPC64_R4(rldicl
, 0x1E, 0x00),
8013 GEN_PPC64_R4(rldicr
, 0x1E, 0x02),
8014 GEN_PPC64_R4(rldic
, 0x1E, 0x04),
8015 GEN_PPC64_R2(rldcl
, 0x1E, 0x08),
8016 GEN_PPC64_R2(rldcr
, 0x1E, 0x09),
8017 GEN_PPC64_R4(rldimi
, 0x1E, 0x06),
8021 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
8022 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8024 #if defined(TARGET_PPC64)
8025 GEN_LDX_E(ldbr
, ld64ur_i64
, 0x14, 0x10, PPC_NONE
, PPC2_DBRX
, CHK_NONE
)
8027 /* HV/P7 and later only */
8028 GEN_LDX_HVRM(ldcix
, ld64_i64
, 0x15, 0x1b, PPC_CILDST
)
8029 GEN_LDX_HVRM(lwzcix
, ld32u
, 0x15, 0x18, PPC_CILDST
)
8030 GEN_LDX_HVRM(lhzcix
, ld16u
, 0x15, 0x19, PPC_CILDST
)
8031 GEN_LDX_HVRM(lbzcix
, ld8u
, 0x15, 0x1a, PPC_CILDST
)
8033 GEN_LDX(lhbr
, ld16ur
, 0x16, 0x18, PPC_INTEGER
)
8034 GEN_LDX(lwbr
, ld32ur
, 0x16, 0x10, PPC_INTEGER
)
8036 /* External PID based load */
8038 #define GEN_LDEPX(name, ldop, opc2, opc3) \
8039 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \
8040 0x00000001, PPC_NONE, PPC2_BOOKE206),
8042 GEN_LDEPX(lb
, DEF_MEMOP(MO_UB
), 0x1F, 0x02)
8043 GEN_LDEPX(lh
, DEF_MEMOP(MO_UW
), 0x1F, 0x08)
8044 GEN_LDEPX(lw
, DEF_MEMOP(MO_UL
), 0x1F, 0x00)
8045 #if defined(TARGET_PPC64)
8046 GEN_LDEPX(ld
, DEF_MEMOP(MO_Q
), 0x1D, 0x00)
8050 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
8051 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2),
8053 #if defined(TARGET_PPC64)
8054 GEN_STX_E(stdbr
, st64r_i64
, 0x14, 0x14, PPC_NONE
, PPC2_DBRX
, CHK_NONE
)
8055 GEN_STX_HVRM(stdcix
, st64_i64
, 0x15, 0x1f, PPC_CILDST
)
8056 GEN_STX_HVRM(stwcix
, st32
, 0x15, 0x1c, PPC_CILDST
)
8057 GEN_STX_HVRM(sthcix
, st16
, 0x15, 0x1d, PPC_CILDST
)
8058 GEN_STX_HVRM(stbcix
, st8
, 0x15, 0x1e, PPC_CILDST
)
8060 GEN_STX(sthbr
, st16r
, 0x16, 0x1C, PPC_INTEGER
)
8061 GEN_STX(stwbr
, st32r
, 0x16, 0x14, PPC_INTEGER
)
8064 #define GEN_STEPX(name, ldop, opc2, opc3) \
8065 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \
8066 0x00000001, PPC_NONE, PPC2_BOOKE206),
8068 GEN_STEPX(stb
, DEF_MEMOP(MO_UB
), 0x1F, 0x06)
8069 GEN_STEPX(sth
, DEF_MEMOP(MO_UW
), 0x1F, 0x0C)
8070 GEN_STEPX(stw
, DEF_MEMOP(MO_UL
), 0x1F, 0x04)
8071 #if defined(TARGET_PPC64)
8072 GEN_STEPX(std
, DEF_MEMOP(MO_Q
), 0x1D, 0x04)
8076 #define GEN_CRLOGIC(name, tcg_op, opc) \
8077 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
8078 GEN_CRLOGIC(crand
, tcg_gen_and_i32
, 0x08),
8079 GEN_CRLOGIC(crandc
, tcg_gen_andc_i32
, 0x04),
8080 GEN_CRLOGIC(creqv
, tcg_gen_eqv_i32
, 0x09),
8081 GEN_CRLOGIC(crnand
, tcg_gen_nand_i32
, 0x07),
8082 GEN_CRLOGIC(crnor
, tcg_gen_nor_i32
, 0x01),
8083 GEN_CRLOGIC(cror
, tcg_gen_or_i32
, 0x0E),
8084 GEN_CRLOGIC(crorc
, tcg_gen_orc_i32
, 0x0D),
8085 GEN_CRLOGIC(crxor
, tcg_gen_xor_i32
, 0x06),
8087 #undef GEN_MAC_HANDLER
8088 #define GEN_MAC_HANDLER(name, opc2, opc3) \
8089 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
8090 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05),
8091 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15),
8092 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07),
8093 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17),
8094 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06),
8095 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16),
8096 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04),
8097 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14),
8098 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01),
8099 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11),
8100 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03),
8101 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13),
8102 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02),
8103 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12),
8104 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00),
8105 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10),
8106 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D),
8107 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D),
8108 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F),
8109 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F),
8110 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C),
8111 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C),
8112 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E),
8113 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E),
8114 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05),
8115 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15),
8116 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07),
8117 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17),
8118 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01),
8119 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11),
8120 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03),
8121 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13),
8122 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D),
8123 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D),
8124 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F),
8125 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F),
8126 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05),
8127 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04),
8128 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01),
8129 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00),
8130 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D),
8131 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C),
8133 GEN_HANDLER2_E(tbegin
, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
8135 GEN_HANDLER2_E(tend
, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
8137 GEN_HANDLER2_E(tabort
, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
8139 GEN_HANDLER2_E(tabortwc
, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
8141 GEN_HANDLER2_E(tabortwci
, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
8143 GEN_HANDLER2_E(tabortdc
, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
8145 GEN_HANDLER2_E(tabortdci
, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
8147 GEN_HANDLER2_E(tsr
, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
8149 GEN_HANDLER2_E(tcheck
, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
8151 GEN_HANDLER2_E(treclaim
, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
8153 GEN_HANDLER2_E(trechkpt
, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
8156 #include "translate/fp-ops.c.inc"
8158 #include "translate/vmx-ops.c.inc"
8160 #include "translate/vsx-ops.c.inc"
8162 #include "translate/dfp-ops.c.inc"
8164 #include "translate/spe-ops.c.inc"
8167 /*****************************************************************************/
8170 PPC_DIRECT
= 0, /* Opcode routine */
8171 PPC_INDIRECT
= 1, /* Indirect opcode table */
8174 #define PPC_OPCODE_MASK 0x3
8176 static inline int is_indirect_opcode(void *handler
)
8178 return ((uintptr_t)handler
& PPC_OPCODE_MASK
) == PPC_INDIRECT
;
8181 static inline opc_handler_t
**ind_table(void *handler
)
8183 return (opc_handler_t
**)((uintptr_t)handler
& ~PPC_OPCODE_MASK
);
8186 /* Instruction table creation */
8187 /* Opcodes tables creation */
8188 static void fill_new_table(opc_handler_t
**table
, int len
)
8192 for (i
= 0; i
< len
; i
++) {
8193 table
[i
] = &invalid_handler
;
8197 static int create_new_table(opc_handler_t
**table
, unsigned char idx
)
8199 opc_handler_t
**tmp
;
8201 tmp
= g_new(opc_handler_t
*, PPC_CPU_INDIRECT_OPCODES_LEN
);
8202 fill_new_table(tmp
, PPC_CPU_INDIRECT_OPCODES_LEN
);
8203 table
[idx
] = (opc_handler_t
*)((uintptr_t)tmp
| PPC_INDIRECT
);
8208 static int insert_in_table(opc_handler_t
**table
, unsigned char idx
,
8209 opc_handler_t
*handler
)
8211 if (table
[idx
] != &invalid_handler
) {
8214 table
[idx
] = handler
;
8219 static int register_direct_insn(opc_handler_t
**ppc_opcodes
,
8220 unsigned char idx
, opc_handler_t
*handler
)
8222 if (insert_in_table(ppc_opcodes
, idx
, handler
) < 0) {
8223 printf("*** ERROR: opcode %02x already assigned in main "
8224 "opcode table\n", idx
);
8231 static int register_ind_in_table(opc_handler_t
**table
,
8232 unsigned char idx1
, unsigned char idx2
,
8233 opc_handler_t
*handler
)
8235 if (table
[idx1
] == &invalid_handler
) {
8236 if (create_new_table(table
, idx1
) < 0) {
8237 printf("*** ERROR: unable to create indirect table "
8238 "idx=%02x\n", idx1
);
8242 if (!is_indirect_opcode(table
[idx1
])) {
8243 printf("*** ERROR: idx %02x already assigned to a direct "
8248 if (handler
!= NULL
&&
8249 insert_in_table(ind_table(table
[idx1
]), idx2
, handler
) < 0) {
8250 printf("*** ERROR: opcode %02x already assigned in "
8251 "opcode table %02x\n", idx2
, idx1
);
8258 static int register_ind_insn(opc_handler_t
**ppc_opcodes
,
8259 unsigned char idx1
, unsigned char idx2
,
8260 opc_handler_t
*handler
)
8262 return register_ind_in_table(ppc_opcodes
, idx1
, idx2
, handler
);
8265 static int register_dblind_insn(opc_handler_t
**ppc_opcodes
,
8266 unsigned char idx1
, unsigned char idx2
,
8267 unsigned char idx3
, opc_handler_t
*handler
)
8269 if (register_ind_in_table(ppc_opcodes
, idx1
, idx2
, NULL
) < 0) {
8270 printf("*** ERROR: unable to join indirect table idx "
8271 "[%02x-%02x]\n", idx1
, idx2
);
8274 if (register_ind_in_table(ind_table(ppc_opcodes
[idx1
]), idx2
, idx3
,
8276 printf("*** ERROR: unable to insert opcode "
8277 "[%02x-%02x-%02x]\n", idx1
, idx2
, idx3
);
8284 static int register_trplind_insn(opc_handler_t
**ppc_opcodes
,
8285 unsigned char idx1
, unsigned char idx2
,
8286 unsigned char idx3
, unsigned char idx4
,
8287 opc_handler_t
*handler
)
8289 opc_handler_t
**table
;
8291 if (register_ind_in_table(ppc_opcodes
, idx1
, idx2
, NULL
) < 0) {
8292 printf("*** ERROR: unable to join indirect table idx "
8293 "[%02x-%02x]\n", idx1
, idx2
);
8296 table
= ind_table(ppc_opcodes
[idx1
]);
8297 if (register_ind_in_table(table
, idx2
, idx3
, NULL
) < 0) {
8298 printf("*** ERROR: unable to join 2nd-level indirect table idx "
8299 "[%02x-%02x-%02x]\n", idx1
, idx2
, idx3
);
8302 table
= ind_table(table
[idx2
]);
8303 if (register_ind_in_table(table
, idx3
, idx4
, handler
) < 0) {
8304 printf("*** ERROR: unable to insert opcode "
8305 "[%02x-%02x-%02x-%02x]\n", idx1
, idx2
, idx3
, idx4
);
8310 static int register_insn(opc_handler_t
**ppc_opcodes
, opcode_t
*insn
)
8312 if (insn
->opc2
!= 0xFF) {
8313 if (insn
->opc3
!= 0xFF) {
8314 if (insn
->opc4
!= 0xFF) {
8315 if (register_trplind_insn(ppc_opcodes
, insn
->opc1
, insn
->opc2
,
8316 insn
->opc3
, insn
->opc4
,
8317 &insn
->handler
) < 0) {
8321 if (register_dblind_insn(ppc_opcodes
, insn
->opc1
, insn
->opc2
,
8322 insn
->opc3
, &insn
->handler
) < 0) {
8327 if (register_ind_insn(ppc_opcodes
, insn
->opc1
,
8328 insn
->opc2
, &insn
->handler
) < 0) {
8333 if (register_direct_insn(ppc_opcodes
, insn
->opc1
, &insn
->handler
) < 0) {
8341 static int test_opcode_table(opc_handler_t
**table
, int len
)
8345 for (i
= 0, count
= 0; i
< len
; i
++) {
8346 /* Consistency fixup */
8347 if (table
[i
] == NULL
) {
8348 table
[i
] = &invalid_handler
;
8350 if (table
[i
] != &invalid_handler
) {
8351 if (is_indirect_opcode(table
[i
])) {
8352 tmp
= test_opcode_table(ind_table(table
[i
]),
8353 PPC_CPU_INDIRECT_OPCODES_LEN
);
8356 table
[i
] = &invalid_handler
;
8369 static void fix_opcode_tables(opc_handler_t
**ppc_opcodes
)
8371 if (test_opcode_table(ppc_opcodes
, PPC_CPU_OPCODES_LEN
) == 0) {
8372 printf("*** WARNING: no opcode defined !\n");
8376 /*****************************************************************************/
8377 void create_ppc_opcodes(PowerPCCPU
*cpu
, Error
**errp
)
8379 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cpu
);
8382 fill_new_table(cpu
->opcodes
, PPC_CPU_OPCODES_LEN
);
8383 for (opc
= opcodes
; opc
< &opcodes
[ARRAY_SIZE(opcodes
)]; opc
++) {
8384 if (((opc
->handler
.type
& pcc
->insns_flags
) != 0) ||
8385 ((opc
->handler
.type2
& pcc
->insns_flags2
) != 0)) {
8386 if (register_insn(cpu
->opcodes
, opc
) < 0) {
8387 error_setg(errp
, "ERROR initializing PowerPC instruction "
8388 "0x%02x 0x%02x 0x%02x", opc
->opc1
, opc
->opc2
,
8394 fix_opcode_tables(cpu
->opcodes
);
8399 void destroy_ppc_opcodes(PowerPCCPU
*cpu
)
8401 opc_handler_t
**table
, **table_2
;
8404 for (i
= 0; i
< PPC_CPU_OPCODES_LEN
; i
++) {
8405 if (cpu
->opcodes
[i
] == &invalid_handler
) {
8408 if (is_indirect_opcode(cpu
->opcodes
[i
])) {
8409 table
= ind_table(cpu
->opcodes
[i
]);
8410 for (j
= 0; j
< PPC_CPU_INDIRECT_OPCODES_LEN
; j
++) {
8411 if (table
[j
] == &invalid_handler
) {
8414 if (is_indirect_opcode(table
[j
])) {
8415 table_2
= ind_table(table
[j
]);
8416 for (k
= 0; k
< PPC_CPU_INDIRECT_OPCODES_LEN
; k
++) {
8417 if (table_2
[k
] != &invalid_handler
&&
8418 is_indirect_opcode(table_2
[k
])) {
8419 g_free((opc_handler_t
*)((uintptr_t)table_2
[k
] &
8423 g_free((opc_handler_t
*)((uintptr_t)table
[j
] &
8427 g_free((opc_handler_t
*)((uintptr_t)cpu
->opcodes
[i
] &
8433 int ppc_fixup_cpu(PowerPCCPU
*cpu
)
8435 CPUPPCState
*env
= &cpu
->env
;
8438 * TCG doesn't (yet) emulate some groups of instructions that are
8439 * implemented on some otherwise supported CPUs (e.g. VSX and
8440 * decimal floating point instructions on POWER7). We remove
8441 * unsupported instruction groups from the cpu state's instruction
8442 * masks and hope the guest can cope. For at least the pseries
8443 * machine, the unavailability of these instructions can be
8444 * advertised to the guest via the device tree.
8446 if ((env
->insns_flags
& ~PPC_TCG_INSNS
)
8447 || (env
->insns_flags2
& ~PPC_TCG_INSNS2
)) {
8448 warn_report("Disabling some instructions which are not "
8449 "emulated by TCG (0x%" PRIx64
", 0x%" PRIx64
")",
8450 env
->insns_flags
& ~PPC_TCG_INSNS
,
8451 env
->insns_flags2
& ~PPC_TCG_INSNS2
);
8453 env
->insns_flags
&= PPC_TCG_INSNS
;
8454 env
->insns_flags2
&= PPC_TCG_INSNS2
;
8458 static bool decode_legacy(PowerPCCPU
*cpu
, DisasContext
*ctx
, uint32_t insn
)
8460 opc_handler_t
**table
, *handler
;
8465 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
8466 insn
, opc1(insn
), opc2(insn
), opc3(insn
), opc4(insn
),
8467 ctx
->le_mode
? "little" : "big");
8469 table
= cpu
->opcodes
;
8470 handler
= table
[opc1(insn
)];
8471 if (is_indirect_opcode(handler
)) {
8472 table
= ind_table(handler
);
8473 handler
= table
[opc2(insn
)];
8474 if (is_indirect_opcode(handler
)) {
8475 table
= ind_table(handler
);
8476 handler
= table
[opc3(insn
)];
8477 if (is_indirect_opcode(handler
)) {
8478 table
= ind_table(handler
);
8479 handler
= table
[opc4(insn
)];
8484 /* Is opcode *REALLY* valid ? */
8485 if (unlikely(handler
->handler
== &gen_invalid
)) {
8486 qemu_log_mask(LOG_GUEST_ERROR
, "invalid/unsupported opcode: "
8487 "%02x - %02x - %02x - %02x (%08x) "
8489 opc1(insn
), opc2(insn
), opc3(insn
), opc4(insn
),
8494 if (unlikely(handler
->type
& (PPC_SPE
| PPC_SPE_SINGLE
| PPC_SPE_DOUBLE
)
8496 inval
= handler
->inval2
;
8498 inval
= handler
->inval1
;
8501 if (unlikely((insn
& inval
) != 0)) {
8502 qemu_log_mask(LOG_GUEST_ERROR
, "invalid bits: %08x for opcode: "
8503 "%02x - %02x - %02x - %02x (%08x) "
8504 TARGET_FMT_lx
"\n", insn
& inval
,
8505 opc1(insn
), opc2(insn
), opc3(insn
), opc4(insn
),
8510 handler
->handler(ctx
);
8514 static void ppc_tr_init_disas_context(DisasContextBase
*dcbase
, CPUState
*cs
)
8516 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
8517 CPUPPCState
*env
= cs
->env_ptr
;
8518 uint32_t hflags
= ctx
->base
.tb
->flags
;
8520 ctx
->spr_cb
= env
->spr_cb
;
8521 ctx
->pr
= (hflags
>> HFLAGS_PR
) & 1;
8522 ctx
->mem_idx
= (hflags
>> HFLAGS_DMMU_IDX
) & 7;
8523 ctx
->dr
= (hflags
>> HFLAGS_DR
) & 1;
8524 ctx
->hv
= (hflags
>> HFLAGS_HV
) & 1;
8525 ctx
->insns_flags
= env
->insns_flags
;
8526 ctx
->insns_flags2
= env
->insns_flags2
;
8527 ctx
->access_type
= -1;
8528 ctx
->need_access_type
= !mmu_is_64bit(env
->mmu_model
);
8529 ctx
->le_mode
= (hflags
>> HFLAGS_LE
) & 1;
8530 ctx
->default_tcg_memop_mask
= ctx
->le_mode
? MO_LE
: MO_BE
;
8531 ctx
->flags
= env
->flags
;
8532 #if defined(TARGET_PPC64)
8533 ctx
->sf_mode
= (hflags
>> HFLAGS_64
) & 1;
8534 ctx
->has_cfar
= !!(env
->flags
& POWERPC_FLAG_CFAR
);
8536 ctx
->lazy_tlb_flush
= env
->mmu_model
== POWERPC_MMU_32B
8537 || env
->mmu_model
== POWERPC_MMU_601
8538 || env
->mmu_model
& POWERPC_MMU_64
;
8540 ctx
->fpu_enabled
= (hflags
>> HFLAGS_FP
) & 1;
8541 ctx
->spe_enabled
= (hflags
>> HFLAGS_SPE
) & 1;
8542 ctx
->altivec_enabled
= (hflags
>> HFLAGS_VR
) & 1;
8543 ctx
->vsx_enabled
= (hflags
>> HFLAGS_VSX
) & 1;
8544 ctx
->tm_enabled
= (hflags
>> HFLAGS_TM
) & 1;
8545 ctx
->gtse
= (hflags
>> HFLAGS_GTSE
) & 1;
8547 ctx
->singlestep_enabled
= 0;
8548 if ((hflags
>> HFLAGS_SE
) & 1) {
8549 ctx
->singlestep_enabled
|= CPU_SINGLE_STEP
;
8551 if ((hflags
>> HFLAGS_BE
) & 1) {
8552 ctx
->singlestep_enabled
|= CPU_BRANCH_STEP
;
8554 if (unlikely(ctx
->base
.singlestep_enabled
)) {
8555 ctx
->singlestep_enabled
|= GDBSTUB_SINGLE_STEP
;
8558 if (ctx
->singlestep_enabled
& (CPU_SINGLE_STEP
| GDBSTUB_SINGLE_STEP
)) {
8559 ctx
->base
.max_insns
= 1;
8563 static void ppc_tr_tb_start(DisasContextBase
*db
, CPUState
*cs
)
8567 static void ppc_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cs
)
8569 tcg_gen_insn_start(dcbase
->pc_next
);
8572 static bool ppc_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cs
,
8573 const CPUBreakpoint
*bp
)
8575 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
8577 gen_update_nip(ctx
, ctx
->base
.pc_next
);
8578 gen_debug_exception(ctx
);
8580 * The address covered by the breakpoint must be included in
8581 * [tb->pc, tb->pc + tb->size) in order to for it to be properly
8582 * cleared -- thus we increment the PC here so that the logic
8583 * setting tb->size below does the right thing.
8585 ctx
->base
.pc_next
+= 4;
8589 static bool is_prefix_insn(DisasContext
*ctx
, uint32_t insn
)
8591 REQUIRE_INSNS_FLAGS2(ctx
, ISA310
);
8592 return opc1(insn
) == 1;
8595 static void ppc_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cs
)
8597 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
8598 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
8599 CPUPPCState
*env
= cs
->env_ptr
;
8604 LOG_DISAS("----------------\n");
8605 LOG_DISAS("nip=" TARGET_FMT_lx
" super=%d ir=%d\n",
8606 ctx
->base
.pc_next
, ctx
->mem_idx
, (int)msr_ir
);
8608 ctx
->cia
= pc
= ctx
->base
.pc_next
;
8609 insn
= translator_ldl_swap(env
, pc
, need_byteswap(ctx
));
8610 ctx
->base
.pc_next
= pc
+= 4;
8612 if (!is_prefix_insn(ctx
, insn
)) {
8613 ok
= (decode_insn32(ctx
, insn
) ||
8614 decode_legacy(cpu
, ctx
, insn
));
8615 } else if ((pc
& 63) == 0) {
8617 * Power v3.1, section 1.9 Exceptions:
8618 * attempt to execute a prefixed instruction that crosses a
8619 * 64-byte address boundary (system alignment error).
8621 gen_exception_err(ctx
, POWERPC_EXCP_ALIGN
, POWERPC_EXCP_ALIGN_INSN
);
8624 uint32_t insn2
= translator_ldl_swap(env
, pc
, need_byteswap(ctx
));
8625 ctx
->base
.pc_next
= pc
+= 4;
8626 ok
= decode_insn64(ctx
, deposit64(insn2
, 32, 32, insn
));
8632 /* End the TB when crossing a page boundary. */
8633 if (ctx
->base
.is_jmp
== DISAS_NEXT
&& !(pc
& ~TARGET_PAGE_MASK
)) {
8634 ctx
->base
.is_jmp
= DISAS_TOO_MANY
;
8637 translator_loop_temp_check(&ctx
->base
);
8640 static void ppc_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cs
)
8642 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
8643 DisasJumpType is_jmp
= ctx
->base
.is_jmp
;
8644 target_ulong nip
= ctx
->base
.pc_next
;
8647 if (is_jmp
== DISAS_NORETURN
) {
8648 /* We have already exited the TB. */
8652 /* Honor single stepping. */
8653 sse
= ctx
->singlestep_enabled
& (CPU_SINGLE_STEP
| GDBSTUB_SINGLE_STEP
);
8654 if (unlikely(sse
)) {
8656 case DISAS_TOO_MANY
:
8657 case DISAS_EXIT_UPDATE
:
8658 case DISAS_CHAIN_UPDATE
:
8659 gen_update_nip(ctx
, nip
);
8665 g_assert_not_reached();
8668 if (sse
& GDBSTUB_SINGLE_STEP
) {
8669 gen_debug_exception(ctx
);
8672 /* else CPU_SINGLE_STEP... */
8673 if (nip
<= 0x100 || nip
> 0xf00) {
8674 gen_helper_raise_exception(cpu_env
, tcg_constant_i32(gen_prep_dbgex(ctx
)));
8680 case DISAS_TOO_MANY
:
8681 if (use_goto_tb(ctx
, nip
)) {
8683 gen_update_nip(ctx
, nip
);
8684 tcg_gen_exit_tb(ctx
->base
.tb
, 0);
8688 case DISAS_CHAIN_UPDATE
:
8689 gen_update_nip(ctx
, nip
);
8692 tcg_gen_lookup_and_goto_ptr();
8695 case DISAS_EXIT_UPDATE
:
8696 gen_update_nip(ctx
, nip
);
8699 tcg_gen_exit_tb(NULL
, 0);
8703 g_assert_not_reached();
8707 static void ppc_tr_disas_log(const DisasContextBase
*dcbase
, CPUState
*cs
)
8709 qemu_log("IN: %s\n", lookup_symbol(dcbase
->pc_first
));
8710 log_target_disas(cs
, dcbase
->pc_first
, dcbase
->tb
->size
);
8713 static const TranslatorOps ppc_tr_ops
= {
8714 .init_disas_context
= ppc_tr_init_disas_context
,
8715 .tb_start
= ppc_tr_tb_start
,
8716 .insn_start
= ppc_tr_insn_start
,
8717 .breakpoint_check
= ppc_tr_breakpoint_check
,
8718 .translate_insn
= ppc_tr_translate_insn
,
8719 .tb_stop
= ppc_tr_tb_stop
,
8720 .disas_log
= ppc_tr_disas_log
,
8723 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
, int max_insns
)
8727 translator_loop(&ppc_tr_ops
, &ctx
.base
, cs
, tb
, max_insns
);
8730 void restore_state_to_opc(CPUPPCState
*env
, TranslationBlock
*tb
,