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ui/cocoa.m: Update to new DisplayChangeListener member names
[qemu/kevin.git] / target-i386 / cpu.c
blobc46286ab3e4add1930faeb0ed22ea0d1cbc8555e
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <string.h>
22 #include <inttypes.h>
23
24 #include "cpu.h"
25 #include "kvm.h"
26
27 #include "qemu-option.h"
28 #include "qemu-config.h"
29
30 #include "qapi/qapi-visit-core.h"
31 #include "arch_init.h"
32
33 #include "hyperv.h"
34
35 #include "hw/hw.h"
36 #if defined(CONFIG_KVM)
37 #include <linux/kvm_para.h>
38 #endif
39
40 #include "sysemu.h"
41 #ifndef CONFIG_USER_ONLY
42 #include "hw/xen.h"
43 #include "hw/sysbus.h"
44 #include "hw/apic_internal.h"
45 #endif
46
47 /* feature flags taken from "Intel Processor Identification and the CPUID
48 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
49 * between feature naming conventions, aliases may be added.
50 */
51 static const char *feature_name[] = {
52 "fpu", "vme", "de", "pse",
53 "tsc", "msr", "pae", "mce",
54 "cx8", "apic", NULL, "sep",
55 "mtrr", "pge", "mca", "cmov",
56 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
57 NULL, "ds" /* Intel dts */, "acpi", "mmx",
58 "fxsr", "sse", "sse2", "ss",
59 "ht" /* Intel htt */, "tm", "ia64", "pbe",
60 };
61 static const char *ext_feature_name[] = {
62 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
63 "ds_cpl", "vmx", "smx", "est",
64 "tm2", "ssse3", "cid", NULL,
65 "fma", "cx16", "xtpr", "pdcm",
66 NULL, "pcid", "dca", "sse4.1|sse4_1",
67 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
68 "tsc-deadline", "aes", "xsave", "osxsave",
69 "avx", NULL, NULL, "hypervisor",
70 };
71 /* Feature names that are already defined on feature_name[] but are set on
72 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
73 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
74 * if and only if CPU vendor is AMD.
75 */
76 static const char *ext2_feature_name[] = {
77 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
78 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
79 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
80 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
81 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
82 "nx|xd", NULL, "mmxext", NULL /* mmx */,
83 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
84 NULL, "lm|i64", "3dnowext", "3dnow",
85 };
86 static const char *ext3_feature_name[] = {
87 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
88 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
89 "3dnowprefetch", "osvw", "ibs", "xop",
90 "skinit", "wdt", NULL, NULL,
91 "fma4", NULL, "cvt16", "nodeid_msr",
92 NULL, NULL, NULL, NULL,
93 NULL, NULL, NULL, NULL,
94 NULL, NULL, NULL, NULL,
95 };
96
97 static const char *kvm_feature_name[] = {
98 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
99 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", NULL,
100 NULL, NULL, NULL, NULL,
101 NULL, NULL, NULL, NULL,
102 NULL, NULL, NULL, NULL,
103 NULL, NULL, NULL, NULL,
104 NULL, NULL, NULL, NULL,
105 NULL, NULL, NULL, NULL,
106 };
107
108 static const char *svm_feature_name[] = {
109 "npt", "lbrv", "svm_lock", "nrip_save",
110 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
111 NULL, NULL, "pause_filter", NULL,
112 "pfthreshold", NULL, NULL, NULL,
113 NULL, NULL, NULL, NULL,
114 NULL, NULL, NULL, NULL,
115 NULL, NULL, NULL, NULL,
116 NULL, NULL, NULL, NULL,
117 };
118
119 static const char *cpuid_7_0_ebx_feature_name[] = {
120 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
121 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
122 NULL, NULL, NULL, NULL, "smap", NULL, NULL, NULL,
123 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
124 };
125
126 /* collects per-function cpuid data
127 */
128 typedef struct model_features_t {
129 uint32_t *guest_feat;
130 uint32_t *host_feat;
131 uint32_t check_feat;
132 const char **flag_names;
133 uint32_t cpuid;
134 } model_features_t;
135
136 int check_cpuid = 0;
137 int enforce_cpuid = 0;
138
139 #if defined(CONFIG_KVM)
140 static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
141 (1 << KVM_FEATURE_NOP_IO_DELAY) |
142 (1 << KVM_FEATURE_MMU_OP) |
143 (1 << KVM_FEATURE_CLOCKSOURCE2) |
144 (1 << KVM_FEATURE_ASYNC_PF) |
145 (1 << KVM_FEATURE_STEAL_TIME) |
146 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
147 static const uint32_t kvm_pv_eoi_features = (0x1 << KVM_FEATURE_PV_EOI);
148 #else
149 static uint32_t kvm_default_features = 0;
150 static const uint32_t kvm_pv_eoi_features = 0;
151 #endif
152
153 void enable_kvm_pv_eoi(void)
154 {
155 kvm_default_features |= kvm_pv_eoi_features;
156 }
157
158 void host_cpuid(uint32_t function, uint32_t count,
159 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
160 {
161 #if defined(CONFIG_KVM)
162 uint32_t vec[4];
163
164 #ifdef __x86_64__
165 asm volatile("cpuid"
166 : "=a"(vec[0]), "=b"(vec[1]),
167 "=c"(vec[2]), "=d"(vec[3])
168 : "0"(function), "c"(count) : "cc");
169 #else
170 asm volatile("pusha \n\t"
171 "cpuid \n\t"
172 "mov %%eax, 0(%2) \n\t"
173 "mov %%ebx, 4(%2) \n\t"
174 "mov %%ecx, 8(%2) \n\t"
175 "mov %%edx, 12(%2) \n\t"
176 "popa"
177 : : "a"(function), "c"(count), "S"(vec)
178 : "memory", "cc");
179 #endif
180
181 if (eax)
182 *eax = vec[0];
183 if (ebx)
184 *ebx = vec[1];
185 if (ecx)
186 *ecx = vec[2];
187 if (edx)
188 *edx = vec[3];
189 #endif
190 }
191
192 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
193
194 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
195 * a substring. ex if !NULL points to the first char after a substring,
196 * otherwise the string is assumed to sized by a terminating nul.
197 * Return lexical ordering of *s1:*s2.
198 */
199 static int sstrcmp(const char *s1, const char *e1, const char *s2,
200 const char *e2)
201 {
202 for (;;) {
203 if (!*s1 || !*s2 || *s1 != *s2)
204 return (*s1 - *s2);
205 ++s1, ++s2;
206 if (s1 == e1 && s2 == e2)
207 return (0);
208 else if (s1 == e1)
209 return (*s2);
210 else if (s2 == e2)
211 return (*s1);
212 }
213 }
214
215 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
216 * '|' delimited (possibly empty) strings in which case search for a match
217 * within the alternatives proceeds left to right. Return 0 for success,
218 * non-zero otherwise.
219 */
220 static int altcmp(const char *s, const char *e, const char *altstr)
221 {
222 const char *p, *q;
223
224 for (q = p = altstr; ; ) {
225 while (*p && *p != '|')
226 ++p;
227 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
228 return (0);
229 if (!*p)
230 return (1);
231 else
232 q = ++p;
233 }
234 }
235
236 /* search featureset for flag *[s..e), if found set corresponding bit in
237 * *pval and return true, otherwise return false
238 */
239 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
240 const char **featureset)
241 {
242 uint32_t mask;
243 const char **ppc;
244 bool found = false;
245
246 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
247 if (*ppc && !altcmp(s, e, *ppc)) {
248 *pval |= mask;
249 found = true;
250 }
251 }
252 return found;
253 }
254
255 static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features,
256 uint32_t *ext_features,
257 uint32_t *ext2_features,
258 uint32_t *ext3_features,
259 uint32_t *kvm_features,
260 uint32_t *svm_features,
261 uint32_t *cpuid_7_0_ebx_features)
262 {
263 if (!lookup_feature(features, flagname, NULL, feature_name) &&
264 !lookup_feature(ext_features, flagname, NULL, ext_feature_name) &&
265 !lookup_feature(ext2_features, flagname, NULL, ext2_feature_name) &&
266 !lookup_feature(ext3_features, flagname, NULL, ext3_feature_name) &&
267 !lookup_feature(kvm_features, flagname, NULL, kvm_feature_name) &&
268 !lookup_feature(svm_features, flagname, NULL, svm_feature_name) &&
269 !lookup_feature(cpuid_7_0_ebx_features, flagname, NULL,
270 cpuid_7_0_ebx_feature_name))
271 fprintf(stderr, "CPU feature %s not found\n", flagname);
272 }
273
274 typedef struct x86_def_t {
275 struct x86_def_t *next;
276 const char *name;
277 uint32_t level;
278 uint32_t vendor1, vendor2, vendor3;
279 int family;
280 int model;
281 int stepping;
282 int tsc_khz;
283 uint32_t features, ext_features, ext2_features, ext3_features;
284 uint32_t kvm_features, svm_features;
285 uint32_t xlevel;
286 char model_id[48];
287 int vendor_override;
288 /* Store the results of Centaur's CPUID instructions */
289 uint32_t ext4_features;
290 uint32_t xlevel2;
291 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
292 uint32_t cpuid_7_0_ebx_features;
293 } x86_def_t;
294
295 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
296 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
297 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
298 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
299 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
300 CPUID_PSE36 | CPUID_FXSR)
301 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
302 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
303 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
304 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
305 CPUID_PAE | CPUID_SEP | CPUID_APIC)
306
307 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
308 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
309 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
310 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
311 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
312 /* partly implemented:
313 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
314 CPUID_PSE36 (needed for Solaris) */
315 /* missing:
316 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
317 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
318 CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
319 CPUID_EXT_HYPERVISOR)
320 /* missing:
321 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
322 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
323 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
324 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
325 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
326 /* missing:
327 CPUID_EXT2_PDPE1GB */
328 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
329 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
330 #define TCG_SVM_FEATURES 0
331 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP)
332
333 /* maintains list of cpu model definitions
334 */
335 static x86_def_t *x86_defs = {NULL};
336
337 /* built-in cpu model definitions (deprecated)
338 */
339 static x86_def_t builtin_x86_defs[] = {
340 {
341 .name = "qemu64",
342 .level = 4,
343 .vendor1 = CPUID_VENDOR_AMD_1,
344 .vendor2 = CPUID_VENDOR_AMD_2,
345 .vendor3 = CPUID_VENDOR_AMD_3,
346 .family = 6,
347 .model = 2,
348 .stepping = 3,
349 .features = PPRO_FEATURES |
350 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
351 CPUID_PSE36,
352 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
353 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
354 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
355 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
356 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
357 .xlevel = 0x8000000A,
358 },
359 {
360 .name = "phenom",
361 .level = 5,
362 .vendor1 = CPUID_VENDOR_AMD_1,
363 .vendor2 = CPUID_VENDOR_AMD_2,
364 .vendor3 = CPUID_VENDOR_AMD_3,
365 .family = 16,
366 .model = 2,
367 .stepping = 3,
368 .features = PPRO_FEATURES |
369 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
370 CPUID_PSE36 | CPUID_VME | CPUID_HT,
371 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
372 CPUID_EXT_POPCNT,
373 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
374 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
375 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
376 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
377 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
378 CPUID_EXT3_CR8LEG,
379 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
380 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
381 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
382 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
383 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
384 .xlevel = 0x8000001A,
385 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
386 },
387 {
388 .name = "core2duo",
389 .level = 10,
390 .family = 6,
391 .model = 15,
392 .stepping = 11,
393 .features = PPRO_FEATURES |
394 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
395 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
396 CPUID_HT | CPUID_TM | CPUID_PBE,
397 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
398 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
399 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
400 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
401 .ext3_features = CPUID_EXT3_LAHF_LM,
402 .xlevel = 0x80000008,
403 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
404 },
405 {
406 .name = "kvm64",
407 .level = 5,
408 .vendor1 = CPUID_VENDOR_INTEL_1,
409 .vendor2 = CPUID_VENDOR_INTEL_2,
410 .vendor3 = CPUID_VENDOR_INTEL_3,
411 .family = 15,
412 .model = 6,
413 .stepping = 1,
414 /* Missing: CPUID_VME, CPUID_HT */
415 .features = PPRO_FEATURES |
416 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
417 CPUID_PSE36,
418 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
419 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
420 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
421 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
422 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
423 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
424 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
425 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
426 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
427 .ext3_features = 0,
428 .xlevel = 0x80000008,
429 .model_id = "Common KVM processor"
430 },
431 {
432 .name = "qemu32",
433 .level = 4,
434 .family = 6,
435 .model = 3,
436 .stepping = 3,
437 .features = PPRO_FEATURES,
438 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
439 .xlevel = 0x80000004,
440 },
441 {
442 .name = "kvm32",
443 .level = 5,
444 .family = 15,
445 .model = 6,
446 .stepping = 1,
447 .features = PPRO_FEATURES |
448 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
449 .ext_features = CPUID_EXT_SSE3,
450 .ext2_features = PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
451 .ext3_features = 0,
452 .xlevel = 0x80000008,
453 .model_id = "Common 32-bit KVM processor"
454 },
455 {
456 .name = "coreduo",
457 .level = 10,
458 .family = 6,
459 .model = 14,
460 .stepping = 8,
461 .features = PPRO_FEATURES | CPUID_VME |
462 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
463 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
464 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
465 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
466 .ext2_features = CPUID_EXT2_NX,
467 .xlevel = 0x80000008,
468 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
469 },
470 {
471 .name = "486",
472 .level = 1,
473 .family = 4,
474 .model = 0,
475 .stepping = 0,
476 .features = I486_FEATURES,
477 .xlevel = 0,
478 },
479 {
480 .name = "pentium",
481 .level = 1,
482 .family = 5,
483 .model = 4,
484 .stepping = 3,
485 .features = PENTIUM_FEATURES,
486 .xlevel = 0,
487 },
488 {
489 .name = "pentium2",
490 .level = 2,
491 .family = 6,
492 .model = 5,
493 .stepping = 2,
494 .features = PENTIUM2_FEATURES,
495 .xlevel = 0,
496 },
497 {
498 .name = "pentium3",
499 .level = 2,
500 .family = 6,
501 .model = 7,
502 .stepping = 3,
503 .features = PENTIUM3_FEATURES,
504 .xlevel = 0,
505 },
506 {
507 .name = "athlon",
508 .level = 2,
509 .vendor1 = CPUID_VENDOR_AMD_1,
510 .vendor2 = CPUID_VENDOR_AMD_2,
511 .vendor3 = CPUID_VENDOR_AMD_3,
512 .family = 6,
513 .model = 2,
514 .stepping = 3,
515 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
516 CPUID_MCA,
517 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
518 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
519 .xlevel = 0x80000008,
520 },
521 {
522 .name = "n270",
523 /* original is on level 10 */
524 .level = 5,
525 .family = 6,
526 .model = 28,
527 .stepping = 2,
528 .features = PPRO_FEATURES |
529 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
530 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
531 /* Some CPUs got no CPUID_SEP */
532 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
533 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
534 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
535 CPUID_EXT2_NX,
536 .ext3_features = CPUID_EXT3_LAHF_LM,
537 .xlevel = 0x8000000A,
538 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
539 },
540 {
541 .name = "Conroe",
542 .level = 2,
543 .vendor1 = CPUID_VENDOR_INTEL_1,
544 .vendor2 = CPUID_VENDOR_INTEL_2,
545 .vendor3 = CPUID_VENDOR_INTEL_3,
546 .family = 6,
547 .model = 2,
548 .stepping = 3,
549 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
550 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
551 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
552 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
553 CPUID_DE | CPUID_FP87,
554 .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
555 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
556 .ext3_features = CPUID_EXT3_LAHF_LM,
557 .xlevel = 0x8000000A,
558 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
559 },
560 {
561 .name = "Penryn",
562 .level = 2,
563 .vendor1 = CPUID_VENDOR_INTEL_1,
564 .vendor2 = CPUID_VENDOR_INTEL_2,
565 .vendor3 = CPUID_VENDOR_INTEL_3,
566 .family = 6,
567 .model = 2,
568 .stepping = 3,
569 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
570 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
571 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
572 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
573 CPUID_DE | CPUID_FP87,
574 .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
575 CPUID_EXT_SSE3,
576 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
577 .ext3_features = CPUID_EXT3_LAHF_LM,
578 .xlevel = 0x8000000A,
579 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
580 },
581 {
582 .name = "Nehalem",
583 .level = 2,
584 .vendor1 = CPUID_VENDOR_INTEL_1,
585 .vendor2 = CPUID_VENDOR_INTEL_2,
586 .vendor3 = CPUID_VENDOR_INTEL_3,
587 .family = 6,
588 .model = 2,
589 .stepping = 3,
590 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
591 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
592 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
593 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
594 CPUID_DE | CPUID_FP87,
595 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
596 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
597 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
598 .ext3_features = CPUID_EXT3_LAHF_LM,
599 .xlevel = 0x8000000A,
600 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
601 },
602 {
603 .name = "Westmere",
604 .level = 11,
605 .vendor1 = CPUID_VENDOR_INTEL_1,
606 .vendor2 = CPUID_VENDOR_INTEL_2,
607 .vendor3 = CPUID_VENDOR_INTEL_3,
608 .family = 6,
609 .model = 44,
610 .stepping = 1,
611 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
612 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
613 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
614 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
615 CPUID_DE | CPUID_FP87,
616 .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
617 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
618 CPUID_EXT_SSE3,
619 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
620 .ext3_features = CPUID_EXT3_LAHF_LM,
621 .xlevel = 0x8000000A,
622 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
623 },
624 {
625 .name = "SandyBridge",
626 .level = 0xd,
627 .vendor1 = CPUID_VENDOR_INTEL_1,
628 .vendor2 = CPUID_VENDOR_INTEL_2,
629 .vendor3 = CPUID_VENDOR_INTEL_3,
630 .family = 6,
631 .model = 42,
632 .stepping = 1,
633 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
634 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
635 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
636 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
637 CPUID_DE | CPUID_FP87,
638 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
639 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
640 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
641 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
642 CPUID_EXT_SSE3,
643 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
644 CPUID_EXT2_SYSCALL,
645 .ext3_features = CPUID_EXT3_LAHF_LM,
646 .xlevel = 0x8000000A,
647 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
648 },
649 {
650 .name = "Opteron_G1",
651 .level = 5,
652 .vendor1 = CPUID_VENDOR_AMD_1,
653 .vendor2 = CPUID_VENDOR_AMD_2,
654 .vendor3 = CPUID_VENDOR_AMD_3,
655 .family = 15,
656 .model = 6,
657 .stepping = 1,
658 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
659 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
660 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
661 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
662 CPUID_DE | CPUID_FP87,
663 .ext_features = CPUID_EXT_SSE3,
664 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
665 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
666 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
667 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
668 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
669 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
670 .xlevel = 0x80000008,
671 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
672 },
673 {
674 .name = "Opteron_G2",
675 .level = 5,
676 .vendor1 = CPUID_VENDOR_AMD_1,
677 .vendor2 = CPUID_VENDOR_AMD_2,
678 .vendor3 = CPUID_VENDOR_AMD_3,
679 .family = 15,
680 .model = 6,
681 .stepping = 1,
682 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
683 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
684 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
685 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
686 CPUID_DE | CPUID_FP87,
687 .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3,
688 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
689 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
690 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
691 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
692 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
693 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
694 CPUID_EXT2_DE | CPUID_EXT2_FPU,
695 .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
696 .xlevel = 0x80000008,
697 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
698 },
699 {
700 .name = "Opteron_G3",
701 .level = 5,
702 .vendor1 = CPUID_VENDOR_AMD_1,
703 .vendor2 = CPUID_VENDOR_AMD_2,
704 .vendor3 = CPUID_VENDOR_AMD_3,
705 .family = 15,
706 .model = 6,
707 .stepping = 1,
708 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
709 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
710 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
711 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
712 CPUID_DE | CPUID_FP87,
713 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
714 CPUID_EXT_SSE3,
715 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
716 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
717 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
718 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
719 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
720 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
721 CPUID_EXT2_DE | CPUID_EXT2_FPU,
722 .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
723 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
724 .xlevel = 0x80000008,
725 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
726 },
727 {
728 .name = "Opteron_G4",
729 .level = 0xd,
730 .vendor1 = CPUID_VENDOR_AMD_1,
731 .vendor2 = CPUID_VENDOR_AMD_2,
732 .vendor3 = CPUID_VENDOR_AMD_3,
733 .family = 21,
734 .model = 1,
735 .stepping = 2,
736 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
737 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
738 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
739 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
740 CPUID_DE | CPUID_FP87,
741 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
742 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
743 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
744 CPUID_EXT_SSE3,
745 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
746 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
747 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
748 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
749 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
750 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
751 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
752 .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
753 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
754 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
755 CPUID_EXT3_LAHF_LM,
756 .xlevel = 0x8000001A,
757 .model_id = "AMD Opteron 62xx class CPU",
758 },
759 };
760
761 static int cpu_x86_fill_model_id(char *str)
762 {
763 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
764 int i;
765
766 for (i = 0; i < 3; i++) {
767 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
768 memcpy(str + i * 16 + 0, &eax, 4);
769 memcpy(str + i * 16 + 4, &ebx, 4);
770 memcpy(str + i * 16 + 8, &ecx, 4);
771 memcpy(str + i * 16 + 12, &edx, 4);
772 }
773 return 0;
774 }
775
776 /* Fill a x86_def_t struct with information about the host CPU, and
777 * the CPU features supported by the host hardware + host kernel
778 *
779 * This function may be called only if KVM is enabled.
780 */
781 static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
782 {
783 KVMState *s = kvm_state;
784 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
785
786 assert(kvm_enabled());
787
788 x86_cpu_def->name = "host";
789 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
790 x86_cpu_def->vendor1 = ebx;
791 x86_cpu_def->vendor2 = edx;
792 x86_cpu_def->vendor3 = ecx;
793
794 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
795 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
796 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
797 x86_cpu_def->stepping = eax & 0x0F;
798
799 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
800 x86_cpu_def->features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
801 x86_cpu_def->ext_features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
802
803 if (x86_cpu_def->level >= 7) {
804 x86_cpu_def->cpuid_7_0_ebx_features =
805 kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
806 } else {
807 x86_cpu_def->cpuid_7_0_ebx_features = 0;
808 }
809
810 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
811 x86_cpu_def->ext2_features =
812 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
813 x86_cpu_def->ext3_features =
814 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
815
816 cpu_x86_fill_model_id(x86_cpu_def->model_id);
817 x86_cpu_def->vendor_override = 0;
818
819 /* Call Centaur's CPUID instruction. */
820 if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
821 x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 &&
822 x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) {
823 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
824 eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
825 if (eax >= 0xC0000001) {
826 /* Support VIA max extended level */
827 x86_cpu_def->xlevel2 = eax;
828 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
829 x86_cpu_def->ext4_features =
830 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
831 }
832 }
833
834 /*
835 * Every SVM feature requires emulation support in KVM - so we can't just
836 * read the host features here. KVM might even support SVM features not
837 * available on the host hardware. Just set all bits and mask out the
838 * unsupported ones later.
839 */
840 x86_cpu_def->svm_features = -1;
841 }
842
843 static int unavailable_host_feature(struct model_features_t *f, uint32_t mask)
844 {
845 int i;
846
847 for (i = 0; i < 32; ++i)
848 if (1 << i & mask) {
849 fprintf(stderr, "warning: host cpuid %04x_%04x lacks requested"
850 " flag '%s' [0x%08x]\n",
851 f->cpuid >> 16, f->cpuid & 0xffff,
852 f->flag_names[i] ? f->flag_names[i] : "[reserved]", mask);
853 break;
854 }
855 return 0;
856 }
857
858 /* best effort attempt to inform user requested cpu flags aren't making
859 * their way to the guest. Note: ft[].check_feat ideally should be
860 * specified via a guest_def field to suppress report of extraneous flags.
861 *
862 * This function may be called only if KVM is enabled.
863 */
864 static int kvm_check_features_against_host(x86_def_t *guest_def)
865 {
866 x86_def_t host_def;
867 uint32_t mask;
868 int rv, i;
869 struct model_features_t ft[] = {
870 {&guest_def->features, &host_def.features,
871 ~0, feature_name, 0x00000000},
872 {&guest_def->ext_features, &host_def.ext_features,
873 ~CPUID_EXT_HYPERVISOR, ext_feature_name, 0x00000001},
874 {&guest_def->ext2_features, &host_def.ext2_features,
875 ~PPRO_FEATURES, ext2_feature_name, 0x80000000},
876 {&guest_def->ext3_features, &host_def.ext3_features,
877 ~CPUID_EXT3_SVM, ext3_feature_name, 0x80000001}};
878
879 assert(kvm_enabled());
880
881 kvm_cpu_fill_host(&host_def);
882 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i)
883 for (mask = 1; mask; mask <<= 1)
884 if (ft[i].check_feat & mask && *ft[i].guest_feat & mask &&
885 !(*ft[i].host_feat & mask)) {
886 unavailable_host_feature(&ft[i], mask);
887 rv = 1;
888 }
889 return rv;
890 }
891
892 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
893 const char *name, Error **errp)
894 {
895 X86CPU *cpu = X86_CPU(obj);
896 CPUX86State *env = &cpu->env;
897 int64_t value;
898
899 value = (env->cpuid_version >> 8) & 0xf;
900 if (value == 0xf) {
901 value += (env->cpuid_version >> 20) & 0xff;
902 }
903 visit_type_int(v, &value, name, errp);
904 }
905
906 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
907 const char *name, Error **errp)
908 {
909 X86CPU *cpu = X86_CPU(obj);
910 CPUX86State *env = &cpu->env;
911 const int64_t min = 0;
912 const int64_t max = 0xff + 0xf;
913 int64_t value;
914
915 visit_type_int(v, &value, name, errp);
916 if (error_is_set(errp)) {
917 return;
918 }
919 if (value < min || value > max) {
920 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
921 name ? name : "null", value, min, max);
922 return;
923 }
924
925 env->cpuid_version &= ~0xff00f00;
926 if (value > 0x0f) {
927 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
928 } else {
929 env->cpuid_version |= value << 8;
930 }
931 }
932
933 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
934 const char *name, Error **errp)
935 {
936 X86CPU *cpu = X86_CPU(obj);
937 CPUX86State *env = &cpu->env;
938 int64_t value;
939
940 value = (env->cpuid_version >> 4) & 0xf;
941 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
942 visit_type_int(v, &value, name, errp);
943 }
944
945 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
946 const char *name, Error **errp)
947 {
948 X86CPU *cpu = X86_CPU(obj);
949 CPUX86State *env = &cpu->env;
950 const int64_t min = 0;
951 const int64_t max = 0xff;
952 int64_t value;
953
954 visit_type_int(v, &value, name, errp);
955 if (error_is_set(errp)) {
956 return;
957 }
958 if (value < min || value > max) {
959 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
960 name ? name : "null", value, min, max);
961 return;
962 }
963
964 env->cpuid_version &= ~0xf00f0;
965 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
966 }
967
968 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
969 void *opaque, const char *name,
970 Error **errp)
971 {
972 X86CPU *cpu = X86_CPU(obj);
973 CPUX86State *env = &cpu->env;
974 int64_t value;
975
976 value = env->cpuid_version & 0xf;
977 visit_type_int(v, &value, name, errp);
978 }
979
980 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
981 void *opaque, const char *name,
982 Error **errp)
983 {
984 X86CPU *cpu = X86_CPU(obj);
985 CPUX86State *env = &cpu->env;
986 const int64_t min = 0;
987 const int64_t max = 0xf;
988 int64_t value;
989
990 visit_type_int(v, &value, name, errp);
991 if (error_is_set(errp)) {
992 return;
993 }
994 if (value < min || value > max) {
995 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
996 name ? name : "null", value, min, max);
997 return;
998 }
999
1000 env->cpuid_version &= ~0xf;
1001 env->cpuid_version |= value & 0xf;
1002 }
1003
1004 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1005 const char *name, Error **errp)
1006 {
1007 X86CPU *cpu = X86_CPU(obj);
1008
1009 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1010 }
1011
1012 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1013 const char *name, Error **errp)
1014 {
1015 X86CPU *cpu = X86_CPU(obj);
1016
1017 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1018 }
1019
1020 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1021 const char *name, Error **errp)
1022 {
1023 X86CPU *cpu = X86_CPU(obj);
1024
1025 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1026 }
1027
1028 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1029 const char *name, Error **errp)
1030 {
1031 X86CPU *cpu = X86_CPU(obj);
1032
1033 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1034 }
1035
1036 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1037 {
1038 X86CPU *cpu = X86_CPU(obj);
1039 CPUX86State *env = &cpu->env;
1040 char *value;
1041 int i;
1042
1043 value = (char *)g_malloc(12 + 1);
1044 for (i = 0; i < 4; i++) {
1045 value[i ] = env->cpuid_vendor1 >> (8 * i);
1046 value[i + 4] = env->cpuid_vendor2 >> (8 * i);
1047 value[i + 8] = env->cpuid_vendor3 >> (8 * i);
1048 }
1049 value[12] = '\0';
1050 return value;
1051 }
1052
1053 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1054 Error **errp)
1055 {
1056 X86CPU *cpu = X86_CPU(obj);
1057 CPUX86State *env = &cpu->env;
1058 int i;
1059
1060 if (strlen(value) != 12) {
1061 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1062 "vendor", value);
1063 return;
1064 }
1065
1066 env->cpuid_vendor1 = 0;
1067 env->cpuid_vendor2 = 0;
1068 env->cpuid_vendor3 = 0;
1069 for (i = 0; i < 4; i++) {
1070 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1071 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1072 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1073 }
1074 env->cpuid_vendor_override = 1;
1075 }
1076
1077 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1078 {
1079 X86CPU *cpu = X86_CPU(obj);
1080 CPUX86State *env = &cpu->env;
1081 char *value;
1082 int i;
1083
1084 value = g_malloc(48 + 1);
1085 for (i = 0; i < 48; i++) {
1086 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1087 }
1088 value[48] = '\0';
1089 return value;
1090 }
1091
1092 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1093 Error **errp)
1094 {
1095 X86CPU *cpu = X86_CPU(obj);
1096 CPUX86State *env = &cpu->env;
1097 int c, len, i;
1098
1099 if (model_id == NULL) {
1100 model_id = "";
1101 }
1102 len = strlen(model_id);
1103 memset(env->cpuid_model, 0, 48);
1104 for (i = 0; i < 48; i++) {
1105 if (i >= len) {
1106 c = '\0';
1107 } else {
1108 c = (uint8_t)model_id[i];
1109 }
1110 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1111 }
1112 }
1113
1114 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1115 const char *name, Error **errp)
1116 {
1117 X86CPU *cpu = X86_CPU(obj);
1118 int64_t value;
1119
1120 value = cpu->env.tsc_khz * 1000;
1121 visit_type_int(v, &value, name, errp);
1122 }
1123
1124 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1125 const char *name, Error **errp)
1126 {
1127 X86CPU *cpu = X86_CPU(obj);
1128 const int64_t min = 0;
1129 const int64_t max = INT64_MAX;
1130 int64_t value;
1131
1132 visit_type_int(v, &value, name, errp);
1133 if (error_is_set(errp)) {
1134 return;
1135 }
1136 if (value < min || value > max) {
1137 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1138 name ? name : "null", value, min, max);
1139 return;
1140 }
1141
1142 cpu->env.tsc_khz = value / 1000;
1143 }
1144
1145 static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *cpu_model)
1146 {
1147 unsigned int i;
1148 x86_def_t *def;
1149
1150 char *s = g_strdup(cpu_model);
1151 char *featurestr, *name = strtok(s, ",");
1152 /* Features to be added*/
1153 uint32_t plus_features = 0, plus_ext_features = 0;
1154 uint32_t plus_ext2_features = 0, plus_ext3_features = 0;
1155 uint32_t plus_kvm_features = kvm_default_features, plus_svm_features = 0;
1156 uint32_t plus_7_0_ebx_features = 0;
1157 /* Features to be removed */
1158 uint32_t minus_features = 0, minus_ext_features = 0;
1159 uint32_t minus_ext2_features = 0, minus_ext3_features = 0;
1160 uint32_t minus_kvm_features = 0, minus_svm_features = 0;
1161 uint32_t minus_7_0_ebx_features = 0;
1162 uint32_t numvalue;
1163
1164 for (def = x86_defs; def; def = def->next)
1165 if (name && !strcmp(name, def->name))
1166 break;
1167 if (kvm_enabled() && name && strcmp(name, "host") == 0) {
1168 kvm_cpu_fill_host(x86_cpu_def);
1169 } else if (!def) {
1170 goto error;
1171 } else {
1172 memcpy(x86_cpu_def, def, sizeof(*def));
1173 }
1174
1175 add_flagname_to_bitmaps("hypervisor", &plus_features,
1176 &plus_ext_features, &plus_ext2_features, &plus_ext3_features,
1177 &plus_kvm_features, &plus_svm_features, &plus_7_0_ebx_features);
1178
1179 featurestr = strtok(NULL, ",");
1180
1181 while (featurestr) {
1182 char *val;
1183 if (featurestr[0] == '+') {
1184 add_flagname_to_bitmaps(featurestr + 1, &plus_features,
1185 &plus_ext_features, &plus_ext2_features,
1186 &plus_ext3_features, &plus_kvm_features,
1187 &plus_svm_features, &plus_7_0_ebx_features);
1188 } else if (featurestr[0] == '-') {
1189 add_flagname_to_bitmaps(featurestr + 1, &minus_features,
1190 &minus_ext_features, &minus_ext2_features,
1191 &minus_ext3_features, &minus_kvm_features,
1192 &minus_svm_features, &minus_7_0_ebx_features);
1193 } else if ((val = strchr(featurestr, '='))) {
1194 *val = 0; val++;
1195 if (!strcmp(featurestr, "family")) {
1196 char *err;
1197 numvalue = strtoul(val, &err, 0);
1198 if (!*val || *err || numvalue > 0xff + 0xf) {
1199 fprintf(stderr, "bad numerical value %s\n", val);
1200 goto error;
1201 }
1202 x86_cpu_def->family = numvalue;
1203 } else if (!strcmp(featurestr, "model")) {
1204 char *err;
1205 numvalue = strtoul(val, &err, 0);
1206 if (!*val || *err || numvalue > 0xff) {
1207 fprintf(stderr, "bad numerical value %s\n", val);
1208 goto error;
1209 }
1210 x86_cpu_def->model = numvalue;
1211 } else if (!strcmp(featurestr, "stepping")) {
1212 char *err;
1213 numvalue = strtoul(val, &err, 0);
1214 if (!*val || *err || numvalue > 0xf) {
1215 fprintf(stderr, "bad numerical value %s\n", val);
1216 goto error;
1217 }
1218 x86_cpu_def->stepping = numvalue ;
1219 } else if (!strcmp(featurestr, "level")) {
1220 char *err;
1221 numvalue = strtoul(val, &err, 0);
1222 if (!*val || *err) {
1223 fprintf(stderr, "bad numerical value %s\n", val);
1224 goto error;
1225 }
1226 x86_cpu_def->level = numvalue;
1227 } else if (!strcmp(featurestr, "xlevel")) {
1228 char *err;
1229 numvalue = strtoul(val, &err, 0);
1230 if (!*val || *err) {
1231 fprintf(stderr, "bad numerical value %s\n", val);
1232 goto error;
1233 }
1234 if (numvalue < 0x80000000) {
1235 numvalue += 0x80000000;
1236 }
1237 x86_cpu_def->xlevel = numvalue;
1238 } else if (!strcmp(featurestr, "vendor")) {
1239 if (strlen(val) != 12) {
1240 fprintf(stderr, "vendor string must be 12 chars long\n");
1241 goto error;
1242 }
1243 x86_cpu_def->vendor1 = 0;
1244 x86_cpu_def->vendor2 = 0;
1245 x86_cpu_def->vendor3 = 0;
1246 for(i = 0; i < 4; i++) {
1247 x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
1248 x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
1249 x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
1250 }
1251 x86_cpu_def->vendor_override = 1;
1252 } else if (!strcmp(featurestr, "model_id")) {
1253 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
1254 val);
1255 } else if (!strcmp(featurestr, "tsc_freq")) {
1256 int64_t tsc_freq;
1257 char *err;
1258
1259 tsc_freq = strtosz_suffix_unit(val, &err,
1260 STRTOSZ_DEFSUFFIX_B, 1000);
1261 if (tsc_freq < 0 || *err) {
1262 fprintf(stderr, "bad numerical value %s\n", val);
1263 goto error;
1264 }
1265 x86_cpu_def->tsc_khz = tsc_freq / 1000;
1266 } else if (!strcmp(featurestr, "hv_spinlocks")) {
1267 char *err;
1268 numvalue = strtoul(val, &err, 0);
1269 if (!*val || *err) {
1270 fprintf(stderr, "bad numerical value %s\n", val);
1271 goto error;
1272 }
1273 hyperv_set_spinlock_retries(numvalue);
1274 } else {
1275 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1276 goto error;
1277 }
1278 } else if (!strcmp(featurestr, "check")) {
1279 check_cpuid = 1;
1280 } else if (!strcmp(featurestr, "enforce")) {
1281 check_cpuid = enforce_cpuid = 1;
1282 } else if (!strcmp(featurestr, "hv_relaxed")) {
1283 hyperv_enable_relaxed_timing(true);
1284 } else if (!strcmp(featurestr, "hv_vapic")) {
1285 hyperv_enable_vapic_recommended(true);
1286 } else {
1287 fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
1288 goto error;
1289 }
1290 featurestr = strtok(NULL, ",");
1291 }
1292 x86_cpu_def->features |= plus_features;
1293 x86_cpu_def->ext_features |= plus_ext_features;
1294 x86_cpu_def->ext2_features |= plus_ext2_features;
1295 x86_cpu_def->ext3_features |= plus_ext3_features;
1296 x86_cpu_def->kvm_features |= plus_kvm_features;
1297 x86_cpu_def->svm_features |= plus_svm_features;
1298 x86_cpu_def->cpuid_7_0_ebx_features |= plus_7_0_ebx_features;
1299 x86_cpu_def->features &= ~minus_features;
1300 x86_cpu_def->ext_features &= ~minus_ext_features;
1301 x86_cpu_def->ext2_features &= ~minus_ext2_features;
1302 x86_cpu_def->ext3_features &= ~minus_ext3_features;
1303 x86_cpu_def->kvm_features &= ~minus_kvm_features;
1304 x86_cpu_def->svm_features &= ~minus_svm_features;
1305 x86_cpu_def->cpuid_7_0_ebx_features &= ~minus_7_0_ebx_features;
1306 if (check_cpuid && kvm_enabled()) {
1307 if (kvm_check_features_against_host(x86_cpu_def) && enforce_cpuid)
1308 goto error;
1309 }
1310 if (x86_cpu_def->cpuid_7_0_ebx_features && x86_cpu_def->level < 7) {
1311 x86_cpu_def->level = 7;
1312 }
1313 g_free(s);
1314 return 0;
1315
1316 error:
1317 g_free(s);
1318 return -1;
1319 }
1320
1321 /* generate a composite string into buf of all cpuid names in featureset
1322 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1323 * if flags, suppress names undefined in featureset.
1324 */
1325 static void listflags(char *buf, int bufsize, uint32_t fbits,
1326 const char **featureset, uint32_t flags)
1327 {
1328 const char **p = &featureset[31];
1329 char *q, *b, bit;
1330 int nc;
1331
1332 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1333 *buf = '\0';
1334 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1335 if (fbits & 1 << bit && (*p || !flags)) {
1336 if (*p)
1337 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1338 else
1339 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1340 if (bufsize <= nc) {
1341 if (b) {
1342 memcpy(b, "...", sizeof("..."));
1343 }
1344 return;
1345 }
1346 q += nc;
1347 bufsize -= nc;
1348 }
1349 }
1350
1351 /* generate CPU information. */
1352 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1353 {
1354 x86_def_t *def;
1355 char buf[256];
1356
1357 for (def = x86_defs; def; def = def->next) {
1358 snprintf(buf, sizeof(buf), "%s", def->name);
1359 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1360 }
1361 if (kvm_enabled()) {
1362 (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
1363 }
1364 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1365 listflags(buf, sizeof(buf), (uint32_t)~0, feature_name, 1);
1366 (*cpu_fprintf)(f, " %s\n", buf);
1367 listflags(buf, sizeof(buf), (uint32_t)~0, ext_feature_name, 1);
1368 (*cpu_fprintf)(f, " %s\n", buf);
1369 listflags(buf, sizeof(buf), (uint32_t)~0, ext2_feature_name, 1);
1370 (*cpu_fprintf)(f, " %s\n", buf);
1371 listflags(buf, sizeof(buf), (uint32_t)~0, ext3_feature_name, 1);
1372 (*cpu_fprintf)(f, " %s\n", buf);
1373 }
1374
1375 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1376 {
1377 CpuDefinitionInfoList *cpu_list = NULL;
1378 x86_def_t *def;
1379
1380 for (def = x86_defs; def; def = def->next) {
1381 CpuDefinitionInfoList *entry;
1382 CpuDefinitionInfo *info;
1383
1384 info = g_malloc0(sizeof(*info));
1385 info->name = g_strdup(def->name);
1386
1387 entry = g_malloc0(sizeof(*entry));
1388 entry->value = info;
1389 entry->next = cpu_list;
1390 cpu_list = entry;
1391 }
1392
1393 return cpu_list;
1394 }
1395
1396 #ifdef CONFIG_KVM
1397 static void filter_features_for_kvm(X86CPU *cpu)
1398 {
1399 CPUX86State *env = &cpu->env;
1400 KVMState *s = kvm_state;
1401
1402 env->cpuid_features &=
1403 kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
1404 env->cpuid_ext_features &=
1405 kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
1406 env->cpuid_ext2_features &=
1407 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1408 env->cpuid_ext3_features &=
1409 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1410 env->cpuid_svm_features &=
1411 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
1412 env->cpuid_7_0_ebx_features &=
1413 kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX);
1414 env->cpuid_kvm_features &=
1415 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1416 env->cpuid_ext4_features &=
1417 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
1418
1419 }
1420 #endif
1421
1422 int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
1423 {
1424 CPUX86State *env = &cpu->env;
1425 x86_def_t def1, *def = &def1;
1426 Error *error = NULL;
1427
1428 memset(def, 0, sizeof(*def));
1429
1430 if (cpu_x86_find_by_name(def, cpu_model) < 0)
1431 return -1;
1432 if (def->vendor1) {
1433 env->cpuid_vendor1 = def->vendor1;
1434 env->cpuid_vendor2 = def->vendor2;
1435 env->cpuid_vendor3 = def->vendor3;
1436 } else {
1437 env->cpuid_vendor1 = CPUID_VENDOR_INTEL_1;
1438 env->cpuid_vendor2 = CPUID_VENDOR_INTEL_2;
1439 env->cpuid_vendor3 = CPUID_VENDOR_INTEL_3;
1440 }
1441 env->cpuid_vendor_override = def->vendor_override;
1442 object_property_set_int(OBJECT(cpu), def->level, "level", &error);
1443 object_property_set_int(OBJECT(cpu), def->family, "family", &error);
1444 object_property_set_int(OBJECT(cpu), def->model, "model", &error);
1445 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &error);
1446 env->cpuid_features = def->features;
1447 env->cpuid_ext_features = def->ext_features;
1448 env->cpuid_ext2_features = def->ext2_features;
1449 env->cpuid_ext3_features = def->ext3_features;
1450 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", &error);
1451 env->cpuid_kvm_features = def->kvm_features;
1452 env->cpuid_svm_features = def->svm_features;
1453 env->cpuid_ext4_features = def->ext4_features;
1454 env->cpuid_7_0_ebx_features = def->cpuid_7_0_ebx_features;
1455 env->cpuid_xlevel2 = def->xlevel2;
1456 object_property_set_int(OBJECT(cpu), (int64_t)def->tsc_khz * 1000,
1457 "tsc-frequency", &error);
1458
1459 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
1460 * CPUID[1].EDX.
1461 */
1462 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
1463 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
1464 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
1465 env->cpuid_ext2_features &= ~CPUID_EXT2_AMD_ALIASES;
1466 env->cpuid_ext2_features |= (def->features & CPUID_EXT2_AMD_ALIASES);
1467 }
1468
1469 if (!kvm_enabled()) {
1470 env->cpuid_features &= TCG_FEATURES;
1471 env->cpuid_ext_features &= TCG_EXT_FEATURES;
1472 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
1473 #ifdef TARGET_X86_64
1474 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
1475 #endif
1476 );
1477 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
1478 env->cpuid_svm_features &= TCG_SVM_FEATURES;
1479 } else {
1480 #ifdef CONFIG_KVM
1481 filter_features_for_kvm(cpu);
1482 #endif
1483 }
1484 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error);
1485 if (error) {
1486 fprintf(stderr, "%s\n", error_get_pretty(error));
1487 error_free(error);
1488 return -1;
1489 }
1490 return 0;
1491 }
1492
1493 #if !defined(CONFIG_USER_ONLY)
1494
1495 void cpu_clear_apic_feature(CPUX86State *env)
1496 {
1497 env->cpuid_features &= ~CPUID_APIC;
1498 }
1499
1500 #endif /* !CONFIG_USER_ONLY */
1501
1502 /* Initialize list of CPU models, filling some non-static fields if necessary
1503 */
1504 void x86_cpudef_setup(void)
1505 {
1506 int i, j;
1507 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
1508
1509 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
1510 x86_def_t *def = &builtin_x86_defs[i];
1511 def->next = x86_defs;
1512
1513 /* Look for specific "cpudef" models that */
1514 /* have the QEMU version in .model_id */
1515 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
1516 if (strcmp(model_with_versions[j], def->name) == 0) {
1517 pstrcpy(def->model_id, sizeof(def->model_id),
1518 "QEMU Virtual CPU version ");
1519 pstrcat(def->model_id, sizeof(def->model_id),
1520 qemu_get_version());
1521 break;
1522 }
1523 }
1524
1525 x86_defs = def;
1526 }
1527 }
1528
1529 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1530 uint32_t *ecx, uint32_t *edx)
1531 {
1532 *ebx = env->cpuid_vendor1;
1533 *edx = env->cpuid_vendor2;
1534 *ecx = env->cpuid_vendor3;
1535
1536 /* sysenter isn't supported on compatibility mode on AMD, syscall
1537 * isn't supported in compatibility mode on Intel.
1538 * Normally we advertise the actual cpu vendor, but you can override
1539 * this if you want to use KVM's sysenter/syscall emulation
1540 * in compatibility mode and when doing cross vendor migration
1541 */
1542 if (kvm_enabled() && ! env->cpuid_vendor_override) {
1543 host_cpuid(0, 0, NULL, ebx, ecx, edx);
1544 }
1545 }
1546
1547 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1548 uint32_t *eax, uint32_t *ebx,
1549 uint32_t *ecx, uint32_t *edx)
1550 {
1551 /* test if maximum index reached */
1552 if (index & 0x80000000) {
1553 if (index > env->cpuid_xlevel) {
1554 if (env->cpuid_xlevel2 > 0) {
1555 /* Handle the Centaur's CPUID instruction. */
1556 if (index > env->cpuid_xlevel2) {
1557 index = env->cpuid_xlevel2;
1558 } else if (index < 0xC0000000) {
1559 index = env->cpuid_xlevel;
1560 }
1561 } else {
1562 index = env->cpuid_xlevel;
1563 }
1564 }
1565 } else {
1566 if (index > env->cpuid_level)
1567 index = env->cpuid_level;
1568 }
1569
1570 switch(index) {
1571 case 0:
1572 *eax = env->cpuid_level;
1573 get_cpuid_vendor(env, ebx, ecx, edx);
1574 break;
1575 case 1:
1576 *eax = env->cpuid_version;
1577 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1578 *ecx = env->cpuid_ext_features;
1579 *edx = env->cpuid_features;
1580 if (env->nr_cores * env->nr_threads > 1) {
1581 *ebx |= (env->nr_cores * env->nr_threads) << 16;
1582 *edx |= 1 << 28; /* HTT bit */
1583 }
1584 break;
1585 case 2:
1586 /* cache info: needed for Pentium Pro compatibility */
1587 *eax = 1;
1588 *ebx = 0;
1589 *ecx = 0;
1590 *edx = 0x2c307d;
1591 break;
1592 case 4:
1593 /* cache info: needed for Core compatibility */
1594 if (env->nr_cores > 1) {
1595 *eax = (env->nr_cores - 1) << 26;
1596 } else {
1597 *eax = 0;
1598 }
1599 switch (count) {
1600 case 0: /* L1 dcache info */
1601 *eax |= 0x0000121;
1602 *ebx = 0x1c0003f;
1603 *ecx = 0x000003f;
1604 *edx = 0x0000001;
1605 break;
1606 case 1: /* L1 icache info */
1607 *eax |= 0x0000122;
1608 *ebx = 0x1c0003f;
1609 *ecx = 0x000003f;
1610 *edx = 0x0000001;
1611 break;
1612 case 2: /* L2 cache info */
1613 *eax |= 0x0000143;
1614 if (env->nr_threads > 1) {
1615 *eax |= (env->nr_threads - 1) << 14;
1616 }
1617 *ebx = 0x3c0003f;
1618 *ecx = 0x0000fff;
1619 *edx = 0x0000001;
1620 break;
1621 default: /* end of info */
1622 *eax = 0;
1623 *ebx = 0;
1624 *ecx = 0;
1625 *edx = 0;
1626 break;
1627 }
1628 break;
1629 case 5:
1630 /* mwait info: needed for Core compatibility */
1631 *eax = 0; /* Smallest monitor-line size in bytes */
1632 *ebx = 0; /* Largest monitor-line size in bytes */
1633 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1634 *edx = 0;
1635 break;
1636 case 6:
1637 /* Thermal and Power Leaf */
1638 *eax = 0;
1639 *ebx = 0;
1640 *ecx = 0;
1641 *edx = 0;
1642 break;
1643 case 7:
1644 /* Structured Extended Feature Flags Enumeration Leaf */
1645 if (count == 0) {
1646 *eax = 0; /* Maximum ECX value for sub-leaves */
1647 *ebx = env->cpuid_7_0_ebx_features; /* Feature flags */
1648 *ecx = 0; /* Reserved */
1649 *edx = 0; /* Reserved */
1650 } else {
1651 *eax = 0;
1652 *ebx = 0;
1653 *ecx = 0;
1654 *edx = 0;
1655 }
1656 break;
1657 case 9:
1658 /* Direct Cache Access Information Leaf */
1659 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1660 *ebx = 0;
1661 *ecx = 0;
1662 *edx = 0;
1663 break;
1664 case 0xA:
1665 /* Architectural Performance Monitoring Leaf */
1666 if (kvm_enabled()) {
1667 KVMState *s = env->kvm_state;
1668
1669 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1670 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1671 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1672 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1673 } else {
1674 *eax = 0;
1675 *ebx = 0;
1676 *ecx = 0;
1677 *edx = 0;
1678 }
1679 break;
1680 case 0xD:
1681 /* Processor Extended State */
1682 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1683 *eax = 0;
1684 *ebx = 0;
1685 *ecx = 0;
1686 *edx = 0;
1687 break;
1688 }
1689 if (kvm_enabled()) {
1690 KVMState *s = env->kvm_state;
1691
1692 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1693 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1694 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1695 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
1696 } else {
1697 *eax = 0;
1698 *ebx = 0;
1699 *ecx = 0;
1700 *edx = 0;
1701 }
1702 break;
1703 case 0x80000000:
1704 *eax = env->cpuid_xlevel;
1705 *ebx = env->cpuid_vendor1;
1706 *edx = env->cpuid_vendor2;
1707 *ecx = env->cpuid_vendor3;
1708 break;
1709 case 0x80000001:
1710 *eax = env->cpuid_version;
1711 *ebx = 0;
1712 *ecx = env->cpuid_ext3_features;
1713 *edx = env->cpuid_ext2_features;
1714
1715 /* The Linux kernel checks for the CMPLegacy bit and
1716 * discards multiple thread information if it is set.
1717 * So dont set it here for Intel to make Linux guests happy.
1718 */
1719 if (env->nr_cores * env->nr_threads > 1) {
1720 uint32_t tebx, tecx, tedx;
1721 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1722 if (tebx != CPUID_VENDOR_INTEL_1 ||
1723 tedx != CPUID_VENDOR_INTEL_2 ||
1724 tecx != CPUID_VENDOR_INTEL_3) {
1725 *ecx |= 1 << 1; /* CmpLegacy bit */
1726 }
1727 }
1728 break;
1729 case 0x80000002:
1730 case 0x80000003:
1731 case 0x80000004:
1732 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1733 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1734 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1735 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1736 break;
1737 case 0x80000005:
1738 /* cache info (L1 cache) */
1739 *eax = 0x01ff01ff;
1740 *ebx = 0x01ff01ff;
1741 *ecx = 0x40020140;
1742 *edx = 0x40020140;
1743 break;
1744 case 0x80000006:
1745 /* cache info (L2 cache) */
1746 *eax = 0;
1747 *ebx = 0x42004200;
1748 *ecx = 0x02008140;
1749 *edx = 0;
1750 break;
1751 case 0x80000008:
1752 /* virtual & phys address size in low 2 bytes. */
1753 /* XXX: This value must match the one used in the MMU code. */
1754 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1755 /* 64 bit processor */
1756 /* XXX: The physical address space is limited to 42 bits in exec.c. */
1757 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1758 } else {
1759 if (env->cpuid_features & CPUID_PSE36)
1760 *eax = 0x00000024; /* 36 bits physical */
1761 else
1762 *eax = 0x00000020; /* 32 bits physical */
1763 }
1764 *ebx = 0;
1765 *ecx = 0;
1766 *edx = 0;
1767 if (env->nr_cores * env->nr_threads > 1) {
1768 *ecx |= (env->nr_cores * env->nr_threads) - 1;
1769 }
1770 break;
1771 case 0x8000000A:
1772 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1773 *eax = 0x00000001; /* SVM Revision */
1774 *ebx = 0x00000010; /* nr of ASIDs */
1775 *ecx = 0;
1776 *edx = env->cpuid_svm_features; /* optional features */
1777 } else {
1778 *eax = 0;
1779 *ebx = 0;
1780 *ecx = 0;
1781 *edx = 0;
1782 }
1783 break;
1784 case 0xC0000000:
1785 *eax = env->cpuid_xlevel2;
1786 *ebx = 0;
1787 *ecx = 0;
1788 *edx = 0;
1789 break;
1790 case 0xC0000001:
1791 /* Support for VIA CPU's CPUID instruction */
1792 *eax = env->cpuid_version;
1793 *ebx = 0;
1794 *ecx = 0;
1795 *edx = env->cpuid_ext4_features;
1796 break;
1797 case 0xC0000002:
1798 case 0xC0000003:
1799 case 0xC0000004:
1800 /* Reserved for the future, and now filled with zero */
1801 *eax = 0;
1802 *ebx = 0;
1803 *ecx = 0;
1804 *edx = 0;
1805 break;
1806 default:
1807 /* reserved values: zero */
1808 *eax = 0;
1809 *ebx = 0;
1810 *ecx = 0;
1811 *edx = 0;
1812 break;
1813 }
1814 }
1815
1816 /* CPUClass::reset() */
1817 static void x86_cpu_reset(CPUState *s)
1818 {
1819 X86CPU *cpu = X86_CPU(s);
1820 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1821 CPUX86State *env = &cpu->env;
1822 int i;
1823
1824 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1825 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
1826 log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1827 }
1828
1829 xcc->parent_reset(s);
1830
1831
1832 memset(env, 0, offsetof(CPUX86State, breakpoints));
1833
1834 tlb_flush(env, 1);
1835
1836 env->old_exception = -1;
1837
1838 /* init to reset state */
1839
1840 #ifdef CONFIG_SOFTMMU
1841 env->hflags |= HF_SOFTMMU_MASK;
1842 #endif
1843 env->hflags2 |= HF2_GIF_MASK;
1844
1845 cpu_x86_update_cr0(env, 0x60000010);
1846 env->a20_mask = ~0x0;
1847 env->smbase = 0x30000;
1848
1849 env->idt.limit = 0xffff;
1850 env->gdt.limit = 0xffff;
1851 env->ldt.limit = 0xffff;
1852 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
1853 env->tr.limit = 0xffff;
1854 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
1855
1856 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
1857 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
1858 DESC_R_MASK | DESC_A_MASK);
1859 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
1860 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1861 DESC_A_MASK);
1862 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
1863 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1864 DESC_A_MASK);
1865 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
1866 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1867 DESC_A_MASK);
1868 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
1869 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1870 DESC_A_MASK);
1871 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
1872 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1873 DESC_A_MASK);
1874
1875 env->eip = 0xfff0;
1876 env->regs[R_EDX] = env->cpuid_version;
1877
1878 env->eflags = 0x2;
1879
1880 /* FPU init */
1881 for (i = 0; i < 8; i++) {
1882 env->fptags[i] = 1;
1883 }
1884 env->fpuc = 0x37f;
1885
1886 env->mxcsr = 0x1f80;
1887
1888 env->pat = 0x0007040600070406ULL;
1889 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
1890
1891 memset(env->dr, 0, sizeof(env->dr));
1892 env->dr[6] = DR6_FIXED_1;
1893 env->dr[7] = DR7_FIXED_1;
1894 cpu_breakpoint_remove_all(env, BP_CPU);
1895 cpu_watchpoint_remove_all(env, BP_CPU);
1896
1897 #if !defined(CONFIG_USER_ONLY)
1898 /* We hard-wire the BSP to the first CPU. */
1899 if (env->cpu_index == 0) {
1900 apic_designate_bsp(env->apic_state);
1901 }
1902
1903 env->halted = !cpu_is_bsp(cpu);
1904 #endif
1905 }
1906
1907 #ifndef CONFIG_USER_ONLY
1908 bool cpu_is_bsp(X86CPU *cpu)
1909 {
1910 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
1911 }
1912
1913 /* TODO: remove me, when reset over QOM tree is implemented */
1914 static void x86_cpu_machine_reset_cb(void *opaque)
1915 {
1916 X86CPU *cpu = opaque;
1917 cpu_reset(CPU(cpu));
1918 }
1919 #endif
1920
1921 static void mce_init(X86CPU *cpu)
1922 {
1923 CPUX86State *cenv = &cpu->env;
1924 unsigned int bank;
1925
1926 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
1927 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
1928 (CPUID_MCE | CPUID_MCA)) {
1929 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
1930 cenv->mcg_ctl = ~(uint64_t)0;
1931 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
1932 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
1933 }
1934 }
1935 }
1936
1937 #define MSI_ADDR_BASE 0xfee00000
1938
1939 #ifndef CONFIG_USER_ONLY
1940 static void x86_cpu_apic_init(X86CPU *cpu, Error **errp)
1941 {
1942 static int apic_mapped;
1943 CPUX86State *env = &cpu->env;
1944 APICCommonState *apic;
1945 const char *apic_type = "apic";
1946
1947 if (kvm_irqchip_in_kernel()) {
1948 apic_type = "kvm-apic";
1949 } else if (xen_enabled()) {
1950 apic_type = "xen-apic";
1951 }
1952
1953 env->apic_state = qdev_try_create(NULL, apic_type);
1954 if (env->apic_state == NULL) {
1955 error_setg(errp, "APIC device '%s' could not be created", apic_type);
1956 return;
1957 }
1958
1959 object_property_add_child(OBJECT(cpu), "apic",
1960 OBJECT(env->apic_state), NULL);
1961 qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
1962 /* TODO: convert to link<> */
1963 apic = APIC_COMMON(env->apic_state);
1964 apic->cpu = cpu;
1965
1966 if (qdev_init(env->apic_state)) {
1967 error_setg(errp, "APIC device '%s' could not be initialized",
1968 object_get_typename(OBJECT(env->apic_state)));
1969 return;
1970 }
1971
1972 /* XXX: mapping more APICs at the same memory location */
1973 if (apic_mapped == 0) {
1974 /* NOTE: the APIC is directly connected to the CPU - it is not
1975 on the global memory bus. */
1976 /* XXX: what if the base changes? */
1977 sysbus_mmio_map(sysbus_from_qdev(env->apic_state), 0, MSI_ADDR_BASE);
1978 apic_mapped = 1;
1979 }
1980 }
1981 #endif
1982
1983 void x86_cpu_realize(Object *obj, Error **errp)
1984 {
1985 X86CPU *cpu = X86_CPU(obj);
1986
1987 #ifndef CONFIG_USER_ONLY
1988 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
1989
1990 if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
1991 x86_cpu_apic_init(cpu, errp);
1992 if (error_is_set(errp)) {
1993 return;
1994 }
1995 }
1996 #endif
1997
1998 mce_init(cpu);
1999 qemu_init_vcpu(&cpu->env);
2000 cpu_reset(CPU(cpu));
2001 }
2002
2003 static void x86_cpu_initfn(Object *obj)
2004 {
2005 X86CPU *cpu = X86_CPU(obj);
2006 CPUX86State *env = &cpu->env;
2007 static int inited;
2008
2009 cpu_exec_init(env);
2010
2011 object_property_add(obj, "family", "int",
2012 x86_cpuid_version_get_family,
2013 x86_cpuid_version_set_family, NULL, NULL, NULL);
2014 object_property_add(obj, "model", "int",
2015 x86_cpuid_version_get_model,
2016 x86_cpuid_version_set_model, NULL, NULL, NULL);
2017 object_property_add(obj, "stepping", "int",
2018 x86_cpuid_version_get_stepping,
2019 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2020 object_property_add(obj, "level", "int",
2021 x86_cpuid_get_level,
2022 x86_cpuid_set_level, NULL, NULL, NULL);
2023 object_property_add(obj, "xlevel", "int",
2024 x86_cpuid_get_xlevel,
2025 x86_cpuid_set_xlevel, NULL, NULL, NULL);
2026 object_property_add_str(obj, "vendor",
2027 x86_cpuid_get_vendor,
2028 x86_cpuid_set_vendor, NULL);
2029 object_property_add_str(obj, "model-id",
2030 x86_cpuid_get_model_id,
2031 x86_cpuid_set_model_id, NULL);
2032 object_property_add(obj, "tsc-frequency", "int",
2033 x86_cpuid_get_tsc_freq,
2034 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2035
2036 env->cpuid_apic_id = env->cpu_index;
2037
2038 /* init various static tables used in TCG mode */
2039 if (tcg_enabled() && !inited) {
2040 inited = 1;
2041 optimize_flags_init();
2042 #ifndef CONFIG_USER_ONLY
2043 cpu_set_debug_excp_handler(breakpoint_handler);
2044 #endif
2045 }
2046 }
2047
2048 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2049 {
2050 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2051 CPUClass *cc = CPU_CLASS(oc);
2052
2053 xcc->parent_reset = cc->reset;
2054 cc->reset = x86_cpu_reset;
2055 }
2056
2057 static const TypeInfo x86_cpu_type_info = {
2058 .name = TYPE_X86_CPU,
2059 .parent = TYPE_CPU,
2060 .instance_size = sizeof(X86CPU),
2061 .instance_init = x86_cpu_initfn,
2062 .abstract = false,
2063 .class_size = sizeof(X86CPUClass),
2064 .class_init = x86_cpu_common_class_init,
2065 };
2066
2067 static void x86_cpu_register_types(void)
2068 {
2069 type_register_static(&x86_cpu_type_info);
2070 }
2071
2072 type_init(x86_cpu_register_types)
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