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trace: split out trace events for target-sparc/ directory
[qemu/kevin.git] / target-ppc / translate_init.c
blobca894ff4af45855a0b91632b08b479eda25e77ef
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "disas/bfd.h"
23 #include "exec/gdbstub.h"
24 #include <sysemu/kvm.h>
25 #include "kvm_ppc.h"
26 #include "sysemu/arch_init.h"
27 #include "sysemu/cpus.h"
28 #include "cpu-models.h"
29 #include "mmu-hash32.h"
30 #include "mmu-hash64.h"
31 #include "qemu/error-report.h"
32 #include "qapi/visitor.h"
33 #include "hw/qdev-properties.h"
34 #include "hw/ppc/ppc.h"
35
36 //#define PPC_DUMP_CPU
37 //#define PPC_DEBUG_SPR
38 //#define PPC_DUMP_SPR_ACCESSES
39 /* #define USE_APPLE_GDB */
40
41 /* Generic callbacks:
42 * do nothing but store/retrieve spr value
43 */
44 static void spr_load_dump_spr(int sprn)
45 {
46 #ifdef PPC_DUMP_SPR_ACCESSES
47 TCGv_i32 t0 = tcg_const_i32(sprn);
48 gen_helper_load_dump_spr(cpu_env, t0);
49 tcg_temp_free_i32(t0);
50 #endif
51 }
52
53 static void spr_read_generic (DisasContext *ctx, int gprn, int sprn)
54 {
55 gen_load_spr(cpu_gpr[gprn], sprn);
56 spr_load_dump_spr(sprn);
57 }
58
59 static void spr_store_dump_spr(int sprn)
60 {
61 #ifdef PPC_DUMP_SPR_ACCESSES
62 TCGv_i32 t0 = tcg_const_i32(sprn);
63 gen_helper_store_dump_spr(cpu_env, t0);
64 tcg_temp_free_i32(t0);
65 #endif
66 }
67
68 static void spr_write_generic (DisasContext *ctx, int sprn, int gprn)
69 {
70 gen_store_spr(sprn, cpu_gpr[gprn]);
71 spr_store_dump_spr(sprn);
72 }
73
74 #if !defined(CONFIG_USER_ONLY)
75 static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
76 {
77 #ifdef TARGET_PPC64
78 TCGv t0 = tcg_temp_new();
79 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
80 gen_store_spr(sprn, t0);
81 tcg_temp_free(t0);
82 spr_store_dump_spr(sprn);
83 #else
84 spr_write_generic(ctx, sprn, gprn);
85 #endif
86 }
87
88 static void spr_write_clear (DisasContext *ctx, int sprn, int gprn)
89 {
90 TCGv t0 = tcg_temp_new();
91 TCGv t1 = tcg_temp_new();
92 gen_load_spr(t0, sprn);
93 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
94 tcg_gen_and_tl(t0, t0, t1);
95 gen_store_spr(sprn, t0);
96 tcg_temp_free(t0);
97 tcg_temp_free(t1);
98 }
99
100 static void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
101 {
102 }
103
104 #endif
105
106 /* SPR common to all PowerPC */
107 /* XER */
108 static void spr_read_xer (DisasContext *ctx, int gprn, int sprn)
109 {
110 gen_read_xer(cpu_gpr[gprn]);
111 }
112
113 static void spr_write_xer (DisasContext *ctx, int sprn, int gprn)
114 {
115 gen_write_xer(cpu_gpr[gprn]);
116 }
117
118 /* LR */
119 static void spr_read_lr (DisasContext *ctx, int gprn, int sprn)
120 {
121 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
122 }
123
124 static void spr_write_lr (DisasContext *ctx, int sprn, int gprn)
125 {
126 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
127 }
128
129 /* CFAR */
130 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
131 static void spr_read_cfar (DisasContext *ctx, int gprn, int sprn)
132 {
133 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
134 }
135
136 static void spr_write_cfar (DisasContext *ctx, int sprn, int gprn)
137 {
138 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
139 }
140 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
141
142 /* CTR */
143 static void spr_read_ctr (DisasContext *ctx, int gprn, int sprn)
144 {
145 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
146 }
147
148 static void spr_write_ctr (DisasContext *ctx, int sprn, int gprn)
149 {
150 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
151 }
152
153 /* User read access to SPR */
154 /* USPRx */
155 /* UMMCRx */
156 /* UPMCx */
157 /* USIA */
158 /* UDECR */
159 static void spr_read_ureg (DisasContext *ctx, int gprn, int sprn)
160 {
161 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
162 }
163
164 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
165 static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
166 {
167 gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
168 }
169 #endif
170
171 /* SPR common to all non-embedded PowerPC */
172 /* DECR */
173 #if !defined(CONFIG_USER_ONLY)
174 static void spr_read_decr (DisasContext *ctx, int gprn, int sprn)
175 {
176 if (ctx->tb->cflags & CF_USE_ICOUNT) {
177 gen_io_start();
178 }
179 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
180 if (ctx->tb->cflags & CF_USE_ICOUNT) {
181 gen_io_end();
182 gen_stop_exception(ctx);
183 }
184 }
185
186 static void spr_write_decr (DisasContext *ctx, int sprn, int gprn)
187 {
188 if (ctx->tb->cflags & CF_USE_ICOUNT) {
189 gen_io_start();
190 }
191 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
192 if (ctx->tb->cflags & CF_USE_ICOUNT) {
193 gen_io_end();
194 gen_stop_exception(ctx);
195 }
196 }
197 #endif
198
199 /* SPR common to all non-embedded PowerPC, except 601 */
200 /* Time base */
201 static void spr_read_tbl (DisasContext *ctx, int gprn, int sprn)
202 {
203 if (ctx->tb->cflags & CF_USE_ICOUNT) {
204 gen_io_start();
205 }
206 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
207 if (ctx->tb->cflags & CF_USE_ICOUNT) {
208 gen_io_end();
209 gen_stop_exception(ctx);
210 }
211 }
212
213 static void spr_read_tbu (DisasContext *ctx, int gprn, int sprn)
214 {
215 if (ctx->tb->cflags & CF_USE_ICOUNT) {
216 gen_io_start();
217 }
218 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
219 if (ctx->tb->cflags & CF_USE_ICOUNT) {
220 gen_io_end();
221 gen_stop_exception(ctx);
222 }
223 }
224
225 __attribute__ (( unused ))
226 static void spr_read_atbl (DisasContext *ctx, int gprn, int sprn)
227 {
228 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
229 }
230
231 __attribute__ (( unused ))
232 static void spr_read_atbu (DisasContext *ctx, int gprn, int sprn)
233 {
234 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
235 }
236
237 #if !defined(CONFIG_USER_ONLY)
238 static void spr_write_tbl (DisasContext *ctx, int sprn, int gprn)
239 {
240 if (ctx->tb->cflags & CF_USE_ICOUNT) {
241 gen_io_start();
242 }
243 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
244 if (ctx->tb->cflags & CF_USE_ICOUNT) {
245 gen_io_end();
246 gen_stop_exception(ctx);
247 }
248 }
249
250 static void spr_write_tbu (DisasContext *ctx, int sprn, int gprn)
251 {
252 if (ctx->tb->cflags & CF_USE_ICOUNT) {
253 gen_io_start();
254 }
255 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
256 if (ctx->tb->cflags & CF_USE_ICOUNT) {
257 gen_io_end();
258 gen_stop_exception(ctx);
259 }
260 }
261
262 __attribute__ (( unused ))
263 static void spr_write_atbl (DisasContext *ctx, int sprn, int gprn)
264 {
265 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
266 }
267
268 __attribute__ (( unused ))
269 static void spr_write_atbu (DisasContext *ctx, int sprn, int gprn)
270 {
271 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
272 }
273
274 #if defined(TARGET_PPC64)
275 __attribute__ (( unused ))
276 static void spr_read_purr (DisasContext *ctx, int gprn, int sprn)
277 {
278 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
279 }
280 #endif
281 #endif
282
283 #if !defined(CONFIG_USER_ONLY)
284 /* IBAT0U...IBAT0U */
285 /* IBAT0L...IBAT7L */
286 static void spr_read_ibat (DisasContext *ctx, int gprn, int sprn)
287 {
288 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
289 }
290
291 static void spr_read_ibat_h (DisasContext *ctx, int gprn, int sprn)
292 {
293 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
294 }
295
296 static void spr_write_ibatu (DisasContext *ctx, int sprn, int gprn)
297 {
298 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
299 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
300 tcg_temp_free_i32(t0);
301 }
302
303 static void spr_write_ibatu_h (DisasContext *ctx, int sprn, int gprn)
304 {
305 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
306 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
307 tcg_temp_free_i32(t0);
308 }
309
310 static void spr_write_ibatl (DisasContext *ctx, int sprn, int gprn)
311 {
312 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
313 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
314 tcg_temp_free_i32(t0);
315 }
316
317 static void spr_write_ibatl_h (DisasContext *ctx, int sprn, int gprn)
318 {
319 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
320 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
321 tcg_temp_free_i32(t0);
322 }
323
324 /* DBAT0U...DBAT7U */
325 /* DBAT0L...DBAT7L */
326 static void spr_read_dbat (DisasContext *ctx, int gprn, int sprn)
327 {
328 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
329 }
330
331 static void spr_read_dbat_h (DisasContext *ctx, int gprn, int sprn)
332 {
333 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
334 }
335
336 static void spr_write_dbatu (DisasContext *ctx, int sprn, int gprn)
337 {
338 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
339 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
340 tcg_temp_free_i32(t0);
341 }
342
343 static void spr_write_dbatu_h (DisasContext *ctx, int sprn, int gprn)
344 {
345 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
346 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
347 tcg_temp_free_i32(t0);
348 }
349
350 static void spr_write_dbatl (DisasContext *ctx, int sprn, int gprn)
351 {
352 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
353 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
354 tcg_temp_free_i32(t0);
355 }
356
357 static void spr_write_dbatl_h (DisasContext *ctx, int sprn, int gprn)
358 {
359 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
360 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
361 tcg_temp_free_i32(t0);
362 }
363
364 /* SDR1 */
365 static void spr_write_sdr1 (DisasContext *ctx, int sprn, int gprn)
366 {
367 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
368 }
369
370 /* 64 bits PowerPC specific SPRs */
371 #if defined(TARGET_PPC64)
372 static void spr_read_hior (DisasContext *ctx, int gprn, int sprn)
373 {
374 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
375 }
376
377 static void spr_write_hior (DisasContext *ctx, int sprn, int gprn)
378 {
379 TCGv t0 = tcg_temp_new();
380 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
381 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
382 tcg_temp_free(t0);
383 }
384 #endif
385 #endif
386
387 /* PowerPC 601 specific registers */
388 /* RTC */
389 static void spr_read_601_rtcl (DisasContext *ctx, int gprn, int sprn)
390 {
391 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
392 }
393
394 static void spr_read_601_rtcu (DisasContext *ctx, int gprn, int sprn)
395 {
396 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
397 }
398
399 #if !defined(CONFIG_USER_ONLY)
400 static void spr_write_601_rtcu (DisasContext *ctx, int sprn, int gprn)
401 {
402 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
403 }
404
405 static void spr_write_601_rtcl (DisasContext *ctx, int sprn, int gprn)
406 {
407 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
408 }
409
410 static void spr_write_hid0_601 (DisasContext *ctx, int sprn, int gprn)
411 {
412 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
413 /* Must stop the translation as endianness may have changed */
414 gen_stop_exception(ctx);
415 }
416 #endif
417
418 /* Unified bats */
419 #if !defined(CONFIG_USER_ONLY)
420 static void spr_read_601_ubat (DisasContext *ctx, int gprn, int sprn)
421 {
422 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
423 }
424
425 static void spr_write_601_ubatu (DisasContext *ctx, int sprn, int gprn)
426 {
427 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
428 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
429 tcg_temp_free_i32(t0);
430 }
431
432 static void spr_write_601_ubatl (DisasContext *ctx, int sprn, int gprn)
433 {
434 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
435 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
436 tcg_temp_free_i32(t0);
437 }
438 #endif
439
440 /* PowerPC 40x specific registers */
441 #if !defined(CONFIG_USER_ONLY)
442 static void spr_read_40x_pit (DisasContext *ctx, int gprn, int sprn)
443 {
444 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
445 }
446
447 static void spr_write_40x_pit (DisasContext *ctx, int sprn, int gprn)
448 {
449 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
450 }
451
452 static void spr_write_40x_dbcr0 (DisasContext *ctx, int sprn, int gprn)
453 {
454 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
455 /* We must stop translation as we may have rebooted */
456 gen_stop_exception(ctx);
457 }
458
459 static void spr_write_40x_sler (DisasContext *ctx, int sprn, int gprn)
460 {
461 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
462 }
463
464 static void spr_write_booke_tcr (DisasContext *ctx, int sprn, int gprn)
465 {
466 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
467 }
468
469 static void spr_write_booke_tsr (DisasContext *ctx, int sprn, int gprn)
470 {
471 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
472 }
473 #endif
474
475 /* PowerPC 403 specific registers */
476 /* PBL1 / PBU1 / PBL2 / PBU2 */
477 #if !defined(CONFIG_USER_ONLY)
478 static void spr_read_403_pbr (DisasContext *ctx, int gprn, int sprn)
479 {
480 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
481 }
482
483 static void spr_write_403_pbr (DisasContext *ctx, int sprn, int gprn)
484 {
485 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
486 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
487 tcg_temp_free_i32(t0);
488 }
489
490 static void spr_write_pir (DisasContext *ctx, int sprn, int gprn)
491 {
492 TCGv t0 = tcg_temp_new();
493 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
494 gen_store_spr(SPR_PIR, t0);
495 tcg_temp_free(t0);
496 }
497 #endif
498
499 /* SPE specific registers */
500 static void spr_read_spefscr (DisasContext *ctx, int gprn, int sprn)
501 {
502 TCGv_i32 t0 = tcg_temp_new_i32();
503 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
504 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
505 tcg_temp_free_i32(t0);
506 }
507
508 static void spr_write_spefscr (DisasContext *ctx, int sprn, int gprn)
509 {
510 TCGv_i32 t0 = tcg_temp_new_i32();
511 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
512 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
513 tcg_temp_free_i32(t0);
514 }
515
516 #if !defined(CONFIG_USER_ONLY)
517 /* Callback used to write the exception vector base */
518 static void spr_write_excp_prefix (DisasContext *ctx, int sprn, int gprn)
519 {
520 TCGv t0 = tcg_temp_new();
521 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
522 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
523 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
524 gen_store_spr(sprn, t0);
525 tcg_temp_free(t0);
526 }
527
528 static void spr_write_excp_vector (DisasContext *ctx, int sprn, int gprn)
529 {
530 int sprn_offs;
531
532 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
533 sprn_offs = sprn - SPR_BOOKE_IVOR0;
534 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
535 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
536 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
537 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
538 } else {
539 printf("Trying to write an unknown exception vector %d %03x\n",
540 sprn, sprn);
541 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
542 return;
543 }
544
545 TCGv t0 = tcg_temp_new();
546 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
547 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
548 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
549 gen_store_spr(sprn, t0);
550 tcg_temp_free(t0);
551 }
552 #endif
553
554 static inline void vscr_init (CPUPPCState *env, uint32_t val)
555 {
556 env->vscr = val;
557 /* Altivec always uses round-to-nearest */
558 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
559 set_flush_to_zero(vscr_nj, &env->vec_status);
560 }
561
562 #ifdef CONFIG_USER_ONLY
563 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
564 oea_read, oea_write, one_reg_id, initial_value) \
565 _spr_register(env, num, name, uea_read, uea_write, initial_value)
566 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
567 oea_read, oea_write, hea_read, hea_write, \
568 one_reg_id, initial_value) \
569 _spr_register(env, num, name, uea_read, uea_write, initial_value)
570 #else
571 #if !defined(CONFIG_KVM)
572 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
573 oea_read, oea_write, one_reg_id, initial_value) \
574 _spr_register(env, num, name, uea_read, uea_write, \
575 oea_read, oea_write, oea_read, oea_write, initial_value)
576 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
577 oea_read, oea_write, hea_read, hea_write, \
578 one_reg_id, initial_value) \
579 _spr_register(env, num, name, uea_read, uea_write, \
580 oea_read, oea_write, hea_read, hea_write, initial_value)
581 #else
582 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
583 oea_read, oea_write, one_reg_id, initial_value) \
584 _spr_register(env, num, name, uea_read, uea_write, \
585 oea_read, oea_write, oea_read, oea_write, \
586 one_reg_id, initial_value)
587 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
588 oea_read, oea_write, hea_read, hea_write, \
589 one_reg_id, initial_value) \
590 _spr_register(env, num, name, uea_read, uea_write, \
591 oea_read, oea_write, hea_read, hea_write, \
592 one_reg_id, initial_value)
593 #endif
594 #endif
595
596 #define spr_register(env, num, name, uea_read, uea_write, \
597 oea_read, oea_write, initial_value) \
598 spr_register_kvm(env, num, name, uea_read, uea_write, \
599 oea_read, oea_write, 0, initial_value)
600
601 #define spr_register_hv(env, num, name, uea_read, uea_write, \
602 oea_read, oea_write, hea_read, hea_write, \
603 initial_value) \
604 spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
605 oea_read, oea_write, hea_read, hea_write, \
606 0, initial_value)
607
608 static inline void _spr_register(CPUPPCState *env, int num,
609 const char *name,
610 void (*uea_read)(DisasContext *ctx, int gprn, int sprn),
611 void (*uea_write)(DisasContext *ctx, int sprn, int gprn),
612 #if !defined(CONFIG_USER_ONLY)
613
614 void (*oea_read)(DisasContext *ctx, int gprn, int sprn),
615 void (*oea_write)(DisasContext *ctx, int sprn, int gprn),
616 void (*hea_read)(DisasContext *opaque, int gprn, int sprn),
617 void (*hea_write)(DisasContext *opaque, int sprn, int gprn),
618 #endif
619 #if defined(CONFIG_KVM)
620 uint64_t one_reg_id,
621 #endif
622 target_ulong initial_value)
623 {
624 ppc_spr_t *spr;
625
626 spr = &env->spr_cb[num];
627 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
628 #if !defined(CONFIG_USER_ONLY)
629 spr->oea_read != NULL || spr->oea_write != NULL ||
630 #endif
631 spr->uea_read != NULL || spr->uea_write != NULL) {
632 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
633 exit(1);
634 }
635 #if defined(PPC_DEBUG_SPR)
636 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
637 name, initial_value);
638 #endif
639 spr->name = name;
640 spr->uea_read = uea_read;
641 spr->uea_write = uea_write;
642 #if !defined(CONFIG_USER_ONLY)
643 spr->oea_read = oea_read;
644 spr->oea_write = oea_write;
645 spr->hea_read = hea_read;
646 spr->hea_write = hea_write;
647 #endif
648 #if defined(CONFIG_KVM)
649 spr->one_reg_id = one_reg_id,
650 #endif
651 env->spr[num] = spr->default_value = initial_value;
652 }
653
654 /* Generic PowerPC SPRs */
655 static void gen_spr_generic (CPUPPCState *env)
656 {
657 /* Integer processing */
658 spr_register(env, SPR_XER, "XER",
659 &spr_read_xer, &spr_write_xer,
660 &spr_read_xer, &spr_write_xer,
661 0x00000000);
662 /* Branch contol */
663 spr_register(env, SPR_LR, "LR",
664 &spr_read_lr, &spr_write_lr,
665 &spr_read_lr, &spr_write_lr,
666 0x00000000);
667 spr_register(env, SPR_CTR, "CTR",
668 &spr_read_ctr, &spr_write_ctr,
669 &spr_read_ctr, &spr_write_ctr,
670 0x00000000);
671 /* Interrupt processing */
672 spr_register(env, SPR_SRR0, "SRR0",
673 SPR_NOACCESS, SPR_NOACCESS,
674 &spr_read_generic, &spr_write_generic,
675 0x00000000);
676 spr_register(env, SPR_SRR1, "SRR1",
677 SPR_NOACCESS, SPR_NOACCESS,
678 &spr_read_generic, &spr_write_generic,
679 0x00000000);
680 /* Processor control */
681 spr_register(env, SPR_SPRG0, "SPRG0",
682 SPR_NOACCESS, SPR_NOACCESS,
683 &spr_read_generic, &spr_write_generic,
684 0x00000000);
685 spr_register(env, SPR_SPRG1, "SPRG1",
686 SPR_NOACCESS, SPR_NOACCESS,
687 &spr_read_generic, &spr_write_generic,
688 0x00000000);
689 spr_register(env, SPR_SPRG2, "SPRG2",
690 SPR_NOACCESS, SPR_NOACCESS,
691 &spr_read_generic, &spr_write_generic,
692 0x00000000);
693 spr_register(env, SPR_SPRG3, "SPRG3",
694 SPR_NOACCESS, SPR_NOACCESS,
695 &spr_read_generic, &spr_write_generic,
696 0x00000000);
697 }
698
699 /* SPR common to all non-embedded PowerPC, including 601 */
700 static void gen_spr_ne_601 (CPUPPCState *env)
701 {
702 /* Exception processing */
703 spr_register_kvm(env, SPR_DSISR, "DSISR",
704 SPR_NOACCESS, SPR_NOACCESS,
705 &spr_read_generic, &spr_write_generic,
706 KVM_REG_PPC_DSISR, 0x00000000);
707 spr_register_kvm(env, SPR_DAR, "DAR",
708 SPR_NOACCESS, SPR_NOACCESS,
709 &spr_read_generic, &spr_write_generic,
710 KVM_REG_PPC_DAR, 0x00000000);
711 /* Timer */
712 spr_register(env, SPR_DECR, "DECR",
713 SPR_NOACCESS, SPR_NOACCESS,
714 &spr_read_decr, &spr_write_decr,
715 0x00000000);
716 /* Memory management */
717 spr_register(env, SPR_SDR1, "SDR1",
718 SPR_NOACCESS, SPR_NOACCESS,
719 &spr_read_generic, &spr_write_sdr1,
720 0x00000000);
721 }
722
723 /* BATs 0-3 */
724 static void gen_low_BATs (CPUPPCState *env)
725 {
726 #if !defined(CONFIG_USER_ONLY)
727 spr_register(env, SPR_IBAT0U, "IBAT0U",
728 SPR_NOACCESS, SPR_NOACCESS,
729 &spr_read_ibat, &spr_write_ibatu,
730 0x00000000);
731 spr_register(env, SPR_IBAT0L, "IBAT0L",
732 SPR_NOACCESS, SPR_NOACCESS,
733 &spr_read_ibat, &spr_write_ibatl,
734 0x00000000);
735 spr_register(env, SPR_IBAT1U, "IBAT1U",
736 SPR_NOACCESS, SPR_NOACCESS,
737 &spr_read_ibat, &spr_write_ibatu,
738 0x00000000);
739 spr_register(env, SPR_IBAT1L, "IBAT1L",
740 SPR_NOACCESS, SPR_NOACCESS,
741 &spr_read_ibat, &spr_write_ibatl,
742 0x00000000);
743 spr_register(env, SPR_IBAT2U, "IBAT2U",
744 SPR_NOACCESS, SPR_NOACCESS,
745 &spr_read_ibat, &spr_write_ibatu,
746 0x00000000);
747 spr_register(env, SPR_IBAT2L, "IBAT2L",
748 SPR_NOACCESS, SPR_NOACCESS,
749 &spr_read_ibat, &spr_write_ibatl,
750 0x00000000);
751 spr_register(env, SPR_IBAT3U, "IBAT3U",
752 SPR_NOACCESS, SPR_NOACCESS,
753 &spr_read_ibat, &spr_write_ibatu,
754 0x00000000);
755 spr_register(env, SPR_IBAT3L, "IBAT3L",
756 SPR_NOACCESS, SPR_NOACCESS,
757 &spr_read_ibat, &spr_write_ibatl,
758 0x00000000);
759 spr_register(env, SPR_DBAT0U, "DBAT0U",
760 SPR_NOACCESS, SPR_NOACCESS,
761 &spr_read_dbat, &spr_write_dbatu,
762 0x00000000);
763 spr_register(env, SPR_DBAT0L, "DBAT0L",
764 SPR_NOACCESS, SPR_NOACCESS,
765 &spr_read_dbat, &spr_write_dbatl,
766 0x00000000);
767 spr_register(env, SPR_DBAT1U, "DBAT1U",
768 SPR_NOACCESS, SPR_NOACCESS,
769 &spr_read_dbat, &spr_write_dbatu,
770 0x00000000);
771 spr_register(env, SPR_DBAT1L, "DBAT1L",
772 SPR_NOACCESS, SPR_NOACCESS,
773 &spr_read_dbat, &spr_write_dbatl,
774 0x00000000);
775 spr_register(env, SPR_DBAT2U, "DBAT2U",
776 SPR_NOACCESS, SPR_NOACCESS,
777 &spr_read_dbat, &spr_write_dbatu,
778 0x00000000);
779 spr_register(env, SPR_DBAT2L, "DBAT2L",
780 SPR_NOACCESS, SPR_NOACCESS,
781 &spr_read_dbat, &spr_write_dbatl,
782 0x00000000);
783 spr_register(env, SPR_DBAT3U, "DBAT3U",
784 SPR_NOACCESS, SPR_NOACCESS,
785 &spr_read_dbat, &spr_write_dbatu,
786 0x00000000);
787 spr_register(env, SPR_DBAT3L, "DBAT3L",
788 SPR_NOACCESS, SPR_NOACCESS,
789 &spr_read_dbat, &spr_write_dbatl,
790 0x00000000);
791 env->nb_BATs += 4;
792 #endif
793 }
794
795 /* BATs 4-7 */
796 static void gen_high_BATs (CPUPPCState *env)
797 {
798 #if !defined(CONFIG_USER_ONLY)
799 spr_register(env, SPR_IBAT4U, "IBAT4U",
800 SPR_NOACCESS, SPR_NOACCESS,
801 &spr_read_ibat_h, &spr_write_ibatu_h,
802 0x00000000);
803 spr_register(env, SPR_IBAT4L, "IBAT4L",
804 SPR_NOACCESS, SPR_NOACCESS,
805 &spr_read_ibat_h, &spr_write_ibatl_h,
806 0x00000000);
807 spr_register(env, SPR_IBAT5U, "IBAT5U",
808 SPR_NOACCESS, SPR_NOACCESS,
809 &spr_read_ibat_h, &spr_write_ibatu_h,
810 0x00000000);
811 spr_register(env, SPR_IBAT5L, "IBAT5L",
812 SPR_NOACCESS, SPR_NOACCESS,
813 &spr_read_ibat_h, &spr_write_ibatl_h,
814 0x00000000);
815 spr_register(env, SPR_IBAT6U, "IBAT6U",
816 SPR_NOACCESS, SPR_NOACCESS,
817 &spr_read_ibat_h, &spr_write_ibatu_h,
818 0x00000000);
819 spr_register(env, SPR_IBAT6L, "IBAT6L",
820 SPR_NOACCESS, SPR_NOACCESS,
821 &spr_read_ibat_h, &spr_write_ibatl_h,
822 0x00000000);
823 spr_register(env, SPR_IBAT7U, "IBAT7U",
824 SPR_NOACCESS, SPR_NOACCESS,
825 &spr_read_ibat_h, &spr_write_ibatu_h,
826 0x00000000);
827 spr_register(env, SPR_IBAT7L, "IBAT7L",
828 SPR_NOACCESS, SPR_NOACCESS,
829 &spr_read_ibat_h, &spr_write_ibatl_h,
830 0x00000000);
831 spr_register(env, SPR_DBAT4U, "DBAT4U",
832 SPR_NOACCESS, SPR_NOACCESS,
833 &spr_read_dbat_h, &spr_write_dbatu_h,
834 0x00000000);
835 spr_register(env, SPR_DBAT4L, "DBAT4L",
836 SPR_NOACCESS, SPR_NOACCESS,
837 &spr_read_dbat_h, &spr_write_dbatl_h,
838 0x00000000);
839 spr_register(env, SPR_DBAT5U, "DBAT5U",
840 SPR_NOACCESS, SPR_NOACCESS,
841 &spr_read_dbat_h, &spr_write_dbatu_h,
842 0x00000000);
843 spr_register(env, SPR_DBAT5L, "DBAT5L",
844 SPR_NOACCESS, SPR_NOACCESS,
845 &spr_read_dbat_h, &spr_write_dbatl_h,
846 0x00000000);
847 spr_register(env, SPR_DBAT6U, "DBAT6U",
848 SPR_NOACCESS, SPR_NOACCESS,
849 &spr_read_dbat_h, &spr_write_dbatu_h,
850 0x00000000);
851 spr_register(env, SPR_DBAT6L, "DBAT6L",
852 SPR_NOACCESS, SPR_NOACCESS,
853 &spr_read_dbat_h, &spr_write_dbatl_h,
854 0x00000000);
855 spr_register(env, SPR_DBAT7U, "DBAT7U",
856 SPR_NOACCESS, SPR_NOACCESS,
857 &spr_read_dbat_h, &spr_write_dbatu_h,
858 0x00000000);
859 spr_register(env, SPR_DBAT7L, "DBAT7L",
860 SPR_NOACCESS, SPR_NOACCESS,
861 &spr_read_dbat_h, &spr_write_dbatl_h,
862 0x00000000);
863 env->nb_BATs += 4;
864 #endif
865 }
866
867 /* Generic PowerPC time base */
868 static void gen_tbl (CPUPPCState *env)
869 {
870 spr_register(env, SPR_VTBL, "TBL",
871 &spr_read_tbl, SPR_NOACCESS,
872 &spr_read_tbl, SPR_NOACCESS,
873 0x00000000);
874 spr_register(env, SPR_TBL, "TBL",
875 &spr_read_tbl, SPR_NOACCESS,
876 &spr_read_tbl, &spr_write_tbl,
877 0x00000000);
878 spr_register(env, SPR_VTBU, "TBU",
879 &spr_read_tbu, SPR_NOACCESS,
880 &spr_read_tbu, SPR_NOACCESS,
881 0x00000000);
882 spr_register(env, SPR_TBU, "TBU",
883 &spr_read_tbu, SPR_NOACCESS,
884 &spr_read_tbu, &spr_write_tbu,
885 0x00000000);
886 }
887
888 /* Softare table search registers */
889 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
890 {
891 #if !defined(CONFIG_USER_ONLY)
892 env->nb_tlb = nb_tlbs;
893 env->nb_ways = nb_ways;
894 env->id_tlbs = 1;
895 env->tlb_type = TLB_6XX;
896 spr_register(env, SPR_DMISS, "DMISS",
897 SPR_NOACCESS, SPR_NOACCESS,
898 &spr_read_generic, SPR_NOACCESS,
899 0x00000000);
900 spr_register(env, SPR_DCMP, "DCMP",
901 SPR_NOACCESS, SPR_NOACCESS,
902 &spr_read_generic, SPR_NOACCESS,
903 0x00000000);
904 spr_register(env, SPR_HASH1, "HASH1",
905 SPR_NOACCESS, SPR_NOACCESS,
906 &spr_read_generic, SPR_NOACCESS,
907 0x00000000);
908 spr_register(env, SPR_HASH2, "HASH2",
909 SPR_NOACCESS, SPR_NOACCESS,
910 &spr_read_generic, SPR_NOACCESS,
911 0x00000000);
912 spr_register(env, SPR_IMISS, "IMISS",
913 SPR_NOACCESS, SPR_NOACCESS,
914 &spr_read_generic, SPR_NOACCESS,
915 0x00000000);
916 spr_register(env, SPR_ICMP, "ICMP",
917 SPR_NOACCESS, SPR_NOACCESS,
918 &spr_read_generic, SPR_NOACCESS,
919 0x00000000);
920 spr_register(env, SPR_RPA, "RPA",
921 SPR_NOACCESS, SPR_NOACCESS,
922 &spr_read_generic, &spr_write_generic,
923 0x00000000);
924 #endif
925 }
926
927 /* SPR common to MPC755 and G2 */
928 static void gen_spr_G2_755 (CPUPPCState *env)
929 {
930 /* SGPRs */
931 spr_register(env, SPR_SPRG4, "SPRG4",
932 SPR_NOACCESS, SPR_NOACCESS,
933 &spr_read_generic, &spr_write_generic,
934 0x00000000);
935 spr_register(env, SPR_SPRG5, "SPRG5",
936 SPR_NOACCESS, SPR_NOACCESS,
937 &spr_read_generic, &spr_write_generic,
938 0x00000000);
939 spr_register(env, SPR_SPRG6, "SPRG6",
940 SPR_NOACCESS, SPR_NOACCESS,
941 &spr_read_generic, &spr_write_generic,
942 0x00000000);
943 spr_register(env, SPR_SPRG7, "SPRG7",
944 SPR_NOACCESS, SPR_NOACCESS,
945 &spr_read_generic, &spr_write_generic,
946 0x00000000);
947 }
948
949 /* SPR common to all 7xx PowerPC implementations */
950 static void gen_spr_7xx (CPUPPCState *env)
951 {
952 /* Breakpoints */
953 /* XXX : not implemented */
954 spr_register_kvm(env, SPR_DABR, "DABR",
955 SPR_NOACCESS, SPR_NOACCESS,
956 &spr_read_generic, &spr_write_generic,
957 KVM_REG_PPC_DABR, 0x00000000);
958 /* XXX : not implemented */
959 spr_register(env, SPR_IABR, "IABR",
960 SPR_NOACCESS, SPR_NOACCESS,
961 &spr_read_generic, &spr_write_generic,
962 0x00000000);
963 /* Cache management */
964 /* XXX : not implemented */
965 spr_register(env, SPR_ICTC, "ICTC",
966 SPR_NOACCESS, SPR_NOACCESS,
967 &spr_read_generic, &spr_write_generic,
968 0x00000000);
969 /* Performance monitors */
970 /* XXX : not implemented */
971 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
972 SPR_NOACCESS, SPR_NOACCESS,
973 &spr_read_generic, &spr_write_generic,
974 0x00000000);
975 /* XXX : not implemented */
976 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
977 SPR_NOACCESS, SPR_NOACCESS,
978 &spr_read_generic, &spr_write_generic,
979 0x00000000);
980 /* XXX : not implemented */
981 spr_register(env, SPR_7XX_PMC1, "PMC1",
982 SPR_NOACCESS, SPR_NOACCESS,
983 &spr_read_generic, &spr_write_generic,
984 0x00000000);
985 /* XXX : not implemented */
986 spr_register(env, SPR_7XX_PMC2, "PMC2",
987 SPR_NOACCESS, SPR_NOACCESS,
988 &spr_read_generic, &spr_write_generic,
989 0x00000000);
990 /* XXX : not implemented */
991 spr_register(env, SPR_7XX_PMC3, "PMC3",
992 SPR_NOACCESS, SPR_NOACCESS,
993 &spr_read_generic, &spr_write_generic,
994 0x00000000);
995 /* XXX : not implemented */
996 spr_register(env, SPR_7XX_PMC4, "PMC4",
997 SPR_NOACCESS, SPR_NOACCESS,
998 &spr_read_generic, &spr_write_generic,
999 0x00000000);
1000 /* XXX : not implemented */
1001 spr_register(env, SPR_7XX_SIAR, "SIAR",
1002 SPR_NOACCESS, SPR_NOACCESS,
1003 &spr_read_generic, SPR_NOACCESS,
1004 0x00000000);
1005 /* XXX : not implemented */
1006 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
1007 &spr_read_ureg, SPR_NOACCESS,
1008 &spr_read_ureg, SPR_NOACCESS,
1009 0x00000000);
1010 /* XXX : not implemented */
1011 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
1012 &spr_read_ureg, SPR_NOACCESS,
1013 &spr_read_ureg, SPR_NOACCESS,
1014 0x00000000);
1015 /* XXX : not implemented */
1016 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
1017 &spr_read_ureg, SPR_NOACCESS,
1018 &spr_read_ureg, SPR_NOACCESS,
1019 0x00000000);
1020 /* XXX : not implemented */
1021 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
1022 &spr_read_ureg, SPR_NOACCESS,
1023 &spr_read_ureg, SPR_NOACCESS,
1024 0x00000000);
1025 /* XXX : not implemented */
1026 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
1027 &spr_read_ureg, SPR_NOACCESS,
1028 &spr_read_ureg, SPR_NOACCESS,
1029 0x00000000);
1030 /* XXX : not implemented */
1031 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
1032 &spr_read_ureg, SPR_NOACCESS,
1033 &spr_read_ureg, SPR_NOACCESS,
1034 0x00000000);
1035 /* XXX : not implemented */
1036 spr_register(env, SPR_7XX_USIAR, "USIAR",
1037 &spr_read_ureg, SPR_NOACCESS,
1038 &spr_read_ureg, SPR_NOACCESS,
1039 0x00000000);
1040 /* External access control */
1041 /* XXX : not implemented */
1042 spr_register(env, SPR_EAR, "EAR",
1043 SPR_NOACCESS, SPR_NOACCESS,
1044 &spr_read_generic, &spr_write_generic,
1045 0x00000000);
1046 }
1047
1048 #ifdef TARGET_PPC64
1049 #ifndef CONFIG_USER_ONLY
1050 static void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
1051 {
1052 TCGv t0 = tcg_temp_new();
1053 TCGv t1 = tcg_temp_new();
1054 TCGv t2 = tcg_temp_new();
1055
1056 /* Note, the HV=1 PR=0 case is handled earlier by simply using
1057 * spr_write_generic for HV mode in the SPR table
1058 */
1059
1060 /* Build insertion mask into t1 based on context */
1061 if (ctx->pr) {
1062 gen_load_spr(t1, SPR_UAMOR);
1063 } else {
1064 gen_load_spr(t1, SPR_AMOR);
1065 }
1066
1067 /* Mask new bits into t2 */
1068 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1069
1070 /* Load AMR and clear new bits in t0 */
1071 gen_load_spr(t0, SPR_AMR);
1072 tcg_gen_andc_tl(t0, t0, t1);
1073
1074 /* Or'in new bits and write it out */
1075 tcg_gen_or_tl(t0, t0, t2);
1076 gen_store_spr(SPR_AMR, t0);
1077 spr_store_dump_spr(SPR_AMR);
1078
1079 tcg_temp_free(t0);
1080 tcg_temp_free(t1);
1081 tcg_temp_free(t2);
1082 }
1083
1084 static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
1085 {
1086 TCGv t0 = tcg_temp_new();
1087 TCGv t1 = tcg_temp_new();
1088 TCGv t2 = tcg_temp_new();
1089
1090 /* Note, the HV=1 case is handled earlier by simply using
1091 * spr_write_generic for HV mode in the SPR table
1092 */
1093
1094 /* Build insertion mask into t1 based on context */
1095 gen_load_spr(t1, SPR_AMOR);
1096
1097 /* Mask new bits into t2 */
1098 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1099
1100 /* Load AMR and clear new bits in t0 */
1101 gen_load_spr(t0, SPR_UAMOR);
1102 tcg_gen_andc_tl(t0, t0, t1);
1103
1104 /* Or'in new bits and write it out */
1105 tcg_gen_or_tl(t0, t0, t2);
1106 gen_store_spr(SPR_UAMOR, t0);
1107 spr_store_dump_spr(SPR_UAMOR);
1108
1109 tcg_temp_free(t0);
1110 tcg_temp_free(t1);
1111 tcg_temp_free(t2);
1112 }
1113
1114 static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
1115 {
1116 TCGv t0 = tcg_temp_new();
1117 TCGv t1 = tcg_temp_new();
1118 TCGv t2 = tcg_temp_new();
1119
1120 /* Note, the HV=1 case is handled earlier by simply using
1121 * spr_write_generic for HV mode in the SPR table
1122 */
1123
1124 /* Build insertion mask into t1 based on context */
1125 gen_load_spr(t1, SPR_AMOR);
1126
1127 /* Mask new bits into t2 */
1128 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1129
1130 /* Load AMR and clear new bits in t0 */
1131 gen_load_spr(t0, SPR_IAMR);
1132 tcg_gen_andc_tl(t0, t0, t1);
1133
1134 /* Or'in new bits and write it out */
1135 tcg_gen_or_tl(t0, t0, t2);
1136 gen_store_spr(SPR_IAMR, t0);
1137 spr_store_dump_spr(SPR_IAMR);
1138
1139 tcg_temp_free(t0);
1140 tcg_temp_free(t1);
1141 tcg_temp_free(t2);
1142 }
1143 #endif /* CONFIG_USER_ONLY */
1144
1145 static void gen_spr_amr(CPUPPCState *env, bool has_iamr)
1146 {
1147 #ifndef CONFIG_USER_ONLY
1148 /* Virtual Page Class Key protection */
1149 /* The AMR is accessible either via SPR 13 or SPR 29. 13 is
1150 * userspace accessible, 29 is privileged. So we only need to set
1151 * the kvm ONE_REG id on one of them, we use 29 */
1152 spr_register(env, SPR_UAMR, "UAMR",
1153 &spr_read_generic, &spr_write_amr,
1154 &spr_read_generic, &spr_write_amr,
1155 0);
1156 spr_register_kvm_hv(env, SPR_AMR, "AMR",
1157 SPR_NOACCESS, SPR_NOACCESS,
1158 &spr_read_generic, &spr_write_amr,
1159 &spr_read_generic, &spr_write_generic,
1160 KVM_REG_PPC_AMR, 0);
1161 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
1162 SPR_NOACCESS, SPR_NOACCESS,
1163 &spr_read_generic, &spr_write_uamor,
1164 &spr_read_generic, &spr_write_generic,
1165 KVM_REG_PPC_UAMOR, 0);
1166 spr_register_hv(env, SPR_AMOR, "AMOR",
1167 SPR_NOACCESS, SPR_NOACCESS,
1168 SPR_NOACCESS, SPR_NOACCESS,
1169 &spr_read_generic, &spr_write_generic,
1170 0);
1171 if (has_iamr) {
1172 spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
1173 SPR_NOACCESS, SPR_NOACCESS,
1174 &spr_read_generic, &spr_write_iamr,
1175 &spr_read_generic, &spr_write_generic,
1176 KVM_REG_PPC_IAMR, 0);
1177 }
1178 #endif /* !CONFIG_USER_ONLY */
1179 }
1180 #endif /* TARGET_PPC64 */
1181
1182 static void gen_spr_thrm (CPUPPCState *env)
1183 {
1184 /* Thermal management */
1185 /* XXX : not implemented */
1186 spr_register(env, SPR_THRM1, "THRM1",
1187 SPR_NOACCESS, SPR_NOACCESS,
1188 &spr_read_generic, &spr_write_generic,
1189 0x00000000);
1190 /* XXX : not implemented */
1191 spr_register(env, SPR_THRM2, "THRM2",
1192 SPR_NOACCESS, SPR_NOACCESS,
1193 &spr_read_generic, &spr_write_generic,
1194 0x00000000);
1195 /* XXX : not implemented */
1196 spr_register(env, SPR_THRM3, "THRM3",
1197 SPR_NOACCESS, SPR_NOACCESS,
1198 &spr_read_generic, &spr_write_generic,
1199 0x00000000);
1200 }
1201
1202 /* SPR specific to PowerPC 604 implementation */
1203 static void gen_spr_604 (CPUPPCState *env)
1204 {
1205 /* Processor identification */
1206 spr_register(env, SPR_PIR, "PIR",
1207 SPR_NOACCESS, SPR_NOACCESS,
1208 &spr_read_generic, &spr_write_pir,
1209 0x00000000);
1210 /* Breakpoints */
1211 /* XXX : not implemented */
1212 spr_register(env, SPR_IABR, "IABR",
1213 SPR_NOACCESS, SPR_NOACCESS,
1214 &spr_read_generic, &spr_write_generic,
1215 0x00000000);
1216 /* XXX : not implemented */
1217 spr_register_kvm(env, SPR_DABR, "DABR",
1218 SPR_NOACCESS, SPR_NOACCESS,
1219 &spr_read_generic, &spr_write_generic,
1220 KVM_REG_PPC_DABR, 0x00000000);
1221 /* Performance counters */
1222 /* XXX : not implemented */
1223 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
1224 SPR_NOACCESS, SPR_NOACCESS,
1225 &spr_read_generic, &spr_write_generic,
1226 0x00000000);
1227 /* XXX : not implemented */
1228 spr_register(env, SPR_7XX_PMC1, "PMC1",
1229 SPR_NOACCESS, SPR_NOACCESS,
1230 &spr_read_generic, &spr_write_generic,
1231 0x00000000);
1232 /* XXX : not implemented */
1233 spr_register(env, SPR_7XX_PMC2, "PMC2",
1234 SPR_NOACCESS, SPR_NOACCESS,
1235 &spr_read_generic, &spr_write_generic,
1236 0x00000000);
1237 /* XXX : not implemented */
1238 spr_register(env, SPR_7XX_SIAR, "SIAR",
1239 SPR_NOACCESS, SPR_NOACCESS,
1240 &spr_read_generic, SPR_NOACCESS,
1241 0x00000000);
1242 /* XXX : not implemented */
1243 spr_register(env, SPR_SDA, "SDA",
1244 SPR_NOACCESS, SPR_NOACCESS,
1245 &spr_read_generic, SPR_NOACCESS,
1246 0x00000000);
1247 /* External access control */
1248 /* XXX : not implemented */
1249 spr_register(env, SPR_EAR, "EAR",
1250 SPR_NOACCESS, SPR_NOACCESS,
1251 &spr_read_generic, &spr_write_generic,
1252 0x00000000);
1253 }
1254
1255 /* SPR specific to PowerPC 603 implementation */
1256 static void gen_spr_603 (CPUPPCState *env)
1257 {
1258 /* External access control */
1259 /* XXX : not implemented */
1260 spr_register(env, SPR_EAR, "EAR",
1261 SPR_NOACCESS, SPR_NOACCESS,
1262 &spr_read_generic, &spr_write_generic,
1263 0x00000000);
1264 /* Breakpoints */
1265 /* XXX : not implemented */
1266 spr_register(env, SPR_IABR, "IABR",
1267 SPR_NOACCESS, SPR_NOACCESS,
1268 &spr_read_generic, &spr_write_generic,
1269 0x00000000);
1270
1271 }
1272
1273 /* SPR specific to PowerPC G2 implementation */
1274 static void gen_spr_G2 (CPUPPCState *env)
1275 {
1276 /* Memory base address */
1277 /* MBAR */
1278 /* XXX : not implemented */
1279 spr_register(env, SPR_MBAR, "MBAR",
1280 SPR_NOACCESS, SPR_NOACCESS,
1281 &spr_read_generic, &spr_write_generic,
1282 0x00000000);
1283 /* Exception processing */
1284 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1285 SPR_NOACCESS, SPR_NOACCESS,
1286 &spr_read_generic, &spr_write_generic,
1287 0x00000000);
1288 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1289 SPR_NOACCESS, SPR_NOACCESS,
1290 &spr_read_generic, &spr_write_generic,
1291 0x00000000);
1292 /* Breakpoints */
1293 /* XXX : not implemented */
1294 spr_register(env, SPR_DABR, "DABR",
1295 SPR_NOACCESS, SPR_NOACCESS,
1296 &spr_read_generic, &spr_write_generic,
1297 0x00000000);
1298 /* XXX : not implemented */
1299 spr_register(env, SPR_DABR2, "DABR2",
1300 SPR_NOACCESS, SPR_NOACCESS,
1301 &spr_read_generic, &spr_write_generic,
1302 0x00000000);
1303 /* XXX : not implemented */
1304 spr_register(env, SPR_IABR, "IABR",
1305 SPR_NOACCESS, SPR_NOACCESS,
1306 &spr_read_generic, &spr_write_generic,
1307 0x00000000);
1308 /* XXX : not implemented */
1309 spr_register(env, SPR_IABR2, "IABR2",
1310 SPR_NOACCESS, SPR_NOACCESS,
1311 &spr_read_generic, &spr_write_generic,
1312 0x00000000);
1313 /* XXX : not implemented */
1314 spr_register(env, SPR_IBCR, "IBCR",
1315 SPR_NOACCESS, SPR_NOACCESS,
1316 &spr_read_generic, &spr_write_generic,
1317 0x00000000);
1318 /* XXX : not implemented */
1319 spr_register(env, SPR_DBCR, "DBCR",
1320 SPR_NOACCESS, SPR_NOACCESS,
1321 &spr_read_generic, &spr_write_generic,
1322 0x00000000);
1323 }
1324
1325 /* SPR specific to PowerPC 602 implementation */
1326 static void gen_spr_602 (CPUPPCState *env)
1327 {
1328 /* ESA registers */
1329 /* XXX : not implemented */
1330 spr_register(env, SPR_SER, "SER",
1331 SPR_NOACCESS, SPR_NOACCESS,
1332 &spr_read_generic, &spr_write_generic,
1333 0x00000000);
1334 /* XXX : not implemented */
1335 spr_register(env, SPR_SEBR, "SEBR",
1336 SPR_NOACCESS, SPR_NOACCESS,
1337 &spr_read_generic, &spr_write_generic,
1338 0x00000000);
1339 /* XXX : not implemented */
1340 spr_register(env, SPR_ESASRR, "ESASRR",
1341 SPR_NOACCESS, SPR_NOACCESS,
1342 &spr_read_generic, &spr_write_generic,
1343 0x00000000);
1344 /* Floating point status */
1345 /* XXX : not implemented */
1346 spr_register(env, SPR_SP, "SP",
1347 SPR_NOACCESS, SPR_NOACCESS,
1348 &spr_read_generic, &spr_write_generic,
1349 0x00000000);
1350 /* XXX : not implemented */
1351 spr_register(env, SPR_LT, "LT",
1352 SPR_NOACCESS, SPR_NOACCESS,
1353 &spr_read_generic, &spr_write_generic,
1354 0x00000000);
1355 /* Watchdog timer */
1356 /* XXX : not implemented */
1357 spr_register(env, SPR_TCR, "TCR",
1358 SPR_NOACCESS, SPR_NOACCESS,
1359 &spr_read_generic, &spr_write_generic,
1360 0x00000000);
1361 /* Interrupt base */
1362 spr_register(env, SPR_IBR, "IBR",
1363 SPR_NOACCESS, SPR_NOACCESS,
1364 &spr_read_generic, &spr_write_generic,
1365 0x00000000);
1366 /* XXX : not implemented */
1367 spr_register(env, SPR_IABR, "IABR",
1368 SPR_NOACCESS, SPR_NOACCESS,
1369 &spr_read_generic, &spr_write_generic,
1370 0x00000000);
1371 }
1372
1373 /* SPR specific to PowerPC 601 implementation */
1374 static void gen_spr_601 (CPUPPCState *env)
1375 {
1376 /* Multiplication/division register */
1377 /* MQ */
1378 spr_register(env, SPR_MQ, "MQ",
1379 &spr_read_generic, &spr_write_generic,
1380 &spr_read_generic, &spr_write_generic,
1381 0x00000000);
1382 /* RTC registers */
1383 spr_register(env, SPR_601_RTCU, "RTCU",
1384 SPR_NOACCESS, SPR_NOACCESS,
1385 SPR_NOACCESS, &spr_write_601_rtcu,
1386 0x00000000);
1387 spr_register(env, SPR_601_VRTCU, "RTCU",
1388 &spr_read_601_rtcu, SPR_NOACCESS,
1389 &spr_read_601_rtcu, SPR_NOACCESS,
1390 0x00000000);
1391 spr_register(env, SPR_601_RTCL, "RTCL",
1392 SPR_NOACCESS, SPR_NOACCESS,
1393 SPR_NOACCESS, &spr_write_601_rtcl,
1394 0x00000000);
1395 spr_register(env, SPR_601_VRTCL, "RTCL",
1396 &spr_read_601_rtcl, SPR_NOACCESS,
1397 &spr_read_601_rtcl, SPR_NOACCESS,
1398 0x00000000);
1399 /* Timer */
1400 #if 0 /* ? */
1401 spr_register(env, SPR_601_UDECR, "UDECR",
1402 &spr_read_decr, SPR_NOACCESS,
1403 &spr_read_decr, SPR_NOACCESS,
1404 0x00000000);
1405 #endif
1406 /* External access control */
1407 /* XXX : not implemented */
1408 spr_register(env, SPR_EAR, "EAR",
1409 SPR_NOACCESS, SPR_NOACCESS,
1410 &spr_read_generic, &spr_write_generic,
1411 0x00000000);
1412 /* Memory management */
1413 #if !defined(CONFIG_USER_ONLY)
1414 spr_register(env, SPR_IBAT0U, "IBAT0U",
1415 SPR_NOACCESS, SPR_NOACCESS,
1416 &spr_read_601_ubat, &spr_write_601_ubatu,
1417 0x00000000);
1418 spr_register(env, SPR_IBAT0L, "IBAT0L",
1419 SPR_NOACCESS, SPR_NOACCESS,
1420 &spr_read_601_ubat, &spr_write_601_ubatl,
1421 0x00000000);
1422 spr_register(env, SPR_IBAT1U, "IBAT1U",
1423 SPR_NOACCESS, SPR_NOACCESS,
1424 &spr_read_601_ubat, &spr_write_601_ubatu,
1425 0x00000000);
1426 spr_register(env, SPR_IBAT1L, "IBAT1L",
1427 SPR_NOACCESS, SPR_NOACCESS,
1428 &spr_read_601_ubat, &spr_write_601_ubatl,
1429 0x00000000);
1430 spr_register(env, SPR_IBAT2U, "IBAT2U",
1431 SPR_NOACCESS, SPR_NOACCESS,
1432 &spr_read_601_ubat, &spr_write_601_ubatu,
1433 0x00000000);
1434 spr_register(env, SPR_IBAT2L, "IBAT2L",
1435 SPR_NOACCESS, SPR_NOACCESS,
1436 &spr_read_601_ubat, &spr_write_601_ubatl,
1437 0x00000000);
1438 spr_register(env, SPR_IBAT3U, "IBAT3U",
1439 SPR_NOACCESS, SPR_NOACCESS,
1440 &spr_read_601_ubat, &spr_write_601_ubatu,
1441 0x00000000);
1442 spr_register(env, SPR_IBAT3L, "IBAT3L",
1443 SPR_NOACCESS, SPR_NOACCESS,
1444 &spr_read_601_ubat, &spr_write_601_ubatl,
1445 0x00000000);
1446 env->nb_BATs = 4;
1447 #endif
1448 }
1449
1450 static void gen_spr_74xx (CPUPPCState *env)
1451 {
1452 /* Processor identification */
1453 spr_register(env, SPR_PIR, "PIR",
1454 SPR_NOACCESS, SPR_NOACCESS,
1455 &spr_read_generic, &spr_write_pir,
1456 0x00000000);
1457 /* XXX : not implemented */
1458 spr_register(env, SPR_74XX_MMCR2, "MMCR2",
1459 SPR_NOACCESS, SPR_NOACCESS,
1460 &spr_read_generic, &spr_write_generic,
1461 0x00000000);
1462 /* XXX : not implemented */
1463 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
1464 &spr_read_ureg, SPR_NOACCESS,
1465 &spr_read_ureg, SPR_NOACCESS,
1466 0x00000000);
1467 /* XXX: not implemented */
1468 spr_register(env, SPR_BAMR, "BAMR",
1469 SPR_NOACCESS, SPR_NOACCESS,
1470 &spr_read_generic, &spr_write_generic,
1471 0x00000000);
1472 /* XXX : not implemented */
1473 spr_register(env, SPR_MSSCR0, "MSSCR0",
1474 SPR_NOACCESS, SPR_NOACCESS,
1475 &spr_read_generic, &spr_write_generic,
1476 0x00000000);
1477 /* Hardware implementation registers */
1478 /* XXX : not implemented */
1479 spr_register(env, SPR_HID0, "HID0",
1480 SPR_NOACCESS, SPR_NOACCESS,
1481 &spr_read_generic, &spr_write_generic,
1482 0x00000000);
1483 /* XXX : not implemented */
1484 spr_register(env, SPR_HID1, "HID1",
1485 SPR_NOACCESS, SPR_NOACCESS,
1486 &spr_read_generic, &spr_write_generic,
1487 0x00000000);
1488 /* Altivec */
1489 spr_register(env, SPR_VRSAVE, "VRSAVE",
1490 &spr_read_generic, &spr_write_generic,
1491 &spr_read_generic, &spr_write_generic,
1492 0x00000000);
1493 /* XXX : not implemented */
1494 spr_register(env, SPR_L2CR, "L2CR",
1495 SPR_NOACCESS, SPR_NOACCESS,
1496 &spr_read_generic, spr_access_nop,
1497 0x00000000);
1498 /* Not strictly an SPR */
1499 vscr_init(env, 0x00010000);
1500 }
1501
1502 static void gen_l3_ctrl (CPUPPCState *env)
1503 {
1504 /* L3CR */
1505 /* XXX : not implemented */
1506 spr_register(env, SPR_L3CR, "L3CR",
1507 SPR_NOACCESS, SPR_NOACCESS,
1508 &spr_read_generic, &spr_write_generic,
1509 0x00000000);
1510 /* L3ITCR0 */
1511 /* XXX : not implemented */
1512 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1513 SPR_NOACCESS, SPR_NOACCESS,
1514 &spr_read_generic, &spr_write_generic,
1515 0x00000000);
1516 /* L3PM */
1517 /* XXX : not implemented */
1518 spr_register(env, SPR_L3PM, "L3PM",
1519 SPR_NOACCESS, SPR_NOACCESS,
1520 &spr_read_generic, &spr_write_generic,
1521 0x00000000);
1522 }
1523
1524 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1525 {
1526 #if !defined(CONFIG_USER_ONLY)
1527 env->nb_tlb = nb_tlbs;
1528 env->nb_ways = nb_ways;
1529 env->id_tlbs = 1;
1530 env->tlb_type = TLB_6XX;
1531 /* XXX : not implemented */
1532 spr_register(env, SPR_PTEHI, "PTEHI",
1533 SPR_NOACCESS, SPR_NOACCESS,
1534 &spr_read_generic, &spr_write_generic,
1535 0x00000000);
1536 /* XXX : not implemented */
1537 spr_register(env, SPR_PTELO, "PTELO",
1538 SPR_NOACCESS, SPR_NOACCESS,
1539 &spr_read_generic, &spr_write_generic,
1540 0x00000000);
1541 /* XXX : not implemented */
1542 spr_register(env, SPR_TLBMISS, "TLBMISS",
1543 SPR_NOACCESS, SPR_NOACCESS,
1544 &spr_read_generic, &spr_write_generic,
1545 0x00000000);
1546 #endif
1547 }
1548
1549 #if !defined(CONFIG_USER_ONLY)
1550 static void spr_write_e500_l1csr0 (DisasContext *ctx, int sprn, int gprn)
1551 {
1552 TCGv t0 = tcg_temp_new();
1553
1554 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
1555 gen_store_spr(sprn, t0);
1556 tcg_temp_free(t0);
1557 }
1558
1559 static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
1560 {
1561 TCGv t0 = tcg_temp_new();
1562
1563 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
1564 gen_store_spr(sprn, t0);
1565 tcg_temp_free(t0);
1566 }
1567
1568 static void spr_write_booke206_mmucsr0 (DisasContext *ctx, int sprn, int gprn)
1569 {
1570 gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
1571 }
1572
1573 static void spr_write_booke_pid (DisasContext *ctx, int sprn, int gprn)
1574 {
1575 TCGv_i32 t0 = tcg_const_i32(sprn);
1576 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1577 tcg_temp_free_i32(t0);
1578 }
1579 #endif
1580
1581 static void gen_spr_usprgh (CPUPPCState *env)
1582 {
1583 spr_register(env, SPR_USPRG4, "USPRG4",
1584 &spr_read_ureg, SPR_NOACCESS,
1585 &spr_read_ureg, SPR_NOACCESS,
1586 0x00000000);
1587 spr_register(env, SPR_USPRG5, "USPRG5",
1588 &spr_read_ureg, SPR_NOACCESS,
1589 &spr_read_ureg, SPR_NOACCESS,
1590 0x00000000);
1591 spr_register(env, SPR_USPRG6, "USPRG6",
1592 &spr_read_ureg, SPR_NOACCESS,
1593 &spr_read_ureg, SPR_NOACCESS,
1594 0x00000000);
1595 spr_register(env, SPR_USPRG7, "USPRG7",
1596 &spr_read_ureg, SPR_NOACCESS,
1597 &spr_read_ureg, SPR_NOACCESS,
1598 0x00000000);
1599 }
1600
1601 /* PowerPC BookE SPR */
1602 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1603 {
1604 const char *ivor_names[64] = {
1605 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1606 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1607 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1608 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1609 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1610 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1611 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1612 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1613 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1614 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1615 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1616 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1617 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1618 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1619 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1620 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1621 };
1622 #define SPR_BOOKE_IVORxx (-1)
1623 int ivor_sprn[64] = {
1624 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1625 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1626 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1627 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1628 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1629 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1630 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1631 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1632 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1633 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1634 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1635 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1636 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1637 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1638 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1639 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1640 };
1641 int i;
1642
1643 /* Interrupt processing */
1644 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1645 SPR_NOACCESS, SPR_NOACCESS,
1646 &spr_read_generic, &spr_write_generic,
1647 0x00000000);
1648 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1649 SPR_NOACCESS, SPR_NOACCESS,
1650 &spr_read_generic, &spr_write_generic,
1651 0x00000000);
1652 /* Debug */
1653 /* XXX : not implemented */
1654 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1655 SPR_NOACCESS, SPR_NOACCESS,
1656 &spr_read_generic, &spr_write_generic,
1657 0x00000000);
1658 /* XXX : not implemented */
1659 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1660 SPR_NOACCESS, SPR_NOACCESS,
1661 &spr_read_generic, &spr_write_generic,
1662 0x00000000);
1663 /* XXX : not implemented */
1664 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1665 SPR_NOACCESS, SPR_NOACCESS,
1666 &spr_read_generic, &spr_write_generic,
1667 0x00000000);
1668 /* XXX : not implemented */
1669 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1670 SPR_NOACCESS, SPR_NOACCESS,
1671 &spr_read_generic, &spr_write_generic,
1672 0x00000000);
1673 /* XXX : not implemented */
1674 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1675 SPR_NOACCESS, SPR_NOACCESS,
1676 &spr_read_generic, &spr_write_40x_dbcr0,
1677 0x00000000);
1678 /* XXX : not implemented */
1679 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1680 SPR_NOACCESS, SPR_NOACCESS,
1681 &spr_read_generic, &spr_write_generic,
1682 0x00000000);
1683 /* XXX : not implemented */
1684 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1685 SPR_NOACCESS, SPR_NOACCESS,
1686 &spr_read_generic, &spr_write_generic,
1687 0x00000000);
1688 /* XXX : not implemented */
1689 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1690 SPR_NOACCESS, SPR_NOACCESS,
1691 &spr_read_generic, &spr_write_clear,
1692 0x00000000);
1693 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1694 SPR_NOACCESS, SPR_NOACCESS,
1695 &spr_read_generic, &spr_write_generic,
1696 0x00000000);
1697 spr_register(env, SPR_BOOKE_ESR, "ESR",
1698 SPR_NOACCESS, SPR_NOACCESS,
1699 &spr_read_generic, &spr_write_generic,
1700 0x00000000);
1701 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1702 SPR_NOACCESS, SPR_NOACCESS,
1703 &spr_read_generic, &spr_write_excp_prefix,
1704 0x00000000);
1705 /* Exception vectors */
1706 for (i = 0; i < 64; i++) {
1707 if (ivor_mask & (1ULL << i)) {
1708 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1709 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1710 exit(1);
1711 }
1712 spr_register(env, ivor_sprn[i], ivor_names[i],
1713 SPR_NOACCESS, SPR_NOACCESS,
1714 &spr_read_generic, &spr_write_excp_vector,
1715 0x00000000);
1716 }
1717 }
1718 spr_register(env, SPR_BOOKE_PID, "PID",
1719 SPR_NOACCESS, SPR_NOACCESS,
1720 &spr_read_generic, &spr_write_booke_pid,
1721 0x00000000);
1722 spr_register(env, SPR_BOOKE_TCR, "TCR",
1723 SPR_NOACCESS, SPR_NOACCESS,
1724 &spr_read_generic, &spr_write_booke_tcr,
1725 0x00000000);
1726 spr_register(env, SPR_BOOKE_TSR, "TSR",
1727 SPR_NOACCESS, SPR_NOACCESS,
1728 &spr_read_generic, &spr_write_booke_tsr,
1729 0x00000000);
1730 /* Timer */
1731 spr_register(env, SPR_DECR, "DECR",
1732 SPR_NOACCESS, SPR_NOACCESS,
1733 &spr_read_decr, &spr_write_decr,
1734 0x00000000);
1735 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1736 SPR_NOACCESS, SPR_NOACCESS,
1737 SPR_NOACCESS, &spr_write_generic,
1738 0x00000000);
1739 /* SPRGs */
1740 spr_register(env, SPR_USPRG0, "USPRG0",
1741 &spr_read_generic, &spr_write_generic,
1742 &spr_read_generic, &spr_write_generic,
1743 0x00000000);
1744 spr_register(env, SPR_SPRG4, "SPRG4",
1745 SPR_NOACCESS, SPR_NOACCESS,
1746 &spr_read_generic, &spr_write_generic,
1747 0x00000000);
1748 spr_register(env, SPR_SPRG5, "SPRG5",
1749 SPR_NOACCESS, SPR_NOACCESS,
1750 &spr_read_generic, &spr_write_generic,
1751 0x00000000);
1752 spr_register(env, SPR_SPRG6, "SPRG6",
1753 SPR_NOACCESS, SPR_NOACCESS,
1754 &spr_read_generic, &spr_write_generic,
1755 0x00000000);
1756 spr_register(env, SPR_SPRG7, "SPRG7",
1757 SPR_NOACCESS, SPR_NOACCESS,
1758 &spr_read_generic, &spr_write_generic,
1759 0x00000000);
1760 }
1761
1762 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1763 uint32_t maxsize, uint32_t flags,
1764 uint32_t nentries)
1765 {
1766 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1767 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1768 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1769 flags | nentries;
1770 }
1771
1772 /* BookE 2.06 storage control registers */
1773 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1774 uint32_t *tlbncfg)
1775 {
1776 #if !defined(CONFIG_USER_ONLY)
1777 const char *mas_names[8] = {
1778 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1779 };
1780 int mas_sprn[8] = {
1781 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1782 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1783 };
1784 int i;
1785
1786 /* TLB assist registers */
1787 /* XXX : not implemented */
1788 for (i = 0; i < 8; i++) {
1789 void (*uea_write)(DisasContext *ctx, int sprn, int gprn) = &spr_write_generic32;
1790 if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1791 uea_write = &spr_write_generic;
1792 }
1793 if (mas_mask & (1 << i)) {
1794 spr_register(env, mas_sprn[i], mas_names[i],
1795 SPR_NOACCESS, SPR_NOACCESS,
1796 &spr_read_generic, uea_write,
1797 0x00000000);
1798 }
1799 }
1800 if (env->nb_pids > 1) {
1801 /* XXX : not implemented */
1802 spr_register(env, SPR_BOOKE_PID1, "PID1",
1803 SPR_NOACCESS, SPR_NOACCESS,
1804 &spr_read_generic, &spr_write_booke_pid,
1805 0x00000000);
1806 }
1807 if (env->nb_pids > 2) {
1808 /* XXX : not implemented */
1809 spr_register(env, SPR_BOOKE_PID2, "PID2",
1810 SPR_NOACCESS, SPR_NOACCESS,
1811 &spr_read_generic, &spr_write_booke_pid,
1812 0x00000000);
1813 }
1814 /* XXX : not implemented */
1815 spr_register(env, SPR_MMUCFG, "MMUCFG",
1816 SPR_NOACCESS, SPR_NOACCESS,
1817 &spr_read_generic, SPR_NOACCESS,
1818 0x00000000); /* TOFIX */
1819 switch (env->nb_ways) {
1820 case 4:
1821 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1822 SPR_NOACCESS, SPR_NOACCESS,
1823 &spr_read_generic, SPR_NOACCESS,
1824 tlbncfg[3]);
1825 /* Fallthru */
1826 case 3:
1827 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1828 SPR_NOACCESS, SPR_NOACCESS,
1829 &spr_read_generic, SPR_NOACCESS,
1830 tlbncfg[2]);
1831 /* Fallthru */
1832 case 2:
1833 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1834 SPR_NOACCESS, SPR_NOACCESS,
1835 &spr_read_generic, SPR_NOACCESS,
1836 tlbncfg[1]);
1837 /* Fallthru */
1838 case 1:
1839 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1840 SPR_NOACCESS, SPR_NOACCESS,
1841 &spr_read_generic, SPR_NOACCESS,
1842 tlbncfg[0]);
1843 /* Fallthru */
1844 case 0:
1845 default:
1846 break;
1847 }
1848 #endif
1849
1850 gen_spr_usprgh(env);
1851 }
1852
1853 /* SPR specific to PowerPC 440 implementation */
1854 static void gen_spr_440 (CPUPPCState *env)
1855 {
1856 /* Cache control */
1857 /* XXX : not implemented */
1858 spr_register(env, SPR_440_DNV0, "DNV0",
1859 SPR_NOACCESS, SPR_NOACCESS,
1860 &spr_read_generic, &spr_write_generic,
1861 0x00000000);
1862 /* XXX : not implemented */
1863 spr_register(env, SPR_440_DNV1, "DNV1",
1864 SPR_NOACCESS, SPR_NOACCESS,
1865 &spr_read_generic, &spr_write_generic,
1866 0x00000000);
1867 /* XXX : not implemented */
1868 spr_register(env, SPR_440_DNV2, "DNV2",
1869 SPR_NOACCESS, SPR_NOACCESS,
1870 &spr_read_generic, &spr_write_generic,
1871 0x00000000);
1872 /* XXX : not implemented */
1873 spr_register(env, SPR_440_DNV3, "DNV3",
1874 SPR_NOACCESS, SPR_NOACCESS,
1875 &spr_read_generic, &spr_write_generic,
1876 0x00000000);
1877 /* XXX : not implemented */
1878 spr_register(env, SPR_440_DTV0, "DTV0",
1879 SPR_NOACCESS, SPR_NOACCESS,
1880 &spr_read_generic, &spr_write_generic,
1881 0x00000000);
1882 /* XXX : not implemented */
1883 spr_register(env, SPR_440_DTV1, "DTV1",
1884 SPR_NOACCESS, SPR_NOACCESS,
1885 &spr_read_generic, &spr_write_generic,
1886 0x00000000);
1887 /* XXX : not implemented */
1888 spr_register(env, SPR_440_DTV2, "DTV2",
1889 SPR_NOACCESS, SPR_NOACCESS,
1890 &spr_read_generic, &spr_write_generic,
1891 0x00000000);
1892 /* XXX : not implemented */
1893 spr_register(env, SPR_440_DTV3, "DTV3",
1894 SPR_NOACCESS, SPR_NOACCESS,
1895 &spr_read_generic, &spr_write_generic,
1896 0x00000000);
1897 /* XXX : not implemented */
1898 spr_register(env, SPR_440_DVLIM, "DVLIM",
1899 SPR_NOACCESS, SPR_NOACCESS,
1900 &spr_read_generic, &spr_write_generic,
1901 0x00000000);
1902 /* XXX : not implemented */
1903 spr_register(env, SPR_440_INV0, "INV0",
1904 SPR_NOACCESS, SPR_NOACCESS,
1905 &spr_read_generic, &spr_write_generic,
1906 0x00000000);
1907 /* XXX : not implemented */
1908 spr_register(env, SPR_440_INV1, "INV1",
1909 SPR_NOACCESS, SPR_NOACCESS,
1910 &spr_read_generic, &spr_write_generic,
1911 0x00000000);
1912 /* XXX : not implemented */
1913 spr_register(env, SPR_440_INV2, "INV2",
1914 SPR_NOACCESS, SPR_NOACCESS,
1915 &spr_read_generic, &spr_write_generic,
1916 0x00000000);
1917 /* XXX : not implemented */
1918 spr_register(env, SPR_440_INV3, "INV3",
1919 SPR_NOACCESS, SPR_NOACCESS,
1920 &spr_read_generic, &spr_write_generic,
1921 0x00000000);
1922 /* XXX : not implemented */
1923 spr_register(env, SPR_440_ITV0, "ITV0",
1924 SPR_NOACCESS, SPR_NOACCESS,
1925 &spr_read_generic, &spr_write_generic,
1926 0x00000000);
1927 /* XXX : not implemented */
1928 spr_register(env, SPR_440_ITV1, "ITV1",
1929 SPR_NOACCESS, SPR_NOACCESS,
1930 &spr_read_generic, &spr_write_generic,
1931 0x00000000);
1932 /* XXX : not implemented */
1933 spr_register(env, SPR_440_ITV2, "ITV2",
1934 SPR_NOACCESS, SPR_NOACCESS,
1935 &spr_read_generic, &spr_write_generic,
1936 0x00000000);
1937 /* XXX : not implemented */
1938 spr_register(env, SPR_440_ITV3, "ITV3",
1939 SPR_NOACCESS, SPR_NOACCESS,
1940 &spr_read_generic, &spr_write_generic,
1941 0x00000000);
1942 /* XXX : not implemented */
1943 spr_register(env, SPR_440_IVLIM, "IVLIM",
1944 SPR_NOACCESS, SPR_NOACCESS,
1945 &spr_read_generic, &spr_write_generic,
1946 0x00000000);
1947 /* Cache debug */
1948 /* XXX : not implemented */
1949 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1950 SPR_NOACCESS, SPR_NOACCESS,
1951 &spr_read_generic, SPR_NOACCESS,
1952 0x00000000);
1953 /* XXX : not implemented */
1954 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1955 SPR_NOACCESS, SPR_NOACCESS,
1956 &spr_read_generic, SPR_NOACCESS,
1957 0x00000000);
1958 /* XXX : not implemented */
1959 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1960 SPR_NOACCESS, SPR_NOACCESS,
1961 &spr_read_generic, SPR_NOACCESS,
1962 0x00000000);
1963 /* XXX : not implemented */
1964 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1965 SPR_NOACCESS, SPR_NOACCESS,
1966 &spr_read_generic, SPR_NOACCESS,
1967 0x00000000);
1968 /* XXX : not implemented */
1969 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1970 SPR_NOACCESS, SPR_NOACCESS,
1971 &spr_read_generic, SPR_NOACCESS,
1972 0x00000000);
1973 /* XXX : not implemented */
1974 spr_register(env, SPR_440_DBDR, "DBDR",
1975 SPR_NOACCESS, SPR_NOACCESS,
1976 &spr_read_generic, &spr_write_generic,
1977 0x00000000);
1978 /* Processor control */
1979 spr_register(env, SPR_4xx_CCR0, "CCR0",
1980 SPR_NOACCESS, SPR_NOACCESS,
1981 &spr_read_generic, &spr_write_generic,
1982 0x00000000);
1983 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1984 SPR_NOACCESS, SPR_NOACCESS,
1985 &spr_read_generic, SPR_NOACCESS,
1986 0x00000000);
1987 /* Storage control */
1988 spr_register(env, SPR_440_MMUCR, "MMUCR",
1989 SPR_NOACCESS, SPR_NOACCESS,
1990 &spr_read_generic, &spr_write_generic,
1991 0x00000000);
1992 }
1993
1994 /* SPR shared between PowerPC 40x implementations */
1995 static void gen_spr_40x (CPUPPCState *env)
1996 {
1997 /* Cache */
1998 /* not emulated, as QEMU do not emulate caches */
1999 spr_register(env, SPR_40x_DCCR, "DCCR",
2000 SPR_NOACCESS, SPR_NOACCESS,
2001 &spr_read_generic, &spr_write_generic,
2002 0x00000000);
2003 /* not emulated, as QEMU do not emulate caches */
2004 spr_register(env, SPR_40x_ICCR, "ICCR",
2005 SPR_NOACCESS, SPR_NOACCESS,
2006 &spr_read_generic, &spr_write_generic,
2007 0x00000000);
2008 /* not emulated, as QEMU do not emulate caches */
2009 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
2010 SPR_NOACCESS, SPR_NOACCESS,
2011 &spr_read_generic, SPR_NOACCESS,
2012 0x00000000);
2013 /* Exception */
2014 spr_register(env, SPR_40x_DEAR, "DEAR",
2015 SPR_NOACCESS, SPR_NOACCESS,
2016 &spr_read_generic, &spr_write_generic,
2017 0x00000000);
2018 spr_register(env, SPR_40x_ESR, "ESR",
2019 SPR_NOACCESS, SPR_NOACCESS,
2020 &spr_read_generic, &spr_write_generic,
2021 0x00000000);
2022 spr_register(env, SPR_40x_EVPR, "EVPR",
2023 SPR_NOACCESS, SPR_NOACCESS,
2024 &spr_read_generic, &spr_write_excp_prefix,
2025 0x00000000);
2026 spr_register(env, SPR_40x_SRR2, "SRR2",
2027 &spr_read_generic, &spr_write_generic,
2028 &spr_read_generic, &spr_write_generic,
2029 0x00000000);
2030 spr_register(env, SPR_40x_SRR3, "SRR3",
2031 &spr_read_generic, &spr_write_generic,
2032 &spr_read_generic, &spr_write_generic,
2033 0x00000000);
2034 /* Timers */
2035 spr_register(env, SPR_40x_PIT, "PIT",
2036 SPR_NOACCESS, SPR_NOACCESS,
2037 &spr_read_40x_pit, &spr_write_40x_pit,
2038 0x00000000);
2039 spr_register(env, SPR_40x_TCR, "TCR",
2040 SPR_NOACCESS, SPR_NOACCESS,
2041 &spr_read_generic, &spr_write_booke_tcr,
2042 0x00000000);
2043 spr_register(env, SPR_40x_TSR, "TSR",
2044 SPR_NOACCESS, SPR_NOACCESS,
2045 &spr_read_generic, &spr_write_booke_tsr,
2046 0x00000000);
2047 }
2048
2049 /* SPR specific to PowerPC 405 implementation */
2050 static void gen_spr_405 (CPUPPCState *env)
2051 {
2052 /* MMU */
2053 spr_register(env, SPR_40x_PID, "PID",
2054 SPR_NOACCESS, SPR_NOACCESS,
2055 &spr_read_generic, &spr_write_generic,
2056 0x00000000);
2057 spr_register(env, SPR_4xx_CCR0, "CCR0",
2058 SPR_NOACCESS, SPR_NOACCESS,
2059 &spr_read_generic, &spr_write_generic,
2060 0x00700000);
2061 /* Debug interface */
2062 /* XXX : not implemented */
2063 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2064 SPR_NOACCESS, SPR_NOACCESS,
2065 &spr_read_generic, &spr_write_40x_dbcr0,
2066 0x00000000);
2067 /* XXX : not implemented */
2068 spr_register(env, SPR_405_DBCR1, "DBCR1",
2069 SPR_NOACCESS, SPR_NOACCESS,
2070 &spr_read_generic, &spr_write_generic,
2071 0x00000000);
2072 /* XXX : not implemented */
2073 spr_register(env, SPR_40x_DBSR, "DBSR",
2074 SPR_NOACCESS, SPR_NOACCESS,
2075 &spr_read_generic, &spr_write_clear,
2076 /* Last reset was system reset */
2077 0x00000300);
2078 /* XXX : not implemented */
2079 spr_register(env, SPR_40x_DAC1, "DAC1",
2080 SPR_NOACCESS, SPR_NOACCESS,
2081 &spr_read_generic, &spr_write_generic,
2082 0x00000000);
2083 spr_register(env, SPR_40x_DAC2, "DAC2",
2084 SPR_NOACCESS, SPR_NOACCESS,
2085 &spr_read_generic, &spr_write_generic,
2086 0x00000000);
2087 /* XXX : not implemented */
2088 spr_register(env, SPR_405_DVC1, "DVC1",
2089 SPR_NOACCESS, SPR_NOACCESS,
2090 &spr_read_generic, &spr_write_generic,
2091 0x00000000);
2092 /* XXX : not implemented */
2093 spr_register(env, SPR_405_DVC2, "DVC2",
2094 SPR_NOACCESS, SPR_NOACCESS,
2095 &spr_read_generic, &spr_write_generic,
2096 0x00000000);
2097 /* XXX : not implemented */
2098 spr_register(env, SPR_40x_IAC1, "IAC1",
2099 SPR_NOACCESS, SPR_NOACCESS,
2100 &spr_read_generic, &spr_write_generic,
2101 0x00000000);
2102 spr_register(env, SPR_40x_IAC2, "IAC2",
2103 SPR_NOACCESS, SPR_NOACCESS,
2104 &spr_read_generic, &spr_write_generic,
2105 0x00000000);
2106 /* XXX : not implemented */
2107 spr_register(env, SPR_405_IAC3, "IAC3",
2108 SPR_NOACCESS, SPR_NOACCESS,
2109 &spr_read_generic, &spr_write_generic,
2110 0x00000000);
2111 /* XXX : not implemented */
2112 spr_register(env, SPR_405_IAC4, "IAC4",
2113 SPR_NOACCESS, SPR_NOACCESS,
2114 &spr_read_generic, &spr_write_generic,
2115 0x00000000);
2116 /* Storage control */
2117 /* XXX: TODO: not implemented */
2118 spr_register(env, SPR_405_SLER, "SLER",
2119 SPR_NOACCESS, SPR_NOACCESS,
2120 &spr_read_generic, &spr_write_40x_sler,
2121 0x00000000);
2122 spr_register(env, SPR_40x_ZPR, "ZPR",
2123 SPR_NOACCESS, SPR_NOACCESS,
2124 &spr_read_generic, &spr_write_generic,
2125 0x00000000);
2126 /* XXX : not implemented */
2127 spr_register(env, SPR_405_SU0R, "SU0R",
2128 SPR_NOACCESS, SPR_NOACCESS,
2129 &spr_read_generic, &spr_write_generic,
2130 0x00000000);
2131 /* SPRG */
2132 spr_register(env, SPR_USPRG0, "USPRG0",
2133 &spr_read_ureg, SPR_NOACCESS,
2134 &spr_read_ureg, SPR_NOACCESS,
2135 0x00000000);
2136 spr_register(env, SPR_SPRG4, "SPRG4",
2137 SPR_NOACCESS, SPR_NOACCESS,
2138 &spr_read_generic, &spr_write_generic,
2139 0x00000000);
2140 spr_register(env, SPR_SPRG5, "SPRG5",
2141 SPR_NOACCESS, SPR_NOACCESS,
2142 spr_read_generic, &spr_write_generic,
2143 0x00000000);
2144 spr_register(env, SPR_SPRG6, "SPRG6",
2145 SPR_NOACCESS, SPR_NOACCESS,
2146 spr_read_generic, &spr_write_generic,
2147 0x00000000);
2148 spr_register(env, SPR_SPRG7, "SPRG7",
2149 SPR_NOACCESS, SPR_NOACCESS,
2150 spr_read_generic, &spr_write_generic,
2151 0x00000000);
2152 gen_spr_usprgh(env);
2153 }
2154
2155 /* SPR shared between PowerPC 401 & 403 implementations */
2156 static void gen_spr_401_403 (CPUPPCState *env)
2157 {
2158 /* Time base */
2159 spr_register(env, SPR_403_VTBL, "TBL",
2160 &spr_read_tbl, SPR_NOACCESS,
2161 &spr_read_tbl, SPR_NOACCESS,
2162 0x00000000);
2163 spr_register(env, SPR_403_TBL, "TBL",
2164 SPR_NOACCESS, SPR_NOACCESS,
2165 SPR_NOACCESS, &spr_write_tbl,
2166 0x00000000);
2167 spr_register(env, SPR_403_VTBU, "TBU",
2168 &spr_read_tbu, SPR_NOACCESS,
2169 &spr_read_tbu, SPR_NOACCESS,
2170 0x00000000);
2171 spr_register(env, SPR_403_TBU, "TBU",
2172 SPR_NOACCESS, SPR_NOACCESS,
2173 SPR_NOACCESS, &spr_write_tbu,
2174 0x00000000);
2175 /* Debug */
2176 /* not emulated, as QEMU do not emulate caches */
2177 spr_register(env, SPR_403_CDBCR, "CDBCR",
2178 SPR_NOACCESS, SPR_NOACCESS,
2179 &spr_read_generic, &spr_write_generic,
2180 0x00000000);
2181 }
2182
2183 /* SPR specific to PowerPC 401 implementation */
2184 static void gen_spr_401 (CPUPPCState *env)
2185 {
2186 /* Debug interface */
2187 /* XXX : not implemented */
2188 spr_register(env, SPR_40x_DBCR0, "DBCR",
2189 SPR_NOACCESS, SPR_NOACCESS,
2190 &spr_read_generic, &spr_write_40x_dbcr0,
2191 0x00000000);
2192 /* XXX : not implemented */
2193 spr_register(env, SPR_40x_DBSR, "DBSR",
2194 SPR_NOACCESS, SPR_NOACCESS,
2195 &spr_read_generic, &spr_write_clear,
2196 /* Last reset was system reset */
2197 0x00000300);
2198 /* XXX : not implemented */
2199 spr_register(env, SPR_40x_DAC1, "DAC",
2200 SPR_NOACCESS, SPR_NOACCESS,
2201 &spr_read_generic, &spr_write_generic,
2202 0x00000000);
2203 /* XXX : not implemented */
2204 spr_register(env, SPR_40x_IAC1, "IAC",
2205 SPR_NOACCESS, SPR_NOACCESS,
2206 &spr_read_generic, &spr_write_generic,
2207 0x00000000);
2208 /* Storage control */
2209 /* XXX: TODO: not implemented */
2210 spr_register(env, SPR_405_SLER, "SLER",
2211 SPR_NOACCESS, SPR_NOACCESS,
2212 &spr_read_generic, &spr_write_40x_sler,
2213 0x00000000);
2214 /* not emulated, as QEMU never does speculative access */
2215 spr_register(env, SPR_40x_SGR, "SGR",
2216 SPR_NOACCESS, SPR_NOACCESS,
2217 &spr_read_generic, &spr_write_generic,
2218 0xFFFFFFFF);
2219 /* not emulated, as QEMU do not emulate caches */
2220 spr_register(env, SPR_40x_DCWR, "DCWR",
2221 SPR_NOACCESS, SPR_NOACCESS,
2222 &spr_read_generic, &spr_write_generic,
2223 0x00000000);
2224 }
2225
2226 static void gen_spr_401x2 (CPUPPCState *env)
2227 {
2228 gen_spr_401(env);
2229 spr_register(env, SPR_40x_PID, "PID",
2230 SPR_NOACCESS, SPR_NOACCESS,
2231 &spr_read_generic, &spr_write_generic,
2232 0x00000000);
2233 spr_register(env, SPR_40x_ZPR, "ZPR",
2234 SPR_NOACCESS, SPR_NOACCESS,
2235 &spr_read_generic, &spr_write_generic,
2236 0x00000000);
2237 }
2238
2239 /* SPR specific to PowerPC 403 implementation */
2240 static void gen_spr_403 (CPUPPCState *env)
2241 {
2242 /* Debug interface */
2243 /* XXX : not implemented */
2244 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2245 SPR_NOACCESS, SPR_NOACCESS,
2246 &spr_read_generic, &spr_write_40x_dbcr0,
2247 0x00000000);
2248 /* XXX : not implemented */
2249 spr_register(env, SPR_40x_DBSR, "DBSR",
2250 SPR_NOACCESS, SPR_NOACCESS,
2251 &spr_read_generic, &spr_write_clear,
2252 /* Last reset was system reset */
2253 0x00000300);
2254 /* XXX : not implemented */
2255 spr_register(env, SPR_40x_DAC1, "DAC1",
2256 SPR_NOACCESS, SPR_NOACCESS,
2257 &spr_read_generic, &spr_write_generic,
2258 0x00000000);
2259 /* XXX : not implemented */
2260 spr_register(env, SPR_40x_DAC2, "DAC2",
2261 SPR_NOACCESS, SPR_NOACCESS,
2262 &spr_read_generic, &spr_write_generic,
2263 0x00000000);
2264 /* XXX : not implemented */
2265 spr_register(env, SPR_40x_IAC1, "IAC1",
2266 SPR_NOACCESS, SPR_NOACCESS,
2267 &spr_read_generic, &spr_write_generic,
2268 0x00000000);
2269 /* XXX : not implemented */
2270 spr_register(env, SPR_40x_IAC2, "IAC2",
2271 SPR_NOACCESS, SPR_NOACCESS,
2272 &spr_read_generic, &spr_write_generic,
2273 0x00000000);
2274 }
2275
2276 static void gen_spr_403_real (CPUPPCState *env)
2277 {
2278 spr_register(env, SPR_403_PBL1, "PBL1",
2279 SPR_NOACCESS, SPR_NOACCESS,
2280 &spr_read_403_pbr, &spr_write_403_pbr,
2281 0x00000000);
2282 spr_register(env, SPR_403_PBU1, "PBU1",
2283 SPR_NOACCESS, SPR_NOACCESS,
2284 &spr_read_403_pbr, &spr_write_403_pbr,
2285 0x00000000);
2286 spr_register(env, SPR_403_PBL2, "PBL2",
2287 SPR_NOACCESS, SPR_NOACCESS,
2288 &spr_read_403_pbr, &spr_write_403_pbr,
2289 0x00000000);
2290 spr_register(env, SPR_403_PBU2, "PBU2",
2291 SPR_NOACCESS, SPR_NOACCESS,
2292 &spr_read_403_pbr, &spr_write_403_pbr,
2293 0x00000000);
2294 }
2295
2296 static void gen_spr_403_mmu (CPUPPCState *env)
2297 {
2298 /* MMU */
2299 spr_register(env, SPR_40x_PID, "PID",
2300 SPR_NOACCESS, SPR_NOACCESS,
2301 &spr_read_generic, &spr_write_generic,
2302 0x00000000);
2303 spr_register(env, SPR_40x_ZPR, "ZPR",
2304 SPR_NOACCESS, SPR_NOACCESS,
2305 &spr_read_generic, &spr_write_generic,
2306 0x00000000);
2307 }
2308
2309 /* SPR specific to PowerPC compression coprocessor extension */
2310 static void gen_spr_compress (CPUPPCState *env)
2311 {
2312 /* XXX : not implemented */
2313 spr_register(env, SPR_401_SKR, "SKR",
2314 SPR_NOACCESS, SPR_NOACCESS,
2315 &spr_read_generic, &spr_write_generic,
2316 0x00000000);
2317 }
2318
2319 static void gen_spr_5xx_8xx (CPUPPCState *env)
2320 {
2321 /* Exception processing */
2322 spr_register_kvm(env, SPR_DSISR, "DSISR",
2323 SPR_NOACCESS, SPR_NOACCESS,
2324 &spr_read_generic, &spr_write_generic,
2325 KVM_REG_PPC_DSISR, 0x00000000);
2326 spr_register_kvm(env, SPR_DAR, "DAR",
2327 SPR_NOACCESS, SPR_NOACCESS,
2328 &spr_read_generic, &spr_write_generic,
2329 KVM_REG_PPC_DAR, 0x00000000);
2330 /* Timer */
2331 spr_register(env, SPR_DECR, "DECR",
2332 SPR_NOACCESS, SPR_NOACCESS,
2333 &spr_read_decr, &spr_write_decr,
2334 0x00000000);
2335 /* XXX : not implemented */
2336 spr_register(env, SPR_MPC_EIE, "EIE",
2337 SPR_NOACCESS, SPR_NOACCESS,
2338 &spr_read_generic, &spr_write_generic,
2339 0x00000000);
2340 /* XXX : not implemented */
2341 spr_register(env, SPR_MPC_EID, "EID",
2342 SPR_NOACCESS, SPR_NOACCESS,
2343 &spr_read_generic, &spr_write_generic,
2344 0x00000000);
2345 /* XXX : not implemented */
2346 spr_register(env, SPR_MPC_NRI, "NRI",
2347 SPR_NOACCESS, SPR_NOACCESS,
2348 &spr_read_generic, &spr_write_generic,
2349 0x00000000);
2350 /* XXX : not implemented */
2351 spr_register(env, SPR_MPC_CMPA, "CMPA",
2352 SPR_NOACCESS, SPR_NOACCESS,
2353 &spr_read_generic, &spr_write_generic,
2354 0x00000000);
2355 /* XXX : not implemented */
2356 spr_register(env, SPR_MPC_CMPB, "CMPB",
2357 SPR_NOACCESS, SPR_NOACCESS,
2358 &spr_read_generic, &spr_write_generic,
2359 0x00000000);
2360 /* XXX : not implemented */
2361 spr_register(env, SPR_MPC_CMPC, "CMPC",
2362 SPR_NOACCESS, SPR_NOACCESS,
2363 &spr_read_generic, &spr_write_generic,
2364 0x00000000);
2365 /* XXX : not implemented */
2366 spr_register(env, SPR_MPC_CMPD, "CMPD",
2367 SPR_NOACCESS, SPR_NOACCESS,
2368 &spr_read_generic, &spr_write_generic,
2369 0x00000000);
2370 /* XXX : not implemented */
2371 spr_register(env, SPR_MPC_ECR, "ECR",
2372 SPR_NOACCESS, SPR_NOACCESS,
2373 &spr_read_generic, &spr_write_generic,
2374 0x00000000);
2375 /* XXX : not implemented */
2376 spr_register(env, SPR_MPC_DER, "DER",
2377 SPR_NOACCESS, SPR_NOACCESS,
2378 &spr_read_generic, &spr_write_generic,
2379 0x00000000);
2380 /* XXX : not implemented */
2381 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2382 SPR_NOACCESS, SPR_NOACCESS,
2383 &spr_read_generic, &spr_write_generic,
2384 0x00000000);
2385 /* XXX : not implemented */
2386 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2387 SPR_NOACCESS, SPR_NOACCESS,
2388 &spr_read_generic, &spr_write_generic,
2389 0x00000000);
2390 /* XXX : not implemented */
2391 spr_register(env, SPR_MPC_CMPE, "CMPE",
2392 SPR_NOACCESS, SPR_NOACCESS,
2393 &spr_read_generic, &spr_write_generic,
2394 0x00000000);
2395 /* XXX : not implemented */
2396 spr_register(env, SPR_MPC_CMPF, "CMPF",
2397 SPR_NOACCESS, SPR_NOACCESS,
2398 &spr_read_generic, &spr_write_generic,
2399 0x00000000);
2400 /* XXX : not implemented */
2401 spr_register(env, SPR_MPC_CMPG, "CMPG",
2402 SPR_NOACCESS, SPR_NOACCESS,
2403 &spr_read_generic, &spr_write_generic,
2404 0x00000000);
2405 /* XXX : not implemented */
2406 spr_register(env, SPR_MPC_CMPH, "CMPH",
2407 SPR_NOACCESS, SPR_NOACCESS,
2408 &spr_read_generic, &spr_write_generic,
2409 0x00000000);
2410 /* XXX : not implemented */
2411 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2412 SPR_NOACCESS, SPR_NOACCESS,
2413 &spr_read_generic, &spr_write_generic,
2414 0x00000000);
2415 /* XXX : not implemented */
2416 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2417 SPR_NOACCESS, SPR_NOACCESS,
2418 &spr_read_generic, &spr_write_generic,
2419 0x00000000);
2420 /* XXX : not implemented */
2421 spr_register(env, SPR_MPC_BAR, "BAR",
2422 SPR_NOACCESS, SPR_NOACCESS,
2423 &spr_read_generic, &spr_write_generic,
2424 0x00000000);
2425 /* XXX : not implemented */
2426 spr_register(env, SPR_MPC_DPDR, "DPDR",
2427 SPR_NOACCESS, SPR_NOACCESS,
2428 &spr_read_generic, &spr_write_generic,
2429 0x00000000);
2430 /* XXX : not implemented */
2431 spr_register(env, SPR_MPC_IMMR, "IMMR",
2432 SPR_NOACCESS, SPR_NOACCESS,
2433 &spr_read_generic, &spr_write_generic,
2434 0x00000000);
2435 }
2436
2437 static void gen_spr_5xx (CPUPPCState *env)
2438 {
2439 /* XXX : not implemented */
2440 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2441 SPR_NOACCESS, SPR_NOACCESS,
2442 &spr_read_generic, &spr_write_generic,
2443 0x00000000);
2444 /* XXX : not implemented */
2445 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2446 SPR_NOACCESS, SPR_NOACCESS,
2447 &spr_read_generic, &spr_write_generic,
2448 0x00000000);
2449 /* XXX : not implemented */
2450 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2451 SPR_NOACCESS, SPR_NOACCESS,
2452 &spr_read_generic, &spr_write_generic,
2453 0x00000000);
2454 /* XXX : not implemented */
2455 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2456 SPR_NOACCESS, SPR_NOACCESS,
2457 &spr_read_generic, &spr_write_generic,
2458 0x00000000);
2459 /* XXX : not implemented */
2460 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2461 SPR_NOACCESS, SPR_NOACCESS,
2462 &spr_read_generic, &spr_write_generic,
2463 0x00000000);
2464 /* XXX : not implemented */
2465 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2466 SPR_NOACCESS, SPR_NOACCESS,
2467 &spr_read_generic, &spr_write_generic,
2468 0x00000000);
2469 /* XXX : not implemented */
2470 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2471 SPR_NOACCESS, SPR_NOACCESS,
2472 &spr_read_generic, &spr_write_generic,
2473 0x00000000);
2474 /* XXX : not implemented */
2475 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2476 SPR_NOACCESS, SPR_NOACCESS,
2477 &spr_read_generic, &spr_write_generic,
2478 0x00000000);
2479 /* XXX : not implemented */
2480 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2481 SPR_NOACCESS, SPR_NOACCESS,
2482 &spr_read_generic, &spr_write_generic,
2483 0x00000000);
2484 /* XXX : not implemented */
2485 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2486 SPR_NOACCESS, SPR_NOACCESS,
2487 &spr_read_generic, &spr_write_generic,
2488 0x00000000);
2489 /* XXX : not implemented */
2490 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2491 SPR_NOACCESS, SPR_NOACCESS,
2492 &spr_read_generic, &spr_write_generic,
2493 0x00000000);
2494 /* XXX : not implemented */
2495 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2496 SPR_NOACCESS, SPR_NOACCESS,
2497 &spr_read_generic, &spr_write_generic,
2498 0x00000000);
2499 /* XXX : not implemented */
2500 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2501 SPR_NOACCESS, SPR_NOACCESS,
2502 &spr_read_generic, &spr_write_generic,
2503 0x00000000);
2504 /* XXX : not implemented */
2505 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2506 SPR_NOACCESS, SPR_NOACCESS,
2507 &spr_read_generic, &spr_write_generic,
2508 0x00000000);
2509 /* XXX : not implemented */
2510 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2511 SPR_NOACCESS, SPR_NOACCESS,
2512 &spr_read_generic, &spr_write_generic,
2513 0x00000000);
2514 /* XXX : not implemented */
2515 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2516 SPR_NOACCESS, SPR_NOACCESS,
2517 &spr_read_generic, &spr_write_generic,
2518 0x00000000);
2519 /* XXX : not implemented */
2520 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2521 SPR_NOACCESS, SPR_NOACCESS,
2522 &spr_read_generic, &spr_write_generic,
2523 0x00000000);
2524 /* XXX : not implemented */
2525 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2526 SPR_NOACCESS, SPR_NOACCESS,
2527 &spr_read_generic, &spr_write_generic,
2528 0x00000000);
2529 /* XXX : not implemented */
2530 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2531 SPR_NOACCESS, SPR_NOACCESS,
2532 &spr_read_generic, &spr_write_generic,
2533 0x00000000);
2534 /* XXX : not implemented */
2535 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2536 SPR_NOACCESS, SPR_NOACCESS,
2537 &spr_read_generic, &spr_write_generic,
2538 0x00000000);
2539 /* XXX : not implemented */
2540 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2541 SPR_NOACCESS, SPR_NOACCESS,
2542 &spr_read_generic, &spr_write_generic,
2543 0x00000000);
2544 }
2545
2546 static void gen_spr_8xx (CPUPPCState *env)
2547 {
2548 /* XXX : not implemented */
2549 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2550 SPR_NOACCESS, SPR_NOACCESS,
2551 &spr_read_generic, &spr_write_generic,
2552 0x00000000);
2553 /* XXX : not implemented */
2554 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2555 SPR_NOACCESS, SPR_NOACCESS,
2556 &spr_read_generic, &spr_write_generic,
2557 0x00000000);
2558 /* XXX : not implemented */
2559 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2560 SPR_NOACCESS, SPR_NOACCESS,
2561 &spr_read_generic, &spr_write_generic,
2562 0x00000000);
2563 /* XXX : not implemented */
2564 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2565 SPR_NOACCESS, SPR_NOACCESS,
2566 &spr_read_generic, &spr_write_generic,
2567 0x00000000);
2568 /* XXX : not implemented */
2569 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2570 SPR_NOACCESS, SPR_NOACCESS,
2571 &spr_read_generic, &spr_write_generic,
2572 0x00000000);
2573 /* XXX : not implemented */
2574 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2575 SPR_NOACCESS, SPR_NOACCESS,
2576 &spr_read_generic, &spr_write_generic,
2577 0x00000000);
2578 /* XXX : not implemented */
2579 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2580 SPR_NOACCESS, SPR_NOACCESS,
2581 &spr_read_generic, &spr_write_generic,
2582 0x00000000);
2583 /* XXX : not implemented */
2584 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2585 SPR_NOACCESS, SPR_NOACCESS,
2586 &spr_read_generic, &spr_write_generic,
2587 0x00000000);
2588 /* XXX : not implemented */
2589 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2590 SPR_NOACCESS, SPR_NOACCESS,
2591 &spr_read_generic, &spr_write_generic,
2592 0x00000000);
2593 /* XXX : not implemented */
2594 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2595 SPR_NOACCESS, SPR_NOACCESS,
2596 &spr_read_generic, &spr_write_generic,
2597 0x00000000);
2598 /* XXX : not implemented */
2599 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2600 SPR_NOACCESS, SPR_NOACCESS,
2601 &spr_read_generic, &spr_write_generic,
2602 0x00000000);
2603 /* XXX : not implemented */
2604 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2605 SPR_NOACCESS, SPR_NOACCESS,
2606 &spr_read_generic, &spr_write_generic,
2607 0x00000000);
2608 /* XXX : not implemented */
2609 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2610 SPR_NOACCESS, SPR_NOACCESS,
2611 &spr_read_generic, &spr_write_generic,
2612 0x00000000);
2613 /* XXX : not implemented */
2614 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2615 SPR_NOACCESS, SPR_NOACCESS,
2616 &spr_read_generic, &spr_write_generic,
2617 0x00000000);
2618 /* XXX : not implemented */
2619 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2620 SPR_NOACCESS, SPR_NOACCESS,
2621 &spr_read_generic, &spr_write_generic,
2622 0x00000000);
2623 /* XXX : not implemented */
2624 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2625 SPR_NOACCESS, SPR_NOACCESS,
2626 &spr_read_generic, &spr_write_generic,
2627 0x00000000);
2628 /* XXX : not implemented */
2629 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2630 SPR_NOACCESS, SPR_NOACCESS,
2631 &spr_read_generic, &spr_write_generic,
2632 0x00000000);
2633 /* XXX : not implemented */
2634 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2635 SPR_NOACCESS, SPR_NOACCESS,
2636 &spr_read_generic, &spr_write_generic,
2637 0x00000000);
2638 /* XXX : not implemented */
2639 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2640 SPR_NOACCESS, SPR_NOACCESS,
2641 &spr_read_generic, &spr_write_generic,
2642 0x00000000);
2643 /* XXX : not implemented */
2644 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2645 SPR_NOACCESS, SPR_NOACCESS,
2646 &spr_read_generic, &spr_write_generic,
2647 0x00000000);
2648 /* XXX : not implemented */
2649 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2650 SPR_NOACCESS, SPR_NOACCESS,
2651 &spr_read_generic, &spr_write_generic,
2652 0x00000000);
2653 /* XXX : not implemented */
2654 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2655 SPR_NOACCESS, SPR_NOACCESS,
2656 &spr_read_generic, &spr_write_generic,
2657 0x00000000);
2658 /* XXX : not implemented */
2659 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2660 SPR_NOACCESS, SPR_NOACCESS,
2661 &spr_read_generic, &spr_write_generic,
2662 0x00000000);
2663 /* XXX : not implemented */
2664 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2665 SPR_NOACCESS, SPR_NOACCESS,
2666 &spr_read_generic, &spr_write_generic,
2667 0x00000000);
2668 /* XXX : not implemented */
2669 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2670 SPR_NOACCESS, SPR_NOACCESS,
2671 &spr_read_generic, &spr_write_generic,
2672 0x00000000);
2673 }
2674
2675 // XXX: TODO
2676 /*
2677 * AMR => SPR 29 (Power 2.04)
2678 * CTRL => SPR 136 (Power 2.04)
2679 * CTRL => SPR 152 (Power 2.04)
2680 * SCOMC => SPR 276 (64 bits ?)
2681 * SCOMD => SPR 277 (64 bits ?)
2682 * TBU40 => SPR 286 (Power 2.04 hypv)
2683 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2684 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2685 * HDSISR => SPR 306 (Power 2.04 hypv)
2686 * HDAR => SPR 307 (Power 2.04 hypv)
2687 * PURR => SPR 309 (Power 2.04 hypv)
2688 * HDEC => SPR 310 (Power 2.04 hypv)
2689 * HIOR => SPR 311 (hypv)
2690 * RMOR => SPR 312 (970)
2691 * HRMOR => SPR 313 (Power 2.04 hypv)
2692 * HSRR0 => SPR 314 (Power 2.04 hypv)
2693 * HSRR1 => SPR 315 (Power 2.04 hypv)
2694 * LPIDR => SPR 317 (970)
2695 * EPR => SPR 702 (Power 2.04 emb)
2696 * perf => 768-783 (Power 2.04)
2697 * perf => 784-799 (Power 2.04)
2698 * PPR => SPR 896 (Power 2.04)
2699 * EPLC => SPR 947 (Power 2.04 emb)
2700 * EPSC => SPR 948 (Power 2.04 emb)
2701 * DABRX => 1015 (Power 2.04 hypv)
2702 * FPECR => SPR 1022 (?)
2703 * ... and more (thermal management, performance counters, ...)
2704 */
2705
2706 /*****************************************************************************/
2707 /* Exception vectors models */
2708 static void init_excp_4xx_real (CPUPPCState *env)
2709 {
2710 #if !defined(CONFIG_USER_ONLY)
2711 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2712 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2713 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2714 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2715 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2716 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2717 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2718 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2719 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2720 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2721 env->ivor_mask = 0x0000FFF0UL;
2722 env->ivpr_mask = 0xFFFF0000UL;
2723 /* Hardware reset vector */
2724 env->hreset_vector = 0xFFFFFFFCUL;
2725 #endif
2726 }
2727
2728 static void init_excp_4xx_softmmu (CPUPPCState *env)
2729 {
2730 #if !defined(CONFIG_USER_ONLY)
2731 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2732 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2733 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2734 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2735 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2736 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2737 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2738 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2739 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2740 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2741 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2742 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2743 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2744 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2745 env->ivor_mask = 0x0000FFF0UL;
2746 env->ivpr_mask = 0xFFFF0000UL;
2747 /* Hardware reset vector */
2748 env->hreset_vector = 0xFFFFFFFCUL;
2749 #endif
2750 }
2751
2752 static void init_excp_MPC5xx (CPUPPCState *env)
2753 {
2754 #if !defined(CONFIG_USER_ONLY)
2755 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2756 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2757 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2758 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2759 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2760 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2761 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2762 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2763 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2764 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2765 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2766 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2767 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2768 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2769 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2770 env->ivor_mask = 0x0000FFF0UL;
2771 env->ivpr_mask = 0xFFFF0000UL;
2772 /* Hardware reset vector */
2773 env->hreset_vector = 0x00000100UL;
2774 #endif
2775 }
2776
2777 static void init_excp_MPC8xx (CPUPPCState *env)
2778 {
2779 #if !defined(CONFIG_USER_ONLY)
2780 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2781 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2782 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2783 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2784 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2785 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2786 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2787 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2788 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2789 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2790 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2791 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2792 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2793 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2794 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2795 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2796 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2797 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2798 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2799 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2800 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2801 env->ivor_mask = 0x0000FFF0UL;
2802 env->ivpr_mask = 0xFFFF0000UL;
2803 /* Hardware reset vector */
2804 env->hreset_vector = 0x00000100UL;
2805 #endif
2806 }
2807
2808 static void init_excp_G2 (CPUPPCState *env)
2809 {
2810 #if !defined(CONFIG_USER_ONLY)
2811 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2812 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2813 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2814 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2815 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2816 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2817 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2818 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2819 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2820 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2821 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2822 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2823 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2824 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2825 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2826 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2827 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2828 /* Hardware reset vector */
2829 env->hreset_vector = 0x00000100UL;
2830 #endif
2831 }
2832
2833 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2834 {
2835 #if !defined(CONFIG_USER_ONLY)
2836 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2837 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2838 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2839 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2840 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2841 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2842 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2843 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2844 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2845 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2846 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2847 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2848 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2849 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2850 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2851 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2852 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2853 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2854 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2855 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2856 env->ivor_mask = 0x0000FFF7UL;
2857 env->ivpr_mask = ivpr_mask;
2858 /* Hardware reset vector */
2859 env->hreset_vector = 0xFFFFFFFCUL;
2860 #endif
2861 }
2862
2863 static void init_excp_BookE (CPUPPCState *env)
2864 {
2865 #if !defined(CONFIG_USER_ONLY)
2866 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2867 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2868 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2869 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2870 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2871 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2872 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2873 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2874 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2875 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2876 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2877 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2878 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2879 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2880 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2881 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2882 env->ivor_mask = 0x0000FFF0UL;
2883 env->ivpr_mask = 0xFFFF0000UL;
2884 /* Hardware reset vector */
2885 env->hreset_vector = 0xFFFFFFFCUL;
2886 #endif
2887 }
2888
2889 static void init_excp_601 (CPUPPCState *env)
2890 {
2891 #if !defined(CONFIG_USER_ONLY)
2892 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2893 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2894 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2895 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2896 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2897 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2898 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2899 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2900 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2901 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2902 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2903 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2904 /* Hardware reset vector */
2905 env->hreset_vector = 0x00000100UL;
2906 #endif
2907 }
2908
2909 static void init_excp_602 (CPUPPCState *env)
2910 {
2911 #if !defined(CONFIG_USER_ONLY)
2912 /* XXX: exception prefix has a special behavior on 602 */
2913 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2914 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2915 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2916 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2917 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2918 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2919 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2920 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2921 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2922 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2923 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2924 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2925 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2926 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2927 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2928 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2929 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2930 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2931 /* Hardware reset vector */
2932 env->hreset_vector = 0x00000100UL;
2933 #endif
2934 }
2935
2936 static void init_excp_603 (CPUPPCState *env)
2937 {
2938 #if !defined(CONFIG_USER_ONLY)
2939 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2940 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2941 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2942 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2943 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2944 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2945 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2946 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2947 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2948 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2949 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2950 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2951 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2952 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2953 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2954 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2955 /* Hardware reset vector */
2956 env->hreset_vector = 0x00000100UL;
2957 #endif
2958 }
2959
2960 static void init_excp_604 (CPUPPCState *env)
2961 {
2962 #if !defined(CONFIG_USER_ONLY)
2963 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2964 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2965 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2966 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2967 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2968 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2969 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2970 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2971 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2972 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2973 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2974 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2975 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2976 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2977 /* Hardware reset vector */
2978 env->hreset_vector = 0x00000100UL;
2979 #endif
2980 }
2981
2982 static void init_excp_7x0 (CPUPPCState *env)
2983 {
2984 #if !defined(CONFIG_USER_ONLY)
2985 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2986 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2987 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2988 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2989 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2990 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2991 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2992 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2993 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2994 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2995 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2996 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2997 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2998 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2999 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3000 /* Hardware reset vector */
3001 env->hreset_vector = 0x00000100UL;
3002 #endif
3003 }
3004
3005 static void init_excp_750cl (CPUPPCState *env)
3006 {
3007 #if !defined(CONFIG_USER_ONLY)
3008 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3009 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3010 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3011 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3012 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3013 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3014 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3015 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3016 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3017 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3018 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3019 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3020 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3021 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3022 /* Hardware reset vector */
3023 env->hreset_vector = 0x00000100UL;
3024 #endif
3025 }
3026
3027 static void init_excp_750cx (CPUPPCState *env)
3028 {
3029 #if !defined(CONFIG_USER_ONLY)
3030 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3031 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3032 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3033 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3034 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3035 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3036 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3037 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3038 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3039 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3040 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3041 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3042 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3043 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3044 /* Hardware reset vector */
3045 env->hreset_vector = 0x00000100UL;
3046 #endif
3047 }
3048
3049 /* XXX: Check if this is correct */
3050 static void init_excp_7x5 (CPUPPCState *env)
3051 {
3052 #if !defined(CONFIG_USER_ONLY)
3053 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3054 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3055 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3056 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3057 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3058 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3059 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3060 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3061 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3062 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3063 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3064 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3065 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3066 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3067 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3068 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3069 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3070 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3071 /* Hardware reset vector */
3072 env->hreset_vector = 0x00000100UL;
3073 #endif
3074 }
3075
3076 static void init_excp_7400 (CPUPPCState *env)
3077 {
3078 #if !defined(CONFIG_USER_ONLY)
3079 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3080 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3081 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3082 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3083 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3084 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3085 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3086 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3087 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3088 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3089 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3090 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3091 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3092 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3093 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3094 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3095 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3096 /* Hardware reset vector */
3097 env->hreset_vector = 0x00000100UL;
3098 #endif
3099 }
3100
3101 static void init_excp_7450 (CPUPPCState *env)
3102 {
3103 #if !defined(CONFIG_USER_ONLY)
3104 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3105 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3106 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3107 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3108 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3109 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3110 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3111 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3112 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3113 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3114 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3115 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3116 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3117 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3118 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3119 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3120 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3121 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3122 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3123 /* Hardware reset vector */
3124 env->hreset_vector = 0x00000100UL;
3125 #endif
3126 }
3127
3128 #if defined (TARGET_PPC64)
3129 static void init_excp_970 (CPUPPCState *env)
3130 {
3131 #if !defined(CONFIG_USER_ONLY)
3132 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3133 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3134 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3135 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3136 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3137 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3138 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3139 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3140 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3141 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3142 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3143 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3144 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3145 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3146 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3147 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3148 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3149 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3150 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3151 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3152 /* Hardware reset vector */
3153 env->hreset_vector = 0x0000000000000100ULL;
3154 #endif
3155 }
3156
3157 static void init_excp_POWER7 (CPUPPCState *env)
3158 {
3159 #if !defined(CONFIG_USER_ONLY)
3160 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3161 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3162 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3163 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3164 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3165 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3166 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3167 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3168 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3169 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3170 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3171 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3172 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3173 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3174 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3175 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3176 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
3177 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60;
3178 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3179 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3180 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3181 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3182 /* Hardware reset vector */
3183 env->hreset_vector = 0x0000000000000100ULL;
3184 #endif
3185 }
3186 #endif
3187
3188 /*****************************************************************************/
3189 /* Power management enable checks */
3190 static int check_pow_none (CPUPPCState *env)
3191 {
3192 return 0;
3193 }
3194
3195 static int check_pow_nocheck (CPUPPCState *env)
3196 {
3197 return 1;
3198 }
3199
3200 static int check_pow_hid0 (CPUPPCState *env)
3201 {
3202 if (env->spr[SPR_HID0] & 0x00E00000)
3203 return 1;
3204
3205 return 0;
3206 }
3207
3208 static int check_pow_hid0_74xx (CPUPPCState *env)
3209 {
3210 if (env->spr[SPR_HID0] & 0x00600000)
3211 return 1;
3212
3213 return 0;
3214 }
3215
3216 static bool ppc_cpu_interrupts_big_endian_always(PowerPCCPU *cpu)
3217 {
3218 return true;
3219 }
3220
3221 #ifdef TARGET_PPC64
3222 static bool ppc_cpu_interrupts_big_endian_lpcr(PowerPCCPU *cpu)
3223 {
3224 return !(cpu->env.spr[SPR_LPCR] & LPCR_ILE);
3225 }
3226 #endif
3227
3228 /*****************************************************************************/
3229 /* PowerPC implementations definitions */
3230
3231 #define POWERPC_FAMILY(_name) \
3232 static void \
3233 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
3234 \
3235 static const TypeInfo \
3236 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
3237 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
3238 .parent = TYPE_POWERPC_CPU, \
3239 .abstract = true, \
3240 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
3241 }; \
3242 \
3243 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
3244 { \
3245 type_register_static( \
3246 &glue(glue(ppc_, _name), _cpu_family_type_info)); \
3247 } \
3248 \
3249 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
3250 \
3251 static void glue(glue(ppc_, _name), _cpu_family_class_init)
3252
3253 static void init_proc_401 (CPUPPCState *env)
3254 {
3255 gen_spr_40x(env);
3256 gen_spr_401_403(env);
3257 gen_spr_401(env);
3258 init_excp_4xx_real(env);
3259 env->dcache_line_size = 32;
3260 env->icache_line_size = 32;
3261 /* Allocate hardware IRQ controller */
3262 ppc40x_irq_init(ppc_env_get_cpu(env));
3263
3264 SET_FIT_PERIOD(12, 16, 20, 24);
3265 SET_WDT_PERIOD(16, 20, 24, 28);
3266 }
3267
3268 POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
3269 {
3270 DeviceClass *dc = DEVICE_CLASS(oc);
3271 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3272
3273 dc->desc = "PowerPC 401";
3274 pcc->init_proc = init_proc_401;
3275 pcc->check_pow = check_pow_nocheck;
3276 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3277 PPC_WRTEE | PPC_DCR |
3278 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3279 PPC_CACHE_DCBZ |
3280 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3281 PPC_4xx_COMMON | PPC_40x_EXCP;
3282 pcc->msr_mask = (1ull << MSR_KEY) |
3283 (1ull << MSR_POW) |
3284 (1ull << MSR_CE) |
3285 (1ull << MSR_ILE) |
3286 (1ull << MSR_EE) |
3287 (1ull << MSR_PR) |
3288 (1ull << MSR_ME) |
3289 (1ull << MSR_DE) |
3290 (1ull << MSR_LE);
3291 pcc->mmu_model = POWERPC_MMU_REAL;
3292 pcc->excp_model = POWERPC_EXCP_40x;
3293 pcc->bus_model = PPC_FLAGS_INPUT_401;
3294 pcc->bfd_mach = bfd_mach_ppc_403;
3295 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3296 POWERPC_FLAG_BUS_CLK;
3297 }
3298
3299 static void init_proc_401x2 (CPUPPCState *env)
3300 {
3301 gen_spr_40x(env);
3302 gen_spr_401_403(env);
3303 gen_spr_401x2(env);
3304 gen_spr_compress(env);
3305 /* Memory management */
3306 #if !defined(CONFIG_USER_ONLY)
3307 env->nb_tlb = 64;
3308 env->nb_ways = 1;
3309 env->id_tlbs = 0;
3310 env->tlb_type = TLB_EMB;
3311 #endif
3312 init_excp_4xx_softmmu(env);
3313 env->dcache_line_size = 32;
3314 env->icache_line_size = 32;
3315 /* Allocate hardware IRQ controller */
3316 ppc40x_irq_init(ppc_env_get_cpu(env));
3317
3318 SET_FIT_PERIOD(12, 16, 20, 24);
3319 SET_WDT_PERIOD(16, 20, 24, 28);
3320 }
3321
3322 POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
3323 {
3324 DeviceClass *dc = DEVICE_CLASS(oc);
3325 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3326
3327 dc->desc = "PowerPC 401x2";
3328 pcc->init_proc = init_proc_401x2;
3329 pcc->check_pow = check_pow_nocheck;
3330 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3331 PPC_DCR | PPC_WRTEE |
3332 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3333 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3334 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3335 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3336 PPC_4xx_COMMON | PPC_40x_EXCP;
3337 pcc->msr_mask = (1ull << 20) |
3338 (1ull << MSR_KEY) |
3339 (1ull << MSR_POW) |
3340 (1ull << MSR_CE) |
3341 (1ull << MSR_ILE) |
3342 (1ull << MSR_EE) |
3343 (1ull << MSR_PR) |
3344 (1ull << MSR_ME) |
3345 (1ull << MSR_DE) |
3346 (1ull << MSR_IR) |
3347 (1ull << MSR_DR) |
3348 (1ull << MSR_LE);
3349 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3350 pcc->excp_model = POWERPC_EXCP_40x;
3351 pcc->bus_model = PPC_FLAGS_INPUT_401;
3352 pcc->bfd_mach = bfd_mach_ppc_403;
3353 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3354 POWERPC_FLAG_BUS_CLK;
3355 }
3356
3357 static void init_proc_401x3 (CPUPPCState *env)
3358 {
3359 gen_spr_40x(env);
3360 gen_spr_401_403(env);
3361 gen_spr_401(env);
3362 gen_spr_401x2(env);
3363 gen_spr_compress(env);
3364 init_excp_4xx_softmmu(env);
3365 env->dcache_line_size = 32;
3366 env->icache_line_size = 32;
3367 /* Allocate hardware IRQ controller */
3368 ppc40x_irq_init(ppc_env_get_cpu(env));
3369
3370 SET_FIT_PERIOD(12, 16, 20, 24);
3371 SET_WDT_PERIOD(16, 20, 24, 28);
3372 }
3373
3374 POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
3375 {
3376 DeviceClass *dc = DEVICE_CLASS(oc);
3377 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3378
3379 dc->desc = "PowerPC 401x3";
3380 pcc->init_proc = init_proc_401x3;
3381 pcc->check_pow = check_pow_nocheck;
3382 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3383 PPC_DCR | PPC_WRTEE |
3384 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3385 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3386 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3387 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3388 PPC_4xx_COMMON | PPC_40x_EXCP;
3389 pcc->msr_mask = (1ull << 20) |
3390 (1ull << MSR_KEY) |
3391 (1ull << MSR_POW) |
3392 (1ull << MSR_CE) |
3393 (1ull << MSR_ILE) |
3394 (1ull << MSR_EE) |
3395 (1ull << MSR_PR) |
3396 (1ull << MSR_ME) |
3397 (1ull << MSR_DWE) |
3398 (1ull << MSR_DE) |
3399 (1ull << MSR_IR) |
3400 (1ull << MSR_DR) |
3401 (1ull << MSR_LE);
3402 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3403 pcc->excp_model = POWERPC_EXCP_40x;
3404 pcc->bus_model = PPC_FLAGS_INPUT_401;
3405 pcc->bfd_mach = bfd_mach_ppc_403;
3406 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3407 POWERPC_FLAG_BUS_CLK;
3408 }
3409
3410 static void init_proc_IOP480 (CPUPPCState *env)
3411 {
3412 gen_spr_40x(env);
3413 gen_spr_401_403(env);
3414 gen_spr_401x2(env);
3415 gen_spr_compress(env);
3416 /* Memory management */
3417 #if !defined(CONFIG_USER_ONLY)
3418 env->nb_tlb = 64;
3419 env->nb_ways = 1;
3420 env->id_tlbs = 0;
3421 env->tlb_type = TLB_EMB;
3422 #endif
3423 init_excp_4xx_softmmu(env);
3424 env->dcache_line_size = 32;
3425 env->icache_line_size = 32;
3426 /* Allocate hardware IRQ controller */
3427 ppc40x_irq_init(ppc_env_get_cpu(env));
3428
3429 SET_FIT_PERIOD(8, 12, 16, 20);
3430 SET_WDT_PERIOD(16, 20, 24, 28);
3431 }
3432
3433 POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
3434 {
3435 DeviceClass *dc = DEVICE_CLASS(oc);
3436 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3437
3438 dc->desc = "IOP480";
3439 pcc->init_proc = init_proc_IOP480;
3440 pcc->check_pow = check_pow_nocheck;
3441 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3442 PPC_DCR | PPC_WRTEE |
3443 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3444 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3445 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3446 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3447 PPC_4xx_COMMON | PPC_40x_EXCP;
3448 pcc->msr_mask = (1ull << 20) |
3449 (1ull << MSR_KEY) |
3450 (1ull << MSR_POW) |
3451 (1ull << MSR_CE) |
3452 (1ull << MSR_ILE) |
3453 (1ull << MSR_EE) |
3454 (1ull << MSR_PR) |
3455 (1ull << MSR_ME) |
3456 (1ull << MSR_DE) |
3457 (1ull << MSR_IR) |
3458 (1ull << MSR_DR) |
3459 (1ull << MSR_LE);
3460 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3461 pcc->excp_model = POWERPC_EXCP_40x;
3462 pcc->bus_model = PPC_FLAGS_INPUT_401;
3463 pcc->bfd_mach = bfd_mach_ppc_403;
3464 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3465 POWERPC_FLAG_BUS_CLK;
3466 }
3467
3468 static void init_proc_403 (CPUPPCState *env)
3469 {
3470 gen_spr_40x(env);
3471 gen_spr_401_403(env);
3472 gen_spr_403(env);
3473 gen_spr_403_real(env);
3474 init_excp_4xx_real(env);
3475 env->dcache_line_size = 32;
3476 env->icache_line_size = 32;
3477 /* Allocate hardware IRQ controller */
3478 ppc40x_irq_init(ppc_env_get_cpu(env));
3479
3480 SET_FIT_PERIOD(8, 12, 16, 20);
3481 SET_WDT_PERIOD(16, 20, 24, 28);
3482 }
3483
3484 POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
3485 {
3486 DeviceClass *dc = DEVICE_CLASS(oc);
3487 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3488
3489 dc->desc = "PowerPC 403";
3490 pcc->init_proc = init_proc_403;
3491 pcc->check_pow = check_pow_nocheck;
3492 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3493 PPC_DCR | PPC_WRTEE |
3494 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3495 PPC_CACHE_DCBZ |
3496 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3497 PPC_4xx_COMMON | PPC_40x_EXCP;
3498 pcc->msr_mask = (1ull << MSR_POW) |
3499 (1ull << MSR_CE) |
3500 (1ull << MSR_ILE) |
3501 (1ull << MSR_EE) |
3502 (1ull << MSR_PR) |
3503 (1ull << MSR_ME) |
3504 (1ull << MSR_PE) |
3505 (1ull << MSR_PX) |
3506 (1ull << MSR_LE);
3507 pcc->mmu_model = POWERPC_MMU_REAL;
3508 pcc->excp_model = POWERPC_EXCP_40x;
3509 pcc->bus_model = PPC_FLAGS_INPUT_401;
3510 pcc->bfd_mach = bfd_mach_ppc_403;
3511 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3512 POWERPC_FLAG_BUS_CLK;
3513 }
3514
3515 static void init_proc_403GCX (CPUPPCState *env)
3516 {
3517 gen_spr_40x(env);
3518 gen_spr_401_403(env);
3519 gen_spr_403(env);
3520 gen_spr_403_real(env);
3521 gen_spr_403_mmu(env);
3522 /* Bus access control */
3523 /* not emulated, as QEMU never does speculative access */
3524 spr_register(env, SPR_40x_SGR, "SGR",
3525 SPR_NOACCESS, SPR_NOACCESS,
3526 &spr_read_generic, &spr_write_generic,
3527 0xFFFFFFFF);
3528 /* not emulated, as QEMU do not emulate caches */
3529 spr_register(env, SPR_40x_DCWR, "DCWR",
3530 SPR_NOACCESS, SPR_NOACCESS,
3531 &spr_read_generic, &spr_write_generic,
3532 0x00000000);
3533 /* Memory management */
3534 #if !defined(CONFIG_USER_ONLY)
3535 env->nb_tlb = 64;
3536 env->nb_ways = 1;
3537 env->id_tlbs = 0;
3538 env->tlb_type = TLB_EMB;
3539 #endif
3540 init_excp_4xx_softmmu(env);
3541 env->dcache_line_size = 32;
3542 env->icache_line_size = 32;
3543 /* Allocate hardware IRQ controller */
3544 ppc40x_irq_init(ppc_env_get_cpu(env));
3545
3546 SET_FIT_PERIOD(8, 12, 16, 20);
3547 SET_WDT_PERIOD(16, 20, 24, 28);
3548 }
3549
3550 POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
3551 {
3552 DeviceClass *dc = DEVICE_CLASS(oc);
3553 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3554
3555 dc->desc = "PowerPC 403 GCX";
3556 pcc->init_proc = init_proc_403GCX;
3557 pcc->check_pow = check_pow_nocheck;
3558 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3559 PPC_DCR | PPC_WRTEE |
3560 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3561 PPC_CACHE_DCBZ |
3562 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3563 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3564 PPC_4xx_COMMON | PPC_40x_EXCP;
3565 pcc->msr_mask = (1ull << MSR_POW) |
3566 (1ull << MSR_CE) |
3567 (1ull << MSR_ILE) |
3568 (1ull << MSR_EE) |
3569 (1ull << MSR_PR) |
3570 (1ull << MSR_ME) |
3571 (1ull << MSR_PE) |
3572 (1ull << MSR_PX) |
3573 (1ull << MSR_LE);
3574 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3575 pcc->excp_model = POWERPC_EXCP_40x;
3576 pcc->bus_model = PPC_FLAGS_INPUT_401;
3577 pcc->bfd_mach = bfd_mach_ppc_403;
3578 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3579 POWERPC_FLAG_BUS_CLK;
3580 }
3581
3582 static void init_proc_405 (CPUPPCState *env)
3583 {
3584 /* Time base */
3585 gen_tbl(env);
3586 gen_spr_40x(env);
3587 gen_spr_405(env);
3588 /* Bus access control */
3589 /* not emulated, as QEMU never does speculative access */
3590 spr_register(env, SPR_40x_SGR, "SGR",
3591 SPR_NOACCESS, SPR_NOACCESS,
3592 &spr_read_generic, &spr_write_generic,
3593 0xFFFFFFFF);
3594 /* not emulated, as QEMU do not emulate caches */
3595 spr_register(env, SPR_40x_DCWR, "DCWR",
3596 SPR_NOACCESS, SPR_NOACCESS,
3597 &spr_read_generic, &spr_write_generic,
3598 0x00000000);
3599 /* Memory management */
3600 #if !defined(CONFIG_USER_ONLY)
3601 env->nb_tlb = 64;
3602 env->nb_ways = 1;
3603 env->id_tlbs = 0;
3604 env->tlb_type = TLB_EMB;
3605 #endif
3606 init_excp_4xx_softmmu(env);
3607 env->dcache_line_size = 32;
3608 env->icache_line_size = 32;
3609 /* Allocate hardware IRQ controller */
3610 ppc40x_irq_init(ppc_env_get_cpu(env));
3611
3612 SET_FIT_PERIOD(8, 12, 16, 20);
3613 SET_WDT_PERIOD(16, 20, 24, 28);
3614 }
3615
3616 POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
3617 {
3618 DeviceClass *dc = DEVICE_CLASS(oc);
3619 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3620
3621 dc->desc = "PowerPC 405";
3622 pcc->init_proc = init_proc_405;
3623 pcc->check_pow = check_pow_nocheck;
3624 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3625 PPC_DCR | PPC_WRTEE |
3626 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3627 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3628 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3629 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3630 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
3631 pcc->msr_mask = (1ull << MSR_POW) |
3632 (1ull << MSR_CE) |
3633 (1ull << MSR_EE) |
3634 (1ull << MSR_PR) |
3635 (1ull << MSR_FP) |
3636 (1ull << MSR_DWE) |
3637 (1ull << MSR_DE) |
3638 (1ull << MSR_IR) |
3639 (1ull << MSR_DR);
3640 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
3641 pcc->excp_model = POWERPC_EXCP_40x;
3642 pcc->bus_model = PPC_FLAGS_INPUT_405;
3643 pcc->bfd_mach = bfd_mach_ppc_403;
3644 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3645 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3646 }
3647
3648 static void init_proc_440EP (CPUPPCState *env)
3649 {
3650 /* Time base */
3651 gen_tbl(env);
3652 gen_spr_BookE(env, 0x000000000000FFFFULL);
3653 gen_spr_440(env);
3654 gen_spr_usprgh(env);
3655 /* Processor identification */
3656 spr_register(env, SPR_BOOKE_PIR, "PIR",
3657 SPR_NOACCESS, SPR_NOACCESS,
3658 &spr_read_generic, &spr_write_pir,
3659 0x00000000);
3660 /* XXX : not implemented */
3661 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3662 SPR_NOACCESS, SPR_NOACCESS,
3663 &spr_read_generic, &spr_write_generic,
3664 0x00000000);
3665 /* XXX : not implemented */
3666 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3667 SPR_NOACCESS, SPR_NOACCESS,
3668 &spr_read_generic, &spr_write_generic,
3669 0x00000000);
3670 /* XXX : not implemented */
3671 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3672 SPR_NOACCESS, SPR_NOACCESS,
3673 &spr_read_generic, &spr_write_generic,
3674 0x00000000);
3675 /* XXX : not implemented */
3676 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3677 SPR_NOACCESS, SPR_NOACCESS,
3678 &spr_read_generic, &spr_write_generic,
3679 0x00000000);
3680 /* XXX : not implemented */
3681 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3682 SPR_NOACCESS, SPR_NOACCESS,
3683 &spr_read_generic, &spr_write_generic,
3684 0x00000000);
3685 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3686 SPR_NOACCESS, SPR_NOACCESS,
3687 &spr_read_generic, &spr_write_generic,
3688 0x00000000);
3689 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3690 SPR_NOACCESS, SPR_NOACCESS,
3691 &spr_read_generic, &spr_write_generic,
3692 0x00000000);
3693 /* XXX : not implemented */
3694 spr_register(env, SPR_440_CCR1, "CCR1",
3695 SPR_NOACCESS, SPR_NOACCESS,
3696 &spr_read_generic, &spr_write_generic,
3697 0x00000000);
3698 /* Memory management */
3699 #if !defined(CONFIG_USER_ONLY)
3700 env->nb_tlb = 64;
3701 env->nb_ways = 1;
3702 env->id_tlbs = 0;
3703 env->tlb_type = TLB_EMB;
3704 #endif
3705 init_excp_BookE(env);
3706 env->dcache_line_size = 32;
3707 env->icache_line_size = 32;
3708 ppc40x_irq_init(ppc_env_get_cpu(env));
3709
3710 SET_FIT_PERIOD(12, 16, 20, 24);
3711 SET_WDT_PERIOD(20, 24, 28, 32);
3712 }
3713
3714 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
3715 {
3716 DeviceClass *dc = DEVICE_CLASS(oc);
3717 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3718
3719 dc->desc = "PowerPC 440 EP";
3720 pcc->init_proc = init_proc_440EP;
3721 pcc->check_pow = check_pow_nocheck;
3722 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3723 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3724 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3725 PPC_FLOAT_STFIWX |
3726 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3727 PPC_CACHE | PPC_CACHE_ICBI |
3728 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3729 PPC_MEM_TLBSYNC | PPC_MFTB |
3730 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3731 PPC_440_SPEC;
3732 pcc->msr_mask = (1ull << MSR_POW) |
3733 (1ull << MSR_CE) |
3734 (1ull << MSR_EE) |
3735 (1ull << MSR_PR) |
3736 (1ull << MSR_FP) |
3737 (1ull << MSR_ME) |
3738 (1ull << MSR_FE0) |
3739 (1ull << MSR_DWE) |
3740 (1ull << MSR_DE) |
3741 (1ull << MSR_FE1) |
3742 (1ull << MSR_IR) |
3743 (1ull << MSR_DR);
3744 pcc->mmu_model = POWERPC_MMU_BOOKE;
3745 pcc->excp_model = POWERPC_EXCP_BOOKE;
3746 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3747 pcc->bfd_mach = bfd_mach_ppc_403;
3748 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3749 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3750 }
3751
3752 static void init_proc_440GP (CPUPPCState *env)
3753 {
3754 /* Time base */
3755 gen_tbl(env);
3756 gen_spr_BookE(env, 0x000000000000FFFFULL);
3757 gen_spr_440(env);
3758 gen_spr_usprgh(env);
3759 /* Processor identification */
3760 spr_register(env, SPR_BOOKE_PIR, "PIR",
3761 SPR_NOACCESS, SPR_NOACCESS,
3762 &spr_read_generic, &spr_write_pir,
3763 0x00000000);
3764 /* XXX : not implemented */
3765 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3766 SPR_NOACCESS, SPR_NOACCESS,
3767 &spr_read_generic, &spr_write_generic,
3768 0x00000000);
3769 /* XXX : not implemented */
3770 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3771 SPR_NOACCESS, SPR_NOACCESS,
3772 &spr_read_generic, &spr_write_generic,
3773 0x00000000);
3774 /* XXX : not implemented */
3775 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3776 SPR_NOACCESS, SPR_NOACCESS,
3777 &spr_read_generic, &spr_write_generic,
3778 0x00000000);
3779 /* XXX : not implemented */
3780 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3781 SPR_NOACCESS, SPR_NOACCESS,
3782 &spr_read_generic, &spr_write_generic,
3783 0x00000000);
3784 /* Memory management */
3785 #if !defined(CONFIG_USER_ONLY)
3786 env->nb_tlb = 64;
3787 env->nb_ways = 1;
3788 env->id_tlbs = 0;
3789 env->tlb_type = TLB_EMB;
3790 #endif
3791 init_excp_BookE(env);
3792 env->dcache_line_size = 32;
3793 env->icache_line_size = 32;
3794 /* XXX: TODO: allocate internal IRQ controller */
3795
3796 SET_FIT_PERIOD(12, 16, 20, 24);
3797 SET_WDT_PERIOD(20, 24, 28, 32);
3798 }
3799
3800 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
3801 {
3802 DeviceClass *dc = DEVICE_CLASS(oc);
3803 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3804
3805 dc->desc = "PowerPC 440 GP";
3806 pcc->init_proc = init_proc_440GP;
3807 pcc->check_pow = check_pow_nocheck;
3808 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3809 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
3810 PPC_CACHE | PPC_CACHE_ICBI |
3811 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3812 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
3813 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3814 PPC_440_SPEC;
3815 pcc->msr_mask = (1ull << MSR_POW) |
3816 (1ull << MSR_CE) |
3817 (1ull << MSR_EE) |
3818 (1ull << MSR_PR) |
3819 (1ull << MSR_FP) |
3820 (1ull << MSR_ME) |
3821 (1ull << MSR_FE0) |
3822 (1ull << MSR_DWE) |
3823 (1ull << MSR_DE) |
3824 (1ull << MSR_FE1) |
3825 (1ull << MSR_IR) |
3826 (1ull << MSR_DR);
3827 pcc->mmu_model = POWERPC_MMU_BOOKE;
3828 pcc->excp_model = POWERPC_EXCP_BOOKE;
3829 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3830 pcc->bfd_mach = bfd_mach_ppc_403;
3831 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3832 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3833 }
3834
3835 static void init_proc_440x4 (CPUPPCState *env)
3836 {
3837 /* Time base */
3838 gen_tbl(env);
3839 gen_spr_BookE(env, 0x000000000000FFFFULL);
3840 gen_spr_440(env);
3841 gen_spr_usprgh(env);
3842 /* Processor identification */
3843 spr_register(env, SPR_BOOKE_PIR, "PIR",
3844 SPR_NOACCESS, SPR_NOACCESS,
3845 &spr_read_generic, &spr_write_pir,
3846 0x00000000);
3847 /* XXX : not implemented */
3848 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3849 SPR_NOACCESS, SPR_NOACCESS,
3850 &spr_read_generic, &spr_write_generic,
3851 0x00000000);
3852 /* XXX : not implemented */
3853 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3854 SPR_NOACCESS, SPR_NOACCESS,
3855 &spr_read_generic, &spr_write_generic,
3856 0x00000000);
3857 /* XXX : not implemented */
3858 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3859 SPR_NOACCESS, SPR_NOACCESS,
3860 &spr_read_generic, &spr_write_generic,
3861 0x00000000);
3862 /* XXX : not implemented */
3863 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3864 SPR_NOACCESS, SPR_NOACCESS,
3865 &spr_read_generic, &spr_write_generic,
3866 0x00000000);
3867 /* Memory management */
3868 #if !defined(CONFIG_USER_ONLY)
3869 env->nb_tlb = 64;
3870 env->nb_ways = 1;
3871 env->id_tlbs = 0;
3872 env->tlb_type = TLB_EMB;
3873 #endif
3874 init_excp_BookE(env);
3875 env->dcache_line_size = 32;
3876 env->icache_line_size = 32;
3877 /* XXX: TODO: allocate internal IRQ controller */
3878
3879 SET_FIT_PERIOD(12, 16, 20, 24);
3880 SET_WDT_PERIOD(20, 24, 28, 32);
3881 }
3882
3883 POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
3884 {
3885 DeviceClass *dc = DEVICE_CLASS(oc);
3886 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3887
3888 dc->desc = "PowerPC 440x4";
3889 pcc->init_proc = init_proc_440x4;
3890 pcc->check_pow = check_pow_nocheck;
3891 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3892 PPC_DCR | PPC_WRTEE |
3893 PPC_CACHE | PPC_CACHE_ICBI |
3894 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3895 PPC_MEM_TLBSYNC | PPC_MFTB |
3896 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3897 PPC_440_SPEC;
3898 pcc->msr_mask = (1ull << MSR_POW) |
3899 (1ull << MSR_CE) |
3900 (1ull << MSR_EE) |
3901 (1ull << MSR_PR) |
3902 (1ull << MSR_FP) |
3903 (1ull << MSR_ME) |
3904 (1ull << MSR_FE0) |
3905 (1ull << MSR_DWE) |
3906 (1ull << MSR_DE) |
3907 (1ull << MSR_FE1) |
3908 (1ull << MSR_IR) |
3909 (1ull << MSR_DR);
3910 pcc->mmu_model = POWERPC_MMU_BOOKE;
3911 pcc->excp_model = POWERPC_EXCP_BOOKE;
3912 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3913 pcc->bfd_mach = bfd_mach_ppc_403;
3914 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3915 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3916 }
3917
3918 static void init_proc_440x5 (CPUPPCState *env)
3919 {
3920 /* Time base */
3921 gen_tbl(env);
3922 gen_spr_BookE(env, 0x000000000000FFFFULL);
3923 gen_spr_440(env);
3924 gen_spr_usprgh(env);
3925 /* Processor identification */
3926 spr_register(env, SPR_BOOKE_PIR, "PIR",
3927 SPR_NOACCESS, SPR_NOACCESS,
3928 &spr_read_generic, &spr_write_pir,
3929 0x00000000);
3930 /* XXX : not implemented */
3931 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3932 SPR_NOACCESS, SPR_NOACCESS,
3933 &spr_read_generic, &spr_write_generic,
3934 0x00000000);
3935 /* XXX : not implemented */
3936 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3937 SPR_NOACCESS, SPR_NOACCESS,
3938 &spr_read_generic, &spr_write_generic,
3939 0x00000000);
3940 /* XXX : not implemented */
3941 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3942 SPR_NOACCESS, SPR_NOACCESS,
3943 &spr_read_generic, &spr_write_generic,
3944 0x00000000);
3945 /* XXX : not implemented */
3946 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3947 SPR_NOACCESS, SPR_NOACCESS,
3948 &spr_read_generic, &spr_write_generic,
3949 0x00000000);
3950 /* XXX : not implemented */
3951 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3952 SPR_NOACCESS, SPR_NOACCESS,
3953 &spr_read_generic, &spr_write_generic,
3954 0x00000000);
3955 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3956 SPR_NOACCESS, SPR_NOACCESS,
3957 &spr_read_generic, &spr_write_generic,
3958 0x00000000);
3959 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3960 SPR_NOACCESS, SPR_NOACCESS,
3961 &spr_read_generic, &spr_write_generic,
3962 0x00000000);
3963 /* XXX : not implemented */
3964 spr_register(env, SPR_440_CCR1, "CCR1",
3965 SPR_NOACCESS, SPR_NOACCESS,
3966 &spr_read_generic, &spr_write_generic,
3967 0x00000000);
3968 /* Memory management */
3969 #if !defined(CONFIG_USER_ONLY)
3970 env->nb_tlb = 64;
3971 env->nb_ways = 1;
3972 env->id_tlbs = 0;
3973 env->tlb_type = TLB_EMB;
3974 #endif
3975 init_excp_BookE(env);
3976 env->dcache_line_size = 32;
3977 env->icache_line_size = 32;
3978 ppc40x_irq_init(ppc_env_get_cpu(env));
3979
3980 SET_FIT_PERIOD(12, 16, 20, 24);
3981 SET_WDT_PERIOD(20, 24, 28, 32);
3982 }
3983
3984 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
3985 {
3986 DeviceClass *dc = DEVICE_CLASS(oc);
3987 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3988
3989 dc->desc = "PowerPC 440x5";
3990 pcc->init_proc = init_proc_440x5;
3991 pcc->check_pow = check_pow_nocheck;
3992 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3993 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3994 PPC_CACHE | PPC_CACHE_ICBI |
3995 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3996 PPC_MEM_TLBSYNC | PPC_MFTB |
3997 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3998 PPC_440_SPEC;
3999 pcc->msr_mask = (1ull << MSR_POW) |
4000 (1ull << MSR_CE) |
4001 (1ull << MSR_EE) |
4002 (1ull << MSR_PR) |
4003 (1ull << MSR_FP) |
4004 (1ull << MSR_ME) |
4005 (1ull << MSR_FE0) |
4006 (1ull << MSR_DWE) |
4007 (1ull << MSR_DE) |
4008 (1ull << MSR_FE1) |
4009 (1ull << MSR_IR) |
4010 (1ull << MSR_DR);
4011 pcc->mmu_model = POWERPC_MMU_BOOKE;
4012 pcc->excp_model = POWERPC_EXCP_BOOKE;
4013 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4014 pcc->bfd_mach = bfd_mach_ppc_403;
4015 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4016 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4017 }
4018
4019 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
4020 {
4021 DeviceClass *dc = DEVICE_CLASS(oc);
4022 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4023
4024 dc->desc = "PowerPC 440x5 with double precision FPU";
4025 pcc->init_proc = init_proc_440x5;
4026 pcc->check_pow = check_pow_nocheck;
4027 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4028 PPC_FLOAT | PPC_FLOAT_FSQRT |
4029 PPC_FLOAT_STFIWX |
4030 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
4031 PPC_CACHE | PPC_CACHE_ICBI |
4032 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4033 PPC_MEM_TLBSYNC | PPC_MFTB |
4034 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4035 PPC_440_SPEC;
4036 pcc->insns_flags2 = PPC2_FP_CVT_S64;
4037 pcc->msr_mask = (1ull << MSR_POW) |
4038 (1ull << MSR_CE) |
4039 (1ull << MSR_EE) |
4040 (1ull << MSR_PR) |
4041 (1ull << MSR_FP) |
4042 (1ull << MSR_ME) |
4043 (1ull << MSR_FE0) |
4044 (1ull << MSR_DWE) |
4045 (1ull << MSR_DE) |
4046 (1ull << MSR_FE1) |
4047 (1ull << MSR_IR) |
4048 (1ull << MSR_DR);
4049 pcc->mmu_model = POWERPC_MMU_BOOKE;
4050 pcc->excp_model = POWERPC_EXCP_BOOKE;
4051 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4052 pcc->bfd_mach = bfd_mach_ppc_403;
4053 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4054 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4055 }
4056
4057 static void init_proc_460 (CPUPPCState *env)
4058 {
4059 /* Time base */
4060 gen_tbl(env);
4061 gen_spr_BookE(env, 0x000000000000FFFFULL);
4062 gen_spr_440(env);
4063 gen_spr_usprgh(env);
4064 /* Processor identification */
4065 spr_register(env, SPR_BOOKE_PIR, "PIR",
4066 SPR_NOACCESS, SPR_NOACCESS,
4067 &spr_read_generic, &spr_write_pir,
4068 0x00000000);
4069 /* XXX : not implemented */
4070 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4071 SPR_NOACCESS, SPR_NOACCESS,
4072 &spr_read_generic, &spr_write_generic,
4073 0x00000000);
4074 /* XXX : not implemented */
4075 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4076 SPR_NOACCESS, SPR_NOACCESS,
4077 &spr_read_generic, &spr_write_generic,
4078 0x00000000);
4079 /* XXX : not implemented */
4080 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4081 SPR_NOACCESS, SPR_NOACCESS,
4082 &spr_read_generic, &spr_write_generic,
4083 0x00000000);
4084 /* XXX : not implemented */
4085 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4086 SPR_NOACCESS, SPR_NOACCESS,
4087 &spr_read_generic, &spr_write_generic,
4088 0x00000000);
4089 /* XXX : not implemented */
4090 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4091 SPR_NOACCESS, SPR_NOACCESS,
4092 &spr_read_generic, &spr_write_generic,
4093 0x00000000);
4094 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4095 SPR_NOACCESS, SPR_NOACCESS,
4096 &spr_read_generic, &spr_write_generic,
4097 0x00000000);
4098 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4099 SPR_NOACCESS, SPR_NOACCESS,
4100 &spr_read_generic, &spr_write_generic,
4101 0x00000000);
4102 /* XXX : not implemented */
4103 spr_register(env, SPR_440_CCR1, "CCR1",
4104 SPR_NOACCESS, SPR_NOACCESS,
4105 &spr_read_generic, &spr_write_generic,
4106 0x00000000);
4107 /* XXX : not implemented */
4108 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
4109 &spr_read_generic, &spr_write_generic,
4110 &spr_read_generic, &spr_write_generic,
4111 0x00000000);
4112 /* Memory management */
4113 #if !defined(CONFIG_USER_ONLY)
4114 env->nb_tlb = 64;
4115 env->nb_ways = 1;
4116 env->id_tlbs = 0;
4117 env->tlb_type = TLB_EMB;
4118 #endif
4119 init_excp_BookE(env);
4120 env->dcache_line_size = 32;
4121 env->icache_line_size = 32;
4122 /* XXX: TODO: allocate internal IRQ controller */
4123
4124 SET_FIT_PERIOD(12, 16, 20, 24);
4125 SET_WDT_PERIOD(20, 24, 28, 32);
4126 }
4127
4128 POWERPC_FAMILY(460)(ObjectClass *oc, void *data)
4129 {
4130 DeviceClass *dc = DEVICE_CLASS(oc);
4131 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4132
4133 dc->desc = "PowerPC 460 (guessed)";
4134 pcc->init_proc = init_proc_460;
4135 pcc->check_pow = check_pow_nocheck;
4136 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4137 PPC_DCR | PPC_DCRX | PPC_DCRUX |
4138 PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB |
4139 PPC_CACHE | PPC_CACHE_ICBI |
4140 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4141 PPC_MEM_TLBSYNC | PPC_TLBIVA |
4142 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4143 PPC_440_SPEC;
4144 pcc->msr_mask = (1ull << MSR_POW) |
4145 (1ull << MSR_CE) |
4146 (1ull << MSR_EE) |
4147 (1ull << MSR_PR) |
4148 (1ull << MSR_FP) |
4149 (1ull << MSR_ME) |
4150 (1ull << MSR_FE0) |
4151 (1ull << MSR_DWE) |
4152 (1ull << MSR_DE) |
4153 (1ull << MSR_FE1) |
4154 (1ull << MSR_IR) |
4155 (1ull << MSR_DR);
4156 pcc->mmu_model = POWERPC_MMU_BOOKE;
4157 pcc->excp_model = POWERPC_EXCP_BOOKE;
4158 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4159 pcc->bfd_mach = bfd_mach_ppc_403;
4160 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4161 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4162 }
4163
4164 static void init_proc_460F (CPUPPCState *env)
4165 {
4166 /* Time base */
4167 gen_tbl(env);
4168 gen_spr_BookE(env, 0x000000000000FFFFULL);
4169 gen_spr_440(env);
4170 gen_spr_usprgh(env);
4171 /* Processor identification */
4172 spr_register(env, SPR_BOOKE_PIR, "PIR",
4173 SPR_NOACCESS, SPR_NOACCESS,
4174 &spr_read_generic, &spr_write_pir,
4175 0x00000000);
4176 /* XXX : not implemented */
4177 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4178 SPR_NOACCESS, SPR_NOACCESS,
4179 &spr_read_generic, &spr_write_generic,
4180 0x00000000);
4181 /* XXX : not implemented */
4182 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4183 SPR_NOACCESS, SPR_NOACCESS,
4184 &spr_read_generic, &spr_write_generic,
4185 0x00000000);
4186 /* XXX : not implemented */
4187 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4188 SPR_NOACCESS, SPR_NOACCESS,
4189 &spr_read_generic, &spr_write_generic,
4190 0x00000000);
4191 /* XXX : not implemented */
4192 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4193 SPR_NOACCESS, SPR_NOACCESS,
4194 &spr_read_generic, &spr_write_generic,
4195 0x00000000);
4196 /* XXX : not implemented */
4197 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4198 SPR_NOACCESS, SPR_NOACCESS,
4199 &spr_read_generic, &spr_write_generic,
4200 0x00000000);
4201 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4202 SPR_NOACCESS, SPR_NOACCESS,
4203 &spr_read_generic, &spr_write_generic,
4204 0x00000000);
4205 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4206 SPR_NOACCESS, SPR_NOACCESS,
4207 &spr_read_generic, &spr_write_generic,
4208 0x00000000);
4209 /* XXX : not implemented */
4210 spr_register(env, SPR_440_CCR1, "CCR1",
4211 SPR_NOACCESS, SPR_NOACCESS,
4212 &spr_read_generic, &spr_write_generic,
4213 0x00000000);
4214 /* XXX : not implemented */
4215 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
4216 &spr_read_generic, &spr_write_generic,
4217 &spr_read_generic, &spr_write_generic,
4218 0x00000000);
4219 /* Memory management */
4220 #if !defined(CONFIG_USER_ONLY)
4221 env->nb_tlb = 64;
4222 env->nb_ways = 1;
4223 env->id_tlbs = 0;
4224 env->tlb_type = TLB_EMB;
4225 #endif
4226 init_excp_BookE(env);
4227 env->dcache_line_size = 32;
4228 env->icache_line_size = 32;
4229 /* XXX: TODO: allocate internal IRQ controller */
4230
4231 SET_FIT_PERIOD(12, 16, 20, 24);
4232 SET_WDT_PERIOD(20, 24, 28, 32);
4233 }
4234
4235 POWERPC_FAMILY(460F)(ObjectClass *oc, void *data)
4236 {
4237 DeviceClass *dc = DEVICE_CLASS(oc);
4238 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4239
4240 dc->desc = "PowerPC 460F (guessed)";
4241 pcc->init_proc = init_proc_460F;
4242 pcc->check_pow = check_pow_nocheck;
4243 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4244 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
4245 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4246 PPC_FLOAT_STFIWX | PPC_MFTB |
4247 PPC_DCR | PPC_DCRX | PPC_DCRUX |
4248 PPC_WRTEE | PPC_MFAPIDI |
4249 PPC_CACHE | PPC_CACHE_ICBI |
4250 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4251 PPC_MEM_TLBSYNC | PPC_TLBIVA |
4252 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4253 PPC_440_SPEC;
4254 pcc->msr_mask = (1ull << MSR_POW) |
4255 (1ull << MSR_CE) |
4256 (1ull << MSR_EE) |
4257 (1ull << MSR_PR) |
4258 (1ull << MSR_FP) |
4259 (1ull << MSR_ME) |
4260 (1ull << MSR_FE0) |
4261 (1ull << MSR_DWE) |
4262 (1ull << MSR_DE) |
4263 (1ull << MSR_FE1) |
4264 (1ull << MSR_IR) |
4265 (1ull << MSR_DR);
4266 pcc->mmu_model = POWERPC_MMU_BOOKE;
4267 pcc->excp_model = POWERPC_EXCP_BOOKE;
4268 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4269 pcc->bfd_mach = bfd_mach_ppc_403;
4270 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4271 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4272 }
4273
4274 static void init_proc_MPC5xx (CPUPPCState *env)
4275 {
4276 /* Time base */
4277 gen_tbl(env);
4278 gen_spr_5xx_8xx(env);
4279 gen_spr_5xx(env);
4280 init_excp_MPC5xx(env);
4281 env->dcache_line_size = 32;
4282 env->icache_line_size = 32;
4283 /* XXX: TODO: allocate internal IRQ controller */
4284 }
4285
4286 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
4287 {
4288 DeviceClass *dc = DEVICE_CLASS(oc);
4289 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4290
4291 dc->desc = "Freescale 5xx cores (aka RCPU)";
4292 pcc->init_proc = init_proc_MPC5xx;
4293 pcc->check_pow = check_pow_none;
4294 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4295 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4296 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
4297 PPC_MFTB;
4298 pcc->msr_mask = (1ull << MSR_ILE) |
4299 (1ull << MSR_EE) |
4300 (1ull << MSR_PR) |
4301 (1ull << MSR_FP) |
4302 (1ull << MSR_ME) |
4303 (1ull << MSR_FE0) |
4304 (1ull << MSR_SE) |
4305 (1ull << MSR_DE) |
4306 (1ull << MSR_FE1) |
4307 (1ull << MSR_EP) |
4308 (1ull << MSR_RI) |
4309 (1ull << MSR_LE);
4310 pcc->mmu_model = POWERPC_MMU_REAL;
4311 pcc->excp_model = POWERPC_EXCP_603;
4312 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4313 pcc->bfd_mach = bfd_mach_ppc_505;
4314 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4315 POWERPC_FLAG_BUS_CLK;
4316 }
4317
4318 static void init_proc_MPC8xx (CPUPPCState *env)
4319 {
4320 /* Time base */
4321 gen_tbl(env);
4322 gen_spr_5xx_8xx(env);
4323 gen_spr_8xx(env);
4324 init_excp_MPC8xx(env);
4325 env->dcache_line_size = 32;
4326 env->icache_line_size = 32;
4327 /* XXX: TODO: allocate internal IRQ controller */
4328 }
4329
4330 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
4331 {
4332 DeviceClass *dc = DEVICE_CLASS(oc);
4333 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4334
4335 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
4336 pcc->init_proc = init_proc_MPC8xx;
4337 pcc->check_pow = check_pow_none;
4338 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4339 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4340 PPC_CACHE_ICBI | PPC_MFTB;
4341 pcc->msr_mask = (1ull << MSR_ILE) |
4342 (1ull << MSR_EE) |
4343 (1ull << MSR_PR) |
4344 (1ull << MSR_FP) |
4345 (1ull << MSR_ME) |
4346 (1ull << MSR_SE) |
4347 (1ull << MSR_DE) |
4348 (1ull << MSR_EP) |
4349 (1ull << MSR_IR) |
4350 (1ull << MSR_DR) |
4351 (1ull << MSR_RI) |
4352 (1ull << MSR_LE);
4353 pcc->mmu_model = POWERPC_MMU_MPC8xx;
4354 pcc->excp_model = POWERPC_EXCP_603;
4355 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4356 pcc->bfd_mach = bfd_mach_ppc_860;
4357 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4358 POWERPC_FLAG_BUS_CLK;
4359 }
4360
4361 /* Freescale 82xx cores (aka PowerQUICC-II) */
4362
4363 static void init_proc_G2 (CPUPPCState *env)
4364 {
4365 gen_spr_ne_601(env);
4366 gen_spr_G2_755(env);
4367 gen_spr_G2(env);
4368 /* Time base */
4369 gen_tbl(env);
4370 /* External access control */
4371 /* XXX : not implemented */
4372 spr_register(env, SPR_EAR, "EAR",
4373 SPR_NOACCESS, SPR_NOACCESS,
4374 &spr_read_generic, &spr_write_generic,
4375 0x00000000);
4376 /* Hardware implementation register */
4377 /* XXX : not implemented */
4378 spr_register(env, SPR_HID0, "HID0",
4379 SPR_NOACCESS, SPR_NOACCESS,
4380 &spr_read_generic, &spr_write_generic,
4381 0x00000000);
4382 /* XXX : not implemented */
4383 spr_register(env, SPR_HID1, "HID1",
4384 SPR_NOACCESS, SPR_NOACCESS,
4385 &spr_read_generic, &spr_write_generic,
4386 0x00000000);
4387 /* XXX : not implemented */
4388 spr_register(env, SPR_HID2, "HID2",
4389 SPR_NOACCESS, SPR_NOACCESS,
4390 &spr_read_generic, &spr_write_generic,
4391 0x00000000);
4392 /* Memory management */
4393 gen_low_BATs(env);
4394 gen_high_BATs(env);
4395 gen_6xx_7xx_soft_tlb(env, 64, 2);
4396 init_excp_G2(env);
4397 env->dcache_line_size = 32;
4398 env->icache_line_size = 32;
4399 /* Allocate hardware IRQ controller */
4400 ppc6xx_irq_init(ppc_env_get_cpu(env));
4401 }
4402
4403 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
4404 {
4405 DeviceClass *dc = DEVICE_CLASS(oc);
4406 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4407
4408 dc->desc = "PowerPC G2";
4409 pcc->init_proc = init_proc_G2;
4410 pcc->check_pow = check_pow_hid0;
4411 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4412 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4413 PPC_FLOAT_STFIWX |
4414 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4415 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4416 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4417 PPC_SEGMENT | PPC_EXTERN;
4418 pcc->msr_mask = (1ull << MSR_POW) |
4419 (1ull << MSR_TGPR) |
4420 (1ull << MSR_EE) |
4421 (1ull << MSR_PR) |
4422 (1ull << MSR_FP) |
4423 (1ull << MSR_ME) |
4424 (1ull << MSR_FE0) |
4425 (1ull << MSR_SE) |
4426 (1ull << MSR_DE) |
4427 (1ull << MSR_FE1) |
4428 (1ull << MSR_AL) |
4429 (1ull << MSR_EP) |
4430 (1ull << MSR_IR) |
4431 (1ull << MSR_DR) |
4432 (1ull << MSR_RI);
4433 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4434 pcc->excp_model = POWERPC_EXCP_G2;
4435 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4436 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4437 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4438 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4439 }
4440
4441 static void init_proc_G2LE (CPUPPCState *env)
4442 {
4443 gen_spr_ne_601(env);
4444 gen_spr_G2_755(env);
4445 gen_spr_G2(env);
4446 /* Time base */
4447 gen_tbl(env);
4448 /* External access control */
4449 /* XXX : not implemented */
4450 spr_register(env, SPR_EAR, "EAR",
4451 SPR_NOACCESS, SPR_NOACCESS,
4452 &spr_read_generic, &spr_write_generic,
4453 0x00000000);
4454 /* Hardware implementation register */
4455 /* XXX : not implemented */
4456 spr_register(env, SPR_HID0, "HID0",
4457 SPR_NOACCESS, SPR_NOACCESS,
4458 &spr_read_generic, &spr_write_generic,
4459 0x00000000);
4460 /* XXX : not implemented */
4461 spr_register(env, SPR_HID1, "HID1",
4462 SPR_NOACCESS, SPR_NOACCESS,
4463 &spr_read_generic, &spr_write_generic,
4464 0x00000000);
4465 /* XXX : not implemented */
4466 spr_register(env, SPR_HID2, "HID2",
4467 SPR_NOACCESS, SPR_NOACCESS,
4468 &spr_read_generic, &spr_write_generic,
4469 0x00000000);
4470
4471 /* Memory management */
4472 gen_low_BATs(env);
4473 gen_high_BATs(env);
4474 gen_6xx_7xx_soft_tlb(env, 64, 2);
4475 init_excp_G2(env);
4476 env->dcache_line_size = 32;
4477 env->icache_line_size = 32;
4478 /* Allocate hardware IRQ controller */
4479 ppc6xx_irq_init(ppc_env_get_cpu(env));
4480 }
4481
4482 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
4483 {
4484 DeviceClass *dc = DEVICE_CLASS(oc);
4485 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4486
4487 dc->desc = "PowerPC G2LE";
4488 pcc->init_proc = init_proc_G2LE;
4489 pcc->check_pow = check_pow_hid0;
4490 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4491 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4492 PPC_FLOAT_STFIWX |
4493 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4494 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4495 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4496 PPC_SEGMENT | PPC_EXTERN;
4497 pcc->msr_mask = (1ull << MSR_POW) |
4498 (1ull << MSR_TGPR) |
4499 (1ull << MSR_ILE) |
4500 (1ull << MSR_EE) |
4501 (1ull << MSR_PR) |
4502 (1ull << MSR_FP) |
4503 (1ull << MSR_ME) |
4504 (1ull << MSR_FE0) |
4505 (1ull << MSR_SE) |
4506 (1ull << MSR_DE) |
4507 (1ull << MSR_FE1) |
4508 (1ull << MSR_AL) |
4509 (1ull << MSR_EP) |
4510 (1ull << MSR_IR) |
4511 (1ull << MSR_DR) |
4512 (1ull << MSR_RI) |
4513 (1ull << MSR_LE);
4514 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4515 pcc->excp_model = POWERPC_EXCP_G2;
4516 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4517 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4518 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4519 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4520 }
4521
4522 static void init_proc_e200 (CPUPPCState *env)
4523 {
4524 /* Time base */
4525 gen_tbl(env);
4526 gen_spr_BookE(env, 0x000000070000FFFFULL);
4527 /* XXX : not implemented */
4528 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4529 &spr_read_spefscr, &spr_write_spefscr,
4530 &spr_read_spefscr, &spr_write_spefscr,
4531 0x00000000);
4532 /* Memory management */
4533 gen_spr_BookE206(env, 0x0000005D, NULL);
4534 /* XXX : not implemented */
4535 spr_register(env, SPR_HID0, "HID0",
4536 SPR_NOACCESS, SPR_NOACCESS,
4537 &spr_read_generic, &spr_write_generic,
4538 0x00000000);
4539 /* XXX : not implemented */
4540 spr_register(env, SPR_HID1, "HID1",
4541 SPR_NOACCESS, SPR_NOACCESS,
4542 &spr_read_generic, &spr_write_generic,
4543 0x00000000);
4544 /* XXX : not implemented */
4545 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4546 SPR_NOACCESS, SPR_NOACCESS,
4547 &spr_read_generic, &spr_write_generic,
4548 0x00000000);
4549 /* XXX : not implemented */
4550 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4551 SPR_NOACCESS, SPR_NOACCESS,
4552 &spr_read_generic, &spr_write_generic,
4553 0x00000000);
4554 /* XXX : not implemented */
4555 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4556 SPR_NOACCESS, SPR_NOACCESS,
4557 &spr_read_generic, &spr_write_generic,
4558 0x00000000);
4559 /* XXX : not implemented */
4560 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4561 SPR_NOACCESS, SPR_NOACCESS,
4562 &spr_read_generic, &spr_write_generic,
4563 0x00000000);
4564 /* XXX : not implemented */
4565 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4566 SPR_NOACCESS, SPR_NOACCESS,
4567 &spr_read_generic, &spr_write_generic,
4568 0x00000000);
4569 /* XXX : not implemented */
4570 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4571 &spr_read_generic, SPR_NOACCESS,
4572 &spr_read_generic, SPR_NOACCESS,
4573 0x00000000);
4574 /* XXX : not implemented */
4575 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4576 SPR_NOACCESS, SPR_NOACCESS,
4577 &spr_read_generic, &spr_write_generic,
4578 0x00000000);
4579 /* XXX : not implemented */
4580 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4581 SPR_NOACCESS, SPR_NOACCESS,
4582 &spr_read_generic, &spr_write_generic,
4583 0x00000000);
4584 /* XXX : not implemented */
4585 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4586 SPR_NOACCESS, SPR_NOACCESS,
4587 &spr_read_generic, &spr_write_generic,
4588 0x00000000);
4589 /* XXX : not implemented */
4590 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4591 SPR_NOACCESS, SPR_NOACCESS,
4592 &spr_read_generic, &spr_write_generic,
4593 0x00000000);
4594 /* XXX : not implemented */
4595 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4596 SPR_NOACCESS, SPR_NOACCESS,
4597 &spr_read_generic, &spr_write_generic,
4598 0x00000000);
4599 /* XXX : not implemented */
4600 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4601 SPR_NOACCESS, SPR_NOACCESS,
4602 &spr_read_generic, &spr_write_generic,
4603 0x00000000);
4604 /* XXX : not implemented */
4605 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4606 SPR_NOACCESS, SPR_NOACCESS,
4607 &spr_read_generic, &spr_write_generic,
4608 0x00000000); /* TOFIX */
4609 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4610 SPR_NOACCESS, SPR_NOACCESS,
4611 &spr_read_generic, &spr_write_generic,
4612 0x00000000);
4613 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4614 SPR_NOACCESS, SPR_NOACCESS,
4615 &spr_read_generic, &spr_write_generic,
4616 0x00000000);
4617 #if !defined(CONFIG_USER_ONLY)
4618 env->nb_tlb = 64;
4619 env->nb_ways = 1;
4620 env->id_tlbs = 0;
4621 env->tlb_type = TLB_EMB;
4622 #endif
4623 init_excp_e200(env, 0xFFFF0000UL);
4624 env->dcache_line_size = 32;
4625 env->icache_line_size = 32;
4626 /* XXX: TODO: allocate internal IRQ controller */
4627 }
4628
4629 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
4630 {
4631 DeviceClass *dc = DEVICE_CLASS(oc);
4632 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4633
4634 dc->desc = "e200 core";
4635 pcc->init_proc = init_proc_e200;
4636 pcc->check_pow = check_pow_hid0;
4637 /* XXX: unimplemented instructions:
4638 * dcblc
4639 * dcbtlst
4640 * dcbtstls
4641 * icblc
4642 * icbtls
4643 * tlbivax
4644 * all SPE multiply-accumulate instructions
4645 */
4646 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4647 PPC_SPE | PPC_SPE_SINGLE |
4648 PPC_WRTEE | PPC_RFDI |
4649 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4650 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4651 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
4652 PPC_BOOKE;
4653 pcc->msr_mask = (1ull << MSR_UCLE) |
4654 (1ull << MSR_SPE) |
4655 (1ull << MSR_POW) |
4656 (1ull << MSR_CE) |
4657 (1ull << MSR_EE) |
4658 (1ull << MSR_PR) |
4659 (1ull << MSR_FP) |
4660 (1ull << MSR_ME) |
4661 (1ull << MSR_FE0) |
4662 (1ull << MSR_DWE) |
4663 (1ull << MSR_DE) |
4664 (1ull << MSR_FE1) |
4665 (1ull << MSR_IR) |
4666 (1ull << MSR_DR);
4667 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4668 pcc->excp_model = POWERPC_EXCP_BOOKE;
4669 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4670 pcc->bfd_mach = bfd_mach_ppc_860;
4671 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4672 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4673 POWERPC_FLAG_BUS_CLK;
4674 }
4675
4676 static void init_proc_e300 (CPUPPCState *env)
4677 {
4678 gen_spr_ne_601(env);
4679 gen_spr_603(env);
4680 /* Time base */
4681 gen_tbl(env);
4682 /* hardware implementation registers */
4683 /* XXX : not implemented */
4684 spr_register(env, SPR_HID0, "HID0",
4685 SPR_NOACCESS, SPR_NOACCESS,
4686 &spr_read_generic, &spr_write_generic,
4687 0x00000000);
4688 /* XXX : not implemented */
4689 spr_register(env, SPR_HID1, "HID1",
4690 SPR_NOACCESS, SPR_NOACCESS,
4691 &spr_read_generic, &spr_write_generic,
4692 0x00000000);
4693 /* XXX : not implemented */
4694 spr_register(env, SPR_HID2, "HID2",
4695 SPR_NOACCESS, SPR_NOACCESS,
4696 &spr_read_generic, &spr_write_generic,
4697 0x00000000);
4698 /* Breakpoints */
4699 /* XXX : not implemented */
4700 spr_register(env, SPR_DABR, "DABR",
4701 SPR_NOACCESS, SPR_NOACCESS,
4702 &spr_read_generic, &spr_write_generic,
4703 0x00000000);
4704 /* XXX : not implemented */
4705 spr_register(env, SPR_DABR2, "DABR2",
4706 SPR_NOACCESS, SPR_NOACCESS,
4707 &spr_read_generic, &spr_write_generic,
4708 0x00000000);
4709 /* XXX : not implemented */
4710 spr_register(env, SPR_IABR2, "IABR2",
4711 SPR_NOACCESS, SPR_NOACCESS,
4712 &spr_read_generic, &spr_write_generic,
4713 0x00000000);
4714 /* XXX : not implemented */
4715 spr_register(env, SPR_IBCR, "IBCR",
4716 SPR_NOACCESS, SPR_NOACCESS,
4717 &spr_read_generic, &spr_write_generic,
4718 0x00000000);
4719 /* XXX : not implemented */
4720 spr_register(env, SPR_DBCR, "DBCR",
4721 SPR_NOACCESS, SPR_NOACCESS,
4722 &spr_read_generic, &spr_write_generic,
4723 0x00000000);
4724 /* Memory management */
4725 gen_low_BATs(env);
4726 gen_high_BATs(env);
4727 gen_6xx_7xx_soft_tlb(env, 64, 2);
4728 init_excp_603(env);
4729 env->dcache_line_size = 32;
4730 env->icache_line_size = 32;
4731 /* Allocate hardware IRQ controller */
4732 ppc6xx_irq_init(ppc_env_get_cpu(env));
4733 }
4734
4735 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
4736 {
4737 DeviceClass *dc = DEVICE_CLASS(oc);
4738 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4739
4740 dc->desc = "e300 core";
4741 pcc->init_proc = init_proc_e300;
4742 pcc->check_pow = check_pow_hid0;
4743 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4744 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4745 PPC_FLOAT_STFIWX |
4746 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4747 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4748 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4749 PPC_SEGMENT | PPC_EXTERN;
4750 pcc->msr_mask = (1ull << MSR_POW) |
4751 (1ull << MSR_TGPR) |
4752 (1ull << MSR_ILE) |
4753 (1ull << MSR_EE) |
4754 (1ull << MSR_PR) |
4755 (1ull << MSR_FP) |
4756 (1ull << MSR_ME) |
4757 (1ull << MSR_FE0) |
4758 (1ull << MSR_SE) |
4759 (1ull << MSR_DE) |
4760 (1ull << MSR_FE1) |
4761 (1ull << MSR_AL) |
4762 (1ull << MSR_EP) |
4763 (1ull << MSR_IR) |
4764 (1ull << MSR_DR) |
4765 (1ull << MSR_RI) |
4766 (1ull << MSR_LE);
4767 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4768 pcc->excp_model = POWERPC_EXCP_603;
4769 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4770 pcc->bfd_mach = bfd_mach_ppc_603;
4771 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4772 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4773 }
4774
4775 #if !defined(CONFIG_USER_ONLY)
4776 static void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
4777 {
4778 TCGv val = tcg_temp_new();
4779 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
4780 gen_store_spr(SPR_BOOKE_MAS3, val);
4781 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
4782 gen_store_spr(SPR_BOOKE_MAS7, val);
4783 tcg_temp_free(val);
4784 }
4785
4786 static void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
4787 {
4788 TCGv mas7 = tcg_temp_new();
4789 TCGv mas3 = tcg_temp_new();
4790 gen_load_spr(mas7, SPR_BOOKE_MAS7);
4791 tcg_gen_shli_tl(mas7, mas7, 32);
4792 gen_load_spr(mas3, SPR_BOOKE_MAS3);
4793 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
4794 tcg_temp_free(mas3);
4795 tcg_temp_free(mas7);
4796 }
4797
4798 #endif
4799
4800 enum fsl_e500_version {
4801 fsl_e500v1,
4802 fsl_e500v2,
4803 fsl_e500mc,
4804 fsl_e5500,
4805 };
4806
4807 static void init_proc_e500 (CPUPPCState *env, int version)
4808 {
4809 PowerPCCPU *cpu = ppc_env_get_cpu(env);
4810 uint32_t tlbncfg[2];
4811 uint64_t ivor_mask;
4812 uint64_t ivpr_mask = 0xFFFF0000ULL;
4813 uint32_t l1cfg0 = 0x3800 /* 8 ways */
4814 | 0x0020; /* 32 kb */
4815 uint32_t l1cfg1 = 0x3800 /* 8 ways */
4816 | 0x0020; /* 32 kb */
4817 #if !defined(CONFIG_USER_ONLY)
4818 int i;
4819 #endif
4820
4821 /* Time base */
4822 gen_tbl(env);
4823 /*
4824 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4825 * complain when accessing them.
4826 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4827 */
4828 switch (version) {
4829 case fsl_e500v1:
4830 case fsl_e500v2:
4831 default:
4832 ivor_mask = 0x0000000F0000FFFFULL;
4833 break;
4834 case fsl_e500mc:
4835 case fsl_e5500:
4836 ivor_mask = 0x000003FE0000FFFFULL;
4837 break;
4838 }
4839 gen_spr_BookE(env, ivor_mask);
4840 /* Processor identification */
4841 spr_register(env, SPR_BOOKE_PIR, "PIR",
4842 SPR_NOACCESS, SPR_NOACCESS,
4843 &spr_read_generic, &spr_write_pir,
4844 0x00000000);
4845 /* XXX : not implemented */
4846 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4847 &spr_read_spefscr, &spr_write_spefscr,
4848 &spr_read_spefscr, &spr_write_spefscr,
4849 0x00000000);
4850 #if !defined(CONFIG_USER_ONLY)
4851 /* Memory management */
4852 env->nb_pids = 3;
4853 env->nb_ways = 2;
4854 env->id_tlbs = 0;
4855 switch (version) {
4856 case fsl_e500v1:
4857 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4858 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4859 break;
4860 case fsl_e500v2:
4861 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4862 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4863 break;
4864 case fsl_e500mc:
4865 case fsl_e5500:
4866 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4867 tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
4868 break;
4869 default:
4870 cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4871 }
4872 #endif
4873 /* Cache sizes */
4874 switch (version) {
4875 case fsl_e500v1:
4876 case fsl_e500v2:
4877 env->dcache_line_size = 32;
4878 env->icache_line_size = 32;
4879 break;
4880 case fsl_e500mc:
4881 case fsl_e5500:
4882 env->dcache_line_size = 64;
4883 env->icache_line_size = 64;
4884 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
4885 l1cfg1 |= 0x1000000; /* 64 byte cache block size */
4886 break;
4887 default:
4888 cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4889 }
4890 gen_spr_BookE206(env, 0x000000DF, tlbncfg);
4891 /* XXX : not implemented */
4892 spr_register(env, SPR_HID0, "HID0",
4893 SPR_NOACCESS, SPR_NOACCESS,
4894 &spr_read_generic, &spr_write_generic,
4895 0x00000000);
4896 /* XXX : not implemented */
4897 spr_register(env, SPR_HID1, "HID1",
4898 SPR_NOACCESS, SPR_NOACCESS,
4899 &spr_read_generic, &spr_write_generic,
4900 0x00000000);
4901 /* XXX : not implemented */
4902 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4903 SPR_NOACCESS, SPR_NOACCESS,
4904 &spr_read_generic, &spr_write_generic,
4905 0x00000000);
4906 /* XXX : not implemented */
4907 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4908 SPR_NOACCESS, SPR_NOACCESS,
4909 &spr_read_generic, &spr_write_generic,
4910 0x00000000);
4911 /* XXX : not implemented */
4912 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4913 SPR_NOACCESS, SPR_NOACCESS,
4914 &spr_read_generic, &spr_write_generic,
4915 0x00000000);
4916 /* XXX : not implemented */
4917 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4918 SPR_NOACCESS, SPR_NOACCESS,
4919 &spr_read_generic, &spr_write_generic,
4920 0x00000000);
4921 /* XXX : not implemented */
4922 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4923 SPR_NOACCESS, SPR_NOACCESS,
4924 &spr_read_generic, &spr_write_generic,
4925 0x00000000);
4926 /* XXX : not implemented */
4927 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4928 SPR_NOACCESS, SPR_NOACCESS,
4929 &spr_read_generic, &spr_write_generic,
4930 0x00000000);
4931 /* XXX : not implemented */
4932 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4933 &spr_read_generic, SPR_NOACCESS,
4934 &spr_read_generic, SPR_NOACCESS,
4935 l1cfg0);
4936 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
4937 &spr_read_generic, SPR_NOACCESS,
4938 &spr_read_generic, SPR_NOACCESS,
4939 l1cfg1);
4940 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4941 SPR_NOACCESS, SPR_NOACCESS,
4942 &spr_read_generic, &spr_write_e500_l1csr0,
4943 0x00000000);
4944 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4945 SPR_NOACCESS, SPR_NOACCESS,
4946 &spr_read_generic, &spr_write_e500_l1csr1,
4947 0x00000000);
4948 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4949 SPR_NOACCESS, SPR_NOACCESS,
4950 &spr_read_generic, &spr_write_generic,
4951 0x00000000);
4952 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4953 SPR_NOACCESS, SPR_NOACCESS,
4954 &spr_read_generic, &spr_write_generic,
4955 0x00000000);
4956 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4957 SPR_NOACCESS, SPR_NOACCESS,
4958 &spr_read_generic, &spr_write_booke206_mmucsr0,
4959 0x00000000);
4960 spr_register(env, SPR_BOOKE_EPR, "EPR",
4961 SPR_NOACCESS, SPR_NOACCESS,
4962 &spr_read_generic, SPR_NOACCESS,
4963 0x00000000);
4964 /* XXX better abstract into Emb.xxx features */
4965 if (version == fsl_e5500) {
4966 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
4967 SPR_NOACCESS, SPR_NOACCESS,
4968 &spr_read_generic, &spr_write_generic,
4969 0x00000000);
4970 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
4971 SPR_NOACCESS, SPR_NOACCESS,
4972 &spr_read_mas73, &spr_write_mas73,
4973 0x00000000);
4974 ivpr_mask = (target_ulong)~0xFFFFULL;
4975 }
4976
4977 #if !defined(CONFIG_USER_ONLY)
4978 env->nb_tlb = 0;
4979 env->tlb_type = TLB_MAS;
4980 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4981 env->nb_tlb += booke206_tlb_size(env, i);
4982 }
4983 #endif
4984
4985 init_excp_e200(env, ivpr_mask);
4986 /* Allocate hardware IRQ controller */
4987 ppce500_irq_init(ppc_env_get_cpu(env));
4988 }
4989
4990 static void init_proc_e500v1(CPUPPCState *env)
4991 {
4992 init_proc_e500(env, fsl_e500v1);
4993 }
4994
4995 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
4996 {
4997 DeviceClass *dc = DEVICE_CLASS(oc);
4998 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4999
5000 dc->desc = "e500v1 core";
5001 pcc->init_proc = init_proc_e500v1;
5002 pcc->check_pow = check_pow_hid0;
5003 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
5004 PPC_SPE | PPC_SPE_SINGLE |
5005 PPC_WRTEE | PPC_RFDI |
5006 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5007 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5008 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
5009 pcc->insns_flags2 = PPC2_BOOKE206;
5010 pcc->msr_mask = (1ull << MSR_UCLE) |
5011 (1ull << MSR_SPE) |
5012 (1ull << MSR_POW) |
5013 (1ull << MSR_CE) |
5014 (1ull << MSR_EE) |
5015 (1ull << MSR_PR) |
5016 (1ull << MSR_FP) |
5017 (1ull << MSR_ME) |
5018 (1ull << MSR_FE0) |
5019 (1ull << MSR_DWE) |
5020 (1ull << MSR_DE) |
5021 (1ull << MSR_FE1) |
5022 (1ull << MSR_IR) |
5023 (1ull << MSR_DR);
5024 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5025 pcc->excp_model = POWERPC_EXCP_BOOKE;
5026 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5027 pcc->bfd_mach = bfd_mach_ppc_860;
5028 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
5029 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
5030 POWERPC_FLAG_BUS_CLK;
5031 }
5032
5033 static void init_proc_e500v2(CPUPPCState *env)
5034 {
5035 init_proc_e500(env, fsl_e500v2);
5036 }
5037
5038 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
5039 {
5040 DeviceClass *dc = DEVICE_CLASS(oc);
5041 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5042
5043 dc->desc = "e500v2 core";
5044 pcc->init_proc = init_proc_e500v2;
5045 pcc->check_pow = check_pow_hid0;
5046 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
5047 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
5048 PPC_WRTEE | PPC_RFDI |
5049 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5050 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5051 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
5052 pcc->insns_flags2 = PPC2_BOOKE206;
5053 pcc->msr_mask = (1ull << MSR_UCLE) |
5054 (1ull << MSR_SPE) |
5055 (1ull << MSR_POW) |
5056 (1ull << MSR_CE) |
5057 (1ull << MSR_EE) |
5058 (1ull << MSR_PR) |
5059 (1ull << MSR_FP) |
5060 (1ull << MSR_ME) |
5061 (1ull << MSR_FE0) |
5062 (1ull << MSR_DWE) |
5063 (1ull << MSR_DE) |
5064 (1ull << MSR_FE1) |
5065 (1ull << MSR_IR) |
5066 (1ull << MSR_DR);
5067 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5068 pcc->excp_model = POWERPC_EXCP_BOOKE;
5069 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5070 pcc->bfd_mach = bfd_mach_ppc_860;
5071 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
5072 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
5073 POWERPC_FLAG_BUS_CLK;
5074 }
5075
5076 static void init_proc_e500mc(CPUPPCState *env)
5077 {
5078 init_proc_e500(env, fsl_e500mc);
5079 }
5080
5081 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
5082 {
5083 DeviceClass *dc = DEVICE_CLASS(oc);
5084 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5085
5086 dc->desc = "e500mc core";
5087 pcc->init_proc = init_proc_e500mc;
5088 pcc->check_pow = check_pow_none;
5089 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
5090 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
5091 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5092 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5093 PPC_FLOAT | PPC_FLOAT_FRES |
5094 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
5095 PPC_FLOAT_STFIWX | PPC_WAIT |
5096 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
5097 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
5098 pcc->msr_mask = (1ull << MSR_GS) |
5099 (1ull << MSR_UCLE) |
5100 (1ull << MSR_CE) |
5101 (1ull << MSR_EE) |
5102 (1ull << MSR_PR) |
5103 (1ull << MSR_FP) |
5104 (1ull << MSR_ME) |
5105 (1ull << MSR_FE0) |
5106 (1ull << MSR_DE) |
5107 (1ull << MSR_FE1) |
5108 (1ull << MSR_IR) |
5109 (1ull << MSR_DR) |
5110 (1ull << MSR_PX) |
5111 (1ull << MSR_RI);
5112 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5113 pcc->excp_model = POWERPC_EXCP_BOOKE;
5114 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5115 /* FIXME: figure out the correct flag for e500mc */
5116 pcc->bfd_mach = bfd_mach_ppc_e500;
5117 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
5118 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5119 }
5120
5121 #ifdef TARGET_PPC64
5122 static void init_proc_e5500(CPUPPCState *env)
5123 {
5124 init_proc_e500(env, fsl_e5500);
5125 }
5126
5127 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
5128 {
5129 DeviceClass *dc = DEVICE_CLASS(oc);
5130 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5131
5132 dc->desc = "e5500 core";
5133 pcc->init_proc = init_proc_e5500;
5134 pcc->check_pow = check_pow_none;
5135 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
5136 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
5137 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5138 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5139 PPC_FLOAT | PPC_FLOAT_FRES |
5140 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
5141 PPC_FLOAT_STFIWX | PPC_WAIT |
5142 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
5143 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
5144 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | \
5145 PPC2_FP_CVT_S64;
5146 pcc->msr_mask = (1ull << MSR_CM) |
5147 (1ull << MSR_GS) |
5148 (1ull << MSR_UCLE) |
5149 (1ull << MSR_CE) |
5150 (1ull << MSR_EE) |
5151 (1ull << MSR_PR) |
5152 (1ull << MSR_FP) |
5153 (1ull << MSR_ME) |
5154 (1ull << MSR_FE0) |
5155 (1ull << MSR_DE) |
5156 (1ull << MSR_FE1) |
5157 (1ull << MSR_IR) |
5158 (1ull << MSR_DR) |
5159 (1ull << MSR_PX) |
5160 (1ull << MSR_RI);
5161 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5162 pcc->excp_model = POWERPC_EXCP_BOOKE;
5163 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5164 /* FIXME: figure out the correct flag for e5500 */
5165 pcc->bfd_mach = bfd_mach_ppc_e500;
5166 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
5167 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5168 }
5169 #endif
5170
5171 /* Non-embedded PowerPC */
5172
5173 /* POWER : same as 601, without mfmsr, mfsr */
5174 POWERPC_FAMILY(POWER)(ObjectClass *oc, void *data)
5175 {
5176 DeviceClass *dc = DEVICE_CLASS(oc);
5177 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5178
5179 dc->desc = "POWER";
5180 /* pcc->insns_flags = XXX_TODO; */
5181 /* POWER RSC (from RAD6000) */
5182 pcc->msr_mask = (1ull << MSR_EE) |
5183 (1ull << MSR_PR) |
5184 (1ull << MSR_FP) |
5185 (1ull << MSR_ME) |
5186 (1ull << MSR_FE0) |
5187 (1ull << MSR_SE) |
5188 (1ull << MSR_DE) |
5189 (1ull << MSR_AL) |
5190 (1ull << MSR_EP) |
5191 (1ull << MSR_IR) |
5192 (1ull << MSR_DR);
5193 }
5194
5195 #define POWERPC_MSRR_601 (0x0000000000001040ULL)
5196
5197 static void init_proc_601 (CPUPPCState *env)
5198 {
5199 gen_spr_ne_601(env);
5200 gen_spr_601(env);
5201 /* Hardware implementation registers */
5202 /* XXX : not implemented */
5203 spr_register(env, SPR_HID0, "HID0",
5204 SPR_NOACCESS, SPR_NOACCESS,
5205 &spr_read_generic, &spr_write_hid0_601,
5206 0x80010080);
5207 /* XXX : not implemented */
5208 spr_register(env, SPR_HID1, "HID1",
5209 SPR_NOACCESS, SPR_NOACCESS,
5210 &spr_read_generic, &spr_write_generic,
5211 0x00000000);
5212 /* XXX : not implemented */
5213 spr_register(env, SPR_601_HID2, "HID2",
5214 SPR_NOACCESS, SPR_NOACCESS,
5215 &spr_read_generic, &spr_write_generic,
5216 0x00000000);
5217 /* XXX : not implemented */
5218 spr_register(env, SPR_601_HID5, "HID5",
5219 SPR_NOACCESS, SPR_NOACCESS,
5220 &spr_read_generic, &spr_write_generic,
5221 0x00000000);
5222 /* Memory management */
5223 init_excp_601(env);
5224 /* XXX: beware that dcache line size is 64
5225 * but dcbz uses 32 bytes "sectors"
5226 * XXX: this breaks clcs instruction !
5227 */
5228 env->dcache_line_size = 32;
5229 env->icache_line_size = 64;
5230 /* Allocate hardware IRQ controller */
5231 ppc6xx_irq_init(ppc_env_get_cpu(env));
5232 }
5233
5234 POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
5235 {
5236 DeviceClass *dc = DEVICE_CLASS(oc);
5237 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5238
5239 dc->desc = "PowerPC 601";
5240 pcc->init_proc = init_proc_601;
5241 pcc->check_pow = check_pow_none;
5242 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
5243 PPC_FLOAT |
5244 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5245 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
5246 PPC_SEGMENT | PPC_EXTERN;
5247 pcc->msr_mask = (1ull << MSR_EE) |
5248 (1ull << MSR_PR) |
5249 (1ull << MSR_FP) |
5250 (1ull << MSR_ME) |
5251 (1ull << MSR_FE0) |
5252 (1ull << MSR_SE) |
5253 (1ull << MSR_FE1) |
5254 (1ull << MSR_EP) |
5255 (1ull << MSR_IR) |
5256 (1ull << MSR_DR);
5257 pcc->mmu_model = POWERPC_MMU_601;
5258 #if defined(CONFIG_SOFTMMU)
5259 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5260 #endif
5261 pcc->excp_model = POWERPC_EXCP_601;
5262 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5263 pcc->bfd_mach = bfd_mach_ppc_601;
5264 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
5265 }
5266
5267 #define POWERPC_MSRR_601v (0x0000000000001040ULL)
5268
5269 static void init_proc_601v (CPUPPCState *env)
5270 {
5271 init_proc_601(env);
5272 /* XXX : not implemented */
5273 spr_register(env, SPR_601_HID15, "HID15",
5274 SPR_NOACCESS, SPR_NOACCESS,
5275 &spr_read_generic, &spr_write_generic,
5276 0x00000000);
5277 }
5278
5279 POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
5280 {
5281 DeviceClass *dc = DEVICE_CLASS(oc);
5282 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5283
5284 dc->desc = "PowerPC 601v";
5285 pcc->init_proc = init_proc_601v;
5286 pcc->check_pow = check_pow_none;
5287 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
5288 PPC_FLOAT |
5289 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5290 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
5291 PPC_SEGMENT | PPC_EXTERN;
5292 pcc->msr_mask = (1ull << MSR_EE) |
5293 (1ull << MSR_PR) |
5294 (1ull << MSR_FP) |
5295 (1ull << MSR_ME) |
5296 (1ull << MSR_FE0) |
5297 (1ull << MSR_SE) |
5298 (1ull << MSR_FE1) |
5299 (1ull << MSR_EP) |
5300 (1ull << MSR_IR) |
5301 (1ull << MSR_DR);
5302 pcc->mmu_model = POWERPC_MMU_601;
5303 #if defined(CONFIG_SOFTMMU)
5304 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5305 #endif
5306 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5307 pcc->bfd_mach = bfd_mach_ppc_601;
5308 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
5309 }
5310
5311 static void init_proc_602 (CPUPPCState *env)
5312 {
5313 gen_spr_ne_601(env);
5314 gen_spr_602(env);
5315 /* Time base */
5316 gen_tbl(env);
5317 /* hardware implementation registers */
5318 /* XXX : not implemented */
5319 spr_register(env, SPR_HID0, "HID0",
5320 SPR_NOACCESS, SPR_NOACCESS,
5321 &spr_read_generic, &spr_write_generic,
5322 0x00000000);
5323 /* XXX : not implemented */
5324 spr_register(env, SPR_HID1, "HID1",
5325 SPR_NOACCESS, SPR_NOACCESS,
5326 &spr_read_generic, &spr_write_generic,
5327 0x00000000);
5328 /* Memory management */
5329 gen_low_BATs(env);
5330 gen_6xx_7xx_soft_tlb(env, 64, 2);
5331 init_excp_602(env);
5332 env->dcache_line_size = 32;
5333 env->icache_line_size = 32;
5334 /* Allocate hardware IRQ controller */
5335 ppc6xx_irq_init(ppc_env_get_cpu(env));
5336 }
5337
5338 POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
5339 {
5340 DeviceClass *dc = DEVICE_CLASS(oc);
5341 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5342
5343 dc->desc = "PowerPC 602";
5344 pcc->init_proc = init_proc_602;
5345 pcc->check_pow = check_pow_hid0;
5346 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5347 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5348 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5349 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5350 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5351 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC |
5352 PPC_SEGMENT | PPC_602_SPEC;
5353 pcc->msr_mask = (1ull << MSR_VSX) |
5354 (1ull << MSR_SA) |
5355 (1ull << MSR_POW) |
5356 (1ull << MSR_TGPR) |
5357 (1ull << MSR_ILE) |
5358 (1ull << MSR_EE) |
5359 (1ull << MSR_PR) |
5360 (1ull << MSR_FP) |
5361 (1ull << MSR_ME) |
5362 (1ull << MSR_FE0) |
5363 (1ull << MSR_SE) |
5364 (1ull << MSR_DE) |
5365 (1ull << MSR_FE1) |
5366 (1ull << MSR_EP) |
5367 (1ull << MSR_IR) |
5368 (1ull << MSR_DR) |
5369 (1ull << MSR_RI) |
5370 (1ull << MSR_LE);
5371 /* XXX: 602 MMU is quite specific. Should add a special case */
5372 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5373 pcc->excp_model = POWERPC_EXCP_602;
5374 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5375 pcc->bfd_mach = bfd_mach_ppc_602;
5376 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5377 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5378 }
5379
5380 static void init_proc_603 (CPUPPCState *env)
5381 {
5382 gen_spr_ne_601(env);
5383 gen_spr_603(env);
5384 /* Time base */
5385 gen_tbl(env);
5386 /* hardware implementation registers */
5387 /* XXX : not implemented */
5388 spr_register(env, SPR_HID0, "HID0",
5389 SPR_NOACCESS, SPR_NOACCESS,
5390 &spr_read_generic, &spr_write_generic,
5391 0x00000000);
5392 /* XXX : not implemented */
5393 spr_register(env, SPR_HID1, "HID1",
5394 SPR_NOACCESS, SPR_NOACCESS,
5395 &spr_read_generic, &spr_write_generic,
5396 0x00000000);
5397 /* Memory management */
5398 gen_low_BATs(env);
5399 gen_6xx_7xx_soft_tlb(env, 64, 2);
5400 init_excp_603(env);
5401 env->dcache_line_size = 32;
5402 env->icache_line_size = 32;
5403 /* Allocate hardware IRQ controller */
5404 ppc6xx_irq_init(ppc_env_get_cpu(env));
5405 }
5406
5407 POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
5408 {
5409 DeviceClass *dc = DEVICE_CLASS(oc);
5410 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5411
5412 dc->desc = "PowerPC 603";
5413 pcc->init_proc = init_proc_603;
5414 pcc->check_pow = check_pow_hid0;
5415 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5416 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5417 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5418 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5419 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5420 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5421 PPC_SEGMENT | PPC_EXTERN;
5422 pcc->msr_mask = (1ull << MSR_POW) |
5423 (1ull << MSR_TGPR) |
5424 (1ull << MSR_ILE) |
5425 (1ull << MSR_EE) |
5426 (1ull << MSR_PR) |
5427 (1ull << MSR_FP) |
5428 (1ull << MSR_ME) |
5429 (1ull << MSR_FE0) |
5430 (1ull << MSR_SE) |
5431 (1ull << MSR_DE) |
5432 (1ull << MSR_FE1) |
5433 (1ull << MSR_EP) |
5434 (1ull << MSR_IR) |
5435 (1ull << MSR_DR) |
5436 (1ull << MSR_RI) |
5437 (1ull << MSR_LE);
5438 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5439 pcc->excp_model = POWERPC_EXCP_603;
5440 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5441 pcc->bfd_mach = bfd_mach_ppc_603;
5442 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5443 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5444 }
5445
5446 static void init_proc_603E (CPUPPCState *env)
5447 {
5448 gen_spr_ne_601(env);
5449 gen_spr_603(env);
5450 /* Time base */
5451 gen_tbl(env);
5452 /* hardware implementation registers */
5453 /* XXX : not implemented */
5454 spr_register(env, SPR_HID0, "HID0",
5455 SPR_NOACCESS, SPR_NOACCESS,
5456 &spr_read_generic, &spr_write_generic,
5457 0x00000000);
5458 /* XXX : not implemented */
5459 spr_register(env, SPR_HID1, "HID1",
5460 SPR_NOACCESS, SPR_NOACCESS,
5461 &spr_read_generic, &spr_write_generic,
5462 0x00000000);
5463 /* Memory management */
5464 gen_low_BATs(env);
5465 gen_6xx_7xx_soft_tlb(env, 64, 2);
5466 init_excp_603(env);
5467 env->dcache_line_size = 32;
5468 env->icache_line_size = 32;
5469 /* Allocate hardware IRQ controller */
5470 ppc6xx_irq_init(ppc_env_get_cpu(env));
5471 }
5472
5473 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
5474 {
5475 DeviceClass *dc = DEVICE_CLASS(oc);
5476 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5477
5478 dc->desc = "PowerPC 603e";
5479 pcc->init_proc = init_proc_603E;
5480 pcc->check_pow = check_pow_hid0;
5481 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5482 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5483 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5484 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5485 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5486 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5487 PPC_SEGMENT | PPC_EXTERN;
5488 pcc->msr_mask = (1ull << MSR_POW) |
5489 (1ull << MSR_TGPR) |
5490 (1ull << MSR_ILE) |
5491 (1ull << MSR_EE) |
5492 (1ull << MSR_PR) |
5493 (1ull << MSR_FP) |
5494 (1ull << MSR_ME) |
5495 (1ull << MSR_FE0) |
5496 (1ull << MSR_SE) |
5497 (1ull << MSR_DE) |
5498 (1ull << MSR_FE1) |
5499 (1ull << MSR_EP) |
5500 (1ull << MSR_IR) |
5501 (1ull << MSR_DR) |
5502 (1ull << MSR_RI) |
5503 (1ull << MSR_LE);
5504 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5505 pcc->excp_model = POWERPC_EXCP_603E;
5506 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5507 pcc->bfd_mach = bfd_mach_ppc_ec603e;
5508 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5509 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5510 }
5511
5512 static void init_proc_604 (CPUPPCState *env)
5513 {
5514 gen_spr_ne_601(env);
5515 gen_spr_604(env);
5516 /* Time base */
5517 gen_tbl(env);
5518 /* Hardware implementation registers */
5519 /* XXX : not implemented */
5520 spr_register(env, SPR_HID0, "HID0",
5521 SPR_NOACCESS, SPR_NOACCESS,
5522 &spr_read_generic, &spr_write_generic,
5523 0x00000000);
5524 /* Memory management */
5525 gen_low_BATs(env);
5526 init_excp_604(env);
5527 env->dcache_line_size = 32;
5528 env->icache_line_size = 32;
5529 /* Allocate hardware IRQ controller */
5530 ppc6xx_irq_init(ppc_env_get_cpu(env));
5531 }
5532
5533 POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
5534 {
5535 DeviceClass *dc = DEVICE_CLASS(oc);
5536 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5537
5538 dc->desc = "PowerPC 604";
5539 pcc->init_proc = init_proc_604;
5540 pcc->check_pow = check_pow_nocheck;
5541 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5542 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5543 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5544 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5545 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5546 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5547 PPC_SEGMENT | PPC_EXTERN;
5548 pcc->msr_mask = (1ull << MSR_POW) |
5549 (1ull << MSR_ILE) |
5550 (1ull << MSR_EE) |
5551 (1ull << MSR_PR) |
5552 (1ull << MSR_FP) |
5553 (1ull << MSR_ME) |
5554 (1ull << MSR_FE0) |
5555 (1ull << MSR_SE) |
5556 (1ull << MSR_DE) |
5557 (1ull << MSR_FE1) |
5558 (1ull << MSR_EP) |
5559 (1ull << MSR_IR) |
5560 (1ull << MSR_DR) |
5561 (1ull << MSR_PMM) |
5562 (1ull << MSR_RI) |
5563 (1ull << MSR_LE);
5564 pcc->mmu_model = POWERPC_MMU_32B;
5565 #if defined(CONFIG_SOFTMMU)
5566 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5567 #endif
5568 pcc->excp_model = POWERPC_EXCP_604;
5569 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5570 pcc->bfd_mach = bfd_mach_ppc_604;
5571 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5572 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5573 }
5574
5575 static void init_proc_604E (CPUPPCState *env)
5576 {
5577 gen_spr_ne_601(env);
5578 gen_spr_604(env);
5579 /* XXX : not implemented */
5580 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
5581 SPR_NOACCESS, SPR_NOACCESS,
5582 &spr_read_generic, &spr_write_generic,
5583 0x00000000);
5584 /* XXX : not implemented */
5585 spr_register(env, SPR_7XX_PMC3, "PMC3",
5586 SPR_NOACCESS, SPR_NOACCESS,
5587 &spr_read_generic, &spr_write_generic,
5588 0x00000000);
5589 /* XXX : not implemented */
5590 spr_register(env, SPR_7XX_PMC4, "PMC4",
5591 SPR_NOACCESS, SPR_NOACCESS,
5592 &spr_read_generic, &spr_write_generic,
5593 0x00000000);
5594 /* Time base */
5595 gen_tbl(env);
5596 /* Hardware implementation registers */
5597 /* XXX : not implemented */
5598 spr_register(env, SPR_HID0, "HID0",
5599 SPR_NOACCESS, SPR_NOACCESS,
5600 &spr_read_generic, &spr_write_generic,
5601 0x00000000);
5602 /* XXX : not implemented */
5603 spr_register(env, SPR_HID1, "HID1",
5604 SPR_NOACCESS, SPR_NOACCESS,
5605 &spr_read_generic, &spr_write_generic,
5606 0x00000000);
5607 /* Memory management */
5608 gen_low_BATs(env);
5609 init_excp_604(env);
5610 env->dcache_line_size = 32;
5611 env->icache_line_size = 32;
5612 /* Allocate hardware IRQ controller */
5613 ppc6xx_irq_init(ppc_env_get_cpu(env));
5614 }
5615
5616 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
5617 {
5618 DeviceClass *dc = DEVICE_CLASS(oc);
5619 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5620
5621 dc->desc = "PowerPC 604E";
5622 pcc->init_proc = init_proc_604E;
5623 pcc->check_pow = check_pow_nocheck;
5624 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5625 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5626 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5627 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5628 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5629 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5630 PPC_SEGMENT | PPC_EXTERN;
5631 pcc->msr_mask = (1ull << MSR_POW) |
5632 (1ull << MSR_ILE) |
5633 (1ull << MSR_EE) |
5634 (1ull << MSR_PR) |
5635 (1ull << MSR_FP) |
5636 (1ull << MSR_ME) |
5637 (1ull << MSR_FE0) |
5638 (1ull << MSR_SE) |
5639 (1ull << MSR_DE) |
5640 (1ull << MSR_FE1) |
5641 (1ull << MSR_EP) |
5642 (1ull << MSR_IR) |
5643 (1ull << MSR_DR) |
5644 (1ull << MSR_PMM) |
5645 (1ull << MSR_RI) |
5646 (1ull << MSR_LE);
5647 pcc->mmu_model = POWERPC_MMU_32B;
5648 #if defined(CONFIG_SOFTMMU)
5649 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5650 #endif
5651 pcc->excp_model = POWERPC_EXCP_604;
5652 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5653 pcc->bfd_mach = bfd_mach_ppc_604;
5654 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5655 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5656 }
5657
5658 static void init_proc_740 (CPUPPCState *env)
5659 {
5660 gen_spr_ne_601(env);
5661 gen_spr_7xx(env);
5662 /* Time base */
5663 gen_tbl(env);
5664 /* Thermal management */
5665 gen_spr_thrm(env);
5666 /* Hardware implementation registers */
5667 /* XXX : not implemented */
5668 spr_register(env, SPR_HID0, "HID0",
5669 SPR_NOACCESS, SPR_NOACCESS,
5670 &spr_read_generic, &spr_write_generic,
5671 0x00000000);
5672 /* XXX : not implemented */
5673 spr_register(env, SPR_HID1, "HID1",
5674 SPR_NOACCESS, SPR_NOACCESS,
5675 &spr_read_generic, &spr_write_generic,
5676 0x00000000);
5677 /* Memory management */
5678 gen_low_BATs(env);
5679 init_excp_7x0(env);
5680 env->dcache_line_size = 32;
5681 env->icache_line_size = 32;
5682 /* Allocate hardware IRQ controller */
5683 ppc6xx_irq_init(ppc_env_get_cpu(env));
5684 }
5685
5686 POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
5687 {
5688 DeviceClass *dc = DEVICE_CLASS(oc);
5689 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5690
5691 dc->desc = "PowerPC 740";
5692 pcc->init_proc = init_proc_740;
5693 pcc->check_pow = check_pow_hid0;
5694 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5695 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5696 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5697 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5698 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5699 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5700 PPC_SEGMENT | PPC_EXTERN;
5701 pcc->msr_mask = (1ull << MSR_POW) |
5702 (1ull << MSR_ILE) |
5703 (1ull << MSR_EE) |
5704 (1ull << MSR_PR) |
5705 (1ull << MSR_FP) |
5706 (1ull << MSR_ME) |
5707 (1ull << MSR_FE0) |
5708 (1ull << MSR_SE) |
5709 (1ull << MSR_DE) |
5710 (1ull << MSR_FE1) |
5711 (1ull << MSR_EP) |
5712 (1ull << MSR_IR) |
5713 (1ull << MSR_DR) |
5714 (1ull << MSR_PMM) |
5715 (1ull << MSR_RI) |
5716 (1ull << MSR_LE);
5717 pcc->mmu_model = POWERPC_MMU_32B;
5718 #if defined(CONFIG_SOFTMMU)
5719 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5720 #endif
5721 pcc->excp_model = POWERPC_EXCP_7x0;
5722 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5723 pcc->bfd_mach = bfd_mach_ppc_750;
5724 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5725 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5726 }
5727
5728 static void init_proc_750 (CPUPPCState *env)
5729 {
5730 gen_spr_ne_601(env);
5731 gen_spr_7xx(env);
5732 /* XXX : not implemented */
5733 spr_register(env, SPR_L2CR, "L2CR",
5734 SPR_NOACCESS, SPR_NOACCESS,
5735 &spr_read_generic, spr_access_nop,
5736 0x00000000);
5737 /* Time base */
5738 gen_tbl(env);
5739 /* Thermal management */
5740 gen_spr_thrm(env);
5741 /* Hardware implementation registers */
5742 /* XXX : not implemented */
5743 spr_register(env, SPR_HID0, "HID0",
5744 SPR_NOACCESS, SPR_NOACCESS,
5745 &spr_read_generic, &spr_write_generic,
5746 0x00000000);
5747 /* XXX : not implemented */
5748 spr_register(env, SPR_HID1, "HID1",
5749 SPR_NOACCESS, SPR_NOACCESS,
5750 &spr_read_generic, &spr_write_generic,
5751 0x00000000);
5752 /* Memory management */
5753 gen_low_BATs(env);
5754 /* XXX: high BATs are also present but are known to be bugged on
5755 * die version 1.x
5756 */
5757 init_excp_7x0(env);
5758 env->dcache_line_size = 32;
5759 env->icache_line_size = 32;
5760 /* Allocate hardware IRQ controller */
5761 ppc6xx_irq_init(ppc_env_get_cpu(env));
5762 }
5763
5764 POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
5765 {
5766 DeviceClass *dc = DEVICE_CLASS(oc);
5767 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5768
5769 dc->desc = "PowerPC 750";
5770 pcc->init_proc = init_proc_750;
5771 pcc->check_pow = check_pow_hid0;
5772 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5773 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5774 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5775 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5776 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5777 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5778 PPC_SEGMENT | PPC_EXTERN;
5779 pcc->msr_mask = (1ull << MSR_POW) |
5780 (1ull << MSR_ILE) |
5781 (1ull << MSR_EE) |
5782 (1ull << MSR_PR) |
5783 (1ull << MSR_FP) |
5784 (1ull << MSR_ME) |
5785 (1ull << MSR_FE0) |
5786 (1ull << MSR_SE) |
5787 (1ull << MSR_DE) |
5788 (1ull << MSR_FE1) |
5789 (1ull << MSR_EP) |
5790 (1ull << MSR_IR) |
5791 (1ull << MSR_DR) |
5792 (1ull << MSR_PMM) |
5793 (1ull << MSR_RI) |
5794 (1ull << MSR_LE);
5795 pcc->mmu_model = POWERPC_MMU_32B;
5796 #if defined(CONFIG_SOFTMMU)
5797 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5798 #endif
5799 pcc->excp_model = POWERPC_EXCP_7x0;
5800 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5801 pcc->bfd_mach = bfd_mach_ppc_750;
5802 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5803 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5804 }
5805
5806 static void init_proc_750cl (CPUPPCState *env)
5807 {
5808 gen_spr_ne_601(env);
5809 gen_spr_7xx(env);
5810 /* XXX : not implemented */
5811 spr_register(env, SPR_L2CR, "L2CR",
5812 SPR_NOACCESS, SPR_NOACCESS,
5813 &spr_read_generic, spr_access_nop,
5814 0x00000000);
5815 /* Time base */
5816 gen_tbl(env);
5817 /* Thermal management */
5818 /* Those registers are fake on 750CL */
5819 spr_register(env, SPR_THRM1, "THRM1",
5820 SPR_NOACCESS, SPR_NOACCESS,
5821 &spr_read_generic, &spr_write_generic,
5822 0x00000000);
5823 spr_register(env, SPR_THRM2, "THRM2",
5824 SPR_NOACCESS, SPR_NOACCESS,
5825 &spr_read_generic, &spr_write_generic,
5826 0x00000000);
5827 spr_register(env, SPR_THRM3, "THRM3",
5828 SPR_NOACCESS, SPR_NOACCESS,
5829 &spr_read_generic, &spr_write_generic,
5830 0x00000000);
5831 /* XXX: not implemented */
5832 spr_register(env, SPR_750_TDCL, "TDCL",
5833 SPR_NOACCESS, SPR_NOACCESS,
5834 &spr_read_generic, &spr_write_generic,
5835 0x00000000);
5836 spr_register(env, SPR_750_TDCH, "TDCH",
5837 SPR_NOACCESS, SPR_NOACCESS,
5838 &spr_read_generic, &spr_write_generic,
5839 0x00000000);
5840 /* DMA */
5841 /* XXX : not implemented */
5842 spr_register(env, SPR_750_WPAR, "WPAR",
5843 SPR_NOACCESS, SPR_NOACCESS,
5844 &spr_read_generic, &spr_write_generic,
5845 0x00000000);
5846 spr_register(env, SPR_750_DMAL, "DMAL",
5847 SPR_NOACCESS, SPR_NOACCESS,
5848 &spr_read_generic, &spr_write_generic,
5849 0x00000000);
5850 spr_register(env, SPR_750_DMAU, "DMAU",
5851 SPR_NOACCESS, SPR_NOACCESS,
5852 &spr_read_generic, &spr_write_generic,
5853 0x00000000);
5854 /* Hardware implementation registers */
5855 /* XXX : not implemented */
5856 spr_register(env, SPR_HID0, "HID0",
5857 SPR_NOACCESS, SPR_NOACCESS,
5858 &spr_read_generic, &spr_write_generic,
5859 0x00000000);
5860 /* XXX : not implemented */
5861 spr_register(env, SPR_HID1, "HID1",
5862 SPR_NOACCESS, SPR_NOACCESS,
5863 &spr_read_generic, &spr_write_generic,
5864 0x00000000);
5865 /* XXX : not implemented */
5866 spr_register(env, SPR_750CL_HID2, "HID2",
5867 SPR_NOACCESS, SPR_NOACCESS,
5868 &spr_read_generic, &spr_write_generic,
5869 0x00000000);
5870 /* XXX : not implemented */
5871 spr_register(env, SPR_750CL_HID4, "HID4",
5872 SPR_NOACCESS, SPR_NOACCESS,
5873 &spr_read_generic, &spr_write_generic,
5874 0x00000000);
5875 /* Quantization registers */
5876 /* XXX : not implemented */
5877 spr_register(env, SPR_750_GQR0, "GQR0",
5878 SPR_NOACCESS, SPR_NOACCESS,
5879 &spr_read_generic, &spr_write_generic,
5880 0x00000000);
5881 /* XXX : not implemented */
5882 spr_register(env, SPR_750_GQR1, "GQR1",
5883 SPR_NOACCESS, SPR_NOACCESS,
5884 &spr_read_generic, &spr_write_generic,
5885 0x00000000);
5886 /* XXX : not implemented */
5887 spr_register(env, SPR_750_GQR2, "GQR2",
5888 SPR_NOACCESS, SPR_NOACCESS,
5889 &spr_read_generic, &spr_write_generic,
5890 0x00000000);
5891 /* XXX : not implemented */
5892 spr_register(env, SPR_750_GQR3, "GQR3",
5893 SPR_NOACCESS, SPR_NOACCESS,
5894 &spr_read_generic, &spr_write_generic,
5895 0x00000000);
5896 /* XXX : not implemented */
5897 spr_register(env, SPR_750_GQR4, "GQR4",
5898 SPR_NOACCESS, SPR_NOACCESS,
5899 &spr_read_generic, &spr_write_generic,
5900 0x00000000);
5901 /* XXX : not implemented */
5902 spr_register(env, SPR_750_GQR5, "GQR5",
5903 SPR_NOACCESS, SPR_NOACCESS,
5904 &spr_read_generic, &spr_write_generic,
5905 0x00000000);
5906 /* XXX : not implemented */
5907 spr_register(env, SPR_750_GQR6, "GQR6",
5908 SPR_NOACCESS, SPR_NOACCESS,
5909 &spr_read_generic, &spr_write_generic,
5910 0x00000000);
5911 /* XXX : not implemented */
5912 spr_register(env, SPR_750_GQR7, "GQR7",
5913 SPR_NOACCESS, SPR_NOACCESS,
5914 &spr_read_generic, &spr_write_generic,
5915 0x00000000);
5916 /* Memory management */
5917 gen_low_BATs(env);
5918 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5919 gen_high_BATs(env);
5920 init_excp_750cl(env);
5921 env->dcache_line_size = 32;
5922 env->icache_line_size = 32;
5923 /* Allocate hardware IRQ controller */
5924 ppc6xx_irq_init(ppc_env_get_cpu(env));
5925 }
5926
5927 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
5928 {
5929 DeviceClass *dc = DEVICE_CLASS(oc);
5930 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5931
5932 dc->desc = "PowerPC 750 CL";
5933 pcc->init_proc = init_proc_750cl;
5934 pcc->check_pow = check_pow_hid0;
5935 /* XXX: not implemented:
5936 * cache lock instructions:
5937 * dcbz_l
5938 * floating point paired instructions
5939 * psq_lux
5940 * psq_lx
5941 * psq_stux
5942 * psq_stx
5943 * ps_abs
5944 * ps_add
5945 * ps_cmpo0
5946 * ps_cmpo1
5947 * ps_cmpu0
5948 * ps_cmpu1
5949 * ps_div
5950 * ps_madd
5951 * ps_madds0
5952 * ps_madds1
5953 * ps_merge00
5954 * ps_merge01
5955 * ps_merge10
5956 * ps_merge11
5957 * ps_mr
5958 * ps_msub
5959 * ps_mul
5960 * ps_muls0
5961 * ps_muls1
5962 * ps_nabs
5963 * ps_neg
5964 * ps_nmadd
5965 * ps_nmsub
5966 * ps_res
5967 * ps_rsqrte
5968 * ps_sel
5969 * ps_sub
5970 * ps_sum0
5971 * ps_sum1
5972 */
5973 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5974 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5975 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5976 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5977 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5978 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5979 PPC_SEGMENT | PPC_EXTERN;
5980 pcc->msr_mask = (1ull << MSR_POW) |
5981 (1ull << MSR_ILE) |
5982 (1ull << MSR_EE) |
5983 (1ull << MSR_PR) |
5984 (1ull << MSR_FP) |
5985 (1ull << MSR_ME) |
5986 (1ull << MSR_FE0) |
5987 (1ull << MSR_SE) |
5988 (1ull << MSR_DE) |
5989 (1ull << MSR_FE1) |
5990 (1ull << MSR_EP) |
5991 (1ull << MSR_IR) |
5992 (1ull << MSR_DR) |
5993 (1ull << MSR_PMM) |
5994 (1ull << MSR_RI) |
5995 (1ull << MSR_LE);
5996 pcc->mmu_model = POWERPC_MMU_32B;
5997 #if defined(CONFIG_SOFTMMU)
5998 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5999 #endif
6000 pcc->excp_model = POWERPC_EXCP_7x0;
6001 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6002 pcc->bfd_mach = bfd_mach_ppc_750;
6003 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6004 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6005 }
6006
6007 static void init_proc_750cx (CPUPPCState *env)
6008 {
6009 gen_spr_ne_601(env);
6010 gen_spr_7xx(env);
6011 /* XXX : not implemented */
6012 spr_register(env, SPR_L2CR, "L2CR",
6013 SPR_NOACCESS, SPR_NOACCESS,
6014 &spr_read_generic, spr_access_nop,
6015 0x00000000);
6016 /* Time base */
6017 gen_tbl(env);
6018 /* Thermal management */
6019 gen_spr_thrm(env);
6020 /* This register is not implemented but is present for compatibility */
6021 spr_register(env, SPR_SDA, "SDA",
6022 SPR_NOACCESS, SPR_NOACCESS,
6023 &spr_read_generic, &spr_write_generic,
6024 0x00000000);
6025 /* Hardware implementation registers */
6026 /* XXX : not implemented */
6027 spr_register(env, SPR_HID0, "HID0",
6028 SPR_NOACCESS, SPR_NOACCESS,
6029 &spr_read_generic, &spr_write_generic,
6030 0x00000000);
6031 /* XXX : not implemented */
6032 spr_register(env, SPR_HID1, "HID1",
6033 SPR_NOACCESS, SPR_NOACCESS,
6034 &spr_read_generic, &spr_write_generic,
6035 0x00000000);
6036 /* Memory management */
6037 gen_low_BATs(env);
6038 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
6039 gen_high_BATs(env);
6040 init_excp_750cx(env);
6041 env->dcache_line_size = 32;
6042 env->icache_line_size = 32;
6043 /* Allocate hardware IRQ controller */
6044 ppc6xx_irq_init(ppc_env_get_cpu(env));
6045 }
6046
6047 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
6048 {
6049 DeviceClass *dc = DEVICE_CLASS(oc);
6050 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6051
6052 dc->desc = "PowerPC 750CX";
6053 pcc->init_proc = init_proc_750cx;
6054 pcc->check_pow = check_pow_hid0;
6055 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6056 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6057 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6058 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6059 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6060 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6061 PPC_SEGMENT | PPC_EXTERN;
6062 pcc->msr_mask = (1ull << MSR_POW) |
6063 (1ull << MSR_ILE) |
6064 (1ull << MSR_EE) |
6065 (1ull << MSR_PR) |
6066 (1ull << MSR_FP) |
6067 (1ull << MSR_ME) |
6068 (1ull << MSR_FE0) |
6069 (1ull << MSR_SE) |
6070 (1ull << MSR_DE) |
6071 (1ull << MSR_FE1) |
6072 (1ull << MSR_EP) |
6073 (1ull << MSR_IR) |
6074 (1ull << MSR_DR) |
6075 (1ull << MSR_PMM) |
6076 (1ull << MSR_RI) |
6077 (1ull << MSR_LE);
6078 pcc->mmu_model = POWERPC_MMU_32B;
6079 #if defined(CONFIG_SOFTMMU)
6080 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6081 #endif
6082 pcc->excp_model = POWERPC_EXCP_7x0;
6083 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6084 pcc->bfd_mach = bfd_mach_ppc_750;
6085 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6086 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6087 }
6088
6089 static void init_proc_750fx (CPUPPCState *env)
6090 {
6091 gen_spr_ne_601(env);
6092 gen_spr_7xx(env);
6093 /* XXX : not implemented */
6094 spr_register(env, SPR_L2CR, "L2CR",
6095 SPR_NOACCESS, SPR_NOACCESS,
6096 &spr_read_generic, spr_access_nop,
6097 0x00000000);
6098 /* Time base */
6099 gen_tbl(env);
6100 /* Thermal management */
6101 gen_spr_thrm(env);
6102 /* XXX : not implemented */
6103 spr_register(env, SPR_750_THRM4, "THRM4",
6104 SPR_NOACCESS, SPR_NOACCESS,
6105 &spr_read_generic, &spr_write_generic,
6106 0x00000000);
6107 /* Hardware implementation registers */
6108 /* XXX : not implemented */
6109 spr_register(env, SPR_HID0, "HID0",
6110 SPR_NOACCESS, SPR_NOACCESS,
6111 &spr_read_generic, &spr_write_generic,
6112 0x00000000);
6113 /* XXX : not implemented */
6114 spr_register(env, SPR_HID1, "HID1",
6115 SPR_NOACCESS, SPR_NOACCESS,
6116 &spr_read_generic, &spr_write_generic,
6117 0x00000000);
6118 /* XXX : not implemented */
6119 spr_register(env, SPR_750FX_HID2, "HID2",
6120 SPR_NOACCESS, SPR_NOACCESS,
6121 &spr_read_generic, &spr_write_generic,
6122 0x00000000);
6123 /* Memory management */
6124 gen_low_BATs(env);
6125 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
6126 gen_high_BATs(env);
6127 init_excp_7x0(env);
6128 env->dcache_line_size = 32;
6129 env->icache_line_size = 32;
6130 /* Allocate hardware IRQ controller */
6131 ppc6xx_irq_init(ppc_env_get_cpu(env));
6132 }
6133
6134 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
6135 {
6136 DeviceClass *dc = DEVICE_CLASS(oc);
6137 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6138
6139 dc->desc = "PowerPC 750FX";
6140 pcc->init_proc = init_proc_750fx;
6141 pcc->check_pow = check_pow_hid0;
6142 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6143 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6144 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6145 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6146 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6147 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6148 PPC_SEGMENT | PPC_EXTERN;
6149 pcc->msr_mask = (1ull << MSR_POW) |
6150 (1ull << MSR_ILE) |
6151 (1ull << MSR_EE) |
6152 (1ull << MSR_PR) |
6153 (1ull << MSR_FP) |
6154 (1ull << MSR_ME) |
6155 (1ull << MSR_FE0) |
6156 (1ull << MSR_SE) |
6157 (1ull << MSR_DE) |
6158 (1ull << MSR_FE1) |
6159 (1ull << MSR_EP) |
6160 (1ull << MSR_IR) |
6161 (1ull << MSR_DR) |
6162 (1ull << MSR_PMM) |
6163 (1ull << MSR_RI) |
6164 (1ull << MSR_LE);
6165 pcc->mmu_model = POWERPC_MMU_32B;
6166 #if defined(CONFIG_SOFTMMU)
6167 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6168 #endif
6169 pcc->excp_model = POWERPC_EXCP_7x0;
6170 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6171 pcc->bfd_mach = bfd_mach_ppc_750;
6172 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6173 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6174 }
6175
6176 static void init_proc_750gx (CPUPPCState *env)
6177 {
6178 gen_spr_ne_601(env);
6179 gen_spr_7xx(env);
6180 /* XXX : not implemented (XXX: different from 750fx) */
6181 spr_register(env, SPR_L2CR, "L2CR",
6182 SPR_NOACCESS, SPR_NOACCESS,
6183 &spr_read_generic, spr_access_nop,
6184 0x00000000);
6185 /* Time base */
6186 gen_tbl(env);
6187 /* Thermal management */
6188 gen_spr_thrm(env);
6189 /* XXX : not implemented */
6190 spr_register(env, SPR_750_THRM4, "THRM4",
6191 SPR_NOACCESS, SPR_NOACCESS,
6192 &spr_read_generic, &spr_write_generic,
6193 0x00000000);
6194 /* Hardware implementation registers */
6195 /* XXX : not implemented (XXX: different from 750fx) */
6196 spr_register(env, SPR_HID0, "HID0",
6197 SPR_NOACCESS, SPR_NOACCESS,
6198 &spr_read_generic, &spr_write_generic,
6199 0x00000000);
6200 /* XXX : not implemented */
6201 spr_register(env, SPR_HID1, "HID1",
6202 SPR_NOACCESS, SPR_NOACCESS,
6203 &spr_read_generic, &spr_write_generic,
6204 0x00000000);
6205 /* XXX : not implemented (XXX: different from 750fx) */
6206 spr_register(env, SPR_750FX_HID2, "HID2",
6207 SPR_NOACCESS, SPR_NOACCESS,
6208 &spr_read_generic, &spr_write_generic,
6209 0x00000000);
6210 /* Memory management */
6211 gen_low_BATs(env);
6212 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
6213 gen_high_BATs(env);
6214 init_excp_7x0(env);
6215 env->dcache_line_size = 32;
6216 env->icache_line_size = 32;
6217 /* Allocate hardware IRQ controller */
6218 ppc6xx_irq_init(ppc_env_get_cpu(env));
6219 }
6220
6221 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
6222 {
6223 DeviceClass *dc = DEVICE_CLASS(oc);
6224 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6225
6226 dc->desc = "PowerPC 750GX";
6227 pcc->init_proc = init_proc_750gx;
6228 pcc->check_pow = check_pow_hid0;
6229 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6230 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6231 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6232 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6233 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6234 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6235 PPC_SEGMENT | PPC_EXTERN;
6236 pcc->msr_mask = (1ull << MSR_POW) |
6237 (1ull << MSR_ILE) |
6238 (1ull << MSR_EE) |
6239 (1ull << MSR_PR) |
6240 (1ull << MSR_FP) |
6241 (1ull << MSR_ME) |
6242 (1ull << MSR_FE0) |
6243 (1ull << MSR_SE) |
6244 (1ull << MSR_DE) |
6245 (1ull << MSR_FE1) |
6246 (1ull << MSR_EP) |
6247 (1ull << MSR_IR) |
6248 (1ull << MSR_DR) |
6249 (1ull << MSR_PMM) |
6250 (1ull << MSR_RI) |
6251 (1ull << MSR_LE);
6252 pcc->mmu_model = POWERPC_MMU_32B;
6253 #if defined(CONFIG_SOFTMMU)
6254 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6255 #endif
6256 pcc->excp_model = POWERPC_EXCP_7x0;
6257 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6258 pcc->bfd_mach = bfd_mach_ppc_750;
6259 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6260 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6261 }
6262
6263 static void init_proc_745 (CPUPPCState *env)
6264 {
6265 gen_spr_ne_601(env);
6266 gen_spr_7xx(env);
6267 gen_spr_G2_755(env);
6268 /* Time base */
6269 gen_tbl(env);
6270 /* Thermal management */
6271 gen_spr_thrm(env);
6272 /* Hardware implementation registers */
6273 /* XXX : not implemented */
6274 spr_register(env, SPR_HID0, "HID0",
6275 SPR_NOACCESS, SPR_NOACCESS,
6276 &spr_read_generic, &spr_write_generic,
6277 0x00000000);
6278 /* XXX : not implemented */
6279 spr_register(env, SPR_HID1, "HID1",
6280 SPR_NOACCESS, SPR_NOACCESS,
6281 &spr_read_generic, &spr_write_generic,
6282 0x00000000);
6283 /* XXX : not implemented */
6284 spr_register(env, SPR_HID2, "HID2",
6285 SPR_NOACCESS, SPR_NOACCESS,
6286 &spr_read_generic, &spr_write_generic,
6287 0x00000000);
6288 /* Memory management */
6289 gen_low_BATs(env);
6290 gen_high_BATs(env);
6291 gen_6xx_7xx_soft_tlb(env, 64, 2);
6292 init_excp_7x5(env);
6293 env->dcache_line_size = 32;
6294 env->icache_line_size = 32;
6295 /* Allocate hardware IRQ controller */
6296 ppc6xx_irq_init(ppc_env_get_cpu(env));
6297 }
6298
6299 POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
6300 {
6301 DeviceClass *dc = DEVICE_CLASS(oc);
6302 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6303
6304 dc->desc = "PowerPC 745";
6305 pcc->init_proc = init_proc_745;
6306 pcc->check_pow = check_pow_hid0;
6307 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6308 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6309 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6310 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6311 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6312 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
6313 PPC_SEGMENT | PPC_EXTERN;
6314 pcc->msr_mask = (1ull << MSR_POW) |
6315 (1ull << MSR_ILE) |
6316 (1ull << MSR_EE) |
6317 (1ull << MSR_PR) |
6318 (1ull << MSR_FP) |
6319 (1ull << MSR_ME) |
6320 (1ull << MSR_FE0) |
6321 (1ull << MSR_SE) |
6322 (1ull << MSR_DE) |
6323 (1ull << MSR_FE1) |
6324 (1ull << MSR_EP) |
6325 (1ull << MSR_IR) |
6326 (1ull << MSR_DR) |
6327 (1ull << MSR_PMM) |
6328 (1ull << MSR_RI) |
6329 (1ull << MSR_LE);
6330 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
6331 pcc->excp_model = POWERPC_EXCP_7x5;
6332 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6333 pcc->bfd_mach = bfd_mach_ppc_750;
6334 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6335 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6336 }
6337
6338 static void init_proc_755 (CPUPPCState *env)
6339 {
6340 gen_spr_ne_601(env);
6341 gen_spr_7xx(env);
6342 gen_spr_G2_755(env);
6343 /* Time base */
6344 gen_tbl(env);
6345 /* L2 cache control */
6346 /* XXX : not implemented */
6347 spr_register(env, SPR_L2CR, "L2CR",
6348 SPR_NOACCESS, SPR_NOACCESS,
6349 &spr_read_generic, spr_access_nop,
6350 0x00000000);
6351 /* XXX : not implemented */
6352 spr_register(env, SPR_L2PMCR, "L2PMCR",
6353 SPR_NOACCESS, SPR_NOACCESS,
6354 &spr_read_generic, &spr_write_generic,
6355 0x00000000);
6356 /* Thermal management */
6357 gen_spr_thrm(env);
6358 /* Hardware implementation registers */
6359 /* XXX : not implemented */
6360 spr_register(env, SPR_HID0, "HID0",
6361 SPR_NOACCESS, SPR_NOACCESS,
6362 &spr_read_generic, &spr_write_generic,
6363 0x00000000);
6364 /* XXX : not implemented */
6365 spr_register(env, SPR_HID1, "HID1",
6366 SPR_NOACCESS, SPR_NOACCESS,
6367 &spr_read_generic, &spr_write_generic,
6368 0x00000000);
6369 /* XXX : not implemented */
6370 spr_register(env, SPR_HID2, "HID2",
6371 SPR_NOACCESS, SPR_NOACCESS,
6372 &spr_read_generic, &spr_write_generic,
6373 0x00000000);
6374 /* Memory management */
6375 gen_low_BATs(env);
6376 gen_high_BATs(env);
6377 gen_6xx_7xx_soft_tlb(env, 64, 2);
6378 init_excp_7x5(env);
6379 env->dcache_line_size = 32;
6380 env->icache_line_size = 32;
6381 /* Allocate hardware IRQ controller */
6382 ppc6xx_irq_init(ppc_env_get_cpu(env));
6383 }
6384
6385 POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
6386 {
6387 DeviceClass *dc = DEVICE_CLASS(oc);
6388 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6389
6390 dc->desc = "PowerPC 755";
6391 pcc->init_proc = init_proc_755;
6392 pcc->check_pow = check_pow_hid0;
6393 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6394 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6395 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6396 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6397 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6398 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
6399 PPC_SEGMENT | PPC_EXTERN;
6400 pcc->msr_mask = (1ull << MSR_POW) |
6401 (1ull << MSR_ILE) |
6402 (1ull << MSR_EE) |
6403 (1ull << MSR_PR) |
6404 (1ull << MSR_FP) |
6405 (1ull << MSR_ME) |
6406 (1ull << MSR_FE0) |
6407 (1ull << MSR_SE) |
6408 (1ull << MSR_DE) |
6409 (1ull << MSR_FE1) |
6410 (1ull << MSR_EP) |
6411 (1ull << MSR_IR) |
6412 (1ull << MSR_DR) |
6413 (1ull << MSR_PMM) |
6414 (1ull << MSR_RI) |
6415 (1ull << MSR_LE);
6416 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
6417 pcc->excp_model = POWERPC_EXCP_7x5;
6418 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6419 pcc->bfd_mach = bfd_mach_ppc_750;
6420 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6421 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6422 }
6423
6424 static void init_proc_7400 (CPUPPCState *env)
6425 {
6426 gen_spr_ne_601(env);
6427 gen_spr_7xx(env);
6428 /* Time base */
6429 gen_tbl(env);
6430 /* 74xx specific SPR */
6431 gen_spr_74xx(env);
6432 /* XXX : not implemented */
6433 spr_register(env, SPR_UBAMR, "UBAMR",
6434 &spr_read_ureg, SPR_NOACCESS,
6435 &spr_read_ureg, SPR_NOACCESS,
6436 0x00000000);
6437 /* XXX: this seems not implemented on all revisions. */
6438 /* XXX : not implemented */
6439 spr_register(env, SPR_MSSCR1, "MSSCR1",
6440 SPR_NOACCESS, SPR_NOACCESS,
6441 &spr_read_generic, &spr_write_generic,
6442 0x00000000);
6443 /* Thermal management */
6444 gen_spr_thrm(env);
6445 /* Memory management */
6446 gen_low_BATs(env);
6447 init_excp_7400(env);
6448 env->dcache_line_size = 32;
6449 env->icache_line_size = 32;
6450 /* Allocate hardware IRQ controller */
6451 ppc6xx_irq_init(ppc_env_get_cpu(env));
6452 }
6453
6454 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
6455 {
6456 DeviceClass *dc = DEVICE_CLASS(oc);
6457 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6458
6459 dc->desc = "PowerPC 7400 (aka G4)";
6460 pcc->init_proc = init_proc_7400;
6461 pcc->check_pow = check_pow_hid0;
6462 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6463 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6464 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6465 PPC_FLOAT_STFIWX |
6466 PPC_CACHE | PPC_CACHE_ICBI |
6467 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6468 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6469 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6470 PPC_MEM_TLBIA |
6471 PPC_SEGMENT | PPC_EXTERN |
6472 PPC_ALTIVEC;
6473 pcc->msr_mask = (1ull << MSR_VR) |
6474 (1ull << MSR_POW) |
6475 (1ull << MSR_ILE) |
6476 (1ull << MSR_EE) |
6477 (1ull << MSR_PR) |
6478 (1ull << MSR_FP) |
6479 (1ull << MSR_ME) |
6480 (1ull << MSR_FE0) |
6481 (1ull << MSR_SE) |
6482 (1ull << MSR_DE) |
6483 (1ull << MSR_FE1) |
6484 (1ull << MSR_EP) |
6485 (1ull << MSR_IR) |
6486 (1ull << MSR_DR) |
6487 (1ull << MSR_PMM) |
6488 (1ull << MSR_RI) |
6489 (1ull << MSR_LE);
6490 pcc->mmu_model = POWERPC_MMU_32B;
6491 #if defined(CONFIG_SOFTMMU)
6492 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6493 #endif
6494 pcc->excp_model = POWERPC_EXCP_74xx;
6495 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6496 pcc->bfd_mach = bfd_mach_ppc_7400;
6497 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6498 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6499 POWERPC_FLAG_BUS_CLK;
6500 }
6501
6502 static void init_proc_7410 (CPUPPCState *env)
6503 {
6504 gen_spr_ne_601(env);
6505 gen_spr_7xx(env);
6506 /* Time base */
6507 gen_tbl(env);
6508 /* 74xx specific SPR */
6509 gen_spr_74xx(env);
6510 /* XXX : not implemented */
6511 spr_register(env, SPR_UBAMR, "UBAMR",
6512 &spr_read_ureg, SPR_NOACCESS,
6513 &spr_read_ureg, SPR_NOACCESS,
6514 0x00000000);
6515 /* Thermal management */
6516 gen_spr_thrm(env);
6517 /* L2PMCR */
6518 /* XXX : not implemented */
6519 spr_register(env, SPR_L2PMCR, "L2PMCR",
6520 SPR_NOACCESS, SPR_NOACCESS,
6521 &spr_read_generic, &spr_write_generic,
6522 0x00000000);
6523 /* LDSTDB */
6524 /* XXX : not implemented */
6525 spr_register(env, SPR_LDSTDB, "LDSTDB",
6526 SPR_NOACCESS, SPR_NOACCESS,
6527 &spr_read_generic, &spr_write_generic,
6528 0x00000000);
6529 /* Memory management */
6530 gen_low_BATs(env);
6531 init_excp_7400(env);
6532 env->dcache_line_size = 32;
6533 env->icache_line_size = 32;
6534 /* Allocate hardware IRQ controller */
6535 ppc6xx_irq_init(ppc_env_get_cpu(env));
6536 }
6537
6538 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
6539 {
6540 DeviceClass *dc = DEVICE_CLASS(oc);
6541 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6542
6543 dc->desc = "PowerPC 7410 (aka G4)";
6544 pcc->init_proc = init_proc_7410;
6545 pcc->check_pow = check_pow_hid0;
6546 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6547 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6548 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6549 PPC_FLOAT_STFIWX |
6550 PPC_CACHE | PPC_CACHE_ICBI |
6551 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6552 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6553 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6554 PPC_MEM_TLBIA |
6555 PPC_SEGMENT | PPC_EXTERN |
6556 PPC_ALTIVEC;
6557 pcc->msr_mask = (1ull << MSR_VR) |
6558 (1ull << MSR_POW) |
6559 (1ull << MSR_ILE) |
6560 (1ull << MSR_EE) |
6561 (1ull << MSR_PR) |
6562 (1ull << MSR_FP) |
6563 (1ull << MSR_ME) |
6564 (1ull << MSR_FE0) |
6565 (1ull << MSR_SE) |
6566 (1ull << MSR_DE) |
6567 (1ull << MSR_FE1) |
6568 (1ull << MSR_EP) |
6569 (1ull << MSR_IR) |
6570 (1ull << MSR_DR) |
6571 (1ull << MSR_PMM) |
6572 (1ull << MSR_RI) |
6573 (1ull << MSR_LE);
6574 pcc->mmu_model = POWERPC_MMU_32B;
6575 #if defined(CONFIG_SOFTMMU)
6576 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6577 #endif
6578 pcc->excp_model = POWERPC_EXCP_74xx;
6579 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6580 pcc->bfd_mach = bfd_mach_ppc_7400;
6581 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6582 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6583 POWERPC_FLAG_BUS_CLK;
6584 }
6585
6586 static void init_proc_7440 (CPUPPCState *env)
6587 {
6588 gen_spr_ne_601(env);
6589 gen_spr_7xx(env);
6590 /* Time base */
6591 gen_tbl(env);
6592 /* 74xx specific SPR */
6593 gen_spr_74xx(env);
6594 /* XXX : not implemented */
6595 spr_register(env, SPR_UBAMR, "UBAMR",
6596 &spr_read_ureg, SPR_NOACCESS,
6597 &spr_read_ureg, SPR_NOACCESS,
6598 0x00000000);
6599 /* LDSTCR */
6600 /* XXX : not implemented */
6601 spr_register(env, SPR_LDSTCR, "LDSTCR",
6602 SPR_NOACCESS, SPR_NOACCESS,
6603 &spr_read_generic, &spr_write_generic,
6604 0x00000000);
6605 /* ICTRL */
6606 /* XXX : not implemented */
6607 spr_register(env, SPR_ICTRL, "ICTRL",
6608 SPR_NOACCESS, SPR_NOACCESS,
6609 &spr_read_generic, &spr_write_generic,
6610 0x00000000);
6611 /* MSSSR0 */
6612 /* XXX : not implemented */
6613 spr_register(env, SPR_MSSSR0, "MSSSR0",
6614 SPR_NOACCESS, SPR_NOACCESS,
6615 &spr_read_generic, &spr_write_generic,
6616 0x00000000);
6617 /* PMC */
6618 /* XXX : not implemented */
6619 spr_register(env, SPR_7XX_PMC5, "PMC5",
6620 SPR_NOACCESS, SPR_NOACCESS,
6621 &spr_read_generic, &spr_write_generic,
6622 0x00000000);
6623 /* XXX : not implemented */
6624 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6625 &spr_read_ureg, SPR_NOACCESS,
6626 &spr_read_ureg, SPR_NOACCESS,
6627 0x00000000);
6628 /* XXX : not implemented */
6629 spr_register(env, SPR_7XX_PMC6, "PMC6",
6630 SPR_NOACCESS, SPR_NOACCESS,
6631 &spr_read_generic, &spr_write_generic,
6632 0x00000000);
6633 /* XXX : not implemented */
6634 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6635 &spr_read_ureg, SPR_NOACCESS,
6636 &spr_read_ureg, SPR_NOACCESS,
6637 0x00000000);
6638 /* Memory management */
6639 gen_low_BATs(env);
6640 gen_74xx_soft_tlb(env, 128, 2);
6641 init_excp_7450(env);
6642 env->dcache_line_size = 32;
6643 env->icache_line_size = 32;
6644 /* Allocate hardware IRQ controller */
6645 ppc6xx_irq_init(ppc_env_get_cpu(env));
6646 }
6647
6648 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
6649 {
6650 DeviceClass *dc = DEVICE_CLASS(oc);
6651 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6652
6653 dc->desc = "PowerPC 7440 (aka G4)";
6654 pcc->init_proc = init_proc_7440;
6655 pcc->check_pow = check_pow_hid0_74xx;
6656 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6657 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6658 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6659 PPC_FLOAT_STFIWX |
6660 PPC_CACHE | PPC_CACHE_ICBI |
6661 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6662 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6663 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6664 PPC_MEM_TLBIA | PPC_74xx_TLB |
6665 PPC_SEGMENT | PPC_EXTERN |
6666 PPC_ALTIVEC;
6667 pcc->msr_mask = (1ull << MSR_VR) |
6668 (1ull << MSR_POW) |
6669 (1ull << MSR_ILE) |
6670 (1ull << MSR_EE) |
6671 (1ull << MSR_PR) |
6672 (1ull << MSR_FP) |
6673 (1ull << MSR_ME) |
6674 (1ull << MSR_FE0) |
6675 (1ull << MSR_SE) |
6676 (1ull << MSR_DE) |
6677 (1ull << MSR_FE1) |
6678 (1ull << MSR_EP) |
6679 (1ull << MSR_IR) |
6680 (1ull << MSR_DR) |
6681 (1ull << MSR_PMM) |
6682 (1ull << MSR_RI) |
6683 (1ull << MSR_LE);
6684 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6685 pcc->excp_model = POWERPC_EXCP_74xx;
6686 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6687 pcc->bfd_mach = bfd_mach_ppc_7400;
6688 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6689 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6690 POWERPC_FLAG_BUS_CLK;
6691 }
6692
6693 static void init_proc_7450 (CPUPPCState *env)
6694 {
6695 gen_spr_ne_601(env);
6696 gen_spr_7xx(env);
6697 /* Time base */
6698 gen_tbl(env);
6699 /* 74xx specific SPR */
6700 gen_spr_74xx(env);
6701 /* Level 3 cache control */
6702 gen_l3_ctrl(env);
6703 /* L3ITCR1 */
6704 /* XXX : not implemented */
6705 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6706 SPR_NOACCESS, SPR_NOACCESS,
6707 &spr_read_generic, &spr_write_generic,
6708 0x00000000);
6709 /* L3ITCR2 */
6710 /* XXX : not implemented */
6711 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6712 SPR_NOACCESS, SPR_NOACCESS,
6713 &spr_read_generic, &spr_write_generic,
6714 0x00000000);
6715 /* L3ITCR3 */
6716 /* XXX : not implemented */
6717 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6718 SPR_NOACCESS, SPR_NOACCESS,
6719 &spr_read_generic, &spr_write_generic,
6720 0x00000000);
6721 /* L3OHCR */
6722 /* XXX : not implemented */
6723 spr_register(env, SPR_L3OHCR, "L3OHCR",
6724 SPR_NOACCESS, SPR_NOACCESS,
6725 &spr_read_generic, &spr_write_generic,
6726 0x00000000);
6727 /* XXX : not implemented */
6728 spr_register(env, SPR_UBAMR, "UBAMR",
6729 &spr_read_ureg, SPR_NOACCESS,
6730 &spr_read_ureg, SPR_NOACCESS,
6731 0x00000000);
6732 /* LDSTCR */
6733 /* XXX : not implemented */
6734 spr_register(env, SPR_LDSTCR, "LDSTCR",
6735 SPR_NOACCESS, SPR_NOACCESS,
6736 &spr_read_generic, &spr_write_generic,
6737 0x00000000);
6738 /* ICTRL */
6739 /* XXX : not implemented */
6740 spr_register(env, SPR_ICTRL, "ICTRL",
6741 SPR_NOACCESS, SPR_NOACCESS,
6742 &spr_read_generic, &spr_write_generic,
6743 0x00000000);
6744 /* MSSSR0 */
6745 /* XXX : not implemented */
6746 spr_register(env, SPR_MSSSR0, "MSSSR0",
6747 SPR_NOACCESS, SPR_NOACCESS,
6748 &spr_read_generic, &spr_write_generic,
6749 0x00000000);
6750 /* PMC */
6751 /* XXX : not implemented */
6752 spr_register(env, SPR_7XX_PMC5, "PMC5",
6753 SPR_NOACCESS, SPR_NOACCESS,
6754 &spr_read_generic, &spr_write_generic,
6755 0x00000000);
6756 /* XXX : not implemented */
6757 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6758 &spr_read_ureg, SPR_NOACCESS,
6759 &spr_read_ureg, SPR_NOACCESS,
6760 0x00000000);
6761 /* XXX : not implemented */
6762 spr_register(env, SPR_7XX_PMC6, "PMC6",
6763 SPR_NOACCESS, SPR_NOACCESS,
6764 &spr_read_generic, &spr_write_generic,
6765 0x00000000);
6766 /* XXX : not implemented */
6767 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6768 &spr_read_ureg, SPR_NOACCESS,
6769 &spr_read_ureg, SPR_NOACCESS,
6770 0x00000000);
6771 /* Memory management */
6772 gen_low_BATs(env);
6773 gen_74xx_soft_tlb(env, 128, 2);
6774 init_excp_7450(env);
6775 env->dcache_line_size = 32;
6776 env->icache_line_size = 32;
6777 /* Allocate hardware IRQ controller */
6778 ppc6xx_irq_init(ppc_env_get_cpu(env));
6779 }
6780
6781 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
6782 {
6783 DeviceClass *dc = DEVICE_CLASS(oc);
6784 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6785
6786 dc->desc = "PowerPC 7450 (aka G4)";
6787 pcc->init_proc = init_proc_7450;
6788 pcc->check_pow = check_pow_hid0_74xx;
6789 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6790 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6791 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6792 PPC_FLOAT_STFIWX |
6793 PPC_CACHE | PPC_CACHE_ICBI |
6794 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6795 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6796 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6797 PPC_MEM_TLBIA | PPC_74xx_TLB |
6798 PPC_SEGMENT | PPC_EXTERN |
6799 PPC_ALTIVEC;
6800 pcc->msr_mask = (1ull << MSR_VR) |
6801 (1ull << MSR_POW) |
6802 (1ull << MSR_ILE) |
6803 (1ull << MSR_EE) |
6804 (1ull << MSR_PR) |
6805 (1ull << MSR_FP) |
6806 (1ull << MSR_ME) |
6807 (1ull << MSR_FE0) |
6808 (1ull << MSR_SE) |
6809 (1ull << MSR_DE) |
6810 (1ull << MSR_FE1) |
6811 (1ull << MSR_EP) |
6812 (1ull << MSR_IR) |
6813 (1ull << MSR_DR) |
6814 (1ull << MSR_PMM) |
6815 (1ull << MSR_RI) |
6816 (1ull << MSR_LE);
6817 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6818 pcc->excp_model = POWERPC_EXCP_74xx;
6819 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6820 pcc->bfd_mach = bfd_mach_ppc_7400;
6821 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6822 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6823 POWERPC_FLAG_BUS_CLK;
6824 }
6825
6826 static void init_proc_7445 (CPUPPCState *env)
6827 {
6828 gen_spr_ne_601(env);
6829 gen_spr_7xx(env);
6830 /* Time base */
6831 gen_tbl(env);
6832 /* 74xx specific SPR */
6833 gen_spr_74xx(env);
6834 /* LDSTCR */
6835 /* XXX : not implemented */
6836 spr_register(env, SPR_LDSTCR, "LDSTCR",
6837 SPR_NOACCESS, SPR_NOACCESS,
6838 &spr_read_generic, &spr_write_generic,
6839 0x00000000);
6840 /* ICTRL */
6841 /* XXX : not implemented */
6842 spr_register(env, SPR_ICTRL, "ICTRL",
6843 SPR_NOACCESS, SPR_NOACCESS,
6844 &spr_read_generic, &spr_write_generic,
6845 0x00000000);
6846 /* MSSSR0 */
6847 /* XXX : not implemented */
6848 spr_register(env, SPR_MSSSR0, "MSSSR0",
6849 SPR_NOACCESS, SPR_NOACCESS,
6850 &spr_read_generic, &spr_write_generic,
6851 0x00000000);
6852 /* PMC */
6853 /* XXX : not implemented */
6854 spr_register(env, SPR_7XX_PMC5, "PMC5",
6855 SPR_NOACCESS, SPR_NOACCESS,
6856 &spr_read_generic, &spr_write_generic,
6857 0x00000000);
6858 /* XXX : not implemented */
6859 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6860 &spr_read_ureg, SPR_NOACCESS,
6861 &spr_read_ureg, SPR_NOACCESS,
6862 0x00000000);
6863 /* XXX : not implemented */
6864 spr_register(env, SPR_7XX_PMC6, "PMC6",
6865 SPR_NOACCESS, SPR_NOACCESS,
6866 &spr_read_generic, &spr_write_generic,
6867 0x00000000);
6868 /* XXX : not implemented */
6869 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6870 &spr_read_ureg, SPR_NOACCESS,
6871 &spr_read_ureg, SPR_NOACCESS,
6872 0x00000000);
6873 /* SPRGs */
6874 spr_register(env, SPR_SPRG4, "SPRG4",
6875 SPR_NOACCESS, SPR_NOACCESS,
6876 &spr_read_generic, &spr_write_generic,
6877 0x00000000);
6878 spr_register(env, SPR_USPRG4, "USPRG4",
6879 &spr_read_ureg, SPR_NOACCESS,
6880 &spr_read_ureg, SPR_NOACCESS,
6881 0x00000000);
6882 spr_register(env, SPR_SPRG5, "SPRG5",
6883 SPR_NOACCESS, SPR_NOACCESS,
6884 &spr_read_generic, &spr_write_generic,
6885 0x00000000);
6886 spr_register(env, SPR_USPRG5, "USPRG5",
6887 &spr_read_ureg, SPR_NOACCESS,
6888 &spr_read_ureg, SPR_NOACCESS,
6889 0x00000000);
6890 spr_register(env, SPR_SPRG6, "SPRG6",
6891 SPR_NOACCESS, SPR_NOACCESS,
6892 &spr_read_generic, &spr_write_generic,
6893 0x00000000);
6894 spr_register(env, SPR_USPRG6, "USPRG6",
6895 &spr_read_ureg, SPR_NOACCESS,
6896 &spr_read_ureg, SPR_NOACCESS,
6897 0x00000000);
6898 spr_register(env, SPR_SPRG7, "SPRG7",
6899 SPR_NOACCESS, SPR_NOACCESS,
6900 &spr_read_generic, &spr_write_generic,
6901 0x00000000);
6902 spr_register(env, SPR_USPRG7, "USPRG7",
6903 &spr_read_ureg, SPR_NOACCESS,
6904 &spr_read_ureg, SPR_NOACCESS,
6905 0x00000000);
6906 /* Memory management */
6907 gen_low_BATs(env);
6908 gen_high_BATs(env);
6909 gen_74xx_soft_tlb(env, 128, 2);
6910 init_excp_7450(env);
6911 env->dcache_line_size = 32;
6912 env->icache_line_size = 32;
6913 /* Allocate hardware IRQ controller */
6914 ppc6xx_irq_init(ppc_env_get_cpu(env));
6915 }
6916
6917 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
6918 {
6919 DeviceClass *dc = DEVICE_CLASS(oc);
6920 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6921
6922 dc->desc = "PowerPC 7445 (aka G4)";
6923 pcc->init_proc = init_proc_7445;
6924 pcc->check_pow = check_pow_hid0_74xx;
6925 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6926 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6927 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6928 PPC_FLOAT_STFIWX |
6929 PPC_CACHE | PPC_CACHE_ICBI |
6930 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6931 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6932 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6933 PPC_MEM_TLBIA | PPC_74xx_TLB |
6934 PPC_SEGMENT | PPC_EXTERN |
6935 PPC_ALTIVEC;
6936 pcc->msr_mask = (1ull << MSR_VR) |
6937 (1ull << MSR_POW) |
6938 (1ull << MSR_ILE) |
6939 (1ull << MSR_EE) |
6940 (1ull << MSR_PR) |
6941 (1ull << MSR_FP) |
6942 (1ull << MSR_ME) |
6943 (1ull << MSR_FE0) |
6944 (1ull << MSR_SE) |
6945 (1ull << MSR_DE) |
6946 (1ull << MSR_FE1) |
6947 (1ull << MSR_EP) |
6948 (1ull << MSR_IR) |
6949 (1ull << MSR_DR) |
6950 (1ull << MSR_PMM) |
6951 (1ull << MSR_RI) |
6952 (1ull << MSR_LE);
6953 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6954 pcc->excp_model = POWERPC_EXCP_74xx;
6955 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6956 pcc->bfd_mach = bfd_mach_ppc_7400;
6957 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6958 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6959 POWERPC_FLAG_BUS_CLK;
6960 }
6961
6962 static void init_proc_7455 (CPUPPCState *env)
6963 {
6964 gen_spr_ne_601(env);
6965 gen_spr_7xx(env);
6966 /* Time base */
6967 gen_tbl(env);
6968 /* 74xx specific SPR */
6969 gen_spr_74xx(env);
6970 /* Level 3 cache control */
6971 gen_l3_ctrl(env);
6972 /* LDSTCR */
6973 /* XXX : not implemented */
6974 spr_register(env, SPR_LDSTCR, "LDSTCR",
6975 SPR_NOACCESS, SPR_NOACCESS,
6976 &spr_read_generic, &spr_write_generic,
6977 0x00000000);
6978 /* ICTRL */
6979 /* XXX : not implemented */
6980 spr_register(env, SPR_ICTRL, "ICTRL",
6981 SPR_NOACCESS, SPR_NOACCESS,
6982 &spr_read_generic, &spr_write_generic,
6983 0x00000000);
6984 /* MSSSR0 */
6985 /* XXX : not implemented */
6986 spr_register(env, SPR_MSSSR0, "MSSSR0",
6987 SPR_NOACCESS, SPR_NOACCESS,
6988 &spr_read_generic, &spr_write_generic,
6989 0x00000000);
6990 /* PMC */
6991 /* XXX : not implemented */
6992 spr_register(env, SPR_7XX_PMC5, "PMC5",
6993 SPR_NOACCESS, SPR_NOACCESS,
6994 &spr_read_generic, &spr_write_generic,
6995 0x00000000);
6996 /* XXX : not implemented */
6997 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6998 &spr_read_ureg, SPR_NOACCESS,
6999 &spr_read_ureg, SPR_NOACCESS,
7000 0x00000000);
7001 /* XXX : not implemented */
7002 spr_register(env, SPR_7XX_PMC6, "PMC6",
7003 SPR_NOACCESS, SPR_NOACCESS,
7004 &spr_read_generic, &spr_write_generic,
7005 0x00000000);
7006 /* XXX : not implemented */
7007 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
7008 &spr_read_ureg, SPR_NOACCESS,
7009 &spr_read_ureg, SPR_NOACCESS,
7010 0x00000000);
7011 /* SPRGs */
7012 spr_register(env, SPR_SPRG4, "SPRG4",
7013 SPR_NOACCESS, SPR_NOACCESS,
7014 &spr_read_generic, &spr_write_generic,
7015 0x00000000);
7016 spr_register(env, SPR_USPRG4, "USPRG4",
7017 &spr_read_ureg, SPR_NOACCESS,
7018 &spr_read_ureg, SPR_NOACCESS,
7019 0x00000000);
7020 spr_register(env, SPR_SPRG5, "SPRG5",
7021 SPR_NOACCESS, SPR_NOACCESS,
7022 &spr_read_generic, &spr_write_generic,
7023 0x00000000);
7024 spr_register(env, SPR_USPRG5, "USPRG5",
7025 &spr_read_ureg, SPR_NOACCESS,
7026 &spr_read_ureg, SPR_NOACCESS,
7027 0x00000000);
7028 spr_register(env, SPR_SPRG6, "SPRG6",
7029 SPR_NOACCESS, SPR_NOACCESS,
7030 &spr_read_generic, &spr_write_generic,
7031 0x00000000);
7032 spr_register(env, SPR_USPRG6, "USPRG6",
7033 &spr_read_ureg, SPR_NOACCESS,
7034 &spr_read_ureg, SPR_NOACCESS,
7035 0x00000000);
7036 spr_register(env, SPR_SPRG7, "SPRG7",
7037 SPR_NOACCESS, SPR_NOACCESS,
7038 &spr_read_generic, &spr_write_generic,
7039 0x00000000);
7040 spr_register(env, SPR_USPRG7, "USPRG7",
7041 &spr_read_ureg, SPR_NOACCESS,
7042 &spr_read_ureg, SPR_NOACCESS,
7043 0x00000000);
7044 /* Memory management */
7045 gen_low_BATs(env);
7046 gen_high_BATs(env);
7047 gen_74xx_soft_tlb(env, 128, 2);
7048 init_excp_7450(env);
7049 env->dcache_line_size = 32;
7050 env->icache_line_size = 32;
7051 /* Allocate hardware IRQ controller */
7052 ppc6xx_irq_init(ppc_env_get_cpu(env));
7053 }
7054
7055 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
7056 {
7057 DeviceClass *dc = DEVICE_CLASS(oc);
7058 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7059
7060 dc->desc = "PowerPC 7455 (aka G4)";
7061 pcc->init_proc = init_proc_7455;
7062 pcc->check_pow = check_pow_hid0_74xx;
7063 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7064 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7065 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7066 PPC_FLOAT_STFIWX |
7067 PPC_CACHE | PPC_CACHE_ICBI |
7068 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7069 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7070 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7071 PPC_MEM_TLBIA | PPC_74xx_TLB |
7072 PPC_SEGMENT | PPC_EXTERN |
7073 PPC_ALTIVEC;
7074 pcc->msr_mask = (1ull << MSR_VR) |
7075 (1ull << MSR_POW) |
7076 (1ull << MSR_ILE) |
7077 (1ull << MSR_EE) |
7078 (1ull << MSR_PR) |
7079 (1ull << MSR_FP) |
7080 (1ull << MSR_ME) |
7081 (1ull << MSR_FE0) |
7082 (1ull << MSR_SE) |
7083 (1ull << MSR_DE) |
7084 (1ull << MSR_FE1) |
7085 (1ull << MSR_EP) |
7086 (1ull << MSR_IR) |
7087 (1ull << MSR_DR) |
7088 (1ull << MSR_PMM) |
7089 (1ull << MSR_RI) |
7090 (1ull << MSR_LE);
7091 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
7092 pcc->excp_model = POWERPC_EXCP_74xx;
7093 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7094 pcc->bfd_mach = bfd_mach_ppc_7400;
7095 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7096 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7097 POWERPC_FLAG_BUS_CLK;
7098 }
7099
7100 static void init_proc_7457 (CPUPPCState *env)
7101 {
7102 gen_spr_ne_601(env);
7103 gen_spr_7xx(env);
7104 /* Time base */
7105 gen_tbl(env);
7106 /* 74xx specific SPR */
7107 gen_spr_74xx(env);
7108 /* Level 3 cache control */
7109 gen_l3_ctrl(env);
7110 /* L3ITCR1 */
7111 /* XXX : not implemented */
7112 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
7113 SPR_NOACCESS, SPR_NOACCESS,
7114 &spr_read_generic, &spr_write_generic,
7115 0x00000000);
7116 /* L3ITCR2 */
7117 /* XXX : not implemented */
7118 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
7119 SPR_NOACCESS, SPR_NOACCESS,
7120 &spr_read_generic, &spr_write_generic,
7121 0x00000000);
7122 /* L3ITCR3 */
7123 /* XXX : not implemented */
7124 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
7125 SPR_NOACCESS, SPR_NOACCESS,
7126 &spr_read_generic, &spr_write_generic,
7127 0x00000000);
7128 /* L3OHCR */
7129 /* XXX : not implemented */
7130 spr_register(env, SPR_L3OHCR, "L3OHCR",
7131 SPR_NOACCESS, SPR_NOACCESS,
7132 &spr_read_generic, &spr_write_generic,
7133 0x00000000);
7134 /* LDSTCR */
7135 /* XXX : not implemented */
7136 spr_register(env, SPR_LDSTCR, "LDSTCR",
7137 SPR_NOACCESS, SPR_NOACCESS,
7138 &spr_read_generic, &spr_write_generic,
7139 0x00000000);
7140 /* ICTRL */
7141 /* XXX : not implemented */
7142 spr_register(env, SPR_ICTRL, "ICTRL",
7143 SPR_NOACCESS, SPR_NOACCESS,
7144 &spr_read_generic, &spr_write_generic,
7145 0x00000000);
7146 /* MSSSR0 */
7147 /* XXX : not implemented */
7148 spr_register(env, SPR_MSSSR0, "MSSSR0",
7149 SPR_NOACCESS, SPR_NOACCESS,
7150 &spr_read_generic, &spr_write_generic,
7151 0x00000000);
7152 /* PMC */
7153 /* XXX : not implemented */
7154 spr_register(env, SPR_7XX_PMC5, "PMC5",
7155 SPR_NOACCESS, SPR_NOACCESS,
7156 &spr_read_generic, &spr_write_generic,
7157 0x00000000);
7158 /* XXX : not implemented */
7159 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
7160 &spr_read_ureg, SPR_NOACCESS,
7161 &spr_read_ureg, SPR_NOACCESS,
7162 0x00000000);
7163 /* XXX : not implemented */
7164 spr_register(env, SPR_7XX_PMC6, "PMC6",
7165 SPR_NOACCESS, SPR_NOACCESS,
7166 &spr_read_generic, &spr_write_generic,
7167 0x00000000);
7168 /* XXX : not implemented */
7169 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
7170 &spr_read_ureg, SPR_NOACCESS,
7171 &spr_read_ureg, SPR_NOACCESS,
7172 0x00000000);
7173 /* SPRGs */
7174 spr_register(env, SPR_SPRG4, "SPRG4",
7175 SPR_NOACCESS, SPR_NOACCESS,
7176 &spr_read_generic, &spr_write_generic,
7177 0x00000000);
7178 spr_register(env, SPR_USPRG4, "USPRG4",
7179 &spr_read_ureg, SPR_NOACCESS,
7180 &spr_read_ureg, SPR_NOACCESS,
7181 0x00000000);
7182 spr_register(env, SPR_SPRG5, "SPRG5",
7183 SPR_NOACCESS, SPR_NOACCESS,
7184 &spr_read_generic, &spr_write_generic,
7185 0x00000000);
7186 spr_register(env, SPR_USPRG5, "USPRG5",
7187 &spr_read_ureg, SPR_NOACCESS,
7188 &spr_read_ureg, SPR_NOACCESS,
7189 0x00000000);
7190 spr_register(env, SPR_SPRG6, "SPRG6",
7191 SPR_NOACCESS, SPR_NOACCESS,
7192 &spr_read_generic, &spr_write_generic,
7193 0x00000000);
7194 spr_register(env, SPR_USPRG6, "USPRG6",
7195 &spr_read_ureg, SPR_NOACCESS,
7196 &spr_read_ureg, SPR_NOACCESS,
7197 0x00000000);
7198 spr_register(env, SPR_SPRG7, "SPRG7",
7199 SPR_NOACCESS, SPR_NOACCESS,
7200 &spr_read_generic, &spr_write_generic,
7201 0x00000000);
7202 spr_register(env, SPR_USPRG7, "USPRG7",
7203 &spr_read_ureg, SPR_NOACCESS,
7204 &spr_read_ureg, SPR_NOACCESS,
7205 0x00000000);
7206 /* Memory management */
7207 gen_low_BATs(env);
7208 gen_high_BATs(env);
7209 gen_74xx_soft_tlb(env, 128, 2);
7210 init_excp_7450(env);
7211 env->dcache_line_size = 32;
7212 env->icache_line_size = 32;
7213 /* Allocate hardware IRQ controller */
7214 ppc6xx_irq_init(ppc_env_get_cpu(env));
7215 }
7216
7217 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
7218 {
7219 DeviceClass *dc = DEVICE_CLASS(oc);
7220 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7221
7222 dc->desc = "PowerPC 7457 (aka G4)";
7223 pcc->init_proc = init_proc_7457;
7224 pcc->check_pow = check_pow_hid0_74xx;
7225 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7226 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7227 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7228 PPC_FLOAT_STFIWX |
7229 PPC_CACHE | PPC_CACHE_ICBI |
7230 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7231 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7232 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7233 PPC_MEM_TLBIA | PPC_74xx_TLB |
7234 PPC_SEGMENT | PPC_EXTERN |
7235 PPC_ALTIVEC;
7236 pcc->msr_mask = (1ull << MSR_VR) |
7237 (1ull << MSR_POW) |
7238 (1ull << MSR_ILE) |
7239 (1ull << MSR_EE) |
7240 (1ull << MSR_PR) |
7241 (1ull << MSR_FP) |
7242 (1ull << MSR_ME) |
7243 (1ull << MSR_FE0) |
7244 (1ull << MSR_SE) |
7245 (1ull << MSR_DE) |
7246 (1ull << MSR_FE1) |
7247 (1ull << MSR_EP) |
7248 (1ull << MSR_IR) |
7249 (1ull << MSR_DR) |
7250 (1ull << MSR_PMM) |
7251 (1ull << MSR_RI) |
7252 (1ull << MSR_LE);
7253 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
7254 pcc->excp_model = POWERPC_EXCP_74xx;
7255 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7256 pcc->bfd_mach = bfd_mach_ppc_7400;
7257 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7258 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7259 POWERPC_FLAG_BUS_CLK;
7260 }
7261
7262 static void init_proc_e600 (CPUPPCState *env)
7263 {
7264 gen_spr_ne_601(env);
7265 gen_spr_7xx(env);
7266 /* Time base */
7267 gen_tbl(env);
7268 /* 74xx specific SPR */
7269 gen_spr_74xx(env);
7270 /* XXX : not implemented */
7271 spr_register(env, SPR_UBAMR, "UBAMR",
7272 &spr_read_ureg, SPR_NOACCESS,
7273 &spr_read_ureg, SPR_NOACCESS,
7274 0x00000000);
7275 /* XXX : not implemented */
7276 spr_register(env, SPR_LDSTCR, "LDSTCR",
7277 SPR_NOACCESS, SPR_NOACCESS,
7278 &spr_read_generic, &spr_write_generic,
7279 0x00000000);
7280 /* XXX : not implemented */
7281 spr_register(env, SPR_ICTRL, "ICTRL",
7282 SPR_NOACCESS, SPR_NOACCESS,
7283 &spr_read_generic, &spr_write_generic,
7284 0x00000000);
7285 /* XXX : not implemented */
7286 spr_register(env, SPR_MSSSR0, "MSSSR0",
7287 SPR_NOACCESS, SPR_NOACCESS,
7288 &spr_read_generic, &spr_write_generic,
7289 0x00000000);
7290 /* XXX : not implemented */
7291 spr_register(env, SPR_7XX_PMC5, "PMC5",
7292 SPR_NOACCESS, SPR_NOACCESS,
7293 &spr_read_generic, &spr_write_generic,
7294 0x00000000);
7295 /* XXX : not implemented */
7296 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
7297 &spr_read_ureg, SPR_NOACCESS,
7298 &spr_read_ureg, SPR_NOACCESS,
7299 0x00000000);
7300 /* XXX : not implemented */
7301 spr_register(env, SPR_7XX_PMC6, "PMC6",
7302 SPR_NOACCESS, SPR_NOACCESS,
7303 &spr_read_generic, &spr_write_generic,
7304 0x00000000);
7305 /* XXX : not implemented */
7306 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
7307 &spr_read_ureg, SPR_NOACCESS,
7308 &spr_read_ureg, SPR_NOACCESS,
7309 0x00000000);
7310 /* SPRGs */
7311 spr_register(env, SPR_SPRG4, "SPRG4",
7312 SPR_NOACCESS, SPR_NOACCESS,
7313 &spr_read_generic, &spr_write_generic,
7314 0x00000000);
7315 spr_register(env, SPR_USPRG4, "USPRG4",
7316 &spr_read_ureg, SPR_NOACCESS,
7317 &spr_read_ureg, SPR_NOACCESS,
7318 0x00000000);
7319 spr_register(env, SPR_SPRG5, "SPRG5",
7320 SPR_NOACCESS, SPR_NOACCESS,
7321 &spr_read_generic, &spr_write_generic,
7322 0x00000000);
7323 spr_register(env, SPR_USPRG5, "USPRG5",
7324 &spr_read_ureg, SPR_NOACCESS,
7325 &spr_read_ureg, SPR_NOACCESS,
7326 0x00000000);
7327 spr_register(env, SPR_SPRG6, "SPRG6",
7328 SPR_NOACCESS, SPR_NOACCESS,
7329 &spr_read_generic, &spr_write_generic,
7330 0x00000000);
7331 spr_register(env, SPR_USPRG6, "USPRG6",
7332 &spr_read_ureg, SPR_NOACCESS,
7333 &spr_read_ureg, SPR_NOACCESS,
7334 0x00000000);
7335 spr_register(env, SPR_SPRG7, "SPRG7",
7336 SPR_NOACCESS, SPR_NOACCESS,
7337 &spr_read_generic, &spr_write_generic,
7338 0x00000000);
7339 spr_register(env, SPR_USPRG7, "USPRG7",
7340 &spr_read_ureg, SPR_NOACCESS,
7341 &spr_read_ureg, SPR_NOACCESS,
7342 0x00000000);
7343 /* Memory management */
7344 gen_low_BATs(env);
7345 gen_high_BATs(env);
7346 gen_74xx_soft_tlb(env, 128, 2);
7347 init_excp_7450(env);
7348 env->dcache_line_size = 32;
7349 env->icache_line_size = 32;
7350 /* Allocate hardware IRQ controller */
7351 ppc6xx_irq_init(ppc_env_get_cpu(env));
7352 }
7353
7354 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
7355 {
7356 DeviceClass *dc = DEVICE_CLASS(oc);
7357 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7358
7359 dc->desc = "PowerPC e600";
7360 pcc->init_proc = init_proc_e600;
7361 pcc->check_pow = check_pow_hid0_74xx;
7362 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7363 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7364 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7365 PPC_FLOAT_STFIWX |
7366 PPC_CACHE | PPC_CACHE_ICBI |
7367 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7368 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7369 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7370 PPC_MEM_TLBIA | PPC_74xx_TLB |
7371 PPC_SEGMENT | PPC_EXTERN |
7372 PPC_ALTIVEC;
7373 pcc->insns_flags2 = PPC_NONE;
7374 pcc->msr_mask = (1ull << MSR_VR) |
7375 (1ull << MSR_POW) |
7376 (1ull << MSR_ILE) |
7377 (1ull << MSR_EE) |
7378 (1ull << MSR_PR) |
7379 (1ull << MSR_FP) |
7380 (1ull << MSR_ME) |
7381 (1ull << MSR_FE0) |
7382 (1ull << MSR_SE) |
7383 (1ull << MSR_DE) |
7384 (1ull << MSR_FE1) |
7385 (1ull << MSR_EP) |
7386 (1ull << MSR_IR) |
7387 (1ull << MSR_DR) |
7388 (1ull << MSR_PMM) |
7389 (1ull << MSR_RI) |
7390 (1ull << MSR_LE);
7391 pcc->mmu_model = POWERPC_MMU_32B;
7392 #if defined(CONFIG_SOFTMMU)
7393 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
7394 #endif
7395 pcc->excp_model = POWERPC_EXCP_74xx;
7396 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7397 pcc->bfd_mach = bfd_mach_ppc_7400;
7398 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7399 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7400 POWERPC_FLAG_BUS_CLK;
7401 }
7402
7403 #if defined (TARGET_PPC64)
7404 #if defined(CONFIG_USER_ONLY)
7405 #define POWERPC970_HID5_INIT 0x00000080
7406 #else
7407 #define POWERPC970_HID5_INIT 0x00000000
7408 #endif
7409
7410 enum BOOK3S_CPU_TYPE {
7411 BOOK3S_CPU_970,
7412 BOOK3S_CPU_POWER5PLUS,
7413 BOOK3S_CPU_POWER6,
7414 BOOK3S_CPU_POWER7,
7415 BOOK3S_CPU_POWER8
7416 };
7417
7418 static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
7419 int bit, int sprn, int cause)
7420 {
7421 TCGv_i32 t1 = tcg_const_i32(bit);
7422 TCGv_i32 t2 = tcg_const_i32(sprn);
7423 TCGv_i32 t3 = tcg_const_i32(cause);
7424
7425 gen_update_current_nip(ctx);
7426 gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
7427
7428 tcg_temp_free_i32(t3);
7429 tcg_temp_free_i32(t2);
7430 tcg_temp_free_i32(t1);
7431 }
7432
7433 static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
7434 int bit, int sprn, int cause)
7435 {
7436 TCGv_i32 t1 = tcg_const_i32(bit);
7437 TCGv_i32 t2 = tcg_const_i32(sprn);
7438 TCGv_i32 t3 = tcg_const_i32(cause);
7439
7440 gen_update_current_nip(ctx);
7441 gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
7442
7443 tcg_temp_free_i32(t3);
7444 tcg_temp_free_i32(t2);
7445 tcg_temp_free_i32(t1);
7446 }
7447
7448 static void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
7449 {
7450 TCGv spr_up = tcg_temp_new();
7451 TCGv spr = tcg_temp_new();
7452
7453 gen_load_spr(spr, sprn - 1);
7454 tcg_gen_shri_tl(spr_up, spr, 32);
7455 tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up);
7456
7457 tcg_temp_free(spr);
7458 tcg_temp_free(spr_up);
7459 }
7460
7461 static void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn)
7462 {
7463 TCGv spr = tcg_temp_new();
7464
7465 gen_load_spr(spr, sprn - 1);
7466 tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32);
7467 gen_store_spr(sprn - 1, spr);
7468
7469 tcg_temp_free(spr);
7470 }
7471
7472 static int check_pow_970 (CPUPPCState *env)
7473 {
7474 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) {
7475 return 1;
7476 }
7477
7478 return 0;
7479 }
7480
7481 static void gen_spr_970_hid(CPUPPCState *env)
7482 {
7483 /* Hardware implementation registers */
7484 /* XXX : not implemented */
7485 spr_register(env, SPR_HID0, "HID0",
7486 SPR_NOACCESS, SPR_NOACCESS,
7487 &spr_read_generic, &spr_write_clear,
7488 0x60000000);
7489 spr_register(env, SPR_HID1, "HID1",
7490 SPR_NOACCESS, SPR_NOACCESS,
7491 &spr_read_generic, &spr_write_generic,
7492 0x00000000);
7493 spr_register(env, SPR_970_HID5, "HID5",
7494 SPR_NOACCESS, SPR_NOACCESS,
7495 &spr_read_generic, &spr_write_generic,
7496 POWERPC970_HID5_INIT);
7497 }
7498
7499 static void gen_spr_970_hior(CPUPPCState *env)
7500 {
7501 spr_register(env, SPR_HIOR, "SPR_HIOR",
7502 SPR_NOACCESS, SPR_NOACCESS,
7503 &spr_read_hior, &spr_write_hior,
7504 0x00000000);
7505 }
7506
7507 static void gen_spr_970_lpar(CPUPPCState *env)
7508 {
7509 /* Logical partitionning */
7510 /* PPC970: HID4 is effectively the LPCR */
7511 spr_register(env, SPR_970_HID4, "HID4",
7512 SPR_NOACCESS, SPR_NOACCESS,
7513 &spr_read_generic, &spr_write_generic,
7514 0x00000000);
7515 }
7516
7517 static void gen_spr_book3s_common(CPUPPCState *env)
7518 {
7519 spr_register(env, SPR_CTRL, "SPR_CTRL",
7520 SPR_NOACCESS, SPR_NOACCESS,
7521 SPR_NOACCESS, &spr_write_generic,
7522 0x00000000);
7523 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
7524 &spr_read_ureg, SPR_NOACCESS,
7525 &spr_read_ureg, SPR_NOACCESS,
7526 0x00000000);
7527 }
7528
7529 static void gen_spr_book3s_altivec(CPUPPCState *env)
7530 {
7531 if (!(env->insns_flags & PPC_ALTIVEC)) {
7532 return;
7533 }
7534
7535 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
7536 &spr_read_generic, &spr_write_generic,
7537 &spr_read_generic, &spr_write_generic,
7538 KVM_REG_PPC_VRSAVE, 0x00000000);
7539
7540 /* Can't find information on what this should be on reset. This
7541 * value is the one used by 74xx processors. */
7542 vscr_init(env, 0x00010000);
7543 }
7544
7545 static void gen_spr_book3s_dbg(CPUPPCState *env)
7546 {
7547 /*
7548 * TODO: different specs define different scopes for these,
7549 * will have to address this:
7550 * 970: super/write and super/read
7551 * powerisa 2.03..2.04: hypv/write and super/read.
7552 * powerisa 2.05 and newer: hypv/write and hypv/read.
7553 */
7554 spr_register_kvm(env, SPR_DABR, "DABR",
7555 SPR_NOACCESS, SPR_NOACCESS,
7556 &spr_read_generic, &spr_write_generic,
7557 KVM_REG_PPC_DABR, 0x00000000);
7558 spr_register_kvm(env, SPR_DABRX, "DABRX",
7559 SPR_NOACCESS, SPR_NOACCESS,
7560 &spr_read_generic, &spr_write_generic,
7561 KVM_REG_PPC_DABRX, 0x00000000);
7562 }
7563
7564 static void gen_spr_book3s_207_dbg(CPUPPCState *env)
7565 {
7566 spr_register_kvm_hv(env, SPR_DAWR, "DAWR",
7567 SPR_NOACCESS, SPR_NOACCESS,
7568 SPR_NOACCESS, SPR_NOACCESS,
7569 &spr_read_generic, &spr_write_generic,
7570 KVM_REG_PPC_DAWR, 0x00000000);
7571 spr_register_kvm_hv(env, SPR_DAWRX, "DAWRX",
7572 SPR_NOACCESS, SPR_NOACCESS,
7573 SPR_NOACCESS, SPR_NOACCESS,
7574 &spr_read_generic, &spr_write_generic,
7575 KVM_REG_PPC_DAWRX, 0x00000000);
7576 spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
7577 SPR_NOACCESS, SPR_NOACCESS,
7578 SPR_NOACCESS, SPR_NOACCESS,
7579 &spr_read_generic, &spr_write_generic,
7580 KVM_REG_PPC_CIABR, 0x00000000);
7581 }
7582
7583 static void gen_spr_970_dbg(CPUPPCState *env)
7584 {
7585 /* Breakpoints */
7586 spr_register(env, SPR_IABR, "IABR",
7587 SPR_NOACCESS, SPR_NOACCESS,
7588 &spr_read_generic, &spr_write_generic,
7589 0x00000000);
7590 }
7591
7592 static void gen_spr_book3s_pmu_sup(CPUPPCState *env)
7593 {
7594 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
7595 SPR_NOACCESS, SPR_NOACCESS,
7596 &spr_read_generic, &spr_write_generic,
7597 KVM_REG_PPC_MMCR0, 0x00000000);
7598 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
7599 SPR_NOACCESS, SPR_NOACCESS,
7600 &spr_read_generic, &spr_write_generic,
7601 KVM_REG_PPC_MMCR1, 0x00000000);
7602 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
7603 SPR_NOACCESS, SPR_NOACCESS,
7604 &spr_read_generic, &spr_write_generic,
7605 KVM_REG_PPC_MMCRA, 0x00000000);
7606 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
7607 SPR_NOACCESS, SPR_NOACCESS,
7608 &spr_read_generic, &spr_write_generic,
7609 KVM_REG_PPC_PMC1, 0x00000000);
7610 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2",
7611 SPR_NOACCESS, SPR_NOACCESS,
7612 &spr_read_generic, &spr_write_generic,
7613 KVM_REG_PPC_PMC2, 0x00000000);
7614 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3",
7615 SPR_NOACCESS, SPR_NOACCESS,
7616 &spr_read_generic, &spr_write_generic,
7617 KVM_REG_PPC_PMC3, 0x00000000);
7618 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4",
7619 SPR_NOACCESS, SPR_NOACCESS,
7620 &spr_read_generic, &spr_write_generic,
7621 KVM_REG_PPC_PMC4, 0x00000000);
7622 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5",
7623 SPR_NOACCESS, SPR_NOACCESS,
7624 &spr_read_generic, &spr_write_generic,
7625 KVM_REG_PPC_PMC5, 0x00000000);
7626 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6",
7627 SPR_NOACCESS, SPR_NOACCESS,
7628 &spr_read_generic, &spr_write_generic,
7629 KVM_REG_PPC_PMC6, 0x00000000);
7630 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR",
7631 SPR_NOACCESS, SPR_NOACCESS,
7632 &spr_read_generic, &spr_write_generic,
7633 KVM_REG_PPC_SIAR, 0x00000000);
7634 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR",
7635 SPR_NOACCESS, SPR_NOACCESS,
7636 &spr_read_generic, &spr_write_generic,
7637 KVM_REG_PPC_SDAR, 0x00000000);
7638 }
7639
7640 static void gen_spr_book3s_pmu_user(CPUPPCState *env)
7641 {
7642 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
7643 &spr_read_ureg, SPR_NOACCESS,
7644 &spr_read_ureg, &spr_write_ureg,
7645 0x00000000);
7646 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
7647 &spr_read_ureg, SPR_NOACCESS,
7648 &spr_read_ureg, &spr_write_ureg,
7649 0x00000000);
7650 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA",
7651 &spr_read_ureg, SPR_NOACCESS,
7652 &spr_read_ureg, &spr_write_ureg,
7653 0x00000000);
7654 spr_register(env, SPR_POWER_UPMC1, "UPMC1",
7655 &spr_read_ureg, SPR_NOACCESS,
7656 &spr_read_ureg, &spr_write_ureg,
7657 0x00000000);
7658 spr_register(env, SPR_POWER_UPMC2, "UPMC2",
7659 &spr_read_ureg, SPR_NOACCESS,
7660 &spr_read_ureg, &spr_write_ureg,
7661 0x00000000);
7662 spr_register(env, SPR_POWER_UPMC3, "UPMC3",
7663 &spr_read_ureg, SPR_NOACCESS,
7664 &spr_read_ureg, &spr_write_ureg,
7665 0x00000000);
7666 spr_register(env, SPR_POWER_UPMC4, "UPMC4",
7667 &spr_read_ureg, SPR_NOACCESS,
7668 &spr_read_ureg, &spr_write_ureg,
7669 0x00000000);
7670 spr_register(env, SPR_POWER_UPMC5, "UPMC5",
7671 &spr_read_ureg, SPR_NOACCESS,
7672 &spr_read_ureg, &spr_write_ureg,
7673 0x00000000);
7674 spr_register(env, SPR_POWER_UPMC6, "UPMC6",
7675 &spr_read_ureg, SPR_NOACCESS,
7676 &spr_read_ureg, &spr_write_ureg,
7677 0x00000000);
7678 spr_register(env, SPR_POWER_USIAR, "USIAR",
7679 &spr_read_ureg, SPR_NOACCESS,
7680 &spr_read_ureg, &spr_write_ureg,
7681 0x00000000);
7682 spr_register(env, SPR_POWER_USDAR, "USDAR",
7683 &spr_read_ureg, SPR_NOACCESS,
7684 &spr_read_ureg, &spr_write_ureg,
7685 0x00000000);
7686 }
7687
7688 static void gen_spr_970_pmu_sup(CPUPPCState *env)
7689 {
7690 spr_register_kvm(env, SPR_970_PMC7, "PMC7",
7691 SPR_NOACCESS, SPR_NOACCESS,
7692 &spr_read_generic, &spr_write_generic,
7693 KVM_REG_PPC_PMC7, 0x00000000);
7694 spr_register_kvm(env, SPR_970_PMC8, "PMC8",
7695 SPR_NOACCESS, SPR_NOACCESS,
7696 &spr_read_generic, &spr_write_generic,
7697 KVM_REG_PPC_PMC8, 0x00000000);
7698 }
7699
7700 static void gen_spr_970_pmu_user(CPUPPCState *env)
7701 {
7702 spr_register(env, SPR_970_UPMC7, "UPMC7",
7703 &spr_read_ureg, SPR_NOACCESS,
7704 &spr_read_ureg, &spr_write_ureg,
7705 0x00000000);
7706 spr_register(env, SPR_970_UPMC8, "UPMC8",
7707 &spr_read_ureg, SPR_NOACCESS,
7708 &spr_read_ureg, &spr_write_ureg,
7709 0x00000000);
7710 }
7711
7712 static void gen_spr_power8_pmu_sup(CPUPPCState *env)
7713 {
7714 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
7715 SPR_NOACCESS, SPR_NOACCESS,
7716 &spr_read_generic, &spr_write_generic,
7717 KVM_REG_PPC_MMCR2, 0x00000000);
7718 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
7719 SPR_NOACCESS, SPR_NOACCESS,
7720 &spr_read_generic, &spr_write_generic,
7721 KVM_REG_PPC_MMCRS, 0x00000000);
7722 spr_register_kvm(env, SPR_POWER_SIER, "SIER",
7723 SPR_NOACCESS, SPR_NOACCESS,
7724 &spr_read_generic, &spr_write_generic,
7725 KVM_REG_PPC_SIER, 0x00000000);
7726 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1",
7727 SPR_NOACCESS, SPR_NOACCESS,
7728 &spr_read_generic, &spr_write_generic,
7729 KVM_REG_PPC_SPMC1, 0x00000000);
7730 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2",
7731 SPR_NOACCESS, SPR_NOACCESS,
7732 &spr_read_generic, &spr_write_generic,
7733 KVM_REG_PPC_SPMC2, 0x00000000);
7734 spr_register_kvm(env, SPR_TACR, "TACR",
7735 SPR_NOACCESS, SPR_NOACCESS,
7736 &spr_read_generic, &spr_write_generic,
7737 KVM_REG_PPC_TACR, 0x00000000);
7738 spr_register_kvm(env, SPR_TCSCR, "TCSCR",
7739 SPR_NOACCESS, SPR_NOACCESS,
7740 &spr_read_generic, &spr_write_generic,
7741 KVM_REG_PPC_TCSCR, 0x00000000);
7742 spr_register_kvm(env, SPR_CSIGR, "CSIGR",
7743 SPR_NOACCESS, SPR_NOACCESS,
7744 &spr_read_generic, &spr_write_generic,
7745 KVM_REG_PPC_CSIGR, 0x00000000);
7746 }
7747
7748 static void gen_spr_power8_pmu_user(CPUPPCState *env)
7749 {
7750 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
7751 &spr_read_ureg, SPR_NOACCESS,
7752 &spr_read_ureg, &spr_write_ureg,
7753 0x00000000);
7754 spr_register(env, SPR_POWER_USIER, "USIER",
7755 &spr_read_generic, SPR_NOACCESS,
7756 &spr_read_generic, &spr_write_generic,
7757 0x00000000);
7758 }
7759
7760 static void gen_spr_power5p_ear(CPUPPCState *env)
7761 {
7762 /* External access control */
7763 spr_register(env, SPR_EAR, "EAR",
7764 SPR_NOACCESS, SPR_NOACCESS,
7765 &spr_read_generic, &spr_write_generic,
7766 0x00000000);
7767 }
7768
7769 static void gen_spr_power5p_lpar(CPUPPCState *env)
7770 {
7771 /* Logical partitionning */
7772 spr_register_kvm(env, SPR_LPCR, "LPCR",
7773 SPR_NOACCESS, SPR_NOACCESS,
7774 &spr_read_generic, &spr_write_generic,
7775 KVM_REG_PPC_LPCR, 0x00000000);
7776 }
7777
7778 static void gen_spr_book3s_ids(CPUPPCState *env)
7779 {
7780 /* Processor identification */
7781 spr_register(env, SPR_PIR, "PIR",
7782 SPR_NOACCESS, SPR_NOACCESS,
7783 &spr_read_generic, &spr_write_pir,
7784 0x00000000);
7785 }
7786
7787 static void gen_spr_power8_ids(CPUPPCState *env)
7788 {
7789 /* Thread identification */
7790 spr_register(env, SPR_TIR, "TIR",
7791 SPR_NOACCESS, SPR_NOACCESS,
7792 &spr_read_generic, SPR_NOACCESS,
7793 0x00000000);
7794 }
7795
7796 static void gen_spr_book3s_purr(CPUPPCState *env)
7797 {
7798 #if !defined(CONFIG_USER_ONLY)
7799 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
7800 spr_register_kvm(env, SPR_PURR, "PURR",
7801 &spr_read_purr, SPR_NOACCESS,
7802 &spr_read_purr, SPR_NOACCESS,
7803 KVM_REG_PPC_PURR, 0x00000000);
7804 spr_register_kvm(env, SPR_SPURR, "SPURR",
7805 &spr_read_purr, SPR_NOACCESS,
7806 &spr_read_purr, SPR_NOACCESS,
7807 KVM_REG_PPC_SPURR, 0x00000000);
7808 #endif
7809 }
7810
7811 static void gen_spr_power6_dbg(CPUPPCState *env)
7812 {
7813 #if !defined(CONFIG_USER_ONLY)
7814 spr_register(env, SPR_CFAR, "SPR_CFAR",
7815 SPR_NOACCESS, SPR_NOACCESS,
7816 &spr_read_cfar, &spr_write_cfar,
7817 0x00000000);
7818 #endif
7819 }
7820
7821 static void gen_spr_power5p_common(CPUPPCState *env)
7822 {
7823 spr_register_kvm(env, SPR_PPR, "PPR",
7824 &spr_read_generic, &spr_write_generic,
7825 &spr_read_generic, &spr_write_generic,
7826 KVM_REG_PPC_PPR, 0x00000000);
7827 }
7828
7829 static void gen_spr_power6_common(CPUPPCState *env)
7830 {
7831 #if !defined(CONFIG_USER_ONLY)
7832 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
7833 SPR_NOACCESS, SPR_NOACCESS,
7834 &spr_read_generic, &spr_write_generic,
7835 KVM_REG_PPC_DSCR, 0x00000000);
7836 #endif
7837 /*
7838 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
7839 * POWERPC_EXCP_INVAL_SPR.
7840 */
7841 spr_register(env, SPR_PCR, "PCR",
7842 SPR_NOACCESS, SPR_NOACCESS,
7843 SPR_NOACCESS, SPR_NOACCESS,
7844 0x00000000);
7845 }
7846
7847 static void spr_read_tar(DisasContext *ctx, int gprn, int sprn)
7848 {
7849 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
7850 spr_read_generic(ctx, gprn, sprn);
7851 }
7852
7853 static void spr_write_tar(DisasContext *ctx, int sprn, int gprn)
7854 {
7855 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
7856 spr_write_generic(ctx, sprn, gprn);
7857 }
7858
7859 static void gen_spr_power8_tce_address_control(CPUPPCState *env)
7860 {
7861 spr_register_kvm(env, SPR_TAR, "TAR",
7862 &spr_read_tar, &spr_write_tar,
7863 &spr_read_generic, &spr_write_generic,
7864 KVM_REG_PPC_TAR, 0x00000000);
7865 }
7866
7867 static void spr_read_tm(DisasContext *ctx, int gprn, int sprn)
7868 {
7869 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
7870 spr_read_generic(ctx, gprn, sprn);
7871 }
7872
7873 static void spr_write_tm(DisasContext *ctx, int sprn, int gprn)
7874 {
7875 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
7876 spr_write_generic(ctx, sprn, gprn);
7877 }
7878
7879 static void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn)
7880 {
7881 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
7882 spr_read_prev_upper32(ctx, gprn, sprn);
7883 }
7884
7885 static void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn)
7886 {
7887 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
7888 spr_write_prev_upper32(ctx, sprn, gprn);
7889 }
7890
7891 static void gen_spr_power8_tm(CPUPPCState *env)
7892 {
7893 spr_register_kvm(env, SPR_TFHAR, "TFHAR",
7894 &spr_read_tm, &spr_write_tm,
7895 &spr_read_tm, &spr_write_tm,
7896 KVM_REG_PPC_TFHAR, 0x00000000);
7897 spr_register_kvm(env, SPR_TFIAR, "TFIAR",
7898 &spr_read_tm, &spr_write_tm,
7899 &spr_read_tm, &spr_write_tm,
7900 KVM_REG_PPC_TFIAR, 0x00000000);
7901 spr_register_kvm(env, SPR_TEXASR, "TEXASR",
7902 &spr_read_tm, &spr_write_tm,
7903 &spr_read_tm, &spr_write_tm,
7904 KVM_REG_PPC_TEXASR, 0x00000000);
7905 spr_register(env, SPR_TEXASRU, "TEXASRU",
7906 &spr_read_tm_upper32, &spr_write_tm_upper32,
7907 &spr_read_tm_upper32, &spr_write_tm_upper32,
7908 0x00000000);
7909 }
7910
7911 static void spr_read_ebb(DisasContext *ctx, int gprn, int sprn)
7912 {
7913 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
7914 spr_read_generic(ctx, gprn, sprn);
7915 }
7916
7917 static void spr_write_ebb(DisasContext *ctx, int sprn, int gprn)
7918 {
7919 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
7920 spr_write_generic(ctx, sprn, gprn);
7921 }
7922
7923 static void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn)
7924 {
7925 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
7926 spr_read_prev_upper32(ctx, gprn, sprn);
7927 }
7928
7929 static void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn)
7930 {
7931 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
7932 spr_write_prev_upper32(ctx, sprn, gprn);
7933 }
7934
7935 static void gen_spr_power8_ebb(CPUPPCState *env)
7936 {
7937 spr_register(env, SPR_BESCRS, "BESCRS",
7938 &spr_read_ebb, &spr_write_ebb,
7939 &spr_read_generic, &spr_write_generic,
7940 0x00000000);
7941 spr_register(env, SPR_BESCRSU, "BESCRSU",
7942 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
7943 &spr_read_prev_upper32, &spr_write_prev_upper32,
7944 0x00000000);
7945 spr_register(env, SPR_BESCRR, "BESCRR",
7946 &spr_read_ebb, &spr_write_ebb,
7947 &spr_read_generic, &spr_write_generic,
7948 0x00000000);
7949 spr_register(env, SPR_BESCRRU, "BESCRRU",
7950 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
7951 &spr_read_prev_upper32, &spr_write_prev_upper32,
7952 0x00000000);
7953 spr_register_kvm(env, SPR_EBBHR, "EBBHR",
7954 &spr_read_ebb, &spr_write_ebb,
7955 &spr_read_generic, &spr_write_generic,
7956 KVM_REG_PPC_EBBHR, 0x00000000);
7957 spr_register_kvm(env, SPR_EBBRR, "EBBRR",
7958 &spr_read_ebb, &spr_write_ebb,
7959 &spr_read_generic, &spr_write_generic,
7960 KVM_REG_PPC_EBBRR, 0x00000000);
7961 spr_register_kvm(env, SPR_BESCR, "BESCR",
7962 &spr_read_ebb, &spr_write_ebb,
7963 &spr_read_generic, &spr_write_generic,
7964 KVM_REG_PPC_BESCR, 0x00000000);
7965 }
7966
7967 /* Virtual Time Base */
7968 static void gen_spr_vtb(CPUPPCState *env)
7969 {
7970 spr_register(env, SPR_VTB, "VTB",
7971 SPR_NOACCESS, SPR_NOACCESS,
7972 &spr_read_tbl, SPR_NOACCESS,
7973 0x00000000);
7974 }
7975
7976 static void gen_spr_power8_fscr(CPUPPCState *env)
7977 {
7978 #if defined(CONFIG_USER_ONLY)
7979 target_ulong initval = 1ULL << FSCR_TAR;
7980 #else
7981 target_ulong initval = 0;
7982 #endif
7983 spr_register_kvm(env, SPR_FSCR, "FSCR",
7984 SPR_NOACCESS, SPR_NOACCESS,
7985 &spr_read_generic, &spr_write_generic,
7986 KVM_REG_PPC_FSCR, initval);
7987 }
7988
7989 static void gen_spr_power8_pspb(CPUPPCState *env)
7990 {
7991 spr_register_kvm(env, SPR_PSPB, "PSPB",
7992 SPR_NOACCESS, SPR_NOACCESS,
7993 &spr_read_generic, &spr_write_generic32,
7994 KVM_REG_PPC_PSPB, 0);
7995 }
7996
7997 static void gen_spr_power8_ic(CPUPPCState *env)
7998 {
7999 #if !defined(CONFIG_USER_ONLY)
8000 spr_register_hv(env, SPR_IC, "IC",
8001 SPR_NOACCESS, SPR_NOACCESS,
8002 &spr_read_generic, SPR_NOACCESS,
8003 &spr_read_generic, &spr_write_generic,
8004 0);
8005 #endif
8006 }
8007
8008 static void gen_spr_power8_book4(CPUPPCState *env)
8009 {
8010 /* Add a number of P8 book4 registers */
8011 #if !defined(CONFIG_USER_ONLY)
8012 spr_register_kvm(env, SPR_ACOP, "ACOP",
8013 SPR_NOACCESS, SPR_NOACCESS,
8014 &spr_read_generic, &spr_write_generic,
8015 KVM_REG_PPC_ACOP, 0);
8016 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
8017 SPR_NOACCESS, SPR_NOACCESS,
8018 &spr_read_generic, &spr_write_generic,
8019 KVM_REG_PPC_PID, 0);
8020 spr_register_kvm(env, SPR_WORT, "WORT",
8021 SPR_NOACCESS, SPR_NOACCESS,
8022 &spr_read_generic, &spr_write_generic,
8023 KVM_REG_PPC_WORT, 0);
8024 #endif
8025 }
8026
8027 static void gen_spr_power7_book4(CPUPPCState *env)
8028 {
8029 /* Add a number of P7 book4 registers */
8030 #if !defined(CONFIG_USER_ONLY)
8031 spr_register_kvm(env, SPR_ACOP, "ACOP",
8032 SPR_NOACCESS, SPR_NOACCESS,
8033 &spr_read_generic, &spr_write_generic,
8034 KVM_REG_PPC_ACOP, 0);
8035 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
8036 SPR_NOACCESS, SPR_NOACCESS,
8037 &spr_read_generic, &spr_write_generic,
8038 KVM_REG_PPC_PID, 0);
8039 #endif
8040 }
8041
8042 static void init_proc_book3s_64(CPUPPCState *env, int version)
8043 {
8044 gen_spr_ne_601(env);
8045 gen_tbl(env);
8046 gen_spr_book3s_altivec(env);
8047 gen_spr_book3s_pmu_sup(env);
8048 gen_spr_book3s_pmu_user(env);
8049 gen_spr_book3s_common(env);
8050
8051 switch (version) {
8052 case BOOK3S_CPU_970:
8053 case BOOK3S_CPU_POWER5PLUS:
8054 gen_spr_970_hid(env);
8055 gen_spr_970_hior(env);
8056 gen_low_BATs(env);
8057 gen_spr_970_pmu_sup(env);
8058 gen_spr_970_pmu_user(env);
8059 break;
8060 case BOOK3S_CPU_POWER7:
8061 case BOOK3S_CPU_POWER8:
8062 gen_spr_book3s_ids(env);
8063 gen_spr_amr(env, version >= BOOK3S_CPU_POWER8);
8064 gen_spr_book3s_purr(env);
8065 env->ci_large_pages = true;
8066 break;
8067 default:
8068 g_assert_not_reached();
8069 }
8070 if (version >= BOOK3S_CPU_POWER5PLUS) {
8071 gen_spr_power5p_common(env);
8072 gen_spr_power5p_lpar(env);
8073 gen_spr_power5p_ear(env);
8074 } else {
8075 gen_spr_970_lpar(env);
8076 }
8077 if (version == BOOK3S_CPU_970) {
8078 gen_spr_970_dbg(env);
8079 }
8080 if (version >= BOOK3S_CPU_POWER6) {
8081 gen_spr_power6_common(env);
8082 gen_spr_power6_dbg(env);
8083 }
8084 if (version == BOOK3S_CPU_POWER7) {
8085 gen_spr_power7_book4(env);
8086 }
8087 if (version >= BOOK3S_CPU_POWER8) {
8088 gen_spr_power8_tce_address_control(env);
8089 gen_spr_power8_ids(env);
8090 gen_spr_power8_ebb(env);
8091 gen_spr_power8_fscr(env);
8092 gen_spr_power8_pmu_sup(env);
8093 gen_spr_power8_pmu_user(env);
8094 gen_spr_power8_tm(env);
8095 gen_spr_power8_pspb(env);
8096 gen_spr_vtb(env);
8097 gen_spr_power8_ic(env);
8098 gen_spr_power8_book4(env);
8099 }
8100 if (version < BOOK3S_CPU_POWER8) {
8101 gen_spr_book3s_dbg(env);
8102 } else {
8103 gen_spr_book3s_207_dbg(env);
8104 }
8105 #if !defined(CONFIG_USER_ONLY)
8106 switch (version) {
8107 case BOOK3S_CPU_970:
8108 case BOOK3S_CPU_POWER5PLUS:
8109 env->slb_nr = 64;
8110 break;
8111 case BOOK3S_CPU_POWER7:
8112 case BOOK3S_CPU_POWER8:
8113 default:
8114 env->slb_nr = 32;
8115 break;
8116 }
8117 #endif
8118 /* Allocate hardware IRQ controller */
8119 switch (version) {
8120 case BOOK3S_CPU_970:
8121 case BOOK3S_CPU_POWER5PLUS:
8122 init_excp_970(env);
8123 ppc970_irq_init(ppc_env_get_cpu(env));
8124 break;
8125 case BOOK3S_CPU_POWER7:
8126 case BOOK3S_CPU_POWER8:
8127 init_excp_POWER7(env);
8128 ppcPOWER7_irq_init(ppc_env_get_cpu(env));
8129 break;
8130 default:
8131 g_assert_not_reached();
8132 }
8133
8134 env->dcache_line_size = 128;
8135 env->icache_line_size = 128;
8136 }
8137
8138 static void init_proc_970(CPUPPCState *env)
8139 {
8140 init_proc_book3s_64(env, BOOK3S_CPU_970);
8141 }
8142
8143 POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
8144 {
8145 DeviceClass *dc = DEVICE_CLASS(oc);
8146 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8147
8148 dc->desc = "PowerPC 970";
8149 pcc->init_proc = init_proc_970;
8150 pcc->check_pow = check_pow_970;
8151 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
8152 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8153 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8154 PPC_FLOAT_STFIWX |
8155 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8156 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8157 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8158 PPC_64B | PPC_ALTIVEC |
8159 PPC_SEGMENT_64B | PPC_SLBI;
8160 pcc->insns_flags2 = PPC2_FP_CVT_S64;
8161 pcc->msr_mask = (1ull << MSR_SF) |
8162 (1ull << MSR_VR) |
8163 (1ull << MSR_POW) |
8164 (1ull << MSR_EE) |
8165 (1ull << MSR_PR) |
8166 (1ull << MSR_FP) |
8167 (1ull << MSR_ME) |
8168 (1ull << MSR_FE0) |
8169 (1ull << MSR_SE) |
8170 (1ull << MSR_DE) |
8171 (1ull << MSR_FE1) |
8172 (1ull << MSR_IR) |
8173 (1ull << MSR_DR) |
8174 (1ull << MSR_PMM) |
8175 (1ull << MSR_RI);
8176 pcc->mmu_model = POWERPC_MMU_64B;
8177 #if defined(CONFIG_SOFTMMU)
8178 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8179 #endif
8180 pcc->excp_model = POWERPC_EXCP_970;
8181 pcc->bus_model = PPC_FLAGS_INPUT_970;
8182 pcc->bfd_mach = bfd_mach_ppc64;
8183 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8184 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8185 POWERPC_FLAG_BUS_CLK;
8186 pcc->l1_dcache_size = 0x8000;
8187 pcc->l1_icache_size = 0x10000;
8188 }
8189
8190 static void init_proc_power5plus(CPUPPCState *env)
8191 {
8192 init_proc_book3s_64(env, BOOK3S_CPU_POWER5PLUS);
8193 }
8194
8195 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
8196 {
8197 DeviceClass *dc = DEVICE_CLASS(oc);
8198 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8199
8200 dc->fw_name = "PowerPC,POWER5";
8201 dc->desc = "POWER5+";
8202 pcc->init_proc = init_proc_power5plus;
8203 pcc->check_pow = check_pow_970;
8204 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
8205 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8206 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8207 PPC_FLOAT_STFIWX |
8208 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8209 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8210 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8211 PPC_64B |
8212 PPC_SEGMENT_64B | PPC_SLBI;
8213 pcc->insns_flags2 = PPC2_FP_CVT_S64;
8214 pcc->msr_mask = (1ull << MSR_SF) |
8215 (1ull << MSR_VR) |
8216 (1ull << MSR_POW) |
8217 (1ull << MSR_EE) |
8218 (1ull << MSR_PR) |
8219 (1ull << MSR_FP) |
8220 (1ull << MSR_ME) |
8221 (1ull << MSR_FE0) |
8222 (1ull << MSR_SE) |
8223 (1ull << MSR_DE) |
8224 (1ull << MSR_FE1) |
8225 (1ull << MSR_IR) |
8226 (1ull << MSR_DR) |
8227 (1ull << MSR_PMM) |
8228 (1ull << MSR_RI);
8229 pcc->mmu_model = POWERPC_MMU_2_03;
8230 #if defined(CONFIG_SOFTMMU)
8231 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8232 #endif
8233 pcc->excp_model = POWERPC_EXCP_970;
8234 pcc->bus_model = PPC_FLAGS_INPUT_970;
8235 pcc->bfd_mach = bfd_mach_ppc64;
8236 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8237 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8238 POWERPC_FLAG_BUS_CLK;
8239 pcc->l1_dcache_size = 0x8000;
8240 pcc->l1_icache_size = 0x10000;
8241 }
8242
8243 static void powerpc_get_compat(Object *obj, Visitor *v, const char *name,
8244 void *opaque, Error **errp)
8245 {
8246 char *value = (char *)"";
8247 Property *prop = opaque;
8248 uint32_t *max_compat = qdev_get_prop_ptr(DEVICE(obj), prop);
8249
8250 switch (*max_compat) {
8251 case CPU_POWERPC_LOGICAL_2_05:
8252 value = (char *)"power6";
8253 break;
8254 case CPU_POWERPC_LOGICAL_2_06:
8255 value = (char *)"power7";
8256 break;
8257 case CPU_POWERPC_LOGICAL_2_07:
8258 value = (char *)"power8";
8259 break;
8260 case 0:
8261 break;
8262 default:
8263 error_setg(errp, "Internal error: compat is set to %x",
8264 max_compat ? *max_compat : -1);
8265 break;
8266 }
8267
8268 visit_type_str(v, name, &value, errp);
8269 }
8270
8271 static void powerpc_set_compat(Object *obj, Visitor *v, const char *name,
8272 void *opaque, Error **errp)
8273 {
8274 Error *error = NULL;
8275 char *value = NULL;
8276 Property *prop = opaque;
8277 uint32_t *max_compat = qdev_get_prop_ptr(DEVICE(obj), prop);
8278
8279 visit_type_str(v, name, &value, &error);
8280 if (error) {
8281 error_propagate(errp, error);
8282 return;
8283 }
8284
8285 if (strcmp(value, "power6") == 0) {
8286 *max_compat = CPU_POWERPC_LOGICAL_2_05;
8287 } else if (strcmp(value, "power7") == 0) {
8288 *max_compat = CPU_POWERPC_LOGICAL_2_06;
8289 } else if (strcmp(value, "power8") == 0) {
8290 *max_compat = CPU_POWERPC_LOGICAL_2_07;
8291 } else {
8292 error_setg(errp, "Invalid compatibility mode \"%s\"", value);
8293 }
8294
8295 g_free(value);
8296 }
8297
8298 static PropertyInfo powerpc_compat_propinfo = {
8299 .name = "str",
8300 .description = "compatibility mode, power6/power7/power8",
8301 .get = powerpc_get_compat,
8302 .set = powerpc_set_compat,
8303 };
8304
8305 #define DEFINE_PROP_POWERPC_COMPAT(_n, _s, _f) \
8306 DEFINE_PROP(_n, _s, _f, powerpc_compat_propinfo, uint32_t)
8307
8308 static Property powerpc_servercpu_properties[] = {
8309 DEFINE_PROP_POWERPC_COMPAT("compat", PowerPCCPU, max_compat),
8310 DEFINE_PROP_END_OF_LIST(),
8311 };
8312
8313 #ifdef CONFIG_SOFTMMU
8314 static const struct ppc_segment_page_sizes POWER7_POWER8_sps = {
8315 .sps = {
8316 {
8317 .page_shift = 12, /* 4K */
8318 .slb_enc = 0,
8319 .enc = { { .page_shift = 12, .pte_enc = 0 },
8320 { .page_shift = 16, .pte_enc = 0x7 },
8321 { .page_shift = 24, .pte_enc = 0x38 }, },
8322 },
8323 {
8324 .page_shift = 16, /* 64K */
8325 .slb_enc = SLB_VSID_64K,
8326 .enc = { { .page_shift = 16, .pte_enc = 0x1 },
8327 { .page_shift = 24, .pte_enc = 0x8 }, },
8328 },
8329 {
8330 .page_shift = 24, /* 16M */
8331 .slb_enc = SLB_VSID_16M,
8332 .enc = { { .page_shift = 24, .pte_enc = 0 }, },
8333 },
8334 {
8335 .page_shift = 34, /* 16G */
8336 .slb_enc = SLB_VSID_16G,
8337 .enc = { { .page_shift = 34, .pte_enc = 0x3 }, },
8338 },
8339 }
8340 };
8341 #endif /* CONFIG_SOFTMMU */
8342
8343 static void init_proc_POWER7 (CPUPPCState *env)
8344 {
8345 init_proc_book3s_64(env, BOOK3S_CPU_POWER7);
8346 }
8347
8348 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr)
8349 {
8350 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) {
8351 return true;
8352 }
8353 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) {
8354 return true;
8355 }
8356 return false;
8357 }
8358
8359 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
8360 {
8361 DeviceClass *dc = DEVICE_CLASS(oc);
8362 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8363
8364 dc->fw_name = "PowerPC,POWER7";
8365 dc->desc = "POWER7";
8366 dc->props = powerpc_servercpu_properties;
8367 pcc->pvr_match = ppc_pvr_match_power7;
8368 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05;
8369 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
8370 pcc->init_proc = init_proc_POWER7;
8371 pcc->check_pow = check_pow_nocheck;
8372 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8373 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8374 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8375 PPC_FLOAT_FRSQRTES |
8376 PPC_FLOAT_STFIWX |
8377 PPC_FLOAT_EXT |
8378 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8379 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8380 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8381 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
8382 PPC_SEGMENT_64B | PPC_SLBI |
8383 PPC_POPCNTB | PPC_POPCNTWD;
8384 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
8385 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
8386 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
8387 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64;
8388 pcc->msr_mask = (1ull << MSR_SF) |
8389 (1ull << MSR_VR) |
8390 (1ull << MSR_VSX) |
8391 (1ull << MSR_EE) |
8392 (1ull << MSR_PR) |
8393 (1ull << MSR_FP) |
8394 (1ull << MSR_ME) |
8395 (1ull << MSR_FE0) |
8396 (1ull << MSR_SE) |
8397 (1ull << MSR_DE) |
8398 (1ull << MSR_FE1) |
8399 (1ull << MSR_IR) |
8400 (1ull << MSR_DR) |
8401 (1ull << MSR_PMM) |
8402 (1ull << MSR_RI) |
8403 (1ull << MSR_LE);
8404 pcc->mmu_model = POWERPC_MMU_2_06;
8405 #if defined(CONFIG_SOFTMMU)
8406 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8407 pcc->sps = &POWER7_POWER8_sps;
8408 #endif
8409 pcc->excp_model = POWERPC_EXCP_POWER7;
8410 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
8411 pcc->bfd_mach = bfd_mach_ppc64;
8412 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8413 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8414 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
8415 POWERPC_FLAG_VSX;
8416 pcc->l1_dcache_size = 0x8000;
8417 pcc->l1_icache_size = 0x8000;
8418 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
8419 }
8420
8421 static void init_proc_POWER8(CPUPPCState *env)
8422 {
8423 init_proc_book3s_64(env, BOOK3S_CPU_POWER8);
8424 }
8425
8426 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr)
8427 {
8428 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) {
8429 return true;
8430 }
8431 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) {
8432 return true;
8433 }
8434 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) {
8435 return true;
8436 }
8437 return false;
8438 }
8439
8440 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
8441 {
8442 DeviceClass *dc = DEVICE_CLASS(oc);
8443 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8444
8445 dc->fw_name = "PowerPC,POWER8";
8446 dc->desc = "POWER8";
8447 dc->props = powerpc_servercpu_properties;
8448 pcc->pvr_match = ppc_pvr_match_power8;
8449 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
8450 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
8451 pcc->init_proc = init_proc_POWER8;
8452 pcc->check_pow = check_pow_nocheck;
8453 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8454 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8455 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8456 PPC_FLOAT_FRSQRTES |
8457 PPC_FLOAT_STFIWX |
8458 PPC_FLOAT_EXT |
8459 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8460 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8461 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8462 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
8463 PPC_SEGMENT_64B | PPC_SLBI |
8464 PPC_POPCNTB | PPC_POPCNTWD;
8465 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
8466 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
8467 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
8468 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
8469 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
8470 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
8471 PPC2_TM;
8472 pcc->msr_mask = (1ull << MSR_SF) |
8473 (1ull << MSR_SHV) |
8474 (1ull << MSR_TM) |
8475 (1ull << MSR_VR) |
8476 (1ull << MSR_VSX) |
8477 (1ull << MSR_EE) |
8478 (1ull << MSR_PR) |
8479 (1ull << MSR_FP) |
8480 (1ull << MSR_ME) |
8481 (1ull << MSR_FE0) |
8482 (1ull << MSR_SE) |
8483 (1ull << MSR_DE) |
8484 (1ull << MSR_FE1) |
8485 (1ull << MSR_IR) |
8486 (1ull << MSR_DR) |
8487 (1ull << MSR_PMM) |
8488 (1ull << MSR_RI) |
8489 (1ull << MSR_LE);
8490 pcc->mmu_model = POWERPC_MMU_2_07;
8491 #if defined(CONFIG_SOFTMMU)
8492 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8493 pcc->sps = &POWER7_POWER8_sps;
8494 #endif
8495 pcc->excp_model = POWERPC_EXCP_POWER8;
8496 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
8497 pcc->bfd_mach = bfd_mach_ppc64;
8498 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8499 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8500 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
8501 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
8502 pcc->l1_dcache_size = 0x8000;
8503 pcc->l1_icache_size = 0x8000;
8504 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
8505 }
8506
8507 #if !defined(CONFIG_USER_ONLY)
8508
8509 void cpu_ppc_set_papr(PowerPCCPU *cpu)
8510 {
8511 CPUPPCState *env = &cpu->env;
8512 ppc_spr_t *amor = &env->spr_cb[SPR_AMOR];
8513
8514 /* PAPR always has exception vectors in RAM not ROM. To ensure this,
8515 * MSR[IP] should never be set.
8516 *
8517 * We also disallow setting of MSR_HV
8518 */
8519 env->msr_mask &= ~((1ull << MSR_EP) | MSR_HVB);
8520
8521 /* Set a full AMOR so guest can use the AMR as it sees fit */
8522 env->spr[SPR_AMOR] = amor->default_value = 0xffffffffffffffffull;
8523
8524 /* Tell KVM that we're in PAPR mode */
8525 if (kvm_enabled()) {
8526 kvmppc_set_papr(cpu);
8527 }
8528 }
8529
8530 #endif /* !defined(CONFIG_USER_ONLY) */
8531
8532 #endif /* defined (TARGET_PPC64) */
8533
8534 /*****************************************************************************/
8535 /* Generic CPU instantiation routine */
8536 static void init_ppc_proc(PowerPCCPU *cpu)
8537 {
8538 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8539 CPUPPCState *env = &cpu->env;
8540 #if !defined(CONFIG_USER_ONLY)
8541 int i;
8542
8543 env->irq_inputs = NULL;
8544 /* Set all exception vectors to an invalid address */
8545 for (i = 0; i < POWERPC_EXCP_NB; i++)
8546 env->excp_vectors[i] = (target_ulong)(-1ULL);
8547 env->ivor_mask = 0x00000000;
8548 env->ivpr_mask = 0x00000000;
8549 /* Default MMU definitions */
8550 env->nb_BATs = 0;
8551 env->nb_tlb = 0;
8552 env->nb_ways = 0;
8553 env->tlb_type = TLB_NONE;
8554 #endif
8555 /* Register SPR common to all PowerPC implementations */
8556 gen_spr_generic(env);
8557 spr_register(env, SPR_PVR, "PVR",
8558 /* Linux permits userspace to read PVR */
8559 #if defined(CONFIG_LINUX_USER)
8560 &spr_read_generic,
8561 #else
8562 SPR_NOACCESS,
8563 #endif
8564 SPR_NOACCESS,
8565 &spr_read_generic, SPR_NOACCESS,
8566 pcc->pvr);
8567 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
8568 if (pcc->svr != POWERPC_SVR_NONE) {
8569 if (pcc->svr & POWERPC_SVR_E500) {
8570 spr_register(env, SPR_E500_SVR, "SVR",
8571 SPR_NOACCESS, SPR_NOACCESS,
8572 &spr_read_generic, SPR_NOACCESS,
8573 pcc->svr & ~POWERPC_SVR_E500);
8574 } else {
8575 spr_register(env, SPR_SVR, "SVR",
8576 SPR_NOACCESS, SPR_NOACCESS,
8577 &spr_read_generic, SPR_NOACCESS,
8578 pcc->svr);
8579 }
8580 }
8581 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
8582 (*pcc->init_proc)(env);
8583
8584 /* MSR bits & flags consistency checks */
8585 if (env->msr_mask & (1 << 25)) {
8586 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8587 case POWERPC_FLAG_SPE:
8588 case POWERPC_FLAG_VRE:
8589 break;
8590 default:
8591 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8592 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
8593 exit(1);
8594 }
8595 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8596 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8597 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
8598 exit(1);
8599 }
8600 if (env->msr_mask & (1 << 17)) {
8601 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8602 case POWERPC_FLAG_TGPR:
8603 case POWERPC_FLAG_CE:
8604 break;
8605 default:
8606 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8607 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
8608 exit(1);
8609 }
8610 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8611 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8612 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
8613 exit(1);
8614 }
8615 if (env->msr_mask & (1 << 10)) {
8616 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8617 POWERPC_FLAG_UBLE)) {
8618 case POWERPC_FLAG_SE:
8619 case POWERPC_FLAG_DWE:
8620 case POWERPC_FLAG_UBLE:
8621 break;
8622 default:
8623 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8624 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
8625 "POWERPC_FLAG_UBLE\n");
8626 exit(1);
8627 }
8628 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8629 POWERPC_FLAG_UBLE)) {
8630 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8631 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
8632 "POWERPC_FLAG_UBLE\n");
8633 exit(1);
8634 }
8635 if (env->msr_mask & (1 << 9)) {
8636 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8637 case POWERPC_FLAG_BE:
8638 case POWERPC_FLAG_DE:
8639 break;
8640 default:
8641 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8642 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
8643 exit(1);
8644 }
8645 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8646 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8647 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
8648 exit(1);
8649 }
8650 if (env->msr_mask & (1 << 2)) {
8651 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8652 case POWERPC_FLAG_PX:
8653 case POWERPC_FLAG_PMM:
8654 break;
8655 default:
8656 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8657 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
8658 exit(1);
8659 }
8660 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8661 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8662 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
8663 exit(1);
8664 }
8665 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
8666 fprintf(stderr, "PowerPC flags inconsistency\n"
8667 "Should define the time-base and decrementer clock source\n");
8668 exit(1);
8669 }
8670 /* Allocate TLBs buffer when needed */
8671 #if !defined(CONFIG_USER_ONLY)
8672 if (env->nb_tlb != 0) {
8673 int nb_tlb = env->nb_tlb;
8674 if (env->id_tlbs != 0)
8675 nb_tlb *= 2;
8676 switch (env->tlb_type) {
8677 case TLB_6XX:
8678 env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
8679 break;
8680 case TLB_EMB:
8681 env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
8682 break;
8683 case TLB_MAS:
8684 env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
8685 break;
8686 }
8687 /* Pre-compute some useful values */
8688 env->tlb_per_way = env->nb_tlb / env->nb_ways;
8689 }
8690 if (env->irq_inputs == NULL) {
8691 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
8692 " Attempt QEMU to crash very soon !\n");
8693 }
8694 #endif
8695 if (env->check_pow == NULL) {
8696 fprintf(stderr, "WARNING: no power management check handler "
8697 "registered.\n"
8698 " Attempt QEMU to crash very soon !\n");
8699 }
8700 }
8701
8702 #if defined(PPC_DUMP_CPU)
8703 static void dump_ppc_sprs (CPUPPCState *env)
8704 {
8705 ppc_spr_t *spr;
8706 #if !defined(CONFIG_USER_ONLY)
8707 uint32_t sr, sw;
8708 #endif
8709 uint32_t ur, uw;
8710 int i, j, n;
8711
8712 printf("Special purpose registers:\n");
8713 for (i = 0; i < 32; i++) {
8714 for (j = 0; j < 32; j++) {
8715 n = (i << 5) | j;
8716 spr = &env->spr_cb[n];
8717 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
8718 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
8719 #if !defined(CONFIG_USER_ONLY)
8720 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
8721 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
8722 if (sw || sr || uw || ur) {
8723 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
8724 (i << 5) | j, (i << 5) | j, spr->name,
8725 sw ? 'w' : '-', sr ? 'r' : '-',
8726 uw ? 'w' : '-', ur ? 'r' : '-');
8727 }
8728 #else
8729 if (uw || ur) {
8730 printf("SPR: %4d (%03x) %-8s u%c%c\n",
8731 (i << 5) | j, (i << 5) | j, spr->name,
8732 uw ? 'w' : '-', ur ? 'r' : '-');
8733 }
8734 #endif
8735 }
8736 }
8737 fflush(stdout);
8738 fflush(stderr);
8739 }
8740 #endif
8741
8742 /*****************************************************************************/
8743
8744 /* Opcode types */
8745 enum {
8746 PPC_DIRECT = 0, /* Opcode routine */
8747 PPC_INDIRECT = 1, /* Indirect opcode table */
8748 };
8749
8750 #define PPC_OPCODE_MASK 0x3
8751
8752 static inline int is_indirect_opcode (void *handler)
8753 {
8754 return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT;
8755 }
8756
8757 static inline opc_handler_t **ind_table(void *handler)
8758 {
8759 return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK);
8760 }
8761
8762 /* Instruction table creation */
8763 /* Opcodes tables creation */
8764 static void fill_new_table (opc_handler_t **table, int len)
8765 {
8766 int i;
8767
8768 for (i = 0; i < len; i++)
8769 table[i] = &invalid_handler;
8770 }
8771
8772 static int create_new_table (opc_handler_t **table, unsigned char idx)
8773 {
8774 opc_handler_t **tmp;
8775
8776 tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN);
8777 fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN);
8778 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
8779
8780 return 0;
8781 }
8782
8783 static int insert_in_table (opc_handler_t **table, unsigned char idx,
8784 opc_handler_t *handler)
8785 {
8786 if (table[idx] != &invalid_handler)
8787 return -1;
8788 table[idx] = handler;
8789
8790 return 0;
8791 }
8792
8793 static int register_direct_insn (opc_handler_t **ppc_opcodes,
8794 unsigned char idx, opc_handler_t *handler)
8795 {
8796 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
8797 printf("*** ERROR: opcode %02x already assigned in main "
8798 "opcode table\n", idx);
8799 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8800 printf(" Registered handler '%s' - new handler '%s'\n",
8801 ppc_opcodes[idx]->oname, handler->oname);
8802 #endif
8803 return -1;
8804 }
8805
8806 return 0;
8807 }
8808
8809 static int register_ind_in_table (opc_handler_t **table,
8810 unsigned char idx1, unsigned char idx2,
8811 opc_handler_t *handler)
8812 {
8813 if (table[idx1] == &invalid_handler) {
8814 if (create_new_table(table, idx1) < 0) {
8815 printf("*** ERROR: unable to create indirect table "
8816 "idx=%02x\n", idx1);
8817 return -1;
8818 }
8819 } else {
8820 if (!is_indirect_opcode(table[idx1])) {
8821 printf("*** ERROR: idx %02x already assigned to a direct "
8822 "opcode\n", idx1);
8823 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8824 printf(" Registered handler '%s' - new handler '%s'\n",
8825 ind_table(table[idx1])[idx2]->oname, handler->oname);
8826 #endif
8827 return -1;
8828 }
8829 }
8830 if (handler != NULL &&
8831 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
8832 printf("*** ERROR: opcode %02x already assigned in "
8833 "opcode table %02x\n", idx2, idx1);
8834 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8835 printf(" Registered handler '%s' - new handler '%s'\n",
8836 ind_table(table[idx1])[idx2]->oname, handler->oname);
8837 #endif
8838 return -1;
8839 }
8840
8841 return 0;
8842 }
8843
8844 static int register_ind_insn (opc_handler_t **ppc_opcodes,
8845 unsigned char idx1, unsigned char idx2,
8846 opc_handler_t *handler)
8847 {
8848 return register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
8849 }
8850
8851 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
8852 unsigned char idx1, unsigned char idx2,
8853 unsigned char idx3, opc_handler_t *handler)
8854 {
8855 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
8856 printf("*** ERROR: unable to join indirect table idx "
8857 "[%02x-%02x]\n", idx1, idx2);
8858 return -1;
8859 }
8860 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
8861 handler) < 0) {
8862 printf("*** ERROR: unable to insert opcode "
8863 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
8864 return -1;
8865 }
8866
8867 return 0;
8868 }
8869
8870 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
8871 {
8872 if (insn->opc2 != 0xFF) {
8873 if (insn->opc3 != 0xFF) {
8874 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
8875 insn->opc3, &insn->handler) < 0)
8876 return -1;
8877 } else {
8878 if (register_ind_insn(ppc_opcodes, insn->opc1,
8879 insn->opc2, &insn->handler) < 0)
8880 return -1;
8881 }
8882 } else {
8883 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
8884 return -1;
8885 }
8886
8887 return 0;
8888 }
8889
8890 static int test_opcode_table (opc_handler_t **table, int len)
8891 {
8892 int i, count, tmp;
8893
8894 for (i = 0, count = 0; i < len; i++) {
8895 /* Consistency fixup */
8896 if (table[i] == NULL)
8897 table[i] = &invalid_handler;
8898 if (table[i] != &invalid_handler) {
8899 if (is_indirect_opcode(table[i])) {
8900 tmp = test_opcode_table(ind_table(table[i]),
8901 PPC_CPU_INDIRECT_OPCODES_LEN);
8902 if (tmp == 0) {
8903 free(table[i]);
8904 table[i] = &invalid_handler;
8905 } else {
8906 count++;
8907 }
8908 } else {
8909 count++;
8910 }
8911 }
8912 }
8913
8914 return count;
8915 }
8916
8917 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
8918 {
8919 if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0)
8920 printf("*** WARNING: no opcode defined !\n");
8921 }
8922
8923 /*****************************************************************************/
8924 static void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
8925 {
8926 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8927 CPUPPCState *env = &cpu->env;
8928 opcode_t *opc;
8929
8930 fill_new_table(env->opcodes, PPC_CPU_OPCODES_LEN);
8931 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
8932 if (((opc->handler.type & pcc->insns_flags) != 0) ||
8933 ((opc->handler.type2 & pcc->insns_flags2) != 0)) {
8934 if (register_insn(env->opcodes, opc) < 0) {
8935 error_setg(errp, "ERROR initializing PowerPC instruction "
8936 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2,
8937 opc->opc3);
8938 return;
8939 }
8940 }
8941 }
8942 fix_opcode_tables(env->opcodes);
8943 fflush(stdout);
8944 fflush(stderr);
8945 }
8946
8947 #if defined(PPC_DUMP_CPU)
8948 static void dump_ppc_insns (CPUPPCState *env)
8949 {
8950 opc_handler_t **table, *handler;
8951 const char *p, *q;
8952 uint8_t opc1, opc2, opc3;
8953
8954 printf("Instructions set:\n");
8955 /* opc1 is 6 bits long */
8956 for (opc1 = 0x00; opc1 < PPC_CPU_OPCODES_LEN; opc1++) {
8957 table = env->opcodes;
8958 handler = table[opc1];
8959 if (is_indirect_opcode(handler)) {
8960 /* opc2 is 5 bits long */
8961 for (opc2 = 0; opc2 < PPC_CPU_INDIRECT_OPCODES_LEN; opc2++) {
8962 table = env->opcodes;
8963 handler = env->opcodes[opc1];
8964 table = ind_table(handler);
8965 handler = table[opc2];
8966 if (is_indirect_opcode(handler)) {
8967 table = ind_table(handler);
8968 /* opc3 is 5 bits long */
8969 for (opc3 = 0; opc3 < PPC_CPU_INDIRECT_OPCODES_LEN;
8970 opc3++) {
8971 handler = table[opc3];
8972 if (handler->handler != &gen_invalid) {
8973 /* Special hack to properly dump SPE insns */
8974 p = strchr(handler->oname, '_');
8975 if (p == NULL) {
8976 printf("INSN: %02x %02x %02x (%02d %04d) : "
8977 "%s\n",
8978 opc1, opc2, opc3, opc1,
8979 (opc3 << 5) | opc2,
8980 handler->oname);
8981 } else {
8982 q = "speundef";
8983 if ((p - handler->oname) != strlen(q) ||
8984 memcmp(handler->oname, q, strlen(q)) != 0) {
8985 /* First instruction */
8986 printf("INSN: %02x %02x %02x (%02d %04d) : "
8987 "%.*s\n",
8988 opc1, opc2 << 1, opc3, opc1,
8989 (opc3 << 6) | (opc2 << 1),
8990 (int)(p - handler->oname),
8991 handler->oname);
8992 }
8993 if (strcmp(p + 1, q) != 0) {
8994 /* Second instruction */
8995 printf("INSN: %02x %02x %02x (%02d %04d) : "
8996 "%s\n",
8997 opc1, (opc2 << 1) | 1, opc3, opc1,
8998 (opc3 << 6) | (opc2 << 1) | 1,
8999 p + 1);
9000 }
9001 }
9002 }
9003 }
9004 } else {
9005 if (handler->handler != &gen_invalid) {
9006 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9007 opc1, opc2, opc1, opc2, handler->oname);
9008 }
9009 }
9010 }
9011 } else {
9012 if (handler->handler != &gen_invalid) {
9013 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9014 opc1, opc1, handler->oname);
9015 }
9016 }
9017 }
9018 }
9019 #endif
9020
9021 static bool avr_need_swap(CPUPPCState *env)
9022 {
9023 #ifdef HOST_WORDS_BIGENDIAN
9024 return msr_le;
9025 #else
9026 return !msr_le;
9027 #endif
9028 }
9029
9030 static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9031 {
9032 if (n < 32) {
9033 stfq_p(mem_buf, env->fpr[n]);
9034 ppc_maybe_bswap_register(env, mem_buf, 8);
9035 return 8;
9036 }
9037 if (n == 32) {
9038 stl_p(mem_buf, env->fpscr);
9039 ppc_maybe_bswap_register(env, mem_buf, 4);
9040 return 4;
9041 }
9042 return 0;
9043 }
9044
9045 static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9046 {
9047 if (n < 32) {
9048 ppc_maybe_bswap_register(env, mem_buf, 8);
9049 env->fpr[n] = ldfq_p(mem_buf);
9050 return 8;
9051 }
9052 if (n == 32) {
9053 ppc_maybe_bswap_register(env, mem_buf, 4);
9054 helper_store_fpscr(env, ldl_p(mem_buf), 0xffffffff);
9055 return 4;
9056 }
9057 return 0;
9058 }
9059
9060 static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9061 {
9062 if (n < 32) {
9063 if (!avr_need_swap(env)) {
9064 stq_p(mem_buf, env->avr[n].u64[0]);
9065 stq_p(mem_buf+8, env->avr[n].u64[1]);
9066 } else {
9067 stq_p(mem_buf, env->avr[n].u64[1]);
9068 stq_p(mem_buf+8, env->avr[n].u64[0]);
9069 }
9070 ppc_maybe_bswap_register(env, mem_buf, 8);
9071 ppc_maybe_bswap_register(env, mem_buf + 8, 8);
9072 return 16;
9073 }
9074 if (n == 32) {
9075 stl_p(mem_buf, env->vscr);
9076 ppc_maybe_bswap_register(env, mem_buf, 4);
9077 return 4;
9078 }
9079 if (n == 33) {
9080 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
9081 ppc_maybe_bswap_register(env, mem_buf, 4);
9082 return 4;
9083 }
9084 return 0;
9085 }
9086
9087 static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9088 {
9089 if (n < 32) {
9090 ppc_maybe_bswap_register(env, mem_buf, 8);
9091 ppc_maybe_bswap_register(env, mem_buf + 8, 8);
9092 if (!avr_need_swap(env)) {
9093 env->avr[n].u64[0] = ldq_p(mem_buf);
9094 env->avr[n].u64[1] = ldq_p(mem_buf+8);
9095 } else {
9096 env->avr[n].u64[1] = ldq_p(mem_buf);
9097 env->avr[n].u64[0] = ldq_p(mem_buf+8);
9098 }
9099 return 16;
9100 }
9101 if (n == 32) {
9102 ppc_maybe_bswap_register(env, mem_buf, 4);
9103 env->vscr = ldl_p(mem_buf);
9104 return 4;
9105 }
9106 if (n == 33) {
9107 ppc_maybe_bswap_register(env, mem_buf, 4);
9108 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
9109 return 4;
9110 }
9111 return 0;
9112 }
9113
9114 static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9115 {
9116 if (n < 32) {
9117 #if defined(TARGET_PPC64)
9118 stl_p(mem_buf, env->gpr[n] >> 32);
9119 ppc_maybe_bswap_register(env, mem_buf, 4);
9120 #else
9121 stl_p(mem_buf, env->gprh[n]);
9122 #endif
9123 return 4;
9124 }
9125 if (n == 32) {
9126 stq_p(mem_buf, env->spe_acc);
9127 ppc_maybe_bswap_register(env, mem_buf, 8);
9128 return 8;
9129 }
9130 if (n == 33) {
9131 stl_p(mem_buf, env->spe_fscr);
9132 ppc_maybe_bswap_register(env, mem_buf, 4);
9133 return 4;
9134 }
9135 return 0;
9136 }
9137
9138 static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9139 {
9140 if (n < 32) {
9141 #if defined(TARGET_PPC64)
9142 target_ulong lo = (uint32_t)env->gpr[n];
9143 target_ulong hi;
9144
9145 ppc_maybe_bswap_register(env, mem_buf, 4);
9146
9147 hi = (target_ulong)ldl_p(mem_buf) << 32;
9148 env->gpr[n] = lo | hi;
9149 #else
9150 env->gprh[n] = ldl_p(mem_buf);
9151 #endif
9152 return 4;
9153 }
9154 if (n == 32) {
9155 ppc_maybe_bswap_register(env, mem_buf, 8);
9156 env->spe_acc = ldq_p(mem_buf);
9157 return 8;
9158 }
9159 if (n == 33) {
9160 ppc_maybe_bswap_register(env, mem_buf, 4);
9161 env->spe_fscr = ldl_p(mem_buf);
9162 return 4;
9163 }
9164 return 0;
9165 }
9166
9167 static int gdb_get_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9168 {
9169 if (n < 32) {
9170 stq_p(mem_buf, env->vsr[n]);
9171 ppc_maybe_bswap_register(env, mem_buf, 8);
9172 return 8;
9173 }
9174 return 0;
9175 }
9176
9177 static int gdb_set_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9178 {
9179 if (n < 32) {
9180 ppc_maybe_bswap_register(env, mem_buf, 8);
9181 env->vsr[n] = ldq_p(mem_buf);
9182 return 8;
9183 }
9184 return 0;
9185 }
9186
9187 static int ppc_fixup_cpu(PowerPCCPU *cpu)
9188 {
9189 CPUPPCState *env = &cpu->env;
9190
9191 /* TCG doesn't (yet) emulate some groups of instructions that
9192 * are implemented on some otherwise supported CPUs (e.g. VSX
9193 * and decimal floating point instructions on POWER7). We
9194 * remove unsupported instruction groups from the cpu state's
9195 * instruction masks and hope the guest can cope. For at
9196 * least the pseries machine, the unavailability of these
9197 * instructions can be advertised to the guest via the device
9198 * tree. */
9199 if ((env->insns_flags & ~PPC_TCG_INSNS)
9200 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
9201 fprintf(stderr, "Warning: Disabling some instructions which are not "
9202 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")\n",
9203 env->insns_flags & ~PPC_TCG_INSNS,
9204 env->insns_flags2 & ~PPC_TCG_INSNS2);
9205 }
9206 env->insns_flags &= PPC_TCG_INSNS;
9207 env->insns_flags2 &= PPC_TCG_INSNS2;
9208 return 0;
9209 }
9210
9211 static inline bool ppc_cpu_is_valid(PowerPCCPUClass *pcc)
9212 {
9213 #ifdef TARGET_PPCEMB
9214 return pcc->mmu_model == POWERPC_MMU_BOOKE ||
9215 pcc->mmu_model == POWERPC_MMU_SOFT_4xx ||
9216 pcc->mmu_model == POWERPC_MMU_SOFT_4xx_Z;
9217 #else
9218 return true;
9219 #endif
9220 }
9221
9222 static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
9223 {
9224 CPUState *cs = CPU(dev);
9225 PowerPCCPU *cpu = POWERPC_CPU(dev);
9226 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9227 Error *local_err = NULL;
9228 #if !defined(CONFIG_USER_ONLY)
9229 int max_smt = kvm_enabled() ? kvmppc_smt_threads() : 1;
9230 #endif
9231
9232 #if !defined(CONFIG_USER_ONLY)
9233 if (smp_threads > max_smt) {
9234 error_setg(errp, "Cannot support more than %d threads on PPC with %s",
9235 max_smt, kvm_enabled() ? "KVM" : "TCG");
9236 return;
9237 }
9238 if (!is_power_of_2(smp_threads)) {
9239 error_setg(errp, "Cannot support %d threads on PPC with %s, "
9240 "threads count must be a power of 2.",
9241 smp_threads, kvm_enabled() ? "KVM" : "TCG");
9242 return;
9243 }
9244 #endif
9245
9246 cpu_exec_init(cs, &local_err);
9247 if (local_err != NULL) {
9248 error_propagate(errp, local_err);
9249 return;
9250 }
9251
9252 #if !defined(CONFIG_USER_ONLY)
9253 cpu->cpu_dt_id = (cs->cpu_index / smp_threads) * max_smt
9254 + (cs->cpu_index % smp_threads);
9255
9256 if (kvm_enabled() && !kvm_vcpu_id_is_valid(cpu->cpu_dt_id)) {
9257 error_setg(errp, "Can't create CPU with id %d in KVM", cpu->cpu_dt_id);
9258 error_append_hint(errp, "Adjust the number of cpus to %d "
9259 "or try to raise the number of threads per core\n",
9260 cpu->cpu_dt_id * smp_threads / max_smt);
9261 return;
9262 }
9263 #endif
9264
9265 if (tcg_enabled()) {
9266 if (ppc_fixup_cpu(cpu) != 0) {
9267 error_setg(errp, "Unable to emulate selected CPU with TCG");
9268 return;
9269 }
9270 }
9271
9272 #if defined(TARGET_PPCEMB)
9273 if (!ppc_cpu_is_valid(pcc)) {
9274 error_setg(errp, "CPU does not possess a BookE or 4xx MMU. "
9275 "Please use qemu-system-ppc or qemu-system-ppc64 instead "
9276 "or choose another CPU model.");
9277 return;
9278 }
9279 #endif
9280
9281 create_ppc_opcodes(cpu, &local_err);
9282 if (local_err != NULL) {
9283 error_propagate(errp, local_err);
9284 return;
9285 }
9286 init_ppc_proc(cpu);
9287
9288 if (pcc->insns_flags & PPC_FLOAT) {
9289 gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg,
9290 33, "power-fpu.xml", 0);
9291 }
9292 if (pcc->insns_flags & PPC_ALTIVEC) {
9293 gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg,
9294 34, "power-altivec.xml", 0);
9295 }
9296 if (pcc->insns_flags & PPC_SPE) {
9297 gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg,
9298 34, "power-spe.xml", 0);
9299 }
9300 if (pcc->insns_flags2 & PPC2_VSX) {
9301 gdb_register_coprocessor(cs, gdb_get_vsx_reg, gdb_set_vsx_reg,
9302 32, "power-vsx.xml", 0);
9303 }
9304
9305 qemu_init_vcpu(cs);
9306
9307 pcc->parent_realize(dev, errp);
9308
9309 #if defined(PPC_DUMP_CPU)
9310 {
9311 CPUPPCState *env = &cpu->env;
9312 const char *mmu_model, *excp_model, *bus_model;
9313 switch (env->mmu_model) {
9314 case POWERPC_MMU_32B:
9315 mmu_model = "PowerPC 32";
9316 break;
9317 case POWERPC_MMU_SOFT_6xx:
9318 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
9319 break;
9320 case POWERPC_MMU_SOFT_74xx:
9321 mmu_model = "PowerPC 74xx with software driven TLBs";
9322 break;
9323 case POWERPC_MMU_SOFT_4xx:
9324 mmu_model = "PowerPC 4xx with software driven TLBs";
9325 break;
9326 case POWERPC_MMU_SOFT_4xx_Z:
9327 mmu_model = "PowerPC 4xx with software driven TLBs "
9328 "and zones protections";
9329 break;
9330 case POWERPC_MMU_REAL:
9331 mmu_model = "PowerPC real mode only";
9332 break;
9333 case POWERPC_MMU_MPC8xx:
9334 mmu_model = "PowerPC MPC8xx";
9335 break;
9336 case POWERPC_MMU_BOOKE:
9337 mmu_model = "PowerPC BookE";
9338 break;
9339 case POWERPC_MMU_BOOKE206:
9340 mmu_model = "PowerPC BookE 2.06";
9341 break;
9342 case POWERPC_MMU_601:
9343 mmu_model = "PowerPC 601";
9344 break;
9345 #if defined (TARGET_PPC64)
9346 case POWERPC_MMU_64B:
9347 mmu_model = "PowerPC 64";
9348 break;
9349 #endif
9350 default:
9351 mmu_model = "Unknown or invalid";
9352 break;
9353 }
9354 switch (env->excp_model) {
9355 case POWERPC_EXCP_STD:
9356 excp_model = "PowerPC";
9357 break;
9358 case POWERPC_EXCP_40x:
9359 excp_model = "PowerPC 40x";
9360 break;
9361 case POWERPC_EXCP_601:
9362 excp_model = "PowerPC 601";
9363 break;
9364 case POWERPC_EXCP_602:
9365 excp_model = "PowerPC 602";
9366 break;
9367 case POWERPC_EXCP_603:
9368 excp_model = "PowerPC 603";
9369 break;
9370 case POWERPC_EXCP_603E:
9371 excp_model = "PowerPC 603e";
9372 break;
9373 case POWERPC_EXCP_604:
9374 excp_model = "PowerPC 604";
9375 break;
9376 case POWERPC_EXCP_7x0:
9377 excp_model = "PowerPC 740/750";
9378 break;
9379 case POWERPC_EXCP_7x5:
9380 excp_model = "PowerPC 745/755";
9381 break;
9382 case POWERPC_EXCP_74xx:
9383 excp_model = "PowerPC 74xx";
9384 break;
9385 case POWERPC_EXCP_BOOKE:
9386 excp_model = "PowerPC BookE";
9387 break;
9388 #if defined (TARGET_PPC64)
9389 case POWERPC_EXCP_970:
9390 excp_model = "PowerPC 970";
9391 break;
9392 #endif
9393 default:
9394 excp_model = "Unknown or invalid";
9395 break;
9396 }
9397 switch (env->bus_model) {
9398 case PPC_FLAGS_INPUT_6xx:
9399 bus_model = "PowerPC 6xx";
9400 break;
9401 case PPC_FLAGS_INPUT_BookE:
9402 bus_model = "PowerPC BookE";
9403 break;
9404 case PPC_FLAGS_INPUT_405:
9405 bus_model = "PowerPC 405";
9406 break;
9407 case PPC_FLAGS_INPUT_401:
9408 bus_model = "PowerPC 401/403";
9409 break;
9410 case PPC_FLAGS_INPUT_RCPU:
9411 bus_model = "RCPU / MPC8xx";
9412 break;
9413 #if defined (TARGET_PPC64)
9414 case PPC_FLAGS_INPUT_970:
9415 bus_model = "PowerPC 970";
9416 break;
9417 #endif
9418 default:
9419 bus_model = "Unknown or invalid";
9420 break;
9421 }
9422 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
9423 " MMU model : %s\n",
9424 object_class_get_name(OBJECT_CLASS(pcc)),
9425 pcc->pvr, pcc->msr_mask, mmu_model);
9426 #if !defined(CONFIG_USER_ONLY)
9427 if (env->tlb.tlb6) {
9428 printf(" %d %s TLB in %d ways\n",
9429 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
9430 env->nb_ways);
9431 }
9432 #endif
9433 printf(" Exceptions model : %s\n"
9434 " Bus model : %s\n",
9435 excp_model, bus_model);
9436 printf(" MSR features :\n");
9437 if (env->flags & POWERPC_FLAG_SPE)
9438 printf(" signal processing engine enable"
9439 "\n");
9440 else if (env->flags & POWERPC_FLAG_VRE)
9441 printf(" vector processor enable\n");
9442 if (env->flags & POWERPC_FLAG_TGPR)
9443 printf(" temporary GPRs\n");
9444 else if (env->flags & POWERPC_FLAG_CE)
9445 printf(" critical input enable\n");
9446 if (env->flags & POWERPC_FLAG_SE)
9447 printf(" single-step trace mode\n");
9448 else if (env->flags & POWERPC_FLAG_DWE)
9449 printf(" debug wait enable\n");
9450 else if (env->flags & POWERPC_FLAG_UBLE)
9451 printf(" user BTB lock enable\n");
9452 if (env->flags & POWERPC_FLAG_BE)
9453 printf(" branch-step trace mode\n");
9454 else if (env->flags & POWERPC_FLAG_DE)
9455 printf(" debug interrupt enable\n");
9456 if (env->flags & POWERPC_FLAG_PX)
9457 printf(" inclusive protection\n");
9458 else if (env->flags & POWERPC_FLAG_PMM)
9459 printf(" performance monitor mark\n");
9460 if (env->flags == POWERPC_FLAG_NONE)
9461 printf(" none\n");
9462 printf(" Time-base/decrementer clock source: %s\n",
9463 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
9464 dump_ppc_insns(env);
9465 dump_ppc_sprs(env);
9466 fflush(stdout);
9467 }
9468 #endif
9469 }
9470
9471 static void ppc_cpu_unrealizefn(DeviceState *dev, Error **errp)
9472 {
9473 PowerPCCPU *cpu = POWERPC_CPU(dev);
9474 CPUPPCState *env = &cpu->env;
9475 opc_handler_t **table;
9476 int i, j;
9477
9478 cpu_exec_exit(CPU(dev));
9479
9480 for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) {
9481 if (env->opcodes[i] == &invalid_handler) {
9482 continue;
9483 }
9484 if (is_indirect_opcode(env->opcodes[i])) {
9485 table = ind_table(env->opcodes[i]);
9486 for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) {
9487 if (table[j] != &invalid_handler &&
9488 is_indirect_opcode(table[j])) {
9489 g_free((opc_handler_t *)((uintptr_t)table[j] &
9490 ~PPC_INDIRECT));
9491 }
9492 }
9493 g_free((opc_handler_t *)((uintptr_t)env->opcodes[i] &
9494 ~PPC_INDIRECT));
9495 }
9496 }
9497 }
9498
9499 int ppc_get_compat_smt_threads(PowerPCCPU *cpu)
9500 {
9501 int ret = MIN(smp_threads, kvmppc_smt_threads());
9502
9503 switch (cpu->cpu_version) {
9504 case CPU_POWERPC_LOGICAL_2_05:
9505 ret = MIN(ret, 2);
9506 break;
9507 case CPU_POWERPC_LOGICAL_2_06:
9508 ret = MIN(ret, 4);
9509 break;
9510 case CPU_POWERPC_LOGICAL_2_07:
9511 ret = MIN(ret, 8);
9512 break;
9513 }
9514
9515 return ret;
9516 }
9517
9518 #ifdef TARGET_PPC64
9519 void ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version, Error **errp)
9520 {
9521 int ret = 0;
9522 CPUPPCState *env = &cpu->env;
9523 PowerPCCPUClass *host_pcc;
9524
9525 cpu->cpu_version = cpu_version;
9526
9527 switch (cpu_version) {
9528 case CPU_POWERPC_LOGICAL_2_05:
9529 env->spr[SPR_PCR] = PCR_TM_DIS | PCR_VSX_DIS | PCR_COMPAT_2_07 |
9530 PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
9531 break;
9532 case CPU_POWERPC_LOGICAL_2_06:
9533 case CPU_POWERPC_LOGICAL_2_06_PLUS:
9534 env->spr[SPR_PCR] = PCR_TM_DIS | PCR_COMPAT_2_07 | PCR_COMPAT_2_06;
9535 break;
9536 case CPU_POWERPC_LOGICAL_2_07:
9537 env->spr[SPR_PCR] = PCR_COMPAT_2_07;
9538 break;
9539 default:
9540 env->spr[SPR_PCR] = 0;
9541 break;
9542 }
9543
9544 host_pcc = kvm_ppc_get_host_cpu_class();
9545 if (host_pcc) {
9546 env->spr[SPR_PCR] &= host_pcc->pcr_mask;
9547 }
9548
9549 if (kvm_enabled()) {
9550 ret = kvmppc_set_compat(cpu, cpu->cpu_version);
9551 if (ret < 0) {
9552 error_setg_errno(errp, -ret,
9553 "Unable to set CPU compatibility mode in KVM");
9554 }
9555 }
9556 }
9557 #endif
9558
9559 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
9560 {
9561 ObjectClass *oc = (ObjectClass *)a;
9562 uint32_t pvr = *(uint32_t *)b;
9563 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
9564
9565 /* -cpu host does a PVR lookup during construction */
9566 if (unlikely(strcmp(object_class_get_name(oc),
9567 TYPE_HOST_POWERPC_CPU) == 0)) {
9568 return -1;
9569 }
9570
9571 if (!ppc_cpu_is_valid(pcc)) {
9572 return -1;
9573 }
9574
9575 return pcc->pvr == pvr ? 0 : -1;
9576 }
9577
9578 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
9579 {
9580 GSList *list, *item;
9581 PowerPCCPUClass *pcc = NULL;
9582
9583 list = object_class_get_list(TYPE_POWERPC_CPU, false);
9584 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
9585 if (item != NULL) {
9586 pcc = POWERPC_CPU_CLASS(item->data);
9587 }
9588 g_slist_free(list);
9589
9590 return pcc;
9591 }
9592
9593 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
9594 {
9595 ObjectClass *oc = (ObjectClass *)a;
9596 uint32_t pvr = *(uint32_t *)b;
9597 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
9598
9599 /* -cpu host does a PVR lookup during construction */
9600 if (unlikely(strcmp(object_class_get_name(oc),
9601 TYPE_HOST_POWERPC_CPU) == 0)) {
9602 return -1;
9603 }
9604
9605 if (!ppc_cpu_is_valid(pcc)) {
9606 return -1;
9607 }
9608
9609 if (pcc->pvr_match(pcc, pvr)) {
9610 return 0;
9611 }
9612
9613 return -1;
9614 }
9615
9616 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
9617 {
9618 GSList *list, *item;
9619 PowerPCCPUClass *pcc = NULL;
9620
9621 list = object_class_get_list(TYPE_POWERPC_CPU, true);
9622 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
9623 if (item != NULL) {
9624 pcc = POWERPC_CPU_CLASS(item->data);
9625 }
9626 g_slist_free(list);
9627
9628 return pcc;
9629 }
9630
9631 static gint ppc_cpu_compare_class_name(gconstpointer a, gconstpointer b)
9632 {
9633 ObjectClass *oc = (ObjectClass *)a;
9634 const char *name = b;
9635 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
9636
9637 if (strncasecmp(name, object_class_get_name(oc), strlen(name)) == 0 &&
9638 ppc_cpu_is_valid(pcc) &&
9639 strcmp(object_class_get_name(oc) + strlen(name),
9640 "-" TYPE_POWERPC_CPU) == 0) {
9641 return 0;
9642 }
9643 return -1;
9644 }
9645
9646
9647 static ObjectClass *ppc_cpu_class_by_name(const char *name);
9648
9649 static ObjectClass *ppc_cpu_class_by_alias(PowerPCCPUAlias *alias)
9650 {
9651 ObjectClass *invalid_class = (void*)ppc_cpu_class_by_alias;
9652
9653 /* Cache target class lookups in the alias table */
9654 if (!alias->oc) {
9655 alias->oc = ppc_cpu_class_by_name(alias->model);
9656 if (!alias->oc) {
9657 /* Fast check for non-existing aliases */
9658 alias->oc = invalid_class;
9659 }
9660 }
9661
9662 if (alias->oc == invalid_class) {
9663 return NULL;
9664 } else {
9665 return alias->oc;
9666 }
9667 }
9668
9669 static ObjectClass *ppc_cpu_class_by_name(const char *name)
9670 {
9671 GSList *list, *item;
9672 ObjectClass *ret = NULL;
9673 const char *p;
9674 int i, len;
9675
9676 /* Check if the given name is a PVR */
9677 len = strlen(name);
9678 if (len == 10 && name[0] == '0' && name[1] == 'x') {
9679 p = name + 2;
9680 goto check_pvr;
9681 } else if (len == 8) {
9682 p = name;
9683 check_pvr:
9684 for (i = 0; i < 8; i++) {
9685 if (!qemu_isxdigit(*p++))
9686 break;
9687 }
9688 if (i == 8) {
9689 return OBJECT_CLASS(ppc_cpu_class_by_pvr(strtoul(name, NULL, 16)));
9690 }
9691 }
9692
9693 list = object_class_get_list(TYPE_POWERPC_CPU, false);
9694 item = g_slist_find_custom(list, name, ppc_cpu_compare_class_name);
9695 if (item != NULL) {
9696 ret = OBJECT_CLASS(item->data);
9697 }
9698 g_slist_free(list);
9699
9700 if (ret) {
9701 return ret;
9702 }
9703
9704 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
9705 if (strcmp(ppc_cpu_aliases[i].alias, name) == 0) {
9706 return ppc_cpu_class_by_alias(&ppc_cpu_aliases[i]);
9707 }
9708 }
9709
9710 return NULL;
9711 }
9712
9713 PowerPCCPU *cpu_ppc_init(const char *cpu_model)
9714 {
9715 return POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, cpu_model));
9716 }
9717
9718 /* Sort by PVR, ordering special case "host" last. */
9719 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
9720 {
9721 ObjectClass *oc_a = (ObjectClass *)a;
9722 ObjectClass *oc_b = (ObjectClass *)b;
9723 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
9724 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
9725 const char *name_a = object_class_get_name(oc_a);
9726 const char *name_b = object_class_get_name(oc_b);
9727
9728 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
9729 return 1;
9730 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
9731 return -1;
9732 } else {
9733 /* Avoid an integer overflow during subtraction */
9734 if (pcc_a->pvr < pcc_b->pvr) {
9735 return -1;
9736 } else if (pcc_a->pvr > pcc_b->pvr) {
9737 return 1;
9738 } else {
9739 return 0;
9740 }
9741 }
9742 }
9743
9744 static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
9745 {
9746 ObjectClass *oc = data;
9747 CPUListState *s = user_data;
9748 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
9749 const char *typename = object_class_get_name(oc);
9750 char *name;
9751 int i;
9752
9753 if (!ppc_cpu_is_valid(pcc)) {
9754 return;
9755 }
9756 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
9757 return;
9758 }
9759
9760 name = g_strndup(typename,
9761 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
9762 (*s->cpu_fprintf)(s->file, "PowerPC %-16s PVR %08x\n",
9763 name, pcc->pvr);
9764 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
9765 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
9766 ObjectClass *alias_oc = ppc_cpu_class_by_alias(alias);
9767
9768 if (alias_oc != oc) {
9769 continue;
9770 }
9771 (*s->cpu_fprintf)(s->file, "PowerPC %-16s (alias for %s)\n",
9772 alias->alias, name);
9773 }
9774 g_free(name);
9775 }
9776
9777 void ppc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
9778 {
9779 CPUListState s = {
9780 .file = f,
9781 .cpu_fprintf = cpu_fprintf,
9782 };
9783 GSList *list;
9784
9785 list = object_class_get_list(TYPE_POWERPC_CPU, false);
9786 list = g_slist_sort(list, ppc_cpu_list_compare);
9787 g_slist_foreach(list, ppc_cpu_list_entry, &s);
9788 g_slist_free(list);
9789
9790 #ifdef CONFIG_KVM
9791 cpu_fprintf(f, "\n");
9792 cpu_fprintf(f, "PowerPC %-16s\n", "host");
9793 #endif
9794 }
9795
9796 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
9797 {
9798 ObjectClass *oc = data;
9799 CpuDefinitionInfoList **first = user_data;
9800 const char *typename;
9801 CpuDefinitionInfoList *entry;
9802 CpuDefinitionInfo *info;
9803 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
9804
9805 if (!ppc_cpu_is_valid(pcc)) {
9806 return;
9807 }
9808
9809 typename = object_class_get_name(oc);
9810 info = g_malloc0(sizeof(*info));
9811 info->name = g_strndup(typename,
9812 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
9813
9814 entry = g_malloc0(sizeof(*entry));
9815 entry->value = info;
9816 entry->next = *first;
9817 *first = entry;
9818 }
9819
9820 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
9821 {
9822 CpuDefinitionInfoList *cpu_list = NULL;
9823 GSList *list;
9824 int i;
9825
9826 list = object_class_get_list(TYPE_POWERPC_CPU, false);
9827 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
9828 g_slist_free(list);
9829
9830 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
9831 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
9832 ObjectClass *oc;
9833 CpuDefinitionInfoList *entry;
9834 CpuDefinitionInfo *info;
9835
9836 oc = ppc_cpu_class_by_alias(alias);
9837 if (oc == NULL) {
9838 continue;
9839 }
9840
9841 info = g_malloc0(sizeof(*info));
9842 info->name = g_strdup(alias->alias);
9843
9844 entry = g_malloc0(sizeof(*entry));
9845 entry->value = info;
9846 entry->next = cpu_list;
9847 cpu_list = entry;
9848 }
9849
9850 return cpu_list;
9851 }
9852
9853 static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
9854 {
9855 PowerPCCPU *cpu = POWERPC_CPU(cs);
9856
9857 cpu->env.nip = value;
9858 }
9859
9860 static bool ppc_cpu_has_work(CPUState *cs)
9861 {
9862 PowerPCCPU *cpu = POWERPC_CPU(cs);
9863 CPUPPCState *env = &cpu->env;
9864
9865 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
9866 }
9867
9868 static void ppc_cpu_exec_enter(CPUState *cs)
9869 {
9870 PowerPCCPU *cpu = POWERPC_CPU(cs);
9871 CPUPPCState *env = &cpu->env;
9872
9873 env->reserve_addr = -1;
9874 }
9875
9876 /* CPUClass::reset() */
9877 static void ppc_cpu_reset(CPUState *s)
9878 {
9879 PowerPCCPU *cpu = POWERPC_CPU(s);
9880 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9881 CPUPPCState *env = &cpu->env;
9882 target_ulong msr;
9883 int i;
9884
9885 pcc->parent_reset(s);
9886
9887 msr = (target_ulong)0;
9888 msr |= (target_ulong)MSR_HVB;
9889 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
9890 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
9891 msr |= (target_ulong)1 << MSR_EP;
9892 #if defined(DO_SINGLE_STEP) && 0
9893 /* Single step trace mode */
9894 msr |= (target_ulong)1 << MSR_SE;
9895 msr |= (target_ulong)1 << MSR_BE;
9896 #endif
9897 #if defined(CONFIG_USER_ONLY)
9898 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
9899 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
9900 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
9901 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
9902 msr |= (target_ulong)1 << MSR_PR;
9903 #if defined(TARGET_PPC64)
9904 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */
9905 #endif
9906 #if !defined(TARGET_WORDS_BIGENDIAN)
9907 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
9908 if (!((env->msr_mask >> MSR_LE) & 1)) {
9909 fprintf(stderr, "Selected CPU does not support little-endian.\n");
9910 exit(1);
9911 }
9912 #endif
9913 #endif
9914
9915 #if defined(TARGET_PPC64)
9916 if (env->mmu_model & POWERPC_MMU_64) {
9917 msr |= (1ULL << MSR_SF);
9918 }
9919 #endif
9920
9921 hreg_store_msr(env, msr, 1);
9922
9923 #if !defined(CONFIG_USER_ONLY)
9924 env->nip = env->hreset_vector | env->excp_prefix;
9925 if (env->mmu_model != POWERPC_MMU_REAL) {
9926 ppc_tlb_invalidate_all(env);
9927 }
9928 #endif
9929
9930 hreg_compute_hflags(env);
9931 env->reserve_addr = (target_ulong)-1ULL;
9932 /* Be sure no exception or interrupt is pending */
9933 env->pending_interrupts = 0;
9934 s->exception_index = POWERPC_EXCP_NONE;
9935 env->error_code = 0;
9936
9937 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
9938 env->vpa_addr = 0;
9939 env->slb_shadow_addr = 0;
9940 env->slb_shadow_size = 0;
9941 env->dtl_addr = 0;
9942 env->dtl_size = 0;
9943 #endif /* TARGET_PPC64 */
9944
9945 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
9946 ppc_spr_t *spr = &env->spr_cb[i];
9947
9948 if (!spr->name) {
9949 continue;
9950 }
9951 env->spr[i] = spr->default_value;
9952 }
9953
9954 /* Flush all TLBs */
9955 tlb_flush(s, 1);
9956 }
9957
9958 #ifndef CONFIG_USER_ONLY
9959 static bool ppc_cpu_is_big_endian(CPUState *cs)
9960 {
9961 PowerPCCPU *cpu = POWERPC_CPU(cs);
9962 CPUPPCState *env = &cpu->env;
9963
9964 cpu_synchronize_state(cs);
9965
9966 return !msr_le;
9967 }
9968 #endif
9969
9970 static void ppc_cpu_initfn(Object *obj)
9971 {
9972 CPUState *cs = CPU(obj);
9973 PowerPCCPU *cpu = POWERPC_CPU(obj);
9974 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9975 CPUPPCState *env = &cpu->env;
9976
9977 cs->env_ptr = env;
9978
9979 env->msr_mask = pcc->msr_mask;
9980 env->mmu_model = pcc->mmu_model;
9981 env->excp_model = pcc->excp_model;
9982 env->bus_model = pcc->bus_model;
9983 env->insns_flags = pcc->insns_flags;
9984 env->insns_flags2 = pcc->insns_flags2;
9985 env->flags = pcc->flags;
9986 env->bfd_mach = pcc->bfd_mach;
9987 env->check_pow = pcc->check_pow;
9988
9989 /* Mark HV mode as supported if the CPU has an MSR_HV bit
9990 * in the msr_mask. The mask can later be cleared by PAPR
9991 * mode but the hv mode support will remain, thus enforcing
9992 * that we cannot use priv. instructions in guest in PAPR
9993 * mode. For 970 we currently simply don't set HV in msr_mask
9994 * thus simulating an "Apple mode" 970. If we ever want to
9995 * support 970 HV mode, we'll have to add a processor attribute
9996 * of some sort.
9997 */
9998 #if !defined(CONFIG_USER_ONLY)
9999 env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
10000 #endif
10001
10002 #if defined(TARGET_PPC64)
10003 if (pcc->sps) {
10004 env->sps = *pcc->sps;
10005 } else if (env->mmu_model & POWERPC_MMU_64) {
10006 /* Use default sets of page sizes */
10007 static const struct ppc_segment_page_sizes defsps = {
10008 .sps = {
10009 { .page_shift = 12, /* 4K */
10010 .slb_enc = 0,
10011 .enc = { { .page_shift = 12, .pte_enc = 0 } }
10012 },
10013 { .page_shift = 24, /* 16M */
10014 .slb_enc = 0x100,
10015 .enc = { { .page_shift = 24, .pte_enc = 0 } }
10016 },
10017 },
10018 };
10019 env->sps = defsps;
10020 }
10021 #endif /* defined(TARGET_PPC64) */
10022
10023 if (tcg_enabled()) {
10024 ppc_translate_init();
10025 }
10026 }
10027
10028 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr)
10029 {
10030 return pcc->pvr == pvr;
10031 }
10032
10033 static gchar *ppc_gdb_arch_name(CPUState *cs)
10034 {
10035 #if defined(TARGET_PPC64)
10036 return g_strdup("powerpc:common64");
10037 #else
10038 return g_strdup("powerpc:common");
10039 #endif
10040 }
10041
10042 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
10043 {
10044 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10045 CPUClass *cc = CPU_CLASS(oc);
10046 DeviceClass *dc = DEVICE_CLASS(oc);
10047
10048 pcc->parent_realize = dc->realize;
10049 pcc->pvr_match = ppc_pvr_match_default;
10050 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always;
10051 dc->realize = ppc_cpu_realizefn;
10052 dc->unrealize = ppc_cpu_unrealizefn;
10053
10054 pcc->parent_reset = cc->reset;
10055 cc->reset = ppc_cpu_reset;
10056
10057 cc->class_by_name = ppc_cpu_class_by_name;
10058 cc->has_work = ppc_cpu_has_work;
10059 cc->do_interrupt = ppc_cpu_do_interrupt;
10060 cc->cpu_exec_interrupt = ppc_cpu_exec_interrupt;
10061 cc->dump_state = ppc_cpu_dump_state;
10062 cc->dump_statistics = ppc_cpu_dump_statistics;
10063 cc->set_pc = ppc_cpu_set_pc;
10064 cc->gdb_read_register = ppc_cpu_gdb_read_register;
10065 cc->gdb_write_register = ppc_cpu_gdb_write_register;
10066 #ifdef CONFIG_USER_ONLY
10067 cc->handle_mmu_fault = ppc_cpu_handle_mmu_fault;
10068 #else
10069 cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
10070 cc->vmsd = &vmstate_ppc_cpu;
10071 #if defined(TARGET_PPC64)
10072 cc->write_elf64_note = ppc64_cpu_write_elf64_note;
10073 #endif
10074 #endif
10075 cc->cpu_exec_enter = ppc_cpu_exec_enter;
10076
10077 cc->gdb_num_core_regs = 71;
10078
10079 #ifdef USE_APPLE_GDB
10080 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple;
10081 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple;
10082 cc->gdb_num_core_regs = 71 + 32;
10083 #endif
10084
10085 cc->gdb_arch_name = ppc_gdb_arch_name;
10086 #if defined(TARGET_PPC64)
10087 cc->gdb_core_xml_file = "power64-core.xml";
10088 #else
10089 cc->gdb_core_xml_file = "power-core.xml";
10090 #endif
10091 #ifndef CONFIG_USER_ONLY
10092 cc->virtio_is_big_endian = ppc_cpu_is_big_endian;
10093 #endif
10094
10095 dc->fw_name = "PowerPC,UNKNOWN";
10096 }
10097
10098 static const TypeInfo ppc_cpu_type_info = {
10099 .name = TYPE_POWERPC_CPU,
10100 .parent = TYPE_CPU,
10101 .instance_size = sizeof(PowerPCCPU),
10102 .instance_init = ppc_cpu_initfn,
10103 .abstract = true,
10104 .class_size = sizeof(PowerPCCPUClass),
10105 .class_init = ppc_cpu_class_init,
10106 };
10107
10108 static void ppc_cpu_register_types(void)
10109 {
10110 type_register_static(&ppc_cpu_type_info);
10111 }
10112
10113 type_init(ppc_cpu_register_types)
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