hw/arm/aspeed: Introduce TYPE_ASPEED2400_SOC
[qemu/kevin.git] / include / hw / arm / aspeed_soc.h
blobee7926b81cc6098ef995196c735b7889c0aab303
1 /*
2 * ASPEED SoC family
4 * Andrew Jeffery <andrew@aj.id.au>
6 * Copyright 2016 IBM Corp.
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
12 #ifndef ASPEED_SOC_H
13 #define ASPEED_SOC_H
15 #include "hw/cpu/a15mpcore.h"
16 #include "hw/arm/armv7m.h"
17 #include "hw/intc/aspeed_vic.h"
18 #include "hw/misc/aspeed_scu.h"
19 #include "hw/adc/aspeed_adc.h"
20 #include "hw/misc/aspeed_sdmc.h"
21 #include "hw/misc/aspeed_xdma.h"
22 #include "hw/timer/aspeed_timer.h"
23 #include "hw/rtc/aspeed_rtc.h"
24 #include "hw/i2c/aspeed_i2c.h"
25 #include "hw/misc/aspeed_i3c.h"
26 #include "hw/ssi/aspeed_smc.h"
27 #include "hw/misc/aspeed_hace.h"
28 #include "hw/misc/aspeed_sbc.h"
29 #include "hw/watchdog/wdt_aspeed.h"
30 #include "hw/net/ftgmac100.h"
31 #include "target/arm/cpu.h"
32 #include "hw/gpio/aspeed_gpio.h"
33 #include "hw/sd/aspeed_sdhci.h"
34 #include "hw/usb/hcd-ehci.h"
35 #include "qom/object.h"
36 #include "hw/misc/aspeed_lpc.h"
37 #include "hw/misc/unimp.h"
38 #include "hw/misc/aspeed_peci.h"
39 #include "hw/char/serial.h"
41 #define ASPEED_SPIS_NUM 2
42 #define ASPEED_EHCIS_NUM 2
43 #define ASPEED_WDTS_NUM 4
44 #define ASPEED_CPUS_NUM 2
45 #define ASPEED_MACS_NUM 4
46 #define ASPEED_UARTS_NUM 13
47 #define ASPEED_JTAG_NUM 2
49 struct AspeedSoCState {
50 /*< private >*/
51 DeviceState parent;
53 /*< public >*/
54 ARMCPU cpu[ASPEED_CPUS_NUM];
55 A15MPPrivState a7mpcore;
56 ARMv7MState armv7m;
57 MemoryRegion *memory;
58 MemoryRegion *dram_mr;
59 MemoryRegion dram_container;
60 MemoryRegion sram;
61 MemoryRegion spi_boot_container;
62 MemoryRegion spi_boot;
63 AspeedVICState vic;
64 AspeedRtcState rtc;
65 AspeedTimerCtrlState timerctrl;
66 AspeedI2CState i2c;
67 AspeedI3CState i3c;
68 AspeedSCUState scu;
69 AspeedHACEState hace;
70 AspeedXDMAState xdma;
71 AspeedADCState adc;
72 AspeedSMCState fmc;
73 AspeedSMCState spi[ASPEED_SPIS_NUM];
74 EHCISysBusState ehci[ASPEED_EHCIS_NUM];
75 AspeedSBCState sbc;
76 MemoryRegion secsram;
77 UnimplementedDeviceState sbc_unimplemented;
78 AspeedSDMCState sdmc;
79 AspeedWDTState wdt[ASPEED_WDTS_NUM];
80 FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
81 AspeedMiiState mii[ASPEED_MACS_NUM];
82 AspeedGPIOState gpio;
83 AspeedGPIOState gpio_1_8v;
84 AspeedSDHCIState sdhci;
85 AspeedSDHCIState emmc;
86 AspeedLPCState lpc;
87 AspeedPECIState peci;
88 SerialMM uart[ASPEED_UARTS_NUM];
89 Clock *sysclk;
90 UnimplementedDeviceState iomem;
91 UnimplementedDeviceState video;
92 UnimplementedDeviceState emmc_boot_controller;
93 UnimplementedDeviceState dpmcu;
94 UnimplementedDeviceState pwm;
95 UnimplementedDeviceState espi;
96 UnimplementedDeviceState udc;
97 UnimplementedDeviceState sgpiom;
98 UnimplementedDeviceState jtag[ASPEED_JTAG_NUM];
101 #define TYPE_ASPEED_SOC "aspeed-soc"
102 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
104 struct Aspeed2400SoCState {
105 AspeedSoCState parent;
108 #define TYPE_ASPEED2400_SOC "aspeed2400-soc"
109 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC)
111 struct Aspeed2600SoCState {
112 AspeedSoCState parent;
115 #define TYPE_ASPEED2600_SOC "aspeed2600-soc"
116 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC)
118 struct Aspeed10x0SoCState {
119 AspeedSoCState parent;
122 #define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
123 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC)
125 struct AspeedSoCClass {
126 DeviceClass parent_class;
128 const char *name;
129 const char *cpu_type;
130 uint32_t silicon_rev;
131 uint64_t sram_size;
132 uint64_t secsram_size;
133 int spis_num;
134 int ehcis_num;
135 int wdts_num;
136 int macs_num;
137 int uarts_num;
138 const int *irqmap;
139 const hwaddr *memmap;
140 uint32_t num_cpus;
141 qemu_irq (*get_irq)(AspeedSoCState *s, int dev);
145 enum {
146 ASPEED_DEV_SPI_BOOT,
147 ASPEED_DEV_IOMEM,
148 ASPEED_DEV_UART1,
149 ASPEED_DEV_UART2,
150 ASPEED_DEV_UART3,
151 ASPEED_DEV_UART4,
152 ASPEED_DEV_UART5,
153 ASPEED_DEV_UART6,
154 ASPEED_DEV_UART7,
155 ASPEED_DEV_UART8,
156 ASPEED_DEV_UART9,
157 ASPEED_DEV_UART10,
158 ASPEED_DEV_UART11,
159 ASPEED_DEV_UART12,
160 ASPEED_DEV_UART13,
161 ASPEED_DEV_VUART,
162 ASPEED_DEV_FMC,
163 ASPEED_DEV_SPI1,
164 ASPEED_DEV_SPI2,
165 ASPEED_DEV_EHCI1,
166 ASPEED_DEV_EHCI2,
167 ASPEED_DEV_VIC,
168 ASPEED_DEV_SDMC,
169 ASPEED_DEV_SCU,
170 ASPEED_DEV_ADC,
171 ASPEED_DEV_SBC,
172 ASPEED_DEV_SECSRAM,
173 ASPEED_DEV_EMMC_BC,
174 ASPEED_DEV_VIDEO,
175 ASPEED_DEV_SRAM,
176 ASPEED_DEV_SDHCI,
177 ASPEED_DEV_GPIO,
178 ASPEED_DEV_GPIO_1_8V,
179 ASPEED_DEV_RTC,
180 ASPEED_DEV_TIMER1,
181 ASPEED_DEV_TIMER2,
182 ASPEED_DEV_TIMER3,
183 ASPEED_DEV_TIMER4,
184 ASPEED_DEV_TIMER5,
185 ASPEED_DEV_TIMER6,
186 ASPEED_DEV_TIMER7,
187 ASPEED_DEV_TIMER8,
188 ASPEED_DEV_WDT,
189 ASPEED_DEV_PWM,
190 ASPEED_DEV_LPC,
191 ASPEED_DEV_IBT,
192 ASPEED_DEV_I2C,
193 ASPEED_DEV_PECI,
194 ASPEED_DEV_ETH1,
195 ASPEED_DEV_ETH2,
196 ASPEED_DEV_ETH3,
197 ASPEED_DEV_ETH4,
198 ASPEED_DEV_MII1,
199 ASPEED_DEV_MII2,
200 ASPEED_DEV_MII3,
201 ASPEED_DEV_MII4,
202 ASPEED_DEV_SDRAM,
203 ASPEED_DEV_XDMA,
204 ASPEED_DEV_EMMC,
205 ASPEED_DEV_KCS,
206 ASPEED_DEV_HACE,
207 ASPEED_DEV_DPMCU,
208 ASPEED_DEV_DP,
209 ASPEED_DEV_I3C,
210 ASPEED_DEV_ESPI,
211 ASPEED_DEV_UDC,
212 ASPEED_DEV_SGPIOM,
213 ASPEED_DEV_JTAG0,
214 ASPEED_DEV_JTAG1,
217 #define ASPEED_SOC_SPI_BOOT_ADDR 0x0
219 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev);
220 bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp);
221 void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr);
222 bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp);
223 void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr);
224 void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
225 const char *name, hwaddr addr,
226 uint64_t size);
227 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
228 unsigned int count, int unit0);
230 #endif /* ASPEED_SOC_H */