2 * QEMU Cadence GEM emulation
4 * Copyright (c) 2011 Xilinx, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include <zlib.h> /* For crc32 */
28 #include "hw/net/cadence_gem.h"
29 #include "net/checksum.h"
31 #ifdef CADENCE_GEM_ERR_DEBUG
32 #define DB_PRINT(...) do { \
33 fprintf(stderr, ": %s: ", __func__); \
34 fprintf(stderr, ## __VA_ARGS__); \
40 #define GEM_NWCTRL (0x00000000/4) /* Network Control reg */
41 #define GEM_NWCFG (0x00000004/4) /* Network Config reg */
42 #define GEM_NWSTATUS (0x00000008/4) /* Network Status reg */
43 #define GEM_USERIO (0x0000000C/4) /* User IO reg */
44 #define GEM_DMACFG (0x00000010/4) /* DMA Control reg */
45 #define GEM_TXSTATUS (0x00000014/4) /* TX Status reg */
46 #define GEM_RXQBASE (0x00000018/4) /* RX Q Base address reg */
47 #define GEM_TXQBASE (0x0000001C/4) /* TX Q Base address reg */
48 #define GEM_RXSTATUS (0x00000020/4) /* RX Status reg */
49 #define GEM_ISR (0x00000024/4) /* Interrupt Status reg */
50 #define GEM_IER (0x00000028/4) /* Interrupt Enable reg */
51 #define GEM_IDR (0x0000002C/4) /* Interrupt Disable reg */
52 #define GEM_IMR (0x00000030/4) /* Interrupt Mask reg */
53 #define GEM_PHYMNTNC (0x00000034/4) /* Phy Maintenance reg */
54 #define GEM_RXPAUSE (0x00000038/4) /* RX Pause Time reg */
55 #define GEM_TXPAUSE (0x0000003C/4) /* TX Pause Time reg */
56 #define GEM_TXPARTIALSF (0x00000040/4) /* TX Partial Store and Forward */
57 #define GEM_RXPARTIALSF (0x00000044/4) /* RX Partial Store and Forward */
58 #define GEM_HASHLO (0x00000080/4) /* Hash Low address reg */
59 #define GEM_HASHHI (0x00000084/4) /* Hash High address reg */
60 #define GEM_SPADDR1LO (0x00000088/4) /* Specific addr 1 low reg */
61 #define GEM_SPADDR1HI (0x0000008C/4) /* Specific addr 1 high reg */
62 #define GEM_SPADDR2LO (0x00000090/4) /* Specific addr 2 low reg */
63 #define GEM_SPADDR2HI (0x00000094/4) /* Specific addr 2 high reg */
64 #define GEM_SPADDR3LO (0x00000098/4) /* Specific addr 3 low reg */
65 #define GEM_SPADDR3HI (0x0000009C/4) /* Specific addr 3 high reg */
66 #define GEM_SPADDR4LO (0x000000A0/4) /* Specific addr 4 low reg */
67 #define GEM_SPADDR4HI (0x000000A4/4) /* Specific addr 4 high reg */
68 #define GEM_TIDMATCH1 (0x000000A8/4) /* Type ID1 Match reg */
69 #define GEM_TIDMATCH2 (0x000000AC/4) /* Type ID2 Match reg */
70 #define GEM_TIDMATCH3 (0x000000B0/4) /* Type ID3 Match reg */
71 #define GEM_TIDMATCH4 (0x000000B4/4) /* Type ID4 Match reg */
72 #define GEM_WOLAN (0x000000B8/4) /* Wake on LAN reg */
73 #define GEM_IPGSTRETCH (0x000000BC/4) /* IPG Stretch reg */
74 #define GEM_SVLAN (0x000000C0/4) /* Stacked VLAN reg */
75 #define GEM_MODID (0x000000FC/4) /* Module ID reg */
76 #define GEM_OCTTXLO (0x00000100/4) /* Octects transmitted Low reg */
77 #define GEM_OCTTXHI (0x00000104/4) /* Octects transmitted High reg */
78 #define GEM_TXCNT (0x00000108/4) /* Error-free Frames transmitted */
79 #define GEM_TXBCNT (0x0000010C/4) /* Error-free Broadcast Frames */
80 #define GEM_TXMCNT (0x00000110/4) /* Error-free Multicast Frame */
81 #define GEM_TXPAUSECNT (0x00000114/4) /* Pause Frames Transmitted */
82 #define GEM_TX64CNT (0x00000118/4) /* Error-free 64 TX */
83 #define GEM_TX65CNT (0x0000011C/4) /* Error-free 65-127 TX */
84 #define GEM_TX128CNT (0x00000120/4) /* Error-free 128-255 TX */
85 #define GEM_TX256CNT (0x00000124/4) /* Error-free 256-511 */
86 #define GEM_TX512CNT (0x00000128/4) /* Error-free 512-1023 TX */
87 #define GEM_TX1024CNT (0x0000012C/4) /* Error-free 1024-1518 TX */
88 #define GEM_TX1519CNT (0x00000130/4) /* Error-free larger than 1519 TX */
89 #define GEM_TXURUNCNT (0x00000134/4) /* TX under run error counter */
90 #define GEM_SINGLECOLLCNT (0x00000138/4) /* Single Collision Frames */
91 #define GEM_MULTCOLLCNT (0x0000013C/4) /* Multiple Collision Frames */
92 #define GEM_EXCESSCOLLCNT (0x00000140/4) /* Excessive Collision Frames */
93 #define GEM_LATECOLLCNT (0x00000144/4) /* Late Collision Frames */
94 #define GEM_DEFERTXCNT (0x00000148/4) /* Deferred Transmission Frames */
95 #define GEM_CSENSECNT (0x0000014C/4) /* Carrier Sense Error Counter */
96 #define GEM_OCTRXLO (0x00000150/4) /* Octects Received register Low */
97 #define GEM_OCTRXHI (0x00000154/4) /* Octects Received register High */
98 #define GEM_RXCNT (0x00000158/4) /* Error-free Frames Received */
99 #define GEM_RXBROADCNT (0x0000015C/4) /* Error-free Broadcast Frames RX */
100 #define GEM_RXMULTICNT (0x00000160/4) /* Error-free Multicast Frames RX */
101 #define GEM_RXPAUSECNT (0x00000164/4) /* Pause Frames Received Counter */
102 #define GEM_RX64CNT (0x00000168/4) /* Error-free 64 byte Frames RX */
103 #define GEM_RX65CNT (0x0000016C/4) /* Error-free 65-127B Frames RX */
104 #define GEM_RX128CNT (0x00000170/4) /* Error-free 128-255B Frames RX */
105 #define GEM_RX256CNT (0x00000174/4) /* Error-free 256-512B Frames RX */
106 #define GEM_RX512CNT (0x00000178/4) /* Error-free 512-1023B Frames RX */
107 #define GEM_RX1024CNT (0x0000017C/4) /* Error-free 1024-1518B Frames RX */
108 #define GEM_RX1519CNT (0x00000180/4) /* Error-free 1519-max Frames RX */
109 #define GEM_RXUNDERCNT (0x00000184/4) /* Undersize Frames Received */
110 #define GEM_RXOVERCNT (0x00000188/4) /* Oversize Frames Received */
111 #define GEM_RXJABCNT (0x0000018C/4) /* Jabbers Received Counter */
112 #define GEM_RXFCSCNT (0x00000190/4) /* Frame Check seq. Error Counter */
113 #define GEM_RXLENERRCNT (0x00000194/4) /* Length Field Error Counter */
114 #define GEM_RXSYMERRCNT (0x00000198/4) /* Symbol Error Counter */
115 #define GEM_RXALIGNERRCNT (0x0000019C/4) /* Alignment Error Counter */
116 #define GEM_RXRSCERRCNT (0x000001A0/4) /* Receive Resource Error Counter */
117 #define GEM_RXORUNCNT (0x000001A4/4) /* Receive Overrun Counter */
118 #define GEM_RXIPCSERRCNT (0x000001A8/4) /* IP header Checksum Error Counter */
119 #define GEM_RXTCPCCNT (0x000001AC/4) /* TCP Checksum Error Counter */
120 #define GEM_RXUDPCCNT (0x000001B0/4) /* UDP Checksum Error Counter */
122 #define GEM_1588S (0x000001D0/4) /* 1588 Timer Seconds */
123 #define GEM_1588NS (0x000001D4/4) /* 1588 Timer Nanoseconds */
124 #define GEM_1588ADJ (0x000001D8/4) /* 1588 Timer Adjust */
125 #define GEM_1588INC (0x000001DC/4) /* 1588 Timer Increment */
126 #define GEM_PTPETXS (0x000001E0/4) /* PTP Event Frame Transmitted (s) */
127 #define GEM_PTPETXNS (0x000001E4/4) /* PTP Event Frame Transmitted (ns) */
128 #define GEM_PTPERXS (0x000001E8/4) /* PTP Event Frame Received (s) */
129 #define GEM_PTPERXNS (0x000001EC/4) /* PTP Event Frame Received (ns) */
130 #define GEM_PTPPTXS (0x000001E0/4) /* PTP Peer Frame Transmitted (s) */
131 #define GEM_PTPPTXNS (0x000001E4/4) /* PTP Peer Frame Transmitted (ns) */
132 #define GEM_PTPPRXS (0x000001E8/4) /* PTP Peer Frame Received (s) */
133 #define GEM_PTPPRXNS (0x000001EC/4) /* PTP Peer Frame Received (ns) */
135 /* Design Configuration Registers */
136 #define GEM_DESCONF (0x00000280/4)
137 #define GEM_DESCONF2 (0x00000284/4)
138 #define GEM_DESCONF3 (0x00000288/4)
139 #define GEM_DESCONF4 (0x0000028C/4)
140 #define GEM_DESCONF5 (0x00000290/4)
141 #define GEM_DESCONF6 (0x00000294/4)
142 #define GEM_DESCONF7 (0x00000298/4)
144 /*****************************************/
145 #define GEM_NWCTRL_TXSTART 0x00000200 /* Transmit Enable */
146 #define GEM_NWCTRL_TXENA 0x00000008 /* Transmit Enable */
147 #define GEM_NWCTRL_RXENA 0x00000004 /* Receive Enable */
148 #define GEM_NWCTRL_LOCALLOOP 0x00000002 /* Local Loopback */
150 #define GEM_NWCFG_STRIP_FCS 0x00020000 /* Strip FCS field */
151 #define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with len err */
152 #define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer offset mask */
153 #define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift */
154 #define GEM_NWCFG_UCAST_HASH 0x00000080 /* accept unicast if hash match */
155 #define GEM_NWCFG_MCAST_HASH 0x00000040 /* accept multicast if hash match */
156 #define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */
157 #define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */
159 #define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask */
160 #define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */
161 #define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */
162 #define GEM_DMACFG_TXCSUM_OFFL 0x00000800 /* Transmit checksum offload */
164 #define GEM_TXSTATUS_TXCMPL 0x00000020 /* Transmit Complete */
165 #define GEM_TXSTATUS_USED 0x00000001 /* sw owned descriptor encountered */
167 #define GEM_RXSTATUS_FRMRCVD 0x00000002 /* Frame received */
168 #define GEM_RXSTATUS_NOBUF 0x00000001 /* Buffer unavailable */
170 /* GEM_ISR GEM_IER GEM_IDR GEM_IMR */
171 #define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */
172 #define GEM_INT_TXUSED 0x00000008
173 #define GEM_INT_RXUSED 0x00000004
174 #define GEM_INT_RXCMPL 0x00000002
176 #define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */
177 #define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */
178 #define GEM_PHYMNTNC_ADDR 0x0F800000 /* Address bits */
179 #define GEM_PHYMNTNC_ADDR_SHFT 23
180 #define GEM_PHYMNTNC_REG 0x007C0000 /* register bits */
181 #define GEM_PHYMNTNC_REG_SHIFT 18
183 /* Marvell PHY definitions */
184 #define BOARD_PHY_ADDRESS 23 /* PHY address we will emulate a device at */
186 #define PHY_REG_CONTROL 0
187 #define PHY_REG_STATUS 1
188 #define PHY_REG_PHYID1 2
189 #define PHY_REG_PHYID2 3
190 #define PHY_REG_ANEGADV 4
191 #define PHY_REG_LINKPABIL 5
192 #define PHY_REG_ANEGEXP 6
193 #define PHY_REG_NEXTP 7
194 #define PHY_REG_LINKPNEXTP 8
195 #define PHY_REG_100BTCTRL 9
196 #define PHY_REG_1000BTSTAT 10
197 #define PHY_REG_EXTSTAT 15
198 #define PHY_REG_PHYSPCFC_CTL 16
199 #define PHY_REG_PHYSPCFC_ST 17
200 #define PHY_REG_INT_EN 18
201 #define PHY_REG_INT_ST 19
202 #define PHY_REG_EXT_PHYSPCFC_CTL 20
203 #define PHY_REG_RXERR 21
204 #define PHY_REG_EACD 22
205 #define PHY_REG_LED 24
206 #define PHY_REG_LED_OVRD 25
207 #define PHY_REG_EXT_PHYSPCFC_CTL2 26
208 #define PHY_REG_EXT_PHYSPCFC_ST 27
209 #define PHY_REG_CABLE_DIAG 28
211 #define PHY_REG_CONTROL_RST 0x8000
212 #define PHY_REG_CONTROL_LOOP 0x4000
213 #define PHY_REG_CONTROL_ANEG 0x1000
215 #define PHY_REG_STATUS_LINK 0x0004
216 #define PHY_REG_STATUS_ANEGCMPL 0x0020
218 #define PHY_REG_INT_ST_ANEGCMPL 0x0800
219 #define PHY_REG_INT_ST_LINKC 0x0400
220 #define PHY_REG_INT_ST_ENERGY 0x0010
222 /***********************************************************************/
223 #define GEM_RX_REJECT (-1)
224 #define GEM_RX_PROMISCUOUS_ACCEPT (-2)
225 #define GEM_RX_BROADCAST_ACCEPT (-3)
226 #define GEM_RX_MULTICAST_HASH_ACCEPT (-4)
227 #define GEM_RX_UNICAST_HASH_ACCEPT (-5)
229 #define GEM_RX_SAR_ACCEPT 0
231 /***********************************************************************/
233 #define DESC_1_USED 0x80000000
234 #define DESC_1_LENGTH 0x00001FFF
236 #define DESC_1_TX_WRAP 0x40000000
237 #define DESC_1_TX_LAST 0x00008000
239 #define DESC_0_RX_WRAP 0x00000002
240 #define DESC_0_RX_OWNERSHIP 0x00000001
242 #define R_DESC_1_RX_SAR_SHIFT 25
243 #define R_DESC_1_RX_SAR_LENGTH 2
244 #define R_DESC_1_RX_SAR_MATCH (1 << 27)
245 #define R_DESC_1_RX_UNICAST_HASH (1 << 29)
246 #define R_DESC_1_RX_MULTICAST_HASH (1 << 30)
247 #define R_DESC_1_RX_BROADCAST (1 << 31)
249 #define DESC_1_RX_SOF 0x00004000
250 #define DESC_1_RX_EOF 0x00008000
252 static inline unsigned tx_desc_get_buffer(unsigned *desc
)
257 static inline unsigned tx_desc_get_used(unsigned *desc
)
259 return (desc
[1] & DESC_1_USED
) ? 1 : 0;
262 static inline void tx_desc_set_used(unsigned *desc
)
264 desc
[1] |= DESC_1_USED
;
267 static inline unsigned tx_desc_get_wrap(unsigned *desc
)
269 return (desc
[1] & DESC_1_TX_WRAP
) ? 1 : 0;
272 static inline unsigned tx_desc_get_last(unsigned *desc
)
274 return (desc
[1] & DESC_1_TX_LAST
) ? 1 : 0;
277 static inline void tx_desc_set_last(unsigned *desc
)
279 desc
[1] |= DESC_1_TX_LAST
;
282 static inline unsigned tx_desc_get_length(unsigned *desc
)
284 return desc
[1] & DESC_1_LENGTH
;
287 static inline void print_gem_tx_desc(unsigned *desc
)
289 DB_PRINT("TXDESC:\n");
290 DB_PRINT("bufaddr: 0x%08x\n", *desc
);
291 DB_PRINT("used_hw: %d\n", tx_desc_get_used(desc
));
292 DB_PRINT("wrap: %d\n", tx_desc_get_wrap(desc
));
293 DB_PRINT("last: %d\n", tx_desc_get_last(desc
));
294 DB_PRINT("length: %d\n", tx_desc_get_length(desc
));
297 static inline unsigned rx_desc_get_buffer(unsigned *desc
)
299 return desc
[0] & ~0x3UL
;
302 static inline unsigned rx_desc_get_wrap(unsigned *desc
)
304 return desc
[0] & DESC_0_RX_WRAP
? 1 : 0;
307 static inline unsigned rx_desc_get_ownership(unsigned *desc
)
309 return desc
[0] & DESC_0_RX_OWNERSHIP
? 1 : 0;
312 static inline void rx_desc_set_ownership(unsigned *desc
)
314 desc
[0] |= DESC_0_RX_OWNERSHIP
;
317 static inline void rx_desc_set_sof(unsigned *desc
)
319 desc
[1] |= DESC_1_RX_SOF
;
322 static inline void rx_desc_set_eof(unsigned *desc
)
324 desc
[1] |= DESC_1_RX_EOF
;
327 static inline void rx_desc_set_length(unsigned *desc
, unsigned len
)
329 desc
[1] &= ~DESC_1_LENGTH
;
333 static inline void rx_desc_set_broadcast(unsigned *desc
)
335 desc
[1] |= R_DESC_1_RX_BROADCAST
;
338 static inline void rx_desc_set_unicast_hash(unsigned *desc
)
340 desc
[1] |= R_DESC_1_RX_UNICAST_HASH
;
343 static inline void rx_desc_set_multicast_hash(unsigned *desc
)
345 desc
[1] |= R_DESC_1_RX_MULTICAST_HASH
;
348 static inline void rx_desc_set_sar(unsigned *desc
, int sar_idx
)
350 desc
[1] = deposit32(desc
[1], R_DESC_1_RX_SAR_SHIFT
, R_DESC_1_RX_SAR_LENGTH
,
352 desc
[1] |= R_DESC_1_RX_SAR_MATCH
;
355 /* The broadcast MAC address: 0xFFFFFFFFFFFF */
356 static const uint8_t broadcast_addr
[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
359 * gem_init_register_masks:
360 * One time initialization.
361 * Set masks to identify which register bits have magical clear properties
363 static void gem_init_register_masks(CadenceGEMState
*s
)
365 /* Mask of register bits which are read only */
366 memset(&s
->regs_ro
[0], 0, sizeof(s
->regs_ro
));
367 s
->regs_ro
[GEM_NWCTRL
] = 0xFFF80000;
368 s
->regs_ro
[GEM_NWSTATUS
] = 0xFFFFFFFF;
369 s
->regs_ro
[GEM_DMACFG
] = 0xFE00F000;
370 s
->regs_ro
[GEM_TXSTATUS
] = 0xFFFFFE08;
371 s
->regs_ro
[GEM_RXQBASE
] = 0x00000003;
372 s
->regs_ro
[GEM_TXQBASE
] = 0x00000003;
373 s
->regs_ro
[GEM_RXSTATUS
] = 0xFFFFFFF0;
374 s
->regs_ro
[GEM_ISR
] = 0xFFFFFFFF;
375 s
->regs_ro
[GEM_IMR
] = 0xFFFFFFFF;
376 s
->regs_ro
[GEM_MODID
] = 0xFFFFFFFF;
378 /* Mask of register bits which are clear on read */
379 memset(&s
->regs_rtc
[0], 0, sizeof(s
->regs_rtc
));
380 s
->regs_rtc
[GEM_ISR
] = 0xFFFFFFFF;
382 /* Mask of register bits which are write 1 to clear */
383 memset(&s
->regs_w1c
[0], 0, sizeof(s
->regs_w1c
));
384 s
->regs_w1c
[GEM_TXSTATUS
] = 0x000001F7;
385 s
->regs_w1c
[GEM_RXSTATUS
] = 0x0000000F;
387 /* Mask of register bits which are write only */
388 memset(&s
->regs_wo
[0], 0, sizeof(s
->regs_wo
));
389 s
->regs_wo
[GEM_NWCTRL
] = 0x00073E60;
390 s
->regs_wo
[GEM_IER
] = 0x07FFFFFF;
391 s
->regs_wo
[GEM_IDR
] = 0x07FFFFFF;
396 * Make the emulated PHY link state match the QEMU "interface" state.
398 static void phy_update_link(CadenceGEMState
*s
)
400 DB_PRINT("down %d\n", qemu_get_queue(s
->nic
)->link_down
);
402 /* Autonegotiation status mirrors link status. */
403 if (qemu_get_queue(s
->nic
)->link_down
) {
404 s
->phy_regs
[PHY_REG_STATUS
] &= ~(PHY_REG_STATUS_ANEGCMPL
|
405 PHY_REG_STATUS_LINK
);
406 s
->phy_regs
[PHY_REG_INT_ST
] |= PHY_REG_INT_ST_LINKC
;
408 s
->phy_regs
[PHY_REG_STATUS
] |= (PHY_REG_STATUS_ANEGCMPL
|
409 PHY_REG_STATUS_LINK
);
410 s
->phy_regs
[PHY_REG_INT_ST
] |= (PHY_REG_INT_ST_LINKC
|
411 PHY_REG_INT_ST_ANEGCMPL
|
412 PHY_REG_INT_ST_ENERGY
);
416 static int gem_can_receive(NetClientState
*nc
)
420 s
= qemu_get_nic_opaque(nc
);
422 /* Do nothing if receive is not enabled. */
423 if (!(s
->regs
[GEM_NWCTRL
] & GEM_NWCTRL_RXENA
)) {
424 if (s
->can_rx_state
!= 1) {
426 DB_PRINT("can't receive - no enable\n");
431 if (rx_desc_get_ownership(s
->rx_desc
) == 1) {
432 if (s
->can_rx_state
!= 2) {
434 DB_PRINT("can't receive - busy buffer descriptor 0x%x\n",
440 if (s
->can_rx_state
!= 0) {
442 DB_PRINT("can receive 0x%x\n", s
->rx_desc_addr
);
448 * gem_update_int_status:
449 * Raise or lower interrupt based on current status.
451 static void gem_update_int_status(CadenceGEMState
*s
)
453 if (s
->regs
[GEM_ISR
]) {
454 DB_PRINT("asserting int. (0x%08x)\n", s
->regs
[GEM_ISR
]);
455 qemu_set_irq(s
->irq
, 1);
460 * gem_receive_updatestats:
461 * Increment receive statistics.
463 static void gem_receive_updatestats(CadenceGEMState
*s
, const uint8_t *packet
,
468 /* Total octets (bytes) received */
469 octets
= ((uint64_t)(s
->regs
[GEM_OCTRXLO
]) << 32) |
470 s
->regs
[GEM_OCTRXHI
];
472 s
->regs
[GEM_OCTRXLO
] = octets
>> 32;
473 s
->regs
[GEM_OCTRXHI
] = octets
;
475 /* Error-free Frames received */
476 s
->regs
[GEM_RXCNT
]++;
478 /* Error-free Broadcast Frames counter */
479 if (!memcmp(packet
, broadcast_addr
, 6)) {
480 s
->regs
[GEM_RXBROADCNT
]++;
483 /* Error-free Multicast Frames counter */
484 if (packet
[0] == 0x01) {
485 s
->regs
[GEM_RXMULTICNT
]++;
489 s
->regs
[GEM_RX64CNT
]++;
490 } else if (bytes
<= 127) {
491 s
->regs
[GEM_RX65CNT
]++;
492 } else if (bytes
<= 255) {
493 s
->regs
[GEM_RX128CNT
]++;
494 } else if (bytes
<= 511) {
495 s
->regs
[GEM_RX256CNT
]++;
496 } else if (bytes
<= 1023) {
497 s
->regs
[GEM_RX512CNT
]++;
498 } else if (bytes
<= 1518) {
499 s
->regs
[GEM_RX1024CNT
]++;
501 s
->regs
[GEM_RX1519CNT
]++;
506 * Get the MAC Address bit from the specified position
508 static unsigned get_bit(const uint8_t *mac
, unsigned bit
)
513 byte
>>= (bit
& 0x7);
520 * Calculate a GEM MAC Address hash index
522 static unsigned calc_mac_hash(const uint8_t *mac
)
524 int index_bit
, mac_bit
;
529 for (index_bit
= 5; index_bit
>= 0; index_bit
--) {
530 hash_index
|= (get_bit(mac
, mac_bit
) ^
531 get_bit(mac
, mac_bit
+ 6) ^
532 get_bit(mac
, mac_bit
+ 12) ^
533 get_bit(mac
, mac_bit
+ 18) ^
534 get_bit(mac
, mac_bit
+ 24) ^
535 get_bit(mac
, mac_bit
+ 30) ^
536 get_bit(mac
, mac_bit
+ 36) ^
537 get_bit(mac
, mac_bit
+ 42)) << index_bit
;
545 * gem_mac_address_filter:
546 * Accept or reject this destination address?
548 * GEM_RX_REJECT: reject
549 * >= 0: Specific address accept (which matched SAR is returned)
550 * others for various other modes of accept:
551 * GEM_RM_PROMISCUOUS_ACCEPT, GEM_RX_BROADCAST_ACCEPT,
552 * GEM_RX_MULTICAST_HASH_ACCEPT or GEM_RX_UNICAST_HASH_ACCEPT
554 static int gem_mac_address_filter(CadenceGEMState
*s
, const uint8_t *packet
)
559 /* Promiscuous mode? */
560 if (s
->regs
[GEM_NWCFG
] & GEM_NWCFG_PROMISC
) {
561 return GEM_RX_PROMISCUOUS_ACCEPT
;
564 if (!memcmp(packet
, broadcast_addr
, 6)) {
565 /* Reject broadcast packets? */
566 if (s
->regs
[GEM_NWCFG
] & GEM_NWCFG_BCAST_REJ
) {
567 return GEM_RX_REJECT
;
569 return GEM_RX_BROADCAST_ACCEPT
;
572 /* Accept packets -w- hash match? */
573 if ((packet
[0] == 0x01 && (s
->regs
[GEM_NWCFG
] & GEM_NWCFG_MCAST_HASH
)) ||
574 (packet
[0] != 0x01 && (s
->regs
[GEM_NWCFG
] & GEM_NWCFG_UCAST_HASH
))) {
577 hash_index
= calc_mac_hash(packet
);
578 if (hash_index
< 32) {
579 if (s
->regs
[GEM_HASHLO
] & (1<<hash_index
)) {
580 return packet
[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT
:
581 GEM_RX_UNICAST_HASH_ACCEPT
;
585 if (s
->regs
[GEM_HASHHI
] & (1<<hash_index
)) {
586 return packet
[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT
:
587 GEM_RX_UNICAST_HASH_ACCEPT
;
592 /* Check all 4 specific addresses */
593 gem_spaddr
= (uint8_t *)&(s
->regs
[GEM_SPADDR1LO
]);
594 for (i
= 3; i
>= 0; i
--) {
595 if (s
->sar_active
[i
] && !memcmp(packet
, gem_spaddr
+ 8 * i
, 6)) {
596 return GEM_RX_SAR_ACCEPT
+ i
;
600 /* No address match; reject the packet */
601 return GEM_RX_REJECT
;
604 static void gem_get_rx_desc(CadenceGEMState
*s
)
606 DB_PRINT("read descriptor 0x%x\n", (unsigned)s
->rx_desc_addr
);
607 /* read current descriptor */
608 cpu_physical_memory_read(s
->rx_desc_addr
,
609 (uint8_t *)s
->rx_desc
, sizeof(s
->rx_desc
));
611 /* Descriptor owned by software ? */
612 if (rx_desc_get_ownership(s
->rx_desc
) == 1) {
613 DB_PRINT("descriptor 0x%x owned by sw.\n",
614 (unsigned)s
->rx_desc_addr
);
615 s
->regs
[GEM_RXSTATUS
] |= GEM_RXSTATUS_NOBUF
;
616 s
->regs
[GEM_ISR
] |= GEM_INT_RXUSED
& ~(s
->regs
[GEM_IMR
]);
617 /* Handle interrupt consequences */
618 gem_update_int_status(s
);
624 * Fit a packet handed to us by QEMU into the receive descriptor ring.
626 static ssize_t
gem_receive(NetClientState
*nc
, const uint8_t *buf
, size_t size
)
629 unsigned rxbufsize
, bytes_to_copy
;
630 unsigned rxbuf_offset
;
633 bool first_desc
= true;
636 s
= qemu_get_nic_opaque(nc
);
638 /* Is this destination MAC address "for us" ? */
639 maf
= gem_mac_address_filter(s
, buf
);
640 if (maf
== GEM_RX_REJECT
) {
644 /* Discard packets with receive length error enabled ? */
645 if (s
->regs
[GEM_NWCFG
] & GEM_NWCFG_LERR_DISC
) {
648 /* Fish the ethertype / length field out of the RX packet */
649 type_len
= buf
[12] << 8 | buf
[13];
650 /* It is a length field, not an ethertype */
651 if (type_len
< 0x600) {
652 if (size
< type_len
) {
660 * Determine configured receive buffer offset (probably 0)
662 rxbuf_offset
= (s
->regs
[GEM_NWCFG
] & GEM_NWCFG_BUFF_OFST_M
) >>
663 GEM_NWCFG_BUFF_OFST_S
;
665 /* The configure size of each receive buffer. Determines how many
666 * buffers needed to hold this packet.
668 rxbufsize
= ((s
->regs
[GEM_DMACFG
] & GEM_DMACFG_RBUFSZ_M
) >>
669 GEM_DMACFG_RBUFSZ_S
) * GEM_DMACFG_RBUFSZ_MUL
;
670 bytes_to_copy
= size
;
672 /* Hardware allows a zero value here but warns against it. To avoid QEMU
673 * indefinite loops we enforce a minimum value here
675 if (rxbufsize
< GEM_DMACFG_RBUFSZ_MUL
) {
676 rxbufsize
= GEM_DMACFG_RBUFSZ_MUL
;
679 /* Pad to minimum length. Assume FCS field is stripped, logic
680 * below will increment it to the real minimum of 64 when
687 /* Strip of FCS field ? (usually yes) */
688 if (s
->regs
[GEM_NWCFG
] & GEM_NWCFG_STRIP_FCS
) {
689 rxbuf_ptr
= (void *)buf
;
693 if (size
> sizeof(rxbuf
) - sizeof(crc_val
)) {
694 size
= sizeof(rxbuf
) - sizeof(crc_val
);
696 bytes_to_copy
= size
;
697 /* The application wants the FCS field, which QEMU does not provide.
698 * We must try and calculate one.
701 memcpy(rxbuf
, buf
, size
);
702 memset(rxbuf
+ size
, 0, sizeof(rxbuf
) - size
);
704 crc_val
= cpu_to_le32(crc32(0, rxbuf
, MAX(size
, 60)));
705 memcpy(rxbuf
+ size
, &crc_val
, sizeof(crc_val
));
711 DB_PRINT("config bufsize: %d packet size: %ld\n", rxbufsize
, size
);
713 while (bytes_to_copy
) {
714 /* Do nothing if receive is not enabled. */
715 if (!gem_can_receive(nc
)) {
720 DB_PRINT("copy %d bytes to 0x%x\n", MIN(bytes_to_copy
, rxbufsize
),
721 rx_desc_get_buffer(s
->rx_desc
));
723 /* Copy packet data to emulated DMA buffer */
724 cpu_physical_memory_write(rx_desc_get_buffer(s
->rx_desc
) + rxbuf_offset
,
725 rxbuf_ptr
, MIN(bytes_to_copy
, rxbufsize
));
726 rxbuf_ptr
+= MIN(bytes_to_copy
, rxbufsize
);
727 bytes_to_copy
-= MIN(bytes_to_copy
, rxbufsize
);
729 /* Update the descriptor. */
731 rx_desc_set_sof(s
->rx_desc
);
734 if (bytes_to_copy
== 0) {
735 rx_desc_set_eof(s
->rx_desc
);
736 rx_desc_set_length(s
->rx_desc
, size
);
738 rx_desc_set_ownership(s
->rx_desc
);
741 case GEM_RX_PROMISCUOUS_ACCEPT
:
743 case GEM_RX_BROADCAST_ACCEPT
:
744 rx_desc_set_broadcast(s
->rx_desc
);
746 case GEM_RX_UNICAST_HASH_ACCEPT
:
747 rx_desc_set_unicast_hash(s
->rx_desc
);
749 case GEM_RX_MULTICAST_HASH_ACCEPT
:
750 rx_desc_set_multicast_hash(s
->rx_desc
);
755 rx_desc_set_sar(s
->rx_desc
, maf
);
758 /* Descriptor write-back. */
759 cpu_physical_memory_write(s
->rx_desc_addr
,
760 (uint8_t *)s
->rx_desc
, sizeof(s
->rx_desc
));
762 /* Next descriptor */
763 if (rx_desc_get_wrap(s
->rx_desc
)) {
764 DB_PRINT("wrapping RX descriptor list\n");
765 s
->rx_desc_addr
= s
->regs
[GEM_RXQBASE
];
767 DB_PRINT("incrementing RX descriptor list\n");
768 s
->rx_desc_addr
+= 8;
774 gem_receive_updatestats(s
, buf
, size
);
776 s
->regs
[GEM_RXSTATUS
] |= GEM_RXSTATUS_FRMRCVD
;
777 s
->regs
[GEM_ISR
] |= GEM_INT_RXCMPL
& ~(s
->regs
[GEM_IMR
]);
779 /* Handle interrupt consequences */
780 gem_update_int_status(s
);
786 * gem_transmit_updatestats:
787 * Increment transmit statistics.
789 static void gem_transmit_updatestats(CadenceGEMState
*s
, const uint8_t *packet
,
794 /* Total octets (bytes) transmitted */
795 octets
= ((uint64_t)(s
->regs
[GEM_OCTTXLO
]) << 32) |
796 s
->regs
[GEM_OCTTXHI
];
798 s
->regs
[GEM_OCTTXLO
] = octets
>> 32;
799 s
->regs
[GEM_OCTTXHI
] = octets
;
801 /* Error-free Frames transmitted */
802 s
->regs
[GEM_TXCNT
]++;
804 /* Error-free Broadcast Frames counter */
805 if (!memcmp(packet
, broadcast_addr
, 6)) {
806 s
->regs
[GEM_TXBCNT
]++;
809 /* Error-free Multicast Frames counter */
810 if (packet
[0] == 0x01) {
811 s
->regs
[GEM_TXMCNT
]++;
815 s
->regs
[GEM_TX64CNT
]++;
816 } else if (bytes
<= 127) {
817 s
->regs
[GEM_TX65CNT
]++;
818 } else if (bytes
<= 255) {
819 s
->regs
[GEM_TX128CNT
]++;
820 } else if (bytes
<= 511) {
821 s
->regs
[GEM_TX256CNT
]++;
822 } else if (bytes
<= 1023) {
823 s
->regs
[GEM_TX512CNT
]++;
824 } else if (bytes
<= 1518) {
825 s
->regs
[GEM_TX1024CNT
]++;
827 s
->regs
[GEM_TX1519CNT
]++;
833 * Fish packets out of the descriptor ring and feed them to QEMU
835 static void gem_transmit(CadenceGEMState
*s
)
838 hwaddr packet_desc_addr
;
839 uint8_t tx_packet
[2048];
841 unsigned total_bytes
;
843 /* Do nothing if transmit is not enabled. */
844 if (!(s
->regs
[GEM_NWCTRL
] & GEM_NWCTRL_TXENA
)) {
850 /* The packet we will hand off to QEMU.
851 * Packets scattered across multiple descriptors are gathered to this
852 * one contiguous buffer first.
857 /* read current descriptor */
858 packet_desc_addr
= s
->tx_desc_addr
;
860 DB_PRINT("read descriptor 0x%" HWADDR_PRIx
"\n", packet_desc_addr
);
861 cpu_physical_memory_read(packet_desc_addr
,
862 (uint8_t *)desc
, sizeof(desc
));
863 /* Handle all descriptors owned by hardware */
864 while (tx_desc_get_used(desc
) == 0) {
866 /* Do nothing if transmit is not enabled. */
867 if (!(s
->regs
[GEM_NWCTRL
] & GEM_NWCTRL_TXENA
)) {
870 print_gem_tx_desc(desc
);
872 /* The real hardware would eat this (and possibly crash).
873 * For QEMU let's lend a helping hand.
875 if ((tx_desc_get_buffer(desc
) == 0) ||
876 (tx_desc_get_length(desc
) == 0)) {
877 DB_PRINT("Invalid TX descriptor @ 0x%x\n",
878 (unsigned)packet_desc_addr
);
882 if (tx_desc_get_length(desc
) > sizeof(tx_packet
) - (p
- tx_packet
)) {
883 DB_PRINT("TX descriptor @ 0x%x too large: size 0x%x space 0x%x\n",
884 (unsigned)packet_desc_addr
,
885 (unsigned)tx_desc_get_length(desc
),
886 sizeof(tx_packet
) - (p
- tx_packet
));
890 /* Gather this fragment of the packet from "dma memory" to our contig.
893 cpu_physical_memory_read(tx_desc_get_buffer(desc
), p
,
894 tx_desc_get_length(desc
));
895 p
+= tx_desc_get_length(desc
);
896 total_bytes
+= tx_desc_get_length(desc
);
898 /* Last descriptor for this packet; hand the whole thing off */
899 if (tx_desc_get_last(desc
)) {
900 unsigned desc_first
[2];
902 /* Modify the 1st descriptor of this packet to be owned by
905 cpu_physical_memory_read(s
->tx_desc_addr
, (uint8_t *)desc_first
,
907 tx_desc_set_used(desc_first
);
908 cpu_physical_memory_write(s
->tx_desc_addr
, (uint8_t *)desc_first
,
910 /* Advance the hardware current descriptor past this packet */
911 if (tx_desc_get_wrap(desc
)) {
912 s
->tx_desc_addr
= s
->regs
[GEM_TXQBASE
];
914 s
->tx_desc_addr
= packet_desc_addr
+ 8;
916 DB_PRINT("TX descriptor next: 0x%08x\n", s
->tx_desc_addr
);
918 s
->regs
[GEM_TXSTATUS
] |= GEM_TXSTATUS_TXCMPL
;
919 s
->regs
[GEM_ISR
] |= GEM_INT_TXCMPL
& ~(s
->regs
[GEM_IMR
]);
921 /* Handle interrupt consequences */
922 gem_update_int_status(s
);
924 /* Is checksum offload enabled? */
925 if (s
->regs
[GEM_DMACFG
] & GEM_DMACFG_TXCSUM_OFFL
) {
926 net_checksum_calculate(tx_packet
, total_bytes
);
929 /* Update MAC statistics */
930 gem_transmit_updatestats(s
, tx_packet
, total_bytes
);
932 /* Send the packet somewhere */
933 if (s
->phy_loop
|| (s
->regs
[GEM_NWCTRL
] & GEM_NWCTRL_LOCALLOOP
)) {
934 gem_receive(qemu_get_queue(s
->nic
), tx_packet
, total_bytes
);
936 qemu_send_packet(qemu_get_queue(s
->nic
), tx_packet
,
940 /* Prepare for next packet */
945 /* read next descriptor */
946 if (tx_desc_get_wrap(desc
)) {
947 tx_desc_set_last(desc
);
948 packet_desc_addr
= s
->regs
[GEM_TXQBASE
];
950 packet_desc_addr
+= 8;
952 DB_PRINT("read descriptor 0x%" HWADDR_PRIx
"\n", packet_desc_addr
);
953 cpu_physical_memory_read(packet_desc_addr
,
954 (uint8_t *)desc
, sizeof(desc
));
957 if (tx_desc_get_used(desc
)) {
958 s
->regs
[GEM_TXSTATUS
] |= GEM_TXSTATUS_USED
;
959 s
->regs
[GEM_ISR
] |= GEM_INT_TXUSED
& ~(s
->regs
[GEM_IMR
]);
960 gem_update_int_status(s
);
964 static void gem_phy_reset(CadenceGEMState
*s
)
966 memset(&s
->phy_regs
[0], 0, sizeof(s
->phy_regs
));
967 s
->phy_regs
[PHY_REG_CONTROL
] = 0x1140;
968 s
->phy_regs
[PHY_REG_STATUS
] = 0x7969;
969 s
->phy_regs
[PHY_REG_PHYID1
] = 0x0141;
970 s
->phy_regs
[PHY_REG_PHYID2
] = 0x0CC2;
971 s
->phy_regs
[PHY_REG_ANEGADV
] = 0x01E1;
972 s
->phy_regs
[PHY_REG_LINKPABIL
] = 0xCDE1;
973 s
->phy_regs
[PHY_REG_ANEGEXP
] = 0x000F;
974 s
->phy_regs
[PHY_REG_NEXTP
] = 0x2001;
975 s
->phy_regs
[PHY_REG_LINKPNEXTP
] = 0x40E6;
976 s
->phy_regs
[PHY_REG_100BTCTRL
] = 0x0300;
977 s
->phy_regs
[PHY_REG_1000BTSTAT
] = 0x7C00;
978 s
->phy_regs
[PHY_REG_EXTSTAT
] = 0x3000;
979 s
->phy_regs
[PHY_REG_PHYSPCFC_CTL
] = 0x0078;
980 s
->phy_regs
[PHY_REG_PHYSPCFC_ST
] = 0x7C00;
981 s
->phy_regs
[PHY_REG_EXT_PHYSPCFC_CTL
] = 0x0C60;
982 s
->phy_regs
[PHY_REG_LED
] = 0x4100;
983 s
->phy_regs
[PHY_REG_EXT_PHYSPCFC_CTL2
] = 0x000A;
984 s
->phy_regs
[PHY_REG_EXT_PHYSPCFC_ST
] = 0x848B;
989 static void gem_reset(DeviceState
*d
)
992 CadenceGEMState
*s
= CADENCE_GEM(d
);
997 /* Set post reset register values */
998 memset(&s
->regs
[0], 0, sizeof(s
->regs
));
999 s
->regs
[GEM_NWCFG
] = 0x00080000;
1000 s
->regs
[GEM_NWSTATUS
] = 0x00000006;
1001 s
->regs
[GEM_DMACFG
] = 0x00020784;
1002 s
->regs
[GEM_IMR
] = 0x07ffffff;
1003 s
->regs
[GEM_TXPAUSE
] = 0x0000ffff;
1004 s
->regs
[GEM_TXPARTIALSF
] = 0x000003ff;
1005 s
->regs
[GEM_RXPARTIALSF
] = 0x000003ff;
1006 s
->regs
[GEM_MODID
] = 0x00020118;
1007 s
->regs
[GEM_DESCONF
] = 0x02500111;
1008 s
->regs
[GEM_DESCONF2
] = 0x2ab13fff;
1009 s
->regs
[GEM_DESCONF5
] = 0x002f2145;
1010 s
->regs
[GEM_DESCONF6
] = 0x00000200;
1012 /* Set MAC address */
1013 a
= &s
->conf
.macaddr
.a
[0];
1014 s
->regs
[GEM_SPADDR1LO
] = a
[0] | (a
[1] << 8) | (a
[2] << 16) | (a
[3] << 24);
1015 s
->regs
[GEM_SPADDR1HI
] = a
[4] | (a
[5] << 8);
1017 for (i
= 0; i
< 4; i
++) {
1018 s
->sar_active
[i
] = false;
1023 gem_update_int_status(s
);
1026 static uint16_t gem_phy_read(CadenceGEMState
*s
, unsigned reg_num
)
1028 DB_PRINT("reg: %d value: 0x%04x\n", reg_num
, s
->phy_regs
[reg_num
]);
1029 return s
->phy_regs
[reg_num
];
1032 static void gem_phy_write(CadenceGEMState
*s
, unsigned reg_num
, uint16_t val
)
1034 DB_PRINT("reg: %d value: 0x%04x\n", reg_num
, val
);
1037 case PHY_REG_CONTROL
:
1038 if (val
& PHY_REG_CONTROL_RST
) {
1041 val
&= ~(PHY_REG_CONTROL_RST
| PHY_REG_CONTROL_LOOP
);
1044 if (val
& PHY_REG_CONTROL_ANEG
) {
1045 /* Complete autonegotiation immediately */
1046 val
&= ~PHY_REG_CONTROL_ANEG
;
1047 s
->phy_regs
[PHY_REG_STATUS
] |= PHY_REG_STATUS_ANEGCMPL
;
1049 if (val
& PHY_REG_CONTROL_LOOP
) {
1050 DB_PRINT("PHY placed in loopback\n");
1057 s
->phy_regs
[reg_num
] = val
;
1062 * Read a GEM register.
1064 static uint64_t gem_read(void *opaque
, hwaddr offset
, unsigned size
)
1069 s
= (CadenceGEMState
*)opaque
;
1072 retval
= s
->regs
[offset
];
1074 DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset
*4, retval
);
1078 DB_PRINT("lowering irq on ISR read\n");
1079 qemu_set_irq(s
->irq
, 0);
1082 if (retval
& GEM_PHYMNTNC_OP_R
) {
1083 uint32_t phy_addr
, reg_num
;
1085 phy_addr
= (retval
& GEM_PHYMNTNC_ADDR
) >> GEM_PHYMNTNC_ADDR_SHFT
;
1086 if (phy_addr
== BOARD_PHY_ADDRESS
|| phy_addr
== 0) {
1087 reg_num
= (retval
& GEM_PHYMNTNC_REG
) >> GEM_PHYMNTNC_REG_SHIFT
;
1088 retval
&= 0xFFFF0000;
1089 retval
|= gem_phy_read(s
, reg_num
);
1091 retval
|= 0xFFFF; /* No device at this address */
1097 /* Squash read to clear bits */
1098 s
->regs
[offset
] &= ~(s
->regs_rtc
[offset
]);
1100 /* Do not provide write only bits */
1101 retval
&= ~(s
->regs_wo
[offset
]);
1103 DB_PRINT("0x%08x\n", retval
);
1109 * Write a GEM register.
1111 static void gem_write(void *opaque
, hwaddr offset
, uint64_t val
,
1114 CadenceGEMState
*s
= (CadenceGEMState
*)opaque
;
1117 DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset
, (unsigned)val
);
1120 /* Squash bits which are read only in write value */
1121 val
&= ~(s
->regs_ro
[offset
]);
1122 /* Preserve (only) bits which are read only and wtc in register */
1123 readonly
= s
->regs
[offset
] & (s
->regs_ro
[offset
] | s
->regs_w1c
[offset
]);
1125 /* Copy register write to backing store */
1126 s
->regs
[offset
] = (val
& ~s
->regs_w1c
[offset
]) | readonly
;
1129 s
->regs
[offset
] &= ~(s
->regs_w1c
[offset
] & val
);
1131 /* Handle register write side effects */
1134 if (val
& GEM_NWCTRL_RXENA
) {
1137 if (val
& GEM_NWCTRL_TXSTART
) {
1140 if (!(val
& GEM_NWCTRL_TXENA
)) {
1141 /* Reset to start of Q when transmit disabled. */
1142 s
->tx_desc_addr
= s
->regs
[GEM_TXQBASE
];
1144 if (gem_can_receive(qemu_get_queue(s
->nic
))) {
1145 qemu_flush_queued_packets(qemu_get_queue(s
->nic
));
1150 gem_update_int_status(s
);
1153 s
->rx_desc_addr
= val
;
1156 s
->tx_desc_addr
= val
;
1159 gem_update_int_status(s
);
1162 s
->regs
[GEM_IMR
] &= ~val
;
1163 gem_update_int_status(s
);
1166 s
->regs
[GEM_IMR
] |= val
;
1167 gem_update_int_status(s
);
1173 s
->sar_active
[(offset
- GEM_SPADDR1LO
) / 2] = false;
1179 s
->sar_active
[(offset
- GEM_SPADDR1HI
) / 2] = true;
1182 if (val
& GEM_PHYMNTNC_OP_W
) {
1183 uint32_t phy_addr
, reg_num
;
1185 phy_addr
= (val
& GEM_PHYMNTNC_ADDR
) >> GEM_PHYMNTNC_ADDR_SHFT
;
1186 if (phy_addr
== BOARD_PHY_ADDRESS
|| phy_addr
== 0) {
1187 reg_num
= (val
& GEM_PHYMNTNC_REG
) >> GEM_PHYMNTNC_REG_SHIFT
;
1188 gem_phy_write(s
, reg_num
, val
);
1194 DB_PRINT("newval: 0x%08x\n", s
->regs
[offset
]);
1197 static const MemoryRegionOps gem_ops
= {
1200 .endianness
= DEVICE_LITTLE_ENDIAN
,
1203 static void gem_set_link(NetClientState
*nc
)
1206 phy_update_link(qemu_get_nic_opaque(nc
));
1209 static NetClientInfo net_gem_info
= {
1210 .type
= NET_CLIENT_OPTIONS_KIND_NIC
,
1211 .size
= sizeof(NICState
),
1212 .can_receive
= gem_can_receive
,
1213 .receive
= gem_receive
,
1214 .link_status_changed
= gem_set_link
,
1217 static int gem_init(SysBusDevice
*sbd
)
1219 DeviceState
*dev
= DEVICE(sbd
);
1220 CadenceGEMState
*s
= CADENCE_GEM(dev
);
1224 gem_init_register_masks(s
);
1225 memory_region_init_io(&s
->iomem
, OBJECT(s
), &gem_ops
, s
,
1226 "enet", sizeof(s
->regs
));
1227 sysbus_init_mmio(sbd
, &s
->iomem
);
1228 sysbus_init_irq(sbd
, &s
->irq
);
1229 qemu_macaddr_default_if_unset(&s
->conf
.macaddr
);
1231 s
->nic
= qemu_new_nic(&net_gem_info
, &s
->conf
,
1232 object_get_typename(OBJECT(dev
)), dev
->id
, s
);
1237 static const VMStateDescription vmstate_cadence_gem
= {
1238 .name
= "cadence_gem",
1240 .minimum_version_id
= 2,
1241 .fields
= (VMStateField
[]) {
1242 VMSTATE_UINT32_ARRAY(regs
, CadenceGEMState
, CADENCE_GEM_MAXREG
),
1243 VMSTATE_UINT16_ARRAY(phy_regs
, CadenceGEMState
, 32),
1244 VMSTATE_UINT8(phy_loop
, CadenceGEMState
),
1245 VMSTATE_UINT32(rx_desc_addr
, CadenceGEMState
),
1246 VMSTATE_UINT32(tx_desc_addr
, CadenceGEMState
),
1247 VMSTATE_BOOL_ARRAY(sar_active
, CadenceGEMState
, 4),
1248 VMSTATE_END_OF_LIST(),
1252 static Property gem_properties
[] = {
1253 DEFINE_NIC_PROPERTIES(CadenceGEMState
, conf
),
1254 DEFINE_PROP_END_OF_LIST(),
1257 static void gem_class_init(ObjectClass
*klass
, void *data
)
1259 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1260 SysBusDeviceClass
*sdc
= SYS_BUS_DEVICE_CLASS(klass
);
1262 sdc
->init
= gem_init
;
1263 dc
->props
= gem_properties
;
1264 dc
->vmsd
= &vmstate_cadence_gem
;
1265 dc
->reset
= gem_reset
;
1268 static const TypeInfo gem_info
= {
1269 .name
= TYPE_CADENCE_GEM
,
1270 .parent
= TYPE_SYS_BUS_DEVICE
,
1271 .instance_size
= sizeof(CadenceGEMState
),
1272 .class_init
= gem_class_init
,
1275 static void gem_register_types(void)
1277 type_register_static(&gem_info
);
1280 type_init(gem_register_types
)