2 * QEMU 8259 interrupt controller emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 #include "qemu/osdep.h"
26 #include "hw/i386/pc.h"
27 #include "hw/isa/isa.h"
28 #include "monitor/monitor.h"
29 #include "qemu/timer.h"
31 #include "hw/isa/i8259_internal.h"
37 #define DPRINTF(fmt, ...) \
38 do { printf("pic: " fmt , ## __VA_ARGS__); } while (0)
40 #define DPRINTF(fmt, ...)
43 //#define DEBUG_IRQ_LATENCY
44 //#define DEBUG_IRQ_COUNT
46 #define TYPE_I8259 "isa-i8259"
47 #define PIC_CLASS(class) OBJECT_CLASS_CHECK(PICClass, (class), TYPE_I8259)
48 #define PIC_GET_CLASS(obj) OBJECT_GET_CLASS(PICClass, (obj), TYPE_I8259)
52 * @parent_realize: The parent's realizefn.
54 typedef struct PICClass
{
55 PICCommonClass parent_class
;
57 DeviceRealize parent_realize
;
60 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
61 static int irq_level
[16];
63 #ifdef DEBUG_IRQ_COUNT
64 static uint64_t irq_count
[16];
66 #ifdef DEBUG_IRQ_LATENCY
67 static int64_t irq_time
[16];
70 static PICCommonState
*slave_pic
;
72 /* return the highest priority found in mask (highest = smallest
73 number). Return 8 if no irq */
74 static int get_priority(PICCommonState
*s
, int mask
)
82 while ((mask
& (1 << ((priority
+ s
->priority_add
) & 7))) == 0) {
88 /* return the pic wanted interrupt. return -1 if none */
89 static int pic_get_irq(PICCommonState
*s
)
91 int mask
, cur_priority
, priority
;
93 mask
= s
->irr
& ~s
->imr
;
94 priority
= get_priority(s
, mask
);
98 /* compute current priority. If special fully nested mode on the
99 master, the IRQ coming from the slave is not taken into account
100 for the priority computation. */
102 if (s
->special_mask
) {
105 if (s
->special_fully_nested_mode
&& s
->master
) {
108 cur_priority
= get_priority(s
, mask
);
109 if (priority
< cur_priority
) {
110 /* higher priority found: an irq should be generated */
111 return (priority
+ s
->priority_add
) & 7;
117 /* Update INT output. Must be called every time the output may have changed. */
118 static void pic_update_irq(PICCommonState
*s
)
122 irq
= pic_get_irq(s
);
124 DPRINTF("pic%d: imr=%x irr=%x padd=%d\n",
125 s
->master
? 0 : 1, s
->imr
, s
->irr
, s
->priority_add
);
126 qemu_irq_raise(s
->int_out
[0]);
128 qemu_irq_lower(s
->int_out
[0]);
132 /* set irq level. If an edge is detected, then the IRR is set to 1 */
133 static void pic_set_irq(void *opaque
, int irq
, int level
)
135 PICCommonState
*s
= opaque
;
138 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT) || \
139 defined(DEBUG_IRQ_LATENCY)
140 int irq_index
= s
->master
? irq
: irq
+ 8;
142 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
143 if (level
!= irq_level
[irq_index
]) {
144 DPRINTF("pic_set_irq: irq=%d level=%d\n", irq_index
, level
);
145 irq_level
[irq_index
] = level
;
146 #ifdef DEBUG_IRQ_COUNT
148 irq_count
[irq_index
]++;
153 #ifdef DEBUG_IRQ_LATENCY
155 irq_time
[irq_index
] = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
159 if (s
->elcr
& mask
) {
160 /* level triggered */
166 s
->last_irr
&= ~mask
;
171 if ((s
->last_irr
& mask
) == 0) {
176 s
->last_irr
&= ~mask
;
182 /* acknowledge interrupt 'irq' */
183 static void pic_intack(PICCommonState
*s
, int irq
)
186 if (s
->rotate_on_auto_eoi
) {
187 s
->priority_add
= (irq
+ 1) & 7;
190 s
->isr
|= (1 << irq
);
192 /* We don't clear a level sensitive interrupt here */
193 if (!(s
->elcr
& (1 << irq
))) {
194 s
->irr
&= ~(1 << irq
);
199 int pic_read_irq(DeviceState
*d
)
201 PICCommonState
*s
= PIC_COMMON(d
);
202 int irq
, irq2
, intno
;
204 irq
= pic_get_irq(s
);
207 irq2
= pic_get_irq(slave_pic
);
209 pic_intack(slave_pic
, irq2
);
211 /* spurious IRQ on slave controller */
214 intno
= slave_pic
->irq_base
+ irq2
;
216 intno
= s
->irq_base
+ irq
;
220 /* spurious IRQ on host controller */
222 intno
= s
->irq_base
+ irq
;
225 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_LATENCY)
230 #ifdef DEBUG_IRQ_LATENCY
231 printf("IRQ%d latency=%0.3fus\n",
233 (double)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) -
234 irq_time
[irq
]) * 1000000.0 / NANOSECONDS_PER_SECOND
);
236 DPRINTF("pic_interrupt: irq=%d\n", irq
);
240 static void pic_init_reset(PICCommonState
*s
)
246 static void pic_reset(DeviceState
*dev
)
248 PICCommonState
*s
= PIC_COMMON(dev
);
254 static void pic_ioport_write(void *opaque
, hwaddr addr64
,
255 uint64_t val64
, unsigned size
)
257 PICCommonState
*s
= opaque
;
258 uint32_t addr
= addr64
;
259 uint32_t val
= val64
;
260 int priority
, cmd
, irq
;
262 DPRINTF("write: addr=0x%02x val=0x%02x\n", addr
, val
);
268 s
->single_mode
= val
& 2;
270 qemu_log_mask(LOG_UNIMP
,
271 "i8259: level sensitive irq not supported\n");
273 } else if (val
& 0x08) {
278 s
->read_reg_select
= val
& 1;
281 s
->special_mask
= (val
>> 5) & 1;
288 s
->rotate_on_auto_eoi
= cmd
>> 2;
290 case 1: /* end of interrupt */
292 priority
= get_priority(s
, s
->isr
);
294 irq
= (priority
+ s
->priority_add
) & 7;
295 s
->isr
&= ~(1 << irq
);
297 s
->priority_add
= (irq
+ 1) & 7;
304 s
->isr
&= ~(1 << irq
);
308 s
->priority_add
= (val
+ 1) & 7;
313 s
->isr
&= ~(1 << irq
);
314 s
->priority_add
= (irq
+ 1) & 7;
323 switch (s
->init_state
) {
330 s
->irq_base
= val
& 0xf8;
331 s
->init_state
= s
->single_mode
? (s
->init4
? 3 : 0) : 2;
341 s
->special_fully_nested_mode
= (val
>> 4) & 1;
342 s
->auto_eoi
= (val
>> 1) & 1;
349 static uint64_t pic_ioport_read(void *opaque
, hwaddr addr
,
352 PICCommonState
*s
= opaque
;
356 ret
= pic_get_irq(s
);
366 if (s
->read_reg_select
) {
375 DPRINTF("read: addr=0x%02" HWADDR_PRIx
" val=0x%02x\n", addr
, ret
);
379 int pic_get_output(DeviceState
*d
)
381 PICCommonState
*s
= PIC_COMMON(d
);
383 return (pic_get_irq(s
) >= 0);
386 static void elcr_ioport_write(void *opaque
, hwaddr addr
,
387 uint64_t val
, unsigned size
)
389 PICCommonState
*s
= opaque
;
390 s
->elcr
= val
& s
->elcr_mask
;
393 static uint64_t elcr_ioport_read(void *opaque
, hwaddr addr
,
396 PICCommonState
*s
= opaque
;
400 static const MemoryRegionOps pic_base_ioport_ops
= {
401 .read
= pic_ioport_read
,
402 .write
= pic_ioport_write
,
404 .min_access_size
= 1,
405 .max_access_size
= 1,
409 static const MemoryRegionOps pic_elcr_ioport_ops
= {
410 .read
= elcr_ioport_read
,
411 .write
= elcr_ioport_write
,
413 .min_access_size
= 1,
414 .max_access_size
= 1,
418 static void pic_realize(DeviceState
*dev
, Error
**errp
)
420 PICCommonState
*s
= PIC_COMMON(dev
);
421 PICClass
*pc
= PIC_GET_CLASS(dev
);
423 memory_region_init_io(&s
->base_io
, OBJECT(s
), &pic_base_ioport_ops
, s
,
425 memory_region_init_io(&s
->elcr_io
, OBJECT(s
), &pic_elcr_ioport_ops
, s
,
428 qdev_init_gpio_out(dev
, s
->int_out
, ARRAY_SIZE(s
->int_out
));
429 qdev_init_gpio_in(dev
, pic_set_irq
, 8);
431 pc
->parent_realize(dev
, errp
);
434 void hmp_info_pic(Monitor
*mon
, const QDict
*qdict
)
442 for (i
= 0; i
< 2; i
++) {
443 s
= i
== 0 ? PIC_COMMON(isa_pic
) : slave_pic
;
444 monitor_printf(mon
, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d "
445 "irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
446 i
, s
->irr
, s
->imr
, s
->isr
, s
->priority_add
,
447 s
->irq_base
, s
->read_reg_select
, s
->elcr
,
448 s
->special_fully_nested_mode
);
452 void hmp_info_irq(Monitor
*mon
, const QDict
*qdict
)
454 #ifndef DEBUG_IRQ_COUNT
455 monitor_printf(mon
, "irq statistic code not compiled.\n");
460 monitor_printf(mon
, "IRQ statistics:\n");
461 for (i
= 0; i
< 16; i
++) {
462 count
= irq_count
[i
];
464 monitor_printf(mon
, "%2d: %" PRId64
"\n", i
, count
);
470 qemu_irq
*i8259_init(ISABus
*bus
, qemu_irq parent_irq
)
477 irq_set
= g_new0(qemu_irq
, ISA_NUM_IRQS
);
479 isadev
= i8259_init_chip(TYPE_I8259
, bus
, true);
480 dev
= DEVICE(isadev
);
482 qdev_connect_gpio_out(dev
, 0, parent_irq
);
483 for (i
= 0 ; i
< 8; i
++) {
484 irq_set
[i
] = qdev_get_gpio_in(dev
, i
);
489 isadev
= i8259_init_chip(TYPE_I8259
, bus
, false);
490 dev
= DEVICE(isadev
);
492 qdev_connect_gpio_out(dev
, 0, irq_set
[2]);
493 for (i
= 0 ; i
< 8; i
++) {
494 irq_set
[i
+ 8] = qdev_get_gpio_in(dev
, i
);
497 slave_pic
= PIC_COMMON(dev
);
502 static void i8259_class_init(ObjectClass
*klass
, void *data
)
504 PICClass
*k
= PIC_CLASS(klass
);
505 DeviceClass
*dc
= DEVICE_CLASS(klass
);
507 k
->parent_realize
= dc
->realize
;
508 dc
->realize
= pic_realize
;
509 dc
->reset
= pic_reset
;
512 static const TypeInfo i8259_info
= {
514 .instance_size
= sizeof(PICCommonState
),
515 .parent
= TYPE_PIC_COMMON
,
516 .class_init
= i8259_class_init
,
517 .class_size
= sizeof(PICClass
),
520 static void pic_register_types(void)
522 type_register_static(&i8259_info
);
525 type_init(pic_register_types
)