2 * QEMU RISC-V VirtIO machine interface
4 * Copyright (c) 2017 SiFive, Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #ifndef HW_RISCV_VIRT_H
20 #define HW_RISCV_VIRT_H
22 #include "hw/riscv/riscv_hart.h"
23 #include "hw/sysbus.h"
24 #include "hw/block/flash.h"
25 #include "qom/object.h"
27 #define VIRT_CPUS_MAX_BITS 9
28 #define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS)
29 #define VIRT_SOCKETS_MAX_BITS 2
30 #define VIRT_SOCKETS_MAX (1 << VIRT_SOCKETS_MAX_BITS)
32 #define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
33 typedef struct RISCVVirtState RISCVVirtState
;
34 DECLARE_INSTANCE_CHECKER(RISCVVirtState
, RISCV_VIRT_MACHINE
,
35 TYPE_RISCV_VIRT_MACHINE
)
37 typedef enum RISCVVirtAIAType
{
38 VIRT_AIA_TYPE_NONE
= 0,
40 VIRT_AIA_TYPE_APLIC_IMSIC
,
43 struct RISCVVirtState
{
48 Notifier machine_done
;
49 DeviceState
*platform_bus_dev
;
50 RISCVHartArrayState soc
[VIRT_SOCKETS_MAX
];
51 DeviceState
*irqchip
[VIRT_SOCKETS_MAX
];
52 PFlashCFI01
*flash
[2];
57 RISCVVirtAIAType aia_type
;
87 VIRTIO_IRQ
= 1, /* 1 to 8 */
89 PCIE_IRQ
= 0x20, /* 32 to 35 */
90 VIRT_PLATFORM_BUS_IRQ
= 64, /* 64 to 96 */
91 VIRTIO_NDEV
= 96 /* Arbitrary maximum number of interrupts */
94 #define VIRT_PLATFORM_BUS_NUM_IRQS 32
96 #define VIRT_IRQCHIP_IPI_MSI 1
97 #define VIRT_IRQCHIP_NUM_MSIS 255
98 #define VIRT_IRQCHIP_NUM_SOURCES VIRTIO_NDEV
99 #define VIRT_IRQCHIP_NUM_PRIO_BITS 3
100 #define VIRT_IRQCHIP_MAX_GUESTS_BITS 3
101 #define VIRT_IRQCHIP_MAX_GUESTS ((1U << VIRT_IRQCHIP_MAX_GUESTS_BITS) - 1U)
103 #define VIRT_PLIC_PRIORITY_BASE 0x04
104 #define VIRT_PLIC_PENDING_BASE 0x1000
105 #define VIRT_PLIC_ENABLE_BASE 0x2000
106 #define VIRT_PLIC_ENABLE_STRIDE 0x80
107 #define VIRT_PLIC_CONTEXT_BASE 0x200000
108 #define VIRT_PLIC_CONTEXT_STRIDE 0x1000
109 #define VIRT_PLIC_SIZE(__num_context) \
110 (VIRT_PLIC_CONTEXT_BASE + (__num_context) * VIRT_PLIC_CONTEXT_STRIDE)
112 #define FDT_PCI_ADDR_CELLS 3
113 #define FDT_PCI_INT_CELLS 1
114 #define FDT_PLIC_INT_CELLS 1
115 #define FDT_APLIC_INT_CELLS 2
116 #define FDT_IMSIC_INT_CELLS 0
117 #define FDT_MAX_INT_CELLS 2
118 #define FDT_MAX_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \
119 1 + FDT_MAX_INT_CELLS)
120 #define FDT_PLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \
121 1 + FDT_PLIC_INT_CELLS)
122 #define FDT_APLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \
123 1 + FDT_APLIC_INT_CELLS)