hw/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "qemu-common.h"
   5 #include "qobject.h"
   6
   7 #include "qdev.h"
   8
   9 /* PCI includes legacy ISA access.  */
  10 #include "isa.h"
  11
  12 /* PCI bus */
  13
  14 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  15 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  16 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  17
  18 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  19 #include "pci_ids.h"
  20
  21 /* QEMU-specific Vendor and Device ID definitions */
  22
  23 /* IBM (0x1014) */
  24 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  25 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  26
  27 /* Hitachi (0x1054) */
  28 #define PCI_VENDOR_ID_HITACHI            0x1054
  29 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  30
  31 /* Apple (0x106b) */
  32 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  33 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  34 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  35 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  36 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  37
  38 /* Realtek (0x10ec) */
  39 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  40
  41 /* Xilinx (0x10ee) */
  42 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  43
  44 /* Marvell (0x11ab) */
  45 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  46
  47 /* QEMU/Bochs VGA (0x1234) */
  48 #define PCI_VENDOR_ID_QEMU               0x1234
  49 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  50
  51 /* VMWare (0x15ad) */
  52 #define PCI_VENDOR_ID_VMWARE             0x15ad
  53 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  54 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  55 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  56 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  57 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  58
  59 /* Intel (0x8086) */
  60 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  61 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  62
  63 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  64 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  65 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  66 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  67
  68 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  69 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  70 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  71 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  72
  73 typedef uint64_t pcibus_t;
  74 #define FMT_PCIBUS                      PRIx64
  75
  76 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  77                                 uint32_t address, uint32_t data, int len);
  78 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  79                                    uint32_t address, int len);
  80 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  81                                 pcibus_t addr, pcibus_t size, int type);
  82 typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
  83
  84 typedef struct PCIIORegion {
  85     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
  86 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
  87     pcibus_t size;
  88     pcibus_t filtered_size;
  89     uint8_t type;
  90     PCIMapIORegionFunc *map_func;
  91 } PCIIORegion;
  92
  93 #define PCI_ROM_SLOT 6
  94 #define PCI_NUM_REGIONS 7
  95
  96 #include "pci_regs.h"
  97
  98 /* PCI HEADER_TYPE */
  99 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 100
 101 #define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \
 102                 PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \
 103                 PCI_STATUS_66MHZ | PCI_STATUS_RESERVED2 | PCI_STATUS_FAST_BACK)
 104
 105 #define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8)
 106
 107 /* Bits in the PCI Command Register (PCI 2.3 spec) */
 108 #define PCI_COMMAND_RESERVED    0xf800
 109
 110 #define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8)
 111
 112 /* Size of the standard PCI config header */
 113 #define PCI_CONFIG_HEADER_SIZE 0x40
 114 /* Size of the standard PCI config space */
 115 #define PCI_CONFIG_SPACE_SIZE 0x100
 116 /* Size of the standart PCIe config space: 4KB */
 117 #define PCIE_CONFIG_SPACE_SIZE  0x1000
 118
 119 #define PCI_NUM_PINS 4 /* A-D */
 120
 121 /* Bits in cap_present field. */
 122 enum {
 123     QEMU_PCI_CAP_MSIX = 0x1,
 124     QEMU_PCI_CAP_EXPRESS = 0x2,
 125 };
 126
 127 struct PCIDevice {
 128     DeviceState qdev;
 129     /* PCI config space */
 130     uint8_t *config;
 131
 132     /* Used to enable config checks on load. Note that writeable bits are
 133      * never checked even if set in cmask. */
 134     uint8_t *cmask;
 135
 136     /* Used to implement R/W bytes */
 137     uint8_t *wmask;
 138
 139     /* Used to allocate config space for capabilities. */
 140     uint8_t *used;
 141
 142     /* the following fields are read only */
 143     PCIBus *bus;
 144     uint32_t devfn;
 145     char name[64];
 146     PCIIORegion io_regions[PCI_NUM_REGIONS];
 147
 148     /* do not access the following fields */
 149     PCIConfigReadFunc *config_read;
 150     PCIConfigWriteFunc *config_write;
 151
 152     /* IRQ objects for the INTA-INTD pins.  */
 153     qemu_irq *irq;
 154
 155     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 156     uint8_t irq_state;
 157
 158     /* Capability bits */
 159     uint32_t cap_present;
 160
 161     /* Offset of MSI-X capability in config space */
 162     uint8_t msix_cap;
 163
 164     /* MSI-X entries */
 165     int msix_entries_nr;
 166
 167     /* Space to store MSIX table */
 168     uint8_t *msix_table_page;
 169     /* MMIO index used to map MSIX table and pending bit entries. */
 170     int msix_mmio_index;
 171     /* Reference-count for entries actually in use by driver. */
 172     unsigned *msix_entry_used;
 173     /* Region including the MSI-X table */
 174     uint32_t msix_bar_size;
 175     /* Version id needed for VMState */
 176     int32_t version_id;
 177
 178     /* Location of option rom */
 179     char *romfile;
 180     ram_addr_t rom_offset;
 181     uint32_t rom_bar;
 182 };
 183
 184 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 185                                int instance_size, int devfn,
 186                                PCIConfigReadFunc *config_read,
 187                                PCIConfigWriteFunc *config_write);
 188
 189 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 190                             pcibus_t size, int type,
 191                             PCIMapIORegionFunc *map_func);
 192
 193 int pci_add_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 194
 195 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 196
 197 void pci_reserve_capability(PCIDevice *pci_dev, uint8_t offset, uint8_t size);
 198
 199 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 200
 201
 202 uint32_t pci_default_read_config(PCIDevice *d,
 203                                  uint32_t address, int len);
 204 void pci_default_write_config(PCIDevice *d,
 205                               uint32_t address, uint32_t val, int len);
 206 void pci_device_save(PCIDevice *s, QEMUFile *f);
 207 int pci_device_load(PCIDevice *s, QEMUFile *f);
 208
 209 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 210 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 211 typedef int (*pci_hotplug_fn)(PCIDevice *pci_dev, int state);
 212 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 213                          const char *name, int devfn_min);
 214 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min);
 215 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 216                   void *irq_opaque, int nirq);
 217 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug);
 218 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 219                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 220                          void *irq_opaque, int devfn_min, int nirq);
 221
 222 void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base);
 223
 224 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 225                         const char *default_devaddr);
 226 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
 227                                const char *default_devaddr);
 228 int pci_bus_num(PCIBus *s);
 229 void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d));
 230 PCIBus *pci_find_root_bus(int domain);
 231 PCIBus *pci_find_bus(PCIBus *bus, int bus_num);
 232 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function);
 233 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
 234
 235 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 236                      unsigned *slotp);
 237
 238 void do_pci_info_print(Monitor *mon, const QObject *data);
 239 void do_pci_info(Monitor *mon, QObject **ret_data);
 240 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
 241                         pci_map_irq_fn map_irq, const char *name);
 242 PCIDevice *pci_bridge_get_device(PCIBus *bus);
 243
 244 static inline void
 245 pci_set_byte(uint8_t *config, uint8_t val)
 246 {
 247     *config = val;
 248 }
 249
 250 static inline uint8_t
 251 pci_get_byte(const uint8_t *config)
 252 {
 253     return *config;
 254 }
 255
 256 static inline void
 257 pci_set_word(uint8_t *config, uint16_t val)
 258 {
 259     cpu_to_le16wu((uint16_t *)config, val);
 260 }
 261
 262 static inline uint16_t
 263 pci_get_word(const uint8_t *config)
 264 {
 265     return le16_to_cpupu((const uint16_t *)config);
 266 }
 267
 268 static inline void
 269 pci_set_long(uint8_t *config, uint32_t val)
 270 {
 271     cpu_to_le32wu((uint32_t *)config, val);
 272 }
 273
 274 static inline uint32_t
 275 pci_get_long(const uint8_t *config)
 276 {
 277     return le32_to_cpupu((const uint32_t *)config);
 278 }
 279
 280 static inline void
 281 pci_set_quad(uint8_t *config, uint64_t val)
 282 {
 283     cpu_to_le64w((uint64_t *)config, val);
 284 }
 285
 286 static inline uint64_t
 287 pci_get_quad(const uint8_t *config)
 288 {
 289     return le64_to_cpup((const uint64_t *)config);
 290 }
 291
 292 static inline void
 293 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 294 {
 295     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 296 }
 297
 298 static inline void
 299 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 300 {
 301     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 302 }
 303
 304 static inline void
 305 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 306 {
 307     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 308 }
 309
 310 typedef int (*pci_qdev_initfn)(PCIDevice *dev);
 311 typedef struct {
 312     DeviceInfo qdev;
 313     pci_qdev_initfn init;
 314     PCIUnregisterFunc *exit;
 315     PCIConfigReadFunc *config_read;
 316     PCIConfigWriteFunc *config_write;
 317
 318     /* pci config header type */
 319     uint8_t header_type;
 320
 321     /* pcie stuff */
 322     int is_express;   /* is this device pci express? */
 323
 324     /* rom bar */
 325     const char *romfile;
 326 } PCIDeviceInfo;
 327
 328 void pci_qdev_register(PCIDeviceInfo *info);
 329 void pci_qdev_register_many(PCIDeviceInfo *info);
 330
 331 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
 332 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 333
 334 static inline int pci_is_express(PCIDevice *d)
 335 {
 336     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
 337 }
 338
 339 static inline uint32_t pci_config_size(PCIDevice *d)
 340 {
 341     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
 342 }
 343
 344 /* These are not pci specific. Should move into a separate header.
 345  * Only pci.c uses them, so keep them here for now.
 346  */
 347
 348 /* Get last byte of a range from offset + length.
 349  * Undefined for ranges that wrap around 0. */
 350 static inline uint64_t range_get_last(uint64_t offset, uint64_t len)
 351 {
 352     return offset + len - 1;
 353 }
 354
 355 /* Check whether a given range covers a given byte. */
 356 static inline int range_covers_byte(uint64_t offset, uint64_t len,
 357                                     uint64_t byte)
 358 {
 359     return offset <= byte && byte <= range_get_last(offset, len);
 360 }
 361
 362 /* Check whether 2 given ranges overlap.
 363  * Undefined if ranges that wrap around 0. */
 364 static inline int ranges_overlap(uint64_t first1, uint64_t len1,
 365                                  uint64_t first2, uint64_t len2)
 366 {
 367     uint64_t last1 = range_get_last(first1, len1);
 368     uint64_t last2 = range_get_last(first2, len2);
 369
 370     return !(last2 < first1 || last1 < first2);
 371 }
 372
 373 #endif