4 #include "host-utils.h"
7 #ifndef CONFIG_USER_ONLY
8 static inline int get_phys_addr(CPUARMState
*env
, uint32_t address
,
9 int access_type
, int is_user
,
10 uint32_t *phys_ptr
, int *prot
,
11 target_ulong
*page_size
);
14 static int vfp_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
18 /* VFP data registers are always little-endian. */
19 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
21 stfq_le_p(buf
, env
->vfp
.regs
[reg
]);
24 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
25 /* Aliases for Q regs. */
28 stfq_le_p(buf
, env
->vfp
.regs
[(reg
- 32) * 2]);
29 stfq_le_p(buf
+ 8, env
->vfp
.regs
[(reg
- 32) * 2 + 1]);
33 switch (reg
- nregs
) {
34 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
35 case 1: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSCR
]); return 4;
36 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
41 static int vfp_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
45 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
47 env
->vfp
.regs
[reg
] = ldfq_le_p(buf
);
50 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
53 env
->vfp
.regs
[(reg
- 32) * 2] = ldfq_le_p(buf
);
54 env
->vfp
.regs
[(reg
- 32) * 2 + 1] = ldfq_le_p(buf
+ 8);
58 switch (reg
- nregs
) {
59 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
60 case 1: env
->vfp
.xregs
[ARM_VFP_FPSCR
] = ldl_p(buf
); return 4;
61 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
66 static int dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
69 tlb_flush(env
, 1); /* Flush TLB as domain not tracked in TLB */
73 static int fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
75 if (env
->cp15
.c13_fcse
!= value
) {
76 /* Unlike real hardware the qemu TLB uses virtual addresses,
77 * not modified virtual addresses, so this causes a TLB flush.
80 env
->cp15
.c13_fcse
= value
;
84 static int contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
87 if (env
->cp15
.c13_context
!= value
&& !arm_feature(env
, ARM_FEATURE_MPU
)) {
88 /* For VMSA (when not using the LPAE long descriptor page table
89 * format) this register includes the ASID, so do a TLB flush.
90 * For PMSA it is purely a process ID and no action is needed.
94 env
->cp15
.c13_context
= value
;
98 static int tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
101 /* Invalidate all (TLBIALL) */
106 static int tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
109 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
110 tlb_flush_page(env
, value
& TARGET_PAGE_MASK
);
114 static int tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
117 /* Invalidate by ASID (TLBIASID) */
118 tlb_flush(env
, value
== 0);
122 static int tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
125 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
126 tlb_flush_page(env
, value
& TARGET_PAGE_MASK
);
130 static const ARMCPRegInfo cp_reginfo
[] = {
131 /* DBGDIDR: just RAZ. In particular this means the "debug architecture
132 * version" bits will read as a reserved value, which should cause
133 * Linux to not try to use the debug hardware.
135 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
136 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
137 /* MMU Domain access control / MPU write buffer control */
138 { .name
= "DACR", .cp
= 15,
139 .crn
= 3, .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
140 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c3
),
141 .resetvalue
= 0, .writefn
= dacr_write
},
142 { .name
= "FCSEIDR", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 0,
143 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_fcse
),
144 .resetvalue
= 0, .writefn
= fcse_write
},
145 { .name
= "CONTEXTIDR", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 1,
146 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_fcse
),
147 .resetvalue
= 0, .writefn
= contextidr_write
},
148 /* ??? This covers not just the impdef TLB lockdown registers but also
149 * some v7VMSA registers relating to TEX remap, so it is overly broad.
151 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= CP_ANY
,
152 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
153 /* MMU TLB control. Note that the wildcarding means we cover not just
154 * the unified TLB ops but also the dside/iside/inner-shareable variants.
156 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
157 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
, },
158 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
159 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
, },
160 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
161 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
, },
162 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
163 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
, },
164 /* Cache maintenance ops; some of this space may be overridden later. */
165 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
166 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
167 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
171 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
172 /* Not all pre-v6 cores implemented this WFI, so this is slightly
175 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
176 .access
= PL1_W
, .type
= ARM_CP_WFI
},
180 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
181 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
182 * is UNPREDICTABLE; we choose to NOP as most implementations do).
184 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
185 .access
= PL1_W
, .type
= ARM_CP_WFI
},
186 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
187 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
188 * OMAPCP will override this space.
190 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
191 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
193 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
194 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
196 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
197 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
198 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
202 static int cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
204 if (env
->cp15
.c1_coproc
!= value
) {
205 env
->cp15
.c1_coproc
= value
;
206 /* ??? Is this safe when called from within a TB? */
212 static const ARMCPRegInfo v6_cp_reginfo
[] = {
213 /* prefetch by MVA in v6, NOP in v7 */
214 { .name
= "MVA_prefetch",
215 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
216 .access
= PL1_W
, .type
= ARM_CP_NOP
},
217 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
218 .access
= PL0_W
, .type
= ARM_CP_NOP
},
219 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
220 .access
= PL0_W
, .type
= ARM_CP_NOP
},
221 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
222 .access
= PL0_W
, .type
= ARM_CP_NOP
},
223 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
224 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_insn
),
226 /* Watchpoint Fault Address Register : should actually only be present
227 * for 1136, 1176, 11MPCore.
229 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
230 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
231 { .name
= "CPACR", .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2,
232 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_coproc
),
233 .resetvalue
= 0, .writefn
= cpacr_write
},
237 static int pmreg_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
240 /* Generic performance monitor register read function for where
241 * user access may be allowed by PMUSERENR.
243 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
246 *value
= CPREG_FIELD32(env
, ri
);
250 static int pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
253 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
256 /* only the DP, X, D and E bits are writable */
257 env
->cp15
.c9_pmcr
&= ~0x39;
258 env
->cp15
.c9_pmcr
|= (value
& 0x39);
262 static int pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
265 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
269 env
->cp15
.c9_pmcnten
|= value
;
273 static int pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
276 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
280 env
->cp15
.c9_pmcnten
&= ~value
;
284 static int pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
287 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
290 env
->cp15
.c9_pmovsr
&= ~value
;
294 static int pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
297 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
300 env
->cp15
.c9_pmxevtyper
= value
& 0xff;
304 static int pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
307 env
->cp15
.c9_pmuserenr
= value
& 1;
311 static int pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
314 /* We have no event counters so only the C bit can be changed */
316 env
->cp15
.c9_pminten
|= value
;
320 static int pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
324 env
->cp15
.c9_pminten
&= ~value
;
328 static int ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
331 ARMCPU
*cpu
= arm_env_get_cpu(env
);
332 *value
= cpu
->ccsidr
[env
->cp15
.c0_cssel
];
336 static int csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
339 env
->cp15
.c0_cssel
= value
& 0xf;
343 static const ARMCPRegInfo v7_cp_reginfo
[] = {
344 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
347 { .name
= "DBGDRAR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
348 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
349 { .name
= "DBGDRAR", .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
350 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
351 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
352 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
353 .access
= PL1_W
, .type
= ARM_CP_NOP
},
354 /* Performance monitors are implementation defined in v7,
355 * but with an ARM recommended set of registers, which we
356 * follow (although we don't actually implement any counters)
358 * Performance registers fall into three categories:
359 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
360 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
361 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
362 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
363 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
365 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
366 .access
= PL0_RW
, .resetvalue
= 0,
367 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
368 .readfn
= pmreg_read
, .writefn
= pmcntenset_write
},
369 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
370 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
371 .readfn
= pmreg_read
, .writefn
= pmcntenclr_write
},
372 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
373 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
374 .readfn
= pmreg_read
, .writefn
= pmovsr_write
},
375 /* Unimplemented so WI. Strictly speaking write accesses in PL0 should
378 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
379 .access
= PL0_W
, .type
= ARM_CP_NOP
},
380 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
381 * We choose to RAZ/WI. XXX should respect PMUSERENR.
383 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
384 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
385 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
386 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
387 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
388 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
390 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmxevtyper
),
391 .readfn
= pmreg_read
, .writefn
= pmxevtyper_write
},
392 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
393 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
394 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
395 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
396 .access
= PL0_R
| PL1_RW
,
397 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
399 .writefn
= pmuserenr_write
},
400 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
402 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
404 .writefn
= pmintenset_write
},
405 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
407 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
409 .writefn
= pmintenclr_write
},
410 { .name
= "SCR", .cp
= 15, .crn
= 1, .crm
= 1, .opc1
= 0, .opc2
= 0,
411 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_scr
),
413 { .name
= "CCSIDR", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
414 .access
= PL1_R
, .readfn
= ccsidr_read
},
415 { .name
= "CSSELR", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
416 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cssel
),
417 .writefn
= csselr_write
, .resetvalue
= 0 },
418 /* Auxiliary ID register: this actually has an IMPDEF value but for now
419 * just RAZ for all cores:
421 { .name
= "AIDR", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 7,
422 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
426 static int teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
433 static int teehbr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
436 /* This is a helper function because the user access rights
437 * depend on the value of the TEECR.
439 if (arm_current_pl(env
) == 0 && (env
->teecr
& 1)) {
442 *value
= env
->teehbr
;
446 static int teehbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
449 if (arm_current_pl(env
) == 0 && (env
->teecr
& 1)) {
456 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
457 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
458 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
460 .writefn
= teecr_write
},
461 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
462 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
464 .readfn
= teehbr_read
, .writefn
= teehbr_write
},
468 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
469 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
471 .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_tls1
),
473 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
474 .access
= PL0_R
|PL1_W
,
475 .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_tls2
),
477 { .name
= "TPIDRPRW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 4,
479 .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_tls3
),
484 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
485 /* Dummy implementation: RAZ/WI the whole crn=14 space */
486 { .name
= "GENERIC_TIMER", .cp
= 15, .crn
= 14,
487 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
488 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
492 static int par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
494 if (arm_feature(env
, ARM_FEATURE_V7
)) {
495 env
->cp15
.c7_par
= value
& 0xfffff6ff;
497 env
->cp15
.c7_par
= value
& 0xfffff1ff;
502 #ifndef CONFIG_USER_ONLY
503 /* get_phys_addr() isn't present for user-mode-only targets */
504 static int ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
507 target_ulong page_size
;
509 int ret
, is_user
= ri
->opc2
& 2;
510 int access_type
= ri
->opc2
& 1;
513 /* Other states are only available with TrustZone */
516 ret
= get_phys_addr(env
, value
, access_type
, is_user
,
517 &phys_addr
, &prot
, &page_size
);
519 /* We do not set any attribute bits in the PAR */
520 if (page_size
== (1 << 24)
521 && arm_feature(env
, ARM_FEATURE_V7
)) {
522 env
->cp15
.c7_par
= (phys_addr
& 0xff000000) | 1 << 1;
524 env
->cp15
.c7_par
= phys_addr
& 0xfffff000;
527 env
->cp15
.c7_par
= ((ret
& (10 << 1)) >> 5) |
528 ((ret
& (12 << 1)) >> 6) |
529 ((ret
& 0xf) << 1) | 1;
535 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
536 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
537 .access
= PL1_RW
, .resetvalue
= 0,
538 .fieldoffset
= offsetof(CPUARMState
, cp15
.c7_par
),
539 .writefn
= par_write
},
540 #ifndef CONFIG_USER_ONLY
541 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
542 .access
= PL1_W
, .writefn
= ats_write
},
547 /* Return basic MPU access permission bits. */
548 static uint32_t simple_mpu_ap_bits(uint32_t val
)
555 for (i
= 0; i
< 16; i
+= 2) {
556 ret
|= (val
>> i
) & mask
;
562 /* Pad basic MPU access permission bits to extended format. */
563 static uint32_t extended_mpu_ap_bits(uint32_t val
)
570 for (i
= 0; i
< 16; i
+= 2) {
571 ret
|= (val
& mask
) << i
;
577 static int pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
580 env
->cp15
.c5_data
= extended_mpu_ap_bits(value
);
584 static int pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
587 *value
= simple_mpu_ap_bits(env
->cp15
.c5_data
);
591 static int pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
594 env
->cp15
.c5_insn
= extended_mpu_ap_bits(value
);
598 static int pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
601 *value
= simple_mpu_ap_bits(env
->cp15
.c5_insn
);
605 static int arm946_prbs_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
611 *value
= env
->cp15
.c6_region
[ri
->crm
];
615 static int arm946_prbs_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
621 env
->cp15
.c6_region
[ri
->crm
] = value
;
625 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
626 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
628 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0,
629 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
630 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
632 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_insn
), .resetvalue
= 0,
633 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
634 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
636 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0, },
637 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
639 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_insn
), .resetvalue
= 0, },
640 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
642 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
643 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
645 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
646 /* Protection region base and size registers */
647 { .name
= "946_PRBS", .cp
= 15, .crn
= 6, .crm
= CP_ANY
, .opc1
= 0,
648 .opc2
= CP_ANY
, .access
= PL1_RW
,
649 .readfn
= arm946_prbs_read
, .writefn
= arm946_prbs_write
, },
653 static int vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
657 env
->cp15
.c2_control
= value
;
658 env
->cp15
.c2_mask
= ~(((uint32_t)0xffffffffu
) >> value
);
659 env
->cp15
.c2_base_mask
= ~((uint32_t)0x3fffu
>> value
);
663 static void vmsa_ttbcr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
665 env
->cp15
.c2_base_mask
= 0xffffc000u
;
666 env
->cp15
.c2_control
= 0;
667 env
->cp15
.c2_mask
= 0;
670 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
671 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
673 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0, },
674 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
676 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_insn
), .resetvalue
= 0, },
677 { .name
= "TTBR0", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
679 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_base0
), .resetvalue
= 0, },
680 { .name
= "TTBR1", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
682 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_base0
), .resetvalue
= 0, },
683 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
684 .access
= PL1_RW
, .writefn
= vmsa_ttbcr_write
,
685 .resetfn
= vmsa_ttbcr_reset
,
686 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_control
) },
687 { .name
= "DFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
688 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_data
),
693 static int omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
696 env
->cp15
.c15_ticonfig
= value
& 0xe7;
697 /* The OS_TYPE bit in this register changes the reported CPUID! */
698 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
699 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
703 static int omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
706 env
->cp15
.c15_threadid
= value
& 0xffff;
710 static int omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
713 /* Wait-for-interrupt (deprecated) */
714 cpu_interrupt(env
, CPU_INTERRUPT_HALT
);
718 static int omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
721 /* On OMAP there are registers indicating the max/min index of dcache lines
722 * containing a dirty line; cache flush operations have to reset these.
724 env
->cp15
.c15_i_max
= 0x000;
725 env
->cp15
.c15_i_min
= 0xff0;
729 static const ARMCPRegInfo omap_cp_reginfo
[] = {
730 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
731 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
732 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0, },
733 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
734 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
735 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
737 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
738 .writefn
= omap_ticonfig_write
},
739 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
741 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
742 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
743 .access
= PL1_RW
, .resetvalue
= 0xff0,
744 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
745 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
747 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
748 .writefn
= omap_threadid_write
},
749 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
750 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
751 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
752 /* TODO: Peripheral port remap register:
753 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
754 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
757 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
758 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
, .type
= ARM_CP_OVERRIDE
,
759 .writefn
= omap_cachemaint_write
},
760 { .name
= "C9", .cp
= 15, .crn
= 9,
761 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
762 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
766 static int xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
770 if (env
->cp15
.c15_cpar
!= value
) {
771 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
773 env
->cp15
.c15_cpar
= value
;
778 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
779 { .name
= "XSCALE_CPAR",
780 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
781 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
782 .writefn
= xscale_cpar_write
, },
783 { .name
= "XSCALE_AUXCR",
784 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
785 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
790 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
791 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
792 * implementation of this implementation-defined space.
793 * Ideally this should eventually disappear in favour of actually
794 * implementing the correct behaviour for all cores.
796 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
797 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
798 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
802 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
803 /* Cache status: RAZ because we have no cache so it's always clean */
804 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
805 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
809 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
810 /* We never have a a block transfer operation in progress */
811 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
812 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
813 /* The cache ops themselves: these all NOP for QEMU */
814 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
815 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
816 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
817 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
818 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
819 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
820 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
821 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
822 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
823 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
824 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
825 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
829 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
830 /* The cache test-and-clean instructions always return (1 << 30)
831 * to indicate that there are no dirty cache lines.
833 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
834 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= (1 << 30) },
835 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
836 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= (1 << 30) },
840 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
841 /* Ignore ReadBuffer accesses */
842 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
843 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
844 .access
= PL1_RW
, .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
,
849 static int mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
852 uint32_t mpidr
= env
->cpu_index
;
853 /* We don't support setting cluster ID ([8..11])
854 * so these bits always RAZ.
856 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
858 /* Cores which are uniprocessor (non-coherent)
859 * but still implement the MP extensions set
860 * bit 30. (For instance, A9UP.) However we do
861 * not currently model any of those cores.
868 static const ARMCPRegInfo mpidr_cp_reginfo
[] = {
869 { .name
= "MPIDR", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
870 .access
= PL1_R
, .readfn
= mpidr_read
},
874 static int sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
876 env
->cp15
.c1_sys
= value
;
877 /* ??? Lots of these bits are not implemented. */
878 /* This may enable/disable the MMU, so do a TLB flush. */
883 void register_cp_regs_for_features(ARMCPU
*cpu
)
885 /* Register all the coprocessor registers based on feature bits */
886 CPUARMState
*env
= &cpu
->env
;
887 if (arm_feature(env
, ARM_FEATURE_M
)) {
888 /* M profile has no coprocessor registers */
892 define_arm_cp_regs(cpu
, cp_reginfo
);
893 if (arm_feature(env
, ARM_FEATURE_V6
)) {
894 /* The ID registers all have impdef reset values */
895 ARMCPRegInfo v6_idregs
[] = {
896 { .name
= "ID_PFR0", .cp
= 15, .crn
= 0, .crm
= 1,
897 .opc1
= 0, .opc2
= 0, .access
= PL1_R
, .type
= ARM_CP_CONST
,
898 .resetvalue
= cpu
->id_pfr0
},
899 { .name
= "ID_PFR1", .cp
= 15, .crn
= 0, .crm
= 1,
900 .opc1
= 0, .opc2
= 1, .access
= PL1_R
, .type
= ARM_CP_CONST
,
901 .resetvalue
= cpu
->id_pfr1
},
902 { .name
= "ID_DFR0", .cp
= 15, .crn
= 0, .crm
= 1,
903 .opc1
= 0, .opc2
= 2, .access
= PL1_R
, .type
= ARM_CP_CONST
,
904 .resetvalue
= cpu
->id_dfr0
},
905 { .name
= "ID_AFR0", .cp
= 15, .crn
= 0, .crm
= 1,
906 .opc1
= 0, .opc2
= 3, .access
= PL1_R
, .type
= ARM_CP_CONST
,
907 .resetvalue
= cpu
->id_afr0
},
908 { .name
= "ID_MMFR0", .cp
= 15, .crn
= 0, .crm
= 1,
909 .opc1
= 0, .opc2
= 4, .access
= PL1_R
, .type
= ARM_CP_CONST
,
910 .resetvalue
= cpu
->id_mmfr0
},
911 { .name
= "ID_MMFR1", .cp
= 15, .crn
= 0, .crm
= 1,
912 .opc1
= 0, .opc2
= 5, .access
= PL1_R
, .type
= ARM_CP_CONST
,
913 .resetvalue
= cpu
->id_mmfr1
},
914 { .name
= "ID_MMFR2", .cp
= 15, .crn
= 0, .crm
= 1,
915 .opc1
= 0, .opc2
= 6, .access
= PL1_R
, .type
= ARM_CP_CONST
,
916 .resetvalue
= cpu
->id_mmfr2
},
917 { .name
= "ID_MMFR3", .cp
= 15, .crn
= 0, .crm
= 1,
918 .opc1
= 0, .opc2
= 7, .access
= PL1_R
, .type
= ARM_CP_CONST
,
919 .resetvalue
= cpu
->id_mmfr3
},
920 { .name
= "ID_ISAR0", .cp
= 15, .crn
= 0, .crm
= 2,
921 .opc1
= 0, .opc2
= 0, .access
= PL1_R
, .type
= ARM_CP_CONST
,
922 .resetvalue
= cpu
->id_isar0
},
923 { .name
= "ID_ISAR1", .cp
= 15, .crn
= 0, .crm
= 2,
924 .opc1
= 0, .opc2
= 1, .access
= PL1_R
, .type
= ARM_CP_CONST
,
925 .resetvalue
= cpu
->id_isar1
},
926 { .name
= "ID_ISAR2", .cp
= 15, .crn
= 0, .crm
= 2,
927 .opc1
= 0, .opc2
= 2, .access
= PL1_R
, .type
= ARM_CP_CONST
,
928 .resetvalue
= cpu
->id_isar2
},
929 { .name
= "ID_ISAR3", .cp
= 15, .crn
= 0, .crm
= 2,
930 .opc1
= 0, .opc2
= 3, .access
= PL1_R
, .type
= ARM_CP_CONST
,
931 .resetvalue
= cpu
->id_isar3
},
932 { .name
= "ID_ISAR4", .cp
= 15, .crn
= 0, .crm
= 2,
933 .opc1
= 0, .opc2
= 4, .access
= PL1_R
, .type
= ARM_CP_CONST
,
934 .resetvalue
= cpu
->id_isar4
},
935 { .name
= "ID_ISAR5", .cp
= 15, .crn
= 0, .crm
= 2,
936 .opc1
= 0, .opc2
= 5, .access
= PL1_R
, .type
= ARM_CP_CONST
,
937 .resetvalue
= cpu
->id_isar5
},
938 /* 6..7 are as yet unallocated and must RAZ */
939 { .name
= "ID_ISAR6", .cp
= 15, .crn
= 0, .crm
= 2,
940 .opc1
= 0, .opc2
= 6, .access
= PL1_R
, .type
= ARM_CP_CONST
,
942 { .name
= "ID_ISAR7", .cp
= 15, .crn
= 0, .crm
= 2,
943 .opc1
= 0, .opc2
= 7, .access
= PL1_R
, .type
= ARM_CP_CONST
,
947 define_arm_cp_regs(cpu
, v6_idregs
);
948 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
950 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
952 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
953 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
955 if (arm_feature(env
, ARM_FEATURE_V7
)) {
956 /* v7 performance monitor control register: same implementor
957 * field as main ID register, and we implement no event counters.
959 ARMCPRegInfo pmcr
= {
960 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
961 .access
= PL0_RW
, .resetvalue
= cpu
->midr
& 0xff000000,
962 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
963 .readfn
= pmreg_read
, .writefn
= pmcr_write
965 ARMCPRegInfo clidr
= {
966 .name
= "CLIDR", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
967 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->clidr
969 define_one_arm_cp_reg(cpu
, &pmcr
);
970 define_one_arm_cp_reg(cpu
, &clidr
);
971 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
973 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
975 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
976 /* These are the MPU registers prior to PMSAv6. Any new
977 * PMSA core later than the ARM946 will require that we
978 * implement the PMSAv6 or PMSAv7 registers, which are
979 * completely different.
981 assert(!arm_feature(env
, ARM_FEATURE_V6
));
982 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
984 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
986 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
987 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
989 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
990 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
992 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
993 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
995 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
996 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
998 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
999 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
1001 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
1002 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
1004 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
1005 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
1007 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
1008 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
1010 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1011 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
1013 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
1014 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
1016 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
1017 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
1019 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
1020 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
1021 * be read-only (ie write causes UNDEF exception).
1024 ARMCPRegInfo id_cp_reginfo
[] = {
1025 /* Note that the MIDR isn't a simple constant register because
1026 * of the TI925 behaviour where writes to another register can
1027 * cause the MIDR value to change.
1030 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
1031 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
1032 .writefn
= arm_cp_write_ignore
,
1033 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
) },
1035 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
1036 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
1038 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
1039 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1041 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
1042 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1043 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
1045 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
1046 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1048 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
1049 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1051 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
1052 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1054 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
1055 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1057 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
1058 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1061 ARMCPRegInfo crn0_wi_reginfo
= {
1062 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
1063 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
1064 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
1066 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
1067 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
1069 /* Register the blanket "writes ignored" value first to cover the
1070 * whole space. Then define the specific ID registers, but update
1071 * their access field to allow write access, so that they ignore
1072 * writes rather than causing them to UNDEF.
1074 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
1075 for (r
= id_cp_reginfo
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
1077 define_one_arm_cp_reg(cpu
, r
);
1080 /* Just register the standard ID registers (read-only, meaning
1081 * that writes will UNDEF).
1083 define_arm_cp_regs(cpu
, id_cp_reginfo
);
1087 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
1088 ARMCPRegInfo auxcr
= {
1089 .name
= "AUXCR", .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1,
1090 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
1091 .resetvalue
= cpu
->reset_auxcr
1093 define_one_arm_cp_reg(cpu
, &auxcr
);
1096 /* Generic registers whose values depend on the implementation */
1098 ARMCPRegInfo sctlr
= {
1099 .name
= "SCTLR", .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
1100 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_sys
),
1101 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
1103 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1104 /* Normally we would always end the TB on an SCTLR write, but Linux
1105 * arch/arm/mach-pxa/sleep.S expects two instructions following
1106 * an MMU enable to execute from cache. Imitate this behaviour.
1108 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
1110 define_one_arm_cp_reg(cpu
, &sctlr
);
1114 ARMCPU
*cpu_arm_init(const char *cpu_model
)
1118 static int inited
= 0;
1120 if (!object_class_by_name(cpu_model
)) {
1123 cpu
= ARM_CPU(object_new(cpu_model
));
1125 env
->cpu_model_str
= cpu_model
;
1126 arm_cpu_realize(cpu
);
1128 if (tcg_enabled() && !inited
) {
1130 arm_translate_init();
1133 cpu_reset(CPU(cpu
));
1134 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
1135 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
1136 51, "arm-neon.xml", 0);
1137 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
1138 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
1139 35, "arm-vfp3.xml", 0);
1140 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
1141 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
1142 19, "arm-vfp.xml", 0);
1144 qemu_init_vcpu(env
);
1148 typedef struct ARMCPUListState
{
1149 fprintf_function cpu_fprintf
;
1153 /* Sort alphabetically by type name, except for "any". */
1154 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
1156 ObjectClass
*class_a
= (ObjectClass
*)a
;
1157 ObjectClass
*class_b
= (ObjectClass
*)b
;
1158 const char *name_a
, *name_b
;
1160 name_a
= object_class_get_name(class_a
);
1161 name_b
= object_class_get_name(class_b
);
1162 if (strcmp(name_a
, "any") == 0) {
1164 } else if (strcmp(name_b
, "any") == 0) {
1167 return strcmp(name_a
, name_b
);
1171 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
1173 ObjectClass
*oc
= data
;
1174 ARMCPUListState
*s
= user_data
;
1176 (*s
->cpu_fprintf
)(s
->file
, " %s\n",
1177 object_class_get_name(oc
));
1180 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
1182 ARMCPUListState s
= {
1184 .cpu_fprintf
= cpu_fprintf
,
1188 list
= object_class_get_list(TYPE_ARM_CPU
, false);
1189 list
= g_slist_sort(list
, arm_cpu_list_compare
);
1190 (*cpu_fprintf
)(f
, "Available CPUs:\n");
1191 g_slist_foreach(list
, arm_cpu_list_entry
, &s
);
1195 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
1196 const ARMCPRegInfo
*r
, void *opaque
)
1198 /* Define implementations of coprocessor registers.
1199 * We store these in a hashtable because typically
1200 * there are less than 150 registers in a space which
1201 * is 16*16*16*8*8 = 262144 in size.
1202 * Wildcarding is supported for the crm, opc1 and opc2 fields.
1203 * If a register is defined twice then the second definition is
1204 * used, so this can be used to define some generic registers and
1205 * then override them with implementation specific variations.
1206 * At least one of the original and the second definition should
1207 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
1208 * against accidental use.
1210 int crm
, opc1
, opc2
;
1211 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
1212 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
1213 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
1214 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
1215 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
1216 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
1217 /* 64 bit registers have only CRm and Opc1 fields */
1218 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
1219 /* Check that the register definition has enough info to handle
1220 * reads and writes if they are permitted.
1222 if (!(r
->type
& (ARM_CP_SPECIAL
|ARM_CP_CONST
))) {
1223 if (r
->access
& PL3_R
) {
1224 assert(r
->fieldoffset
|| r
->readfn
);
1226 if (r
->access
& PL3_W
) {
1227 assert(r
->fieldoffset
|| r
->writefn
);
1230 /* Bad type field probably means missing sentinel at end of reg list */
1231 assert(cptype_valid(r
->type
));
1232 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
1233 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
1234 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
1235 uint32_t *key
= g_new(uint32_t, 1);
1236 ARMCPRegInfo
*r2
= g_memdup(r
, sizeof(ARMCPRegInfo
));
1237 int is64
= (r
->type
& ARM_CP_64BIT
) ? 1 : 0;
1238 *key
= ENCODE_CP_REG(r
->cp
, is64
, r
->crn
, crm
, opc1
, opc2
);
1239 r2
->opaque
= opaque
;
1240 /* Make sure reginfo passed to helpers for wildcarded regs
1241 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
1246 /* Overriding of an existing definition must be explicitly
1249 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
1250 ARMCPRegInfo
*oldreg
;
1251 oldreg
= g_hash_table_lookup(cpu
->cp_regs
, key
);
1252 if (oldreg
&& !(oldreg
->type
& ARM_CP_OVERRIDE
)) {
1253 fprintf(stderr
, "Register redefined: cp=%d %d bit "
1254 "crn=%d crm=%d opc1=%d opc2=%d, "
1255 "was %s, now %s\n", r2
->cp
, 32 + 32 * is64
,
1256 r2
->crn
, r2
->crm
, r2
->opc1
, r2
->opc2
,
1257 oldreg
->name
, r2
->name
);
1261 g_hash_table_insert(cpu
->cp_regs
, key
, r2
);
1267 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
1268 const ARMCPRegInfo
*regs
, void *opaque
)
1270 /* Define a whole list of registers */
1271 const ARMCPRegInfo
*r
;
1272 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
1273 define_one_arm_cp_reg_with_opaque(cpu
, r
, opaque
);
1277 const ARMCPRegInfo
*get_arm_cp_reginfo(ARMCPU
*cpu
, uint32_t encoded_cp
)
1279 return g_hash_table_lookup(cpu
->cp_regs
, &encoded_cp
);
1282 int arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1285 /* Helper coprocessor write function for write-ignore registers */
1289 int arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t *value
)
1291 /* Helper coprocessor write function for read-as-zero registers */
1296 static int bad_mode_switch(CPUARMState
*env
, int mode
)
1298 /* Return true if it is not valid for us to switch to
1299 * this CPU mode (ie all the UNPREDICTABLE cases in
1300 * the ARM ARM CPSRWriteByInstr pseudocode).
1303 case ARM_CPU_MODE_USR
:
1304 case ARM_CPU_MODE_SYS
:
1305 case ARM_CPU_MODE_SVC
:
1306 case ARM_CPU_MODE_ABT
:
1307 case ARM_CPU_MODE_UND
:
1308 case ARM_CPU_MODE_IRQ
:
1309 case ARM_CPU_MODE_FIQ
:
1316 uint32_t cpsr_read(CPUARMState
*env
)
1319 ZF
= (env
->ZF
== 0);
1320 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
1321 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
1322 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
1323 | ((env
->condexec_bits
& 0xfc) << 8)
1327 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
1329 if (mask
& CPSR_NZCV
) {
1330 env
->ZF
= (~val
) & CPSR_Z
;
1332 env
->CF
= (val
>> 29) & 1;
1333 env
->VF
= (val
<< 3) & 0x80000000;
1336 env
->QF
= ((val
& CPSR_Q
) != 0);
1338 env
->thumb
= ((val
& CPSR_T
) != 0);
1339 if (mask
& CPSR_IT_0_1
) {
1340 env
->condexec_bits
&= ~3;
1341 env
->condexec_bits
|= (val
>> 25) & 3;
1343 if (mask
& CPSR_IT_2_7
) {
1344 env
->condexec_bits
&= 3;
1345 env
->condexec_bits
|= (val
>> 8) & 0xfc;
1347 if (mask
& CPSR_GE
) {
1348 env
->GE
= (val
>> 16) & 0xf;
1351 if ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
) {
1352 if (bad_mode_switch(env
, val
& CPSR_M
)) {
1353 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
1354 * We choose to ignore the attempt and leave the CPSR M field
1359 switch_mode(env
, val
& CPSR_M
);
1362 mask
&= ~CACHED_CPSR_BITS
;
1363 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
1366 /* Sign/zero extend */
1367 uint32_t HELPER(sxtb16
)(uint32_t x
)
1370 res
= (uint16_t)(int8_t)x
;
1371 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
1375 uint32_t HELPER(uxtb16
)(uint32_t x
)
1378 res
= (uint16_t)(uint8_t)x
;
1379 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
1383 uint32_t HELPER(clz
)(uint32_t x
)
1388 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
1392 if (num
== INT_MIN
&& den
== -1)
1397 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
1404 uint32_t HELPER(rbit
)(uint32_t x
)
1406 x
= ((x
& 0xff000000) >> 24)
1407 | ((x
& 0x00ff0000) >> 8)
1408 | ((x
& 0x0000ff00) << 8)
1409 | ((x
& 0x000000ff) << 24);
1410 x
= ((x
& 0xf0f0f0f0) >> 4)
1411 | ((x
& 0x0f0f0f0f) << 4);
1412 x
= ((x
& 0x88888888) >> 3)
1413 | ((x
& 0x44444444) >> 1)
1414 | ((x
& 0x22222222) << 1)
1415 | ((x
& 0x11111111) << 3);
1419 uint32_t HELPER(abs
)(uint32_t x
)
1421 return ((int32_t)x
< 0) ? -x
: x
;
1424 #if defined(CONFIG_USER_ONLY)
1426 void do_interrupt (CPUARMState
*env
)
1428 env
->exception_index
= -1;
1431 int cpu_arm_handle_mmu_fault (CPUARMState
*env
, target_ulong address
, int rw
,
1435 env
->exception_index
= EXCP_PREFETCH_ABORT
;
1436 env
->cp15
.c6_insn
= address
;
1438 env
->exception_index
= EXCP_DATA_ABORT
;
1439 env
->cp15
.c6_data
= address
;
1444 /* These should probably raise undefined insn exceptions. */
1445 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
1447 cpu_abort(env
, "v7m_mrs %d\n", reg
);
1450 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
1452 cpu_abort(env
, "v7m_mrs %d\n", reg
);
1456 void switch_mode(CPUARMState
*env
, int mode
)
1458 if (mode
!= ARM_CPU_MODE_USR
)
1459 cpu_abort(env
, "Tried to switch out of user mode\n");
1462 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
1464 cpu_abort(env
, "banked r13 write\n");
1467 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
1469 cpu_abort(env
, "banked r13 read\n");
1475 /* Map CPU modes onto saved register banks. */
1476 static inline int bank_number(CPUARMState
*env
, int mode
)
1479 case ARM_CPU_MODE_USR
:
1480 case ARM_CPU_MODE_SYS
:
1482 case ARM_CPU_MODE_SVC
:
1484 case ARM_CPU_MODE_ABT
:
1486 case ARM_CPU_MODE_UND
:
1488 case ARM_CPU_MODE_IRQ
:
1490 case ARM_CPU_MODE_FIQ
:
1493 cpu_abort(env
, "Bad mode %x\n", mode
);
1497 void switch_mode(CPUARMState
*env
, int mode
)
1502 old_mode
= env
->uncached_cpsr
& CPSR_M
;
1503 if (mode
== old_mode
)
1506 if (old_mode
== ARM_CPU_MODE_FIQ
) {
1507 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
1508 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
1509 } else if (mode
== ARM_CPU_MODE_FIQ
) {
1510 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
1511 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
1514 i
= bank_number(env
, old_mode
);
1515 env
->banked_r13
[i
] = env
->regs
[13];
1516 env
->banked_r14
[i
] = env
->regs
[14];
1517 env
->banked_spsr
[i
] = env
->spsr
;
1519 i
= bank_number(env
, mode
);
1520 env
->regs
[13] = env
->banked_r13
[i
];
1521 env
->regs
[14] = env
->banked_r14
[i
];
1522 env
->spsr
= env
->banked_spsr
[i
];
1525 static void v7m_push(CPUARMState
*env
, uint32_t val
)
1528 stl_phys(env
->regs
[13], val
);
1531 static uint32_t v7m_pop(CPUARMState
*env
)
1534 val
= ldl_phys(env
->regs
[13]);
1539 /* Switch to V7M main or process stack pointer. */
1540 static void switch_v7m_sp(CPUARMState
*env
, int process
)
1543 if (env
->v7m
.current_sp
!= process
) {
1544 tmp
= env
->v7m
.other_sp
;
1545 env
->v7m
.other_sp
= env
->regs
[13];
1546 env
->regs
[13] = tmp
;
1547 env
->v7m
.current_sp
= process
;
1551 static void do_v7m_exception_exit(CPUARMState
*env
)
1556 type
= env
->regs
[15];
1557 if (env
->v7m
.exception
!= 0)
1558 armv7m_nvic_complete_irq(env
->nvic
, env
->v7m
.exception
);
1560 /* Switch to the target stack. */
1561 switch_v7m_sp(env
, (type
& 4) != 0);
1562 /* Pop registers. */
1563 env
->regs
[0] = v7m_pop(env
);
1564 env
->regs
[1] = v7m_pop(env
);
1565 env
->regs
[2] = v7m_pop(env
);
1566 env
->regs
[3] = v7m_pop(env
);
1567 env
->regs
[12] = v7m_pop(env
);
1568 env
->regs
[14] = v7m_pop(env
);
1569 env
->regs
[15] = v7m_pop(env
);
1570 xpsr
= v7m_pop(env
);
1571 xpsr_write(env
, xpsr
, 0xfffffdff);
1572 /* Undo stack alignment. */
1575 /* ??? The exception return type specifies Thread/Handler mode. However
1576 this is also implied by the xPSR value. Not sure what to do
1577 if there is a mismatch. */
1578 /* ??? Likewise for mismatches between the CONTROL register and the stack
1582 static void do_interrupt_v7m(CPUARMState
*env
)
1584 uint32_t xpsr
= xpsr_read(env
);
1589 if (env
->v7m
.current_sp
)
1591 if (env
->v7m
.exception
== 0)
1594 /* For exceptions we just mark as pending on the NVIC, and let that
1596 /* TODO: Need to escalate if the current priority is higher than the
1597 one we're raising. */
1598 switch (env
->exception_index
) {
1600 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
);
1604 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SVC
);
1606 case EXCP_PREFETCH_ABORT
:
1607 case EXCP_DATA_ABORT
:
1608 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
);
1611 if (semihosting_enabled
) {
1613 nr
= arm_lduw_code(env
->regs
[15], env
->bswap_code
) & 0xff;
1616 env
->regs
[0] = do_arm_semihosting(env
);
1620 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_DEBUG
);
1623 env
->v7m
.exception
= armv7m_nvic_acknowledge_irq(env
->nvic
);
1625 case EXCP_EXCEPTION_EXIT
:
1626 do_v7m_exception_exit(env
);
1629 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
1630 return; /* Never happens. Keep compiler happy. */
1633 /* Align stack pointer. */
1634 /* ??? Should only do this if Configuration Control Register
1635 STACKALIGN bit is set. */
1636 if (env
->regs
[13] & 4) {
1640 /* Switch to the handler mode. */
1641 v7m_push(env
, xpsr
);
1642 v7m_push(env
, env
->regs
[15]);
1643 v7m_push(env
, env
->regs
[14]);
1644 v7m_push(env
, env
->regs
[12]);
1645 v7m_push(env
, env
->regs
[3]);
1646 v7m_push(env
, env
->regs
[2]);
1647 v7m_push(env
, env
->regs
[1]);
1648 v7m_push(env
, env
->regs
[0]);
1649 switch_v7m_sp(env
, 0);
1651 env
->condexec_bits
= 0;
1653 addr
= ldl_phys(env
->v7m
.vecbase
+ env
->v7m
.exception
* 4);
1654 env
->regs
[15] = addr
& 0xfffffffe;
1655 env
->thumb
= addr
& 1;
1658 /* Handle a CPU exception. */
1659 void do_interrupt(CPUARMState
*env
)
1667 do_interrupt_v7m(env
);
1670 /* TODO: Vectored interrupt controller. */
1671 switch (env
->exception_index
) {
1673 new_mode
= ARM_CPU_MODE_UND
;
1682 if (semihosting_enabled
) {
1683 /* Check for semihosting interrupt. */
1685 mask
= arm_lduw_code(env
->regs
[15] - 2, env
->bswap_code
) & 0xff;
1687 mask
= arm_ldl_code(env
->regs
[15] - 4, env
->bswap_code
)
1690 /* Only intercept calls from privileged modes, to provide some
1691 semblance of security. */
1692 if (((mask
== 0x123456 && !env
->thumb
)
1693 || (mask
== 0xab && env
->thumb
))
1694 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
1695 env
->regs
[0] = do_arm_semihosting(env
);
1699 new_mode
= ARM_CPU_MODE_SVC
;
1702 /* The PC already points to the next instruction. */
1706 /* See if this is a semihosting syscall. */
1707 if (env
->thumb
&& semihosting_enabled
) {
1708 mask
= arm_lduw_code(env
->regs
[15], env
->bswap_code
) & 0xff;
1710 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
1712 env
->regs
[0] = do_arm_semihosting(env
);
1716 env
->cp15
.c5_insn
= 2;
1717 /* Fall through to prefetch abort. */
1718 case EXCP_PREFETCH_ABORT
:
1719 new_mode
= ARM_CPU_MODE_ABT
;
1721 mask
= CPSR_A
| CPSR_I
;
1724 case EXCP_DATA_ABORT
:
1725 new_mode
= ARM_CPU_MODE_ABT
;
1727 mask
= CPSR_A
| CPSR_I
;
1731 new_mode
= ARM_CPU_MODE_IRQ
;
1733 /* Disable IRQ and imprecise data aborts. */
1734 mask
= CPSR_A
| CPSR_I
;
1738 new_mode
= ARM_CPU_MODE_FIQ
;
1740 /* Disable FIQ, IRQ and imprecise data aborts. */
1741 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
1745 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
1746 return; /* Never happens. Keep compiler happy. */
1749 if (env
->cp15
.c1_sys
& (1 << 13)) {
1752 switch_mode (env
, new_mode
);
1753 env
->spsr
= cpsr_read(env
);
1754 /* Clear IT bits. */
1755 env
->condexec_bits
= 0;
1756 /* Switch to the new mode, and to the correct instruction set. */
1757 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
1758 env
->uncached_cpsr
|= mask
;
1759 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
1760 * and we should just guard the thumb mode on V4 */
1761 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
1762 env
->thumb
= (env
->cp15
.c1_sys
& (1 << 30)) != 0;
1764 env
->regs
[14] = env
->regs
[15] + offset
;
1765 env
->regs
[15] = addr
;
1766 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
1769 /* Check section/page access permissions.
1770 Returns the page protection flags, or zero if the access is not
1772 static inline int check_ap(CPUARMState
*env
, int ap
, int domain_prot
,
1773 int access_type
, int is_user
)
1777 if (domain_prot
== 3) {
1778 return PAGE_READ
| PAGE_WRITE
;
1781 if (access_type
== 1)
1784 prot_ro
= PAGE_READ
;
1788 if (access_type
== 1)
1790 switch ((env
->cp15
.c1_sys
>> 8) & 3) {
1792 return is_user
? 0 : PAGE_READ
;
1799 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
1804 return PAGE_READ
| PAGE_WRITE
;
1806 return PAGE_READ
| PAGE_WRITE
;
1807 case 4: /* Reserved. */
1810 return is_user
? 0 : prot_ro
;
1814 if (!arm_feature (env
, ARM_FEATURE_V6K
))
1822 static uint32_t get_level1_table_address(CPUARMState
*env
, uint32_t address
)
1826 if (address
& env
->cp15
.c2_mask
)
1827 table
= env
->cp15
.c2_base1
& 0xffffc000;
1829 table
= env
->cp15
.c2_base0
& env
->cp15
.c2_base_mask
;
1831 table
|= (address
>> 18) & 0x3ffc;
1835 static int get_phys_addr_v5(CPUARMState
*env
, uint32_t address
, int access_type
,
1836 int is_user
, uint32_t *phys_ptr
, int *prot
,
1837 target_ulong
*page_size
)
1848 /* Pagetable walk. */
1849 /* Lookup l1 descriptor. */
1850 table
= get_level1_table_address(env
, address
);
1851 desc
= ldl_phys(table
);
1853 domain
= (desc
>> 5) & 0x0f;
1854 domain_prot
= (env
->cp15
.c3
>> (domain
* 2)) & 3;
1856 /* Section translation fault. */
1860 if (domain_prot
== 0 || domain_prot
== 2) {
1862 code
= 9; /* Section domain fault. */
1864 code
= 11; /* Page domain fault. */
1869 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
1870 ap
= (desc
>> 10) & 3;
1872 *page_size
= 1024 * 1024;
1874 /* Lookup l2 entry. */
1876 /* Coarse pagetable. */
1877 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
1879 /* Fine pagetable. */
1880 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
1882 desc
= ldl_phys(table
);
1884 case 0: /* Page translation fault. */
1887 case 1: /* 64k page. */
1888 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
1889 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
1890 *page_size
= 0x10000;
1892 case 2: /* 4k page. */
1893 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1894 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
1895 *page_size
= 0x1000;
1897 case 3: /* 1k page. */
1899 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1900 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1902 /* Page translation fault. */
1907 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
1909 ap
= (desc
>> 4) & 3;
1913 /* Never happens, but compiler isn't smart enough to tell. */
1918 *prot
= check_ap(env
, ap
, domain_prot
, access_type
, is_user
);
1920 /* Access permission fault. */
1924 *phys_ptr
= phys_addr
;
1927 return code
| (domain
<< 4);
1930 static int get_phys_addr_v6(CPUARMState
*env
, uint32_t address
, int access_type
,
1931 int is_user
, uint32_t *phys_ptr
, int *prot
,
1932 target_ulong
*page_size
)
1944 /* Pagetable walk. */
1945 /* Lookup l1 descriptor. */
1946 table
= get_level1_table_address(env
, address
);
1947 desc
= ldl_phys(table
);
1950 /* Section translation fault. */
1954 } else if (type
== 2 && (desc
& (1 << 18))) {
1958 /* Section or page. */
1959 domain
= (desc
>> 5) & 0x0f;
1961 domain_prot
= (env
->cp15
.c3
>> (domain
* 2)) & 3;
1962 if (domain_prot
== 0 || domain_prot
== 2) {
1964 code
= 9; /* Section domain fault. */
1966 code
= 11; /* Page domain fault. */
1970 if (desc
& (1 << 18)) {
1972 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
1973 *page_size
= 0x1000000;
1976 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
1977 *page_size
= 0x100000;
1979 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
1980 xn
= desc
& (1 << 4);
1983 /* Lookup l2 entry. */
1984 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
1985 desc
= ldl_phys(table
);
1986 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
1988 case 0: /* Page translation fault. */
1991 case 1: /* 64k page. */
1992 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
1993 xn
= desc
& (1 << 15);
1994 *page_size
= 0x10000;
1996 case 2: case 3: /* 4k page. */
1997 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1999 *page_size
= 0x1000;
2002 /* Never happens, but compiler isn't smart enough to tell. */
2007 if (domain_prot
== 3) {
2008 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
2010 if (xn
&& access_type
== 2)
2013 /* The simplified model uses AP[0] as an access control bit. */
2014 if ((env
->cp15
.c1_sys
& (1 << 29)) && (ap
& 1) == 0) {
2015 /* Access flag fault. */
2016 code
= (code
== 15) ? 6 : 3;
2019 *prot
= check_ap(env
, ap
, domain_prot
, access_type
, is_user
);
2021 /* Access permission fault. */
2028 *phys_ptr
= phys_addr
;
2031 return code
| (domain
<< 4);
2034 static int get_phys_addr_mpu(CPUARMState
*env
, uint32_t address
, int access_type
,
2035 int is_user
, uint32_t *phys_ptr
, int *prot
)
2041 *phys_ptr
= address
;
2042 for (n
= 7; n
>= 0; n
--) {
2043 base
= env
->cp15
.c6_region
[n
];
2044 if ((base
& 1) == 0)
2046 mask
= 1 << ((base
>> 1) & 0x1f);
2047 /* Keep this shift separate from the above to avoid an
2048 (undefined) << 32. */
2049 mask
= (mask
<< 1) - 1;
2050 if (((base
^ address
) & ~mask
) == 0)
2056 if (access_type
== 2) {
2057 mask
= env
->cp15
.c5_insn
;
2059 mask
= env
->cp15
.c5_data
;
2061 mask
= (mask
>> (n
* 4)) & 0xf;
2068 *prot
= PAGE_READ
| PAGE_WRITE
;
2073 *prot
|= PAGE_WRITE
;
2076 *prot
= PAGE_READ
| PAGE_WRITE
;
2087 /* Bad permission. */
2094 static inline int get_phys_addr(CPUARMState
*env
, uint32_t address
,
2095 int access_type
, int is_user
,
2096 uint32_t *phys_ptr
, int *prot
,
2097 target_ulong
*page_size
)
2099 /* Fast Context Switch Extension. */
2100 if (address
< 0x02000000)
2101 address
+= env
->cp15
.c13_fcse
;
2103 if ((env
->cp15
.c1_sys
& 1) == 0) {
2104 /* MMU/MPU disabled. */
2105 *phys_ptr
= address
;
2106 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
2107 *page_size
= TARGET_PAGE_SIZE
;
2109 } else if (arm_feature(env
, ARM_FEATURE_MPU
)) {
2110 *page_size
= TARGET_PAGE_SIZE
;
2111 return get_phys_addr_mpu(env
, address
, access_type
, is_user
, phys_ptr
,
2113 } else if (env
->cp15
.c1_sys
& (1 << 23)) {
2114 return get_phys_addr_v6(env
, address
, access_type
, is_user
, phys_ptr
,
2117 return get_phys_addr_v5(env
, address
, access_type
, is_user
, phys_ptr
,
2122 int cpu_arm_handle_mmu_fault (CPUARMState
*env
, target_ulong address
,
2123 int access_type
, int mmu_idx
)
2126 target_ulong page_size
;
2130 is_user
= mmu_idx
== MMU_USER_IDX
;
2131 ret
= get_phys_addr(env
, address
, access_type
, is_user
, &phys_addr
, &prot
,
2134 /* Map a single [sub]page. */
2135 phys_addr
&= ~(uint32_t)0x3ff;
2136 address
&= ~(uint32_t)0x3ff;
2137 tlb_set_page (env
, address
, phys_addr
, prot
, mmu_idx
, page_size
);
2141 if (access_type
== 2) {
2142 env
->cp15
.c5_insn
= ret
;
2143 env
->cp15
.c6_insn
= address
;
2144 env
->exception_index
= EXCP_PREFETCH_ABORT
;
2146 env
->cp15
.c5_data
= ret
;
2147 if (access_type
== 1 && arm_feature(env
, ARM_FEATURE_V6
))
2148 env
->cp15
.c5_data
|= (1 << 11);
2149 env
->cp15
.c6_data
= address
;
2150 env
->exception_index
= EXCP_DATA_ABORT
;
2155 target_phys_addr_t
cpu_get_phys_page_debug(CPUARMState
*env
, target_ulong addr
)
2158 target_ulong page_size
;
2162 ret
= get_phys_addr(env
, addr
, 0, 0, &phys_addr
, &prot
, &page_size
);
2170 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
2172 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
2173 env
->regs
[13] = val
;
2175 env
->banked_r13
[bank_number(env
, mode
)] = val
;
2179 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
2181 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
2182 return env
->regs
[13];
2184 return env
->banked_r13
[bank_number(env
, mode
)];
2188 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
2192 return xpsr_read(env
) & 0xf8000000;
2194 return xpsr_read(env
) & 0xf80001ff;
2196 return xpsr_read(env
) & 0xff00fc00;
2198 return xpsr_read(env
) & 0xff00fdff;
2200 return xpsr_read(env
) & 0x000001ff;
2202 return xpsr_read(env
) & 0x0700fc00;
2204 return xpsr_read(env
) & 0x0700edff;
2206 return env
->v7m
.current_sp
? env
->v7m
.other_sp
: env
->regs
[13];
2208 return env
->v7m
.current_sp
? env
->regs
[13] : env
->v7m
.other_sp
;
2209 case 16: /* PRIMASK */
2210 return (env
->uncached_cpsr
& CPSR_I
) != 0;
2211 case 17: /* BASEPRI */
2212 case 18: /* BASEPRI_MAX */
2213 return env
->v7m
.basepri
;
2214 case 19: /* FAULTMASK */
2215 return (env
->uncached_cpsr
& CPSR_F
) != 0;
2216 case 20: /* CONTROL */
2217 return env
->v7m
.control
;
2219 /* ??? For debugging only. */
2220 cpu_abort(env
, "Unimplemented system register read (%d)\n", reg
);
2225 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
2229 xpsr_write(env
, val
, 0xf8000000);
2232 xpsr_write(env
, val
, 0xf8000000);
2235 xpsr_write(env
, val
, 0xfe00fc00);
2238 xpsr_write(env
, val
, 0xfe00fc00);
2241 /* IPSR bits are readonly. */
2244 xpsr_write(env
, val
, 0x0600fc00);
2247 xpsr_write(env
, val
, 0x0600fc00);
2250 if (env
->v7m
.current_sp
)
2251 env
->v7m
.other_sp
= val
;
2253 env
->regs
[13] = val
;
2256 if (env
->v7m
.current_sp
)
2257 env
->regs
[13] = val
;
2259 env
->v7m
.other_sp
= val
;
2261 case 16: /* PRIMASK */
2263 env
->uncached_cpsr
|= CPSR_I
;
2265 env
->uncached_cpsr
&= ~CPSR_I
;
2267 case 17: /* BASEPRI */
2268 env
->v7m
.basepri
= val
& 0xff;
2270 case 18: /* BASEPRI_MAX */
2272 if (val
!= 0 && (val
< env
->v7m
.basepri
|| env
->v7m
.basepri
== 0))
2273 env
->v7m
.basepri
= val
;
2275 case 19: /* FAULTMASK */
2277 env
->uncached_cpsr
|= CPSR_F
;
2279 env
->uncached_cpsr
&= ~CPSR_F
;
2281 case 20: /* CONTROL */
2282 env
->v7m
.control
= val
& 3;
2283 switch_v7m_sp(env
, (val
& 2) != 0);
2286 /* ??? For debugging only. */
2287 cpu_abort(env
, "Unimplemented system register write (%d)\n", reg
);
2294 /* Note that signed overflow is undefined in C. The following routines are
2295 careful to use unsigned types where modulo arithmetic is required.
2296 Failure to do so _will_ break on newer gcc. */
2298 /* Signed saturating arithmetic. */
2300 /* Perform 16-bit signed saturating addition. */
2301 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
2306 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
2315 /* Perform 8-bit signed saturating addition. */
2316 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
2321 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
2330 /* Perform 16-bit signed saturating subtraction. */
2331 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
2336 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
2345 /* Perform 8-bit signed saturating subtraction. */
2346 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
2351 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
2360 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2361 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2362 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2363 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2366 #include "op_addsub.h"
2368 /* Unsigned saturating arithmetic. */
2369 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
2378 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
2386 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
2395 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
2403 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2404 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2405 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2406 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2409 #include "op_addsub.h"
2411 /* Signed modulo arithmetic. */
2412 #define SARITH16(a, b, n, op) do { \
2414 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
2415 RESULT(sum, n, 16); \
2417 ge |= 3 << (n * 2); \
2420 #define SARITH8(a, b, n, op) do { \
2422 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
2423 RESULT(sum, n, 8); \
2429 #define ADD16(a, b, n) SARITH16(a, b, n, +)
2430 #define SUB16(a, b, n) SARITH16(a, b, n, -)
2431 #define ADD8(a, b, n) SARITH8(a, b, n, +)
2432 #define SUB8(a, b, n) SARITH8(a, b, n, -)
2436 #include "op_addsub.h"
2438 /* Unsigned modulo arithmetic. */
2439 #define ADD16(a, b, n) do { \
2441 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2442 RESULT(sum, n, 16); \
2443 if ((sum >> 16) == 1) \
2444 ge |= 3 << (n * 2); \
2447 #define ADD8(a, b, n) do { \
2449 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2450 RESULT(sum, n, 8); \
2451 if ((sum >> 8) == 1) \
2455 #define SUB16(a, b, n) do { \
2457 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2458 RESULT(sum, n, 16); \
2459 if ((sum >> 16) == 0) \
2460 ge |= 3 << (n * 2); \
2463 #define SUB8(a, b, n) do { \
2465 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2466 RESULT(sum, n, 8); \
2467 if ((sum >> 8) == 0) \
2474 #include "op_addsub.h"
2476 /* Halved signed arithmetic. */
2477 #define ADD16(a, b, n) \
2478 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2479 #define SUB16(a, b, n) \
2480 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2481 #define ADD8(a, b, n) \
2482 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2483 #define SUB8(a, b, n) \
2484 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2487 #include "op_addsub.h"
2489 /* Halved unsigned arithmetic. */
2490 #define ADD16(a, b, n) \
2491 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2492 #define SUB16(a, b, n) \
2493 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2494 #define ADD8(a, b, n) \
2495 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2496 #define SUB8(a, b, n) \
2497 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2500 #include "op_addsub.h"
2502 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
2510 /* Unsigned sum of absolute byte differences. */
2511 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
2514 sum
= do_usad(a
, b
);
2515 sum
+= do_usad(a
>> 8, b
>> 8);
2516 sum
+= do_usad(a
>> 16, b
>>16);
2517 sum
+= do_usad(a
>> 24, b
>> 24);
2521 /* For ARMv6 SEL instruction. */
2522 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
2535 return (a
& mask
) | (b
& ~mask
);
2538 uint32_t HELPER(logicq_cc
)(uint64_t val
)
2540 return (val
>> 32) | (val
!= 0);
2543 /* VFP support. We follow the convention used for VFP instrunctions:
2544 Single precition routines have a "s" suffix, double precision a
2547 /* Convert host exception flags to vfp form. */
2548 static inline int vfp_exceptbits_from_host(int host_bits
)
2550 int target_bits
= 0;
2552 if (host_bits
& float_flag_invalid
)
2554 if (host_bits
& float_flag_divbyzero
)
2556 if (host_bits
& float_flag_overflow
)
2558 if (host_bits
& (float_flag_underflow
| float_flag_output_denormal
))
2560 if (host_bits
& float_flag_inexact
)
2561 target_bits
|= 0x10;
2562 if (host_bits
& float_flag_input_denormal
)
2563 target_bits
|= 0x80;
2567 uint32_t HELPER(vfp_get_fpscr
)(CPUARMState
*env
)
2572 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
2573 | (env
->vfp
.vec_len
<< 16)
2574 | (env
->vfp
.vec_stride
<< 20);
2575 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
2576 i
|= get_float_exception_flags(&env
->vfp
.standard_fp_status
);
2577 fpscr
|= vfp_exceptbits_from_host(i
);
2581 uint32_t vfp_get_fpscr(CPUARMState
*env
)
2583 return HELPER(vfp_get_fpscr
)(env
);
2586 /* Convert vfp exception flags to target form. */
2587 static inline int vfp_exceptbits_to_host(int target_bits
)
2591 if (target_bits
& 1)
2592 host_bits
|= float_flag_invalid
;
2593 if (target_bits
& 2)
2594 host_bits
|= float_flag_divbyzero
;
2595 if (target_bits
& 4)
2596 host_bits
|= float_flag_overflow
;
2597 if (target_bits
& 8)
2598 host_bits
|= float_flag_underflow
;
2599 if (target_bits
& 0x10)
2600 host_bits
|= float_flag_inexact
;
2601 if (target_bits
& 0x80)
2602 host_bits
|= float_flag_input_denormal
;
2606 void HELPER(vfp_set_fpscr
)(CPUARMState
*env
, uint32_t val
)
2611 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
2612 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
2613 env
->vfp
.vec_len
= (val
>> 16) & 7;
2614 env
->vfp
.vec_stride
= (val
>> 20) & 3;
2617 if (changed
& (3 << 22)) {
2618 i
= (val
>> 22) & 3;
2621 i
= float_round_nearest_even
;
2627 i
= float_round_down
;
2630 i
= float_round_to_zero
;
2633 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
2635 if (changed
& (1 << 24)) {
2636 set_flush_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
2637 set_flush_inputs_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
2639 if (changed
& (1 << 25))
2640 set_default_nan_mode((val
& (1 << 25)) != 0, &env
->vfp
.fp_status
);
2642 i
= vfp_exceptbits_to_host(val
);
2643 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
2644 set_float_exception_flags(0, &env
->vfp
.standard_fp_status
);
2647 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
)
2649 HELPER(vfp_set_fpscr
)(env
, val
);
2652 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2654 #define VFP_BINOP(name) \
2655 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
2657 float_status *fpst = fpstp; \
2658 return float32_ ## name(a, b, fpst); \
2660 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
2662 float_status *fpst = fpstp; \
2663 return float64_ ## name(a, b, fpst); \
2671 float32
VFP_HELPER(neg
, s
)(float32 a
)
2673 return float32_chs(a
);
2676 float64
VFP_HELPER(neg
, d
)(float64 a
)
2678 return float64_chs(a
);
2681 float32
VFP_HELPER(abs
, s
)(float32 a
)
2683 return float32_abs(a
);
2686 float64
VFP_HELPER(abs
, d
)(float64 a
)
2688 return float64_abs(a
);
2691 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUARMState
*env
)
2693 return float32_sqrt(a
, &env
->vfp
.fp_status
);
2696 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUARMState
*env
)
2698 return float64_sqrt(a
, &env
->vfp
.fp_status
);
2701 /* XXX: check quiet/signaling case */
2702 #define DO_VFP_cmp(p, type) \
2703 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
2706 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2707 case 0: flags = 0x6; break; \
2708 case -1: flags = 0x8; break; \
2709 case 1: flags = 0x2; break; \
2710 default: case 2: flags = 0x3; break; \
2712 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2713 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2715 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
2718 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2719 case 0: flags = 0x6; break; \
2720 case -1: flags = 0x8; break; \
2721 case 1: flags = 0x2; break; \
2722 default: case 2: flags = 0x3; break; \
2724 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2725 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2727 DO_VFP_cmp(s
, float32
)
2728 DO_VFP_cmp(d
, float64
)
2731 /* Integer to float and float to integer conversions */
2733 #define CONV_ITOF(name, fsz, sign) \
2734 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
2736 float_status *fpst = fpstp; \
2737 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
2740 #define CONV_FTOI(name, fsz, sign, round) \
2741 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
2743 float_status *fpst = fpstp; \
2744 if (float##fsz##_is_any_nan(x)) { \
2745 float_raise(float_flag_invalid, fpst); \
2748 return float##fsz##_to_##sign##int32##round(x, fpst); \
2751 #define FLOAT_CONVS(name, p, fsz, sign) \
2752 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
2753 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
2754 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
2756 FLOAT_CONVS(si
, s
, 32, )
2757 FLOAT_CONVS(si
, d
, 64, )
2758 FLOAT_CONVS(ui
, s
, 32, u
)
2759 FLOAT_CONVS(ui
, d
, 64, u
)
2765 /* floating point conversion */
2766 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUARMState
*env
)
2768 float64 r
= float32_to_float64(x
, &env
->vfp
.fp_status
);
2769 /* ARM requires that S<->D conversion of any kind of NaN generates
2770 * a quiet NaN by forcing the most significant frac bit to 1.
2772 return float64_maybe_silence_nan(r
);
2775 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUARMState
*env
)
2777 float32 r
= float64_to_float32(x
, &env
->vfp
.fp_status
);
2778 /* ARM requires that S<->D conversion of any kind of NaN generates
2779 * a quiet NaN by forcing the most significant frac bit to 1.
2781 return float32_maybe_silence_nan(r
);
2784 /* VFP3 fixed point conversion. */
2785 #define VFP_CONV_FIX(name, p, fsz, itype, sign) \
2786 float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \
2789 float_status *fpst = fpstp; \
2791 tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
2792 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
2794 uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
2797 float_status *fpst = fpstp; \
2799 if (float##fsz##_is_any_nan(x)) { \
2800 float_raise(float_flag_invalid, fpst); \
2803 tmp = float##fsz##_scalbn(x, shift, fpst); \
2804 return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
2807 VFP_CONV_FIX(sh
, d
, 64, int16
, )
2808 VFP_CONV_FIX(sl
, d
, 64, int32
, )
2809 VFP_CONV_FIX(uh
, d
, 64, uint16
, u
)
2810 VFP_CONV_FIX(ul
, d
, 64, uint32
, u
)
2811 VFP_CONV_FIX(sh
, s
, 32, int16
, )
2812 VFP_CONV_FIX(sl
, s
, 32, int32
, )
2813 VFP_CONV_FIX(uh
, s
, 32, uint16
, u
)
2814 VFP_CONV_FIX(ul
, s
, 32, uint32
, u
)
2817 /* Half precision conversions. */
2818 static float32
do_fcvt_f16_to_f32(uint32_t a
, CPUARMState
*env
, float_status
*s
)
2820 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
2821 float32 r
= float16_to_float32(make_float16(a
), ieee
, s
);
2823 return float32_maybe_silence_nan(r
);
2828 static uint32_t do_fcvt_f32_to_f16(float32 a
, CPUARMState
*env
, float_status
*s
)
2830 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
2831 float16 r
= float32_to_float16(a
, ieee
, s
);
2833 r
= float16_maybe_silence_nan(r
);
2835 return float16_val(r
);
2838 float32
HELPER(neon_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
2840 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.standard_fp_status
);
2843 uint32_t HELPER(neon_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
2845 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.standard_fp_status
);
2848 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
2850 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.fp_status
);
2853 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
2855 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.fp_status
);
2858 #define float32_two make_float32(0x40000000)
2859 #define float32_three make_float32(0x40400000)
2860 #define float32_one_point_five make_float32(0x3fc00000)
2862 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
2864 float_status
*s
= &env
->vfp
.standard_fp_status
;
2865 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
2866 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
2867 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
2868 float_raise(float_flag_input_denormal
, s
);
2872 return float32_sub(float32_two
, float32_mul(a
, b
, s
), s
);
2875 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
2877 float_status
*s
= &env
->vfp
.standard_fp_status
;
2879 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
2880 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
2881 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
2882 float_raise(float_flag_input_denormal
, s
);
2884 return float32_one_point_five
;
2886 product
= float32_mul(a
, b
, s
);
2887 return float32_div(float32_sub(float32_three
, product
, s
), float32_two
, s
);
2892 /* Constants 256 and 512 are used in some helpers; we avoid relying on
2893 * int->float conversions at run-time. */
2894 #define float64_256 make_float64(0x4070000000000000LL)
2895 #define float64_512 make_float64(0x4080000000000000LL)
2897 /* The algorithm that must be used to calculate the estimate
2898 * is specified by the ARM ARM.
2900 static float64
recip_estimate(float64 a
, CPUARMState
*env
)
2902 /* These calculations mustn't set any fp exception flags,
2903 * so we use a local copy of the fp_status.
2905 float_status dummy_status
= env
->vfp
.standard_fp_status
;
2906 float_status
*s
= &dummy_status
;
2907 /* q = (int)(a * 512.0) */
2908 float64 q
= float64_mul(float64_512
, a
, s
);
2909 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
2911 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
2912 q
= int64_to_float64(q_int
, s
);
2913 q
= float64_add(q
, float64_half
, s
);
2914 q
= float64_div(q
, float64_512
, s
);
2915 q
= float64_div(float64_one
, q
, s
);
2917 /* s = (int)(256.0 * r + 0.5) */
2918 q
= float64_mul(q
, float64_256
, s
);
2919 q
= float64_add(q
, float64_half
, s
);
2920 q_int
= float64_to_int64_round_to_zero(q
, s
);
2922 /* return (double)s / 256.0 */
2923 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
2926 float32
HELPER(recpe_f32
)(float32 a
, CPUARMState
*env
)
2928 float_status
*s
= &env
->vfp
.standard_fp_status
;
2930 uint32_t val32
= float32_val(a
);
2933 int a_exp
= (val32
& 0x7f800000) >> 23;
2934 int sign
= val32
& 0x80000000;
2936 if (float32_is_any_nan(a
)) {
2937 if (float32_is_signaling_nan(a
)) {
2938 float_raise(float_flag_invalid
, s
);
2940 return float32_default_nan
;
2941 } else if (float32_is_infinity(a
)) {
2942 return float32_set_sign(float32_zero
, float32_is_neg(a
));
2943 } else if (float32_is_zero_or_denormal(a
)) {
2944 if (!float32_is_zero(a
)) {
2945 float_raise(float_flag_input_denormal
, s
);
2947 float_raise(float_flag_divbyzero
, s
);
2948 return float32_set_sign(float32_infinity
, float32_is_neg(a
));
2949 } else if (a_exp
>= 253) {
2950 float_raise(float_flag_underflow
, s
);
2951 return float32_set_sign(float32_zero
, float32_is_neg(a
));
2954 f64
= make_float64((0x3feULL
<< 52)
2955 | ((int64_t)(val32
& 0x7fffff) << 29));
2957 result_exp
= 253 - a_exp
;
2959 f64
= recip_estimate(f64
, env
);
2962 | ((result_exp
& 0xff) << 23)
2963 | ((float64_val(f64
) >> 29) & 0x7fffff);
2964 return make_float32(val32
);
2967 /* The algorithm that must be used to calculate the estimate
2968 * is specified by the ARM ARM.
2970 static float64
recip_sqrt_estimate(float64 a
, CPUARMState
*env
)
2972 /* These calculations mustn't set any fp exception flags,
2973 * so we use a local copy of the fp_status.
2975 float_status dummy_status
= env
->vfp
.standard_fp_status
;
2976 float_status
*s
= &dummy_status
;
2980 if (float64_lt(a
, float64_half
, s
)) {
2981 /* range 0.25 <= a < 0.5 */
2983 /* a in units of 1/512 rounded down */
2984 /* q0 = (int)(a * 512.0); */
2985 q
= float64_mul(float64_512
, a
, s
);
2986 q_int
= float64_to_int64_round_to_zero(q
, s
);
2988 /* reciprocal root r */
2989 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
2990 q
= int64_to_float64(q_int
, s
);
2991 q
= float64_add(q
, float64_half
, s
);
2992 q
= float64_div(q
, float64_512
, s
);
2993 q
= float64_sqrt(q
, s
);
2994 q
= float64_div(float64_one
, q
, s
);
2996 /* range 0.5 <= a < 1.0 */
2998 /* a in units of 1/256 rounded down */
2999 /* q1 = (int)(a * 256.0); */
3000 q
= float64_mul(float64_256
, a
, s
);
3001 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
3003 /* reciprocal root r */
3004 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
3005 q
= int64_to_float64(q_int
, s
);
3006 q
= float64_add(q
, float64_half
, s
);
3007 q
= float64_div(q
, float64_256
, s
);
3008 q
= float64_sqrt(q
, s
);
3009 q
= float64_div(float64_one
, q
, s
);
3011 /* r in units of 1/256 rounded to nearest */
3012 /* s = (int)(256.0 * r + 0.5); */
3014 q
= float64_mul(q
, float64_256
,s
);
3015 q
= float64_add(q
, float64_half
, s
);
3016 q_int
= float64_to_int64_round_to_zero(q
, s
);
3018 /* return (double)s / 256.0;*/
3019 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
3022 float32
HELPER(rsqrte_f32
)(float32 a
, CPUARMState
*env
)
3024 float_status
*s
= &env
->vfp
.standard_fp_status
;
3030 val
= float32_val(a
);
3032 if (float32_is_any_nan(a
)) {
3033 if (float32_is_signaling_nan(a
)) {
3034 float_raise(float_flag_invalid
, s
);
3036 return float32_default_nan
;
3037 } else if (float32_is_zero_or_denormal(a
)) {
3038 if (!float32_is_zero(a
)) {
3039 float_raise(float_flag_input_denormal
, s
);
3041 float_raise(float_flag_divbyzero
, s
);
3042 return float32_set_sign(float32_infinity
, float32_is_neg(a
));
3043 } else if (float32_is_neg(a
)) {
3044 float_raise(float_flag_invalid
, s
);
3045 return float32_default_nan
;
3046 } else if (float32_is_infinity(a
)) {
3047 return float32_zero
;
3050 /* Normalize to a double-precision value between 0.25 and 1.0,
3051 * preserving the parity of the exponent. */
3052 if ((val
& 0x800000) == 0) {
3053 f64
= make_float64(((uint64_t)(val
& 0x80000000) << 32)
3055 | ((uint64_t)(val
& 0x7fffff) << 29));
3057 f64
= make_float64(((uint64_t)(val
& 0x80000000) << 32)
3059 | ((uint64_t)(val
& 0x7fffff) << 29));
3062 result_exp
= (380 - ((val
& 0x7f800000) >> 23)) / 2;
3064 f64
= recip_sqrt_estimate(f64
, env
);
3066 val64
= float64_val(f64
);
3068 val
= ((result_exp
& 0xff) << 23)
3069 | ((val64
>> 29) & 0x7fffff);
3070 return make_float32(val
);
3073 uint32_t HELPER(recpe_u32
)(uint32_t a
, CPUARMState
*env
)
3077 if ((a
& 0x80000000) == 0) {
3081 f64
= make_float64((0x3feULL
<< 52)
3082 | ((int64_t)(a
& 0x7fffffff) << 21));
3084 f64
= recip_estimate (f64
, env
);
3086 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
3089 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, CPUARMState
*env
)
3093 if ((a
& 0xc0000000) == 0) {
3097 if (a
& 0x80000000) {
3098 f64
= make_float64((0x3feULL
<< 52)
3099 | ((uint64_t)(a
& 0x7fffffff) << 21));
3100 } else { /* bits 31-30 == '01' */
3101 f64
= make_float64((0x3fdULL
<< 52)
3102 | ((uint64_t)(a
& 0x3fffffff) << 22));
3105 f64
= recip_sqrt_estimate(f64
, env
);
3107 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
3110 /* VFPv4 fused multiply-accumulate */
3111 float32
VFP_HELPER(muladd
, s
)(float32 a
, float32 b
, float32 c
, void *fpstp
)
3113 float_status
*fpst
= fpstp
;
3114 return float32_muladd(a
, b
, c
, 0, fpst
);
3117 float64
VFP_HELPER(muladd
, d
)(float64 a
, float64 b
, float64 c
, void *fpstp
)
3119 float_status
*fpst
= fpstp
;
3120 return float64_muladd(a
, b
, c
, 0, fpst
);