4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qapi/error.h"
22 #include "qemu/cutils.h"
24 #include "exec/exec-all.h"
25 #include "exec/target_page.h"
27 #include "hw/qdev-core.h"
28 #include "hw/qdev-properties.h"
29 #if !defined(CONFIG_USER_ONLY)
30 #include "hw/boards.h"
31 #include "hw/xen/xen.h"
33 #include "sysemu/kvm.h"
34 #include "sysemu/sysemu.h"
35 #include "qemu/timer.h"
36 #include "qemu/config-file.h"
37 #include "qemu/error-report.h"
38 #if defined(CONFIG_USER_ONLY)
40 #else /* !CONFIG_USER_ONLY */
42 #include "exec/memory.h"
43 #include "exec/ioport.h"
44 #include "sysemu/dma.h"
45 #include "sysemu/numa.h"
46 #include "sysemu/hw_accel.h"
47 #include "exec/address-spaces.h"
48 #include "sysemu/xen-mapcache.h"
49 #include "trace-root.h"
51 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
52 #include <linux/falloc.h>
56 #include "qemu/rcu_queue.h"
57 #include "qemu/main-loop.h"
58 #include "translate-all.h"
59 #include "sysemu/replay.h"
61 #include "exec/memory-internal.h"
62 #include "exec/ram_addr.h"
65 #include "migration/vmstate.h"
67 #include "qemu/range.h"
69 #include "qemu/mmap-alloc.h"
72 #include "monitor/monitor.h"
74 //#define DEBUG_SUBPAGE
76 #if !defined(CONFIG_USER_ONLY)
77 /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes
78 * are protected by the ramlist lock.
80 RAMList ram_list
= { .blocks
= QLIST_HEAD_INITIALIZER(ram_list
.blocks
) };
82 static MemoryRegion
*system_memory
;
83 static MemoryRegion
*system_io
;
85 AddressSpace address_space_io
;
86 AddressSpace address_space_memory
;
88 MemoryRegion io_mem_rom
, io_mem_notdirty
;
89 static MemoryRegion io_mem_unassigned
;
91 /* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */
92 #define RAM_PREALLOC (1 << 0)
94 /* RAM is mmap-ed with MAP_SHARED */
95 #define RAM_SHARED (1 << 1)
97 /* Only a portion of RAM (used_length) is actually used, and migrated.
98 * This used_length size can change across reboots.
100 #define RAM_RESIZEABLE (1 << 2)
104 #ifdef TARGET_PAGE_BITS_VARY
105 int target_page_bits
;
106 bool target_page_bits_decided
;
109 struct CPUTailQ cpus
= QTAILQ_HEAD_INITIALIZER(cpus
);
110 /* current CPU in the current thread. It is only valid inside
112 __thread CPUState
*current_cpu
;
113 /* 0 = Do not count executed instructions.
114 1 = Precise instruction counting.
115 2 = Adaptive rate instruction counting. */
118 uintptr_t qemu_host_page_size
;
119 intptr_t qemu_host_page_mask
;
121 bool set_preferred_target_page_bits(int bits
)
123 /* The target page size is the lowest common denominator for all
124 * the CPUs in the system, so we can only make it smaller, never
125 * larger. And we can't make it smaller once we've committed to
128 #ifdef TARGET_PAGE_BITS_VARY
129 assert(bits
>= TARGET_PAGE_BITS_MIN
);
130 if (target_page_bits
== 0 || target_page_bits
> bits
) {
131 if (target_page_bits_decided
) {
134 target_page_bits
= bits
;
140 #if !defined(CONFIG_USER_ONLY)
142 static void finalize_target_page_bits(void)
144 #ifdef TARGET_PAGE_BITS_VARY
145 if (target_page_bits
== 0) {
146 target_page_bits
= TARGET_PAGE_BITS_MIN
;
148 target_page_bits_decided
= true;
152 typedef struct PhysPageEntry PhysPageEntry
;
154 struct PhysPageEntry
{
155 /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */
157 /* index into phys_sections (!skip) or phys_map_nodes (skip) */
161 #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6)
163 /* Size of the L2 (and L3, etc) page tables. */
164 #define ADDR_SPACE_BITS 64
167 #define P_L2_SIZE (1 << P_L2_BITS)
169 #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1)
171 typedef PhysPageEntry Node
[P_L2_SIZE
];
173 typedef struct PhysPageMap
{
176 unsigned sections_nb
;
177 unsigned sections_nb_alloc
;
179 unsigned nodes_nb_alloc
;
181 MemoryRegionSection
*sections
;
184 struct AddressSpaceDispatch
{
185 MemoryRegionSection
*mru_section
;
186 /* This is a multi-level map on the physical address space.
187 * The bottom level has pointers to MemoryRegionSections.
189 PhysPageEntry phys_map
;
193 #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
194 typedef struct subpage_t
{
198 uint16_t sub_section
[];
201 #define PHYS_SECTION_UNASSIGNED 0
202 #define PHYS_SECTION_NOTDIRTY 1
203 #define PHYS_SECTION_ROM 2
204 #define PHYS_SECTION_WATCH 3
206 static void io_mem_init(void);
207 static void memory_map_init(void);
208 static void tcg_commit(MemoryListener
*listener
);
210 static MemoryRegion io_mem_watch
;
213 * CPUAddressSpace: all the information a CPU needs about an AddressSpace
214 * @cpu: the CPU whose AddressSpace this is
215 * @as: the AddressSpace itself
216 * @memory_dispatch: its dispatch pointer (cached, RCU protected)
217 * @tcg_as_listener: listener for tracking changes to the AddressSpace
219 struct CPUAddressSpace
{
222 struct AddressSpaceDispatch
*memory_dispatch
;
223 MemoryListener tcg_as_listener
;
226 struct DirtyBitmapSnapshot
{
229 unsigned long dirty
[];
234 #if !defined(CONFIG_USER_ONLY)
236 static void phys_map_node_reserve(PhysPageMap
*map
, unsigned nodes
)
238 static unsigned alloc_hint
= 16;
239 if (map
->nodes_nb
+ nodes
> map
->nodes_nb_alloc
) {
240 map
->nodes_nb_alloc
= MAX(map
->nodes_nb_alloc
, alloc_hint
);
241 map
->nodes_nb_alloc
= MAX(map
->nodes_nb_alloc
, map
->nodes_nb
+ nodes
);
242 map
->nodes
= g_renew(Node
, map
->nodes
, map
->nodes_nb_alloc
);
243 alloc_hint
= map
->nodes_nb_alloc
;
247 static uint32_t phys_map_node_alloc(PhysPageMap
*map
, bool leaf
)
254 ret
= map
->nodes_nb
++;
256 assert(ret
!= PHYS_MAP_NODE_NIL
);
257 assert(ret
!= map
->nodes_nb_alloc
);
259 e
.skip
= leaf
? 0 : 1;
260 e
.ptr
= leaf
? PHYS_SECTION_UNASSIGNED
: PHYS_MAP_NODE_NIL
;
261 for (i
= 0; i
< P_L2_SIZE
; ++i
) {
262 memcpy(&p
[i
], &e
, sizeof(e
));
267 static void phys_page_set_level(PhysPageMap
*map
, PhysPageEntry
*lp
,
268 hwaddr
*index
, hwaddr
*nb
, uint16_t leaf
,
272 hwaddr step
= (hwaddr
)1 << (level
* P_L2_BITS
);
274 if (lp
->skip
&& lp
->ptr
== PHYS_MAP_NODE_NIL
) {
275 lp
->ptr
= phys_map_node_alloc(map
, level
== 0);
277 p
= map
->nodes
[lp
->ptr
];
278 lp
= &p
[(*index
>> (level
* P_L2_BITS
)) & (P_L2_SIZE
- 1)];
280 while (*nb
&& lp
< &p
[P_L2_SIZE
]) {
281 if ((*index
& (step
- 1)) == 0 && *nb
>= step
) {
287 phys_page_set_level(map
, lp
, index
, nb
, leaf
, level
- 1);
293 static void phys_page_set(AddressSpaceDispatch
*d
,
294 hwaddr index
, hwaddr nb
,
297 /* Wildly overreserve - it doesn't matter much. */
298 phys_map_node_reserve(&d
->map
, 3 * P_L2_LEVELS
);
300 phys_page_set_level(&d
->map
, &d
->phys_map
, &index
, &nb
, leaf
, P_L2_LEVELS
- 1);
303 /* Compact a non leaf page entry. Simply detect that the entry has a single child,
304 * and update our entry so we can skip it and go directly to the destination.
306 static void phys_page_compact(PhysPageEntry
*lp
, Node
*nodes
)
308 unsigned valid_ptr
= P_L2_SIZE
;
313 if (lp
->ptr
== PHYS_MAP_NODE_NIL
) {
318 for (i
= 0; i
< P_L2_SIZE
; i
++) {
319 if (p
[i
].ptr
== PHYS_MAP_NODE_NIL
) {
326 phys_page_compact(&p
[i
], nodes
);
330 /* We can only compress if there's only one child. */
335 assert(valid_ptr
< P_L2_SIZE
);
337 /* Don't compress if it won't fit in the # of bits we have. */
338 if (lp
->skip
+ p
[valid_ptr
].skip
>= (1 << 3)) {
342 lp
->ptr
= p
[valid_ptr
].ptr
;
343 if (!p
[valid_ptr
].skip
) {
344 /* If our only child is a leaf, make this a leaf. */
345 /* By design, we should have made this node a leaf to begin with so we
346 * should never reach here.
347 * But since it's so simple to handle this, let's do it just in case we
352 lp
->skip
+= p
[valid_ptr
].skip
;
356 void address_space_dispatch_compact(AddressSpaceDispatch
*d
)
358 if (d
->phys_map
.skip
) {
359 phys_page_compact(&d
->phys_map
, d
->map
.nodes
);
363 static inline bool section_covers_addr(const MemoryRegionSection
*section
,
366 /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means
367 * the section must cover the entire address space.
369 return int128_gethi(section
->size
) ||
370 range_covers_byte(section
->offset_within_address_space
,
371 int128_getlo(section
->size
), addr
);
374 static MemoryRegionSection
*phys_page_find(AddressSpaceDispatch
*d
, hwaddr addr
)
376 PhysPageEntry lp
= d
->phys_map
, *p
;
377 Node
*nodes
= d
->map
.nodes
;
378 MemoryRegionSection
*sections
= d
->map
.sections
;
379 hwaddr index
= addr
>> TARGET_PAGE_BITS
;
382 for (i
= P_L2_LEVELS
; lp
.skip
&& (i
-= lp
.skip
) >= 0;) {
383 if (lp
.ptr
== PHYS_MAP_NODE_NIL
) {
384 return §ions
[PHYS_SECTION_UNASSIGNED
];
387 lp
= p
[(index
>> (i
* P_L2_BITS
)) & (P_L2_SIZE
- 1)];
390 if (section_covers_addr(§ions
[lp
.ptr
], addr
)) {
391 return §ions
[lp
.ptr
];
393 return §ions
[PHYS_SECTION_UNASSIGNED
];
397 bool memory_region_is_unassigned(MemoryRegion
*mr
)
399 return mr
!= &io_mem_rom
&& mr
!= &io_mem_notdirty
&& !mr
->rom_device
400 && mr
!= &io_mem_watch
;
403 /* Called from RCU critical section */
404 static MemoryRegionSection
*address_space_lookup_region(AddressSpaceDispatch
*d
,
406 bool resolve_subpage
)
408 MemoryRegionSection
*section
= atomic_read(&d
->mru_section
);
411 if (!section
|| section
== &d
->map
.sections
[PHYS_SECTION_UNASSIGNED
] ||
412 !section_covers_addr(section
, addr
)) {
413 section
= phys_page_find(d
, addr
);
414 atomic_set(&d
->mru_section
, section
);
416 if (resolve_subpage
&& section
->mr
->subpage
) {
417 subpage
= container_of(section
->mr
, subpage_t
, iomem
);
418 section
= &d
->map
.sections
[subpage
->sub_section
[SUBPAGE_IDX(addr
)]];
423 /* Called from RCU critical section */
424 static MemoryRegionSection
*
425 address_space_translate_internal(AddressSpaceDispatch
*d
, hwaddr addr
, hwaddr
*xlat
,
426 hwaddr
*plen
, bool resolve_subpage
)
428 MemoryRegionSection
*section
;
432 section
= address_space_lookup_region(d
, addr
, resolve_subpage
);
433 /* Compute offset within MemoryRegionSection */
434 addr
-= section
->offset_within_address_space
;
436 /* Compute offset within MemoryRegion */
437 *xlat
= addr
+ section
->offset_within_region
;
441 /* MMIO registers can be expected to perform full-width accesses based only
442 * on their address, without considering adjacent registers that could
443 * decode to completely different MemoryRegions. When such registers
444 * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO
445 * regions overlap wildly. For this reason we cannot clamp the accesses
448 * If the length is small (as is the case for address_space_ldl/stl),
449 * everything works fine. If the incoming length is large, however,
450 * the caller really has to do the clamping through memory_access_size.
452 if (memory_region_is_ram(mr
)) {
453 diff
= int128_sub(section
->size
, int128_make64(addr
));
454 *plen
= int128_get64(int128_min(diff
, int128_make64(*plen
)));
460 * flatview_do_translate - translate an address in FlatView
462 * @fv: the flat view that we want to translate on
463 * @addr: the address to be translated in above address space
464 * @xlat: the translated address offset within memory region. It
466 * @plen_out: valid read/write length of the translated address. It
467 * can be @NULL when we don't care about it.
468 * @page_mask_out: page mask for the translated address. This
469 * should only be meaningful for IOMMU translated
470 * addresses, since there may be huge pages that this bit
471 * would tell. It can be @NULL if we don't care about it.
472 * @is_write: whether the translation operation is for write
473 * @is_mmio: whether this can be MMIO, set true if it can
475 * This function is called from RCU critical section
477 static MemoryRegionSection
flatview_do_translate(FlatView
*fv
,
481 hwaddr
*page_mask_out
,
484 AddressSpace
**target_as
)
487 MemoryRegionSection
*section
;
488 IOMMUMemoryRegion
*iommu_mr
;
489 IOMMUMemoryRegionClass
*imrc
;
490 hwaddr page_mask
= (hwaddr
)(-1);
491 hwaddr plen
= (hwaddr
)(-1);
498 section
= address_space_translate_internal(
499 flatview_to_dispatch(fv
), addr
, &addr
,
502 iommu_mr
= memory_region_get_iommu(section
->mr
);
506 imrc
= memory_region_get_iommu_class_nocheck(iommu_mr
);
508 iotlb
= imrc
->translate(iommu_mr
, addr
, is_write
?
509 IOMMU_WO
: IOMMU_RO
);
510 addr
= ((iotlb
.translated_addr
& ~iotlb
.addr_mask
)
511 | (addr
& iotlb
.addr_mask
));
512 page_mask
&= iotlb
.addr_mask
;
513 plen
= MIN(plen
, (addr
| iotlb
.addr_mask
) - addr
+ 1);
514 if (!(iotlb
.perm
& (1 << is_write
))) {
518 fv
= address_space_to_flatview(iotlb
.target_as
);
519 *target_as
= iotlb
.target_as
;
524 if (page_mask
== (hwaddr
)(-1)) {
525 /* Not behind an IOMMU, use default page size. */
526 page_mask
= ~TARGET_PAGE_MASK
;
530 *page_mask_out
= page_mask
;
540 return (MemoryRegionSection
) { .mr
= &io_mem_unassigned
};
543 /* Called from RCU critical section */
544 IOMMUTLBEntry
address_space_get_iotlb_entry(AddressSpace
*as
, hwaddr addr
,
547 MemoryRegionSection section
;
548 hwaddr xlat
, page_mask
;
551 * This can never be MMIO, and we don't really care about plen,
554 section
= flatview_do_translate(address_space_to_flatview(as
), addr
, &xlat
,
555 NULL
, &page_mask
, is_write
, false, &as
);
557 /* Illegal translation */
558 if (section
.mr
== &io_mem_unassigned
) {
562 /* Convert memory region offset into address space offset */
563 xlat
+= section
.offset_within_address_space
-
564 section
.offset_within_region
;
566 return (IOMMUTLBEntry
) {
568 .iova
= addr
& ~page_mask
,
569 .translated_addr
= xlat
& ~page_mask
,
570 .addr_mask
= page_mask
,
571 /* IOTLBs are for DMAs, and DMA only allows on RAMs. */
576 return (IOMMUTLBEntry
) {0};
579 /* Called from RCU critical section */
580 MemoryRegion
*flatview_translate(FlatView
*fv
, hwaddr addr
, hwaddr
*xlat
,
581 hwaddr
*plen
, bool is_write
)
584 MemoryRegionSection section
;
585 AddressSpace
*as
= NULL
;
587 /* This can be MMIO, so setup MMIO bit. */
588 section
= flatview_do_translate(fv
, addr
, xlat
, plen
, NULL
,
589 is_write
, true, &as
);
592 if (xen_enabled() && memory_access_is_direct(mr
, is_write
)) {
593 hwaddr page
= ((addr
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
) - addr
;
594 *plen
= MIN(page
, *plen
);
600 /* Called from RCU critical section */
601 MemoryRegionSection
*
602 address_space_translate_for_iotlb(CPUState
*cpu
, int asidx
, hwaddr addr
,
603 hwaddr
*xlat
, hwaddr
*plen
)
605 MemoryRegionSection
*section
;
606 AddressSpaceDispatch
*d
= atomic_rcu_read(&cpu
->cpu_ases
[asidx
].memory_dispatch
);
608 section
= address_space_translate_internal(d
, addr
, xlat
, plen
, false);
610 assert(!memory_region_is_iommu(section
->mr
));
615 #if !defined(CONFIG_USER_ONLY)
617 static int cpu_common_post_load(void *opaque
, int version_id
)
619 CPUState
*cpu
= opaque
;
621 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
622 version_id is increased. */
623 cpu
->interrupt_request
&= ~0x01;
629 static int cpu_common_pre_load(void *opaque
)
631 CPUState
*cpu
= opaque
;
633 cpu
->exception_index
= -1;
638 static bool cpu_common_exception_index_needed(void *opaque
)
640 CPUState
*cpu
= opaque
;
642 return tcg_enabled() && cpu
->exception_index
!= -1;
645 static const VMStateDescription vmstate_cpu_common_exception_index
= {
646 .name
= "cpu_common/exception_index",
648 .minimum_version_id
= 1,
649 .needed
= cpu_common_exception_index_needed
,
650 .fields
= (VMStateField
[]) {
651 VMSTATE_INT32(exception_index
, CPUState
),
652 VMSTATE_END_OF_LIST()
656 static bool cpu_common_crash_occurred_needed(void *opaque
)
658 CPUState
*cpu
= opaque
;
660 return cpu
->crash_occurred
;
663 static const VMStateDescription vmstate_cpu_common_crash_occurred
= {
664 .name
= "cpu_common/crash_occurred",
666 .minimum_version_id
= 1,
667 .needed
= cpu_common_crash_occurred_needed
,
668 .fields
= (VMStateField
[]) {
669 VMSTATE_BOOL(crash_occurred
, CPUState
),
670 VMSTATE_END_OF_LIST()
674 const VMStateDescription vmstate_cpu_common
= {
675 .name
= "cpu_common",
677 .minimum_version_id
= 1,
678 .pre_load
= cpu_common_pre_load
,
679 .post_load
= cpu_common_post_load
,
680 .fields
= (VMStateField
[]) {
681 VMSTATE_UINT32(halted
, CPUState
),
682 VMSTATE_UINT32(interrupt_request
, CPUState
),
683 VMSTATE_END_OF_LIST()
685 .subsections
= (const VMStateDescription
*[]) {
686 &vmstate_cpu_common_exception_index
,
687 &vmstate_cpu_common_crash_occurred
,
694 CPUState
*qemu_get_cpu(int index
)
699 if (cpu
->cpu_index
== index
) {
707 #if !defined(CONFIG_USER_ONLY)
708 void cpu_address_space_init(CPUState
*cpu
, int asidx
,
709 const char *prefix
, MemoryRegion
*mr
)
711 CPUAddressSpace
*newas
;
712 AddressSpace
*as
= g_new0(AddressSpace
, 1);
716 as_name
= g_strdup_printf("%s-%d", prefix
, cpu
->cpu_index
);
717 address_space_init(as
, mr
, as_name
);
720 /* Target code should have set num_ases before calling us */
721 assert(asidx
< cpu
->num_ases
);
724 /* address space 0 gets the convenience alias */
728 /* KVM cannot currently support multiple address spaces. */
729 assert(asidx
== 0 || !kvm_enabled());
731 if (!cpu
->cpu_ases
) {
732 cpu
->cpu_ases
= g_new0(CPUAddressSpace
, cpu
->num_ases
);
735 newas
= &cpu
->cpu_ases
[asidx
];
739 newas
->tcg_as_listener
.commit
= tcg_commit
;
740 memory_listener_register(&newas
->tcg_as_listener
, as
);
744 AddressSpace
*cpu_get_address_space(CPUState
*cpu
, int asidx
)
746 /* Return the AddressSpace corresponding to the specified index */
747 return cpu
->cpu_ases
[asidx
].as
;
751 void cpu_exec_unrealizefn(CPUState
*cpu
)
753 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
755 cpu_list_remove(cpu
);
757 if (cc
->vmsd
!= NULL
) {
758 vmstate_unregister(NULL
, cc
->vmsd
, cpu
);
760 if (qdev_get_vmsd(DEVICE(cpu
)) == NULL
) {
761 vmstate_unregister(NULL
, &vmstate_cpu_common
, cpu
);
765 Property cpu_common_props
[] = {
766 #ifndef CONFIG_USER_ONLY
767 /* Create a memory property for softmmu CPU object,
768 * so users can wire up its memory. (This can't go in qom/cpu.c
769 * because that file is compiled only once for both user-mode
770 * and system builds.) The default if no link is set up is to use
771 * the system address space.
773 DEFINE_PROP_LINK("memory", CPUState
, memory
, TYPE_MEMORY_REGION
,
776 DEFINE_PROP_END_OF_LIST(),
779 void cpu_exec_initfn(CPUState
*cpu
)
784 #ifndef CONFIG_USER_ONLY
785 cpu
->thread_id
= qemu_get_thread_id();
786 cpu
->memory
= system_memory
;
787 object_ref(OBJECT(cpu
->memory
));
791 void cpu_exec_realizefn(CPUState
*cpu
, Error
**errp
)
793 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
794 static bool tcg_target_initialized
;
798 if (tcg_enabled() && !tcg_target_initialized
) {
799 tcg_target_initialized
= true;
800 cc
->tcg_initialize();
803 #ifndef CONFIG_USER_ONLY
804 if (qdev_get_vmsd(DEVICE(cpu
)) == NULL
) {
805 vmstate_register(NULL
, cpu
->cpu_index
, &vmstate_cpu_common
, cpu
);
807 if (cc
->vmsd
!= NULL
) {
808 vmstate_register(NULL
, cpu
->cpu_index
, cc
->vmsd
, cpu
);
813 #if defined(CONFIG_USER_ONLY)
814 static void breakpoint_invalidate(CPUState
*cpu
, target_ulong pc
)
818 tb_invalidate_phys_page_range(pc
, pc
+ 1, 0);
823 static void breakpoint_invalidate(CPUState
*cpu
, target_ulong pc
)
826 hwaddr phys
= cpu_get_phys_page_attrs_debug(cpu
, pc
, &attrs
);
827 int asidx
= cpu_asidx_from_attrs(cpu
, attrs
);
829 /* Locks grabbed by tb_invalidate_phys_addr */
830 tb_invalidate_phys_addr(cpu
->cpu_ases
[asidx
].as
,
831 phys
| (pc
& ~TARGET_PAGE_MASK
));
836 #if defined(CONFIG_USER_ONLY)
837 void cpu_watchpoint_remove_all(CPUState
*cpu
, int mask
)
842 int cpu_watchpoint_remove(CPUState
*cpu
, vaddr addr
, vaddr len
,
848 void cpu_watchpoint_remove_by_ref(CPUState
*cpu
, CPUWatchpoint
*watchpoint
)
852 int cpu_watchpoint_insert(CPUState
*cpu
, vaddr addr
, vaddr len
,
853 int flags
, CPUWatchpoint
**watchpoint
)
858 /* Add a watchpoint. */
859 int cpu_watchpoint_insert(CPUState
*cpu
, vaddr addr
, vaddr len
,
860 int flags
, CPUWatchpoint
**watchpoint
)
864 /* forbid ranges which are empty or run off the end of the address space */
865 if (len
== 0 || (addr
+ len
- 1) < addr
) {
866 error_report("tried to set invalid watchpoint at %"
867 VADDR_PRIx
", len=%" VADDR_PRIu
, addr
, len
);
870 wp
= g_malloc(sizeof(*wp
));
876 /* keep all GDB-injected watchpoints in front */
877 if (flags
& BP_GDB
) {
878 QTAILQ_INSERT_HEAD(&cpu
->watchpoints
, wp
, entry
);
880 QTAILQ_INSERT_TAIL(&cpu
->watchpoints
, wp
, entry
);
883 tlb_flush_page(cpu
, addr
);
890 /* Remove a specific watchpoint. */
891 int cpu_watchpoint_remove(CPUState
*cpu
, vaddr addr
, vaddr len
,
896 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
897 if (addr
== wp
->vaddr
&& len
== wp
->len
898 && flags
== (wp
->flags
& ~BP_WATCHPOINT_HIT
)) {
899 cpu_watchpoint_remove_by_ref(cpu
, wp
);
906 /* Remove a specific watchpoint by reference. */
907 void cpu_watchpoint_remove_by_ref(CPUState
*cpu
, CPUWatchpoint
*watchpoint
)
909 QTAILQ_REMOVE(&cpu
->watchpoints
, watchpoint
, entry
);
911 tlb_flush_page(cpu
, watchpoint
->vaddr
);
916 /* Remove all matching watchpoints. */
917 void cpu_watchpoint_remove_all(CPUState
*cpu
, int mask
)
919 CPUWatchpoint
*wp
, *next
;
921 QTAILQ_FOREACH_SAFE(wp
, &cpu
->watchpoints
, entry
, next
) {
922 if (wp
->flags
& mask
) {
923 cpu_watchpoint_remove_by_ref(cpu
, wp
);
928 /* Return true if this watchpoint address matches the specified
929 * access (ie the address range covered by the watchpoint overlaps
930 * partially or completely with the address range covered by the
933 static inline bool cpu_watchpoint_address_matches(CPUWatchpoint
*wp
,
937 /* We know the lengths are non-zero, but a little caution is
938 * required to avoid errors in the case where the range ends
939 * exactly at the top of the address space and so addr + len
940 * wraps round to zero.
942 vaddr wpend
= wp
->vaddr
+ wp
->len
- 1;
943 vaddr addrend
= addr
+ len
- 1;
945 return !(addr
> wpend
|| wp
->vaddr
> addrend
);
950 /* Add a breakpoint. */
951 int cpu_breakpoint_insert(CPUState
*cpu
, vaddr pc
, int flags
,
952 CPUBreakpoint
**breakpoint
)
956 bp
= g_malloc(sizeof(*bp
));
961 /* keep all GDB-injected breakpoints in front */
962 if (flags
& BP_GDB
) {
963 QTAILQ_INSERT_HEAD(&cpu
->breakpoints
, bp
, entry
);
965 QTAILQ_INSERT_TAIL(&cpu
->breakpoints
, bp
, entry
);
968 breakpoint_invalidate(cpu
, pc
);
976 /* Remove a specific breakpoint. */
977 int cpu_breakpoint_remove(CPUState
*cpu
, vaddr pc
, int flags
)
981 QTAILQ_FOREACH(bp
, &cpu
->breakpoints
, entry
) {
982 if (bp
->pc
== pc
&& bp
->flags
== flags
) {
983 cpu_breakpoint_remove_by_ref(cpu
, bp
);
990 /* Remove a specific breakpoint by reference. */
991 void cpu_breakpoint_remove_by_ref(CPUState
*cpu
, CPUBreakpoint
*breakpoint
)
993 QTAILQ_REMOVE(&cpu
->breakpoints
, breakpoint
, entry
);
995 breakpoint_invalidate(cpu
, breakpoint
->pc
);
1000 /* Remove all matching breakpoints. */
1001 void cpu_breakpoint_remove_all(CPUState
*cpu
, int mask
)
1003 CPUBreakpoint
*bp
, *next
;
1005 QTAILQ_FOREACH_SAFE(bp
, &cpu
->breakpoints
, entry
, next
) {
1006 if (bp
->flags
& mask
) {
1007 cpu_breakpoint_remove_by_ref(cpu
, bp
);
1012 /* enable or disable single step mode. EXCP_DEBUG is returned by the
1013 CPU loop after each instruction */
1014 void cpu_single_step(CPUState
*cpu
, int enabled
)
1016 if (cpu
->singlestep_enabled
!= enabled
) {
1017 cpu
->singlestep_enabled
= enabled
;
1018 if (kvm_enabled()) {
1019 kvm_update_guest_debug(cpu
, 0);
1021 /* must flush all the translated code to avoid inconsistencies */
1022 /* XXX: only flush what is necessary */
1028 void cpu_abort(CPUState
*cpu
, const char *fmt
, ...)
1035 fprintf(stderr
, "qemu: fatal: ");
1036 vfprintf(stderr
, fmt
, ap
);
1037 fprintf(stderr
, "\n");
1038 cpu_dump_state(cpu
, stderr
, fprintf
, CPU_DUMP_FPU
| CPU_DUMP_CCOP
);
1039 if (qemu_log_separate()) {
1041 qemu_log("qemu: fatal: ");
1042 qemu_log_vprintf(fmt
, ap2
);
1044 log_cpu_state(cpu
, CPU_DUMP_FPU
| CPU_DUMP_CCOP
);
1052 #if defined(CONFIG_USER_ONLY)
1054 struct sigaction act
;
1055 sigfillset(&act
.sa_mask
);
1056 act
.sa_handler
= SIG_DFL
;
1057 sigaction(SIGABRT
, &act
, NULL
);
1063 #if !defined(CONFIG_USER_ONLY)
1064 /* Called from RCU critical section */
1065 static RAMBlock
*qemu_get_ram_block(ram_addr_t addr
)
1069 block
= atomic_rcu_read(&ram_list
.mru_block
);
1070 if (block
&& addr
- block
->offset
< block
->max_length
) {
1073 RAMBLOCK_FOREACH(block
) {
1074 if (addr
- block
->offset
< block
->max_length
) {
1079 fprintf(stderr
, "Bad ram offset %" PRIx64
"\n", (uint64_t)addr
);
1083 /* It is safe to write mru_block outside the iothread lock. This
1088 * xxx removed from list
1092 * call_rcu(reclaim_ramblock, xxx);
1095 * atomic_rcu_set is not needed here. The block was already published
1096 * when it was placed into the list. Here we're just making an extra
1097 * copy of the pointer.
1099 ram_list
.mru_block
= block
;
1103 static void tlb_reset_dirty_range_all(ram_addr_t start
, ram_addr_t length
)
1110 end
= TARGET_PAGE_ALIGN(start
+ length
);
1111 start
&= TARGET_PAGE_MASK
;
1114 block
= qemu_get_ram_block(start
);
1115 assert(block
== qemu_get_ram_block(end
- 1));
1116 start1
= (uintptr_t)ramblock_ptr(block
, start
- block
->offset
);
1118 tlb_reset_dirty(cpu
, start1
, length
);
1123 /* Note: start and end must be within the same ram block. */
1124 bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start
,
1128 DirtyMemoryBlocks
*blocks
;
1129 unsigned long end
, page
;
1136 end
= TARGET_PAGE_ALIGN(start
+ length
) >> TARGET_PAGE_BITS
;
1137 page
= start
>> TARGET_PAGE_BITS
;
1141 blocks
= atomic_rcu_read(&ram_list
.dirty_memory
[client
]);
1143 while (page
< end
) {
1144 unsigned long idx
= page
/ DIRTY_MEMORY_BLOCK_SIZE
;
1145 unsigned long offset
= page
% DIRTY_MEMORY_BLOCK_SIZE
;
1146 unsigned long num
= MIN(end
- page
, DIRTY_MEMORY_BLOCK_SIZE
- offset
);
1148 dirty
|= bitmap_test_and_clear_atomic(blocks
->blocks
[idx
],
1155 if (dirty
&& tcg_enabled()) {
1156 tlb_reset_dirty_range_all(start
, length
);
1162 DirtyBitmapSnapshot
*cpu_physical_memory_snapshot_and_clear_dirty
1163 (ram_addr_t start
, ram_addr_t length
, unsigned client
)
1165 DirtyMemoryBlocks
*blocks
;
1166 unsigned long align
= 1UL << (TARGET_PAGE_BITS
+ BITS_PER_LEVEL
);
1167 ram_addr_t first
= QEMU_ALIGN_DOWN(start
, align
);
1168 ram_addr_t last
= QEMU_ALIGN_UP(start
+ length
, align
);
1169 DirtyBitmapSnapshot
*snap
;
1170 unsigned long page
, end
, dest
;
1172 snap
= g_malloc0(sizeof(*snap
) +
1173 ((last
- first
) >> (TARGET_PAGE_BITS
+ 3)));
1174 snap
->start
= first
;
1177 page
= first
>> TARGET_PAGE_BITS
;
1178 end
= last
>> TARGET_PAGE_BITS
;
1183 blocks
= atomic_rcu_read(&ram_list
.dirty_memory
[client
]);
1185 while (page
< end
) {
1186 unsigned long idx
= page
/ DIRTY_MEMORY_BLOCK_SIZE
;
1187 unsigned long offset
= page
% DIRTY_MEMORY_BLOCK_SIZE
;
1188 unsigned long num
= MIN(end
- page
, DIRTY_MEMORY_BLOCK_SIZE
- offset
);
1190 assert(QEMU_IS_ALIGNED(offset
, (1 << BITS_PER_LEVEL
)));
1191 assert(QEMU_IS_ALIGNED(num
, (1 << BITS_PER_LEVEL
)));
1192 offset
>>= BITS_PER_LEVEL
;
1194 bitmap_copy_and_clear_atomic(snap
->dirty
+ dest
,
1195 blocks
->blocks
[idx
] + offset
,
1198 dest
+= num
>> BITS_PER_LEVEL
;
1203 if (tcg_enabled()) {
1204 tlb_reset_dirty_range_all(start
, length
);
1210 bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot
*snap
,
1214 unsigned long page
, end
;
1216 assert(start
>= snap
->start
);
1217 assert(start
+ length
<= snap
->end
);
1219 end
= TARGET_PAGE_ALIGN(start
+ length
- snap
->start
) >> TARGET_PAGE_BITS
;
1220 page
= (start
- snap
->start
) >> TARGET_PAGE_BITS
;
1222 while (page
< end
) {
1223 if (test_bit(page
, snap
->dirty
)) {
1231 /* Called from RCU critical section */
1232 hwaddr
memory_region_section_get_iotlb(CPUState
*cpu
,
1233 MemoryRegionSection
*section
,
1235 hwaddr paddr
, hwaddr xlat
,
1237 target_ulong
*address
)
1242 if (memory_region_is_ram(section
->mr
)) {
1244 iotlb
= memory_region_get_ram_addr(section
->mr
) + xlat
;
1245 if (!section
->readonly
) {
1246 iotlb
|= PHYS_SECTION_NOTDIRTY
;
1248 iotlb
|= PHYS_SECTION_ROM
;
1251 AddressSpaceDispatch
*d
;
1253 d
= flatview_to_dispatch(section
->fv
);
1254 iotlb
= section
- d
->map
.sections
;
1258 /* Make accesses to pages with watchpoints go via the
1259 watchpoint trap routines. */
1260 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
1261 if (cpu_watchpoint_address_matches(wp
, vaddr
, TARGET_PAGE_SIZE
)) {
1262 /* Avoid trapping reads of pages with a write breakpoint. */
1263 if ((prot
& PAGE_WRITE
) || (wp
->flags
& BP_MEM_READ
)) {
1264 iotlb
= PHYS_SECTION_WATCH
+ paddr
;
1265 *address
|= TLB_MMIO
;
1273 #endif /* defined(CONFIG_USER_ONLY) */
1275 #if !defined(CONFIG_USER_ONLY)
1277 static int subpage_register (subpage_t
*mmio
, uint32_t start
, uint32_t end
,
1279 static subpage_t
*subpage_init(FlatView
*fv
, hwaddr base
);
1281 static void *(*phys_mem_alloc
)(size_t size
, uint64_t *align
) =
1282 qemu_anon_ram_alloc
;
1285 * Set a custom physical guest memory alloator.
1286 * Accelerators with unusual needs may need this. Hopefully, we can
1287 * get rid of it eventually.
1289 void phys_mem_set_alloc(void *(*alloc
)(size_t, uint64_t *align
))
1291 phys_mem_alloc
= alloc
;
1294 static uint16_t phys_section_add(PhysPageMap
*map
,
1295 MemoryRegionSection
*section
)
1297 /* The physical section number is ORed with a page-aligned
1298 * pointer to produce the iotlb entries. Thus it should
1299 * never overflow into the page-aligned value.
1301 assert(map
->sections_nb
< TARGET_PAGE_SIZE
);
1303 if (map
->sections_nb
== map
->sections_nb_alloc
) {
1304 map
->sections_nb_alloc
= MAX(map
->sections_nb_alloc
* 2, 16);
1305 map
->sections
= g_renew(MemoryRegionSection
, map
->sections
,
1306 map
->sections_nb_alloc
);
1308 map
->sections
[map
->sections_nb
] = *section
;
1309 memory_region_ref(section
->mr
);
1310 return map
->sections_nb
++;
1313 static void phys_section_destroy(MemoryRegion
*mr
)
1315 bool have_sub_page
= mr
->subpage
;
1317 memory_region_unref(mr
);
1319 if (have_sub_page
) {
1320 subpage_t
*subpage
= container_of(mr
, subpage_t
, iomem
);
1321 object_unref(OBJECT(&subpage
->iomem
));
1326 static void phys_sections_free(PhysPageMap
*map
)
1328 while (map
->sections_nb
> 0) {
1329 MemoryRegionSection
*section
= &map
->sections
[--map
->sections_nb
];
1330 phys_section_destroy(section
->mr
);
1332 g_free(map
->sections
);
1336 static void register_subpage(FlatView
*fv
, MemoryRegionSection
*section
)
1338 AddressSpaceDispatch
*d
= flatview_to_dispatch(fv
);
1340 hwaddr base
= section
->offset_within_address_space
1342 MemoryRegionSection
*existing
= phys_page_find(d
, base
);
1343 MemoryRegionSection subsection
= {
1344 .offset_within_address_space
= base
,
1345 .size
= int128_make64(TARGET_PAGE_SIZE
),
1349 assert(existing
->mr
->subpage
|| existing
->mr
== &io_mem_unassigned
);
1351 if (!(existing
->mr
->subpage
)) {
1352 subpage
= subpage_init(fv
, base
);
1354 subsection
.mr
= &subpage
->iomem
;
1355 phys_page_set(d
, base
>> TARGET_PAGE_BITS
, 1,
1356 phys_section_add(&d
->map
, &subsection
));
1358 subpage
= container_of(existing
->mr
, subpage_t
, iomem
);
1360 start
= section
->offset_within_address_space
& ~TARGET_PAGE_MASK
;
1361 end
= start
+ int128_get64(section
->size
) - 1;
1362 subpage_register(subpage
, start
, end
,
1363 phys_section_add(&d
->map
, section
));
1367 static void register_multipage(FlatView
*fv
,
1368 MemoryRegionSection
*section
)
1370 AddressSpaceDispatch
*d
= flatview_to_dispatch(fv
);
1371 hwaddr start_addr
= section
->offset_within_address_space
;
1372 uint16_t section_index
= phys_section_add(&d
->map
, section
);
1373 uint64_t num_pages
= int128_get64(int128_rshift(section
->size
,
1377 phys_page_set(d
, start_addr
>> TARGET_PAGE_BITS
, num_pages
, section_index
);
1380 void flatview_add_to_dispatch(FlatView
*fv
, MemoryRegionSection
*section
)
1382 MemoryRegionSection now
= *section
, remain
= *section
;
1383 Int128 page_size
= int128_make64(TARGET_PAGE_SIZE
);
1385 if (now
.offset_within_address_space
& ~TARGET_PAGE_MASK
) {
1386 uint64_t left
= TARGET_PAGE_ALIGN(now
.offset_within_address_space
)
1387 - now
.offset_within_address_space
;
1389 now
.size
= int128_min(int128_make64(left
), now
.size
);
1390 register_subpage(fv
, &now
);
1392 now
.size
= int128_zero();
1394 while (int128_ne(remain
.size
, now
.size
)) {
1395 remain
.size
= int128_sub(remain
.size
, now
.size
);
1396 remain
.offset_within_address_space
+= int128_get64(now
.size
);
1397 remain
.offset_within_region
+= int128_get64(now
.size
);
1399 if (int128_lt(remain
.size
, page_size
)) {
1400 register_subpage(fv
, &now
);
1401 } else if (remain
.offset_within_address_space
& ~TARGET_PAGE_MASK
) {
1402 now
.size
= page_size
;
1403 register_subpage(fv
, &now
);
1405 now
.size
= int128_and(now
.size
, int128_neg(page_size
));
1406 register_multipage(fv
, &now
);
1411 void qemu_flush_coalesced_mmio_buffer(void)
1414 kvm_flush_coalesced_mmio_buffer();
1417 void qemu_mutex_lock_ramlist(void)
1419 qemu_mutex_lock(&ram_list
.mutex
);
1422 void qemu_mutex_unlock_ramlist(void)
1424 qemu_mutex_unlock(&ram_list
.mutex
);
1427 void ram_block_dump(Monitor
*mon
)
1433 monitor_printf(mon
, "%24s %8s %18s %18s %18s\n",
1434 "Block Name", "PSize", "Offset", "Used", "Total");
1435 RAMBLOCK_FOREACH(block
) {
1436 psize
= size_to_str(block
->page_size
);
1437 monitor_printf(mon
, "%24s %8s 0x%016" PRIx64
" 0x%016" PRIx64
1438 " 0x%016" PRIx64
"\n", block
->idstr
, psize
,
1439 (uint64_t)block
->offset
,
1440 (uint64_t)block
->used_length
,
1441 (uint64_t)block
->max_length
);
1449 * FIXME TOCTTOU: this iterates over memory backends' mem-path, which
1450 * may or may not name the same files / on the same filesystem now as
1451 * when we actually open and map them. Iterate over the file
1452 * descriptors instead, and use qemu_fd_getpagesize().
1454 static int find_max_supported_pagesize(Object
*obj
, void *opaque
)
1457 long *hpsize_min
= opaque
;
1459 if (object_dynamic_cast(obj
, TYPE_MEMORY_BACKEND
)) {
1460 mem_path
= object_property_get_str(obj
, "mem-path", NULL
);
1462 long hpsize
= qemu_mempath_getpagesize(mem_path
);
1463 if (hpsize
< *hpsize_min
) {
1464 *hpsize_min
= hpsize
;
1467 *hpsize_min
= getpagesize();
1474 long qemu_getrampagesize(void)
1476 long hpsize
= LONG_MAX
;
1477 long mainrampagesize
;
1478 Object
*memdev_root
;
1481 mainrampagesize
= qemu_mempath_getpagesize(mem_path
);
1483 mainrampagesize
= getpagesize();
1486 /* it's possible we have memory-backend objects with
1487 * hugepage-backed RAM. these may get mapped into system
1488 * address space via -numa parameters or memory hotplug
1489 * hooks. we want to take these into account, but we
1490 * also want to make sure these supported hugepage
1491 * sizes are applicable across the entire range of memory
1492 * we may boot from, so we take the min across all
1493 * backends, and assume normal pages in cases where a
1494 * backend isn't backed by hugepages.
1496 memdev_root
= object_resolve_path("/objects", NULL
);
1498 object_child_foreach(memdev_root
, find_max_supported_pagesize
, &hpsize
);
1500 if (hpsize
== LONG_MAX
) {
1501 /* No additional memory regions found ==> Report main RAM page size */
1502 return mainrampagesize
;
1505 /* If NUMA is disabled or the NUMA nodes are not backed with a
1506 * memory-backend, then there is at least one node using "normal" RAM,
1507 * so if its page size is smaller we have got to report that size instead.
1509 if (hpsize
> mainrampagesize
&&
1510 (nb_numa_nodes
== 0 || numa_info
[0].node_memdev
== NULL
)) {
1513 error_report("Huge page support disabled (n/a for main memory).");
1516 return mainrampagesize
;
1522 long qemu_getrampagesize(void)
1524 return getpagesize();
1529 static int64_t get_file_size(int fd
)
1531 int64_t size
= lseek(fd
, 0, SEEK_END
);
1538 static int file_ram_open(const char *path
,
1539 const char *region_name
,
1544 char *sanitized_name
;
1550 fd
= open(path
, O_RDWR
);
1552 /* @path names an existing file, use it */
1555 if (errno
== ENOENT
) {
1556 /* @path names a file that doesn't exist, create it */
1557 fd
= open(path
, O_RDWR
| O_CREAT
| O_EXCL
, 0644);
1562 } else if (errno
== EISDIR
) {
1563 /* @path names a directory, create a file there */
1564 /* Make name safe to use with mkstemp by replacing '/' with '_'. */
1565 sanitized_name
= g_strdup(region_name
);
1566 for (c
= sanitized_name
; *c
!= '\0'; c
++) {
1572 filename
= g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path
,
1574 g_free(sanitized_name
);
1576 fd
= mkstemp(filename
);
1584 if (errno
!= EEXIST
&& errno
!= EINTR
) {
1585 error_setg_errno(errp
, errno
,
1586 "can't open backing store %s for guest RAM",
1591 * Try again on EINTR and EEXIST. The latter happens when
1592 * something else creates the file between our two open().
1599 static void *file_ram_alloc(RAMBlock
*block
,
1607 block
->page_size
= qemu_fd_getpagesize(fd
);
1608 block
->mr
->align
= block
->page_size
;
1609 #if defined(__s390x__)
1610 if (kvm_enabled()) {
1611 block
->mr
->align
= MAX(block
->mr
->align
, QEMU_VMALLOC_ALIGN
);
1615 if (memory
< block
->page_size
) {
1616 error_setg(errp
, "memory size 0x" RAM_ADDR_FMT
" must be equal to "
1617 "or larger than page size 0x%zx",
1618 memory
, block
->page_size
);
1622 memory
= ROUND_UP(memory
, block
->page_size
);
1625 * ftruncate is not supported by hugetlbfs in older
1626 * hosts, so don't bother bailing out on errors.
1627 * If anything goes wrong with it under other filesystems,
1630 * Do not truncate the non-empty backend file to avoid corrupting
1631 * the existing data in the file. Disabling shrinking is not
1632 * enough. For example, the current vNVDIMM implementation stores
1633 * the guest NVDIMM labels at the end of the backend file. If the
1634 * backend file is later extended, QEMU will not be able to find
1635 * those labels. Therefore, extending the non-empty backend file
1636 * is disabled as well.
1638 if (truncate
&& ftruncate(fd
, memory
)) {
1639 perror("ftruncate");
1642 area
= qemu_ram_mmap(fd
, memory
, block
->mr
->align
,
1643 block
->flags
& RAM_SHARED
);
1644 if (area
== MAP_FAILED
) {
1645 error_setg_errno(errp
, errno
,
1646 "unable to map backing store for guest RAM");
1651 os_mem_prealloc(fd
, area
, memory
, smp_cpus
, errp
);
1652 if (errp
&& *errp
) {
1653 qemu_ram_munmap(area
, memory
);
1663 /* Allocate space within the ram_addr_t space that governs the
1665 * Called with the ramlist lock held.
1667 static ram_addr_t
find_ram_offset(ram_addr_t size
)
1669 RAMBlock
*block
, *next_block
;
1670 ram_addr_t offset
= RAM_ADDR_MAX
, mingap
= RAM_ADDR_MAX
;
1672 assert(size
!= 0); /* it would hand out same offset multiple times */
1674 if (QLIST_EMPTY_RCU(&ram_list
.blocks
)) {
1678 RAMBLOCK_FOREACH(block
) {
1679 ram_addr_t candidate
, next
= RAM_ADDR_MAX
;
1681 candidate
= block
->offset
+ block
->max_length
;
1683 /* Search for the closest following block
1686 RAMBLOCK_FOREACH(next_block
) {
1687 if (next_block
->offset
>= candidate
) {
1688 next
= MIN(next
, next_block
->offset
);
1692 /* If it fits remember our place and remember the size
1693 * of gap, but keep going so that we might find a smaller
1694 * gap to fill so avoiding fragmentation.
1696 if (next
- candidate
>= size
&& next
- candidate
< mingap
) {
1698 mingap
= next
- candidate
;
1701 trace_find_ram_offset_loop(size
, candidate
, offset
, next
, mingap
);
1704 if (offset
== RAM_ADDR_MAX
) {
1705 fprintf(stderr
, "Failed to find gap of requested size: %" PRIu64
"\n",
1710 trace_find_ram_offset(size
, offset
);
1715 unsigned long last_ram_page(void)
1718 ram_addr_t last
= 0;
1721 RAMBLOCK_FOREACH(block
) {
1722 last
= MAX(last
, block
->offset
+ block
->max_length
);
1725 return last
>> TARGET_PAGE_BITS
;
1728 static void qemu_ram_setup_dump(void *addr
, ram_addr_t size
)
1732 /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */
1733 if (!machine_dump_guest_core(current_machine
)) {
1734 ret
= qemu_madvise(addr
, size
, QEMU_MADV_DONTDUMP
);
1736 perror("qemu_madvise");
1737 fprintf(stderr
, "madvise doesn't support MADV_DONTDUMP, "
1738 "but dump_guest_core=off specified\n");
1743 const char *qemu_ram_get_idstr(RAMBlock
*rb
)
1748 bool qemu_ram_is_shared(RAMBlock
*rb
)
1750 return rb
->flags
& RAM_SHARED
;
1753 /* Called with iothread lock held. */
1754 void qemu_ram_set_idstr(RAMBlock
*new_block
, const char *name
, DeviceState
*dev
)
1759 assert(!new_block
->idstr
[0]);
1762 char *id
= qdev_get_dev_path(dev
);
1764 snprintf(new_block
->idstr
, sizeof(new_block
->idstr
), "%s/", id
);
1768 pstrcat(new_block
->idstr
, sizeof(new_block
->idstr
), name
);
1771 RAMBLOCK_FOREACH(block
) {
1772 if (block
!= new_block
&&
1773 !strcmp(block
->idstr
, new_block
->idstr
)) {
1774 fprintf(stderr
, "RAMBlock \"%s\" already registered, abort!\n",
1782 /* Called with iothread lock held. */
1783 void qemu_ram_unset_idstr(RAMBlock
*block
)
1785 /* FIXME: arch_init.c assumes that this is not called throughout
1786 * migration. Ignore the problem since hot-unplug during migration
1787 * does not work anyway.
1790 memset(block
->idstr
, 0, sizeof(block
->idstr
));
1794 size_t qemu_ram_pagesize(RAMBlock
*rb
)
1796 return rb
->page_size
;
1799 /* Returns the largest size of page in use */
1800 size_t qemu_ram_pagesize_largest(void)
1805 RAMBLOCK_FOREACH(block
) {
1806 largest
= MAX(largest
, qemu_ram_pagesize(block
));
1812 static int memory_try_enable_merging(void *addr
, size_t len
)
1814 if (!machine_mem_merge(current_machine
)) {
1815 /* disabled by the user */
1819 return qemu_madvise(addr
, len
, QEMU_MADV_MERGEABLE
);
1822 /* Only legal before guest might have detected the memory size: e.g. on
1823 * incoming migration, or right after reset.
1825 * As memory core doesn't know how is memory accessed, it is up to
1826 * resize callback to update device state and/or add assertions to detect
1827 * misuse, if necessary.
1829 int qemu_ram_resize(RAMBlock
*block
, ram_addr_t newsize
, Error
**errp
)
1833 newsize
= HOST_PAGE_ALIGN(newsize
);
1835 if (block
->used_length
== newsize
) {
1839 if (!(block
->flags
& RAM_RESIZEABLE
)) {
1840 error_setg_errno(errp
, EINVAL
,
1841 "Length mismatch: %s: 0x" RAM_ADDR_FMT
1842 " in != 0x" RAM_ADDR_FMT
, block
->idstr
,
1843 newsize
, block
->used_length
);
1847 if (block
->max_length
< newsize
) {
1848 error_setg_errno(errp
, EINVAL
,
1849 "Length too large: %s: 0x" RAM_ADDR_FMT
1850 " > 0x" RAM_ADDR_FMT
, block
->idstr
,
1851 newsize
, block
->max_length
);
1855 cpu_physical_memory_clear_dirty_range(block
->offset
, block
->used_length
);
1856 block
->used_length
= newsize
;
1857 cpu_physical_memory_set_dirty_range(block
->offset
, block
->used_length
,
1859 memory_region_set_size(block
->mr
, newsize
);
1860 if (block
->resized
) {
1861 block
->resized(block
->idstr
, newsize
, block
->host
);
1866 /* Called with ram_list.mutex held */
1867 static void dirty_memory_extend(ram_addr_t old_ram_size
,
1868 ram_addr_t new_ram_size
)
1870 ram_addr_t old_num_blocks
= DIV_ROUND_UP(old_ram_size
,
1871 DIRTY_MEMORY_BLOCK_SIZE
);
1872 ram_addr_t new_num_blocks
= DIV_ROUND_UP(new_ram_size
,
1873 DIRTY_MEMORY_BLOCK_SIZE
);
1876 /* Only need to extend if block count increased */
1877 if (new_num_blocks
<= old_num_blocks
) {
1881 for (i
= 0; i
< DIRTY_MEMORY_NUM
; i
++) {
1882 DirtyMemoryBlocks
*old_blocks
;
1883 DirtyMemoryBlocks
*new_blocks
;
1886 old_blocks
= atomic_rcu_read(&ram_list
.dirty_memory
[i
]);
1887 new_blocks
= g_malloc(sizeof(*new_blocks
) +
1888 sizeof(new_blocks
->blocks
[0]) * new_num_blocks
);
1890 if (old_num_blocks
) {
1891 memcpy(new_blocks
->blocks
, old_blocks
->blocks
,
1892 old_num_blocks
* sizeof(old_blocks
->blocks
[0]));
1895 for (j
= old_num_blocks
; j
< new_num_blocks
; j
++) {
1896 new_blocks
->blocks
[j
] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE
);
1899 atomic_rcu_set(&ram_list
.dirty_memory
[i
], new_blocks
);
1902 g_free_rcu(old_blocks
, rcu
);
1907 static void ram_block_add(RAMBlock
*new_block
, Error
**errp
)
1910 RAMBlock
*last_block
= NULL
;
1911 ram_addr_t old_ram_size
, new_ram_size
;
1914 old_ram_size
= last_ram_page();
1916 qemu_mutex_lock_ramlist();
1917 new_block
->offset
= find_ram_offset(new_block
->max_length
);
1919 if (!new_block
->host
) {
1920 if (xen_enabled()) {
1921 xen_ram_alloc(new_block
->offset
, new_block
->max_length
,
1922 new_block
->mr
, &err
);
1924 error_propagate(errp
, err
);
1925 qemu_mutex_unlock_ramlist();
1929 new_block
->host
= phys_mem_alloc(new_block
->max_length
,
1930 &new_block
->mr
->align
);
1931 if (!new_block
->host
) {
1932 error_setg_errno(errp
, errno
,
1933 "cannot set up guest memory '%s'",
1934 memory_region_name(new_block
->mr
));
1935 qemu_mutex_unlock_ramlist();
1938 memory_try_enable_merging(new_block
->host
, new_block
->max_length
);
1942 new_ram_size
= MAX(old_ram_size
,
1943 (new_block
->offset
+ new_block
->max_length
) >> TARGET_PAGE_BITS
);
1944 if (new_ram_size
> old_ram_size
) {
1945 dirty_memory_extend(old_ram_size
, new_ram_size
);
1947 /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ,
1948 * QLIST (which has an RCU-friendly variant) does not have insertion at
1949 * tail, so save the last element in last_block.
1951 RAMBLOCK_FOREACH(block
) {
1953 if (block
->max_length
< new_block
->max_length
) {
1958 QLIST_INSERT_BEFORE_RCU(block
, new_block
, next
);
1959 } else if (last_block
) {
1960 QLIST_INSERT_AFTER_RCU(last_block
, new_block
, next
);
1961 } else { /* list is empty */
1962 QLIST_INSERT_HEAD_RCU(&ram_list
.blocks
, new_block
, next
);
1964 ram_list
.mru_block
= NULL
;
1966 /* Write list before version */
1969 qemu_mutex_unlock_ramlist();
1971 cpu_physical_memory_set_dirty_range(new_block
->offset
,
1972 new_block
->used_length
,
1975 if (new_block
->host
) {
1976 qemu_ram_setup_dump(new_block
->host
, new_block
->max_length
);
1977 qemu_madvise(new_block
->host
, new_block
->max_length
, QEMU_MADV_HUGEPAGE
);
1978 /* MADV_DONTFORK is also needed by KVM in absence of synchronous MMU */
1979 qemu_madvise(new_block
->host
, new_block
->max_length
, QEMU_MADV_DONTFORK
);
1980 ram_block_notify_add(new_block
->host
, new_block
->max_length
);
1985 RAMBlock
*qemu_ram_alloc_from_fd(ram_addr_t size
, MemoryRegion
*mr
,
1989 RAMBlock
*new_block
;
1990 Error
*local_err
= NULL
;
1993 if (xen_enabled()) {
1994 error_setg(errp
, "-mem-path not supported with Xen");
1998 if (kvm_enabled() && !kvm_has_sync_mmu()) {
2000 "host lacks kvm mmu notifiers, -mem-path unsupported");
2004 if (phys_mem_alloc
!= qemu_anon_ram_alloc
) {
2006 * file_ram_alloc() needs to allocate just like
2007 * phys_mem_alloc, but we haven't bothered to provide
2011 "-mem-path not supported with this accelerator");
2015 size
= HOST_PAGE_ALIGN(size
);
2016 file_size
= get_file_size(fd
);
2017 if (file_size
> 0 && file_size
< size
) {
2018 error_setg(errp
, "backing store %s size 0x%" PRIx64
2019 " does not match 'size' option 0x" RAM_ADDR_FMT
,
2020 mem_path
, file_size
, size
);
2024 new_block
= g_malloc0(sizeof(*new_block
));
2026 new_block
->used_length
= size
;
2027 new_block
->max_length
= size
;
2028 new_block
->flags
= share
? RAM_SHARED
: 0;
2029 new_block
->host
= file_ram_alloc(new_block
, size
, fd
, !file_size
, errp
);
2030 if (!new_block
->host
) {
2035 ram_block_add(new_block
, &local_err
);
2038 error_propagate(errp
, local_err
);
2046 RAMBlock
*qemu_ram_alloc_from_file(ram_addr_t size
, MemoryRegion
*mr
,
2047 bool share
, const char *mem_path
,
2054 fd
= file_ram_open(mem_path
, memory_region_name(mr
), &created
, errp
);
2059 block
= qemu_ram_alloc_from_fd(size
, mr
, share
, fd
, errp
);
2073 RAMBlock
*qemu_ram_alloc_internal(ram_addr_t size
, ram_addr_t max_size
,
2074 void (*resized
)(const char*,
2077 void *host
, bool resizeable
,
2078 MemoryRegion
*mr
, Error
**errp
)
2080 RAMBlock
*new_block
;
2081 Error
*local_err
= NULL
;
2083 size
= HOST_PAGE_ALIGN(size
);
2084 max_size
= HOST_PAGE_ALIGN(max_size
);
2085 new_block
= g_malloc0(sizeof(*new_block
));
2087 new_block
->resized
= resized
;
2088 new_block
->used_length
= size
;
2089 new_block
->max_length
= max_size
;
2090 assert(max_size
>= size
);
2092 new_block
->page_size
= getpagesize();
2093 new_block
->host
= host
;
2095 new_block
->flags
|= RAM_PREALLOC
;
2098 new_block
->flags
|= RAM_RESIZEABLE
;
2100 ram_block_add(new_block
, &local_err
);
2103 error_propagate(errp
, local_err
);
2109 RAMBlock
*qemu_ram_alloc_from_ptr(ram_addr_t size
, void *host
,
2110 MemoryRegion
*mr
, Error
**errp
)
2112 return qemu_ram_alloc_internal(size
, size
, NULL
, host
, false, mr
, errp
);
2115 RAMBlock
*qemu_ram_alloc(ram_addr_t size
, MemoryRegion
*mr
, Error
**errp
)
2117 return qemu_ram_alloc_internal(size
, size
, NULL
, NULL
, false, mr
, errp
);
2120 RAMBlock
*qemu_ram_alloc_resizeable(ram_addr_t size
, ram_addr_t maxsz
,
2121 void (*resized
)(const char*,
2124 MemoryRegion
*mr
, Error
**errp
)
2126 return qemu_ram_alloc_internal(size
, maxsz
, resized
, NULL
, true, mr
, errp
);
2129 static void reclaim_ramblock(RAMBlock
*block
)
2131 if (block
->flags
& RAM_PREALLOC
) {
2133 } else if (xen_enabled()) {
2134 xen_invalidate_map_cache_entry(block
->host
);
2136 } else if (block
->fd
>= 0) {
2137 qemu_ram_munmap(block
->host
, block
->max_length
);
2141 qemu_anon_ram_free(block
->host
, block
->max_length
);
2146 void qemu_ram_free(RAMBlock
*block
)
2153 ram_block_notify_remove(block
->host
, block
->max_length
);
2156 qemu_mutex_lock_ramlist();
2157 QLIST_REMOVE_RCU(block
, next
);
2158 ram_list
.mru_block
= NULL
;
2159 /* Write list before version */
2162 call_rcu(block
, reclaim_ramblock
, rcu
);
2163 qemu_mutex_unlock_ramlist();
2167 void qemu_ram_remap(ram_addr_t addr
, ram_addr_t length
)
2174 RAMBLOCK_FOREACH(block
) {
2175 offset
= addr
- block
->offset
;
2176 if (offset
< block
->max_length
) {
2177 vaddr
= ramblock_ptr(block
, offset
);
2178 if (block
->flags
& RAM_PREALLOC
) {
2180 } else if (xen_enabled()) {
2184 if (block
->fd
>= 0) {
2185 flags
|= (block
->flags
& RAM_SHARED
?
2186 MAP_SHARED
: MAP_PRIVATE
);
2187 area
= mmap(vaddr
, length
, PROT_READ
| PROT_WRITE
,
2188 flags
, block
->fd
, offset
);
2191 * Remap needs to match alloc. Accelerators that
2192 * set phys_mem_alloc never remap. If they did,
2193 * we'd need a remap hook here.
2195 assert(phys_mem_alloc
== qemu_anon_ram_alloc
);
2197 flags
|= MAP_PRIVATE
| MAP_ANONYMOUS
;
2198 area
= mmap(vaddr
, length
, PROT_READ
| PROT_WRITE
,
2201 if (area
!= vaddr
) {
2202 fprintf(stderr
, "Could not remap addr: "
2203 RAM_ADDR_FMT
"@" RAM_ADDR_FMT
"\n",
2207 memory_try_enable_merging(vaddr
, length
);
2208 qemu_ram_setup_dump(vaddr
, length
);
2213 #endif /* !_WIN32 */
2215 /* Return a host pointer to ram allocated with qemu_ram_alloc.
2216 * This should not be used for general purpose DMA. Use address_space_map
2217 * or address_space_rw instead. For local memory (e.g. video ram) that the
2218 * device owns, use memory_region_get_ram_ptr.
2220 * Called within RCU critical section.
2222 void *qemu_map_ram_ptr(RAMBlock
*ram_block
, ram_addr_t addr
)
2224 RAMBlock
*block
= ram_block
;
2226 if (block
== NULL
) {
2227 block
= qemu_get_ram_block(addr
);
2228 addr
-= block
->offset
;
2231 if (xen_enabled() && block
->host
== NULL
) {
2232 /* We need to check if the requested address is in the RAM
2233 * because we don't want to map the entire memory in QEMU.
2234 * In that case just map until the end of the page.
2236 if (block
->offset
== 0) {
2237 return xen_map_cache(addr
, 0, 0, false);
2240 block
->host
= xen_map_cache(block
->offset
, block
->max_length
, 1, false);
2242 return ramblock_ptr(block
, addr
);
2245 /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr
2246 * but takes a size argument.
2248 * Called within RCU critical section.
2250 static void *qemu_ram_ptr_length(RAMBlock
*ram_block
, ram_addr_t addr
,
2251 hwaddr
*size
, bool lock
)
2253 RAMBlock
*block
= ram_block
;
2258 if (block
== NULL
) {
2259 block
= qemu_get_ram_block(addr
);
2260 addr
-= block
->offset
;
2262 *size
= MIN(*size
, block
->max_length
- addr
);
2264 if (xen_enabled() && block
->host
== NULL
) {
2265 /* We need to check if the requested address is in the RAM
2266 * because we don't want to map the entire memory in QEMU.
2267 * In that case just map the requested area.
2269 if (block
->offset
== 0) {
2270 return xen_map_cache(addr
, *size
, lock
, lock
);
2273 block
->host
= xen_map_cache(block
->offset
, block
->max_length
, 1, lock
);
2276 return ramblock_ptr(block
, addr
);
2280 * Translates a host ptr back to a RAMBlock, a ram_addr and an offset
2283 * ptr: Host pointer to look up
2284 * round_offset: If true round the result offset down to a page boundary
2285 * *ram_addr: set to result ram_addr
2286 * *offset: set to result offset within the RAMBlock
2288 * Returns: RAMBlock (or NULL if not found)
2290 * By the time this function returns, the returned pointer is not protected
2291 * by RCU anymore. If the caller is not within an RCU critical section and
2292 * does not hold the iothread lock, it must have other means of protecting the
2293 * pointer, such as a reference to the region that includes the incoming
2296 RAMBlock
*qemu_ram_block_from_host(void *ptr
, bool round_offset
,
2300 uint8_t *host
= ptr
;
2302 if (xen_enabled()) {
2303 ram_addr_t ram_addr
;
2305 ram_addr
= xen_ram_addr_from_mapcache(ptr
);
2306 block
= qemu_get_ram_block(ram_addr
);
2308 *offset
= ram_addr
- block
->offset
;
2315 block
= atomic_rcu_read(&ram_list
.mru_block
);
2316 if (block
&& block
->host
&& host
- block
->host
< block
->max_length
) {
2320 RAMBLOCK_FOREACH(block
) {
2321 /* This case append when the block is not mapped. */
2322 if (block
->host
== NULL
) {
2325 if (host
- block
->host
< block
->max_length
) {
2334 *offset
= (host
- block
->host
);
2336 *offset
&= TARGET_PAGE_MASK
;
2343 * Finds the named RAMBlock
2345 * name: The name of RAMBlock to find
2347 * Returns: RAMBlock (or NULL if not found)
2349 RAMBlock
*qemu_ram_block_by_name(const char *name
)
2353 RAMBLOCK_FOREACH(block
) {
2354 if (!strcmp(name
, block
->idstr
)) {
2362 /* Some of the softmmu routines need to translate from a host pointer
2363 (typically a TLB entry) back to a ram offset. */
2364 ram_addr_t
qemu_ram_addr_from_host(void *ptr
)
2369 block
= qemu_ram_block_from_host(ptr
, false, &offset
);
2371 return RAM_ADDR_INVALID
;
2374 return block
->offset
+ offset
;
2377 /* Called within RCU critical section. */
2378 void memory_notdirty_write_prepare(NotDirtyInfo
*ndi
,
2381 ram_addr_t ram_addr
,
2385 ndi
->ram_addr
= ram_addr
;
2386 ndi
->mem_vaddr
= mem_vaddr
;
2388 ndi
->locked
= false;
2390 assert(tcg_enabled());
2391 if (!cpu_physical_memory_get_dirty_flag(ram_addr
, DIRTY_MEMORY_CODE
)) {
2394 tb_invalidate_phys_page_fast(ram_addr
, size
);
2398 /* Called within RCU critical section. */
2399 void memory_notdirty_write_complete(NotDirtyInfo
*ndi
)
2405 /* Set both VGA and migration bits for simplicity and to remove
2406 * the notdirty callback faster.
2408 cpu_physical_memory_set_dirty_range(ndi
->ram_addr
, ndi
->size
,
2409 DIRTY_CLIENTS_NOCODE
);
2410 /* we remove the notdirty callback only if the code has been
2412 if (!cpu_physical_memory_is_clean(ndi
->ram_addr
)) {
2413 tlb_set_dirty(ndi
->cpu
, ndi
->mem_vaddr
);
2417 /* Called within RCU critical section. */
2418 static void notdirty_mem_write(void *opaque
, hwaddr ram_addr
,
2419 uint64_t val
, unsigned size
)
2423 memory_notdirty_write_prepare(&ndi
, current_cpu
, current_cpu
->mem_io_vaddr
,
2428 stb_p(qemu_map_ram_ptr(NULL
, ram_addr
), val
);
2431 stw_p(qemu_map_ram_ptr(NULL
, ram_addr
), val
);
2434 stl_p(qemu_map_ram_ptr(NULL
, ram_addr
), val
);
2437 stq_p(qemu_map_ram_ptr(NULL
, ram_addr
), val
);
2442 memory_notdirty_write_complete(&ndi
);
2445 static bool notdirty_mem_accepts(void *opaque
, hwaddr addr
,
2446 unsigned size
, bool is_write
)
2451 static const MemoryRegionOps notdirty_mem_ops
= {
2452 .write
= notdirty_mem_write
,
2453 .valid
.accepts
= notdirty_mem_accepts
,
2454 .endianness
= DEVICE_NATIVE_ENDIAN
,
2456 .min_access_size
= 1,
2457 .max_access_size
= 8,
2461 .min_access_size
= 1,
2462 .max_access_size
= 8,
2467 /* Generate a debug exception if a watchpoint has been hit. */
2468 static void check_watchpoint(int offset
, int len
, MemTxAttrs attrs
, int flags
)
2470 CPUState
*cpu
= current_cpu
;
2471 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
2475 assert(tcg_enabled());
2476 if (cpu
->watchpoint_hit
) {
2477 /* We re-entered the check after replacing the TB. Now raise
2478 * the debug interrupt so that is will trigger after the
2479 * current instruction. */
2480 cpu_interrupt(cpu
, CPU_INTERRUPT_DEBUG
);
2483 vaddr
= (cpu
->mem_io_vaddr
& TARGET_PAGE_MASK
) + offset
;
2484 vaddr
= cc
->adjust_watchpoint_address(cpu
, vaddr
, len
);
2485 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
2486 if (cpu_watchpoint_address_matches(wp
, vaddr
, len
)
2487 && (wp
->flags
& flags
)) {
2488 if (flags
== BP_MEM_READ
) {
2489 wp
->flags
|= BP_WATCHPOINT_HIT_READ
;
2491 wp
->flags
|= BP_WATCHPOINT_HIT_WRITE
;
2493 wp
->hitaddr
= vaddr
;
2494 wp
->hitattrs
= attrs
;
2495 if (!cpu
->watchpoint_hit
) {
2496 if (wp
->flags
& BP_CPU
&&
2497 !cc
->debug_check_watchpoint(cpu
, wp
)) {
2498 wp
->flags
&= ~BP_WATCHPOINT_HIT
;
2501 cpu
->watchpoint_hit
= wp
;
2503 /* Both tb_lock and iothread_mutex will be reset when
2504 * cpu_loop_exit or cpu_loop_exit_noexc longjmp
2505 * back into the cpu_exec main loop.
2508 tb_check_watchpoint(cpu
);
2509 if (wp
->flags
& BP_STOP_BEFORE_ACCESS
) {
2510 cpu
->exception_index
= EXCP_DEBUG
;
2513 /* Force execution of one insn next time. */
2514 cpu
->cflags_next_tb
= 1 | curr_cflags();
2515 cpu_loop_exit_noexc(cpu
);
2519 wp
->flags
&= ~BP_WATCHPOINT_HIT
;
2524 /* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
2525 so these check for a hit then pass through to the normal out-of-line
2527 static MemTxResult
watch_mem_read(void *opaque
, hwaddr addr
, uint64_t *pdata
,
2528 unsigned size
, MemTxAttrs attrs
)
2532 int asidx
= cpu_asidx_from_attrs(current_cpu
, attrs
);
2533 AddressSpace
*as
= current_cpu
->cpu_ases
[asidx
].as
;
2535 check_watchpoint(addr
& ~TARGET_PAGE_MASK
, size
, attrs
, BP_MEM_READ
);
2538 data
= address_space_ldub(as
, addr
, attrs
, &res
);
2541 data
= address_space_lduw(as
, addr
, attrs
, &res
);
2544 data
= address_space_ldl(as
, addr
, attrs
, &res
);
2547 data
= address_space_ldq(as
, addr
, attrs
, &res
);
2555 static MemTxResult
watch_mem_write(void *opaque
, hwaddr addr
,
2556 uint64_t val
, unsigned size
,
2560 int asidx
= cpu_asidx_from_attrs(current_cpu
, attrs
);
2561 AddressSpace
*as
= current_cpu
->cpu_ases
[asidx
].as
;
2563 check_watchpoint(addr
& ~TARGET_PAGE_MASK
, size
, attrs
, BP_MEM_WRITE
);
2566 address_space_stb(as
, addr
, val
, attrs
, &res
);
2569 address_space_stw(as
, addr
, val
, attrs
, &res
);
2572 address_space_stl(as
, addr
, val
, attrs
, &res
);
2575 address_space_stq(as
, addr
, val
, attrs
, &res
);
2582 static const MemoryRegionOps watch_mem_ops
= {
2583 .read_with_attrs
= watch_mem_read
,
2584 .write_with_attrs
= watch_mem_write
,
2585 .endianness
= DEVICE_NATIVE_ENDIAN
,
2587 .min_access_size
= 1,
2588 .max_access_size
= 8,
2592 .min_access_size
= 1,
2593 .max_access_size
= 8,
2598 static MemTxResult
flatview_write(FlatView
*fv
, hwaddr addr
, MemTxAttrs attrs
,
2599 const uint8_t *buf
, int len
);
2600 static bool flatview_access_valid(FlatView
*fv
, hwaddr addr
, int len
,
2603 static MemTxResult
subpage_read(void *opaque
, hwaddr addr
, uint64_t *data
,
2604 unsigned len
, MemTxAttrs attrs
)
2606 subpage_t
*subpage
= opaque
;
2610 #if defined(DEBUG_SUBPAGE)
2611 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
"\n", __func__
,
2612 subpage
, len
, addr
);
2614 res
= flatview_read(subpage
->fv
, addr
+ subpage
->base
, attrs
, buf
, len
);
2620 *data
= ldub_p(buf
);
2623 *data
= lduw_p(buf
);
2636 static MemTxResult
subpage_write(void *opaque
, hwaddr addr
,
2637 uint64_t value
, unsigned len
, MemTxAttrs attrs
)
2639 subpage_t
*subpage
= opaque
;
2642 #if defined(DEBUG_SUBPAGE)
2643 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
2644 " value %"PRIx64
"\n",
2645 __func__
, subpage
, len
, addr
, value
);
2663 return flatview_write(subpage
->fv
, addr
+ subpage
->base
, attrs
, buf
, len
);
2666 static bool subpage_accepts(void *opaque
, hwaddr addr
,
2667 unsigned len
, bool is_write
)
2669 subpage_t
*subpage
= opaque
;
2670 #if defined(DEBUG_SUBPAGE)
2671 printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx
"\n",
2672 __func__
, subpage
, is_write
? 'w' : 'r', len
, addr
);
2675 return flatview_access_valid(subpage
->fv
, addr
+ subpage
->base
,
2679 static const MemoryRegionOps subpage_ops
= {
2680 .read_with_attrs
= subpage_read
,
2681 .write_with_attrs
= subpage_write
,
2682 .impl
.min_access_size
= 1,
2683 .impl
.max_access_size
= 8,
2684 .valid
.min_access_size
= 1,
2685 .valid
.max_access_size
= 8,
2686 .valid
.accepts
= subpage_accepts
,
2687 .endianness
= DEVICE_NATIVE_ENDIAN
,
2690 static int subpage_register (subpage_t
*mmio
, uint32_t start
, uint32_t end
,
2695 if (start
>= TARGET_PAGE_SIZE
|| end
>= TARGET_PAGE_SIZE
)
2697 idx
= SUBPAGE_IDX(start
);
2698 eidx
= SUBPAGE_IDX(end
);
2699 #if defined(DEBUG_SUBPAGE)
2700 printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n",
2701 __func__
, mmio
, start
, end
, idx
, eidx
, section
);
2703 for (; idx
<= eidx
; idx
++) {
2704 mmio
->sub_section
[idx
] = section
;
2710 static subpage_t
*subpage_init(FlatView
*fv
, hwaddr base
)
2714 mmio
= g_malloc0(sizeof(subpage_t
) + TARGET_PAGE_SIZE
* sizeof(uint16_t));
2717 memory_region_init_io(&mmio
->iomem
, NULL
, &subpage_ops
, mmio
,
2718 NULL
, TARGET_PAGE_SIZE
);
2719 mmio
->iomem
.subpage
= true;
2720 #if defined(DEBUG_SUBPAGE)
2721 printf("%s: %p base " TARGET_FMT_plx
" len %08x\n", __func__
,
2722 mmio
, base
, TARGET_PAGE_SIZE
);
2724 subpage_register(mmio
, 0, TARGET_PAGE_SIZE
-1, PHYS_SECTION_UNASSIGNED
);
2729 static uint16_t dummy_section(PhysPageMap
*map
, FlatView
*fv
, MemoryRegion
*mr
)
2732 MemoryRegionSection section
= {
2735 .offset_within_address_space
= 0,
2736 .offset_within_region
= 0,
2737 .size
= int128_2_64(),
2740 return phys_section_add(map
, §ion
);
2743 static void readonly_mem_write(void *opaque
, hwaddr addr
,
2744 uint64_t val
, unsigned size
)
2746 /* Ignore any write to ROM. */
2749 static bool readonly_mem_accepts(void *opaque
, hwaddr addr
,
2750 unsigned size
, bool is_write
)
2755 /* This will only be used for writes, because reads are special cased
2756 * to directly access the underlying host ram.
2758 static const MemoryRegionOps readonly_mem_ops
= {
2759 .write
= readonly_mem_write
,
2760 .valid
.accepts
= readonly_mem_accepts
,
2761 .endianness
= DEVICE_NATIVE_ENDIAN
,
2763 .min_access_size
= 1,
2764 .max_access_size
= 8,
2768 .min_access_size
= 1,
2769 .max_access_size
= 8,
2774 MemoryRegion
*iotlb_to_region(CPUState
*cpu
, hwaddr index
, MemTxAttrs attrs
)
2776 int asidx
= cpu_asidx_from_attrs(cpu
, attrs
);
2777 CPUAddressSpace
*cpuas
= &cpu
->cpu_ases
[asidx
];
2778 AddressSpaceDispatch
*d
= atomic_rcu_read(&cpuas
->memory_dispatch
);
2779 MemoryRegionSection
*sections
= d
->map
.sections
;
2781 return sections
[index
& ~TARGET_PAGE_MASK
].mr
;
2784 static void io_mem_init(void)
2786 memory_region_init_io(&io_mem_rom
, NULL
, &readonly_mem_ops
,
2787 NULL
, NULL
, UINT64_MAX
);
2788 memory_region_init_io(&io_mem_unassigned
, NULL
, &unassigned_mem_ops
, NULL
,
2791 /* io_mem_notdirty calls tb_invalidate_phys_page_fast,
2792 * which can be called without the iothread mutex.
2794 memory_region_init_io(&io_mem_notdirty
, NULL
, ¬dirty_mem_ops
, NULL
,
2796 memory_region_clear_global_locking(&io_mem_notdirty
);
2798 memory_region_init_io(&io_mem_watch
, NULL
, &watch_mem_ops
, NULL
,
2802 AddressSpaceDispatch
*address_space_dispatch_new(FlatView
*fv
)
2804 AddressSpaceDispatch
*d
= g_new0(AddressSpaceDispatch
, 1);
2807 n
= dummy_section(&d
->map
, fv
, &io_mem_unassigned
);
2808 assert(n
== PHYS_SECTION_UNASSIGNED
);
2809 n
= dummy_section(&d
->map
, fv
, &io_mem_notdirty
);
2810 assert(n
== PHYS_SECTION_NOTDIRTY
);
2811 n
= dummy_section(&d
->map
, fv
, &io_mem_rom
);
2812 assert(n
== PHYS_SECTION_ROM
);
2813 n
= dummy_section(&d
->map
, fv
, &io_mem_watch
);
2814 assert(n
== PHYS_SECTION_WATCH
);
2816 d
->phys_map
= (PhysPageEntry
) { .ptr
= PHYS_MAP_NODE_NIL
, .skip
= 1 };
2821 void address_space_dispatch_free(AddressSpaceDispatch
*d
)
2823 phys_sections_free(&d
->map
);
2827 static void tcg_commit(MemoryListener
*listener
)
2829 CPUAddressSpace
*cpuas
;
2830 AddressSpaceDispatch
*d
;
2832 /* since each CPU stores ram addresses in its TLB cache, we must
2833 reset the modified entries */
2834 cpuas
= container_of(listener
, CPUAddressSpace
, tcg_as_listener
);
2835 cpu_reloading_memory_map();
2836 /* The CPU and TLB are protected by the iothread lock.
2837 * We reload the dispatch pointer now because cpu_reloading_memory_map()
2838 * may have split the RCU critical section.
2840 d
= address_space_to_dispatch(cpuas
->as
);
2841 atomic_rcu_set(&cpuas
->memory_dispatch
, d
);
2842 tlb_flush(cpuas
->cpu
);
2845 static void memory_map_init(void)
2847 system_memory
= g_malloc(sizeof(*system_memory
));
2849 memory_region_init(system_memory
, NULL
, "system", UINT64_MAX
);
2850 address_space_init(&address_space_memory
, system_memory
, "memory");
2852 system_io
= g_malloc(sizeof(*system_io
));
2853 memory_region_init_io(system_io
, NULL
, &unassigned_io_ops
, NULL
, "io",
2855 address_space_init(&address_space_io
, system_io
, "I/O");
2858 MemoryRegion
*get_system_memory(void)
2860 return system_memory
;
2863 MemoryRegion
*get_system_io(void)
2868 #endif /* !defined(CONFIG_USER_ONLY) */
2870 /* physical memory access (slow version, mainly for debug) */
2871 #if defined(CONFIG_USER_ONLY)
2872 int cpu_memory_rw_debug(CPUState
*cpu
, target_ulong addr
,
2873 uint8_t *buf
, int len
, int is_write
)
2880 page
= addr
& TARGET_PAGE_MASK
;
2881 l
= (page
+ TARGET_PAGE_SIZE
) - addr
;
2884 flags
= page_get_flags(page
);
2885 if (!(flags
& PAGE_VALID
))
2888 if (!(flags
& PAGE_WRITE
))
2890 /* XXX: this code should not depend on lock_user */
2891 if (!(p
= lock_user(VERIFY_WRITE
, addr
, l
, 0)))
2894 unlock_user(p
, addr
, l
);
2896 if (!(flags
& PAGE_READ
))
2898 /* XXX: this code should not depend on lock_user */
2899 if (!(p
= lock_user(VERIFY_READ
, addr
, l
, 1)))
2902 unlock_user(p
, addr
, 0);
2913 static void invalidate_and_set_dirty(MemoryRegion
*mr
, hwaddr addr
,
2916 uint8_t dirty_log_mask
= memory_region_get_dirty_log_mask(mr
);
2917 addr
+= memory_region_get_ram_addr(mr
);
2919 /* No early return if dirty_log_mask is or becomes 0, because
2920 * cpu_physical_memory_set_dirty_range will still call
2921 * xen_modified_memory.
2923 if (dirty_log_mask
) {
2925 cpu_physical_memory_range_includes_clean(addr
, length
, dirty_log_mask
);
2927 if (dirty_log_mask
& (1 << DIRTY_MEMORY_CODE
)) {
2928 assert(tcg_enabled());
2930 tb_invalidate_phys_range(addr
, addr
+ length
);
2932 dirty_log_mask
&= ~(1 << DIRTY_MEMORY_CODE
);
2934 cpu_physical_memory_set_dirty_range(addr
, length
, dirty_log_mask
);
2937 static int memory_access_size(MemoryRegion
*mr
, unsigned l
, hwaddr addr
)
2939 unsigned access_size_max
= mr
->ops
->valid
.max_access_size
;
2941 /* Regions are assumed to support 1-4 byte accesses unless
2942 otherwise specified. */
2943 if (access_size_max
== 0) {
2944 access_size_max
= 4;
2947 /* Bound the maximum access by the alignment of the address. */
2948 if (!mr
->ops
->impl
.unaligned
) {
2949 unsigned align_size_max
= addr
& -addr
;
2950 if (align_size_max
!= 0 && align_size_max
< access_size_max
) {
2951 access_size_max
= align_size_max
;
2955 /* Don't attempt accesses larger than the maximum. */
2956 if (l
> access_size_max
) {
2957 l
= access_size_max
;
2964 static bool prepare_mmio_access(MemoryRegion
*mr
)
2966 bool unlocked
= !qemu_mutex_iothread_locked();
2967 bool release_lock
= false;
2969 if (unlocked
&& mr
->global_locking
) {
2970 qemu_mutex_lock_iothread();
2972 release_lock
= true;
2974 if (mr
->flush_coalesced_mmio
) {
2976 qemu_mutex_lock_iothread();
2978 qemu_flush_coalesced_mmio_buffer();
2980 qemu_mutex_unlock_iothread();
2984 return release_lock
;
2987 /* Called within RCU critical section. */
2988 static MemTxResult
flatview_write_continue(FlatView
*fv
, hwaddr addr
,
2991 int len
, hwaddr addr1
,
2992 hwaddr l
, MemoryRegion
*mr
)
2996 MemTxResult result
= MEMTX_OK
;
2997 bool release_lock
= false;
3000 if (!memory_access_is_direct(mr
, true)) {
3001 release_lock
|= prepare_mmio_access(mr
);
3002 l
= memory_access_size(mr
, l
, addr1
);
3003 /* XXX: could force current_cpu to NULL to avoid
3007 /* 64 bit write access */
3009 result
|= memory_region_dispatch_write(mr
, addr1
, val
, 8,
3013 /* 32 bit write access */
3014 val
= (uint32_t)ldl_p(buf
);
3015 result
|= memory_region_dispatch_write(mr
, addr1
, val
, 4,
3019 /* 16 bit write access */
3021 result
|= memory_region_dispatch_write(mr
, addr1
, val
, 2,
3025 /* 8 bit write access */
3027 result
|= memory_region_dispatch_write(mr
, addr1
, val
, 1,
3035 ptr
= qemu_ram_ptr_length(mr
->ram_block
, addr1
, &l
, false);
3036 memcpy(ptr
, buf
, l
);
3037 invalidate_and_set_dirty(mr
, addr1
, l
);
3041 qemu_mutex_unlock_iothread();
3042 release_lock
= false;
3054 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, true);
3060 static MemTxResult
flatview_write(FlatView
*fv
, hwaddr addr
, MemTxAttrs attrs
,
3061 const uint8_t *buf
, int len
)
3066 MemTxResult result
= MEMTX_OK
;
3071 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, true);
3072 result
= flatview_write_continue(fv
, addr
, attrs
, buf
, len
,
3080 MemTxResult
address_space_write(AddressSpace
*as
, hwaddr addr
,
3082 const uint8_t *buf
, int len
)
3084 return flatview_write(address_space_to_flatview(as
), addr
, attrs
, buf
, len
);
3087 /* Called within RCU critical section. */
3088 MemTxResult
flatview_read_continue(FlatView
*fv
, hwaddr addr
,
3089 MemTxAttrs attrs
, uint8_t *buf
,
3090 int len
, hwaddr addr1
, hwaddr l
,
3095 MemTxResult result
= MEMTX_OK
;
3096 bool release_lock
= false;
3099 if (!memory_access_is_direct(mr
, false)) {
3101 release_lock
|= prepare_mmio_access(mr
);
3102 l
= memory_access_size(mr
, l
, addr1
);
3105 /* 64 bit read access */
3106 result
|= memory_region_dispatch_read(mr
, addr1
, &val
, 8,
3111 /* 32 bit read access */
3112 result
|= memory_region_dispatch_read(mr
, addr1
, &val
, 4,
3117 /* 16 bit read access */
3118 result
|= memory_region_dispatch_read(mr
, addr1
, &val
, 2,
3123 /* 8 bit read access */
3124 result
|= memory_region_dispatch_read(mr
, addr1
, &val
, 1,
3133 ptr
= qemu_ram_ptr_length(mr
->ram_block
, addr1
, &l
, false);
3134 memcpy(buf
, ptr
, l
);
3138 qemu_mutex_unlock_iothread();
3139 release_lock
= false;
3151 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, false);
3157 MemTxResult
flatview_read_full(FlatView
*fv
, hwaddr addr
,
3158 MemTxAttrs attrs
, uint8_t *buf
, int len
)
3163 MemTxResult result
= MEMTX_OK
;
3168 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, false);
3169 result
= flatview_read_continue(fv
, addr
, attrs
, buf
, len
,
3177 static MemTxResult
flatview_rw(FlatView
*fv
, hwaddr addr
, MemTxAttrs attrs
,
3178 uint8_t *buf
, int len
, bool is_write
)
3181 return flatview_write(fv
, addr
, attrs
, (uint8_t *)buf
, len
);
3183 return flatview_read(fv
, addr
, attrs
, (uint8_t *)buf
, len
);
3187 MemTxResult
address_space_rw(AddressSpace
*as
, hwaddr addr
,
3188 MemTxAttrs attrs
, uint8_t *buf
,
3189 int len
, bool is_write
)
3191 return flatview_rw(address_space_to_flatview(as
),
3192 addr
, attrs
, buf
, len
, is_write
);
3195 void cpu_physical_memory_rw(hwaddr addr
, uint8_t *buf
,
3196 int len
, int is_write
)
3198 address_space_rw(&address_space_memory
, addr
, MEMTXATTRS_UNSPECIFIED
,
3199 buf
, len
, is_write
);
3202 enum write_rom_type
{
3207 static inline void cpu_physical_memory_write_rom_internal(AddressSpace
*as
,
3208 hwaddr addr
, const uint8_t *buf
, int len
, enum write_rom_type type
)
3218 mr
= address_space_translate(as
, addr
, &addr1
, &l
, true);
3220 if (!(memory_region_is_ram(mr
) ||
3221 memory_region_is_romd(mr
))) {
3222 l
= memory_access_size(mr
, l
, addr1
);
3225 ptr
= qemu_map_ram_ptr(mr
->ram_block
, addr1
);
3228 memcpy(ptr
, buf
, l
);
3229 invalidate_and_set_dirty(mr
, addr1
, l
);
3232 flush_icache_range((uintptr_t)ptr
, (uintptr_t)ptr
+ l
);
3243 /* used for ROM loading : can write in RAM and ROM */
3244 void cpu_physical_memory_write_rom(AddressSpace
*as
, hwaddr addr
,
3245 const uint8_t *buf
, int len
)
3247 cpu_physical_memory_write_rom_internal(as
, addr
, buf
, len
, WRITE_DATA
);
3250 void cpu_flush_icache_range(hwaddr start
, int len
)
3253 * This function should do the same thing as an icache flush that was
3254 * triggered from within the guest. For TCG we are always cache coherent,
3255 * so there is no need to flush anything. For KVM / Xen we need to flush
3256 * the host's instruction cache at least.
3258 if (tcg_enabled()) {
3262 cpu_physical_memory_write_rom_internal(&address_space_memory
,
3263 start
, NULL
, len
, FLUSH_CACHE
);
3274 static BounceBuffer bounce
;
3276 typedef struct MapClient
{
3278 QLIST_ENTRY(MapClient
) link
;
3281 QemuMutex map_client_list_lock
;
3282 static QLIST_HEAD(map_client_list
, MapClient
) map_client_list
3283 = QLIST_HEAD_INITIALIZER(map_client_list
);
3285 static void cpu_unregister_map_client_do(MapClient
*client
)
3287 QLIST_REMOVE(client
, link
);
3291 static void cpu_notify_map_clients_locked(void)
3295 while (!QLIST_EMPTY(&map_client_list
)) {
3296 client
= QLIST_FIRST(&map_client_list
);
3297 qemu_bh_schedule(client
->bh
);
3298 cpu_unregister_map_client_do(client
);
3302 void cpu_register_map_client(QEMUBH
*bh
)
3304 MapClient
*client
= g_malloc(sizeof(*client
));
3306 qemu_mutex_lock(&map_client_list_lock
);
3308 QLIST_INSERT_HEAD(&map_client_list
, client
, link
);
3309 if (!atomic_read(&bounce
.in_use
)) {
3310 cpu_notify_map_clients_locked();
3312 qemu_mutex_unlock(&map_client_list_lock
);
3315 void cpu_exec_init_all(void)
3317 qemu_mutex_init(&ram_list
.mutex
);
3318 /* The data structures we set up here depend on knowing the page size,
3319 * so no more changes can be made after this point.
3320 * In an ideal world, nothing we did before we had finished the
3321 * machine setup would care about the target page size, and we could
3322 * do this much later, rather than requiring board models to state
3323 * up front what their requirements are.
3325 finalize_target_page_bits();
3328 qemu_mutex_init(&map_client_list_lock
);
3331 void cpu_unregister_map_client(QEMUBH
*bh
)
3335 qemu_mutex_lock(&map_client_list_lock
);
3336 QLIST_FOREACH(client
, &map_client_list
, link
) {
3337 if (client
->bh
== bh
) {
3338 cpu_unregister_map_client_do(client
);
3342 qemu_mutex_unlock(&map_client_list_lock
);
3345 static void cpu_notify_map_clients(void)
3347 qemu_mutex_lock(&map_client_list_lock
);
3348 cpu_notify_map_clients_locked();
3349 qemu_mutex_unlock(&map_client_list_lock
);
3352 static bool flatview_access_valid(FlatView
*fv
, hwaddr addr
, int len
,
3361 mr
= flatview_translate(fv
, addr
, &xlat
, &l
, is_write
);
3362 if (!memory_access_is_direct(mr
, is_write
)) {
3363 l
= memory_access_size(mr
, l
, addr
);
3364 if (!memory_region_access_valid(mr
, xlat
, l
, is_write
)) {
3377 bool address_space_access_valid(AddressSpace
*as
, hwaddr addr
,
3378 int len
, bool is_write
)
3380 return flatview_access_valid(address_space_to_flatview(as
),
3381 addr
, len
, is_write
);
3385 flatview_extend_translation(FlatView
*fv
, hwaddr addr
,
3387 MemoryRegion
*mr
, hwaddr base
, hwaddr len
,
3392 MemoryRegion
*this_mr
;
3398 if (target_len
== 0) {
3403 this_mr
= flatview_translate(fv
, addr
, &xlat
,
3405 if (this_mr
!= mr
|| xlat
!= base
+ done
) {
3411 /* Map a physical memory region into a host virtual address.
3412 * May map a subset of the requested range, given by and returned in *plen.
3413 * May return NULL if resources needed to perform the mapping are exhausted.
3414 * Use only for reads OR writes - not for read-modify-write operations.
3415 * Use cpu_register_map_client() to know when retrying the map operation is
3416 * likely to succeed.
3418 void *address_space_map(AddressSpace
*as
,
3427 FlatView
*fv
= address_space_to_flatview(as
);
3435 mr
= flatview_translate(fv
, addr
, &xlat
, &l
, is_write
);
3437 if (!memory_access_is_direct(mr
, is_write
)) {
3438 if (atomic_xchg(&bounce
.in_use
, true)) {
3442 /* Avoid unbounded allocations */
3443 l
= MIN(l
, TARGET_PAGE_SIZE
);
3444 bounce
.buffer
= qemu_memalign(TARGET_PAGE_SIZE
, l
);
3448 memory_region_ref(mr
);
3451 flatview_read(fv
, addr
, MEMTXATTRS_UNSPECIFIED
,
3457 return bounce
.buffer
;
3461 memory_region_ref(mr
);
3462 *plen
= flatview_extend_translation(fv
, addr
, len
, mr
, xlat
,
3464 ptr
= qemu_ram_ptr_length(mr
->ram_block
, xlat
, plen
, true);
3470 /* Unmaps a memory region previously mapped by address_space_map().
3471 * Will also mark the memory as dirty if is_write == 1. access_len gives
3472 * the amount of memory that was actually read or written by the caller.
3474 void address_space_unmap(AddressSpace
*as
, void *buffer
, hwaddr len
,
3475 int is_write
, hwaddr access_len
)
3477 if (buffer
!= bounce
.buffer
) {
3481 mr
= memory_region_from_host(buffer
, &addr1
);
3484 invalidate_and_set_dirty(mr
, addr1
, access_len
);
3486 if (xen_enabled()) {
3487 xen_invalidate_map_cache_entry(buffer
);
3489 memory_region_unref(mr
);
3493 address_space_write(as
, bounce
.addr
, MEMTXATTRS_UNSPECIFIED
,
3494 bounce
.buffer
, access_len
);
3496 qemu_vfree(bounce
.buffer
);
3497 bounce
.buffer
= NULL
;
3498 memory_region_unref(bounce
.mr
);
3499 atomic_mb_set(&bounce
.in_use
, false);
3500 cpu_notify_map_clients();
3503 void *cpu_physical_memory_map(hwaddr addr
,
3507 return address_space_map(&address_space_memory
, addr
, plen
, is_write
);
3510 void cpu_physical_memory_unmap(void *buffer
, hwaddr len
,
3511 int is_write
, hwaddr access_len
)
3513 return address_space_unmap(&address_space_memory
, buffer
, len
, is_write
, access_len
);
3516 #define ARG1_DECL AddressSpace *as
3519 #define TRANSLATE(...) address_space_translate(as, __VA_ARGS__)
3520 #define IS_DIRECT(mr, is_write) memory_access_is_direct(mr, is_write)
3521 #define MAP_RAM(mr, ofs) qemu_map_ram_ptr((mr)->ram_block, ofs)
3522 #define INVALIDATE(mr, ofs, len) invalidate_and_set_dirty(mr, ofs, len)
3523 #define RCU_READ_LOCK(...) rcu_read_lock()
3524 #define RCU_READ_UNLOCK(...) rcu_read_unlock()
3525 #include "memory_ldst.inc.c"
3527 int64_t address_space_cache_init(MemoryRegionCache
*cache
,
3539 void address_space_cache_invalidate(MemoryRegionCache
*cache
,
3545 void address_space_cache_destroy(MemoryRegionCache
*cache
)
3550 #define ARG1_DECL MemoryRegionCache *cache
3552 #define SUFFIX _cached
3553 #define TRANSLATE(addr, ...) \
3554 address_space_translate(cache->as, cache->xlat + (addr), __VA_ARGS__)
3555 #define IS_DIRECT(mr, is_write) true
3556 #define MAP_RAM(mr, ofs) qemu_map_ram_ptr((mr)->ram_block, ofs)
3557 #define INVALIDATE(mr, ofs, len) invalidate_and_set_dirty(mr, ofs, len)
3558 #define RCU_READ_LOCK() rcu_read_lock()
3559 #define RCU_READ_UNLOCK() rcu_read_unlock()
3560 #include "memory_ldst.inc.c"
3562 /* virtual memory access for debug (includes writing to ROM) */
3563 int cpu_memory_rw_debug(CPUState
*cpu
, target_ulong addr
,
3564 uint8_t *buf
, int len
, int is_write
)
3570 cpu_synchronize_state(cpu
);
3575 page
= addr
& TARGET_PAGE_MASK
;
3576 phys_addr
= cpu_get_phys_page_attrs_debug(cpu
, page
, &attrs
);
3577 asidx
= cpu_asidx_from_attrs(cpu
, attrs
);
3578 /* if no physical page mapped, return an error */
3579 if (phys_addr
== -1)
3581 l
= (page
+ TARGET_PAGE_SIZE
) - addr
;
3584 phys_addr
+= (addr
& ~TARGET_PAGE_MASK
);
3586 cpu_physical_memory_write_rom(cpu
->cpu_ases
[asidx
].as
,
3589 address_space_rw(cpu
->cpu_ases
[asidx
].as
, phys_addr
,
3590 MEMTXATTRS_UNSPECIFIED
,
3601 * Allows code that needs to deal with migration bitmaps etc to still be built
3602 * target independent.
3604 size_t qemu_target_page_size(void)
3606 return TARGET_PAGE_SIZE
;
3609 int qemu_target_page_bits(void)
3611 return TARGET_PAGE_BITS
;
3614 int qemu_target_page_bits_min(void)
3616 return TARGET_PAGE_BITS_MIN
;
3621 * A helper function for the _utterly broken_ virtio device model to find out if
3622 * it's running on a big endian machine. Don't do this at home kids!
3624 bool target_words_bigendian(void);
3625 bool target_words_bigendian(void)
3627 #if defined(TARGET_WORDS_BIGENDIAN)
3634 #ifndef CONFIG_USER_ONLY
3635 bool cpu_physical_memory_is_io(hwaddr phys_addr
)
3642 mr
= address_space_translate(&address_space_memory
,
3643 phys_addr
, &phys_addr
, &l
, false);
3645 res
= !(memory_region_is_ram(mr
) || memory_region_is_romd(mr
));
3650 int qemu_ram_foreach_block(RAMBlockIterFunc func
, void *opaque
)
3656 RAMBLOCK_FOREACH(block
) {
3657 ret
= func(block
->idstr
, block
->host
, block
->offset
,
3658 block
->used_length
, opaque
);
3668 * Unmap pages of memory from start to start+length such that
3669 * they a) read as 0, b) Trigger whatever fault mechanism
3670 * the OS provides for postcopy.
3671 * The pages must be unmapped by the end of the function.
3672 * Returns: 0 on success, none-0 on failure
3675 int ram_block_discard_range(RAMBlock
*rb
, uint64_t start
, size_t length
)
3679 uint8_t *host_startaddr
= rb
->host
+ start
;
3681 if ((uintptr_t)host_startaddr
& (rb
->page_size
- 1)) {
3682 error_report("ram_block_discard_range: Unaligned start address: %p",
3687 if ((start
+ length
) <= rb
->used_length
) {
3688 uint8_t *host_endaddr
= host_startaddr
+ length
;
3689 if ((uintptr_t)host_endaddr
& (rb
->page_size
- 1)) {
3690 error_report("ram_block_discard_range: Unaligned end address: %p",
3695 errno
= ENOTSUP
; /* If we are missing MADVISE etc */
3697 if (rb
->page_size
== qemu_host_page_size
) {
3698 #if defined(CONFIG_MADVISE)
3699 /* Note: We need the madvise MADV_DONTNEED behaviour of definitely
3702 ret
= madvise(host_startaddr
, length
, MADV_DONTNEED
);
3705 /* Huge page case - unfortunately it can't do DONTNEED, but
3706 * it can do the equivalent by FALLOC_FL_PUNCH_HOLE in the
3709 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
3710 ret
= fallocate(rb
->fd
, FALLOC_FL_PUNCH_HOLE
| FALLOC_FL_KEEP_SIZE
,
3716 error_report("ram_block_discard_range: Failed to discard range "
3717 "%s:%" PRIx64
" +%zx (%d)",
3718 rb
->idstr
, start
, length
, ret
);
3721 error_report("ram_block_discard_range: Overrun block '%s' (%" PRIu64
3722 "/%zx/" RAM_ADDR_FMT
")",
3723 rb
->idstr
, start
, length
, rb
->used_length
);
3732 void page_size_init(void)
3734 /* NOTE: we can always suppose that qemu_host_page_size >=
3736 if (qemu_host_page_size
== 0) {
3737 qemu_host_page_size
= qemu_real_host_page_size
;
3739 if (qemu_host_page_size
< TARGET_PAGE_SIZE
) {
3740 qemu_host_page_size
= TARGET_PAGE_SIZE
;
3742 qemu_host_page_mask
= -(intptr_t)qemu_host_page_size
;
3745 #if !defined(CONFIG_USER_ONLY)
3747 static void mtree_print_phys_entries(fprintf_function mon
, void *f
,
3748 int start
, int end
, int skip
, int ptr
)
3750 if (start
== end
- 1) {
3751 mon(f
, "\t%3d ", start
);
3753 mon(f
, "\t%3d..%-3d ", start
, end
- 1);
3755 mon(f
, " skip=%d ", skip
);
3756 if (ptr
== PHYS_MAP_NODE_NIL
) {
3759 mon(f
, " ptr=#%d", ptr
);
3761 mon(f
, " ptr=[%d]", ptr
);
3766 #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
3767 int128_sub((size), int128_one())) : 0)
3769 void mtree_print_dispatch(fprintf_function mon
, void *f
,
3770 AddressSpaceDispatch
*d
, MemoryRegion
*root
)
3774 mon(f
, " Dispatch\n");
3775 mon(f
, " Physical sections\n");
3777 for (i
= 0; i
< d
->map
.sections_nb
; ++i
) {
3778 MemoryRegionSection
*s
= d
->map
.sections
+ i
;
3779 const char *names
[] = { " [unassigned]", " [not dirty]",
3780 " [ROM]", " [watch]" };
3782 mon(f
, " #%d @" TARGET_FMT_plx
".." TARGET_FMT_plx
" %s%s%s%s%s",
3784 s
->offset_within_address_space
,
3785 s
->offset_within_address_space
+ MR_SIZE(s
->mr
->size
),
3786 s
->mr
->name
? s
->mr
->name
: "(noname)",
3787 i
< ARRAY_SIZE(names
) ? names
[i
] : "",
3788 s
->mr
== root
? " [ROOT]" : "",
3789 s
== d
->mru_section
? " [MRU]" : "",
3790 s
->mr
->is_iommu
? " [iommu]" : "");
3793 mon(f
, " alias=%s", s
->mr
->alias
->name
?
3794 s
->mr
->alias
->name
: "noname");
3799 mon(f
, " Nodes (%d bits per level, %d levels) ptr=[%d] skip=%d\n",
3800 P_L2_BITS
, P_L2_LEVELS
, d
->phys_map
.ptr
, d
->phys_map
.skip
);
3801 for (i
= 0; i
< d
->map
.nodes_nb
; ++i
) {
3804 Node
*n
= d
->map
.nodes
+ i
;
3806 mon(f
, " [%d]\n", i
);
3808 for (j
= 0, jprev
= 0, prev
= *n
[0]; j
< ARRAY_SIZE(*n
); ++j
) {
3809 PhysPageEntry
*pe
= *n
+ j
;
3811 if (pe
->ptr
== prev
.ptr
&& pe
->skip
== prev
.skip
) {
3815 mtree_print_phys_entries(mon
, f
, jprev
, j
, prev
.skip
, prev
.ptr
);
3821 if (jprev
!= ARRAY_SIZE(*n
)) {
3822 mtree_print_phys_entries(mon
, f
, jprev
, j
, prev
.skip
, prev
.ptr
);