target/microblaze/cpu.c

   1 /*
   2  * QEMU MicroBlaze CPU
   3  *
   4  * Copyright (c) 2009 Edgar E. Iglesias
   5  * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
   6  * Copyright (c) 2012 SUSE LINUX Products GmbH
   7  * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2.1 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see
  21  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "qemu/log.h"
  26 #include "qapi/error.h"
  27 #include "cpu.h"
  28 #include "qemu/module.h"
  29 #include "hw/qdev-properties.h"
  30 #include "exec/exec-all.h"
  31 #include "fpu/softfloat-helpers.h"
  32
  33 static const struct {
  34     const char *name;
  35     uint8_t version_id;
  36 } mb_cpu_lookup[] = {
  37     /* These key value are as per MBV field in PVR0 */
  38     {"5.00.a", 0x01},
  39     {"5.00.b", 0x02},
  40     {"5.00.c", 0x03},
  41     {"6.00.a", 0x04},
  42     {"6.00.b", 0x06},
  43     {"7.00.a", 0x05},
  44     {"7.00.b", 0x07},
  45     {"7.10.a", 0x08},
  46     {"7.10.b", 0x09},
  47     {"7.10.c", 0x0a},
  48     {"7.10.d", 0x0b},
  49     {"7.20.a", 0x0c},
  50     {"7.20.b", 0x0d},
  51     {"7.20.c", 0x0e},
  52     {"7.20.d", 0x0f},
  53     {"7.30.a", 0x10},
  54     {"7.30.b", 0x11},
  55     {"8.00.a", 0x12},
  56     {"8.00.b", 0x13},
  57     {"8.10.a", 0x14},
  58     {"8.20.a", 0x15},
  59     {"8.20.b", 0x16},
  60     {"8.30.a", 0x17},
  61     {"8.40.a", 0x18},
  62     {"8.40.b", 0x19},
  63     {"8.50.a", 0x1A},
  64     {"9.0", 0x1B},
  65     {"9.1", 0x1D},
  66     {"9.2", 0x1F},
  67     {"9.3", 0x20},
  68     {"9.4", 0x21},
  69     {"9.5", 0x22},
  70     {"9.6", 0x23},
  71     {"10.0", 0x24},
  72     {NULL, 0},
  73 };
  74
  75 /* If no specific version gets selected, default to the following.  */
  76 #define DEFAULT_CPU_VERSION "10.0"
  77
  78 static void mb_cpu_set_pc(CPUState *cs, vaddr value)
  79 {
  80     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
  81
  82     cpu->env.pc = value;
  83     /* Ensure D_FLAG and IMM_FLAG are clear for the new PC */
  84     cpu->env.iflags = 0;
  85 }
  86
  87 static void mb_cpu_synchronize_from_tb(CPUState *cs,
  88                                        const TranslationBlock *tb)
  89 {
  90     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
  91
  92     cpu->env.pc = tb->pc;
  93     cpu->env.iflags = tb->flags & IFLAGS_TB_MASK;
  94 }
  95
  96 static bool mb_cpu_has_work(CPUState *cs)
  97 {
  98     return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
  99 }
 100
 101 #ifndef CONFIG_USER_ONLY
 102 static void mb_cpu_ns_axi_dp(void *opaque, int irq, int level)
 103 {
 104     MicroBlazeCPU *cpu = opaque;
 105     bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DP_MASK;
 106
 107     cpu->ns_axi_dp = level & en;
 108 }
 109
 110 static void mb_cpu_ns_axi_ip(void *opaque, int irq, int level)
 111 {
 112     MicroBlazeCPU *cpu = opaque;
 113     bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IP_MASK;
 114
 115     cpu->ns_axi_ip = level & en;
 116 }
 117
 118 static void mb_cpu_ns_axi_dc(void *opaque, int irq, int level)
 119 {
 120     MicroBlazeCPU *cpu = opaque;
 121     bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DC_MASK;
 122
 123     cpu->ns_axi_dc = level & en;
 124 }
 125
 126 static void mb_cpu_ns_axi_ic(void *opaque, int irq, int level)
 127 {
 128     MicroBlazeCPU *cpu = opaque;
 129     bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IC_MASK;
 130
 131     cpu->ns_axi_ic = level & en;
 132 }
 133
 134 static void microblaze_cpu_set_irq(void *opaque, int irq, int level)
 135 {
 136     MicroBlazeCPU *cpu = opaque;
 137     CPUState *cs = CPU(cpu);
 138     int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
 139
 140     if (level) {
 141         cpu_interrupt(cs, type);
 142     } else {
 143         cpu_reset_interrupt(cs, type);
 144     }
 145 }
 146 #endif
 147
 148 static void mb_cpu_reset(DeviceState *dev)
 149 {
 150     CPUState *s = CPU(dev);
 151     MicroBlazeCPU *cpu = MICROBLAZE_CPU(s);
 152     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu);
 153     CPUMBState *env = &cpu->env;
 154
 155     mcc->parent_reset(dev);
 156
 157     memset(env, 0, offsetof(CPUMBState, end_reset_fields));
 158     env->res_addr = RES_ADDR_NONE;
 159
 160     /* Disable stack protector.  */
 161     env->shr = ~0;
 162
 163     env->pc = cpu->cfg.base_vectors;
 164
 165 #if defined(CONFIG_USER_ONLY)
 166     /* start in user mode with interrupts enabled.  */
 167     mb_cpu_write_msr(env, MSR_EE | MSR_IE | MSR_VM | MSR_UM);
 168 #else
 169     mb_cpu_write_msr(env, 0);
 170     mmu_init(&env->mmu);
 171 #endif
 172 }
 173
 174 static void mb_disas_set_info(CPUState *cpu, disassemble_info *info)
 175 {
 176     info->mach = bfd_arch_microblaze;
 177     info->print_insn = print_insn_microblaze;
 178 }
 179
 180 static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
 181 {
 182     CPUState *cs = CPU(dev);
 183     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
 184     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
 185     uint8_t version_code = 0;
 186     const char *version;
 187     int i = 0;
 188     Error *local_err = NULL;
 189
 190     cpu_exec_realizefn(cs, &local_err);
 191     if (local_err != NULL) {
 192         error_propagate(errp, local_err);
 193         return;
 194     }
 195
 196     if (cpu->cfg.addr_size < 32 || cpu->cfg.addr_size > 64) {
 197         error_setg(errp, "addr-size %d is out of range (32 - 64)",
 198                    cpu->cfg.addr_size);
 199         return;
 200     }
 201
 202     qemu_init_vcpu(cs);
 203
 204     version = cpu->cfg.version ? cpu->cfg.version : DEFAULT_CPU_VERSION;
 205     for (i = 0; mb_cpu_lookup[i].name && version; i++) {
 206         if (strcmp(mb_cpu_lookup[i].name, version) == 0) {
 207             version_code = mb_cpu_lookup[i].version_id;
 208             break;
 209         }
 210     }
 211
 212     if (!version_code) {
 213         qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version);
 214     }
 215
 216     cpu->cfg.pvr_regs[0] =
 217         (PVR0_USE_EXC_MASK |
 218          PVR0_USE_ICACHE_MASK |
 219          PVR0_USE_DCACHE_MASK |
 220          (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
 221          (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
 222          (cpu->cfg.use_hw_mul ? PVR0_USE_HW_MUL_MASK : 0) |
 223          (cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) |
 224          (cpu->cfg.use_div ? PVR0_USE_DIV_MASK : 0) |
 225          (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
 226          (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
 227          (version_code << PVR0_VERSION_SHIFT) |
 228          (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0) |
 229          cpu->cfg.pvr_user1);
 230
 231     cpu->cfg.pvr_regs[1] = cpu->cfg.pvr_user2;
 232
 233     cpu->cfg.pvr_regs[2] =
 234         (PVR2_D_OPB_MASK |
 235          PVR2_D_LMB_MASK |
 236          PVR2_I_OPB_MASK |
 237          PVR2_I_LMB_MASK |
 238          PVR2_FPU_EXC_MASK |
 239          (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
 240          (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) |
 241          (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) |
 242          (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) |
 243          (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) |
 244          (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) |
 245          (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) |
 246          (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0) |
 247          (cpu->cfg.dopb_bus_exception ? PVR2_DOPB_BUS_EXC_MASK : 0) |
 248          (cpu->cfg.iopb_bus_exception ? PVR2_IOPB_BUS_EXC_MASK : 0) |
 249          (cpu->cfg.div_zero_exception ? PVR2_DIV_ZERO_EXC_MASK : 0) |
 250          (cpu->cfg.illegal_opcode_exception ? PVR2_ILL_OPCODE_EXC_MASK : 0) |
 251          (cpu->cfg.unaligned_exceptions ? PVR2_UNALIGNED_EXC_MASK : 0) |
 252          (cpu->cfg.opcode_0_illegal ? PVR2_OPCODE_0x0_ILL_MASK : 0));
 253
 254     cpu->cfg.pvr_regs[5] |=
 255         cpu->cfg.dcache_writeback ? PVR5_DCACHE_WRITEBACK_MASK : 0;
 256
 257     cpu->cfg.pvr_regs[10] =
 258         (0x0c000000 | /* Default to spartan 3a dsp family.  */
 259          (cpu->cfg.addr_size - 32) << PVR10_ASIZE_SHIFT);
 260
 261     cpu->cfg.pvr_regs[11] = ((cpu->cfg.use_mmu ? PVR11_USE_MMU : 0) |
 262                              16 << 17);
 263
 264     cpu->cfg.mmu = 3;
 265     cpu->cfg.mmu_tlb_access = 3;
 266     cpu->cfg.mmu_zones = 16;
 267     cpu->cfg.addr_mask = MAKE_64BIT_MASK(0, cpu->cfg.addr_size);
 268
 269     mcc->parent_realize(dev, errp);
 270 }
 271
 272 static void mb_cpu_initfn(Object *obj)
 273 {
 274     MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj);
 275     CPUMBState *env = &cpu->env;
 276
 277     cpu_set_cpustate_pointers(cpu);
 278
 279     set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
 280
 281 #ifndef CONFIG_USER_ONLY
 282     /* Inbound IRQ and FIR lines */
 283     qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2);
 284     qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dp, "ns_axi_dp", 1);
 285     qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ip, "ns_axi_ip", 1);
 286     qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dc, "ns_axi_dc", 1);
 287     qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ic, "ns_axi_ic", 1);
 288 #endif
 289 }
 290
 291 static Property mb_properties[] = {
 292     DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0),
 293     DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot,
 294                      false),
 295     /*
 296      * This is the C_ADDR_SIZE synth-time configuration option of the
 297      * MicroBlaze cores. Supported values range between 32 and 64.
 298      *
 299      * When set to > 32, 32bit MicroBlaze can emit load/stores
 300      * with extended addressing.
 301      */
 302     DEFINE_PROP_UINT8("addr-size", MicroBlazeCPU, cfg.addr_size, 32),
 303     /* If use-fpu > 0 - FPU is enabled
 304      * If use-fpu = 2 - Floating point conversion and square root instructions
 305      *                  are enabled
 306      */
 307     DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
 308     /* If use-hw-mul > 0 - Multiplier is enabled
 309      * If use-hw-mul = 2 - 64-bit multiplier is enabled
 310      */
 311     DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU, cfg.use_hw_mul, 2),
 312     DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true),
 313     DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true),
 314     DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true),
 315     DEFINE_PROP_BOOL("use-pcmp-instr", MicroBlazeCPU, cfg.use_pcmp_instr, true),
 316     DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
 317     /*
 318      * use-non-secure enables/disables the use of the non_secure[3:0] signals.
 319      * It is a bitfield where 1 = non-secure for the following bits and their
 320      * corresponding interfaces:
 321      * 0x1 - M_AXI_DP
 322      * 0x2 - M_AXI_IP
 323      * 0x4 - M_AXI_DC
 324      * 0x8 - M_AXI_IC
 325      */
 326     DEFINE_PROP_UINT8("use-non-secure", MicroBlazeCPU, cfg.use_non_secure, 0),
 327     DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
 328                      false),
 329     DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
 330     /* Enables bus exceptions on failed data accesses (load/stores).  */
 331     DEFINE_PROP_BOOL("dopb-bus-exception", MicroBlazeCPU,
 332                      cfg.dopb_bus_exception, false),
 333     /* Enables bus exceptions on failed instruction fetches.  */
 334     DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU,
 335                      cfg.iopb_bus_exception, false),
 336     DEFINE_PROP_BOOL("ill-opcode-exception", MicroBlazeCPU,
 337                      cfg.illegal_opcode_exception, false),
 338     DEFINE_PROP_BOOL("div-zero-exception", MicroBlazeCPU,
 339                      cfg.div_zero_exception, false),
 340     DEFINE_PROP_BOOL("unaligned-exceptions", MicroBlazeCPU,
 341                      cfg.unaligned_exceptions, false),
 342     DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
 343                      cfg.opcode_0_illegal, false),
 344     DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
 345     DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
 346     DEFINE_PROP_UINT8("pvr-user1", MicroBlazeCPU, cfg.pvr_user1, 0),
 347     DEFINE_PROP_UINT32("pvr-user2", MicroBlazeCPU, cfg.pvr_user2, 0),
 348     DEFINE_PROP_END_OF_LIST(),
 349 };
 350
 351 static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
 352 {
 353     return object_class_by_name(TYPE_MICROBLAZE_CPU);
 354 }
 355
 356 #ifndef CONFIG_USER_ONLY
 357 #include "hw/core/sysemu-cpu-ops.h"
 358
 359 static const struct SysemuCPUOps mb_sysemu_ops = {
 360     .get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug,
 361 };
 362 #endif
 363
 364 #include "hw/core/tcg-cpu-ops.h"
 365
 366 static const struct TCGCPUOps mb_tcg_ops = {
 367     .initialize = mb_tcg_init,
 368     .synchronize_from_tb = mb_cpu_synchronize_from_tb,
 369
 370 #ifndef CONFIG_USER_ONLY
 371     .tlb_fill = mb_cpu_tlb_fill,
 372     .cpu_exec_interrupt = mb_cpu_exec_interrupt,
 373     .do_interrupt = mb_cpu_do_interrupt,
 374     .do_transaction_failed = mb_cpu_transaction_failed,
 375     .do_unaligned_access = mb_cpu_do_unaligned_access,
 376 #endif /* !CONFIG_USER_ONLY */
 377 };
 378
 379 static void mb_cpu_class_init(ObjectClass *oc, void *data)
 380 {
 381     DeviceClass *dc = DEVICE_CLASS(oc);
 382     CPUClass *cc = CPU_CLASS(oc);
 383     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
 384
 385     device_class_set_parent_realize(dc, mb_cpu_realizefn,
 386                                     &mcc->parent_realize);
 387     device_class_set_parent_reset(dc, mb_cpu_reset, &mcc->parent_reset);
 388
 389     cc->class_by_name = mb_cpu_class_by_name;
 390     cc->has_work = mb_cpu_has_work;
 391
 392     cc->dump_state = mb_cpu_dump_state;
 393     cc->set_pc = mb_cpu_set_pc;
 394     cc->gdb_read_register = mb_cpu_gdb_read_register;
 395     cc->gdb_write_register = mb_cpu_gdb_write_register;
 396
 397 #ifndef CONFIG_USER_ONLY
 398     dc->vmsd = &vmstate_mb_cpu;
 399     cc->sysemu_ops = &mb_sysemu_ops;
 400 #endif
 401     device_class_set_props(dc, mb_properties);
 402     cc->gdb_num_core_regs = 32 + 27;
 403
 404     cc->disas_set_info = mb_disas_set_info;
 405     cc->tcg_ops = &mb_tcg_ops;
 406 }
 407
 408 static const TypeInfo mb_cpu_type_info = {
 409     .name = TYPE_MICROBLAZE_CPU,
 410     .parent = TYPE_CPU,
 411     .instance_size = sizeof(MicroBlazeCPU),
 412     .instance_init = mb_cpu_initfn,
 413     .class_size = sizeof(MicroBlazeCPUClass),
 414     .class_init = mb_cpu_class_init,
 415 };
 416
 417 static void mb_cpu_register_types(void)
 418 {
 419     type_register_static(&mb_cpu_type_info);
 420 }
 421
 422 type_init(mb_cpu_register_types)