4 * Copyright (c) 2012 Jia Liu <proljc@gmail.com>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
22 #include "qemu/qemu-print.h"
24 #include "exec/exec-all.h"
25 #include "fpu/softfloat-helpers.h"
28 static void openrisc_cpu_set_pc(CPUState
*cs
, vaddr value
)
30 OpenRISCCPU
*cpu
= OPENRISC_CPU(cs
);
36 static vaddr
openrisc_cpu_get_pc(CPUState
*cs
)
38 OpenRISCCPU
*cpu
= OPENRISC_CPU(cs
);
43 static void openrisc_cpu_synchronize_from_tb(CPUState
*cs
,
44 const TranslationBlock
*tb
)
46 OpenRISCCPU
*cpu
= OPENRISC_CPU(cs
);
48 tcg_debug_assert(!(cs
->tcg_cflags
& CF_PCREL
));
52 static void openrisc_restore_state_to_opc(CPUState
*cs
,
53 const TranslationBlock
*tb
,
56 OpenRISCCPU
*cpu
= OPENRISC_CPU(cs
);
58 cpu
->env
.pc
= data
[0];
59 cpu
->env
.dflag
= data
[1] & 1;
61 cpu
->env
.ppc
= cpu
->env
.pc
- 4;
65 static bool openrisc_cpu_has_work(CPUState
*cs
)
67 return cs
->interrupt_request
& (CPU_INTERRUPT_HARD
|
71 static void openrisc_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
73 info
->print_insn
= print_insn_or1k
;
76 static void openrisc_cpu_reset_hold(Object
*obj
)
78 CPUState
*s
= CPU(obj
);
79 OpenRISCCPU
*cpu
= OPENRISC_CPU(s
);
80 OpenRISCCPUClass
*occ
= OPENRISC_CPU_GET_CLASS(cpu
);
82 if (occ
->parent_phases
.hold
) {
83 occ
->parent_phases
.hold(obj
);
86 memset(&cpu
->env
, 0, offsetof(CPUOpenRISCState
, end_reset_fields
));
89 cpu
->env
.sr
= SR_FO
| SR_SM
;
90 cpu
->env
.lock_addr
= -1;
91 s
->exception_index
= -1;
92 cpu_set_fpcsr(&cpu
->env
, 0);
94 set_float_detect_tininess(float_tininess_before_rounding
,
97 #ifndef CONFIG_USER_ONLY
98 cpu
->env
.picmr
= 0x00000000;
99 cpu
->env
.picsr
= 0x00000000;
101 cpu
->env
.ttmr
= 0x00000000;
105 #ifndef CONFIG_USER_ONLY
106 static void openrisc_cpu_set_irq(void *opaque
, int irq
, int level
)
108 OpenRISCCPU
*cpu
= (OpenRISCCPU
*)opaque
;
109 CPUState
*cs
= CPU(cpu
);
112 if (irq
> 31 || irq
< 0) {
119 cpu
->env
.picsr
|= irq_bit
;
121 cpu
->env
.picsr
&= ~irq_bit
;
124 if (cpu
->env
.picsr
& cpu
->env
.picmr
) {
125 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
127 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
132 static void openrisc_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
134 CPUState
*cs
= CPU(dev
);
135 OpenRISCCPUClass
*occ
= OPENRISC_CPU_GET_CLASS(dev
);
136 Error
*local_err
= NULL
;
138 cpu_exec_realizefn(cs
, &local_err
);
139 if (local_err
!= NULL
) {
140 error_propagate(errp
, local_err
);
147 occ
->parent_realize(dev
, errp
);
150 static void openrisc_cpu_initfn(Object
*obj
)
152 #ifndef CONFIG_USER_ONLY
153 qdev_init_gpio_in_named(DEVICE(obj
), openrisc_cpu_set_irq
, "IRQ", NR_IRQS
);
159 static ObjectClass
*openrisc_cpu_class_by_name(const char *cpu_model
)
164 typename
= g_strdup_printf(OPENRISC_CPU_TYPE_NAME("%s"), cpu_model
);
165 oc
= object_class_by_name(typename
);
167 if (oc
!= NULL
&& !object_class_dynamic_cast(oc
, TYPE_OPENRISC_CPU
)) {
173 static void or1200_initfn(Object
*obj
)
175 OpenRISCCPU
*cpu
= OPENRISC_CPU(obj
);
177 cpu
->env
.vr
= 0x13000008;
178 cpu
->env
.upr
= UPR_UP
| UPR_DMP
| UPR_IMP
| UPR_PICP
| UPR_TTP
| UPR_PMP
;
179 cpu
->env
.cpucfgr
= CPUCFGR_NSGF
| CPUCFGR_OB32S
| CPUCFGR_OF32S
|
182 /* 1Way, TLB_SIZE entries. */
183 cpu
->env
.dmmucfgr
= (DMMUCFGR_NTW
& (0 << 2))
184 | (DMMUCFGR_NTS
& (ctz32(TLB_SIZE
) << 2));
185 cpu
->env
.immucfgr
= (IMMUCFGR_NTW
& (0 << 2))
186 | (IMMUCFGR_NTS
& (ctz32(TLB_SIZE
) << 2));
189 static void openrisc_any_initfn(Object
*obj
)
191 OpenRISCCPU
*cpu
= OPENRISC_CPU(obj
);
193 cpu
->env
.vr
= 0x13000040; /* Obsolete VER + UVRP for new SPRs */
194 cpu
->env
.vr2
= 0; /* No version specific id */
195 cpu
->env
.avr
= 0x01030000; /* Architecture v1.3 */
197 cpu
->env
.upr
= UPR_UP
| UPR_DMP
| UPR_IMP
| UPR_PICP
| UPR_TTP
| UPR_PMP
;
198 cpu
->env
.cpucfgr
= CPUCFGR_NSGF
| CPUCFGR_OB32S
| CPUCFGR_OF32S
|
199 CPUCFGR_AVRP
| CPUCFGR_EVBARP
| CPUCFGR_OF64A32S
;
201 /* 1Way, TLB_SIZE entries. */
202 cpu
->env
.dmmucfgr
= (DMMUCFGR_NTW
& (0 << 2))
203 | (DMMUCFGR_NTS
& (ctz32(TLB_SIZE
) << 2));
204 cpu
->env
.immucfgr
= (IMMUCFGR_NTW
& (0 << 2))
205 | (IMMUCFGR_NTS
& (ctz32(TLB_SIZE
) << 2));
208 #ifndef CONFIG_USER_ONLY
209 #include "hw/core/sysemu-cpu-ops.h"
211 static const struct SysemuCPUOps openrisc_sysemu_ops
= {
212 .get_phys_page_debug
= openrisc_cpu_get_phys_page_debug
,
216 #include "hw/core/tcg-cpu-ops.h"
218 static const struct TCGCPUOps openrisc_tcg_ops
= {
219 .initialize
= openrisc_translate_init
,
220 .synchronize_from_tb
= openrisc_cpu_synchronize_from_tb
,
221 .restore_state_to_opc
= openrisc_restore_state_to_opc
,
223 #ifndef CONFIG_USER_ONLY
224 .tlb_fill
= openrisc_cpu_tlb_fill
,
225 .cpu_exec_interrupt
= openrisc_cpu_exec_interrupt
,
226 .do_interrupt
= openrisc_cpu_do_interrupt
,
227 #endif /* !CONFIG_USER_ONLY */
230 static void openrisc_cpu_class_init(ObjectClass
*oc
, void *data
)
232 OpenRISCCPUClass
*occ
= OPENRISC_CPU_CLASS(oc
);
233 CPUClass
*cc
= CPU_CLASS(occ
);
234 DeviceClass
*dc
= DEVICE_CLASS(oc
);
235 ResettableClass
*rc
= RESETTABLE_CLASS(oc
);
237 device_class_set_parent_realize(dc
, openrisc_cpu_realizefn
,
238 &occ
->parent_realize
);
239 resettable_class_set_parent_phases(rc
, NULL
, openrisc_cpu_reset_hold
, NULL
,
240 &occ
->parent_phases
);
242 cc
->class_by_name
= openrisc_cpu_class_by_name
;
243 cc
->has_work
= openrisc_cpu_has_work
;
244 cc
->dump_state
= openrisc_cpu_dump_state
;
245 cc
->set_pc
= openrisc_cpu_set_pc
;
246 cc
->get_pc
= openrisc_cpu_get_pc
;
247 cc
->gdb_read_register
= openrisc_cpu_gdb_read_register
;
248 cc
->gdb_write_register
= openrisc_cpu_gdb_write_register
;
249 #ifndef CONFIG_USER_ONLY
250 dc
->vmsd
= &vmstate_openrisc_cpu
;
251 cc
->sysemu_ops
= &openrisc_sysemu_ops
;
253 cc
->gdb_num_core_regs
= 32 + 3;
254 cc
->disas_set_info
= openrisc_disas_set_info
;
255 cc
->tcg_ops
= &openrisc_tcg_ops
;
258 /* Sort alphabetically by type name, except for "any". */
259 static gint
openrisc_cpu_list_compare(gconstpointer a
, gconstpointer b
)
261 ObjectClass
*class_a
= (ObjectClass
*)a
;
262 ObjectClass
*class_b
= (ObjectClass
*)b
;
263 const char *name_a
, *name_b
;
265 name_a
= object_class_get_name(class_a
);
266 name_b
= object_class_get_name(class_b
);
267 if (strcmp(name_a
, "any-" TYPE_OPENRISC_CPU
) == 0) {
269 } else if (strcmp(name_b
, "any-" TYPE_OPENRISC_CPU
) == 0) {
272 return strcmp(name_a
, name_b
);
276 static void openrisc_cpu_list_entry(gpointer data
, gpointer user_data
)
278 ObjectClass
*oc
= data
;
279 const char *typename
;
282 typename
= object_class_get_name(oc
);
283 name
= g_strndup(typename
,
284 strlen(typename
) - strlen("-" TYPE_OPENRISC_CPU
));
285 qemu_printf(" %s\n", name
);
289 void cpu_openrisc_list(void)
293 list
= object_class_get_list(TYPE_OPENRISC_CPU
, false);
294 list
= g_slist_sort(list
, openrisc_cpu_list_compare
);
295 qemu_printf("Available CPUs:\n");
296 g_slist_foreach(list
, openrisc_cpu_list_entry
, NULL
);
300 #define DEFINE_OPENRISC_CPU_TYPE(cpu_model, initfn) \
302 .parent = TYPE_OPENRISC_CPU, \
303 .instance_init = initfn, \
304 .name = OPENRISC_CPU_TYPE_NAME(cpu_model), \
307 static const TypeInfo openrisc_cpus_type_infos
[] = {
308 { /* base class should be registered first */
309 .name
= TYPE_OPENRISC_CPU
,
311 .instance_size
= sizeof(OpenRISCCPU
),
312 .instance_align
= __alignof(OpenRISCCPU
),
313 .instance_init
= openrisc_cpu_initfn
,
315 .class_size
= sizeof(OpenRISCCPUClass
),
316 .class_init
= openrisc_cpu_class_init
,
318 DEFINE_OPENRISC_CPU_TYPE("or1200", or1200_initfn
),
319 DEFINE_OPENRISC_CPU_TYPE("any", openrisc_any_initfn
),
322 DEFINE_TYPES(openrisc_cpus_type_infos
)