2 # HPPA instruction decode definitions.
4 # Copyright (c) 2018 Richard Henderson <rth@twiddle.net>
6 # This library is free software; you can redistribute it and/or
7 # modify it under the terms of the GNU Lesser General Public
8 # License as published by the Free Software Foundation; either
9 # version 2.1 of the License, or (at your option) any later version.
11 # This library is distributed in the hope that it will be useful,
12 # but WITHOUT ANY WARRANTY; without even the implied warranty of
13 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 # Lesser General Public License for more details.
16 # You should have received a copy of the GNU Lesser General Public
17 # License along with this library; if not, see <http://www.gnu.org/licenses/>.
24 %assemble_sr3 13:1 14:2
25 %assemble_sr3x 13:1 14:2 !function=expand_sr3x
27 %assemble_11a 0:s1 4:10 !function=expand_shl3
28 %assemble_12 0:s1 2:1 3:10 !function=expand_shl2
29 %assemble_12a 0:s1 3:11 !function=expand_shl2
30 %assemble_17 0:s1 16:5 2:1 3:10 !function=expand_shl2
31 %assemble_22 0:s1 16:10 2:1 3:10 !function=expand_shl2
33 %assemble_21 0:s1 1:11 14:2 16:5 12:2 !function=expand_shl11
38 %sm_imm 16:10 !function=expand_sm_imm
49 %len5 0:5 !function=assemble_6
50 %len6_8 8:1 0:5 !function=assemble_6
51 %len6_12 12:1 0:5 !function=assemble_6
53 %ma_to_m 5:1 13:1 !function=ma_to_m
54 %ma2_to_m 2:2 !function=ma_to_m
55 %pos_to_m 0:1 !function=pos_to_m
56 %neg_to_m 0:1 !function=neg_to_m
57 %a_to_m 2:1 !function=neg_to_m
58 %cmpbid_c 13:2 !function=cmpbid_c
61 # Argument set definitions
64 # All insns that need to form a virtual address should use this set.
65 &ldst t b x disp sp m scale size
70 &rrr_cf_d t r1 r2 cf d
72 &rrr_cf_d_sh t r1 r2 cf d sh
77 &rrb_c_f disp n c f r1 r2
78 &rrb_c_d_f disp n c d f r1 r2
79 &rib_c_f disp n c f r i
80 &rib_c_d_f disp n c d f r i
86 @rr_cf_d ...... r:5 ..... cf:4 ...... d:1 t:5 &rr_cf_d
87 @rrr ...... r2:5 r1:5 .... ....... t:5 &rrr
88 @rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf
89 @rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d
90 @rrr_sh ...... r2:5 r1:5 ........ sh:2 . t:5 &rrr_sh
91 @rrr_cf_d_sh ...... r2:5 r1:5 cf:4 .... sh:2 d:1 t:5 &rrr_cf_d_sh
92 @rrr_cf_d_sh0 ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d_sh sh=0
93 @rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=%lowsign_11
94 @rri_cf_d ...... r:5 t:5 cf:4 d:1 ........... &rri_cf_d i=%lowsign_11
96 @rrb_cf ...... r2:5 r1:5 c:3 ........... n:1 . \
97 &rrb_c_f disp=%assemble_12
98 @rrb_cdf ...... r2:5 r1:5 c:3 ........... n:1 . \
99 &rrb_c_d_f disp=%assemble_12
100 @rib_cf ...... r:5 ..... c:3 ........... n:1 . \
101 &rib_c_f disp=%assemble_12 i=%im5_16
102 @rib_cdf ...... r:5 ..... c:3 ........... n:1 . \
103 &rib_c_d_f disp=%assemble_12 i=%im5_16
109 break 000000 ----- ----- --- 00000000 -----
111 mtsp 000000 ----- r:5 ... 11000001 00000 sp=%assemble_sr3
112 mtctl 000000 t:5 r:5 --- 11000010 00000
113 mtsarcm 000000 01011 r:5 --- 11000110 00000
114 mtsm 000000 00000 r:5 000 11000011 00000
116 mfia 000000 ----- 00000 --- 10100101 t:5
117 mfsp 000000 ----- 00000 ... 00100101 t:5 sp=%assemble_sr3
118 mfctl 000000 r:5 00000- e:1 -01000101 t:5
120 sync 000000 ----- ----- 000 00100000 00000 # sync, syncdma
122 ldsid 000000 b:5 ----- sp:2 0 10000101 t:5
124 rsm 000000 .......... 000 01110011 t:5 i=%sm_imm
125 ssm 000000 .......... 000 01101011 t:5 i=%sm_imm
127 rfi 000000 ----- ----- --- 01100000 00000
128 rfi_r 000000 ----- ----- --- 01100101 00000
130 # These are artificial instructions used by QEMU firmware.
131 # They are allocated from the unassigned instruction space.
132 halt 1111 1111 1111 1101 1110 1010 1101 0000
133 reset 1111 1111 1111 1101 1110 1010 1101 0001
134 getshadowregs 1111 1111 1111 1101 1110 1010 1101 0010
140 @addrx ...... b:5 x:5 .. ........ m:1 ..... \
141 &ldst disp=0 scale=0 t=0 sp=0 size=0
143 nop 000001 ----- ----- -- 11001010 0 ----- # fdc, disp
144 nop_addrx 000001 ..... ..... -- 01001010 . ----- @addrx # fdc, index
145 nop_addrx 000001 ..... ..... -- 01001011 . ----- @addrx # fdce
146 nop_addrx 000001 ..... ..... --- 0001010 . ----- @addrx # fic 0x0a
147 nop_addrx 000001 ..... ..... -- 01001111 . 00000 @addrx # fic 0x4f
148 nop_addrx 000001 ..... ..... --- 0001011 . ----- @addrx # fice
149 nop_addrx 000001 ..... ..... -- 01001110 . 00000 @addrx # pdc
151 probe 000001 b:5 ri:5 sp:2 imm:1 100011 write:1 0 t:5
153 # pa1.x tlb insert instructions
154 ixtlbx 000001 b:5 r:5 sp:2 0100000 addr:1 0 00000 data=1
155 ixtlbx 000001 b:5 r:5 ... 000000 addr:1 0 00000 \
156 sp=%assemble_sr3x data=0
158 # pcxl and pcxl2 Fast TLB Insert instructions
159 ixtlbxf 000001 00000 r:5 00 0 data:1 01000 addr:1 0 00000
161 # pa2.0 tlb insert idtlbt and iitlbt instructions
162 ixtlbt 000001 r2:5 r1:5 000 data:1 100000 0 00000 # idtlbt
165 pxtlb 000001 b:5 x:5 sp:2 01001000 m:1 ----- \
166 &ldst disp=0 scale=0 size=0 t=0
167 pxtlb 000001 b:5 x:5 ... 0001000 m:1 ----- \
168 &ldst disp=0 scale=0 size=0 t=0 sp=%assemble_sr3x
171 pxtlb_l 000001 b:5 x:5 sp:2 01011000 m:1 ----- \
172 &ldst disp=0 scale=0 size=0 t=0
173 pxtlb_l 000001 b:5 x:5 ... 0011000 m:1 ----- \
174 &ldst disp=0 scale=0 size=0 t=0 sp=%assemble_sr3x
177 pxtlbe 000001 b:5 x:5 sp:2 01001001 m:1 ----- \
178 &ldst disp=0 scale=0 size=0 t=0
179 pxtlbe 000001 b:5 x:5 ... 0001001 m:1 ----- \
180 &ldst disp=0 scale=0 size=0 t=0 sp=%assemble_sr3x
182 lpa 000001 b:5 x:5 sp:2 01001101 m:1 t:5 \
183 &ldst disp=0 scale=0 size=0
185 lci 000001 ----- ----- -- 01001100 0 t:5
191 andcm 000010 ..... ..... .... 000000 . ..... @rrr_cf_d
192 and 000010 ..... ..... .... 001000 . ..... @rrr_cf_d
193 or 000010 ..... ..... .... 001001 . ..... @rrr_cf_d
194 xor 000010 ..... ..... .... 001010 . ..... @rrr_cf_d
195 uxor 000010 ..... ..... .... 001110 . ..... @rrr_cf_d
196 ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf
197 cmpclr 000010 ..... ..... .... 100010 . ..... @rrr_cf_d
198 uaddcm 000010 ..... ..... .... 100110 . ..... @rrr_cf_d
199 uaddcm_tc 000010 ..... ..... .... 100111 . ..... @rrr_cf_d
200 dcor 000010 ..... 00000 .... 101110 . ..... @rr_cf_d
201 dcor_i 000010 ..... 00000 .... 101111 . ..... @rr_cf_d
203 add 000010 ..... ..... .... 0110.. . ..... @rrr_cf_d_sh
204 add_l 000010 ..... ..... .... 1010.. . ..... @rrr_cf_d_sh
205 add_tsv 000010 ..... ..... .... 1110.. . ..... @rrr_cf_d_sh
207 add_c 000010 ..... ..... .... 011100 . ..... @rrr_cf_d_sh0
208 hshladd 000010 ..... ..... 0000 0111.. 0 ..... @rrr_sh
210 add_c_tsv 000010 ..... ..... .... 111100 . ..... @rrr_cf_d_sh0
212 sub 000010 ..... ..... .... 010000 . ..... @rrr_cf_d
213 sub_tsv 000010 ..... ..... .... 110000 . ..... @rrr_cf_d
214 sub_tc 000010 ..... ..... .... 010011 . ..... @rrr_cf_d
215 sub_tsv_tc 000010 ..... ..... .... 110011 . ..... @rrr_cf_d
217 sub_b 000010 ..... ..... .... 010100 . ..... @rrr_cf_d
218 hshradd 000010 ..... ..... 0000 0101.. 0 ..... @rrr_sh
220 sub_b_tsv 000010 ..... ..... .... 110100 . ..... @rrr_cf_d
222 ldil 001000 t:5 ..................... i=%assemble_21
223 addil 001010 r:5 ..................... i=%assemble_21
224 ldo 001101 b:5 t:5 -- .............. i=%lowsign_14
226 addi 101101 ..... ..... .... 0 ........... @rri_cf
227 addi_tsv 101101 ..... ..... .... 1 ........... @rri_cf
228 addi_tc 101100 ..... ..... .... 0 ........... @rri_cf
229 addi_tc_tsv 101100 ..... ..... .... 1 ........... @rri_cf
231 subi 100101 ..... ..... .... 0 ........... @rri_cf
232 subi_tsv 100101 ..... ..... .... 1 ........... @rri_cf
234 cmpiclr 100100 ..... ..... .... . ........... @rri_cf_d
236 hadd 000010 ..... ..... 00000011 11 0 ..... @rrr
237 hadd_ss 000010 ..... ..... 00000011 01 0 ..... @rrr
238 hadd_us 000010 ..... ..... 00000011 00 0 ..... @rrr
240 havg 000010 ..... ..... 00000010 11 0 ..... @rrr
242 hshl 111110 00000 r:5 100010 i:4 0 t:5 &rri
243 hshr_s 111110 r:5 00000 110011 i:4 0 t:5 &rri
244 hshr_u 111110 r:5 00000 110010 i:4 0 t:5 &rri
246 hsub 000010 ..... ..... 00000001 11 0 ..... @rrr
247 hsub_ss 000010 ..... ..... 00000001 01 0 ..... @rrr
248 hsub_us 000010 ..... ..... 00000001 00 0 ..... @rrr
250 mixh_l 111110 ..... ..... 1 00 00100000 ..... @rrr
251 mixh_r 111110 ..... ..... 1 10 00100000 ..... @rrr
252 mixw_l 111110 ..... ..... 1 00 00000000 ..... @rrr
253 mixw_r 111110 ..... ..... 1 10 00000000 ..... @rrr
255 permh 111110 r1:5 r2:5 0 c0:2 0 c1:2 c2:2 c3:2 0 t:5
261 @ldstx ...... b:5 x:5 sp:2 scale:1 ....... m:1 t:5 &ldst disp=0
262 @ldim5 ...... b:5 ..... sp:2 ......... t:5 \
263 &ldst disp=%im5_16 x=0 scale=0 m=%ma_to_m
264 @stim5 ...... b:5 t:5 sp:2 ......... ..... \
265 &ldst disp=%im5_0 x=0 scale=0 m=%ma_to_m
267 ld 000011 ..... ..... .. . 1 -- 00 size:2 ...... @ldim5
268 ld 000011 ..... ..... .. . 0 -- 00 size:2 ...... @ldstx
269 st 000011 ..... ..... .. . 1 -- 10 size:2 ...... @stim5
270 ldc 000011 ..... ..... .. . 1 -- 0111 ...... @ldim5 size=2
271 ldc 000011 ..... ..... .. . 0 -- 0111 ...... @ldstx size=2
272 ldc 000011 ..... ..... .. . 1 -- 0101 ...... @ldim5 size=3
273 ldc 000011 ..... ..... .. . 0 -- 0101 ...... @ldstx size=3
274 lda 000011 ..... ..... .. . 1 -- 0110 ...... @ldim5 size=2
275 lda 000011 ..... ..... .. . 0 -- 0110 ...... @ldstx size=2
276 lda 000011 ..... ..... .. . 1 -- 0100 ...... @ldim5 size=3
277 lda 000011 ..... ..... .. . 0 -- 0100 ...... @ldstx size=3
278 sta 000011 ..... ..... .. . 1 -- 1110 ...... @stim5 size=2
279 sta 000011 ..... ..... .. . 1 -- 1111 ...... @stim5 size=3
280 stby 000011 b:5 r:5 sp:2 a:1 1 -- 1100 m:1 ..... disp=%im5_0
281 stdby 000011 b:5 r:5 sp:2 a:1 1 -- 1101 m:1 ..... disp=%im5_0
283 @fldstwx ...... b:5 x:5 sp:2 scale:1 ....... m:1 ..... \
284 &ldst t=%rt64 disp=0 size=2
285 @fldstwi ...... b:5 ..... sp:2 . ....... . ..... \
286 &ldst t=%rt64 disp=%im5_16 m=%ma_to_m x=0 scale=0 size=2
288 fldw 001001 ..... ..... .. . 0 -- 000 . . ..... @fldstwx
289 fldw 001001 ..... ..... .. . 1 -- 000 . . ..... @fldstwi
290 fstw 001001 ..... ..... .. . 0 -- 100 . . ..... @fldstwx
291 fstw 001001 ..... ..... .. . 1 -- 100 . . ..... @fldstwi
293 @fldstdx ...... b:5 x:5 sp:2 scale:1 ....... m:1 t:5 \
295 @fldstdi ...... b:5 ..... sp:2 . ....... . t:5 \
296 &ldst disp=%im5_16 m=%ma_to_m x=0 scale=0 size=3
298 fldd 001011 ..... ..... .. . 0 -- 000 0 . ..... @fldstdx
299 fldd 001011 ..... ..... .. . 1 -- 000 0 . ..... @fldstdi
300 fstd 001011 ..... ..... .. . 0 -- 100 0 . ..... @fldstdx
301 fstd 001011 ..... ..... .. . 1 -- 100 0 . ..... @fldstdi
307 @ldstim11 ...... b:5 t:5 sp:2 .............. \
308 &ldst disp=%assemble_11a m=%ma2_to_m x=0 scale=0 size=3
309 @ldstim14 ...... b:5 t:5 sp:2 .............. \
310 &ldst disp=%lowsign_14 x=0 scale=0 m=0
311 @ldstim14m ...... b:5 t:5 sp:2 .............. \
312 &ldst disp=%lowsign_14 x=0 scale=0 m=%neg_to_m
313 @ldstim12m ...... b:5 t:5 sp:2 .............. \
314 &ldst disp=%assemble_12a x=0 scale=0 m=%pos_to_m
316 # LDB, LDH, LDW, LDWM
317 ld 010000 ..... ..... .. .............. @ldstim14 size=0
318 ld 010001 ..... ..... .. .............. @ldstim14 size=1
319 ld 010010 ..... ..... .. .............. @ldstim14 size=2
320 ld 010011 ..... ..... .. .............. @ldstim14m size=2
321 ld 010111 ..... ..... .. ...........10. @ldstim12m size=2
323 # STB, STH, STW, STWM
324 st 011000 ..... ..... .. .............. @ldstim14 size=0
325 st 011001 ..... ..... .. .............. @ldstim14 size=1
326 st 011010 ..... ..... .. .............. @ldstim14 size=2
327 st 011011 ..... ..... .. .............. @ldstim14m size=2
328 st 011111 ..... ..... .. ...........10. @ldstim12m size=2
330 fldw 010110 b:5 ..... sp:2 .............. \
331 &ldst disp=%assemble_12a t=%rm64 m=%a_to_m x=0 scale=0 size=2
332 fldw 010111 b:5 ..... sp:2 ...........0.. \
333 &ldst disp=%assemble_12a t=%rm64 m=0 x=0 scale=0 size=2
335 fstw 011110 b:5 ..... sp:2 .............. \
336 &ldst disp=%assemble_12a t=%rm64 m=%a_to_m x=0 scale=0 size=2
337 fstw 011111 b:5 ..... sp:2 ...........0.. \
338 &ldst disp=%assemble_12a t=%rm64 m=0 x=0 scale=0 size=2
340 ld 010100 ..... ..... .. ............0. @ldstim11
341 fldd 010100 ..... ..... .. ............1. @ldstim11
343 st 011100 ..... ..... .. ............0. @ldstim11
344 fstd 011100 ..... ..... .. ............1. @ldstim11
347 # Floating-point Multiply Add
350 &mpyadd rm1 rm2 ta ra tm
351 @mpyadd ...... rm1:5 rm2:5 ta:5 ra:5 . tm:5 &mpyadd
353 fmpyadd_f 000110 ..... ..... ..... ..... 0 ..... @mpyadd
354 fmpyadd_d 000110 ..... ..... ..... ..... 1 ..... @mpyadd
355 fmpysub_f 100110 ..... ..... ..... ..... 0 ..... @mpyadd
356 fmpysub_d 100110 ..... ..... ..... ..... 1 ..... @mpyadd
359 # Conditional Branches
362 bb_sar 110000 00000 r:5 c:1 1 d:1 ........... n:1 . disp=%assemble_12
363 bb_imm 110001 p:5 r:5 c:1 1 d:1 ........... n:1 . disp=%assemble_12
365 movb 110010 ..... ..... ... ........... . . @rrb_cf f=0
366 movbi 110011 ..... ..... ... ........... . . @rib_cf f=0
368 cmpb 100000 ..... ..... ... ........... . . @rrb_cdf d=0 f=0
369 cmpb 100010 ..... ..... ... ........... . . @rrb_cdf d=0 f=1
370 cmpb 100111 ..... ..... ... ........... . . @rrb_cdf d=1 f=0
371 cmpb 101111 ..... ..... ... ........... . . @rrb_cdf d=1 f=1
372 cmpbi 100001 ..... ..... ... ........... . . @rib_cdf d=0 f=0
373 cmpbi 100011 ..... ..... ... ........... . . @rib_cdf d=0 f=1
374 cmpbi 111011 r:5 ..... f:1 .. ........... n:1 . \
375 &rib_c_d_f d=1 disp=%assemble_12 c=%cmpbid_c i=%im5_16
377 addb 101000 ..... ..... ... ........... . . @rrb_cf f=0
378 addb 101010 ..... ..... ... ........... . . @rrb_cf f=1
379 addbi 101001 ..... ..... ... ........... . . @rib_cf f=0
380 addbi 101011 ..... ..... ... ........... . . @rib_cf f=1
383 # Shift, Extract, Deposit
386 shrp_sar 110100 r2:5 r1:5 c:3 00 0 d:1 0000 t:5
387 shrp_imm 110100 r2:5 r1:5 c:3 01 0 cpos:5 t:5 d=0
388 shrp_imm 110100 r2:5 r1:5 c:3 0. 1 ..... t:5 \
391 extr_sar 110100 r:5 t:5 c:3 10 se:1 00 000 ..... d=0 len=%len5
392 extr_sar 110100 r:5 t:5 c:3 10 se:1 1. 000 ..... d=1 len=%len6_8
393 extr_imm 110100 r:5 t:5 c:3 11 se:1 pos:5 ..... d=0 len=%len5
394 extr_imm 110110 r:5 t:5 c:3 .. se:1 ..... ..... \
395 d=1 len=%len6_12 pos=%cpos6_11
397 dep_sar 110101 t:5 r:5 c:3 00 nz:1 00 000 ..... d=0 len=%len5
398 dep_sar 110101 t:5 r:5 c:3 00 nz:1 1. 000 ..... d=1 len=%len6_8
399 dep_imm 110101 t:5 r:5 c:3 01 nz:1 cpos:5 ..... d=0 len=%len5
400 dep_imm 111100 t:5 r:5 c:3 .. nz:1 ..... ..... \
401 d=1 len=%len6_12 cpos=%cpos6_11
402 depi_sar 110101 t:5 ..... c:3 10 nz:1 d:1 . 000 ..... \
403 i=%im5_16 len=%len6_8
404 depi_imm 110101 t:5 ..... c:3 11 nz:1 cpos:5 ..... \
405 d=0 i=%im5_16 len=%len5
406 depi_imm 111101 t:5 ..... c:3 .. nz:1 ..... ..... \
407 d=1 i=%im5_16 len=%len6_12 cpos=%cpos6_11
414 @be ...... b:5 ..... ... ........... n:1 . \
415 &BE disp=%assemble_17 sp=%assemble_sr3
417 be 111000 ..... ..... ... ........... . . @be l=0
418 be 111001 ..... ..... ... ........... . . @be l=31
425 @bl ...... l:5 ..... ... ........... n:1 . &BL disp=%assemble_17
428 bl 111010 ..... ..... 000 ........... . . @bl
429 bl 111010 ..... ..... 100 ........... . . @bl
430 # B,L (long displacement)
431 bl 111010 ..... ..... 101 ........... n:1 . &BL l=2 \
433 b_gate 111010 ..... ..... 001 ........... . . @bl
434 blr 111010 l:5 x:5 010 00000000000 n:1 0
435 nopbts 111010 00000 00000 010 0---------1 0 1 # clrbts/popbts
436 nopbts 111010 00000 ----- 010 00000000000 0 1 # pushbts/pushnom
437 bv 111010 b:5 x:5 110 00000000000 n:1 0
438 bve 111010 b:5 00000 110 10000000000 n:1 - l=0
439 bve 111010 b:5 00000 111 10000000000 n:1 - l=2
442 # FP Fused Multiple-Add
445 fmpyfadd_f 101110 ..... ..... ... . 0 ... . . neg:1 ..... \
446 rm1=%ra64 rm2=%rb64 ra3=%rc64 t=%rt64
447 fmpyfadd_d 101110 rm1:5 rm2:5 ... 0 1 ..0 0 0 neg:1 t:5 ra3=%rc32
457 @f0c_0 ...... r:5 00000 ..... 00 000 0 t:5 &fclass01
458 @f0c_1 ...... r:5 000.. ..... 01 000 0 t:5 &fclass01
459 @f0c_2 ...... r1:5 r2:5 y:3 .. 10 000 . c:5 &fclass2
460 @f0c_3 ...... r1:5 r2:5 ..... 11 000 0 t:5 &fclass3
462 @f0e_f_0 ...... ..... 00000 ... 0 0 000 .. 0 ..... \
463 &fclass01 r=%ra64 t=%rt64
464 @f0e_d_0 ...... r:5 00000 ... 0 1 000 00 0 t:5 &fclass01
466 @f0e_ff_1 ...... ..... 000 ... 0000 010 .. 0 ..... \
467 &fclass01 r=%ra64 t=%rt64
468 @f0e_fd_1 ...... ..... 000 ... 0100 010 .0 0 t:5 &fclass01 r=%ra64
469 @f0e_df_1 ...... r:5 000 ... 0001 010 0. 0 ..... &fclass01 t=%rt64
470 @f0e_dd_1 ...... r:5 000 ... 0101 010 00 0 t:5 &fclass01
472 @f0e_f_2 ...... ..... ..... y:3 .0 100 .00 c:5 \
473 &fclass2 r1=%ra64 r2=%rb64
474 @f0e_d_2 ...... r1:5 r2:5 y:3 01 100 000 c:5 &fclass2
476 @f0e_f_3 ...... ..... ..... ... .0 110 ..0 ..... \
477 &fclass3 r1=%ra64 r2=%rb64 t=%rt64
478 @f0e_d_3 ...... r1:5 r2:5 ... 01 110 000 t:5 &fclass3
480 # Floating point class 0
482 fid_f 001100 00000 00000 000 00 000000 00000
484 fcpy_f 001100 ..... ..... 010 00 ...... ..... @f0c_0
485 fabs_f 001100 ..... ..... 011 00 ...... ..... @f0c_0
486 fsqrt_f 001100 ..... ..... 100 00 ...... ..... @f0c_0
487 frnd_f 001100 ..... ..... 101 00 ...... ..... @f0c_0
488 fneg_f 001100 ..... ..... 110 00 ...... ..... @f0c_0
489 fnegabs_f 001100 ..... ..... 111 00 ...... ..... @f0c_0
491 fcpy_d 001100 ..... ..... 010 01 ...... ..... @f0c_0
492 fabs_d 001100 ..... ..... 011 01 ...... ..... @f0c_0
493 fsqrt_d 001100 ..... ..... 100 01 ...... ..... @f0c_0
494 frnd_d 001100 ..... ..... 101 01 ...... ..... @f0c_0
495 fneg_d 001100 ..... ..... 110 01 ...... ..... @f0c_0
496 fnegabs_d 001100 ..... ..... 111 01 ...... ..... @f0c_0
498 fcpy_f 001110 ..... ..... 010 ........ ..... @f0e_f_0
499 fabs_f 001110 ..... ..... 011 ........ ..... @f0e_f_0
500 fsqrt_f 001110 ..... ..... 100 ........ ..... @f0e_f_0
501 frnd_f 001110 ..... ..... 101 ........ ..... @f0e_f_0
502 fneg_f 001110 ..... ..... 110 ........ ..... @f0e_f_0
503 fnegabs_f 001110 ..... ..... 111 ........ ..... @f0e_f_0
505 fcpy_d 001110 ..... ..... 010 ........ ..... @f0e_d_0
506 fabs_d 001110 ..... ..... 011 ........ ..... @f0e_d_0
507 fsqrt_d 001110 ..... ..... 100 ........ ..... @f0e_d_0
508 frnd_d 001110 ..... ..... 101 ........ ..... @f0e_d_0
509 fneg_d 001110 ..... ..... 110 ........ ..... @f0e_d_0
510 fnegabs_d 001110 ..... ..... 111 ........ ..... @f0e_d_0
512 # Floating point class 1
515 fcnv_d_f 001100 ..... ... 000 00 01 ...... ..... @f0c_1
516 fcnv_f_d 001100 ..... ... 000 01 00 ...... ..... @f0c_1
518 fcnv_d_f 001110 ..... ... 000 .......... ..... @f0e_df_1
519 fcnv_f_d 001110 ..... ... 000 .......... ..... @f0e_fd_1
522 fcnv_w_f 001100 ..... ... 001 00 00 ...... ..... @f0c_1
523 fcnv_q_f 001100 ..... ... 001 00 01 ...... ..... @f0c_1
524 fcnv_w_d 001100 ..... ... 001 01 00 ...... ..... @f0c_1
525 fcnv_q_d 001100 ..... ... 001 01 01 ...... ..... @f0c_1
527 fcnv_w_f 001110 ..... ... 001 .......... ..... @f0e_ff_1
528 fcnv_q_f 001110 ..... ... 001 .......... ..... @f0e_df_1
529 fcnv_w_d 001110 ..... ... 001 .......... ..... @f0e_fd_1
530 fcnv_q_d 001110 ..... ... 001 .......... ..... @f0e_dd_1
533 fcnv_f_w 001100 ..... ... 010 00 00 ...... ..... @f0c_1
534 fcnv_d_w 001100 ..... ... 010 00 01 ...... ..... @f0c_1
535 fcnv_f_q 001100 ..... ... 010 01 00 ...... ..... @f0c_1
536 fcnv_d_q 001100 ..... ... 010 01 01 ...... ..... @f0c_1
538 fcnv_f_w 001110 ..... ... 010 .......... ..... @f0e_ff_1
539 fcnv_d_w 001110 ..... ... 010 .......... ..... @f0e_df_1
540 fcnv_f_q 001110 ..... ... 010 .......... ..... @f0e_fd_1
541 fcnv_d_q 001110 ..... ... 010 .......... ..... @f0e_dd_1
544 fcnv_t_f_w 001100 ..... ... 011 00 00 ...... ..... @f0c_1
545 fcnv_t_d_w 001100 ..... ... 011 00 01 ...... ..... @f0c_1
546 fcnv_t_f_q 001100 ..... ... 011 01 00 ...... ..... @f0c_1
547 fcnv_t_d_q 001100 ..... ... 011 01 01 ...... ..... @f0c_1
549 fcnv_t_f_w 001110 ..... ... 011 .......... ..... @f0e_ff_1
550 fcnv_t_d_w 001110 ..... ... 011 .......... ..... @f0e_df_1
551 fcnv_t_f_q 001110 ..... ... 011 .......... ..... @f0e_fd_1
552 fcnv_t_d_q 001110 ..... ... 011 .......... ..... @f0e_dd_1
555 fcnv_uw_f 001100 ..... ... 101 00 00 ...... ..... @f0c_1
556 fcnv_uq_f 001100 ..... ... 101 00 01 ...... ..... @f0c_1
557 fcnv_uw_d 001100 ..... ... 101 01 00 ...... ..... @f0c_1
558 fcnv_uq_d 001100 ..... ... 101 01 01 ...... ..... @f0c_1
560 fcnv_uw_f 001110 ..... ... 101 .......... ..... @f0e_ff_1
561 fcnv_uq_f 001110 ..... ... 101 .......... ..... @f0e_df_1
562 fcnv_uw_d 001110 ..... ... 101 .......... ..... @f0e_fd_1
563 fcnv_uq_d 001110 ..... ... 101 .......... ..... @f0e_dd_1
566 fcnv_f_uw 001100 ..... ... 110 00 00 ...... ..... @f0c_1
567 fcnv_d_uw 001100 ..... ... 110 00 01 ...... ..... @f0c_1
568 fcnv_f_uq 001100 ..... ... 110 01 00 ...... ..... @f0c_1
569 fcnv_d_uq 001100 ..... ... 110 01 01 ...... ..... @f0c_1
571 fcnv_f_uw 001110 ..... ... 110 .......... ..... @f0e_ff_1
572 fcnv_d_uw 001110 ..... ... 110 .......... ..... @f0e_df_1
573 fcnv_f_uq 001110 ..... ... 110 .......... ..... @f0e_fd_1
574 fcnv_d_uq 001110 ..... ... 110 .......... ..... @f0e_dd_1
577 fcnv_t_f_uw 001100 ..... ... 111 00 00 ...... ..... @f0c_1
578 fcnv_t_d_uw 001100 ..... ... 111 00 01 ...... ..... @f0c_1
579 fcnv_t_f_uq 001100 ..... ... 111 01 00 ...... ..... @f0c_1
580 fcnv_t_d_uq 001100 ..... ... 111 01 01 ...... ..... @f0c_1
582 fcnv_t_f_uw 001110 ..... ... 111 .......... ..... @f0e_ff_1
583 fcnv_t_d_uw 001110 ..... ... 111 .......... ..... @f0e_df_1
584 fcnv_t_f_uq 001110 ..... ... 111 .......... ..... @f0e_fd_1
585 fcnv_t_d_uq 001110 ..... ... 111 .......... ..... @f0e_dd_1
587 # Floating point class 2
589 ftest 001100 00000 00000 y:3 00 10000 1 c:5
591 fcmp_f 001100 ..... ..... ... 00 ..... 0 ..... @f0c_2
592 fcmp_d 001100 ..... ..... ... 01 ..... 0 ..... @f0c_2
594 fcmp_f 001110 ..... ..... ... ..... ... ..... @f0e_f_2
595 fcmp_d 001110 ..... ..... ... ..... ... ..... @f0e_d_2
597 # Floating point class 3
599 fadd_f 001100 ..... ..... 000 00 ...... ..... @f0c_3
600 fsub_f 001100 ..... ..... 001 00 ...... ..... @f0c_3
601 fmpy_f 001100 ..... ..... 010 00 ...... ..... @f0c_3
602 fdiv_f 001100 ..... ..... 011 00 ...... ..... @f0c_3
604 fadd_d 001100 ..... ..... 000 01 ...... ..... @f0c_3
605 fsub_d 001100 ..... ..... 001 01 ...... ..... @f0c_3
606 fmpy_d 001100 ..... ..... 010 01 ...... ..... @f0c_3
607 fdiv_d 001100 ..... ..... 011 01 ...... ..... @f0c_3
609 fadd_f 001110 ..... ..... 000 ..... ... ..... @f0e_f_3
610 fsub_f 001110 ..... ..... 001 ..... ... ..... @f0e_f_3
611 fmpy_f 001110 ..... ..... 010 ..... ... ..... @f0e_f_3
612 fdiv_f 001110 ..... ..... 011 ..... ... ..... @f0e_f_3
614 fadd_d 001110 ..... ..... 000 ..... ... ..... @f0e_d_3
615 fsub_d 001110 ..... ..... 001 ..... ... ..... @f0e_d_3
616 fmpy_d 001110 ..... ..... 010 ..... ... ..... @f0e_d_3
617 fdiv_d 001110 ..... ..... 011 ..... ... ..... @f0e_d_3
619 xmpyu 001110 ..... ..... 010 .0111 .00 t:5 r1=%ra64 r2=%rb64