target/hexagon/cpu.h

   1 /*
   2  *  Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
   3  *
   4  *  This program is free software; you can redistribute it and/or modify
   5  *  it under the terms of the GNU General Public License as published by
   6  *  the Free Software Foundation; either version 2 of the License, or
   7  *  (at your option) any later version.
   8  *
   9  *  This program is distributed in the hope that it will be useful,
  10  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  *  GNU General Public License for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License
  15  *  along with this program; if not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef HEXAGON_CPU_H
  19 #define HEXAGON_CPU_H
  20
  21 #include "fpu/softfloat-types.h"
  22
  23 #include "cpu-qom.h"
  24 #include "exec/cpu-defs.h"
  25 #include "hex_regs.h"
  26 #include "mmvec/mmvec.h"
  27 #include "hw/registerfields.h"
  28
  29 #define NUM_PREGS 4
  30 #define TOTAL_PER_THREAD_REGS 64
  31
  32 #define SLOTS_MAX 4
  33 #define STORES_MAX 2
  34 #define REG_WRITES_MAX 32
  35 #define PRED_WRITES_MAX 5                   /* 4 insns + endloop */
  36 #define VSTORES_MAX 2
  37
  38 #define CPU_RESOLVING_TYPE TYPE_HEXAGON_CPU
  39
  40 void hexagon_cpu_list(void);
  41 #define cpu_list hexagon_cpu_list
  42
  43 #define MMU_USER_IDX 0
  44
  45 typedef struct {
  46     target_ulong va;
  47     uint8_t width;
  48     uint32_t data32;
  49     uint64_t data64;
  50 } MemLog;
  51
  52 typedef struct {
  53     target_ulong va;
  54     int size;
  55     DECLARE_BITMAP(mask, MAX_VEC_SIZE_BYTES) QEMU_ALIGNED(16);
  56     MMVector data QEMU_ALIGNED(16);
  57 } VStoreLog;
  58
  59 #define EXEC_STATUS_OK          0x0000
  60 #define EXEC_STATUS_STOP        0x0002
  61 #define EXEC_STATUS_REPLAY      0x0010
  62 #define EXEC_STATUS_LOCKED      0x0020
  63 #define EXEC_STATUS_EXCEPTION   0x0100
  64
  65
  66 #define EXCEPTION_DETECTED      (env->status & EXEC_STATUS_EXCEPTION)
  67 #define REPLAY_DETECTED         (env->status & EXEC_STATUS_REPLAY)
  68 #define CLEAR_EXCEPTION         (env->status &= (~EXEC_STATUS_EXCEPTION))
  69 #define SET_EXCEPTION           (env->status |= EXEC_STATUS_EXCEPTION)
  70
  71 /* Maximum number of vector temps in a packet */
  72 #define VECTOR_TEMPS_MAX            4
  73
  74 typedef struct CPUArchState {
  75     target_ulong gpr[TOTAL_PER_THREAD_REGS];
  76     target_ulong pred[NUM_PREGS];
  77
  78     /* For comparing with LLDB on target - see adjust_stack_ptrs function */
  79     target_ulong last_pc_dumped;
  80     target_ulong stack_start;
  81
  82     uint8_t slot_cancelled;
  83     target_ulong new_value_usr;
  84
  85     /*
  86      * Only used when HEX_DEBUG is on, but unconditionally included
  87      * to reduce recompile time when turning HEX_DEBUG on/off.
  88      */
  89     target_ulong reg_written[TOTAL_PER_THREAD_REGS];
  90
  91     MemLog mem_log_stores[STORES_MAX];
  92
  93     float_status fp_status;
  94
  95     target_ulong llsc_addr;
  96     target_ulong llsc_val;
  97     uint64_t     llsc_val_i64;
  98
  99     MMVector VRegs[NUM_VREGS] QEMU_ALIGNED(16);
 100     MMVector future_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16);
 101     MMVector tmp_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16);
 102
 103     MMQReg QRegs[NUM_QREGS] QEMU_ALIGNED(16);
 104     MMQReg future_QRegs[NUM_QREGS] QEMU_ALIGNED(16);
 105
 106     /* Temporaries used within instructions */
 107     MMVectorPair VuuV QEMU_ALIGNED(16);
 108     MMVectorPair VvvV QEMU_ALIGNED(16);
 109     MMVectorPair VxxV QEMU_ALIGNED(16);
 110     MMVector     vtmp QEMU_ALIGNED(16);
 111     MMQReg       qtmp QEMU_ALIGNED(16);
 112
 113     VStoreLog vstore[VSTORES_MAX];
 114     target_ulong vstore_pending[VSTORES_MAX];
 115     bool vtcm_pending;
 116     VTCMStoreLog vtcm_log;
 117 } CPUHexagonState;
 118
 119 typedef struct HexagonCPUClass {
 120     CPUClass parent_class;
 121
 122     DeviceRealize parent_realize;
 123     ResettablePhases parent_phases;
 124 } HexagonCPUClass;
 125
 126 struct ArchCPU {
 127     CPUState parent_obj;
 128
 129     CPUHexagonState env;
 130
 131     bool lldb_compat;
 132     target_ulong lldb_stack_adjust;
 133     bool short_circuit;
 134 };
 135
 136 #include "cpu_bits.h"
 137
 138 FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1)
 139
 140 static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc,
 141                                         uint64_t *cs_base, uint32_t *flags)
 142 {
 143     uint32_t hex_flags = 0;
 144     *pc = env->gpr[HEX_REG_PC];
 145     *cs_base = 0;
 146     if (*pc == env->gpr[HEX_REG_SA0]) {
 147         hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1);
 148     }
 149     *flags = hex_flags;
 150 }
 151
 152 static inline int cpu_mmu_index(CPUHexagonState *env, bool ifetch)
 153 {
 154 #ifdef CONFIG_USER_ONLY
 155     return MMU_USER_IDX;
 156 #else
 157 #error System mode not supported on Hexagon yet
 158 #endif
 159 }
 160
 161 typedef HexagonCPU ArchCPU;
 162
 163 void hexagon_translate_init(void);
 164
 165 #include "exec/cpu-all.h"
 166
 167 #endif /* HEXAGON_CPU_H */