2 * USB xHCI controller emulation
4 * Copyright (c) 2011 Securiforest
5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 #include "qemu/timer.h"
24 #include "hw/pci/pci.h"
25 #include "hw/pci/msi.h"
26 #include "hw/pci/msix.h"
33 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__)
35 #define DPRINTF(...) do {} while (0)
37 #define FIXME(_msg) do { fprintf(stderr, "FIXME %s:%d %s\n", \
38 __func__, __LINE__, _msg); abort(); } while (0)
43 #define MAXPORTS (MAXPORTS_2+MAXPORTS_3)
49 /* Very pessimistic, let's hope it's enough for all cases */
50 #define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS)
51 /* Do not deliver ER Full events. NEC's driver does some things not bound
52 * to the specs when it gets them */
56 #define LEN_OPER (0x400 + 0x10 * MAXPORTS)
57 #define LEN_RUNTIME ((MAXINTRS + 1) * 0x20)
58 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20)
60 #define OFF_OPER LEN_CAP
61 #define OFF_RUNTIME 0x1000
62 #define OFF_DOORBELL 0x2000
63 #define OFF_MSIX_TABLE 0x3000
64 #define OFF_MSIX_PBA 0x3800
65 /* must be power of 2 */
66 #define LEN_REGS 0x4000
68 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME
69 #error Increase OFF_RUNTIME
71 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL
72 #error Increase OFF_DOORBELL
74 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS
75 # error Increase LEN_REGS
79 #define USBCMD_RS (1<<0)
80 #define USBCMD_HCRST (1<<1)
81 #define USBCMD_INTE (1<<2)
82 #define USBCMD_HSEE (1<<3)
83 #define USBCMD_LHCRST (1<<7)
84 #define USBCMD_CSS (1<<8)
85 #define USBCMD_CRS (1<<9)
86 #define USBCMD_EWE (1<<10)
87 #define USBCMD_EU3S (1<<11)
89 #define USBSTS_HCH (1<<0)
90 #define USBSTS_HSE (1<<2)
91 #define USBSTS_EINT (1<<3)
92 #define USBSTS_PCD (1<<4)
93 #define USBSTS_SSS (1<<8)
94 #define USBSTS_RSS (1<<9)
95 #define USBSTS_SRE (1<<10)
96 #define USBSTS_CNR (1<<11)
97 #define USBSTS_HCE (1<<12)
100 #define PORTSC_CCS (1<<0)
101 #define PORTSC_PED (1<<1)
102 #define PORTSC_OCA (1<<3)
103 #define PORTSC_PR (1<<4)
104 #define PORTSC_PLS_SHIFT 5
105 #define PORTSC_PLS_MASK 0xf
106 #define PORTSC_PP (1<<9)
107 #define PORTSC_SPEED_SHIFT 10
108 #define PORTSC_SPEED_MASK 0xf
109 #define PORTSC_SPEED_FULL (1<<10)
110 #define PORTSC_SPEED_LOW (2<<10)
111 #define PORTSC_SPEED_HIGH (3<<10)
112 #define PORTSC_SPEED_SUPER (4<<10)
113 #define PORTSC_PIC_SHIFT 14
114 #define PORTSC_PIC_MASK 0x3
115 #define PORTSC_LWS (1<<16)
116 #define PORTSC_CSC (1<<17)
117 #define PORTSC_PEC (1<<18)
118 #define PORTSC_WRC (1<<19)
119 #define PORTSC_OCC (1<<20)
120 #define PORTSC_PRC (1<<21)
121 #define PORTSC_PLC (1<<22)
122 #define PORTSC_CEC (1<<23)
123 #define PORTSC_CAS (1<<24)
124 #define PORTSC_WCE (1<<25)
125 #define PORTSC_WDE (1<<26)
126 #define PORTSC_WOE (1<<27)
127 #define PORTSC_DR (1<<30)
128 #define PORTSC_WPR (1<<31)
130 #define CRCR_RCS (1<<0)
131 #define CRCR_CS (1<<1)
132 #define CRCR_CA (1<<2)
133 #define CRCR_CRR (1<<3)
135 #define IMAN_IP (1<<0)
136 #define IMAN_IE (1<<1)
138 #define ERDP_EHB (1<<3)
141 typedef struct XHCITRB
{
160 PLS_COMPILANCE_MODE
= 10,
165 typedef enum TRBType
{
178 CR_CONFIGURE_ENDPOINT
,
186 CR_SET_LATENCY_TOLERANCE
,
187 CR_GET_PORT_BANDWIDTH
,
192 ER_PORT_STATUS_CHANGE
,
193 ER_BANDWIDTH_REQUEST
,
196 ER_DEVICE_NOTIFICATION
,
198 /* vendor specific bits */
199 CR_VENDOR_VIA_CHALLENGE_RESPONSE
= 48,
200 CR_VENDOR_NEC_FIRMWARE_REVISION
= 49,
201 CR_VENDOR_NEC_CHALLENGE_RESPONSE
= 50,
204 #define CR_LINK TR_LINK
206 typedef enum TRBCCode
{
209 CC_DATA_BUFFER_ERROR
,
211 CC_USB_TRANSACTION_ERROR
,
217 CC_INVALID_STREAM_TYPE_ERROR
,
218 CC_SLOT_NOT_ENABLED_ERROR
,
219 CC_EP_NOT_ENABLED_ERROR
,
225 CC_BANDWIDTH_OVERRUN
,
226 CC_CONTEXT_STATE_ERROR
,
227 CC_NO_PING_RESPONSE_ERROR
,
228 CC_EVENT_RING_FULL_ERROR
,
229 CC_INCOMPATIBLE_DEVICE_ERROR
,
230 CC_MISSED_SERVICE_ERROR
,
231 CC_COMMAND_RING_STOPPED
,
234 CC_STOPPED_LENGTH_INVALID
,
235 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR
= 29,
236 CC_ISOCH_BUFFER_OVERRUN
= 31,
239 CC_INVALID_STREAM_ID_ERROR
,
240 CC_SECONDARY_BANDWIDTH_ERROR
,
241 CC_SPLIT_TRANSACTION_ERROR
245 #define TRB_TYPE_SHIFT 10
246 #define TRB_TYPE_MASK 0x3f
247 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
249 #define TRB_EV_ED (1<<2)
251 #define TRB_TR_ENT (1<<1)
252 #define TRB_TR_ISP (1<<2)
253 #define TRB_TR_NS (1<<3)
254 #define TRB_TR_CH (1<<4)
255 #define TRB_TR_IOC (1<<5)
256 #define TRB_TR_IDT (1<<6)
257 #define TRB_TR_TBC_SHIFT 7
258 #define TRB_TR_TBC_MASK 0x3
259 #define TRB_TR_BEI (1<<9)
260 #define TRB_TR_TLBPC_SHIFT 16
261 #define TRB_TR_TLBPC_MASK 0xf
262 #define TRB_TR_FRAMEID_SHIFT 20
263 #define TRB_TR_FRAMEID_MASK 0x7ff
264 #define TRB_TR_SIA (1<<31)
266 #define TRB_TR_DIR (1<<16)
268 #define TRB_CR_SLOTID_SHIFT 24
269 #define TRB_CR_SLOTID_MASK 0xff
270 #define TRB_CR_EPID_SHIFT 16
271 #define TRB_CR_EPID_MASK 0x1f
273 #define TRB_CR_BSR (1<<9)
274 #define TRB_CR_DC (1<<9)
276 #define TRB_LK_TC (1<<1)
278 #define TRB_INTR_SHIFT 22
279 #define TRB_INTR_MASK 0x3ff
280 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK)
282 #define EP_TYPE_MASK 0x7
283 #define EP_TYPE_SHIFT 3
285 #define EP_STATE_MASK 0x7
286 #define EP_DISABLED (0<<0)
287 #define EP_RUNNING (1<<0)
288 #define EP_HALTED (2<<0)
289 #define EP_STOPPED (3<<0)
290 #define EP_ERROR (4<<0)
292 #define SLOT_STATE_MASK 0x1f
293 #define SLOT_STATE_SHIFT 27
294 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
295 #define SLOT_ENABLED 0
296 #define SLOT_DEFAULT 1
297 #define SLOT_ADDRESSED 2
298 #define SLOT_CONFIGURED 3
300 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f
301 #define SLOT_CONTEXT_ENTRIES_SHIFT 27
303 typedef struct XHCIState XHCIState
;
304 typedef struct XHCIStreamContext XHCIStreamContext
;
305 typedef struct XHCIEPContext XHCIEPContext
;
307 #define get_field(data, field) \
308 (((data) >> field##_SHIFT) & field##_MASK)
310 #define set_field(data, newval, field) do { \
311 uint32_t val = *data; \
312 val &= ~(field##_MASK << field##_SHIFT); \
313 val |= ((newval) & field##_MASK) << field##_SHIFT; \
317 typedef enum EPType
{
328 typedef struct XHCIRing
{
333 typedef struct XHCIPort
{
343 typedef struct XHCITransfer
{
352 unsigned int iso_pkts
;
355 unsigned int streamid
;
359 unsigned int trb_count
;
360 unsigned int trb_alloced
;
366 unsigned int pktsize
;
367 unsigned int cur_pkt
;
369 uint64_t mfindex_kick
;
372 struct XHCIStreamContext
{
376 XHCIStreamContext
*sstreams
;
379 struct XHCIEPContext
{
385 unsigned int next_xfer
;
386 unsigned int comp_xfer
;
387 XHCITransfer transfers
[TD_QUEUE
];
391 unsigned int max_psize
;
395 unsigned int max_pstreams
;
397 unsigned int nr_pstreams
;
398 XHCIStreamContext
*pstreams
;
400 /* iso xfer scheduling */
401 unsigned int interval
;
402 int64_t mfindex_last
;
403 QEMUTimer
*kick_timer
;
406 typedef struct XHCISlot
{
411 XHCIEPContext
* eps
[31];
414 typedef struct XHCIEvent
{
424 typedef struct XHCIInterrupter
{
429 uint32_t erstba_high
;
433 bool msix_used
, er_pcs
, er_full
;
437 unsigned int er_ep_idx
;
439 XHCIEvent ev_buffer
[EV_QUEUE
];
440 unsigned int ev_buffer_put
;
441 unsigned int ev_buffer_get
;
447 PCIDevice parent_obj
;
453 MemoryRegion mem_cap
;
454 MemoryRegion mem_oper
;
455 MemoryRegion mem_runtime
;
456 MemoryRegion mem_doorbell
;
465 /* Operational Registers */
472 uint32_t dcbaap_high
;
475 USBPort uports
[MAX(MAXPORTS_2
, MAXPORTS_3
)];
476 XHCIPort ports
[MAXPORTS
];
477 XHCISlot slots
[MAXSLOTS
];
480 /* Runtime Registers */
481 int64_t mfindex_start
;
482 QEMUTimer
*mfwrap_timer
;
483 XHCIInterrupter intr
[MAXINTRS
];
488 #define TYPE_XHCI "nec-usb-xhci"
491 OBJECT_CHECK(XHCIState, (obj), TYPE_XHCI)
493 typedef struct XHCIEvRingSeg
{
501 XHCI_FLAG_USE_MSI
= 1,
505 static void xhci_kick_ep(XHCIState
*xhci
, unsigned int slotid
,
506 unsigned int epid
, unsigned int streamid
);
507 static TRBCCode
xhci_disable_ep(XHCIState
*xhci
, unsigned int slotid
,
509 static void xhci_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
);
510 static void xhci_write_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
);
512 static const char *TRBType_names
[] = {
513 [TRB_RESERVED
] = "TRB_RESERVED",
514 [TR_NORMAL
] = "TR_NORMAL",
515 [TR_SETUP
] = "TR_SETUP",
516 [TR_DATA
] = "TR_DATA",
517 [TR_STATUS
] = "TR_STATUS",
518 [TR_ISOCH
] = "TR_ISOCH",
519 [TR_LINK
] = "TR_LINK",
520 [TR_EVDATA
] = "TR_EVDATA",
521 [TR_NOOP
] = "TR_NOOP",
522 [CR_ENABLE_SLOT
] = "CR_ENABLE_SLOT",
523 [CR_DISABLE_SLOT
] = "CR_DISABLE_SLOT",
524 [CR_ADDRESS_DEVICE
] = "CR_ADDRESS_DEVICE",
525 [CR_CONFIGURE_ENDPOINT
] = "CR_CONFIGURE_ENDPOINT",
526 [CR_EVALUATE_CONTEXT
] = "CR_EVALUATE_CONTEXT",
527 [CR_RESET_ENDPOINT
] = "CR_RESET_ENDPOINT",
528 [CR_STOP_ENDPOINT
] = "CR_STOP_ENDPOINT",
529 [CR_SET_TR_DEQUEUE
] = "CR_SET_TR_DEQUEUE",
530 [CR_RESET_DEVICE
] = "CR_RESET_DEVICE",
531 [CR_FORCE_EVENT
] = "CR_FORCE_EVENT",
532 [CR_NEGOTIATE_BW
] = "CR_NEGOTIATE_BW",
533 [CR_SET_LATENCY_TOLERANCE
] = "CR_SET_LATENCY_TOLERANCE",
534 [CR_GET_PORT_BANDWIDTH
] = "CR_GET_PORT_BANDWIDTH",
535 [CR_FORCE_HEADER
] = "CR_FORCE_HEADER",
536 [CR_NOOP
] = "CR_NOOP",
537 [ER_TRANSFER
] = "ER_TRANSFER",
538 [ER_COMMAND_COMPLETE
] = "ER_COMMAND_COMPLETE",
539 [ER_PORT_STATUS_CHANGE
] = "ER_PORT_STATUS_CHANGE",
540 [ER_BANDWIDTH_REQUEST
] = "ER_BANDWIDTH_REQUEST",
541 [ER_DOORBELL
] = "ER_DOORBELL",
542 [ER_HOST_CONTROLLER
] = "ER_HOST_CONTROLLER",
543 [ER_DEVICE_NOTIFICATION
] = "ER_DEVICE_NOTIFICATION",
544 [ER_MFINDEX_WRAP
] = "ER_MFINDEX_WRAP",
545 [CR_VENDOR_VIA_CHALLENGE_RESPONSE
] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE",
546 [CR_VENDOR_NEC_FIRMWARE_REVISION
] = "CR_VENDOR_NEC_FIRMWARE_REVISION",
547 [CR_VENDOR_NEC_CHALLENGE_RESPONSE
] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE",
550 static const char *TRBCCode_names
[] = {
551 [CC_INVALID
] = "CC_INVALID",
552 [CC_SUCCESS
] = "CC_SUCCESS",
553 [CC_DATA_BUFFER_ERROR
] = "CC_DATA_BUFFER_ERROR",
554 [CC_BABBLE_DETECTED
] = "CC_BABBLE_DETECTED",
555 [CC_USB_TRANSACTION_ERROR
] = "CC_USB_TRANSACTION_ERROR",
556 [CC_TRB_ERROR
] = "CC_TRB_ERROR",
557 [CC_STALL_ERROR
] = "CC_STALL_ERROR",
558 [CC_RESOURCE_ERROR
] = "CC_RESOURCE_ERROR",
559 [CC_BANDWIDTH_ERROR
] = "CC_BANDWIDTH_ERROR",
560 [CC_NO_SLOTS_ERROR
] = "CC_NO_SLOTS_ERROR",
561 [CC_INVALID_STREAM_TYPE_ERROR
] = "CC_INVALID_STREAM_TYPE_ERROR",
562 [CC_SLOT_NOT_ENABLED_ERROR
] = "CC_SLOT_NOT_ENABLED_ERROR",
563 [CC_EP_NOT_ENABLED_ERROR
] = "CC_EP_NOT_ENABLED_ERROR",
564 [CC_SHORT_PACKET
] = "CC_SHORT_PACKET",
565 [CC_RING_UNDERRUN
] = "CC_RING_UNDERRUN",
566 [CC_RING_OVERRUN
] = "CC_RING_OVERRUN",
567 [CC_VF_ER_FULL
] = "CC_VF_ER_FULL",
568 [CC_PARAMETER_ERROR
] = "CC_PARAMETER_ERROR",
569 [CC_BANDWIDTH_OVERRUN
] = "CC_BANDWIDTH_OVERRUN",
570 [CC_CONTEXT_STATE_ERROR
] = "CC_CONTEXT_STATE_ERROR",
571 [CC_NO_PING_RESPONSE_ERROR
] = "CC_NO_PING_RESPONSE_ERROR",
572 [CC_EVENT_RING_FULL_ERROR
] = "CC_EVENT_RING_FULL_ERROR",
573 [CC_INCOMPATIBLE_DEVICE_ERROR
] = "CC_INCOMPATIBLE_DEVICE_ERROR",
574 [CC_MISSED_SERVICE_ERROR
] = "CC_MISSED_SERVICE_ERROR",
575 [CC_COMMAND_RING_STOPPED
] = "CC_COMMAND_RING_STOPPED",
576 [CC_COMMAND_ABORTED
] = "CC_COMMAND_ABORTED",
577 [CC_STOPPED
] = "CC_STOPPED",
578 [CC_STOPPED_LENGTH_INVALID
] = "CC_STOPPED_LENGTH_INVALID",
579 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR
]
580 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR",
581 [CC_ISOCH_BUFFER_OVERRUN
] = "CC_ISOCH_BUFFER_OVERRUN",
582 [CC_EVENT_LOST_ERROR
] = "CC_EVENT_LOST_ERROR",
583 [CC_UNDEFINED_ERROR
] = "CC_UNDEFINED_ERROR",
584 [CC_INVALID_STREAM_ID_ERROR
] = "CC_INVALID_STREAM_ID_ERROR",
585 [CC_SECONDARY_BANDWIDTH_ERROR
] = "CC_SECONDARY_BANDWIDTH_ERROR",
586 [CC_SPLIT_TRANSACTION_ERROR
] = "CC_SPLIT_TRANSACTION_ERROR",
589 static const char *lookup_name(uint32_t index
, const char **list
, uint32_t llen
)
591 if (index
>= llen
|| list
[index
] == NULL
) {
597 static const char *trb_name(XHCITRB
*trb
)
599 return lookup_name(TRB_TYPE(*trb
), TRBType_names
,
600 ARRAY_SIZE(TRBType_names
));
603 static const char *event_name(XHCIEvent
*event
)
605 return lookup_name(event
->ccode
, TRBCCode_names
,
606 ARRAY_SIZE(TRBCCode_names
));
609 static uint64_t xhci_mfindex_get(XHCIState
*xhci
)
611 int64_t now
= qemu_get_clock_ns(vm_clock
);
612 return (now
- xhci
->mfindex_start
) / 125000;
615 static void xhci_mfwrap_update(XHCIState
*xhci
)
617 const uint32_t bits
= USBCMD_RS
| USBCMD_EWE
;
618 uint32_t mfindex
, left
;
621 if ((xhci
->usbcmd
& bits
) == bits
) {
622 now
= qemu_get_clock_ns(vm_clock
);
623 mfindex
= ((now
- xhci
->mfindex_start
) / 125000) & 0x3fff;
624 left
= 0x4000 - mfindex
;
625 qemu_mod_timer(xhci
->mfwrap_timer
, now
+ left
* 125000);
627 qemu_del_timer(xhci
->mfwrap_timer
);
631 static void xhci_mfwrap_timer(void *opaque
)
633 XHCIState
*xhci
= opaque
;
634 XHCIEvent wrap
= { ER_MFINDEX_WRAP
, CC_SUCCESS
};
636 xhci_event(xhci
, &wrap
, 0);
637 xhci_mfwrap_update(xhci
);
640 static inline dma_addr_t
xhci_addr64(uint32_t low
, uint32_t high
)
642 if (sizeof(dma_addr_t
) == 4) {
645 return low
| (((dma_addr_t
)high
<< 16) << 16);
649 static inline dma_addr_t
xhci_mask64(uint64_t addr
)
651 if (sizeof(dma_addr_t
) == 4) {
652 return addr
& 0xffffffff;
658 static inline void xhci_dma_read_u32s(XHCIState
*xhci
, dma_addr_t addr
,
659 uint32_t *buf
, size_t len
)
663 assert((len
% sizeof(uint32_t)) == 0);
665 pci_dma_read(PCI_DEVICE(xhci
), addr
, buf
, len
);
667 for (i
= 0; i
< (len
/ sizeof(uint32_t)); i
++) {
668 buf
[i
] = le32_to_cpu(buf
[i
]);
672 static inline void xhci_dma_write_u32s(XHCIState
*xhci
, dma_addr_t addr
,
673 uint32_t *buf
, size_t len
)
676 uint32_t tmp
[len
/ sizeof(uint32_t)];
678 assert((len
% sizeof(uint32_t)) == 0);
680 for (i
= 0; i
< (len
/ sizeof(uint32_t)); i
++) {
681 tmp
[i
] = cpu_to_le32(buf
[i
]);
683 pci_dma_write(PCI_DEVICE(xhci
), addr
, tmp
, len
);
686 static XHCIPort
*xhci_lookup_port(XHCIState
*xhci
, struct USBPort
*uport
)
693 switch (uport
->dev
->speed
) {
697 index
= uport
->index
;
699 case USB_SPEED_SUPER
:
700 index
= uport
->index
+ xhci
->numports_2
;
705 return &xhci
->ports
[index
];
708 static void xhci_intx_update(XHCIState
*xhci
)
710 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
713 if (msix_enabled(pci_dev
) ||
714 msi_enabled(pci_dev
)) {
718 if (xhci
->intr
[0].iman
& IMAN_IP
&&
719 xhci
->intr
[0].iman
& IMAN_IE
&&
720 xhci
->usbcmd
& USBCMD_INTE
) {
724 trace_usb_xhci_irq_intx(level
);
725 qemu_set_irq(xhci
->irq
, level
);
728 static void xhci_msix_update(XHCIState
*xhci
, int v
)
730 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
733 if (!msix_enabled(pci_dev
)) {
737 enabled
= xhci
->intr
[v
].iman
& IMAN_IE
;
738 if (enabled
== xhci
->intr
[v
].msix_used
) {
743 trace_usb_xhci_irq_msix_use(v
);
744 msix_vector_use(pci_dev
, v
);
745 xhci
->intr
[v
].msix_used
= true;
747 trace_usb_xhci_irq_msix_unuse(v
);
748 msix_vector_unuse(pci_dev
, v
);
749 xhci
->intr
[v
].msix_used
= false;
753 static void xhci_intr_raise(XHCIState
*xhci
, int v
)
755 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
757 xhci
->intr
[v
].erdp_low
|= ERDP_EHB
;
758 xhci
->intr
[v
].iman
|= IMAN_IP
;
759 xhci
->usbsts
|= USBSTS_EINT
;
761 if (!(xhci
->intr
[v
].iman
& IMAN_IE
)) {
765 if (!(xhci
->usbcmd
& USBCMD_INTE
)) {
769 if (msix_enabled(pci_dev
)) {
770 trace_usb_xhci_irq_msix(v
);
771 msix_notify(pci_dev
, v
);
775 if (msi_enabled(pci_dev
)) {
776 trace_usb_xhci_irq_msi(v
);
777 msi_notify(pci_dev
, v
);
782 trace_usb_xhci_irq_intx(1);
783 qemu_set_irq(xhci
->irq
, 1);
787 static inline int xhci_running(XHCIState
*xhci
)
789 return !(xhci
->usbsts
& USBSTS_HCH
) && !xhci
->intr
[0].er_full
;
792 static void xhci_die(XHCIState
*xhci
)
794 xhci
->usbsts
|= USBSTS_HCE
;
795 fprintf(stderr
, "xhci: asserted controller error\n");
798 static void xhci_write_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
)
800 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
801 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
805 ev_trb
.parameter
= cpu_to_le64(event
->ptr
);
806 ev_trb
.status
= cpu_to_le32(event
->length
| (event
->ccode
<< 24));
807 ev_trb
.control
= (event
->slotid
<< 24) | (event
->epid
<< 16) |
808 event
->flags
| (event
->type
<< TRB_TYPE_SHIFT
);
810 ev_trb
.control
|= TRB_C
;
812 ev_trb
.control
= cpu_to_le32(ev_trb
.control
);
814 trace_usb_xhci_queue_event(v
, intr
->er_ep_idx
, trb_name(&ev_trb
),
815 event_name(event
), ev_trb
.parameter
,
816 ev_trb
.status
, ev_trb
.control
);
818 addr
= intr
->er_start
+ TRB_SIZE
*intr
->er_ep_idx
;
819 pci_dma_write(pci_dev
, addr
, &ev_trb
, TRB_SIZE
);
822 if (intr
->er_ep_idx
>= intr
->er_size
) {
824 intr
->er_pcs
= !intr
->er_pcs
;
828 static void xhci_events_update(XHCIState
*xhci
, int v
)
830 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
835 if (xhci
->usbsts
& USBSTS_HCH
) {
839 erdp
= xhci_addr64(intr
->erdp_low
, intr
->erdp_high
);
840 if (erdp
< intr
->er_start
||
841 erdp
>= (intr
->er_start
+ TRB_SIZE
*intr
->er_size
)) {
842 fprintf(stderr
, "xhci: ERDP out of bounds: "DMA_ADDR_FMT
"\n", erdp
);
843 fprintf(stderr
, "xhci: ER[%d] at "DMA_ADDR_FMT
" len %d\n",
844 v
, intr
->er_start
, intr
->er_size
);
848 dp_idx
= (erdp
- intr
->er_start
) / TRB_SIZE
;
849 assert(dp_idx
< intr
->er_size
);
851 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus
852 * deadlocks when the ER is full. Hack it by holding off events until
853 * the driver decides to free at least half of the ring */
855 int er_free
= dp_idx
- intr
->er_ep_idx
;
857 er_free
+= intr
->er_size
;
859 if (er_free
< (intr
->er_size
/2)) {
860 DPRINTF("xhci_events_update(): event ring still "
861 "more than half full (hack)\n");
866 while (intr
->ev_buffer_put
!= intr
->ev_buffer_get
) {
867 assert(intr
->er_full
);
868 if (((intr
->er_ep_idx
+1) % intr
->er_size
) == dp_idx
) {
869 DPRINTF("xhci_events_update(): event ring full again\n");
871 XHCIEvent full
= {ER_HOST_CONTROLLER
, CC_EVENT_RING_FULL_ERROR
};
872 xhci_write_event(xhci
, &full
, v
);
877 XHCIEvent
*event
= &intr
->ev_buffer
[intr
->ev_buffer_get
];
878 xhci_write_event(xhci
, event
, v
);
879 intr
->ev_buffer_get
++;
881 if (intr
->ev_buffer_get
== EV_QUEUE
) {
882 intr
->ev_buffer_get
= 0;
887 xhci_intr_raise(xhci
, v
);
890 if (intr
->er_full
&& intr
->ev_buffer_put
== intr
->ev_buffer_get
) {
891 DPRINTF("xhci_events_update(): event ring no longer full\n");
896 static void xhci_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
)
898 XHCIInterrupter
*intr
;
902 if (v
>= xhci
->numintrs
) {
903 DPRINTF("intr nr out of range (%d >= %d)\n", v
, xhci
->numintrs
);
906 intr
= &xhci
->intr
[v
];
909 DPRINTF("xhci_event(): ER full, queueing\n");
910 if (((intr
->ev_buffer_put
+1) % EV_QUEUE
) == intr
->ev_buffer_get
) {
911 fprintf(stderr
, "xhci: event queue full, dropping event!\n");
914 intr
->ev_buffer
[intr
->ev_buffer_put
++] = *event
;
915 if (intr
->ev_buffer_put
== EV_QUEUE
) {
916 intr
->ev_buffer_put
= 0;
921 erdp
= xhci_addr64(intr
->erdp_low
, intr
->erdp_high
);
922 if (erdp
< intr
->er_start
||
923 erdp
>= (intr
->er_start
+ TRB_SIZE
*intr
->er_size
)) {
924 fprintf(stderr
, "xhci: ERDP out of bounds: "DMA_ADDR_FMT
"\n", erdp
);
925 fprintf(stderr
, "xhci: ER[%d] at "DMA_ADDR_FMT
" len %d\n",
926 v
, intr
->er_start
, intr
->er_size
);
931 dp_idx
= (erdp
- intr
->er_start
) / TRB_SIZE
;
932 assert(dp_idx
< intr
->er_size
);
934 if ((intr
->er_ep_idx
+1) % intr
->er_size
== dp_idx
) {
935 DPRINTF("xhci_event(): ER full, queueing\n");
937 XHCIEvent full
= {ER_HOST_CONTROLLER
, CC_EVENT_RING_FULL_ERROR
};
938 xhci_write_event(xhci
, &full
);
941 if (((intr
->ev_buffer_put
+1) % EV_QUEUE
) == intr
->ev_buffer_get
) {
942 fprintf(stderr
, "xhci: event queue full, dropping event!\n");
945 intr
->ev_buffer
[intr
->ev_buffer_put
++] = *event
;
946 if (intr
->ev_buffer_put
== EV_QUEUE
) {
947 intr
->ev_buffer_put
= 0;
950 xhci_write_event(xhci
, event
, v
);
953 xhci_intr_raise(xhci
, v
);
956 static void xhci_ring_init(XHCIState
*xhci
, XHCIRing
*ring
,
959 ring
->dequeue
= base
;
963 static TRBType
xhci_ring_fetch(XHCIState
*xhci
, XHCIRing
*ring
, XHCITRB
*trb
,
966 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
970 pci_dma_read(pci_dev
, ring
->dequeue
, trb
, TRB_SIZE
);
971 trb
->addr
= ring
->dequeue
;
972 trb
->ccs
= ring
->ccs
;
973 le64_to_cpus(&trb
->parameter
);
974 le32_to_cpus(&trb
->status
);
975 le32_to_cpus(&trb
->control
);
977 trace_usb_xhci_fetch_trb(ring
->dequeue
, trb_name(trb
),
978 trb
->parameter
, trb
->status
, trb
->control
);
980 if ((trb
->control
& TRB_C
) != ring
->ccs
) {
984 type
= TRB_TYPE(*trb
);
986 if (type
!= TR_LINK
) {
988 *addr
= ring
->dequeue
;
990 ring
->dequeue
+= TRB_SIZE
;
993 ring
->dequeue
= xhci_mask64(trb
->parameter
);
994 if (trb
->control
& TRB_LK_TC
) {
995 ring
->ccs
= !ring
->ccs
;
1001 static int xhci_ring_chain_length(XHCIState
*xhci
, const XHCIRing
*ring
)
1003 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
1006 dma_addr_t dequeue
= ring
->dequeue
;
1007 bool ccs
= ring
->ccs
;
1008 /* hack to bundle together the two/three TDs that make a setup transfer */
1009 bool control_td_set
= 0;
1013 pci_dma_read(pci_dev
, dequeue
, &trb
, TRB_SIZE
);
1014 le64_to_cpus(&trb
.parameter
);
1015 le32_to_cpus(&trb
.status
);
1016 le32_to_cpus(&trb
.control
);
1018 if ((trb
.control
& TRB_C
) != ccs
) {
1022 type
= TRB_TYPE(trb
);
1024 if (type
== TR_LINK
) {
1025 dequeue
= xhci_mask64(trb
.parameter
);
1026 if (trb
.control
& TRB_LK_TC
) {
1033 dequeue
+= TRB_SIZE
;
1035 if (type
== TR_SETUP
) {
1037 } else if (type
== TR_STATUS
) {
1041 if (!control_td_set
&& !(trb
.control
& TRB_TR_CH
)) {
1047 static void xhci_er_reset(XHCIState
*xhci
, int v
)
1049 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
1052 if (intr
->erstsz
== 0) {
1058 /* cache the (sole) event ring segment location */
1059 if (intr
->erstsz
!= 1) {
1060 fprintf(stderr
, "xhci: invalid value for ERSTSZ: %d\n", intr
->erstsz
);
1064 dma_addr_t erstba
= xhci_addr64(intr
->erstba_low
, intr
->erstba_high
);
1065 pci_dma_read(PCI_DEVICE(xhci
), erstba
, &seg
, sizeof(seg
));
1066 le32_to_cpus(&seg
.addr_low
);
1067 le32_to_cpus(&seg
.addr_high
);
1068 le32_to_cpus(&seg
.size
);
1069 if (seg
.size
< 16 || seg
.size
> 4096) {
1070 fprintf(stderr
, "xhci: invalid value for segment size: %d\n", seg
.size
);
1074 intr
->er_start
= xhci_addr64(seg
.addr_low
, seg
.addr_high
);
1075 intr
->er_size
= seg
.size
;
1077 intr
->er_ep_idx
= 0;
1081 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT
" [%d]\n",
1082 v
, intr
->er_start
, intr
->er_size
);
1085 static void xhci_run(XHCIState
*xhci
)
1087 trace_usb_xhci_run();
1088 xhci
->usbsts
&= ~USBSTS_HCH
;
1089 xhci
->mfindex_start
= qemu_get_clock_ns(vm_clock
);
1092 static void xhci_stop(XHCIState
*xhci
)
1094 trace_usb_xhci_stop();
1095 xhci
->usbsts
|= USBSTS_HCH
;
1096 xhci
->crcr_low
&= ~CRCR_CRR
;
1099 static XHCIStreamContext
*xhci_alloc_stream_contexts(unsigned count
,
1102 XHCIStreamContext
*stctx
;
1105 stctx
= g_new0(XHCIStreamContext
, count
);
1106 for (i
= 0; i
< count
; i
++) {
1107 stctx
[i
].pctx
= base
+ i
* 16;
1113 static void xhci_reset_streams(XHCIEPContext
*epctx
)
1117 for (i
= 0; i
< epctx
->nr_pstreams
; i
++) {
1118 epctx
->pstreams
[i
].sct
= -1;
1119 g_free(epctx
->pstreams
[i
].sstreams
);
1123 static void xhci_alloc_streams(XHCIEPContext
*epctx
, dma_addr_t base
)
1125 assert(epctx
->pstreams
== NULL
);
1126 epctx
->nr_pstreams
= 2 << epctx
->max_pstreams
;
1127 epctx
->pstreams
= xhci_alloc_stream_contexts(epctx
->nr_pstreams
, base
);
1130 static void xhci_free_streams(XHCIEPContext
*epctx
)
1134 assert(epctx
->pstreams
!= NULL
);
1137 for (i
= 0; i
< epctx
->nr_pstreams
; i
++) {
1138 g_free(epctx
->pstreams
[i
].sstreams
);
1141 g_free(epctx
->pstreams
);
1142 epctx
->pstreams
= NULL
;
1143 epctx
->nr_pstreams
= 0;
1146 static XHCIStreamContext
*xhci_find_stream(XHCIEPContext
*epctx
,
1147 unsigned int streamid
,
1150 XHCIStreamContext
*sctx
;
1152 uint32_t ctx
[2], sct
;
1154 assert(streamid
!= 0);
1156 if (streamid
>= epctx
->nr_pstreams
) {
1157 *cc_error
= CC_INVALID_STREAM_ID_ERROR
;
1160 sctx
= epctx
->pstreams
+ streamid
;
1162 FIXME("secondary streams not implemented yet");
1165 if (sctx
->sct
== -1) {
1166 xhci_dma_read_u32s(epctx
->xhci
, sctx
->pctx
, ctx
, sizeof(ctx
));
1167 fprintf(stderr
, "%s: init sctx #%d @ " DMA_ADDR_FMT
": %08x %08x\n",
1168 __func__
, streamid
, sctx
->pctx
, ctx
[0], ctx
[1]);
1169 sct
= (ctx
[0] >> 1) & 0x07;
1170 if (epctx
->lsa
&& sct
!= 1) {
1171 *cc_error
= CC_INVALID_STREAM_TYPE_ERROR
;
1175 base
= xhci_addr64(ctx
[0] & ~0xf, ctx
[1]);
1176 xhci_ring_init(epctx
->xhci
, &sctx
->ring
, base
);
1181 static void xhci_set_ep_state(XHCIState
*xhci
, XHCIEPContext
*epctx
,
1182 XHCIStreamContext
*sctx
, uint32_t state
)
1187 xhci_dma_read_u32s(xhci
, epctx
->pctx
, ctx
, sizeof(ctx
));
1188 ctx
[0] &= ~EP_STATE_MASK
;
1191 /* update ring dequeue ptr */
1192 if (epctx
->nr_pstreams
) {
1194 xhci_dma_read_u32s(xhci
, sctx
->pctx
, ctx2
, sizeof(ctx2
));
1196 ctx2
[0] |= sctx
->ring
.dequeue
| sctx
->ring
.ccs
;
1197 ctx2
[1] = (sctx
->ring
.dequeue
>> 16) >> 16;
1198 xhci_dma_write_u32s(xhci
, sctx
->pctx
, ctx2
, sizeof(ctx2
));
1201 ctx
[2] = epctx
->ring
.dequeue
| epctx
->ring
.ccs
;
1202 ctx
[3] = (epctx
->ring
.dequeue
>> 16) >> 16;
1203 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT
" state=%d dequeue=%08x%08x\n",
1204 epctx
->pctx
, state
, ctx
[3], ctx
[2]);
1207 xhci_dma_write_u32s(xhci
, epctx
->pctx
, ctx
, sizeof(ctx
));
1208 epctx
->state
= state
;
1211 static void xhci_ep_kick_timer(void *opaque
)
1213 XHCIEPContext
*epctx
= opaque
;
1214 xhci_kick_ep(epctx
->xhci
, epctx
->slotid
, epctx
->epid
, 0);
1217 static XHCIEPContext
*xhci_alloc_epctx(XHCIState
*xhci
,
1218 unsigned int slotid
,
1221 XHCIEPContext
*epctx
;
1224 epctx
= g_new0(XHCIEPContext
, 1);
1226 epctx
->slotid
= slotid
;
1229 for (i
= 0; i
< ARRAY_SIZE(epctx
->transfers
); i
++) {
1230 usb_packet_init(&epctx
->transfers
[i
].packet
);
1232 epctx
->kick_timer
= qemu_new_timer_ns(vm_clock
, xhci_ep_kick_timer
, epctx
);
1237 static void xhci_init_epctx(XHCIEPContext
*epctx
,
1238 dma_addr_t pctx
, uint32_t *ctx
)
1242 dequeue
= xhci_addr64(ctx
[2] & ~0xf, ctx
[3]);
1244 epctx
->type
= (ctx
[1] >> EP_TYPE_SHIFT
) & EP_TYPE_MASK
;
1245 DPRINTF("xhci: endpoint %d.%d type is %d\n", epid
/2, epid
%2, epctx
->type
);
1247 epctx
->max_psize
= ctx
[1]>>16;
1248 epctx
->max_psize
*= 1+((ctx
[1]>>8)&0xff);
1249 epctx
->max_pstreams
= (ctx
[0] >> 10) & 0xf;
1250 epctx
->lsa
= (ctx
[0] >> 15) & 1;
1251 DPRINTF("xhci: endpoint %d.%d max transaction (burst) size is %d\n",
1252 epid
/2, epid
%2, epctx
->max_psize
);
1253 if (epctx
->max_pstreams
) {
1254 xhci_alloc_streams(epctx
, dequeue
);
1256 xhci_ring_init(epctx
->xhci
, &epctx
->ring
, dequeue
);
1257 epctx
->ring
.ccs
= ctx
[2] & 1;
1260 epctx
->interval
= 1 << (ctx
[0] >> 16) & 0xff;
1263 static TRBCCode
xhci_enable_ep(XHCIState
*xhci
, unsigned int slotid
,
1264 unsigned int epid
, dma_addr_t pctx
,
1268 XHCIEPContext
*epctx
;
1270 trace_usb_xhci_ep_enable(slotid
, epid
);
1271 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1272 assert(epid
>= 1 && epid
<= 31);
1274 slot
= &xhci
->slots
[slotid
-1];
1275 if (slot
->eps
[epid
-1]) {
1276 xhci_disable_ep(xhci
, slotid
, epid
);
1279 epctx
= xhci_alloc_epctx(xhci
, slotid
, epid
);
1280 slot
->eps
[epid
-1] = epctx
;
1281 xhci_init_epctx(epctx
, pctx
, ctx
);
1283 epctx
->mfindex_last
= 0;
1285 epctx
->state
= EP_RUNNING
;
1286 ctx
[0] &= ~EP_STATE_MASK
;
1287 ctx
[0] |= EP_RUNNING
;
1292 static int xhci_ep_nuke_one_xfer(XHCITransfer
*t
)
1296 if (t
->running_async
) {
1297 usb_cancel_packet(&t
->packet
);
1298 t
->running_async
= 0;
1300 DPRINTF("xhci: cancelling transfer, waiting for it to complete\n");
1303 if (t
->running_retry
) {
1304 XHCIEPContext
*epctx
= t
->xhci
->slots
[t
->slotid
-1].eps
[t
->epid
-1];
1306 epctx
->retry
= NULL
;
1307 qemu_del_timer(epctx
->kick_timer
);
1309 t
->running_retry
= 0;
1316 t
->trb_count
= t
->trb_alloced
= 0;
1321 static int xhci_ep_nuke_xfers(XHCIState
*xhci
, unsigned int slotid
,
1325 XHCIEPContext
*epctx
;
1326 int i
, xferi
, killed
= 0;
1327 USBEndpoint
*ep
= NULL
;
1328 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1329 assert(epid
>= 1 && epid
<= 31);
1331 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid
, epid
);
1333 slot
= &xhci
->slots
[slotid
-1];
1335 if (!slot
->eps
[epid
-1]) {
1339 epctx
= slot
->eps
[epid
-1];
1341 xferi
= epctx
->next_xfer
;
1342 for (i
= 0; i
< TD_QUEUE
; i
++) {
1343 if (epctx
->transfers
[xferi
].packet
.ep
) {
1344 ep
= epctx
->transfers
[xferi
].packet
.ep
;
1346 killed
+= xhci_ep_nuke_one_xfer(&epctx
->transfers
[xferi
]);
1347 epctx
->transfers
[xferi
].packet
.ep
= NULL
;
1348 xferi
= (xferi
+ 1) % TD_QUEUE
;
1351 usb_device_ep_stopped(ep
->dev
, ep
);
1356 static TRBCCode
xhci_disable_ep(XHCIState
*xhci
, unsigned int slotid
,
1360 XHCIEPContext
*epctx
;
1362 trace_usb_xhci_ep_disable(slotid
, epid
);
1363 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1364 assert(epid
>= 1 && epid
<= 31);
1366 slot
= &xhci
->slots
[slotid
-1];
1368 if (!slot
->eps
[epid
-1]) {
1369 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid
, epid
);
1373 xhci_ep_nuke_xfers(xhci
, slotid
, epid
);
1375 epctx
= slot
->eps
[epid
-1];
1377 if (epctx
->nr_pstreams
) {
1378 xhci_free_streams(epctx
);
1381 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_DISABLED
);
1383 qemu_free_timer(epctx
->kick_timer
);
1385 slot
->eps
[epid
-1] = NULL
;
1390 static TRBCCode
xhci_stop_ep(XHCIState
*xhci
, unsigned int slotid
,
1394 XHCIEPContext
*epctx
;
1396 trace_usb_xhci_ep_stop(slotid
, epid
);
1397 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1399 if (epid
< 1 || epid
> 31) {
1400 fprintf(stderr
, "xhci: bad ep %d\n", epid
);
1401 return CC_TRB_ERROR
;
1404 slot
= &xhci
->slots
[slotid
-1];
1406 if (!slot
->eps
[epid
-1]) {
1407 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1408 return CC_EP_NOT_ENABLED_ERROR
;
1411 if (xhci_ep_nuke_xfers(xhci
, slotid
, epid
) > 0) {
1412 fprintf(stderr
, "xhci: FIXME: endpoint stopped w/ xfers running, "
1413 "data might be lost\n");
1416 epctx
= slot
->eps
[epid
-1];
1418 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_STOPPED
);
1420 if (epctx
->nr_pstreams
) {
1421 xhci_reset_streams(epctx
);
1427 static TRBCCode
xhci_reset_ep(XHCIState
*xhci
, unsigned int slotid
,
1431 XHCIEPContext
*epctx
;
1434 trace_usb_xhci_ep_reset(slotid
, epid
);
1435 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1437 if (epid
< 1 || epid
> 31) {
1438 fprintf(stderr
, "xhci: bad ep %d\n", epid
);
1439 return CC_TRB_ERROR
;
1442 slot
= &xhci
->slots
[slotid
-1];
1444 if (!slot
->eps
[epid
-1]) {
1445 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1446 return CC_EP_NOT_ENABLED_ERROR
;
1449 epctx
= slot
->eps
[epid
-1];
1451 if (epctx
->state
!= EP_HALTED
) {
1452 fprintf(stderr
, "xhci: reset EP while EP %d not halted (%d)\n",
1453 epid
, epctx
->state
);
1454 return CC_CONTEXT_STATE_ERROR
;
1457 if (xhci_ep_nuke_xfers(xhci
, slotid
, epid
) > 0) {
1458 fprintf(stderr
, "xhci: FIXME: endpoint reset w/ xfers running, "
1459 "data might be lost\n");
1462 uint8_t ep
= epid
>>1;
1468 dev
= xhci
->slots
[slotid
-1].uport
->dev
;
1470 return CC_USB_TRANSACTION_ERROR
;
1473 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_STOPPED
);
1475 if (epctx
->nr_pstreams
) {
1476 xhci_reset_streams(epctx
);
1482 static TRBCCode
xhci_set_ep_dequeue(XHCIState
*xhci
, unsigned int slotid
,
1483 unsigned int epid
, unsigned int streamid
,
1487 XHCIEPContext
*epctx
;
1488 XHCIStreamContext
*sctx
;
1491 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1493 if (epid
< 1 || epid
> 31) {
1494 fprintf(stderr
, "xhci: bad ep %d\n", epid
);
1495 return CC_TRB_ERROR
;
1498 trace_usb_xhci_ep_set_dequeue(slotid
, epid
, streamid
, pdequeue
);
1499 dequeue
= xhci_mask64(pdequeue
);
1501 slot
= &xhci
->slots
[slotid
-1];
1503 if (!slot
->eps
[epid
-1]) {
1504 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1505 return CC_EP_NOT_ENABLED_ERROR
;
1508 epctx
= slot
->eps
[epid
-1];
1510 if (epctx
->state
!= EP_STOPPED
) {
1511 fprintf(stderr
, "xhci: set EP dequeue pointer while EP %d not stopped\n", epid
);
1512 return CC_CONTEXT_STATE_ERROR
;
1515 if (epctx
->nr_pstreams
) {
1517 sctx
= xhci_find_stream(epctx
, streamid
, &err
);
1521 xhci_ring_init(xhci
, &sctx
->ring
, dequeue
& ~0xf);
1522 sctx
->ring
.ccs
= dequeue
& 1;
1525 xhci_ring_init(xhci
, &epctx
->ring
, dequeue
& ~0xF);
1526 epctx
->ring
.ccs
= dequeue
& 1;
1529 xhci_set_ep_state(xhci
, epctx
, sctx
, EP_STOPPED
);
1534 static int xhci_xfer_create_sgl(XHCITransfer
*xfer
, int in_xfer
)
1536 XHCIState
*xhci
= xfer
->xhci
;
1539 xfer
->int_req
= false;
1540 pci_dma_sglist_init(&xfer
->sgl
, PCI_DEVICE(xhci
), xfer
->trb_count
);
1541 for (i
= 0; i
< xfer
->trb_count
; i
++) {
1542 XHCITRB
*trb
= &xfer
->trbs
[i
];
1544 unsigned int chunk
= 0;
1546 if (trb
->control
& TRB_TR_IOC
) {
1547 xfer
->int_req
= true;
1550 switch (TRB_TYPE(*trb
)) {
1552 if ((!(trb
->control
& TRB_TR_DIR
)) != (!in_xfer
)) {
1553 fprintf(stderr
, "xhci: data direction mismatch for TR_DATA\n");
1559 addr
= xhci_mask64(trb
->parameter
);
1560 chunk
= trb
->status
& 0x1ffff;
1561 if (trb
->control
& TRB_TR_IDT
) {
1562 if (chunk
> 8 || in_xfer
) {
1563 fprintf(stderr
, "xhci: invalid immediate data TRB\n");
1566 qemu_sglist_add(&xfer
->sgl
, trb
->addr
, chunk
);
1568 qemu_sglist_add(&xfer
->sgl
, addr
, chunk
);
1577 qemu_sglist_destroy(&xfer
->sgl
);
1582 static void xhci_xfer_unmap(XHCITransfer
*xfer
)
1584 usb_packet_unmap(&xfer
->packet
, &xfer
->sgl
);
1585 qemu_sglist_destroy(&xfer
->sgl
);
1588 static void xhci_xfer_report(XHCITransfer
*xfer
)
1594 XHCIEvent event
= {ER_TRANSFER
, CC_SUCCESS
};
1595 XHCIState
*xhci
= xfer
->xhci
;
1598 left
= xfer
->packet
.actual_length
;
1600 for (i
= 0; i
< xfer
->trb_count
; i
++) {
1601 XHCITRB
*trb
= &xfer
->trbs
[i
];
1602 unsigned int chunk
= 0;
1604 switch (TRB_TYPE(*trb
)) {
1608 chunk
= trb
->status
& 0x1ffff;
1611 if (xfer
->status
== CC_SUCCESS
) {
1624 if (!reported
&& ((trb
->control
& TRB_TR_IOC
) ||
1625 (shortpkt
&& (trb
->control
& TRB_TR_ISP
)) ||
1626 (xfer
->status
!= CC_SUCCESS
&& left
== 0))) {
1627 event
.slotid
= xfer
->slotid
;
1628 event
.epid
= xfer
->epid
;
1629 event
.length
= (trb
->status
& 0x1ffff) - chunk
;
1631 event
.ptr
= trb
->addr
;
1632 if (xfer
->status
== CC_SUCCESS
) {
1633 event
.ccode
= shortpkt
? CC_SHORT_PACKET
: CC_SUCCESS
;
1635 event
.ccode
= xfer
->status
;
1637 if (TRB_TYPE(*trb
) == TR_EVDATA
) {
1638 event
.ptr
= trb
->parameter
;
1639 event
.flags
|= TRB_EV_ED
;
1640 event
.length
= edtla
& 0xffffff;
1641 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event
.length
);
1644 xhci_event(xhci
, &event
, TRB_INTR(*trb
));
1646 if (xfer
->status
!= CC_SUCCESS
) {
1653 static void xhci_stall_ep(XHCITransfer
*xfer
)
1655 XHCIState
*xhci
= xfer
->xhci
;
1656 XHCISlot
*slot
= &xhci
->slots
[xfer
->slotid
-1];
1657 XHCIEPContext
*epctx
= slot
->eps
[xfer
->epid
-1];
1659 XHCIStreamContext
*sctx
;
1661 if (epctx
->nr_pstreams
) {
1662 sctx
= xhci_find_stream(epctx
, xfer
->streamid
, &err
);
1666 sctx
->ring
.dequeue
= xfer
->trbs
[0].addr
;
1667 sctx
->ring
.ccs
= xfer
->trbs
[0].ccs
;
1668 xhci_set_ep_state(xhci
, epctx
, sctx
, EP_HALTED
);
1670 epctx
->ring
.dequeue
= xfer
->trbs
[0].addr
;
1671 epctx
->ring
.ccs
= xfer
->trbs
[0].ccs
;
1672 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_HALTED
);
1676 static int xhci_submit(XHCIState
*xhci
, XHCITransfer
*xfer
,
1677 XHCIEPContext
*epctx
);
1679 static int xhci_setup_packet(XHCITransfer
*xfer
)
1681 XHCIState
*xhci
= xfer
->xhci
;
1686 dir
= xfer
->in_xfer
? USB_TOKEN_IN
: USB_TOKEN_OUT
;
1688 if (xfer
->packet
.ep
) {
1689 ep
= xfer
->packet
.ep
;
1692 if (!xhci
->slots
[xfer
->slotid
-1].uport
) {
1693 fprintf(stderr
, "xhci: slot %d has no device\n",
1697 dev
= xhci
->slots
[xfer
->slotid
-1].uport
->dev
;
1698 ep
= usb_ep_get(dev
, dir
, xfer
->epid
>> 1);
1701 xhci_xfer_create_sgl(xfer
, dir
== USB_TOKEN_IN
); /* Also sets int_req */
1702 usb_packet_setup(&xfer
->packet
, dir
, ep
, xfer
->streamid
,
1703 xfer
->trbs
[0].addr
, false, xfer
->int_req
);
1704 usb_packet_map(&xfer
->packet
, &xfer
->sgl
);
1705 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",
1706 xfer
->packet
.pid
, dev
->addr
, ep
->nr
);
1710 static int xhci_complete_packet(XHCITransfer
*xfer
)
1712 if (xfer
->packet
.status
== USB_RET_ASYNC
) {
1713 trace_usb_xhci_xfer_async(xfer
);
1714 xfer
->running_async
= 1;
1715 xfer
->running_retry
= 0;
1717 xfer
->cancelled
= 0;
1719 } else if (xfer
->packet
.status
== USB_RET_NAK
) {
1720 trace_usb_xhci_xfer_nak(xfer
);
1721 xfer
->running_async
= 0;
1722 xfer
->running_retry
= 1;
1724 xfer
->cancelled
= 0;
1727 xfer
->running_async
= 0;
1728 xfer
->running_retry
= 0;
1730 xhci_xfer_unmap(xfer
);
1733 if (xfer
->packet
.status
== USB_RET_SUCCESS
) {
1734 trace_usb_xhci_xfer_success(xfer
, xfer
->packet
.actual_length
);
1735 xfer
->status
= CC_SUCCESS
;
1736 xhci_xfer_report(xfer
);
1741 trace_usb_xhci_xfer_error(xfer
, xfer
->packet
.status
);
1742 switch (xfer
->packet
.status
) {
1744 xfer
->status
= CC_USB_TRANSACTION_ERROR
;
1745 xhci_xfer_report(xfer
);
1746 xhci_stall_ep(xfer
);
1749 xfer
->status
= CC_STALL_ERROR
;
1750 xhci_xfer_report(xfer
);
1751 xhci_stall_ep(xfer
);
1753 case USB_RET_BABBLE
:
1754 xfer
->status
= CC_BABBLE_DETECTED
;
1755 xhci_xfer_report(xfer
);
1756 xhci_stall_ep(xfer
);
1759 fprintf(stderr
, "%s: FIXME: status = %d\n", __func__
,
1760 xfer
->packet
.status
);
1761 FIXME("unhandled USB_RET_*");
1766 static int xhci_fire_ctl_transfer(XHCIState
*xhci
, XHCITransfer
*xfer
)
1768 XHCITRB
*trb_setup
, *trb_status
;
1769 uint8_t bmRequestType
;
1771 trb_setup
= &xfer
->trbs
[0];
1772 trb_status
= &xfer
->trbs
[xfer
->trb_count
-1];
1774 trace_usb_xhci_xfer_start(xfer
, xfer
->slotid
, xfer
->epid
, xfer
->streamid
);
1776 /* at most one Event Data TRB allowed after STATUS */
1777 if (TRB_TYPE(*trb_status
) == TR_EVDATA
&& xfer
->trb_count
> 2) {
1781 /* do some sanity checks */
1782 if (TRB_TYPE(*trb_setup
) != TR_SETUP
) {
1783 fprintf(stderr
, "xhci: ep0 first TD not SETUP: %d\n",
1784 TRB_TYPE(*trb_setup
));
1787 if (TRB_TYPE(*trb_status
) != TR_STATUS
) {
1788 fprintf(stderr
, "xhci: ep0 last TD not STATUS: %d\n",
1789 TRB_TYPE(*trb_status
));
1792 if (!(trb_setup
->control
& TRB_TR_IDT
)) {
1793 fprintf(stderr
, "xhci: Setup TRB doesn't have IDT set\n");
1796 if ((trb_setup
->status
& 0x1ffff) != 8) {
1797 fprintf(stderr
, "xhci: Setup TRB has bad length (%d)\n",
1798 (trb_setup
->status
& 0x1ffff));
1802 bmRequestType
= trb_setup
->parameter
;
1804 xfer
->in_xfer
= bmRequestType
& USB_DIR_IN
;
1805 xfer
->iso_xfer
= false;
1807 if (xhci_setup_packet(xfer
) < 0) {
1810 xfer
->packet
.parameter
= trb_setup
->parameter
;
1812 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
1814 xhci_complete_packet(xfer
);
1815 if (!xfer
->running_async
&& !xfer
->running_retry
) {
1816 xhci_kick_ep(xhci
, xfer
->slotid
, xfer
->epid
, 0);
1821 static void xhci_calc_iso_kick(XHCIState
*xhci
, XHCITransfer
*xfer
,
1822 XHCIEPContext
*epctx
, uint64_t mfindex
)
1824 if (xfer
->trbs
[0].control
& TRB_TR_SIA
) {
1825 uint64_t asap
= ((mfindex
+ epctx
->interval
- 1) &
1826 ~(epctx
->interval
-1));
1827 if (asap
>= epctx
->mfindex_last
&&
1828 asap
<= epctx
->mfindex_last
+ epctx
->interval
* 4) {
1829 xfer
->mfindex_kick
= epctx
->mfindex_last
+ epctx
->interval
;
1831 xfer
->mfindex_kick
= asap
;
1834 xfer
->mfindex_kick
= (xfer
->trbs
[0].control
>> TRB_TR_FRAMEID_SHIFT
)
1835 & TRB_TR_FRAMEID_MASK
;
1836 xfer
->mfindex_kick
|= mfindex
& ~0x3fff;
1837 if (xfer
->mfindex_kick
< mfindex
) {
1838 xfer
->mfindex_kick
+= 0x4000;
1843 static void xhci_check_iso_kick(XHCIState
*xhci
, XHCITransfer
*xfer
,
1844 XHCIEPContext
*epctx
, uint64_t mfindex
)
1846 if (xfer
->mfindex_kick
> mfindex
) {
1847 qemu_mod_timer(epctx
->kick_timer
, qemu_get_clock_ns(vm_clock
) +
1848 (xfer
->mfindex_kick
- mfindex
) * 125000);
1849 xfer
->running_retry
= 1;
1851 epctx
->mfindex_last
= xfer
->mfindex_kick
;
1852 qemu_del_timer(epctx
->kick_timer
);
1853 xfer
->running_retry
= 0;
1858 static int xhci_submit(XHCIState
*xhci
, XHCITransfer
*xfer
, XHCIEPContext
*epctx
)
1862 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer
->slotid
, xfer
->epid
);
1864 xfer
->in_xfer
= epctx
->type
>>2;
1866 switch(epctx
->type
) {
1872 xfer
->iso_xfer
= false;
1877 xfer
->iso_xfer
= true;
1878 mfindex
= xhci_mfindex_get(xhci
);
1879 xhci_calc_iso_kick(xhci
, xfer
, epctx
, mfindex
);
1880 xhci_check_iso_kick(xhci
, xfer
, epctx
, mfindex
);
1881 if (xfer
->running_retry
) {
1886 fprintf(stderr
, "xhci: unknown or unhandled EP "
1887 "(type %d, in %d, ep %02x)\n",
1888 epctx
->type
, xfer
->in_xfer
, xfer
->epid
);
1892 if (xhci_setup_packet(xfer
) < 0) {
1895 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
1897 xhci_complete_packet(xfer
);
1898 if (!xfer
->running_async
&& !xfer
->running_retry
) {
1899 xhci_kick_ep(xhci
, xfer
->slotid
, xfer
->epid
, xfer
->streamid
);
1904 static int xhci_fire_transfer(XHCIState
*xhci
, XHCITransfer
*xfer
, XHCIEPContext
*epctx
)
1906 trace_usb_xhci_xfer_start(xfer
, xfer
->slotid
, xfer
->epid
, xfer
->streamid
);
1907 return xhci_submit(xhci
, xfer
, epctx
);
1910 static void xhci_kick_ep(XHCIState
*xhci
, unsigned int slotid
,
1911 unsigned int epid
, unsigned int streamid
)
1913 XHCIStreamContext
*stctx
;
1914 XHCIEPContext
*epctx
;
1916 USBEndpoint
*ep
= NULL
;
1921 trace_usb_xhci_ep_kick(slotid
, epid
, streamid
);
1922 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1923 assert(epid
>= 1 && epid
<= 31);
1925 if (!xhci
->slots
[slotid
-1].enabled
) {
1926 fprintf(stderr
, "xhci: xhci_kick_ep for disabled slot %d\n", slotid
);
1929 epctx
= xhci
->slots
[slotid
-1].eps
[epid
-1];
1931 fprintf(stderr
, "xhci: xhci_kick_ep for disabled endpoint %d,%d\n",
1937 XHCITransfer
*xfer
= epctx
->retry
;
1939 trace_usb_xhci_xfer_retry(xfer
);
1940 assert(xfer
->running_retry
);
1941 if (xfer
->iso_xfer
) {
1942 /* retry delayed iso transfer */
1943 mfindex
= xhci_mfindex_get(xhci
);
1944 xhci_check_iso_kick(xhci
, xfer
, epctx
, mfindex
);
1945 if (xfer
->running_retry
) {
1948 if (xhci_setup_packet(xfer
) < 0) {
1951 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
1952 assert(xfer
->packet
.status
!= USB_RET_NAK
);
1953 xhci_complete_packet(xfer
);
1955 /* retry nak'ed transfer */
1956 if (xhci_setup_packet(xfer
) < 0) {
1959 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
1960 if (xfer
->packet
.status
== USB_RET_NAK
) {
1963 xhci_complete_packet(xfer
);
1965 assert(!xfer
->running_retry
);
1966 epctx
->retry
= NULL
;
1969 if (epctx
->state
== EP_HALTED
) {
1970 DPRINTF("xhci: ep halted, not running schedule\n");
1975 if (epctx
->nr_pstreams
) {
1977 stctx
= xhci_find_stream(epctx
, streamid
, &err
);
1978 if (stctx
== NULL
) {
1981 ring
= &stctx
->ring
;
1982 xhci_set_ep_state(xhci
, epctx
, stctx
, EP_RUNNING
);
1984 ring
= &epctx
->ring
;
1986 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_RUNNING
);
1988 assert(ring
->dequeue
!= 0);
1991 XHCITransfer
*xfer
= &epctx
->transfers
[epctx
->next_xfer
];
1992 if (xfer
->running_async
|| xfer
->running_retry
) {
1995 length
= xhci_ring_chain_length(xhci
, ring
);
1998 } else if (length
== 0) {
2001 if (xfer
->trbs
&& xfer
->trb_alloced
< length
) {
2002 xfer
->trb_count
= 0;
2003 xfer
->trb_alloced
= 0;
2008 xfer
->trbs
= g_malloc(sizeof(XHCITRB
) * length
);
2009 xfer
->trb_alloced
= length
;
2011 xfer
->trb_count
= length
;
2013 for (i
= 0; i
< length
; i
++) {
2014 assert(xhci_ring_fetch(xhci
, ring
, &xfer
->trbs
[i
], NULL
));
2018 xfer
->slotid
= slotid
;
2019 xfer
->streamid
= streamid
;
2022 if (xhci_fire_ctl_transfer(xhci
, xfer
) >= 0) {
2023 epctx
->next_xfer
= (epctx
->next_xfer
+ 1) % TD_QUEUE
;
2024 ep
= xfer
->packet
.ep
;
2026 fprintf(stderr
, "xhci: error firing CTL transfer\n");
2029 if (xhci_fire_transfer(xhci
, xfer
, epctx
) >= 0) {
2030 epctx
->next_xfer
= (epctx
->next_xfer
+ 1) % TD_QUEUE
;
2031 ep
= xfer
->packet
.ep
;
2033 if (!xfer
->iso_xfer
) {
2034 fprintf(stderr
, "xhci: error firing data transfer\n");
2039 if (epctx
->state
== EP_HALTED
) {
2042 if (xfer
->running_retry
) {
2043 DPRINTF("xhci: xfer nacked, stopping schedule\n");
2044 epctx
->retry
= xfer
;
2049 usb_device_flush_ep_queue(ep
->dev
, ep
);
2053 static TRBCCode
xhci_enable_slot(XHCIState
*xhci
, unsigned int slotid
)
2055 trace_usb_xhci_slot_enable(slotid
);
2056 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2057 xhci
->slots
[slotid
-1].enabled
= 1;
2058 xhci
->slots
[slotid
-1].uport
= NULL
;
2059 memset(xhci
->slots
[slotid
-1].eps
, 0, sizeof(XHCIEPContext
*)*31);
2064 static TRBCCode
xhci_disable_slot(XHCIState
*xhci
, unsigned int slotid
)
2068 trace_usb_xhci_slot_disable(slotid
);
2069 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2071 for (i
= 1; i
<= 31; i
++) {
2072 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
2073 xhci_disable_ep(xhci
, slotid
, i
);
2077 xhci
->slots
[slotid
-1].enabled
= 0;
2078 xhci
->slots
[slotid
-1].addressed
= 0;
2082 static USBPort
*xhci_lookup_uport(XHCIState
*xhci
, uint32_t *slot_ctx
)
2088 port
= (slot_ctx
[1]>>16) & 0xFF;
2089 port
= xhci
->ports
[port
-1].uport
->index
+1;
2090 pos
= snprintf(path
, sizeof(path
), "%d", port
);
2091 for (i
= 0; i
< 5; i
++) {
2092 port
= (slot_ctx
[0] >> 4*i
) & 0x0f;
2096 pos
+= snprintf(path
+ pos
, sizeof(path
) - pos
, ".%d", port
);
2099 QTAILQ_FOREACH(uport
, &xhci
->bus
.used
, next
) {
2100 if (strcmp(uport
->path
, path
) == 0) {
2107 static TRBCCode
xhci_address_slot(XHCIState
*xhci
, unsigned int slotid
,
2108 uint64_t pictx
, bool bsr
)
2113 dma_addr_t ictx
, octx
, dcbaap
;
2115 uint32_t ictl_ctx
[2];
2116 uint32_t slot_ctx
[4];
2117 uint32_t ep0_ctx
[5];
2121 trace_usb_xhci_slot_address(slotid
);
2122 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2124 dcbaap
= xhci_addr64(xhci
->dcbaap_low
, xhci
->dcbaap_high
);
2125 poctx
= ldq_le_pci_dma(PCI_DEVICE(xhci
), dcbaap
+ 8 * slotid
);
2126 ictx
= xhci_mask64(pictx
);
2127 octx
= xhci_mask64(poctx
);
2129 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
2130 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2132 xhci_dma_read_u32s(xhci
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
2134 if (ictl_ctx
[0] != 0x0 || ictl_ctx
[1] != 0x3) {
2135 fprintf(stderr
, "xhci: invalid input context control %08x %08x\n",
2136 ictl_ctx
[0], ictl_ctx
[1]);
2137 return CC_TRB_ERROR
;
2140 xhci_dma_read_u32s(xhci
, ictx
+32, slot_ctx
, sizeof(slot_ctx
));
2141 xhci_dma_read_u32s(xhci
, ictx
+64, ep0_ctx
, sizeof(ep0_ctx
));
2143 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2144 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2146 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2147 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
2149 uport
= xhci_lookup_uport(xhci
, slot_ctx
);
2150 if (uport
== NULL
) {
2151 fprintf(stderr
, "xhci: port not found\n");
2152 return CC_TRB_ERROR
;
2157 fprintf(stderr
, "xhci: port %s not connected\n", uport
->path
);
2158 return CC_USB_TRANSACTION_ERROR
;
2161 for (i
= 0; i
< xhci
->numslots
; i
++) {
2162 if (i
== slotid
-1) {
2165 if (xhci
->slots
[i
].uport
== uport
) {
2166 fprintf(stderr
, "xhci: port %s already assigned to slot %d\n",
2168 return CC_TRB_ERROR
;
2172 slot
= &xhci
->slots
[slotid
-1];
2173 slot
->uport
= uport
;
2177 slot_ctx
[3] = SLOT_DEFAULT
<< SLOT_STATE_SHIFT
;
2182 slot_ctx
[3] = (SLOT_ADDRESSED
<< SLOT_STATE_SHIFT
) | slotid
;
2183 usb_device_reset(dev
);
2184 memset(&p
, 0, sizeof(p
));
2185 usb_packet_addbuf(&p
, buf
, sizeof(buf
));
2186 usb_packet_setup(&p
, USB_TOKEN_OUT
,
2187 usb_ep_get(dev
, USB_TOKEN_OUT
, 0), 0,
2189 usb_device_handle_control(dev
, &p
,
2190 DeviceOutRequest
| USB_REQ_SET_ADDRESS
,
2191 slotid
, 0, 0, NULL
);
2192 assert(p
.status
!= USB_RET_ASYNC
);
2195 res
= xhci_enable_ep(xhci
, slotid
, 1, octx
+32, ep0_ctx
);
2197 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2198 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2199 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2200 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
2202 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2203 xhci_dma_write_u32s(xhci
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
2205 xhci
->slots
[slotid
-1].addressed
= 1;
2210 static TRBCCode
xhci_configure_slot(XHCIState
*xhci
, unsigned int slotid
,
2211 uint64_t pictx
, bool dc
)
2213 dma_addr_t ictx
, octx
;
2214 uint32_t ictl_ctx
[2];
2215 uint32_t slot_ctx
[4];
2216 uint32_t islot_ctx
[4];
2221 trace_usb_xhci_slot_configure(slotid
);
2222 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2224 ictx
= xhci_mask64(pictx
);
2225 octx
= xhci
->slots
[slotid
-1].ctx
;
2227 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
2228 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2231 for (i
= 2; i
<= 31; i
++) {
2232 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
2233 xhci_disable_ep(xhci
, slotid
, i
);
2237 xhci_dma_read_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2238 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
2239 slot_ctx
[3] |= SLOT_ADDRESSED
<< SLOT_STATE_SHIFT
;
2240 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2241 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2242 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2247 xhci_dma_read_u32s(xhci
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
2249 if ((ictl_ctx
[0] & 0x3) != 0x0 || (ictl_ctx
[1] & 0x3) != 0x1) {
2250 fprintf(stderr
, "xhci: invalid input context control %08x %08x\n",
2251 ictl_ctx
[0], ictl_ctx
[1]);
2252 return CC_TRB_ERROR
;
2255 xhci_dma_read_u32s(xhci
, ictx
+32, islot_ctx
, sizeof(islot_ctx
));
2256 xhci_dma_read_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2258 if (SLOT_STATE(slot_ctx
[3]) < SLOT_ADDRESSED
) {
2259 fprintf(stderr
, "xhci: invalid slot state %08x\n", slot_ctx
[3]);
2260 return CC_CONTEXT_STATE_ERROR
;
2263 for (i
= 2; i
<= 31; i
++) {
2264 if (ictl_ctx
[0] & (1<<i
)) {
2265 xhci_disable_ep(xhci
, slotid
, i
);
2267 if (ictl_ctx
[1] & (1<<i
)) {
2268 xhci_dma_read_u32s(xhci
, ictx
+32+(32*i
), ep_ctx
, sizeof(ep_ctx
));
2269 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",
2270 i
/2, i
%2, ep_ctx
[0], ep_ctx
[1], ep_ctx
[2],
2271 ep_ctx
[3], ep_ctx
[4]);
2272 xhci_disable_ep(xhci
, slotid
, i
);
2273 res
= xhci_enable_ep(xhci
, slotid
, i
, octx
+(32*i
), ep_ctx
);
2274 if (res
!= CC_SUCCESS
) {
2277 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",
2278 i
/2, i
%2, ep_ctx
[0], ep_ctx
[1], ep_ctx
[2],
2279 ep_ctx
[3], ep_ctx
[4]);
2280 xhci_dma_write_u32s(xhci
, octx
+(32*i
), ep_ctx
, sizeof(ep_ctx
));
2284 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
2285 slot_ctx
[3] |= SLOT_CONFIGURED
<< SLOT_STATE_SHIFT
;
2286 slot_ctx
[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK
<< SLOT_CONTEXT_ENTRIES_SHIFT
);
2287 slot_ctx
[0] |= islot_ctx
[0] & (SLOT_CONTEXT_ENTRIES_MASK
<<
2288 SLOT_CONTEXT_ENTRIES_SHIFT
);
2289 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2290 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2292 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2298 static TRBCCode
xhci_evaluate_slot(XHCIState
*xhci
, unsigned int slotid
,
2301 dma_addr_t ictx
, octx
;
2302 uint32_t ictl_ctx
[2];
2303 uint32_t iep0_ctx
[5];
2304 uint32_t ep0_ctx
[5];
2305 uint32_t islot_ctx
[4];
2306 uint32_t slot_ctx
[4];
2308 trace_usb_xhci_slot_evaluate(slotid
);
2309 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2311 ictx
= xhci_mask64(pictx
);
2312 octx
= xhci
->slots
[slotid
-1].ctx
;
2314 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
2315 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2317 xhci_dma_read_u32s(xhci
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
2319 if (ictl_ctx
[0] != 0x0 || ictl_ctx
[1] & ~0x3) {
2320 fprintf(stderr
, "xhci: invalid input context control %08x %08x\n",
2321 ictl_ctx
[0], ictl_ctx
[1]);
2322 return CC_TRB_ERROR
;
2325 if (ictl_ctx
[1] & 0x1) {
2326 xhci_dma_read_u32s(xhci
, ictx
+32, islot_ctx
, sizeof(islot_ctx
));
2328 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2329 islot_ctx
[0], islot_ctx
[1], islot_ctx
[2], islot_ctx
[3]);
2331 xhci_dma_read_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2333 slot_ctx
[1] &= ~0xFFFF; /* max exit latency */
2334 slot_ctx
[1] |= islot_ctx
[1] & 0xFFFF;
2335 slot_ctx
[2] &= ~0xFF00000; /* interrupter target */
2336 slot_ctx
[2] |= islot_ctx
[2] & 0xFF000000;
2338 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2339 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2341 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2344 if (ictl_ctx
[1] & 0x2) {
2345 xhci_dma_read_u32s(xhci
, ictx
+64, iep0_ctx
, sizeof(iep0_ctx
));
2347 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2348 iep0_ctx
[0], iep0_ctx
[1], iep0_ctx
[2],
2349 iep0_ctx
[3], iep0_ctx
[4]);
2351 xhci_dma_read_u32s(xhci
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
2353 ep0_ctx
[1] &= ~0xFFFF0000; /* max packet size*/
2354 ep0_ctx
[1] |= iep0_ctx
[1] & 0xFFFF0000;
2356 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2357 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
2359 xhci_dma_write_u32s(xhci
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
2365 static TRBCCode
xhci_reset_slot(XHCIState
*xhci
, unsigned int slotid
)
2367 uint32_t slot_ctx
[4];
2371 trace_usb_xhci_slot_reset(slotid
);
2372 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2374 octx
= xhci
->slots
[slotid
-1].ctx
;
2376 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2378 for (i
= 2; i
<= 31; i
++) {
2379 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
2380 xhci_disable_ep(xhci
, slotid
, i
);
2384 xhci_dma_read_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2385 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
2386 slot_ctx
[3] |= SLOT_DEFAULT
<< SLOT_STATE_SHIFT
;
2387 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2388 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2389 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2394 static unsigned int xhci_get_slot(XHCIState
*xhci
, XHCIEvent
*event
, XHCITRB
*trb
)
2396 unsigned int slotid
;
2397 slotid
= (trb
->control
>> TRB_CR_SLOTID_SHIFT
) & TRB_CR_SLOTID_MASK
;
2398 if (slotid
< 1 || slotid
> xhci
->numslots
) {
2399 fprintf(stderr
, "xhci: bad slot id %d\n", slotid
);
2400 event
->ccode
= CC_TRB_ERROR
;
2402 } else if (!xhci
->slots
[slotid
-1].enabled
) {
2403 fprintf(stderr
, "xhci: slot id %d not enabled\n", slotid
);
2404 event
->ccode
= CC_SLOT_NOT_ENABLED_ERROR
;
2410 /* cleanup slot state on usb device detach */
2411 static void xhci_detach_slot(XHCIState
*xhci
, USBPort
*uport
)
2415 for (slot
= 0; slot
< xhci
->numslots
; slot
++) {
2416 if (xhci
->slots
[slot
].uport
== uport
) {
2420 if (slot
== xhci
->numslots
) {
2424 for (ep
= 0; ep
< 31; ep
++) {
2425 if (xhci
->slots
[slot
].eps
[ep
]) {
2426 xhci_ep_nuke_xfers(xhci
, slot
+1, ep
+1);
2429 xhci
->slots
[slot
].uport
= NULL
;
2432 static TRBCCode
xhci_get_port_bandwidth(XHCIState
*xhci
, uint64_t pctx
)
2435 uint8_t bw_ctx
[xhci
->numports
+1];
2437 DPRINTF("xhci_get_port_bandwidth()\n");
2439 ctx
= xhci_mask64(pctx
);
2441 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT
"\n", ctx
);
2443 /* TODO: actually implement real values here */
2445 memset(&bw_ctx
[1], 80, xhci
->numports
); /* 80% */
2446 pci_dma_write(PCI_DEVICE(xhci
), ctx
, bw_ctx
, sizeof(bw_ctx
));
2451 static uint32_t rotl(uint32_t v
, unsigned count
)
2454 return (v
<< count
) | (v
>> (32 - count
));
2458 static uint32_t xhci_nec_challenge(uint32_t hi
, uint32_t lo
)
2461 val
= rotl(lo
- 0x49434878, 32 - ((hi
>>8) & 0x1F));
2462 val
+= rotl(lo
+ 0x49434878, hi
& 0x1F);
2463 val
-= rotl(hi
^ 0x49434878, (lo
>> 16) & 0x1F);
2467 static void xhci_via_challenge(XHCIState
*xhci
, uint64_t addr
)
2469 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
2472 dma_addr_t paddr
= xhci_mask64(addr
);
2474 pci_dma_read(pci_dev
, paddr
, &buf
, 32);
2476 memcpy(obuf
, buf
, sizeof(obuf
));
2478 if ((buf
[0] & 0xff) == 2) {
2479 obuf
[0] = 0x49932000 + 0x54dc200 * buf
[2] + 0x7429b578 * buf
[3];
2480 obuf
[0] |= (buf
[2] * buf
[3]) & 0xff;
2481 obuf
[1] = 0x0132bb37 + 0xe89 * buf
[2] + 0xf09 * buf
[3];
2482 obuf
[2] = 0x0066c2e9 + 0x2091 * buf
[2] + 0x19bd * buf
[3];
2483 obuf
[3] = 0xd5281342 + 0x2cc9691 * buf
[2] + 0x2367662 * buf
[3];
2484 obuf
[4] = 0x0123c75c + 0x1595 * buf
[2] + 0x19ec * buf
[3];
2485 obuf
[5] = 0x00f695de + 0x26fd * buf
[2] + 0x3e9 * buf
[3];
2486 obuf
[6] = obuf
[2] ^ obuf
[3] ^ 0x29472956;
2487 obuf
[7] = obuf
[2] ^ obuf
[3] ^ 0x65866593;
2490 pci_dma_write(pci_dev
, paddr
, &obuf
, 32);
2493 static void xhci_process_commands(XHCIState
*xhci
)
2497 XHCIEvent event
= {ER_COMMAND_COMPLETE
, CC_SUCCESS
};
2499 unsigned int i
, slotid
= 0;
2501 DPRINTF("xhci_process_commands()\n");
2502 if (!xhci_running(xhci
)) {
2503 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n");
2507 xhci
->crcr_low
|= CRCR_CRR
;
2509 while ((type
= xhci_ring_fetch(xhci
, &xhci
->cmd_ring
, &trb
, &addr
))) {
2512 case CR_ENABLE_SLOT
:
2513 for (i
= 0; i
< xhci
->numslots
; i
++) {
2514 if (!xhci
->slots
[i
].enabled
) {
2518 if (i
>= xhci
->numslots
) {
2519 fprintf(stderr
, "xhci: no device slots available\n");
2520 event
.ccode
= CC_NO_SLOTS_ERROR
;
2523 event
.ccode
= xhci_enable_slot(xhci
, slotid
);
2526 case CR_DISABLE_SLOT
:
2527 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2529 event
.ccode
= xhci_disable_slot(xhci
, slotid
);
2532 case CR_ADDRESS_DEVICE
:
2533 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2535 event
.ccode
= xhci_address_slot(xhci
, slotid
, trb
.parameter
,
2536 trb
.control
& TRB_CR_BSR
);
2539 case CR_CONFIGURE_ENDPOINT
:
2540 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2542 event
.ccode
= xhci_configure_slot(xhci
, slotid
, trb
.parameter
,
2543 trb
.control
& TRB_CR_DC
);
2546 case CR_EVALUATE_CONTEXT
:
2547 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2549 event
.ccode
= xhci_evaluate_slot(xhci
, slotid
, trb
.parameter
);
2552 case CR_STOP_ENDPOINT
:
2553 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2555 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2557 event
.ccode
= xhci_stop_ep(xhci
, slotid
, epid
);
2560 case CR_RESET_ENDPOINT
:
2561 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2563 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2565 event
.ccode
= xhci_reset_ep(xhci
, slotid
, epid
);
2568 case CR_SET_TR_DEQUEUE
:
2569 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2571 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2573 unsigned int streamid
= (trb
.status
>> 16) & 0xffff;
2574 event
.ccode
= xhci_set_ep_dequeue(xhci
, slotid
,
2579 case CR_RESET_DEVICE
:
2580 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2582 event
.ccode
= xhci_reset_slot(xhci
, slotid
);
2585 case CR_GET_PORT_BANDWIDTH
:
2586 event
.ccode
= xhci_get_port_bandwidth(xhci
, trb
.parameter
);
2588 case CR_VENDOR_VIA_CHALLENGE_RESPONSE
:
2589 xhci_via_challenge(xhci
, trb
.parameter
);
2591 case CR_VENDOR_NEC_FIRMWARE_REVISION
:
2592 event
.type
= 48; /* NEC reply */
2593 event
.length
= 0x3025;
2595 case CR_VENDOR_NEC_CHALLENGE_RESPONSE
:
2597 uint32_t chi
= trb
.parameter
>> 32;
2598 uint32_t clo
= trb
.parameter
;
2599 uint32_t val
= xhci_nec_challenge(chi
, clo
);
2600 event
.length
= val
& 0xFFFF;
2601 event
.epid
= val
>> 16;
2603 event
.type
= 48; /* NEC reply */
2607 trace_usb_xhci_unimplemented("command", type
);
2608 event
.ccode
= CC_TRB_ERROR
;
2611 event
.slotid
= slotid
;
2612 xhci_event(xhci
, &event
, 0);
2616 static bool xhci_port_have_device(XHCIPort
*port
)
2618 if (!port
->uport
->dev
|| !port
->uport
->dev
->attached
) {
2619 return false; /* no device present */
2621 if (!((1 << port
->uport
->dev
->speed
) & port
->speedmask
)) {
2622 return false; /* speed mismatch */
2627 static void xhci_port_notify(XHCIPort
*port
, uint32_t bits
)
2629 XHCIEvent ev
= { ER_PORT_STATUS_CHANGE
, CC_SUCCESS
,
2630 port
->portnr
<< 24 };
2632 if ((port
->portsc
& bits
) == bits
) {
2635 trace_usb_xhci_port_notify(port
->portnr
, bits
);
2636 port
->portsc
|= bits
;
2637 if (!xhci_running(port
->xhci
)) {
2640 xhci_event(port
->xhci
, &ev
, 0);
2643 static void xhci_port_update(XHCIPort
*port
, int is_detach
)
2645 uint32_t pls
= PLS_RX_DETECT
;
2647 port
->portsc
= PORTSC_PP
;
2648 if (!is_detach
&& xhci_port_have_device(port
)) {
2649 port
->portsc
|= PORTSC_CCS
;
2650 switch (port
->uport
->dev
->speed
) {
2652 port
->portsc
|= PORTSC_SPEED_LOW
;
2655 case USB_SPEED_FULL
:
2656 port
->portsc
|= PORTSC_SPEED_FULL
;
2659 case USB_SPEED_HIGH
:
2660 port
->portsc
|= PORTSC_SPEED_HIGH
;
2663 case USB_SPEED_SUPER
:
2664 port
->portsc
|= PORTSC_SPEED_SUPER
;
2665 port
->portsc
|= PORTSC_PED
;
2670 set_field(&port
->portsc
, pls
, PORTSC_PLS
);
2671 trace_usb_xhci_port_link(port
->portnr
, pls
);
2672 xhci_port_notify(port
, PORTSC_CSC
);
2675 static void xhci_port_reset(XHCIPort
*port
)
2677 trace_usb_xhci_port_reset(port
->portnr
);
2679 if (!xhci_port_have_device(port
)) {
2683 usb_device_reset(port
->uport
->dev
);
2685 switch (port
->uport
->dev
->speed
) {
2687 case USB_SPEED_FULL
:
2688 case USB_SPEED_HIGH
:
2689 set_field(&port
->portsc
, PLS_U0
, PORTSC_PLS
);
2690 trace_usb_xhci_port_link(port
->portnr
, PLS_U0
);
2691 port
->portsc
|= PORTSC_PED
;
2695 port
->portsc
&= ~PORTSC_PR
;
2696 xhci_port_notify(port
, PORTSC_PRC
);
2699 static void xhci_reset(DeviceState
*dev
)
2701 XHCIState
*xhci
= XHCI(dev
);
2704 trace_usb_xhci_reset();
2705 if (!(xhci
->usbsts
& USBSTS_HCH
)) {
2706 fprintf(stderr
, "xhci: reset while running!\n");
2710 xhci
->usbsts
= USBSTS_HCH
;
2713 xhci
->crcr_high
= 0;
2714 xhci
->dcbaap_low
= 0;
2715 xhci
->dcbaap_high
= 0;
2718 for (i
= 0; i
< xhci
->numslots
; i
++) {
2719 xhci_disable_slot(xhci
, i
+1);
2722 for (i
= 0; i
< xhci
->numports
; i
++) {
2723 xhci_port_update(xhci
->ports
+ i
, 0);
2726 for (i
= 0; i
< xhci
->numintrs
; i
++) {
2727 xhci
->intr
[i
].iman
= 0;
2728 xhci
->intr
[i
].imod
= 0;
2729 xhci
->intr
[i
].erstsz
= 0;
2730 xhci
->intr
[i
].erstba_low
= 0;
2731 xhci
->intr
[i
].erstba_high
= 0;
2732 xhci
->intr
[i
].erdp_low
= 0;
2733 xhci
->intr
[i
].erdp_high
= 0;
2734 xhci
->intr
[i
].msix_used
= 0;
2736 xhci
->intr
[i
].er_ep_idx
= 0;
2737 xhci
->intr
[i
].er_pcs
= 1;
2738 xhci
->intr
[i
].er_full
= 0;
2739 xhci
->intr
[i
].ev_buffer_put
= 0;
2740 xhci
->intr
[i
].ev_buffer_get
= 0;
2743 xhci
->mfindex_start
= qemu_get_clock_ns(vm_clock
);
2744 xhci_mfwrap_update(xhci
);
2747 static uint64_t xhci_cap_read(void *ptr
, hwaddr reg
, unsigned size
)
2749 XHCIState
*xhci
= ptr
;
2753 case 0x00: /* HCIVERSION, CAPLENGTH */
2754 ret
= 0x01000000 | LEN_CAP
;
2756 case 0x04: /* HCSPARAMS 1 */
2757 ret
= ((xhci
->numports_2
+xhci
->numports_3
)<<24)
2758 | (xhci
->numintrs
<<8) | xhci
->numslots
;
2760 case 0x08: /* HCSPARAMS 2 */
2763 case 0x0c: /* HCSPARAMS 3 */
2766 case 0x10: /* HCCPARAMS */
2767 if (sizeof(dma_addr_t
) == 4) {
2773 case 0x14: /* DBOFF */
2776 case 0x18: /* RTSOFF */
2780 /* extended capabilities */
2781 case 0x20: /* Supported Protocol:00 */
2782 ret
= 0x02000402; /* USB 2.0 */
2784 case 0x24: /* Supported Protocol:04 */
2785 ret
= 0x20425355; /* "USB " */
2787 case 0x28: /* Supported Protocol:08 */
2788 ret
= 0x00000001 | (xhci
->numports_2
<<8);
2790 case 0x2c: /* Supported Protocol:0c */
2791 ret
= 0x00000000; /* reserved */
2793 case 0x30: /* Supported Protocol:00 */
2794 ret
= 0x03000002; /* USB 3.0 */
2796 case 0x34: /* Supported Protocol:04 */
2797 ret
= 0x20425355; /* "USB " */
2799 case 0x38: /* Supported Protocol:08 */
2800 ret
= 0x00000000 | (xhci
->numports_2
+1) | (xhci
->numports_3
<<8);
2802 case 0x3c: /* Supported Protocol:0c */
2803 ret
= 0x00000000; /* reserved */
2806 trace_usb_xhci_unimplemented("cap read", reg
);
2810 trace_usb_xhci_cap_read(reg
, ret
);
2814 static uint64_t xhci_port_read(void *ptr
, hwaddr reg
, unsigned size
)
2816 XHCIPort
*port
= ptr
;
2820 case 0x00: /* PORTSC */
2823 case 0x04: /* PORTPMSC */
2824 case 0x08: /* PORTLI */
2827 case 0x0c: /* reserved */
2829 trace_usb_xhci_unimplemented("port read", reg
);
2833 trace_usb_xhci_port_read(port
->portnr
, reg
, ret
);
2837 static void xhci_port_write(void *ptr
, hwaddr reg
,
2838 uint64_t val
, unsigned size
)
2840 XHCIPort
*port
= ptr
;
2841 uint32_t portsc
, notify
;
2843 trace_usb_xhci_port_write(port
->portnr
, reg
, val
);
2846 case 0x00: /* PORTSC */
2847 /* write-1-to-start bits */
2848 if (val
& PORTSC_PR
) {
2849 xhci_port_reset(port
);
2853 portsc
= port
->portsc
;
2855 /* write-1-to-clear bits*/
2856 portsc
&= ~(val
& (PORTSC_CSC
|PORTSC_PEC
|PORTSC_WRC
|PORTSC_OCC
|
2857 PORTSC_PRC
|PORTSC_PLC
|PORTSC_CEC
));
2858 if (val
& PORTSC_LWS
) {
2859 /* overwrite PLS only when LWS=1 */
2860 uint32_t old_pls
= get_field(port
->portsc
, PORTSC_PLS
);
2861 uint32_t new_pls
= get_field(val
, PORTSC_PLS
);
2864 if (old_pls
!= PLS_U0
) {
2865 set_field(&portsc
, new_pls
, PORTSC_PLS
);
2866 trace_usb_xhci_port_link(port
->portnr
, new_pls
);
2867 notify
= PORTSC_PLC
;
2871 if (old_pls
< PLS_U3
) {
2872 set_field(&portsc
, new_pls
, PORTSC_PLS
);
2873 trace_usb_xhci_port_link(port
->portnr
, new_pls
);
2877 /* windows does this for some reason, don't spam stderr */
2880 fprintf(stderr
, "%s: ignore pls write (old %d, new %d)\n",
2881 __func__
, old_pls
, new_pls
);
2885 /* read/write bits */
2886 portsc
&= ~(PORTSC_PP
|PORTSC_WCE
|PORTSC_WDE
|PORTSC_WOE
);
2887 portsc
|= (val
& (PORTSC_PP
|PORTSC_WCE
|PORTSC_WDE
|PORTSC_WOE
));
2888 port
->portsc
= portsc
;
2890 xhci_port_notify(port
, notify
);
2893 case 0x04: /* PORTPMSC */
2894 case 0x08: /* PORTLI */
2896 trace_usb_xhci_unimplemented("port write", reg
);
2900 static uint64_t xhci_oper_read(void *ptr
, hwaddr reg
, unsigned size
)
2902 XHCIState
*xhci
= ptr
;
2906 case 0x00: /* USBCMD */
2909 case 0x04: /* USBSTS */
2912 case 0x08: /* PAGESIZE */
2915 case 0x14: /* DNCTRL */
2918 case 0x18: /* CRCR low */
2919 ret
= xhci
->crcr_low
& ~0xe;
2921 case 0x1c: /* CRCR high */
2922 ret
= xhci
->crcr_high
;
2924 case 0x30: /* DCBAAP low */
2925 ret
= xhci
->dcbaap_low
;
2927 case 0x34: /* DCBAAP high */
2928 ret
= xhci
->dcbaap_high
;
2930 case 0x38: /* CONFIG */
2934 trace_usb_xhci_unimplemented("oper read", reg
);
2938 trace_usb_xhci_oper_read(reg
, ret
);
2942 static void xhci_oper_write(void *ptr
, hwaddr reg
,
2943 uint64_t val
, unsigned size
)
2945 XHCIState
*xhci
= ptr
;
2946 DeviceState
*d
= DEVICE(ptr
);
2948 trace_usb_xhci_oper_write(reg
, val
);
2951 case 0x00: /* USBCMD */
2952 if ((val
& USBCMD_RS
) && !(xhci
->usbcmd
& USBCMD_RS
)) {
2954 } else if (!(val
& USBCMD_RS
) && (xhci
->usbcmd
& USBCMD_RS
)) {
2957 xhci
->usbcmd
= val
& 0xc0f;
2958 xhci_mfwrap_update(xhci
);
2959 if (val
& USBCMD_HCRST
) {
2962 xhci_intx_update(xhci
);
2965 case 0x04: /* USBSTS */
2966 /* these bits are write-1-to-clear */
2967 xhci
->usbsts
&= ~(val
& (USBSTS_HSE
|USBSTS_EINT
|USBSTS_PCD
|USBSTS_SRE
));
2968 xhci_intx_update(xhci
);
2971 case 0x14: /* DNCTRL */
2972 xhci
->dnctrl
= val
& 0xffff;
2974 case 0x18: /* CRCR low */
2975 xhci
->crcr_low
= (val
& 0xffffffcf) | (xhci
->crcr_low
& CRCR_CRR
);
2977 case 0x1c: /* CRCR high */
2978 xhci
->crcr_high
= val
;
2979 if (xhci
->crcr_low
& (CRCR_CA
|CRCR_CS
) && (xhci
->crcr_low
& CRCR_CRR
)) {
2980 XHCIEvent event
= {ER_COMMAND_COMPLETE
, CC_COMMAND_RING_STOPPED
};
2981 xhci
->crcr_low
&= ~CRCR_CRR
;
2982 xhci_event(xhci
, &event
, 0);
2983 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci
->crcr_low
);
2985 dma_addr_t base
= xhci_addr64(xhci
->crcr_low
& ~0x3f, val
);
2986 xhci_ring_init(xhci
, &xhci
->cmd_ring
, base
);
2988 xhci
->crcr_low
&= ~(CRCR_CA
| CRCR_CS
);
2990 case 0x30: /* DCBAAP low */
2991 xhci
->dcbaap_low
= val
& 0xffffffc0;
2993 case 0x34: /* DCBAAP high */
2994 xhci
->dcbaap_high
= val
;
2996 case 0x38: /* CONFIG */
2997 xhci
->config
= val
& 0xff;
3000 trace_usb_xhci_unimplemented("oper write", reg
);
3004 static uint64_t xhci_runtime_read(void *ptr
, hwaddr reg
,
3007 XHCIState
*xhci
= ptr
;
3012 case 0x00: /* MFINDEX */
3013 ret
= xhci_mfindex_get(xhci
) & 0x3fff;
3016 trace_usb_xhci_unimplemented("runtime read", reg
);
3020 int v
= (reg
- 0x20) / 0x20;
3021 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
3022 switch (reg
& 0x1f) {
3023 case 0x00: /* IMAN */
3026 case 0x04: /* IMOD */
3029 case 0x08: /* ERSTSZ */
3032 case 0x10: /* ERSTBA low */
3033 ret
= intr
->erstba_low
;
3035 case 0x14: /* ERSTBA high */
3036 ret
= intr
->erstba_high
;
3038 case 0x18: /* ERDP low */
3039 ret
= intr
->erdp_low
;
3041 case 0x1c: /* ERDP high */
3042 ret
= intr
->erdp_high
;
3047 trace_usb_xhci_runtime_read(reg
, ret
);
3051 static void xhci_runtime_write(void *ptr
, hwaddr reg
,
3052 uint64_t val
, unsigned size
)
3054 XHCIState
*xhci
= ptr
;
3055 int v
= (reg
- 0x20) / 0x20;
3056 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
3057 trace_usb_xhci_runtime_write(reg
, val
);
3060 trace_usb_xhci_unimplemented("runtime write", reg
);
3064 switch (reg
& 0x1f) {
3065 case 0x00: /* IMAN */
3066 if (val
& IMAN_IP
) {
3067 intr
->iman
&= ~IMAN_IP
;
3069 intr
->iman
&= ~IMAN_IE
;
3070 intr
->iman
|= val
& IMAN_IE
;
3072 xhci_intx_update(xhci
);
3074 xhci_msix_update(xhci
, v
);
3076 case 0x04: /* IMOD */
3079 case 0x08: /* ERSTSZ */
3080 intr
->erstsz
= val
& 0xffff;
3082 case 0x10: /* ERSTBA low */
3083 /* XXX NEC driver bug: it doesn't align this to 64 bytes
3084 intr->erstba_low = val & 0xffffffc0; */
3085 intr
->erstba_low
= val
& 0xfffffff0;
3087 case 0x14: /* ERSTBA high */
3088 intr
->erstba_high
= val
;
3089 xhci_er_reset(xhci
, v
);
3091 case 0x18: /* ERDP low */
3092 if (val
& ERDP_EHB
) {
3093 intr
->erdp_low
&= ~ERDP_EHB
;
3095 intr
->erdp_low
= (val
& ~ERDP_EHB
) | (intr
->erdp_low
& ERDP_EHB
);
3097 case 0x1c: /* ERDP high */
3098 intr
->erdp_high
= val
;
3099 xhci_events_update(xhci
, v
);
3102 trace_usb_xhci_unimplemented("oper write", reg
);
3106 static uint64_t xhci_doorbell_read(void *ptr
, hwaddr reg
,
3109 /* doorbells always read as 0 */
3110 trace_usb_xhci_doorbell_read(reg
, 0);
3114 static void xhci_doorbell_write(void *ptr
, hwaddr reg
,
3115 uint64_t val
, unsigned size
)
3117 XHCIState
*xhci
= ptr
;
3118 unsigned int epid
, streamid
;
3120 trace_usb_xhci_doorbell_write(reg
, val
);
3122 if (!xhci_running(xhci
)) {
3123 fprintf(stderr
, "xhci: wrote doorbell while xHC stopped or paused\n");
3131 xhci_process_commands(xhci
);
3133 fprintf(stderr
, "xhci: bad doorbell 0 write: 0x%x\n",
3138 streamid
= (val
>> 16) & 0xffff;
3139 if (reg
> xhci
->numslots
) {
3140 fprintf(stderr
, "xhci: bad doorbell %d\n", (int)reg
);
3141 } else if (epid
> 31) {
3142 fprintf(stderr
, "xhci: bad doorbell %d write: 0x%x\n",
3143 (int)reg
, (uint32_t)val
);
3145 xhci_kick_ep(xhci
, reg
, epid
, streamid
);
3150 static void xhci_cap_write(void *opaque
, hwaddr addr
, uint64_t val
,
3156 static const MemoryRegionOps xhci_cap_ops
= {
3157 .read
= xhci_cap_read
,
3158 .write
= xhci_cap_write
,
3159 .valid
.min_access_size
= 1,
3160 .valid
.max_access_size
= 4,
3161 .impl
.min_access_size
= 4,
3162 .impl
.max_access_size
= 4,
3163 .endianness
= DEVICE_LITTLE_ENDIAN
,
3166 static const MemoryRegionOps xhci_oper_ops
= {
3167 .read
= xhci_oper_read
,
3168 .write
= xhci_oper_write
,
3169 .valid
.min_access_size
= 4,
3170 .valid
.max_access_size
= 4,
3171 .endianness
= DEVICE_LITTLE_ENDIAN
,
3174 static const MemoryRegionOps xhci_port_ops
= {
3175 .read
= xhci_port_read
,
3176 .write
= xhci_port_write
,
3177 .valid
.min_access_size
= 4,
3178 .valid
.max_access_size
= 4,
3179 .endianness
= DEVICE_LITTLE_ENDIAN
,
3182 static const MemoryRegionOps xhci_runtime_ops
= {
3183 .read
= xhci_runtime_read
,
3184 .write
= xhci_runtime_write
,
3185 .valid
.min_access_size
= 4,
3186 .valid
.max_access_size
= 4,
3187 .endianness
= DEVICE_LITTLE_ENDIAN
,
3190 static const MemoryRegionOps xhci_doorbell_ops
= {
3191 .read
= xhci_doorbell_read
,
3192 .write
= xhci_doorbell_write
,
3193 .valid
.min_access_size
= 4,
3194 .valid
.max_access_size
= 4,
3195 .endianness
= DEVICE_LITTLE_ENDIAN
,
3198 static void xhci_attach(USBPort
*usbport
)
3200 XHCIState
*xhci
= usbport
->opaque
;
3201 XHCIPort
*port
= xhci_lookup_port(xhci
, usbport
);
3203 xhci_port_update(port
, 0);
3206 static void xhci_detach(USBPort
*usbport
)
3208 XHCIState
*xhci
= usbport
->opaque
;
3209 XHCIPort
*port
= xhci_lookup_port(xhci
, usbport
);
3211 xhci_detach_slot(xhci
, usbport
);
3212 xhci_port_update(port
, 1);
3215 static void xhci_wakeup(USBPort
*usbport
)
3217 XHCIState
*xhci
= usbport
->opaque
;
3218 XHCIPort
*port
= xhci_lookup_port(xhci
, usbport
);
3220 if (get_field(port
->portsc
, PORTSC_PLS
) != PLS_U3
) {
3223 set_field(&port
->portsc
, PLS_RESUME
, PORTSC_PLS
);
3224 xhci_port_notify(port
, PORTSC_PLC
);
3227 static void xhci_complete(USBPort
*port
, USBPacket
*packet
)
3229 XHCITransfer
*xfer
= container_of(packet
, XHCITransfer
, packet
);
3231 if (packet
->status
== USB_RET_REMOVE_FROM_QUEUE
) {
3232 xhci_ep_nuke_one_xfer(xfer
);
3235 xhci_complete_packet(xfer
);
3236 xhci_kick_ep(xfer
->xhci
, xfer
->slotid
, xfer
->epid
, xfer
->streamid
);
3239 static void xhci_child_detach(USBPort
*uport
, USBDevice
*child
)
3241 USBBus
*bus
= usb_bus_from_device(child
);
3242 XHCIState
*xhci
= container_of(bus
, XHCIState
, bus
);
3244 xhci_detach_slot(xhci
, uport
);
3247 static USBPortOps xhci_uport_ops
= {
3248 .attach
= xhci_attach
,
3249 .detach
= xhci_detach
,
3250 .wakeup
= xhci_wakeup
,
3251 .complete
= xhci_complete
,
3252 .child_detach
= xhci_child_detach
,
3255 static int xhci_find_epid(USBEndpoint
*ep
)
3260 if (ep
->pid
== USB_TOKEN_IN
) {
3261 return ep
->nr
* 2 + 1;
3267 static void xhci_wakeup_endpoint(USBBus
*bus
, USBEndpoint
*ep
,
3268 unsigned int stream
)
3270 XHCIState
*xhci
= container_of(bus
, XHCIState
, bus
);
3273 DPRINTF("%s\n", __func__
);
3274 slotid
= ep
->dev
->addr
;
3275 if (slotid
== 0 || !xhci
->slots
[slotid
-1].enabled
) {
3276 DPRINTF("%s: oops, no slot for dev %d\n", __func__
, ep
->dev
->addr
);
3279 xhci_kick_ep(xhci
, slotid
, xhci_find_epid(ep
), stream
);
3282 static USBBusOps xhci_bus_ops
= {
3283 .wakeup_endpoint
= xhci_wakeup_endpoint
,
3286 static void usb_xhci_init(XHCIState
*xhci
)
3288 DeviceState
*dev
= DEVICE(xhci
);
3290 int i
, usbports
, speedmask
;
3292 xhci
->usbsts
= USBSTS_HCH
;
3294 if (xhci
->numports_2
> MAXPORTS_2
) {
3295 xhci
->numports_2
= MAXPORTS_2
;
3297 if (xhci
->numports_3
> MAXPORTS_3
) {
3298 xhci
->numports_3
= MAXPORTS_3
;
3300 usbports
= MAX(xhci
->numports_2
, xhci
->numports_3
);
3301 xhci
->numports
= xhci
->numports_2
+ xhci
->numports_3
;
3303 usb_bus_new(&xhci
->bus
, &xhci_bus_ops
, dev
);
3305 for (i
= 0; i
< usbports
; i
++) {
3307 if (i
< xhci
->numports_2
) {
3308 port
= &xhci
->ports
[i
];
3309 port
->portnr
= i
+ 1;
3310 port
->uport
= &xhci
->uports
[i
];
3312 USB_SPEED_MASK_LOW
|
3313 USB_SPEED_MASK_FULL
|
3314 USB_SPEED_MASK_HIGH
;
3315 snprintf(port
->name
, sizeof(port
->name
), "usb2 port #%d", i
+1);
3316 speedmask
|= port
->speedmask
;
3318 if (i
< xhci
->numports_3
) {
3319 port
= &xhci
->ports
[i
+ xhci
->numports_2
];
3320 port
->portnr
= i
+ 1 + xhci
->numports_2
;
3321 port
->uport
= &xhci
->uports
[i
];
3322 port
->speedmask
= USB_SPEED_MASK_SUPER
;
3323 snprintf(port
->name
, sizeof(port
->name
), "usb3 port #%d", i
+1);
3324 speedmask
|= port
->speedmask
;
3326 usb_register_port(&xhci
->bus
, &xhci
->uports
[i
], xhci
, i
,
3327 &xhci_uport_ops
, speedmask
);
3331 static int usb_xhci_initfn(struct PCIDevice
*dev
)
3335 XHCIState
*xhci
= XHCI(dev
);
3337 dev
->config
[PCI_CLASS_PROG
] = 0x30; /* xHCI */
3338 dev
->config
[PCI_INTERRUPT_PIN
] = 0x01; /* interrupt pin 1 */
3339 dev
->config
[PCI_CACHE_LINE_SIZE
] = 0x10;
3340 dev
->config
[0x60] = 0x30; /* release number */
3342 usb_xhci_init(xhci
);
3344 if (xhci
->numintrs
> MAXINTRS
) {
3345 xhci
->numintrs
= MAXINTRS
;
3347 while (xhci
->numintrs
& (xhci
->numintrs
- 1)) { /* ! power of 2 */
3350 if (xhci
->numintrs
< 1) {
3353 if (xhci
->numslots
> MAXSLOTS
) {
3354 xhci
->numslots
= MAXSLOTS
;
3356 if (xhci
->numslots
< 1) {
3360 xhci
->mfwrap_timer
= qemu_new_timer_ns(vm_clock
, xhci_mfwrap_timer
, xhci
);
3362 xhci
->irq
= dev
->irq
[0];
3364 memory_region_init(&xhci
->mem
, OBJECT(xhci
), "xhci", LEN_REGS
);
3365 memory_region_init_io(&xhci
->mem_cap
, OBJECT(xhci
), &xhci_cap_ops
, xhci
,
3366 "capabilities", LEN_CAP
);
3367 memory_region_init_io(&xhci
->mem_oper
, OBJECT(xhci
), &xhci_oper_ops
, xhci
,
3368 "operational", 0x400);
3369 memory_region_init_io(&xhci
->mem_runtime
, OBJECT(xhci
), &xhci_runtime_ops
, xhci
,
3370 "runtime", LEN_RUNTIME
);
3371 memory_region_init_io(&xhci
->mem_doorbell
, OBJECT(xhci
), &xhci_doorbell_ops
, xhci
,
3372 "doorbell", LEN_DOORBELL
);
3374 memory_region_add_subregion(&xhci
->mem
, 0, &xhci
->mem_cap
);
3375 memory_region_add_subregion(&xhci
->mem
, OFF_OPER
, &xhci
->mem_oper
);
3376 memory_region_add_subregion(&xhci
->mem
, OFF_RUNTIME
, &xhci
->mem_runtime
);
3377 memory_region_add_subregion(&xhci
->mem
, OFF_DOORBELL
, &xhci
->mem_doorbell
);
3379 for (i
= 0; i
< xhci
->numports
; i
++) {
3380 XHCIPort
*port
= &xhci
->ports
[i
];
3381 uint32_t offset
= OFF_OPER
+ 0x400 + 0x10 * i
;
3383 memory_region_init_io(&port
->mem
, OBJECT(xhci
), &xhci_port_ops
, port
,
3385 memory_region_add_subregion(&xhci
->mem
, offset
, &port
->mem
);
3388 pci_register_bar(dev
, 0,
3389 PCI_BASE_ADDRESS_SPACE_MEMORY
|PCI_BASE_ADDRESS_MEM_TYPE_64
,
3392 ret
= pcie_endpoint_cap_init(dev
, 0xa0);
3395 if (xhci
->flags
& (1 << XHCI_FLAG_USE_MSI
)) {
3396 msi_init(dev
, 0x70, xhci
->numintrs
, true, false);
3398 if (xhci
->flags
& (1 << XHCI_FLAG_USE_MSI_X
)) {
3399 msix_init(dev
, xhci
->numintrs
,
3400 &xhci
->mem
, 0, OFF_MSIX_TABLE
,
3401 &xhci
->mem
, 0, OFF_MSIX_PBA
,
3408 static int usb_xhci_post_load(void *opaque
, int version_id
)
3410 XHCIState
*xhci
= opaque
;
3411 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
3413 XHCIEPContext
*epctx
;
3414 dma_addr_t dcbaap
, pctx
;
3415 uint32_t slot_ctx
[4];
3417 int slotid
, epid
, state
, intr
;
3419 dcbaap
= xhci_addr64(xhci
->dcbaap_low
, xhci
->dcbaap_high
);
3421 for (slotid
= 1; slotid
<= xhci
->numslots
; slotid
++) {
3422 slot
= &xhci
->slots
[slotid
-1];
3423 if (!slot
->addressed
) {
3427 xhci_mask64(ldq_le_pci_dma(pci_dev
, dcbaap
+ 8 * slotid
));
3428 xhci_dma_read_u32s(xhci
, slot
->ctx
, slot_ctx
, sizeof(slot_ctx
));
3429 slot
->uport
= xhci_lookup_uport(xhci
, slot_ctx
);
3430 assert(slot
->uport
&& slot
->uport
->dev
);
3432 for (epid
= 1; epid
<= 32; epid
++) {
3433 pctx
= slot
->ctx
+ 32 * epid
;
3434 xhci_dma_read_u32s(xhci
, pctx
, ep_ctx
, sizeof(ep_ctx
));
3435 state
= ep_ctx
[0] & EP_STATE_MASK
;
3436 if (state
== EP_DISABLED
) {
3439 epctx
= xhci_alloc_epctx(xhci
, slotid
, epid
);
3440 slot
->eps
[epid
-1] = epctx
;
3441 xhci_init_epctx(epctx
, pctx
, ep_ctx
);
3442 epctx
->state
= state
;
3443 if (state
== EP_RUNNING
) {
3444 /* kick endpoint after vmload is finished */
3445 qemu_mod_timer(epctx
->kick_timer
, qemu_get_clock_ns(vm_clock
));
3450 for (intr
= 0; intr
< xhci
->numintrs
; intr
++) {
3451 if (xhci
->intr
[intr
].msix_used
) {
3452 msix_vector_use(pci_dev
, intr
);
3454 msix_vector_unuse(pci_dev
, intr
);
3461 static const VMStateDescription vmstate_xhci_ring
= {
3462 .name
= "xhci-ring",
3464 .fields
= (VMStateField
[]) {
3465 VMSTATE_UINT64(dequeue
, XHCIRing
),
3466 VMSTATE_BOOL(ccs
, XHCIRing
),
3467 VMSTATE_END_OF_LIST()
3471 static const VMStateDescription vmstate_xhci_port
= {
3472 .name
= "xhci-port",
3474 .fields
= (VMStateField
[]) {
3475 VMSTATE_UINT32(portsc
, XHCIPort
),
3476 VMSTATE_END_OF_LIST()
3480 static const VMStateDescription vmstate_xhci_slot
= {
3481 .name
= "xhci-slot",
3483 .fields
= (VMStateField
[]) {
3484 VMSTATE_BOOL(enabled
, XHCISlot
),
3485 VMSTATE_BOOL(addressed
, XHCISlot
),
3486 VMSTATE_END_OF_LIST()
3490 static const VMStateDescription vmstate_xhci_event
= {
3491 .name
= "xhci-event",
3493 .fields
= (VMStateField
[]) {
3494 VMSTATE_UINT32(type
, XHCIEvent
),
3495 VMSTATE_UINT32(ccode
, XHCIEvent
),
3496 VMSTATE_UINT64(ptr
, XHCIEvent
),
3497 VMSTATE_UINT32(length
, XHCIEvent
),
3498 VMSTATE_UINT32(flags
, XHCIEvent
),
3499 VMSTATE_UINT8(slotid
, XHCIEvent
),
3500 VMSTATE_UINT8(epid
, XHCIEvent
),
3504 static bool xhci_er_full(void *opaque
, int version_id
)
3506 struct XHCIInterrupter
*intr
= opaque
;
3507 return intr
->er_full
;
3510 static const VMStateDescription vmstate_xhci_intr
= {
3511 .name
= "xhci-intr",
3513 .fields
= (VMStateField
[]) {
3515 VMSTATE_UINT32(iman
, XHCIInterrupter
),
3516 VMSTATE_UINT32(imod
, XHCIInterrupter
),
3517 VMSTATE_UINT32(erstsz
, XHCIInterrupter
),
3518 VMSTATE_UINT32(erstba_low
, XHCIInterrupter
),
3519 VMSTATE_UINT32(erstba_high
, XHCIInterrupter
),
3520 VMSTATE_UINT32(erdp_low
, XHCIInterrupter
),
3521 VMSTATE_UINT32(erdp_high
, XHCIInterrupter
),
3524 VMSTATE_BOOL(msix_used
, XHCIInterrupter
),
3525 VMSTATE_BOOL(er_pcs
, XHCIInterrupter
),
3526 VMSTATE_UINT64(er_start
, XHCIInterrupter
),
3527 VMSTATE_UINT32(er_size
, XHCIInterrupter
),
3528 VMSTATE_UINT32(er_ep_idx
, XHCIInterrupter
),
3530 /* event queue (used if ring is full) */
3531 VMSTATE_BOOL(er_full
, XHCIInterrupter
),
3532 VMSTATE_UINT32_TEST(ev_buffer_put
, XHCIInterrupter
, xhci_er_full
),
3533 VMSTATE_UINT32_TEST(ev_buffer_get
, XHCIInterrupter
, xhci_er_full
),
3534 VMSTATE_STRUCT_ARRAY_TEST(ev_buffer
, XHCIInterrupter
, EV_QUEUE
,
3536 vmstate_xhci_event
, XHCIEvent
),
3538 VMSTATE_END_OF_LIST()
3542 static const VMStateDescription vmstate_xhci
= {
3545 .post_load
= usb_xhci_post_load
,
3546 .fields
= (VMStateField
[]) {
3547 VMSTATE_PCIE_DEVICE(parent_obj
, XHCIState
),
3548 VMSTATE_MSIX(parent_obj
, XHCIState
),
3550 VMSTATE_STRUCT_VARRAY_UINT32(ports
, XHCIState
, numports
, 1,
3551 vmstate_xhci_port
, XHCIPort
),
3552 VMSTATE_STRUCT_VARRAY_UINT32(slots
, XHCIState
, numslots
, 1,
3553 vmstate_xhci_slot
, XHCISlot
),
3554 VMSTATE_STRUCT_VARRAY_UINT32(intr
, XHCIState
, numintrs
, 1,
3555 vmstate_xhci_intr
, XHCIInterrupter
),
3557 /* Operational Registers */
3558 VMSTATE_UINT32(usbcmd
, XHCIState
),
3559 VMSTATE_UINT32(usbsts
, XHCIState
),
3560 VMSTATE_UINT32(dnctrl
, XHCIState
),
3561 VMSTATE_UINT32(crcr_low
, XHCIState
),
3562 VMSTATE_UINT32(crcr_high
, XHCIState
),
3563 VMSTATE_UINT32(dcbaap_low
, XHCIState
),
3564 VMSTATE_UINT32(dcbaap_high
, XHCIState
),
3565 VMSTATE_UINT32(config
, XHCIState
),
3567 /* Runtime Registers & state */
3568 VMSTATE_INT64(mfindex_start
, XHCIState
),
3569 VMSTATE_TIMER(mfwrap_timer
, XHCIState
),
3570 VMSTATE_STRUCT(cmd_ring
, XHCIState
, 1, vmstate_xhci_ring
, XHCIRing
),
3572 VMSTATE_END_OF_LIST()
3576 static Property xhci_properties
[] = {
3577 DEFINE_PROP_BIT("msi", XHCIState
, flags
, XHCI_FLAG_USE_MSI
, true),
3578 DEFINE_PROP_BIT("msix", XHCIState
, flags
, XHCI_FLAG_USE_MSI_X
, true),
3579 DEFINE_PROP_UINT32("intrs", XHCIState
, numintrs
, MAXINTRS
),
3580 DEFINE_PROP_UINT32("slots", XHCIState
, numslots
, MAXSLOTS
),
3581 DEFINE_PROP_UINT32("p2", XHCIState
, numports_2
, 4),
3582 DEFINE_PROP_UINT32("p3", XHCIState
, numports_3
, 4),
3583 DEFINE_PROP_END_OF_LIST(),
3586 static void xhci_class_init(ObjectClass
*klass
, void *data
)
3588 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
3589 DeviceClass
*dc
= DEVICE_CLASS(klass
);
3591 dc
->vmsd
= &vmstate_xhci
;
3592 dc
->props
= xhci_properties
;
3593 dc
->reset
= xhci_reset
;
3594 set_bit(DEVICE_CATEGORY_USB
, dc
->categories
);
3595 k
->init
= usb_xhci_initfn
;
3596 k
->vendor_id
= PCI_VENDOR_ID_NEC
;
3597 k
->device_id
= PCI_DEVICE_ID_NEC_UPD720200
;
3598 k
->class_id
= PCI_CLASS_SERIAL_USB
;
3604 static const TypeInfo xhci_info
= {
3606 .parent
= TYPE_PCI_DEVICE
,
3607 .instance_size
= sizeof(XHCIState
),
3608 .class_init
= xhci_class_init
,
3611 static void xhci_register_types(void)
3613 type_register_static(&xhci_info
);
3616 type_init(xhci_register_types
)