hw/ppc/ppc405.h

   1 /*
   2  * QEMU PowerPC 405 shared definitions
   3  *
   4  * Copyright (c) 2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #ifndef PPC405_H
  26 #define PPC405_H
  27
  28 #include "qom/object.h"
  29 #include "hw/ppc/ppc4xx.h"
  30
  31 #define PPC405EP_SDRAM_BASE 0x00000000
  32 #define PPC405EP_NVRAM_BASE 0xF0000000
  33 #define PPC405EP_FPGA_BASE  0xF0300000
  34 #define PPC405EP_SRAM_BASE  0xFFF00000
  35 #define PPC405EP_SRAM_SIZE  (512 * KiB)
  36 #define PPC405EP_FLASH_BASE 0xFFF80000
  37
  38 /* Bootinfo as set-up by u-boot */
  39 typedef struct ppc4xx_bd_info_t ppc4xx_bd_info_t;
  40 struct ppc4xx_bd_info_t {
  41     uint32_t bi_memstart;
  42     uint32_t bi_memsize;
  43     uint32_t bi_flashstart;
  44     uint32_t bi_flashsize;
  45     uint32_t bi_flashoffset; /* 0x10 */
  46     uint32_t bi_sramstart;
  47     uint32_t bi_sramsize;
  48     uint32_t bi_bootflags;
  49     uint32_t bi_ipaddr; /* 0x20 */
  50     uint8_t  bi_enetaddr[6];
  51     uint16_t bi_ethspeed;
  52     uint32_t bi_intfreq;
  53     uint32_t bi_busfreq; /* 0x30 */
  54     uint32_t bi_baudrate;
  55     uint8_t  bi_s_version[4];
  56     uint8_t  bi_r_version[32];
  57     uint32_t bi_procfreq;
  58     uint32_t bi_plb_busfreq;
  59     uint32_t bi_pci_busfreq;
  60     uint8_t  bi_pci_enetaddr[6];
  61     uint8_t  bi_pci_enetaddr2[6]; /* PPC405EP specific */
  62     uint32_t bi_opbfreq;
  63     uint32_t bi_iic_fast[2];
  64 };
  65
  66 /* GPIO */
  67 #define TYPE_PPC405_GPIO "ppc405-gpio"
  68 OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GpioState, PPC405_GPIO);
  69 struct Ppc405GpioState {
  70     SysBusDevice parent_obj;
  71
  72     MemoryRegion io;
  73     uint32_t or;
  74     uint32_t tcr;
  75     uint32_t osrh;
  76     uint32_t osrl;
  77     uint32_t tsrh;
  78     uint32_t tsrl;
  79     uint32_t odr;
  80     uint32_t ir;
  81     uint32_t rr1;
  82     uint32_t isr1h;
  83     uint32_t isr1l;
  84 };
  85
  86 /* On Chip Memory */
  87 #define TYPE_PPC405_OCM "ppc405-ocm"
  88 OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OcmState, PPC405_OCM);
  89 struct Ppc405OcmState {
  90     Ppc4xxDcrDeviceState parent_obj;
  91
  92     MemoryRegion ram;
  93     MemoryRegion isarc_ram;
  94     MemoryRegion dsarc_ram;
  95     uint32_t isarc;
  96     uint32_t isacntl;
  97     uint32_t dsarc;
  98     uint32_t dsacntl;
  99 };
 100
 101 /* General purpose timers */
 102 #define TYPE_PPC405_GPT "ppc405-gpt"
 103 OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GptState, PPC405_GPT);
 104 struct Ppc405GptState {
 105     SysBusDevice parent_obj;
 106
 107     MemoryRegion iomem;
 108
 109     int64_t tb_offset;
 110     uint32_t tb_freq;
 111     QEMUTimer *timer;
 112     qemu_irq irqs[5];
 113     uint32_t oe;
 114     uint32_t ol;
 115     uint32_t im;
 116     uint32_t is;
 117     uint32_t ie;
 118     uint32_t comp[5];
 119     uint32_t mask[5];
 120 };
 121
 122 #define TYPE_PPC405_CPC "ppc405-cpc"
 123 OBJECT_DECLARE_SIMPLE_TYPE(Ppc405CpcState, PPC405_CPC);
 124
 125 enum {
 126     PPC405EP_CPU_CLK   = 0,
 127     PPC405EP_PLB_CLK   = 1,
 128     PPC405EP_OPB_CLK   = 2,
 129     PPC405EP_EBC_CLK   = 3,
 130     PPC405EP_MAL_CLK   = 4,
 131     PPC405EP_PCI_CLK   = 5,
 132     PPC405EP_UART0_CLK = 6,
 133     PPC405EP_UART1_CLK = 7,
 134     PPC405EP_CLK_NB    = 8,
 135 };
 136
 137 struct Ppc405CpcState {
 138     Ppc4xxDcrDeviceState parent_obj;
 139
 140     uint32_t sysclk;
 141     clk_setup_t clk_setup[PPC405EP_CLK_NB];
 142     uint32_t boot;
 143     uint32_t epctl;
 144     uint32_t pllmr[2];
 145     uint32_t ucr;
 146     uint32_t srr;
 147     uint32_t jtagid;
 148     uint32_t pci;
 149     /* Clock and power management */
 150     uint32_t er;
 151     uint32_t fr;
 152     uint32_t sr;
 153 };
 154
 155 #define TYPE_PPC405_SOC "ppc405-soc"
 156 OBJECT_DECLARE_SIMPLE_TYPE(Ppc405SoCState, PPC405_SOC);
 157
 158 struct Ppc405SoCState {
 159     /* Private */
 160     DeviceState parent_obj;
 161
 162     /* Public */
 163     MemoryRegion ram_banks[2];
 164     hwaddr ram_bases[2], ram_sizes[2];
 165     bool do_dram_init;
 166
 167     MemoryRegion *dram_mr;
 168     hwaddr ram_size;
 169
 170     PowerPCCPU cpu;
 171     DeviceState *uic;
 172     Ppc405CpcState cpc;
 173     Ppc405GptState gpt;
 174     Ppc405OcmState ocm;
 175     Ppc405GpioState gpio;
 176 };
 177
 178 /* PowerPC 405 core */
 179 ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size);
 180
 181 void ppc4xx_plb_init(CPUPPCState *env);
 182 void ppc405_ebc_init(CPUPPCState *env);
 183
 184 #endif /* PPC405_H */