4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
36 pci_set_irq_fn set_irq
;
37 pci_map_irq_fn map_irq
;
38 uint32_t config_reg
; /* XXX: suppress */
40 SetIRQFunc
*low_set_irq
;
42 PCIDevice
*devices
[256];
43 PCIDevice
*parent_dev
;
45 /* The bus IRQ state is the logical OR of the connected devices.
46 Keep a count of the number of devices with raised IRQs. */
51 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
);
53 static struct BusInfo pci_bus_info
= {
55 .size
= sizeof(PCIBus
),
56 .print_dev
= pcibus_dev_print
,
59 static void pci_update_mappings(PCIDevice
*d
);
60 static void pci_set_irq(void *opaque
, int irq_num
, int level
);
62 target_phys_addr_t pci_mem_base
;
63 static uint16_t pci_default_sub_vendor_id
= PCI_SUBVENDOR_ID_REDHAT_QUMRANET
;
64 static uint16_t pci_default_sub_device_id
= PCI_SUBDEVICE_ID_QEMU
;
65 static PCIBus
*first_bus
;
67 static void pcibus_save(QEMUFile
*f
, void *opaque
)
69 PCIBus
*bus
= (PCIBus
*)opaque
;
72 qemu_put_be32(f
, bus
->nirq
);
73 for (i
= 0; i
< bus
->nirq
; i
++)
74 qemu_put_be32(f
, bus
->irq_count
[i
]);
77 static int pcibus_load(QEMUFile
*f
, void *opaque
, int version_id
)
79 PCIBus
*bus
= (PCIBus
*)opaque
;
85 nirq
= qemu_get_be32(f
);
86 if (bus
->nirq
!= nirq
) {
87 fprintf(stderr
, "pcibus_load: nirq mismatch: src=%d dst=%d\n",
92 for (i
= 0; i
< nirq
; i
++)
93 bus
->irq_count
[i
] = qemu_get_be32(f
);
98 static void pci_bus_reset(void *opaque
)
100 PCIBus
*bus
= (PCIBus
*)opaque
;
103 for (i
= 0; i
< bus
->nirq
; i
++) {
104 bus
->irq_count
[i
] = 0;
106 for (i
= 0; i
< 256; i
++) {
108 memset(bus
->devices
[i
]->irq_state
, 0,
109 sizeof(bus
->devices
[i
]->irq_state
));
113 PCIBus
*pci_register_bus(DeviceState
*parent
, const char *name
,
114 pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
115 qemu_irq
*pic
, int devfn_min
, int nirq
)
120 bus
= FROM_QBUS(PCIBus
, qbus_create(&pci_bus_info
, parent
, name
));
121 bus
->set_irq
= set_irq
;
122 bus
->map_irq
= map_irq
;
123 bus
->irq_opaque
= pic
;
124 bus
->devfn_min
= devfn_min
;
126 bus
->irq_count
= qemu_malloc(nirq
* sizeof(bus
->irq_count
[0]));
127 bus
->next
= first_bus
;
129 register_savevm("PCIBUS", nbus
++, 1, pcibus_save
, pcibus_load
, bus
);
130 qemu_register_reset(pci_bus_reset
, bus
);
134 static PCIBus
*pci_register_secondary_bus(PCIDevice
*dev
, pci_map_irq_fn map_irq
)
137 bus
= qemu_mallocz(sizeof(PCIBus
));
138 bus
->map_irq
= map_irq
;
139 bus
->parent_dev
= dev
;
140 bus
->next
= dev
->bus
->next
;
141 dev
->bus
->next
= bus
;
145 int pci_bus_num(PCIBus
*s
)
150 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
)
154 qemu_put_be32(f
, 2); /* PCI device version */
155 qemu_put_buffer(f
, s
->config
, 256);
156 for (i
= 0; i
< 4; i
++)
157 qemu_put_be32(f
, s
->irq_state
[i
]);
160 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
)
162 uint8_t config
[PCI_CONFIG_SPACE_SIZE
];
166 version_id
= qemu_get_be32(f
);
169 qemu_get_buffer(f
, config
, sizeof config
);
170 for (i
= 0; i
< sizeof config
; ++i
)
171 if ((config
[i
] ^ s
->config
[i
]) & s
->cmask
[i
] & ~s
->wmask
[i
])
173 memcpy(s
->config
, config
, sizeof config
);
175 pci_update_mappings(s
);
178 for (i
= 0; i
< 4; i
++)
179 s
->irq_state
[i
] = qemu_get_be32(f
);
183 static int pci_set_default_subsystem_id(PCIDevice
*pci_dev
)
187 id
= (void*)(&pci_dev
->config
[PCI_SUBVENDOR_ID
]);
188 id
[0] = cpu_to_le16(pci_default_sub_vendor_id
);
189 id
[1] = cpu_to_le16(pci_default_sub_device_id
);
194 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
196 static int pci_parse_devaddr(const char *addr
, int *domp
, int *busp
, unsigned *slotp
)
201 unsigned long dom
= 0, bus
= 0;
205 val
= strtoul(p
, &e
, 16);
211 val
= strtoul(p
, &e
, 16);
218 val
= strtoul(p
, &e
, 16);
224 if (dom
> 0xffff || bus
> 0xff || val
> 0x1f)
232 /* Note: QEMU doesn't implement domains other than 0 */
233 if (dom
!= 0 || pci_find_bus(bus
) == NULL
)
242 int pci_read_devaddr(Monitor
*mon
, const char *addr
, int *domp
, int *busp
,
245 /* strip legacy tag */
246 if (!strncmp(addr
, "pci_addr=", 9)) {
249 if (pci_parse_devaddr(addr
, domp
, busp
, slotp
)) {
250 monitor_printf(mon
, "Invalid pci address\n");
256 static PCIBus
*pci_get_bus_devfn(int *devfnp
, const char *devaddr
)
263 return pci_find_bus(0);
266 if (pci_parse_devaddr(devaddr
, &dom
, &bus
, &slot
) < 0) {
271 return pci_find_bus(bus
);
274 static void pci_init_cmask(PCIDevice
*dev
)
276 pci_set_word(dev
->cmask
+ PCI_VENDOR_ID
, 0xffff);
277 pci_set_word(dev
->cmask
+ PCI_DEVICE_ID
, 0xffff);
278 dev
->cmask
[PCI_STATUS
] = PCI_STATUS_CAP_LIST
;
279 dev
->cmask
[PCI_REVISION_ID
] = 0xff;
280 dev
->cmask
[PCI_CLASS_PROG
] = 0xff;
281 pci_set_word(dev
->cmask
+ PCI_CLASS_DEVICE
, 0xffff);
282 dev
->cmask
[PCI_HEADER_TYPE
] = 0xff;
283 dev
->cmask
[PCI_CAPABILITY_LIST
] = 0xff;
286 static void pci_init_wmask(PCIDevice
*dev
)
289 dev
->wmask
[PCI_CACHE_LINE_SIZE
] = 0xff;
290 dev
->wmask
[PCI_INTERRUPT_LINE
] = 0xff;
291 dev
->wmask
[PCI_COMMAND
] = PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
292 | PCI_COMMAND_MASTER
;
293 for (i
= PCI_CONFIG_HEADER_SIZE
; i
< PCI_CONFIG_SPACE_SIZE
; ++i
)
294 dev
->wmask
[i
] = 0xff;
297 /* -1 for devfn means auto assign */
298 static PCIDevice
*do_pci_register_device(PCIDevice
*pci_dev
, PCIBus
*bus
,
299 const char *name
, int devfn
,
300 PCIConfigReadFunc
*config_read
,
301 PCIConfigWriteFunc
*config_write
)
304 for(devfn
= bus
->devfn_min
; devfn
< 256; devfn
+= 8) {
305 if (!bus
->devices
[devfn
])
310 } else if (bus
->devices
[devfn
]) {
314 pci_dev
->devfn
= devfn
;
315 pstrcpy(pci_dev
->name
, sizeof(pci_dev
->name
), name
);
316 memset(pci_dev
->irq_state
, 0, sizeof(pci_dev
->irq_state
));
317 pci_set_default_subsystem_id(pci_dev
);
318 pci_init_cmask(pci_dev
);
319 pci_init_wmask(pci_dev
);
322 config_read
= pci_default_read_config
;
324 config_write
= pci_default_write_config
;
325 pci_dev
->config_read
= config_read
;
326 pci_dev
->config_write
= config_write
;
327 bus
->devices
[devfn
] = pci_dev
;
328 pci_dev
->irq
= qemu_allocate_irqs(pci_set_irq
, pci_dev
, 4);
332 PCIDevice
*pci_register_device(PCIBus
*bus
, const char *name
,
333 int instance_size
, int devfn
,
334 PCIConfigReadFunc
*config_read
,
335 PCIConfigWriteFunc
*config_write
)
339 pci_dev
= qemu_mallocz(instance_size
);
340 pci_dev
= do_pci_register_device(pci_dev
, bus
, name
, devfn
,
341 config_read
, config_write
);
344 static target_phys_addr_t
pci_to_cpu_addr(target_phys_addr_t addr
)
346 return addr
+ pci_mem_base
;
349 static void pci_unregister_io_regions(PCIDevice
*pci_dev
)
354 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
355 r
= &pci_dev
->io_regions
[i
];
356 if (!r
->size
|| r
->addr
== -1)
358 if (r
->type
== PCI_ADDRESS_SPACE_IO
) {
359 isa_unassign_ioport(r
->addr
, r
->size
);
361 cpu_register_physical_memory(pci_to_cpu_addr(r
->addr
),
368 int pci_unregister_device(PCIDevice
*pci_dev
)
372 if (pci_dev
->unregister
)
373 ret
= pci_dev
->unregister(pci_dev
);
377 pci_unregister_io_regions(pci_dev
);
379 qemu_free_irqs(pci_dev
->irq
);
380 pci_dev
->bus
->devices
[pci_dev
->devfn
] = NULL
;
381 qdev_free(&pci_dev
->qdev
);
385 void pci_register_bar(PCIDevice
*pci_dev
, int region_num
,
386 uint32_t size
, int type
,
387 PCIMapIORegionFunc
*map_func
)
393 if ((unsigned int)region_num
>= PCI_NUM_REGIONS
)
396 if (size
& (size
-1)) {
397 fprintf(stderr
, "ERROR: PCI region size must be pow2 "
398 "type=0x%x, size=0x%x\n", type
, size
);
402 r
= &pci_dev
->io_regions
[region_num
];
406 r
->map_func
= map_func
;
409 if (region_num
== PCI_ROM_SLOT
) {
411 /* ROM enable bit is writeable */
414 addr
= 0x10 + region_num
* 4;
416 *(uint32_t *)(pci_dev
->config
+ addr
) = cpu_to_le32(type
);
417 *(uint32_t *)(pci_dev
->wmask
+ addr
) = cpu_to_le32(wmask
);
418 *(uint32_t *)(pci_dev
->cmask
+ addr
) = 0xffffffff;
421 static void pci_update_mappings(PCIDevice
*d
)
425 uint32_t last_addr
, new_addr
, config_ofs
;
427 cmd
= le16_to_cpu(*(uint16_t *)(d
->config
+ PCI_COMMAND
));
428 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
429 r
= &d
->io_regions
[i
];
430 if (i
== PCI_ROM_SLOT
) {
433 config_ofs
= 0x10 + i
* 4;
436 if (r
->type
& PCI_ADDRESS_SPACE_IO
) {
437 if (cmd
& PCI_COMMAND_IO
) {
438 new_addr
= le32_to_cpu(*(uint32_t *)(d
->config
+
440 new_addr
= new_addr
& ~(r
->size
- 1);
441 last_addr
= new_addr
+ r
->size
- 1;
442 /* NOTE: we have only 64K ioports on PC */
443 if (last_addr
<= new_addr
|| new_addr
== 0 ||
444 last_addr
>= 0x10000) {
451 if (cmd
& PCI_COMMAND_MEMORY
) {
452 new_addr
= le32_to_cpu(*(uint32_t *)(d
->config
+
454 /* the ROM slot has a specific enable bit */
455 if (i
== PCI_ROM_SLOT
&& !(new_addr
& 1))
457 new_addr
= new_addr
& ~(r
->size
- 1);
458 last_addr
= new_addr
+ r
->size
- 1;
459 /* NOTE: we do not support wrapping */
460 /* XXX: as we cannot support really dynamic
461 mappings, we handle specific values as invalid
463 if (last_addr
<= new_addr
|| new_addr
== 0 ||
472 /* now do the real mapping */
473 if (new_addr
!= r
->addr
) {
475 if (r
->type
& PCI_ADDRESS_SPACE_IO
) {
477 /* NOTE: specific hack for IDE in PC case:
478 only one byte must be mapped. */
479 class = d
->config
[0x0a] | (d
->config
[0x0b] << 8);
480 if (class == 0x0101 && r
->size
== 4) {
481 isa_unassign_ioport(r
->addr
+ 2, 1);
483 isa_unassign_ioport(r
->addr
, r
->size
);
486 cpu_register_physical_memory(pci_to_cpu_addr(r
->addr
),
489 qemu_unregister_coalesced_mmio(r
->addr
, r
->size
);
494 r
->map_func(d
, i
, r
->addr
, r
->size
, r
->type
);
501 uint32_t pci_default_read_config(PCIDevice
*d
,
502 uint32_t address
, int len
)
509 if (address
<= 0xfc) {
510 val
= le32_to_cpu(*(uint32_t *)(d
->config
+ address
));
515 if (address
<= 0xfe) {
516 val
= le16_to_cpu(*(uint16_t *)(d
->config
+ address
));
521 val
= d
->config
[address
];
527 void pci_default_write_config(PCIDevice
*d
, uint32_t addr
, uint32_t val
, int l
)
529 uint8_t orig
[PCI_CONFIG_SPACE_SIZE
];
532 /* not efficient, but simple */
533 memcpy(orig
, d
->config
, PCI_CONFIG_SPACE_SIZE
);
534 for(i
= 0; i
< l
&& addr
< PCI_CONFIG_SPACE_SIZE
; val
>>= 8, ++i
, ++addr
) {
535 uint8_t wmask
= d
->wmask
[addr
];
536 d
->config
[addr
] = (d
->config
[addr
] & ~wmask
) | (val
& wmask
);
538 if (memcmp(orig
+ PCI_BASE_ADDRESS_0
, d
->config
+ PCI_BASE_ADDRESS_0
, 24)
539 || ((orig
[PCI_COMMAND
] ^ d
->config
[PCI_COMMAND
])
540 & (PCI_COMMAND_MEMORY
| PCI_COMMAND_IO
)))
541 pci_update_mappings(d
);
544 void pci_data_write(void *opaque
, uint32_t addr
, uint32_t val
, int len
)
548 int config_addr
, bus_num
;
550 #if defined(DEBUG_PCI) && 0
551 printf("pci_data_write: addr=%08x val=%08x len=%d\n",
554 bus_num
= (addr
>> 16) & 0xff;
555 while (s
&& s
->bus_num
!= bus_num
)
559 pci_dev
= s
->devices
[(addr
>> 8) & 0xff];
562 config_addr
= addr
& 0xff;
563 #if defined(DEBUG_PCI)
564 printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
565 pci_dev
->name
, config_addr
, val
, len
);
567 pci_dev
->config_write(pci_dev
, config_addr
, val
, len
);
570 uint32_t pci_data_read(void *opaque
, uint32_t addr
, int len
)
574 int config_addr
, bus_num
;
577 bus_num
= (addr
>> 16) & 0xff;
578 while (s
&& s
->bus_num
!= bus_num
)
582 pci_dev
= s
->devices
[(addr
>> 8) & 0xff];
599 config_addr
= addr
& 0xff;
600 val
= pci_dev
->config_read(pci_dev
, config_addr
, len
);
601 #if defined(DEBUG_PCI)
602 printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
603 pci_dev
->name
, config_addr
, val
, len
);
606 #if defined(DEBUG_PCI) && 0
607 printf("pci_data_read: addr=%08x val=%08x len=%d\n",
613 /***********************************************************/
614 /* generic PCI irq support */
616 /* 0 <= irq_num <= 3. level must be 0 or 1 */
617 static void pci_set_irq(void *opaque
, int irq_num
, int level
)
619 PCIDevice
*pci_dev
= (PCIDevice
*)opaque
;
623 change
= level
- pci_dev
->irq_state
[irq_num
];
627 pci_dev
->irq_state
[irq_num
] = level
;
630 irq_num
= bus
->map_irq(pci_dev
, irq_num
);
633 pci_dev
= bus
->parent_dev
;
635 bus
->irq_count
[irq_num
] += change
;
636 bus
->set_irq(bus
->irq_opaque
, irq_num
, bus
->irq_count
[irq_num
] != 0);
639 /***********************************************************/
640 /* monitor info on PCI */
647 static const pci_class_desc pci_class_descriptions
[] =
649 { 0x0100, "SCSI controller"},
650 { 0x0101, "IDE controller"},
651 { 0x0102, "Floppy controller"},
652 { 0x0103, "IPI controller"},
653 { 0x0104, "RAID controller"},
654 { 0x0106, "SATA controller"},
655 { 0x0107, "SAS controller"},
656 { 0x0180, "Storage controller"},
657 { 0x0200, "Ethernet controller"},
658 { 0x0201, "Token Ring controller"},
659 { 0x0202, "FDDI controller"},
660 { 0x0203, "ATM controller"},
661 { 0x0280, "Network controller"},
662 { 0x0300, "VGA controller"},
663 { 0x0301, "XGA controller"},
664 { 0x0302, "3D controller"},
665 { 0x0380, "Display controller"},
666 { 0x0400, "Video controller"},
667 { 0x0401, "Audio controller"},
669 { 0x0480, "Multimedia controller"},
670 { 0x0500, "RAM controller"},
671 { 0x0501, "Flash controller"},
672 { 0x0580, "Memory controller"},
673 { 0x0600, "Host bridge"},
674 { 0x0601, "ISA bridge"},
675 { 0x0602, "EISA bridge"},
676 { 0x0603, "MC bridge"},
677 { 0x0604, "PCI bridge"},
678 { 0x0605, "PCMCIA bridge"},
679 { 0x0606, "NUBUS bridge"},
680 { 0x0607, "CARDBUS bridge"},
681 { 0x0608, "RACEWAY bridge"},
683 { 0x0c03, "USB controller"},
687 static void pci_info_device(PCIDevice
*d
)
689 Monitor
*mon
= cur_mon
;
692 const pci_class_desc
*desc
;
694 monitor_printf(mon
, " Bus %2d, device %3d, function %d:\n",
695 d
->bus
->bus_num
, d
->devfn
>> 3, d
->devfn
& 7);
696 class = le16_to_cpu(*((uint16_t *)(d
->config
+ PCI_CLASS_DEVICE
)));
697 monitor_printf(mon
, " ");
698 desc
= pci_class_descriptions
;
699 while (desc
->desc
&& class != desc
->class)
702 monitor_printf(mon
, "%s", desc
->desc
);
704 monitor_printf(mon
, "Class %04x", class);
706 monitor_printf(mon
, ": PCI device %04x:%04x\n",
707 le16_to_cpu(*((uint16_t *)(d
->config
+ PCI_VENDOR_ID
))),
708 le16_to_cpu(*((uint16_t *)(d
->config
+ PCI_DEVICE_ID
))));
710 if (d
->config
[PCI_INTERRUPT_PIN
] != 0) {
711 monitor_printf(mon
, " IRQ %d.\n",
712 d
->config
[PCI_INTERRUPT_LINE
]);
714 if (class == 0x0604) {
715 monitor_printf(mon
, " BUS %d.\n", d
->config
[0x19]);
717 for(i
= 0;i
< PCI_NUM_REGIONS
; i
++) {
718 r
= &d
->io_regions
[i
];
720 monitor_printf(mon
, " BAR%d: ", i
);
721 if (r
->type
& PCI_ADDRESS_SPACE_IO
) {
722 monitor_printf(mon
, "I/O at 0x%04x [0x%04x].\n",
723 r
->addr
, r
->addr
+ r
->size
- 1);
725 monitor_printf(mon
, "32 bit memory at 0x%08x [0x%08x].\n",
726 r
->addr
, r
->addr
+ r
->size
- 1);
730 if (class == 0x0604 && d
->config
[0x19] != 0) {
731 pci_for_each_device(d
->config
[0x19], pci_info_device
);
735 void pci_for_each_device(int bus_num
, void (*fn
)(PCIDevice
*d
))
737 PCIBus
*bus
= first_bus
;
741 while (bus
&& bus
->bus_num
!= bus_num
)
744 for(devfn
= 0; devfn
< 256; devfn
++) {
745 d
= bus
->devices
[devfn
];
752 void pci_info(Monitor
*mon
)
754 pci_for_each_device(0, pci_info_device
);
757 PCIDevice
*pci_create(const char *name
, const char *devaddr
)
763 bus
= pci_get_bus_devfn(&devfn
, devaddr
);
765 fprintf(stderr
, "Invalid PCI device address %s for device %s\n",
770 dev
= qdev_create(&bus
->qbus
, name
);
771 qdev_set_prop_int(dev
, "devfn", devfn
);
772 return (PCIDevice
*)dev
;
775 static const char * const pci_nic_models
[] = {
787 static const char * const pci_nic_names
[] = {
799 /* Initialize a PCI NIC. */
800 PCIDevice
*pci_nic_init(NICInfo
*nd
, const char *default_model
,
801 const char *default_devaddr
)
803 const char *devaddr
= nd
->devaddr
? nd
->devaddr
: default_devaddr
;
808 qemu_check_nic_model_list(nd
, pci_nic_models
, default_model
);
810 for (i
= 0; pci_nic_models
[i
]; i
++) {
811 if (strcmp(nd
->model
, pci_nic_models
[i
]) == 0) {
812 pci_dev
= pci_create(pci_nic_names
[i
], devaddr
);
813 dev
= &pci_dev
->qdev
;
814 qdev_set_netdev(dev
, nd
);
829 static void pci_bridge_write_config(PCIDevice
*d
,
830 uint32_t address
, uint32_t val
, int len
)
832 PCIBridge
*s
= (PCIBridge
*)d
;
834 pci_default_write_config(d
, address
, val
, len
);
835 s
->bus
->bus_num
= d
->config
[PCI_SECONDARY_BUS
];
838 PCIBus
*pci_find_bus(int bus_num
)
840 PCIBus
*bus
= first_bus
;
842 while (bus
&& bus
->bus_num
!= bus_num
)
848 PCIDevice
*pci_find_device(int bus_num
, int slot
, int function
)
850 PCIBus
*bus
= pci_find_bus(bus_num
);
855 return bus
->devices
[PCI_DEVFN(slot
, function
)];
858 PCIBus
*pci_bridge_init(PCIBus
*bus
, int devfn
, uint16_t vid
, uint16_t did
,
859 pci_map_irq_fn map_irq
, const char *name
)
862 s
= (PCIBridge
*)pci_register_device(bus
, name
, sizeof(PCIBridge
),
863 devfn
, NULL
, pci_bridge_write_config
);
865 pci_config_set_vendor_id(s
->dev
.config
, vid
);
866 pci_config_set_device_id(s
->dev
.config
, did
);
868 s
->dev
.config
[0x04] = 0x06; // command = bus master, pci mem
869 s
->dev
.config
[0x05] = 0x00;
870 s
->dev
.config
[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
871 s
->dev
.config
[0x07] = 0x00; // status = fast devsel
872 s
->dev
.config
[0x08] = 0x00; // revision
873 s
->dev
.config
[0x09] = 0x00; // programming i/f
874 pci_config_set_class(s
->dev
.config
, PCI_CLASS_BRIDGE_PCI
);
875 s
->dev
.config
[0x0D] = 0x10; // latency_timer
876 s
->dev
.config
[PCI_HEADER_TYPE
] =
877 PCI_HEADER_TYPE_MULTI_FUNCTION
| PCI_HEADER_TYPE_BRIDGE
; // header_type
878 s
->dev
.config
[0x1E] = 0xa0; // secondary status
880 s
->bus
= pci_register_secondary_bus(&s
->dev
, map_irq
);
884 static void pci_qdev_init(DeviceState
*qdev
, DeviceInfo
*base
)
886 PCIDevice
*pci_dev
= (PCIDevice
*)qdev
;
887 PCIDeviceInfo
*info
= container_of(base
, PCIDeviceInfo
, qdev
);
891 bus
= FROM_QBUS(PCIBus
, qdev_get_parent_bus(qdev
));
892 devfn
= qdev_get_prop_int(qdev
, "devfn", -1);
893 pci_dev
= do_pci_register_device(pci_dev
, bus
, "FIXME", devfn
,
894 info
->config_read
, info
->config_write
);
899 void pci_qdev_register(PCIDeviceInfo
*info
)
901 info
->qdev
.init
= pci_qdev_init
;
902 info
->qdev
.bus_info
= &pci_bus_info
;
903 qdev_register(&info
->qdev
);
906 void pci_qdev_register_many(PCIDeviceInfo
*info
)
908 while (info
->qdev
.name
) {
909 pci_qdev_register(info
);
914 PCIDevice
*pci_create_simple(PCIBus
*bus
, int devfn
, const char *name
)
918 dev
= qdev_create(&bus
->qbus
, name
);
919 qdev_set_prop_int(dev
, "devfn", devfn
);
922 return (PCIDevice
*)dev
;
925 static int pci_find_space(PCIDevice
*pdev
, uint8_t size
)
927 int offset
= PCI_CONFIG_HEADER_SIZE
;
929 for (i
= PCI_CONFIG_HEADER_SIZE
; i
< PCI_CONFIG_SPACE_SIZE
; ++i
)
932 else if (i
- offset
+ 1 == size
)
937 static uint8_t pci_find_capability_list(PCIDevice
*pdev
, uint8_t cap_id
,
942 if (!(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
))
945 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
946 prev
= next
+ PCI_CAP_LIST_NEXT
)
947 if (pdev
->config
[next
+ PCI_CAP_LIST_ID
] == cap_id
)
955 /* Reserve space and add capability to the linked list in pci config space */
956 int pci_add_capability(PCIDevice
*pdev
, uint8_t cap_id
, uint8_t size
)
958 uint8_t offset
= pci_find_space(pdev
, size
);
959 uint8_t *config
= pdev
->config
+ offset
;
962 config
[PCI_CAP_LIST_ID
] = cap_id
;
963 config
[PCI_CAP_LIST_NEXT
] = pdev
->config
[PCI_CAPABILITY_LIST
];
964 pdev
->config
[PCI_CAPABILITY_LIST
] = offset
;
965 pdev
->config
[PCI_STATUS
] |= PCI_STATUS_CAP_LIST
;
966 memset(pdev
->used
+ offset
, 0xFF, size
);
967 /* Make capability read-only by default */
968 memset(pdev
->wmask
+ offset
, 0, size
);
969 /* Check capability by default */
970 memset(pdev
->cmask
+ offset
, 0xFF, size
);
974 /* Unlink capability from the pci config space. */
975 void pci_del_capability(PCIDevice
*pdev
, uint8_t cap_id
, uint8_t size
)
977 uint8_t prev
, offset
= pci_find_capability_list(pdev
, cap_id
, &prev
);
980 pdev
->config
[prev
] = pdev
->config
[offset
+ PCI_CAP_LIST_NEXT
];
981 /* Make capability writeable again */
982 memset(pdev
->wmask
+ offset
, 0xff, size
);
983 /* Clear cmask as device-specific registers can't be checked */
984 memset(pdev
->cmask
+ offset
, 0, size
);
985 memset(pdev
->used
+ offset
, 0, size
);
987 if (!pdev
->config
[PCI_CAPABILITY_LIST
])
988 pdev
->config
[PCI_STATUS
] &= ~PCI_STATUS_CAP_LIST
;
991 /* Reserve space for capability at a known offset (to call after load). */
992 void pci_reserve_capability(PCIDevice
*pdev
, uint8_t offset
, uint8_t size
)
994 memset(pdev
->used
+ offset
, 0xff, size
);
997 uint8_t pci_find_capability(PCIDevice
*pdev
, uint8_t cap_id
)
999 return pci_find_capability_list(pdev
, cap_id
, NULL
);
1002 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
)
1004 PCIDevice
*d
= (PCIDevice
*)dev
;
1005 const pci_class_desc
*desc
;
1010 class = le16_to_cpu(*((uint16_t *)(d
->config
+ PCI_CLASS_DEVICE
)));
1011 desc
= pci_class_descriptions
;
1012 while (desc
->desc
&& class != desc
->class)
1015 snprintf(ctxt
, sizeof(ctxt
), "%s", desc
->desc
);
1017 snprintf(ctxt
, sizeof(ctxt
), "Class %04x", class);
1020 monitor_printf(mon
, "%*sclass %s, addr %02x:%02x.%x, "
1021 "pci id %04x:%04x (sub %04x:%04x)\n",
1023 d
->bus
->bus_num
, d
->devfn
>> 3, d
->devfn
& 7,
1024 le16_to_cpu(*((uint16_t *)(d
->config
+ PCI_VENDOR_ID
))),
1025 le16_to_cpu(*((uint16_t *)(d
->config
+ PCI_DEVICE_ID
))),
1026 le16_to_cpu(*((uint16_t *)(d
->config
+ PCI_SUBSYSTEM_VENDOR_ID
))),
1027 le16_to_cpu(*((uint16_t *)(d
->config
+ PCI_SUBSYSTEM_ID
))));
1028 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1029 r
= &d
->io_regions
[i
];
1032 monitor_printf(mon
, "%*sbar %d: %s at 0x%x [0x%x]\n", indent
, "",
1033 i
, r
->type
& PCI_ADDRESS_SPACE_IO
? "i/o" : "mem",
1034 r
->addr
, r
->addr
+ r
->size
- 1);