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target/ppc: convert vsplt[bhw] to use vector operations
[qemu/kevin.git] / target / ppc / translate / vmx-impl.inc.c
blob41ddbd879f14347ecd73cf9ac237c70497e29eba
1 /*
2 * translate/vmx-impl.c
3 *
4 * Altivec/VMX translation
5 */
6
7 /*** Altivec vector extension ***/
8 /* Altivec registers moves */
9
10 static inline TCGv_ptr gen_avr_ptr(int reg)
11 {
12 TCGv_ptr r = tcg_temp_new_ptr();
13 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, vsr[32 + reg].u64[0]));
14 return r;
15 }
16
17 static inline long avr64_offset(int reg, bool high)
18 {
19 return offsetof(CPUPPCState, vsr[32 + reg].u64[(high ? 0 : 1)]);
20 }
21
22 #define GEN_VR_LDX(name, opc2, opc3) \
23 static void glue(gen_, name)(DisasContext *ctx) \
24 { \
25 TCGv EA; \
26 TCGv_i64 avr; \
27 if (unlikely(!ctx->altivec_enabled)) { \
28 gen_exception(ctx, POWERPC_EXCP_VPU); \
29 return; \
30 } \
31 gen_set_access_type(ctx, ACCESS_INT); \
32 avr = tcg_temp_new_i64(); \
33 EA = tcg_temp_new(); \
34 gen_addr_reg_index(ctx, EA); \
35 tcg_gen_andi_tl(EA, EA, ~0xf); \
36 /* We only need to swap high and low halves. gen_qemu_ld64_i64 does \
37 necessary 64-bit byteswap already. */ \
38 if (ctx->le_mode) { \
39 gen_qemu_ld64_i64(ctx, avr, EA); \
40 set_avr64(rD(ctx->opcode), avr, false); \
41 tcg_gen_addi_tl(EA, EA, 8); \
42 gen_qemu_ld64_i64(ctx, avr, EA); \
43 set_avr64(rD(ctx->opcode), avr, true); \
44 } else { \
45 gen_qemu_ld64_i64(ctx, avr, EA); \
46 set_avr64(rD(ctx->opcode), avr, true); \
47 tcg_gen_addi_tl(EA, EA, 8); \
48 gen_qemu_ld64_i64(ctx, avr, EA); \
49 set_avr64(rD(ctx->opcode), avr, false); \
50 } \
51 tcg_temp_free(EA); \
52 tcg_temp_free_i64(avr); \
53 }
54
55 #define GEN_VR_STX(name, opc2, opc3) \
56 static void gen_st##name(DisasContext *ctx) \
57 { \
58 TCGv EA; \
59 TCGv_i64 avr; \
60 if (unlikely(!ctx->altivec_enabled)) { \
61 gen_exception(ctx, POWERPC_EXCP_VPU); \
62 return; \
63 } \
64 gen_set_access_type(ctx, ACCESS_INT); \
65 avr = tcg_temp_new_i64(); \
66 EA = tcg_temp_new(); \
67 gen_addr_reg_index(ctx, EA); \
68 tcg_gen_andi_tl(EA, EA, ~0xf); \
69 /* We only need to swap high and low halves. gen_qemu_st64_i64 does \
70 necessary 64-bit byteswap already. */ \
71 if (ctx->le_mode) { \
72 get_avr64(avr, rD(ctx->opcode), false); \
73 gen_qemu_st64_i64(ctx, avr, EA); \
74 tcg_gen_addi_tl(EA, EA, 8); \
75 get_avr64(avr, rD(ctx->opcode), true); \
76 gen_qemu_st64_i64(ctx, avr, EA); \
77 } else { \
78 get_avr64(avr, rD(ctx->opcode), true); \
79 gen_qemu_st64_i64(ctx, avr, EA); \
80 tcg_gen_addi_tl(EA, EA, 8); \
81 get_avr64(avr, rD(ctx->opcode), false); \
82 gen_qemu_st64_i64(ctx, avr, EA); \
83 } \
84 tcg_temp_free(EA); \
85 tcg_temp_free_i64(avr); \
86 }
87
88 #define GEN_VR_LVE(name, opc2, opc3, size) \
89 static void gen_lve##name(DisasContext *ctx) \
90 { \
91 TCGv EA; \
92 TCGv_ptr rs; \
93 if (unlikely(!ctx->altivec_enabled)) { \
94 gen_exception(ctx, POWERPC_EXCP_VPU); \
95 return; \
96 } \
97 gen_set_access_type(ctx, ACCESS_INT); \
98 EA = tcg_temp_new(); \
99 gen_addr_reg_index(ctx, EA); \
100 if (size > 1) { \
101 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
102 } \
103 rs = gen_avr_ptr(rS(ctx->opcode)); \
104 gen_helper_lve##name(cpu_env, rs, EA); \
105 tcg_temp_free(EA); \
106 tcg_temp_free_ptr(rs); \
107 }
108
109 #define GEN_VR_STVE(name, opc2, opc3, size) \
110 static void gen_stve##name(DisasContext *ctx) \
111 { \
112 TCGv EA; \
113 TCGv_ptr rs; \
114 if (unlikely(!ctx->altivec_enabled)) { \
115 gen_exception(ctx, POWERPC_EXCP_VPU); \
116 return; \
117 } \
118 gen_set_access_type(ctx, ACCESS_INT); \
119 EA = tcg_temp_new(); \
120 gen_addr_reg_index(ctx, EA); \
121 if (size > 1) { \
122 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
123 } \
124 rs = gen_avr_ptr(rS(ctx->opcode)); \
125 gen_helper_stve##name(cpu_env, rs, EA); \
126 tcg_temp_free(EA); \
127 tcg_temp_free_ptr(rs); \
128 }
129
130 GEN_VR_LDX(lvx, 0x07, 0x03);
131 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
132 GEN_VR_LDX(lvxl, 0x07, 0x0B);
133
134 GEN_VR_LVE(bx, 0x07, 0x00, 1);
135 GEN_VR_LVE(hx, 0x07, 0x01, 2);
136 GEN_VR_LVE(wx, 0x07, 0x02, 4);
137
138 GEN_VR_STX(svx, 0x07, 0x07);
139 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
140 GEN_VR_STX(svxl, 0x07, 0x0F);
141
142 GEN_VR_STVE(bx, 0x07, 0x04, 1);
143 GEN_VR_STVE(hx, 0x07, 0x05, 2);
144 GEN_VR_STVE(wx, 0x07, 0x06, 4);
145
146 static void gen_lvsl(DisasContext *ctx)
147 {
148 TCGv_ptr rd;
149 TCGv EA;
150 if (unlikely(!ctx->altivec_enabled)) {
151 gen_exception(ctx, POWERPC_EXCP_VPU);
152 return;
153 }
154 EA = tcg_temp_new();
155 gen_addr_reg_index(ctx, EA);
156 rd = gen_avr_ptr(rD(ctx->opcode));
157 gen_helper_lvsl(rd, EA);
158 tcg_temp_free(EA);
159 tcg_temp_free_ptr(rd);
160 }
161
162 static void gen_lvsr(DisasContext *ctx)
163 {
164 TCGv_ptr rd;
165 TCGv EA;
166 if (unlikely(!ctx->altivec_enabled)) {
167 gen_exception(ctx, POWERPC_EXCP_VPU);
168 return;
169 }
170 EA = tcg_temp_new();
171 gen_addr_reg_index(ctx, EA);
172 rd = gen_avr_ptr(rD(ctx->opcode));
173 gen_helper_lvsr(rd, EA);
174 tcg_temp_free(EA);
175 tcg_temp_free_ptr(rd);
176 }
177
178 static void gen_mfvscr(DisasContext *ctx)
179 {
180 TCGv_i32 t;
181 TCGv_i64 avr;
182 if (unlikely(!ctx->altivec_enabled)) {
183 gen_exception(ctx, POWERPC_EXCP_VPU);
184 return;
185 }
186 avr = tcg_temp_new_i64();
187 tcg_gen_movi_i64(avr, 0);
188 set_avr64(rD(ctx->opcode), avr, true);
189 t = tcg_temp_new_i32();
190 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
191 tcg_gen_extu_i32_i64(avr, t);
192 set_avr64(rD(ctx->opcode), avr, false);
193 tcg_temp_free_i32(t);
194 tcg_temp_free_i64(avr);
195 }
196
197 static void gen_mtvscr(DisasContext *ctx)
198 {
199 TCGv_ptr p;
200 if (unlikely(!ctx->altivec_enabled)) {
201 gen_exception(ctx, POWERPC_EXCP_VPU);
202 return;
203 }
204 p = gen_avr_ptr(rB(ctx->opcode));
205 gen_helper_mtvscr(cpu_env, p);
206 tcg_temp_free_ptr(p);
207 }
208
209 #define GEN_VX_VMUL10(name, add_cin, ret_carry) \
210 static void glue(gen_, name)(DisasContext *ctx) \
211 { \
212 TCGv_i64 t0; \
213 TCGv_i64 t1; \
214 TCGv_i64 t2; \
215 TCGv_i64 avr; \
216 TCGv_i64 ten, z; \
217 \
218 if (unlikely(!ctx->altivec_enabled)) { \
219 gen_exception(ctx, POWERPC_EXCP_VPU); \
220 return; \
221 } \
222 \
223 t0 = tcg_temp_new_i64(); \
224 t1 = tcg_temp_new_i64(); \
225 t2 = tcg_temp_new_i64(); \
226 avr = tcg_temp_new_i64(); \
227 ten = tcg_const_i64(10); \
228 z = tcg_const_i64(0); \
229 \
230 if (add_cin) { \
231 get_avr64(avr, rA(ctx->opcode), false); \
232 tcg_gen_mulu2_i64(t0, t1, avr, ten); \
233 get_avr64(avr, rB(ctx->opcode), false); \
234 tcg_gen_andi_i64(t2, avr, 0xF); \
235 tcg_gen_add2_i64(avr, t2, t0, t1, t2, z); \
236 set_avr64(rD(ctx->opcode), avr, false); \
237 } else { \
238 get_avr64(avr, rA(ctx->opcode), false); \
239 tcg_gen_mulu2_i64(avr, t2, avr, ten); \
240 set_avr64(rD(ctx->opcode), avr, false); \
241 } \
242 \
243 if (ret_carry) { \
244 get_avr64(avr, rA(ctx->opcode), true); \
245 tcg_gen_mulu2_i64(t0, t1, avr, ten); \
246 tcg_gen_add2_i64(t0, avr, t0, t1, t2, z); \
247 set_avr64(rD(ctx->opcode), avr, false); \
248 set_avr64(rD(ctx->opcode), z, true); \
249 } else { \
250 get_avr64(avr, rA(ctx->opcode), true); \
251 tcg_gen_mul_i64(t0, avr, ten); \
252 tcg_gen_add_i64(avr, t0, t2); \
253 set_avr64(rD(ctx->opcode), avr, true); \
254 } \
255 \
256 tcg_temp_free_i64(t0); \
257 tcg_temp_free_i64(t1); \
258 tcg_temp_free_i64(t2); \
259 tcg_temp_free_i64(avr); \
260 tcg_temp_free_i64(ten); \
261 tcg_temp_free_i64(z); \
262 } \
263
264 GEN_VX_VMUL10(vmul10uq, 0, 0);
265 GEN_VX_VMUL10(vmul10euq, 1, 0);
266 GEN_VX_VMUL10(vmul10cuq, 0, 1);
267 GEN_VX_VMUL10(vmul10ecuq, 1, 1);
268
269 #define GEN_VXFORM_V(name, vece, tcg_op, opc2, opc3) \
270 static void glue(gen_, name)(DisasContext *ctx) \
271 { \
272 if (unlikely(!ctx->altivec_enabled)) { \
273 gen_exception(ctx, POWERPC_EXCP_VPU); \
274 return; \
275 } \
276 \
277 tcg_op(vece, \
278 avr64_offset(rD(ctx->opcode), true), \
279 avr64_offset(rA(ctx->opcode), true), \
280 avr64_offset(rB(ctx->opcode), true), \
281 16, 16); \
282 }
283
284 /* Logical operations */
285 GEN_VXFORM_V(vand, MO_64, tcg_gen_gvec_and, 2, 16);
286 GEN_VXFORM_V(vandc, MO_64, tcg_gen_gvec_andc, 2, 17);
287 GEN_VXFORM_V(vor, MO_64, tcg_gen_gvec_or, 2, 18);
288 GEN_VXFORM_V(vxor, MO_64, tcg_gen_gvec_xor, 2, 19);
289 GEN_VXFORM_V(vnor, MO_64, tcg_gen_gvec_nor, 2, 20);
290 GEN_VXFORM_V(veqv, MO_64, tcg_gen_gvec_eqv, 2, 26);
291 GEN_VXFORM_V(vnand, MO_64, tcg_gen_gvec_nand, 2, 22);
292 GEN_VXFORM_V(vorc, MO_64, tcg_gen_gvec_orc, 2, 21);
293
294 #define GEN_VXFORM(name, opc2, opc3) \
295 static void glue(gen_, name)(DisasContext *ctx) \
296 { \
297 TCGv_ptr ra, rb, rd; \
298 if (unlikely(!ctx->altivec_enabled)) { \
299 gen_exception(ctx, POWERPC_EXCP_VPU); \
300 return; \
301 } \
302 ra = gen_avr_ptr(rA(ctx->opcode)); \
303 rb = gen_avr_ptr(rB(ctx->opcode)); \
304 rd = gen_avr_ptr(rD(ctx->opcode)); \
305 gen_helper_##name (rd, ra, rb); \
306 tcg_temp_free_ptr(ra); \
307 tcg_temp_free_ptr(rb); \
308 tcg_temp_free_ptr(rd); \
309 }
310
311 #define GEN_VXFORM_ENV(name, opc2, opc3) \
312 static void glue(gen_, name)(DisasContext *ctx) \
313 { \
314 TCGv_ptr ra, rb, rd; \
315 if (unlikely(!ctx->altivec_enabled)) { \
316 gen_exception(ctx, POWERPC_EXCP_VPU); \
317 return; \
318 } \
319 ra = gen_avr_ptr(rA(ctx->opcode)); \
320 rb = gen_avr_ptr(rB(ctx->opcode)); \
321 rd = gen_avr_ptr(rD(ctx->opcode)); \
322 gen_helper_##name(cpu_env, rd, ra, rb); \
323 tcg_temp_free_ptr(ra); \
324 tcg_temp_free_ptr(rb); \
325 tcg_temp_free_ptr(rd); \
326 }
327
328 #define GEN_VXFORM3(name, opc2, opc3) \
329 static void glue(gen_, name)(DisasContext *ctx) \
330 { \
331 TCGv_ptr ra, rb, rc, rd; \
332 if (unlikely(!ctx->altivec_enabled)) { \
333 gen_exception(ctx, POWERPC_EXCP_VPU); \
334 return; \
335 } \
336 ra = gen_avr_ptr(rA(ctx->opcode)); \
337 rb = gen_avr_ptr(rB(ctx->opcode)); \
338 rc = gen_avr_ptr(rC(ctx->opcode)); \
339 rd = gen_avr_ptr(rD(ctx->opcode)); \
340 gen_helper_##name(rd, ra, rb, rc); \
341 tcg_temp_free_ptr(ra); \
342 tcg_temp_free_ptr(rb); \
343 tcg_temp_free_ptr(rc); \
344 tcg_temp_free_ptr(rd); \
345 }
346
347 /*
348 * Support for Altivec instruction pairs that use bit 31 (Rc) as
349 * an opcode bit. In general, these pairs come from different
350 * versions of the ISA, so we must also support a pair of flags for
351 * each instruction.
352 */
353 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
354 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
355 { \
356 if ((Rc(ctx->opcode) == 0) && \
357 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
358 gen_##name0(ctx); \
359 } else if ((Rc(ctx->opcode) == 1) && \
360 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
361 gen_##name1(ctx); \
362 } else { \
363 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
364 } \
365 }
366
367 /* Adds support to provide invalid mask */
368 #define GEN_VXFORM_DUAL_EXT(name0, flg0, flg2_0, inval0, \
369 name1, flg1, flg2_1, inval1) \
370 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
371 { \
372 if ((Rc(ctx->opcode) == 0) && \
373 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0)) && \
374 !(ctx->opcode & inval0)) { \
375 gen_##name0(ctx); \
376 } else if ((Rc(ctx->opcode) == 1) && \
377 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1)) && \
378 !(ctx->opcode & inval1)) { \
379 gen_##name1(ctx); \
380 } else { \
381 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
382 } \
383 }
384
385 #define GEN_VXFORM_HETRO(name, opc2, opc3) \
386 static void glue(gen_, name)(DisasContext *ctx) \
387 { \
388 TCGv_ptr rb; \
389 if (unlikely(!ctx->altivec_enabled)) { \
390 gen_exception(ctx, POWERPC_EXCP_VPU); \
391 return; \
392 } \
393 rb = gen_avr_ptr(rB(ctx->opcode)); \
394 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], rb); \
395 tcg_temp_free_ptr(rb); \
396 }
397
398 GEN_VXFORM_V(vaddubm, MO_8, tcg_gen_gvec_add, 0, 0);
399 GEN_VXFORM_DUAL_EXT(vaddubm, PPC_ALTIVEC, PPC_NONE, 0, \
400 vmul10cuq, PPC_NONE, PPC2_ISA300, 0x0000F800)
401 GEN_VXFORM_V(vadduhm, MO_16, tcg_gen_gvec_add, 0, 1);
402 GEN_VXFORM_DUAL(vadduhm, PPC_ALTIVEC, PPC_NONE, \
403 vmul10ecuq, PPC_NONE, PPC2_ISA300)
404 GEN_VXFORM_V(vadduwm, MO_32, tcg_gen_gvec_add, 0, 2);
405 GEN_VXFORM_V(vaddudm, MO_64, tcg_gen_gvec_add, 0, 3);
406 GEN_VXFORM_V(vsububm, MO_8, tcg_gen_gvec_sub, 0, 16);
407 GEN_VXFORM_V(vsubuhm, MO_16, tcg_gen_gvec_sub, 0, 17);
408 GEN_VXFORM_V(vsubuwm, MO_32, tcg_gen_gvec_sub, 0, 18);
409 GEN_VXFORM_V(vsubudm, MO_64, tcg_gen_gvec_sub, 0, 19);
410 GEN_VXFORM(vmaxub, 1, 0);
411 GEN_VXFORM(vmaxuh, 1, 1);
412 GEN_VXFORM(vmaxuw, 1, 2);
413 GEN_VXFORM(vmaxud, 1, 3);
414 GEN_VXFORM(vmaxsb, 1, 4);
415 GEN_VXFORM(vmaxsh, 1, 5);
416 GEN_VXFORM(vmaxsw, 1, 6);
417 GEN_VXFORM(vmaxsd, 1, 7);
418 GEN_VXFORM(vminub, 1, 8);
419 GEN_VXFORM(vminuh, 1, 9);
420 GEN_VXFORM(vminuw, 1, 10);
421 GEN_VXFORM(vminud, 1, 11);
422 GEN_VXFORM(vminsb, 1, 12);
423 GEN_VXFORM(vminsh, 1, 13);
424 GEN_VXFORM(vminsw, 1, 14);
425 GEN_VXFORM(vminsd, 1, 15);
426 GEN_VXFORM(vavgub, 1, 16);
427 GEN_VXFORM(vabsdub, 1, 16);
428 GEN_VXFORM_DUAL(vavgub, PPC_ALTIVEC, PPC_NONE, \
429 vabsdub, PPC_NONE, PPC2_ISA300)
430 GEN_VXFORM(vavguh, 1, 17);
431 GEN_VXFORM(vabsduh, 1, 17);
432 GEN_VXFORM_DUAL(vavguh, PPC_ALTIVEC, PPC_NONE, \
433 vabsduh, PPC_NONE, PPC2_ISA300)
434 GEN_VXFORM(vavguw, 1, 18);
435 GEN_VXFORM(vabsduw, 1, 18);
436 GEN_VXFORM_DUAL(vavguw, PPC_ALTIVEC, PPC_NONE, \
437 vabsduw, PPC_NONE, PPC2_ISA300)
438 GEN_VXFORM(vavgsb, 1, 20);
439 GEN_VXFORM(vavgsh, 1, 21);
440 GEN_VXFORM(vavgsw, 1, 22);
441 GEN_VXFORM(vmrghb, 6, 0);
442 GEN_VXFORM(vmrghh, 6, 1);
443 GEN_VXFORM(vmrghw, 6, 2);
444 GEN_VXFORM(vmrglb, 6, 4);
445 GEN_VXFORM(vmrglh, 6, 5);
446 GEN_VXFORM(vmrglw, 6, 6);
447
448 static void gen_vmrgew(DisasContext *ctx)
449 {
450 TCGv_i64 tmp;
451 TCGv_i64 avr;
452 int VT, VA, VB;
453 if (unlikely(!ctx->altivec_enabled)) {
454 gen_exception(ctx, POWERPC_EXCP_VPU);
455 return;
456 }
457 VT = rD(ctx->opcode);
458 VA = rA(ctx->opcode);
459 VB = rB(ctx->opcode);
460 tmp = tcg_temp_new_i64();
461 avr = tcg_temp_new_i64();
462
463 get_avr64(avr, VB, true);
464 tcg_gen_shri_i64(tmp, avr, 32);
465 get_avr64(avr, VA, true);
466 tcg_gen_deposit_i64(avr, avr, tmp, 0, 32);
467 set_avr64(VT, avr, true);
468
469 get_avr64(avr, VB, false);
470 tcg_gen_shri_i64(tmp, avr, 32);
471 get_avr64(avr, VA, false);
472 tcg_gen_deposit_i64(avr, avr, tmp, 0, 32);
473 set_avr64(VT, avr, false);
474
475 tcg_temp_free_i64(tmp);
476 tcg_temp_free_i64(avr);
477 }
478
479 static void gen_vmrgow(DisasContext *ctx)
480 {
481 TCGv_i64 t0, t1;
482 TCGv_i64 avr;
483 int VT, VA, VB;
484 if (unlikely(!ctx->altivec_enabled)) {
485 gen_exception(ctx, POWERPC_EXCP_VPU);
486 return;
487 }
488 VT = rD(ctx->opcode);
489 VA = rA(ctx->opcode);
490 VB = rB(ctx->opcode);
491 t0 = tcg_temp_new_i64();
492 t1 = tcg_temp_new_i64();
493 avr = tcg_temp_new_i64();
494
495 get_avr64(t0, VB, true);
496 get_avr64(t1, VA, true);
497 tcg_gen_deposit_i64(avr, t0, t1, 32, 32);
498 set_avr64(VT, avr, true);
499
500 get_avr64(t0, VB, false);
501 get_avr64(t1, VA, false);
502 tcg_gen_deposit_i64(avr, t0, t1, 32, 32);
503 set_avr64(VT, avr, false);
504
505 tcg_temp_free_i64(t0);
506 tcg_temp_free_i64(t1);
507 tcg_temp_free_i64(avr);
508 }
509
510 GEN_VXFORM(vmuloub, 4, 0);
511 GEN_VXFORM(vmulouh, 4, 1);
512 GEN_VXFORM(vmulouw, 4, 2);
513 GEN_VXFORM(vmuluwm, 4, 2);
514 GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
515 vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
516 GEN_VXFORM(vmulosb, 4, 4);
517 GEN_VXFORM(vmulosh, 4, 5);
518 GEN_VXFORM(vmulosw, 4, 6);
519 GEN_VXFORM(vmuleub, 4, 8);
520 GEN_VXFORM(vmuleuh, 4, 9);
521 GEN_VXFORM(vmuleuw, 4, 10);
522 GEN_VXFORM(vmulesb, 4, 12);
523 GEN_VXFORM(vmulesh, 4, 13);
524 GEN_VXFORM(vmulesw, 4, 14);
525 GEN_VXFORM(vslb, 2, 4);
526 GEN_VXFORM(vslh, 2, 5);
527 GEN_VXFORM(vslw, 2, 6);
528 GEN_VXFORM(vrlwnm, 2, 6);
529 GEN_VXFORM_DUAL(vslw, PPC_ALTIVEC, PPC_NONE, \
530 vrlwnm, PPC_NONE, PPC2_ISA300)
531 GEN_VXFORM(vsld, 2, 23);
532 GEN_VXFORM(vsrb, 2, 8);
533 GEN_VXFORM(vsrh, 2, 9);
534 GEN_VXFORM(vsrw, 2, 10);
535 GEN_VXFORM(vsrd, 2, 27);
536 GEN_VXFORM(vsrab, 2, 12);
537 GEN_VXFORM(vsrah, 2, 13);
538 GEN_VXFORM(vsraw, 2, 14);
539 GEN_VXFORM(vsrad, 2, 15);
540 GEN_VXFORM(vsrv, 2, 28);
541 GEN_VXFORM(vslv, 2, 29);
542 GEN_VXFORM(vslo, 6, 16);
543 GEN_VXFORM(vsro, 6, 17);
544 GEN_VXFORM(vaddcuw, 0, 6);
545 GEN_VXFORM(vsubcuw, 0, 22);
546 GEN_VXFORM_ENV(vaddubs, 0, 8);
547 GEN_VXFORM_DUAL_EXT(vaddubs, PPC_ALTIVEC, PPC_NONE, 0, \
548 vmul10uq, PPC_NONE, PPC2_ISA300, 0x0000F800)
549 GEN_VXFORM_ENV(vadduhs, 0, 9);
550 GEN_VXFORM_DUAL(vadduhs, PPC_ALTIVEC, PPC_NONE, \
551 vmul10euq, PPC_NONE, PPC2_ISA300)
552 GEN_VXFORM_ENV(vadduws, 0, 10);
553 GEN_VXFORM_ENV(vaddsbs, 0, 12);
554 GEN_VXFORM_ENV(vaddshs, 0, 13);
555 GEN_VXFORM_ENV(vaddsws, 0, 14);
556 GEN_VXFORM_ENV(vsububs, 0, 24);
557 GEN_VXFORM_ENV(vsubuhs, 0, 25);
558 GEN_VXFORM_ENV(vsubuws, 0, 26);
559 GEN_VXFORM_ENV(vsubsbs, 0, 28);
560 GEN_VXFORM_ENV(vsubshs, 0, 29);
561 GEN_VXFORM_ENV(vsubsws, 0, 30);
562 GEN_VXFORM(vadduqm, 0, 4);
563 GEN_VXFORM(vaddcuq, 0, 5);
564 GEN_VXFORM3(vaddeuqm, 30, 0);
565 GEN_VXFORM3(vaddecuq, 30, 0);
566 GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
567 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
568 GEN_VXFORM(vsubuqm, 0, 20);
569 GEN_VXFORM(vsubcuq, 0, 21);
570 GEN_VXFORM3(vsubeuqm, 31, 0);
571 GEN_VXFORM3(vsubecuq, 31, 0);
572 GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
573 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
574 GEN_VXFORM(vrlb, 2, 0);
575 GEN_VXFORM(vrlh, 2, 1);
576 GEN_VXFORM(vrlw, 2, 2);
577 GEN_VXFORM(vrlwmi, 2, 2);
578 GEN_VXFORM_DUAL(vrlw, PPC_ALTIVEC, PPC_NONE, \
579 vrlwmi, PPC_NONE, PPC2_ISA300)
580 GEN_VXFORM(vrld, 2, 3);
581 GEN_VXFORM(vrldmi, 2, 3);
582 GEN_VXFORM_DUAL(vrld, PPC_NONE, PPC2_ALTIVEC_207, \
583 vrldmi, PPC_NONE, PPC2_ISA300)
584 GEN_VXFORM(vsl, 2, 7);
585 GEN_VXFORM(vrldnm, 2, 7);
586 GEN_VXFORM_DUAL(vsl, PPC_ALTIVEC, PPC_NONE, \
587 vrldnm, PPC_NONE, PPC2_ISA300)
588 GEN_VXFORM(vsr, 2, 11);
589 GEN_VXFORM_ENV(vpkuhum, 7, 0);
590 GEN_VXFORM_ENV(vpkuwum, 7, 1);
591 GEN_VXFORM_ENV(vpkudum, 7, 17);
592 GEN_VXFORM_ENV(vpkuhus, 7, 2);
593 GEN_VXFORM_ENV(vpkuwus, 7, 3);
594 GEN_VXFORM_ENV(vpkudus, 7, 19);
595 GEN_VXFORM_ENV(vpkshus, 7, 4);
596 GEN_VXFORM_ENV(vpkswus, 7, 5);
597 GEN_VXFORM_ENV(vpksdus, 7, 21);
598 GEN_VXFORM_ENV(vpkshss, 7, 6);
599 GEN_VXFORM_ENV(vpkswss, 7, 7);
600 GEN_VXFORM_ENV(vpksdss, 7, 23);
601 GEN_VXFORM(vpkpx, 7, 12);
602 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
603 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
604 GEN_VXFORM_ENV(vsum4shs, 4, 25);
605 GEN_VXFORM_ENV(vsum2sws, 4, 26);
606 GEN_VXFORM_ENV(vsumsws, 4, 30);
607 GEN_VXFORM_ENV(vaddfp, 5, 0);
608 GEN_VXFORM_ENV(vsubfp, 5, 1);
609 GEN_VXFORM_ENV(vmaxfp, 5, 16);
610 GEN_VXFORM_ENV(vminfp, 5, 17);
611 GEN_VXFORM_HETRO(vextublx, 6, 24)
612 GEN_VXFORM_HETRO(vextuhlx, 6, 25)
613 GEN_VXFORM_HETRO(vextuwlx, 6, 26)
614 GEN_VXFORM_DUAL(vmrgow, PPC_NONE, PPC2_ALTIVEC_207,
615 vextuwlx, PPC_NONE, PPC2_ISA300)
616 GEN_VXFORM_HETRO(vextubrx, 6, 28)
617 GEN_VXFORM_HETRO(vextuhrx, 6, 29)
618 GEN_VXFORM_HETRO(vextuwrx, 6, 30)
619 GEN_VXFORM_DUAL(vmrgew, PPC_NONE, PPC2_ALTIVEC_207, \
620 vextuwrx, PPC_NONE, PPC2_ISA300)
621
622 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
623 static void glue(gen_, name)(DisasContext *ctx) \
624 { \
625 TCGv_ptr ra, rb, rd; \
626 if (unlikely(!ctx->altivec_enabled)) { \
627 gen_exception(ctx, POWERPC_EXCP_VPU); \
628 return; \
629 } \
630 ra = gen_avr_ptr(rA(ctx->opcode)); \
631 rb = gen_avr_ptr(rB(ctx->opcode)); \
632 rd = gen_avr_ptr(rD(ctx->opcode)); \
633 gen_helper_##opname(cpu_env, rd, ra, rb); \
634 tcg_temp_free_ptr(ra); \
635 tcg_temp_free_ptr(rb); \
636 tcg_temp_free_ptr(rd); \
637 }
638
639 #define GEN_VXRFORM(name, opc2, opc3) \
640 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
641 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
642
643 /*
644 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
645 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
646 * come from different versions of the ISA, so we must also support a
647 * pair of flags for each instruction.
648 */
649 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
650 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
651 { \
652 if ((Rc(ctx->opcode) == 0) && \
653 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
654 if (Rc21(ctx->opcode) == 0) { \
655 gen_##name0(ctx); \
656 } else { \
657 gen_##name0##_(ctx); \
658 } \
659 } else if ((Rc(ctx->opcode) == 1) && \
660 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
661 if (Rc21(ctx->opcode) == 0) { \
662 gen_##name1(ctx); \
663 } else { \
664 gen_##name1##_(ctx); \
665 } \
666 } else { \
667 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
668 } \
669 }
670
671 GEN_VXRFORM(vcmpequb, 3, 0)
672 GEN_VXRFORM(vcmpequh, 3, 1)
673 GEN_VXRFORM(vcmpequw, 3, 2)
674 GEN_VXRFORM(vcmpequd, 3, 3)
675 GEN_VXRFORM(vcmpnezb, 3, 4)
676 GEN_VXRFORM(vcmpnezh, 3, 5)
677 GEN_VXRFORM(vcmpnezw, 3, 6)
678 GEN_VXRFORM(vcmpgtsb, 3, 12)
679 GEN_VXRFORM(vcmpgtsh, 3, 13)
680 GEN_VXRFORM(vcmpgtsw, 3, 14)
681 GEN_VXRFORM(vcmpgtsd, 3, 15)
682 GEN_VXRFORM(vcmpgtub, 3, 8)
683 GEN_VXRFORM(vcmpgtuh, 3, 9)
684 GEN_VXRFORM(vcmpgtuw, 3, 10)
685 GEN_VXRFORM(vcmpgtud, 3, 11)
686 GEN_VXRFORM(vcmpeqfp, 3, 3)
687 GEN_VXRFORM(vcmpgefp, 3, 7)
688 GEN_VXRFORM(vcmpgtfp, 3, 11)
689 GEN_VXRFORM(vcmpbfp, 3, 15)
690 GEN_VXRFORM(vcmpneb, 3, 0)
691 GEN_VXRFORM(vcmpneh, 3, 1)
692 GEN_VXRFORM(vcmpnew, 3, 2)
693
694 GEN_VXRFORM_DUAL(vcmpequb, PPC_ALTIVEC, PPC_NONE, \
695 vcmpneb, PPC_NONE, PPC2_ISA300)
696 GEN_VXRFORM_DUAL(vcmpequh, PPC_ALTIVEC, PPC_NONE, \
697 vcmpneh, PPC_NONE, PPC2_ISA300)
698 GEN_VXRFORM_DUAL(vcmpequw, PPC_ALTIVEC, PPC_NONE, \
699 vcmpnew, PPC_NONE, PPC2_ISA300)
700 GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
701 vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
702 GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
703 vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
704 GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
705 vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
706
707 #define GEN_VXFORM_DUPI(name, tcg_op, opc2, opc3) \
708 static void glue(gen_, name)(DisasContext *ctx) \
709 { \
710 int simm; \
711 if (unlikely(!ctx->altivec_enabled)) { \
712 gen_exception(ctx, POWERPC_EXCP_VPU); \
713 return; \
714 } \
715 simm = SIMM5(ctx->opcode); \
716 tcg_op(avr64_offset(rD(ctx->opcode), true), 16, 16, simm); \
717 }
718
719 GEN_VXFORM_DUPI(vspltisb, tcg_gen_gvec_dup8i, 6, 12);
720 GEN_VXFORM_DUPI(vspltish, tcg_gen_gvec_dup16i, 6, 13);
721 GEN_VXFORM_DUPI(vspltisw, tcg_gen_gvec_dup32i, 6, 14);
722
723 #define GEN_VXFORM_NOA(name, opc2, opc3) \
724 static void glue(gen_, name)(DisasContext *ctx) \
725 { \
726 TCGv_ptr rb, rd; \
727 if (unlikely(!ctx->altivec_enabled)) { \
728 gen_exception(ctx, POWERPC_EXCP_VPU); \
729 return; \
730 } \
731 rb = gen_avr_ptr(rB(ctx->opcode)); \
732 rd = gen_avr_ptr(rD(ctx->opcode)); \
733 gen_helper_##name (rd, rb); \
734 tcg_temp_free_ptr(rb); \
735 tcg_temp_free_ptr(rd); \
736 }
737
738 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
739 static void glue(gen_, name)(DisasContext *ctx) \
740 { \
741 TCGv_ptr rb, rd; \
742 \
743 if (unlikely(!ctx->altivec_enabled)) { \
744 gen_exception(ctx, POWERPC_EXCP_VPU); \
745 return; \
746 } \
747 rb = gen_avr_ptr(rB(ctx->opcode)); \
748 rd = gen_avr_ptr(rD(ctx->opcode)); \
749 gen_helper_##name(cpu_env, rd, rb); \
750 tcg_temp_free_ptr(rb); \
751 tcg_temp_free_ptr(rd); \
752 }
753
754 #define GEN_VXFORM_NOA_2(name, opc2, opc3, opc4) \
755 static void glue(gen_, name)(DisasContext *ctx) \
756 { \
757 TCGv_ptr rb, rd; \
758 if (unlikely(!ctx->altivec_enabled)) { \
759 gen_exception(ctx, POWERPC_EXCP_VPU); \
760 return; \
761 } \
762 rb = gen_avr_ptr(rB(ctx->opcode)); \
763 rd = gen_avr_ptr(rD(ctx->opcode)); \
764 gen_helper_##name(rd, rb); \
765 tcg_temp_free_ptr(rb); \
766 tcg_temp_free_ptr(rd); \
767 }
768
769 #define GEN_VXFORM_NOA_3(name, opc2, opc3, opc4) \
770 static void glue(gen_, name)(DisasContext *ctx) \
771 { \
772 TCGv_ptr rb; \
773 if (unlikely(!ctx->altivec_enabled)) { \
774 gen_exception(ctx, POWERPC_EXCP_VPU); \
775 return; \
776 } \
777 rb = gen_avr_ptr(rB(ctx->opcode)); \
778 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], rb); \
779 tcg_temp_free_ptr(rb); \
780 }
781 GEN_VXFORM_NOA(vupkhsb, 7, 8);
782 GEN_VXFORM_NOA(vupkhsh, 7, 9);
783 GEN_VXFORM_NOA(vupkhsw, 7, 25);
784 GEN_VXFORM_NOA(vupklsb, 7, 10);
785 GEN_VXFORM_NOA(vupklsh, 7, 11);
786 GEN_VXFORM_NOA(vupklsw, 7, 27);
787 GEN_VXFORM_NOA(vupkhpx, 7, 13);
788 GEN_VXFORM_NOA(vupklpx, 7, 15);
789 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
790 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
791 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
792 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
793 GEN_VXFORM_NOA_ENV(vrfim, 5, 11);
794 GEN_VXFORM_NOA_ENV(vrfin, 5, 8);
795 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
796 GEN_VXFORM_NOA_ENV(vrfiz, 5, 9);
797 GEN_VXFORM_NOA(vprtybw, 1, 24);
798 GEN_VXFORM_NOA(vprtybd, 1, 24);
799 GEN_VXFORM_NOA(vprtybq, 1, 24);
800
801 static void gen_vsplt(DisasContext *ctx, int vece)
802 {
803 int uimm, dofs, bofs;
804
805 if (unlikely(!ctx->altivec_enabled)) {
806 gen_exception(ctx, POWERPC_EXCP_VPU);
807 return;
808 }
809
810 uimm = UIMM5(ctx->opcode);
811 bofs = avr64_offset(rB(ctx->opcode), true);
812 dofs = avr64_offset(rD(ctx->opcode), true);
813
814 /* Experimental testing shows that hardware masks the immediate. */
815 bofs += (uimm << vece) & 15;
816 #ifndef HOST_WORDS_BIGENDIAN
817 bofs ^= 15;
818 bofs &= ~((1 << vece) - 1);
819 #endif
820
821 tcg_gen_gvec_dup_mem(vece, dofs, bofs, 16, 16);
822 }
823
824 #define GEN_VXFORM_VSPLT(name, vece, opc2, opc3) \
825 static void glue(gen_, name)(DisasContext *ctx) { gen_vsplt(ctx, vece); }
826
827 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
828 static void glue(gen_, name)(DisasContext *ctx) \
829 { \
830 TCGv_ptr rb, rd; \
831 TCGv_i32 uimm; \
832 \
833 if (unlikely(!ctx->altivec_enabled)) { \
834 gen_exception(ctx, POWERPC_EXCP_VPU); \
835 return; \
836 } \
837 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
838 rb = gen_avr_ptr(rB(ctx->opcode)); \
839 rd = gen_avr_ptr(rD(ctx->opcode)); \
840 gen_helper_##name(cpu_env, rd, rb, uimm); \
841 tcg_temp_free_i32(uimm); \
842 tcg_temp_free_ptr(rb); \
843 tcg_temp_free_ptr(rd); \
844 }
845
846 #define GEN_VXFORM_UIMM_SPLAT(name, opc2, opc3, splat_max) \
847 static void glue(gen_, name)(DisasContext *ctx) \
848 { \
849 TCGv_ptr rb, rd; \
850 uint8_t uimm = UIMM4(ctx->opcode); \
851 TCGv_i32 t0; \
852 if (unlikely(!ctx->altivec_enabled)) { \
853 gen_exception(ctx, POWERPC_EXCP_VPU); \
854 return; \
855 } \
856 if (uimm > splat_max) { \
857 uimm = 0; \
858 } \
859 t0 = tcg_temp_new_i32(); \
860 tcg_gen_movi_i32(t0, uimm); \
861 rb = gen_avr_ptr(rB(ctx->opcode)); \
862 rd = gen_avr_ptr(rD(ctx->opcode)); \
863 gen_helper_##name(rd, rb, t0); \
864 tcg_temp_free_i32(t0); \
865 tcg_temp_free_ptr(rb); \
866 tcg_temp_free_ptr(rd); \
867 }
868
869 GEN_VXFORM_VSPLT(vspltb, MO_8, 6, 8);
870 GEN_VXFORM_VSPLT(vsplth, MO_16, 6, 9);
871 GEN_VXFORM_VSPLT(vspltw, MO_32, 6, 10);
872 GEN_VXFORM_UIMM_SPLAT(vextractub, 6, 8, 15);
873 GEN_VXFORM_UIMM_SPLAT(vextractuh, 6, 9, 14);
874 GEN_VXFORM_UIMM_SPLAT(vextractuw, 6, 10, 12);
875 GEN_VXFORM_UIMM_SPLAT(vextractd, 6, 11, 8);
876 GEN_VXFORM_UIMM_SPLAT(vinsertb, 6, 12, 15);
877 GEN_VXFORM_UIMM_SPLAT(vinserth, 6, 13, 14);
878 GEN_VXFORM_UIMM_SPLAT(vinsertw, 6, 14, 12);
879 GEN_VXFORM_UIMM_SPLAT(vinsertd, 6, 15, 8);
880 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
881 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
882 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
883 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
884 GEN_VXFORM_DUAL(vspltb, PPC_ALTIVEC, PPC_NONE,
885 vextractub, PPC_NONE, PPC2_ISA300);
886 GEN_VXFORM_DUAL(vsplth, PPC_ALTIVEC, PPC_NONE,
887 vextractuh, PPC_NONE, PPC2_ISA300);
888 GEN_VXFORM_DUAL(vspltw, PPC_ALTIVEC, PPC_NONE,
889 vextractuw, PPC_NONE, PPC2_ISA300);
890 GEN_VXFORM_DUAL(vspltisb, PPC_ALTIVEC, PPC_NONE,
891 vinsertb, PPC_NONE, PPC2_ISA300);
892 GEN_VXFORM_DUAL(vspltish, PPC_ALTIVEC, PPC_NONE,
893 vinserth, PPC_NONE, PPC2_ISA300);
894 GEN_VXFORM_DUAL(vspltisw, PPC_ALTIVEC, PPC_NONE,
895 vinsertw, PPC_NONE, PPC2_ISA300);
896
897 static void gen_vsldoi(DisasContext *ctx)
898 {
899 TCGv_ptr ra, rb, rd;
900 TCGv_i32 sh;
901 if (unlikely(!ctx->altivec_enabled)) {
902 gen_exception(ctx, POWERPC_EXCP_VPU);
903 return;
904 }
905 ra = gen_avr_ptr(rA(ctx->opcode));
906 rb = gen_avr_ptr(rB(ctx->opcode));
907 rd = gen_avr_ptr(rD(ctx->opcode));
908 sh = tcg_const_i32(VSH(ctx->opcode));
909 gen_helper_vsldoi (rd, ra, rb, sh);
910 tcg_temp_free_ptr(ra);
911 tcg_temp_free_ptr(rb);
912 tcg_temp_free_ptr(rd);
913 tcg_temp_free_i32(sh);
914 }
915
916 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
917 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
918 { \
919 TCGv_ptr ra, rb, rc, rd; \
920 if (unlikely(!ctx->altivec_enabled)) { \
921 gen_exception(ctx, POWERPC_EXCP_VPU); \
922 return; \
923 } \
924 ra = gen_avr_ptr(rA(ctx->opcode)); \
925 rb = gen_avr_ptr(rB(ctx->opcode)); \
926 rc = gen_avr_ptr(rC(ctx->opcode)); \
927 rd = gen_avr_ptr(rD(ctx->opcode)); \
928 if (Rc(ctx->opcode)) { \
929 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
930 } else { \
931 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
932 } \
933 tcg_temp_free_ptr(ra); \
934 tcg_temp_free_ptr(rb); \
935 tcg_temp_free_ptr(rc); \
936 tcg_temp_free_ptr(rd); \
937 }
938
939 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
940
941 static void gen_vmladduhm(DisasContext *ctx)
942 {
943 TCGv_ptr ra, rb, rc, rd;
944 if (unlikely(!ctx->altivec_enabled)) {
945 gen_exception(ctx, POWERPC_EXCP_VPU);
946 return;
947 }
948 ra = gen_avr_ptr(rA(ctx->opcode));
949 rb = gen_avr_ptr(rB(ctx->opcode));
950 rc = gen_avr_ptr(rC(ctx->opcode));
951 rd = gen_avr_ptr(rD(ctx->opcode));
952 gen_helper_vmladduhm(rd, ra, rb, rc);
953 tcg_temp_free_ptr(ra);
954 tcg_temp_free_ptr(rb);
955 tcg_temp_free_ptr(rc);
956 tcg_temp_free_ptr(rd);
957 }
958
959 static void gen_vpermr(DisasContext *ctx)
960 {
961 TCGv_ptr ra, rb, rc, rd;
962 if (unlikely(!ctx->altivec_enabled)) {
963 gen_exception(ctx, POWERPC_EXCP_VPU);
964 return;
965 }
966 ra = gen_avr_ptr(rA(ctx->opcode));
967 rb = gen_avr_ptr(rB(ctx->opcode));
968 rc = gen_avr_ptr(rC(ctx->opcode));
969 rd = gen_avr_ptr(rD(ctx->opcode));
970 gen_helper_vpermr(cpu_env, rd, ra, rb, rc);
971 tcg_temp_free_ptr(ra);
972 tcg_temp_free_ptr(rb);
973 tcg_temp_free_ptr(rc);
974 tcg_temp_free_ptr(rd);
975 }
976
977 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
978 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
979 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
980 GEN_VAFORM_PAIRED(vsel, vperm, 21)
981 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
982
983 GEN_VXFORM_NOA(vclzb, 1, 28)
984 GEN_VXFORM_NOA(vclzh, 1, 29)
985 GEN_VXFORM_NOA(vclzw, 1, 30)
986 GEN_VXFORM_NOA(vclzd, 1, 31)
987 GEN_VXFORM_NOA_2(vnegw, 1, 24, 6)
988 GEN_VXFORM_NOA_2(vnegd, 1, 24, 7)
989 GEN_VXFORM_NOA_2(vextsb2w, 1, 24, 16)
990 GEN_VXFORM_NOA_2(vextsh2w, 1, 24, 17)
991 GEN_VXFORM_NOA_2(vextsb2d, 1, 24, 24)
992 GEN_VXFORM_NOA_2(vextsh2d, 1, 24, 25)
993 GEN_VXFORM_NOA_2(vextsw2d, 1, 24, 26)
994 GEN_VXFORM_NOA_2(vctzb, 1, 24, 28)
995 GEN_VXFORM_NOA_2(vctzh, 1, 24, 29)
996 GEN_VXFORM_NOA_2(vctzw, 1, 24, 30)
997 GEN_VXFORM_NOA_2(vctzd, 1, 24, 31)
998 GEN_VXFORM_NOA_3(vclzlsbb, 1, 24, 0)
999 GEN_VXFORM_NOA_3(vctzlsbb, 1, 24, 1)
1000 GEN_VXFORM_NOA(vpopcntb, 1, 28)
1001 GEN_VXFORM_NOA(vpopcnth, 1, 29)
1002 GEN_VXFORM_NOA(vpopcntw, 1, 30)
1003 GEN_VXFORM_NOA(vpopcntd, 1, 31)
1004 GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
1005 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
1006 GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
1007 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
1008 GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
1009 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
1010 GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
1011 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
1012 GEN_VXFORM(vbpermd, 6, 23);
1013 GEN_VXFORM(vbpermq, 6, 21);
1014 GEN_VXFORM_NOA(vgbbd, 6, 20);
1015 GEN_VXFORM(vpmsumb, 4, 16)
1016 GEN_VXFORM(vpmsumh, 4, 17)
1017 GEN_VXFORM(vpmsumw, 4, 18)
1018 GEN_VXFORM(vpmsumd, 4, 19)
1019
1020 #define GEN_BCD(op) \
1021 static void gen_##op(DisasContext *ctx) \
1022 { \
1023 TCGv_ptr ra, rb, rd; \
1024 TCGv_i32 ps; \
1025 \
1026 if (unlikely(!ctx->altivec_enabled)) { \
1027 gen_exception(ctx, POWERPC_EXCP_VPU); \
1028 return; \
1029 } \
1030 \
1031 ra = gen_avr_ptr(rA(ctx->opcode)); \
1032 rb = gen_avr_ptr(rB(ctx->opcode)); \
1033 rd = gen_avr_ptr(rD(ctx->opcode)); \
1034 \
1035 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
1036 \
1037 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
1038 \
1039 tcg_temp_free_ptr(ra); \
1040 tcg_temp_free_ptr(rb); \
1041 tcg_temp_free_ptr(rd); \
1042 tcg_temp_free_i32(ps); \
1043 }
1044
1045 #define GEN_BCD2(op) \
1046 static void gen_##op(DisasContext *ctx) \
1047 { \
1048 TCGv_ptr rd, rb; \
1049 TCGv_i32 ps; \
1050 \
1051 if (unlikely(!ctx->altivec_enabled)) { \
1052 gen_exception(ctx, POWERPC_EXCP_VPU); \
1053 return; \
1054 } \
1055 \
1056 rb = gen_avr_ptr(rB(ctx->opcode)); \
1057 rd = gen_avr_ptr(rD(ctx->opcode)); \
1058 \
1059 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
1060 \
1061 gen_helper_##op(cpu_crf[6], rd, rb, ps); \
1062 \
1063 tcg_temp_free_ptr(rb); \
1064 tcg_temp_free_ptr(rd); \
1065 tcg_temp_free_i32(ps); \
1066 }
1067
1068 GEN_BCD(bcdadd)
1069 GEN_BCD(bcdsub)
1070 GEN_BCD2(bcdcfn)
1071 GEN_BCD2(bcdctn)
1072 GEN_BCD2(bcdcfz)
1073 GEN_BCD2(bcdctz)
1074 GEN_BCD2(bcdcfsq)
1075 GEN_BCD2(bcdctsq)
1076 GEN_BCD2(bcdsetsgn)
1077 GEN_BCD(bcdcpsgn);
1078 GEN_BCD(bcds);
1079 GEN_BCD(bcdus);
1080 GEN_BCD(bcdsr);
1081 GEN_BCD(bcdtrunc);
1082 GEN_BCD(bcdutrunc);
1083
1084 static void gen_xpnd04_1(DisasContext *ctx)
1085 {
1086 switch (opc4(ctx->opcode)) {
1087 case 0:
1088 gen_bcdctsq(ctx);
1089 break;
1090 case 2:
1091 gen_bcdcfsq(ctx);
1092 break;
1093 case 4:
1094 gen_bcdctz(ctx);
1095 break;
1096 case 5:
1097 gen_bcdctn(ctx);
1098 break;
1099 case 6:
1100 gen_bcdcfz(ctx);
1101 break;
1102 case 7:
1103 gen_bcdcfn(ctx);
1104 break;
1105 case 31:
1106 gen_bcdsetsgn(ctx);
1107 break;
1108 default:
1109 gen_invalid(ctx);
1110 break;
1111 }
1112 }
1113
1114 static void gen_xpnd04_2(DisasContext *ctx)
1115 {
1116 switch (opc4(ctx->opcode)) {
1117 case 0:
1118 gen_bcdctsq(ctx);
1119 break;
1120 case 2:
1121 gen_bcdcfsq(ctx);
1122 break;
1123 case 4:
1124 gen_bcdctz(ctx);
1125 break;
1126 case 6:
1127 gen_bcdcfz(ctx);
1128 break;
1129 case 7:
1130 gen_bcdcfn(ctx);
1131 break;
1132 case 31:
1133 gen_bcdsetsgn(ctx);
1134 break;
1135 default:
1136 gen_invalid(ctx);
1137 break;
1138 }
1139 }
1140
1141
1142 GEN_VXFORM_DUAL(vsubcuw, PPC_ALTIVEC, PPC_NONE, \
1143 xpnd04_1, PPC_NONE, PPC2_ISA300)
1144 GEN_VXFORM_DUAL(vsubsws, PPC_ALTIVEC, PPC_NONE, \
1145 xpnd04_2, PPC_NONE, PPC2_ISA300)
1146
1147 GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
1148 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
1149 GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
1150 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
1151 GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
1152 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
1153 GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
1154 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
1155 GEN_VXFORM_DUAL(vaddshs, PPC_ALTIVEC, PPC_NONE, \
1156 bcdcpsgn, PPC_NONE, PPC2_ISA300)
1157 GEN_VXFORM_DUAL(vsubudm, PPC2_ALTIVEC_207, PPC_NONE, \
1158 bcds, PPC_NONE, PPC2_ISA300)
1159 GEN_VXFORM_DUAL(vsubuwm, PPC_ALTIVEC, PPC_NONE, \
1160 bcdus, PPC_NONE, PPC2_ISA300)
1161 GEN_VXFORM_DUAL(vsubsbs, PPC_ALTIVEC, PPC_NONE, \
1162 bcdtrunc, PPC_NONE, PPC2_ISA300)
1163 GEN_VXFORM_DUAL(vsubuqm, PPC2_ALTIVEC_207, PPC_NONE, \
1164 bcdtrunc, PPC_NONE, PPC2_ISA300)
1165 GEN_VXFORM_DUAL(vsubcuq, PPC2_ALTIVEC_207, PPC_NONE, \
1166 bcdutrunc, PPC_NONE, PPC2_ISA300)
1167
1168
1169 static void gen_vsbox(DisasContext *ctx)
1170 {
1171 TCGv_ptr ra, rd;
1172 if (unlikely(!ctx->altivec_enabled)) {
1173 gen_exception(ctx, POWERPC_EXCP_VPU);
1174 return;
1175 }
1176 ra = gen_avr_ptr(rA(ctx->opcode));
1177 rd = gen_avr_ptr(rD(ctx->opcode));
1178 gen_helper_vsbox(rd, ra);
1179 tcg_temp_free_ptr(ra);
1180 tcg_temp_free_ptr(rd);
1181 }
1182
1183 GEN_VXFORM(vcipher, 4, 20)
1184 GEN_VXFORM(vcipherlast, 4, 20)
1185 GEN_VXFORM(vncipher, 4, 21)
1186 GEN_VXFORM(vncipherlast, 4, 21)
1187
1188 GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
1189 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
1190 GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
1191 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
1192
1193 #define VSHASIGMA(op) \
1194 static void gen_##op(DisasContext *ctx) \
1195 { \
1196 TCGv_ptr ra, rd; \
1197 TCGv_i32 st_six; \
1198 if (unlikely(!ctx->altivec_enabled)) { \
1199 gen_exception(ctx, POWERPC_EXCP_VPU); \
1200 return; \
1201 } \
1202 ra = gen_avr_ptr(rA(ctx->opcode)); \
1203 rd = gen_avr_ptr(rD(ctx->opcode)); \
1204 st_six = tcg_const_i32(rB(ctx->opcode)); \
1205 gen_helper_##op(rd, ra, st_six); \
1206 tcg_temp_free_ptr(ra); \
1207 tcg_temp_free_ptr(rd); \
1208 tcg_temp_free_i32(st_six); \
1209 }
1210
1211 VSHASIGMA(vshasigmaw)
1212 VSHASIGMA(vshasigmad)
1213
1214 GEN_VXFORM3(vpermxor, 22, 0xFF)
1215 GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
1216 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
1217
1218 #undef GEN_VR_LDX
1219 #undef GEN_VR_STX
1220 #undef GEN_VR_LVE
1221 #undef GEN_VR_STVE
1222
1223 #undef GEN_VX_LOGICAL
1224 #undef GEN_VX_LOGICAL_207
1225 #undef GEN_VXFORM
1226 #undef GEN_VXFORM_207
1227 #undef GEN_VXFORM_DUAL
1228 #undef GEN_VXRFORM_DUAL
1229 #undef GEN_VXRFORM1
1230 #undef GEN_VXRFORM
1231 #undef GEN_VXFORM_DUPI
1232 #undef GEN_VXFORM_NOA
1233 #undef GEN_VXFORM_UIMM
1234 #undef GEN_VAFORM_PAIRED
1235
1236 #undef GEN_BCD2
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