2 * PowerPC emulation for qemu: main translation routines.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
24 #include "disas/disas.h"
25 #include "exec/exec-all.h"
27 #include "qemu/host-utils.h"
28 #include "exec/cpu_ldst.h"
30 #include "exec/helper-proto.h"
31 #include "exec/helper-gen.h"
33 #include "trace-tcg.h"
37 #define CPU_SINGLE_STEP 0x1
38 #define CPU_BRANCH_STEP 0x2
39 #define GDBSTUB_SINGLE_STEP 0x4
41 /* Include definitions for instructions classes and implementations flags */
42 //#define PPC_DEBUG_DISAS
43 //#define DO_PPC_STATISTICS
45 #ifdef PPC_DEBUG_DISAS
46 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
48 # define LOG_DISAS(...) do { } while (0)
50 /*****************************************************************************/
51 /* Code translation helpers */
53 /* global register indexes */
54 static TCGv_env cpu_env
;
55 static char cpu_reg_names
[10*3 + 22*4 /* GPR */
56 + 10*4 + 22*5 /* SPE GPRh */
57 + 10*4 + 22*5 /* FPR */
58 + 2*(10*6 + 22*7) /* AVRh, AVRl */
59 + 10*5 + 22*6 /* VSR */
61 static TCGv cpu_gpr
[32];
62 static TCGv cpu_gprh
[32];
63 static TCGv_i64 cpu_fpr
[32];
64 static TCGv_i64 cpu_avrh
[32], cpu_avrl
[32];
65 static TCGv_i64 cpu_vsr
[32];
66 static TCGv_i32 cpu_crf
[8];
71 #if defined(TARGET_PPC64)
74 static TCGv cpu_xer
, cpu_so
, cpu_ov
, cpu_ca
, cpu_ov32
, cpu_ca32
;
75 static TCGv cpu_reserve
;
76 static TCGv cpu_reserve_val
;
77 static TCGv cpu_fpscr
;
78 static TCGv_i32 cpu_access_type
;
80 #include "exec/gen-icount.h"
82 void ppc_translate_init(void)
86 size_t cpu_reg_names_size
;
87 static int done_init
= 0;
92 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
93 tcg_ctx
.tcg_env
= cpu_env
;
96 cpu_reg_names_size
= sizeof(cpu_reg_names
);
98 for (i
= 0; i
< 8; i
++) {
99 snprintf(p
, cpu_reg_names_size
, "crf%d", i
);
100 cpu_crf
[i
] = tcg_global_mem_new_i32(cpu_env
,
101 offsetof(CPUPPCState
, crf
[i
]), p
);
103 cpu_reg_names_size
-= 5;
106 for (i
= 0; i
< 32; i
++) {
107 snprintf(p
, cpu_reg_names_size
, "r%d", i
);
108 cpu_gpr
[i
] = tcg_global_mem_new(cpu_env
,
109 offsetof(CPUPPCState
, gpr
[i
]), p
);
110 p
+= (i
< 10) ? 3 : 4;
111 cpu_reg_names_size
-= (i
< 10) ? 3 : 4;
112 snprintf(p
, cpu_reg_names_size
, "r%dH", i
);
113 cpu_gprh
[i
] = tcg_global_mem_new(cpu_env
,
114 offsetof(CPUPPCState
, gprh
[i
]), p
);
115 p
+= (i
< 10) ? 4 : 5;
116 cpu_reg_names_size
-= (i
< 10) ? 4 : 5;
118 snprintf(p
, cpu_reg_names_size
, "fp%d", i
);
119 cpu_fpr
[i
] = tcg_global_mem_new_i64(cpu_env
,
120 offsetof(CPUPPCState
, fpr
[i
]), p
);
121 p
+= (i
< 10) ? 4 : 5;
122 cpu_reg_names_size
-= (i
< 10) ? 4 : 5;
124 snprintf(p
, cpu_reg_names_size
, "avr%dH", i
);
125 #ifdef HOST_WORDS_BIGENDIAN
126 cpu_avrh
[i
] = tcg_global_mem_new_i64(cpu_env
,
127 offsetof(CPUPPCState
, avr
[i
].u64
[0]), p
);
129 cpu_avrh
[i
] = tcg_global_mem_new_i64(cpu_env
,
130 offsetof(CPUPPCState
, avr
[i
].u64
[1]), p
);
132 p
+= (i
< 10) ? 6 : 7;
133 cpu_reg_names_size
-= (i
< 10) ? 6 : 7;
135 snprintf(p
, cpu_reg_names_size
, "avr%dL", i
);
136 #ifdef HOST_WORDS_BIGENDIAN
137 cpu_avrl
[i
] = tcg_global_mem_new_i64(cpu_env
,
138 offsetof(CPUPPCState
, avr
[i
].u64
[1]), p
);
140 cpu_avrl
[i
] = tcg_global_mem_new_i64(cpu_env
,
141 offsetof(CPUPPCState
, avr
[i
].u64
[0]), p
);
143 p
+= (i
< 10) ? 6 : 7;
144 cpu_reg_names_size
-= (i
< 10) ? 6 : 7;
145 snprintf(p
, cpu_reg_names_size
, "vsr%d", i
);
146 cpu_vsr
[i
] = tcg_global_mem_new_i64(cpu_env
,
147 offsetof(CPUPPCState
, vsr
[i
]), p
);
148 p
+= (i
< 10) ? 5 : 6;
149 cpu_reg_names_size
-= (i
< 10) ? 5 : 6;
152 cpu_nip
= tcg_global_mem_new(cpu_env
,
153 offsetof(CPUPPCState
, nip
), "nip");
155 cpu_msr
= tcg_global_mem_new(cpu_env
,
156 offsetof(CPUPPCState
, msr
), "msr");
158 cpu_ctr
= tcg_global_mem_new(cpu_env
,
159 offsetof(CPUPPCState
, ctr
), "ctr");
161 cpu_lr
= tcg_global_mem_new(cpu_env
,
162 offsetof(CPUPPCState
, lr
), "lr");
164 #if defined(TARGET_PPC64)
165 cpu_cfar
= tcg_global_mem_new(cpu_env
,
166 offsetof(CPUPPCState
, cfar
), "cfar");
169 cpu_xer
= tcg_global_mem_new(cpu_env
,
170 offsetof(CPUPPCState
, xer
), "xer");
171 cpu_so
= tcg_global_mem_new(cpu_env
,
172 offsetof(CPUPPCState
, so
), "SO");
173 cpu_ov
= tcg_global_mem_new(cpu_env
,
174 offsetof(CPUPPCState
, ov
), "OV");
175 cpu_ca
= tcg_global_mem_new(cpu_env
,
176 offsetof(CPUPPCState
, ca
), "CA");
177 cpu_ov32
= tcg_global_mem_new(cpu_env
,
178 offsetof(CPUPPCState
, ov32
), "OV32");
179 cpu_ca32
= tcg_global_mem_new(cpu_env
,
180 offsetof(CPUPPCState
, ca32
), "CA32");
182 cpu_reserve
= tcg_global_mem_new(cpu_env
,
183 offsetof(CPUPPCState
, reserve_addr
),
185 cpu_reserve_val
= tcg_global_mem_new(cpu_env
,
186 offsetof(CPUPPCState
, reserve_val
),
189 cpu_fpscr
= tcg_global_mem_new(cpu_env
,
190 offsetof(CPUPPCState
, fpscr
), "fpscr");
192 cpu_access_type
= tcg_global_mem_new_i32(cpu_env
,
193 offsetof(CPUPPCState
, access_type
), "access_type");
198 /* internal defines */
199 struct DisasContext
{
200 struct TranslationBlock
*tb
;
204 /* Routine used to access memory */
205 bool pr
, hv
, dr
, le_mode
;
207 bool need_access_type
;
210 /* Translation flags */
211 TCGMemOp default_tcg_memop_mask
;
212 #if defined(TARGET_PPC64)
217 bool altivec_enabled
;
222 ppc_spr_t
*spr_cb
; /* Needed to check rights for mfspr/mtspr */
223 int singlestep_enabled
;
224 uint64_t insns_flags
;
225 uint64_t insns_flags2
;
228 /* Return true iff byteswap is needed in a scalar memop */
229 static inline bool need_byteswap(const DisasContext
*ctx
)
231 #if defined(TARGET_WORDS_BIGENDIAN)
234 return !ctx
->le_mode
;
238 /* True when active word size < size of target_long. */
240 # define NARROW_MODE(C) (!(C)->sf_mode)
242 # define NARROW_MODE(C) 0
245 struct opc_handler_t
{
246 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
248 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
250 /* instruction type */
252 /* extended instruction type */
255 void (*handler
)(DisasContext
*ctx
);
256 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
259 #if defined(DO_PPC_STATISTICS)
264 static inline void gen_set_access_type(DisasContext
*ctx
, int access_type
)
266 if (ctx
->need_access_type
&& ctx
->access_type
!= access_type
) {
267 tcg_gen_movi_i32(cpu_access_type
, access_type
);
268 ctx
->access_type
= access_type
;
272 static inline void gen_update_nip(DisasContext
*ctx
, target_ulong nip
)
274 if (NARROW_MODE(ctx
)) {
277 tcg_gen_movi_tl(cpu_nip
, nip
);
280 static void gen_exception_err(DisasContext
*ctx
, uint32_t excp
, uint32_t error
)
284 /* These are all synchronous exceptions, we set the PC back to
285 * the faulting instruction
287 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
288 gen_update_nip(ctx
, ctx
->nip
- 4);
290 t0
= tcg_const_i32(excp
);
291 t1
= tcg_const_i32(error
);
292 gen_helper_raise_exception_err(cpu_env
, t0
, t1
);
293 tcg_temp_free_i32(t0
);
294 tcg_temp_free_i32(t1
);
295 ctx
->exception
= (excp
);
298 static void gen_exception(DisasContext
*ctx
, uint32_t excp
)
302 /* These are all synchronous exceptions, we set the PC back to
303 * the faulting instruction
305 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
306 gen_update_nip(ctx
, ctx
->nip
- 4);
308 t0
= tcg_const_i32(excp
);
309 gen_helper_raise_exception(cpu_env
, t0
);
310 tcg_temp_free_i32(t0
);
311 ctx
->exception
= (excp
);
314 static void gen_exception_nip(DisasContext
*ctx
, uint32_t excp
,
319 gen_update_nip(ctx
, nip
);
320 t0
= tcg_const_i32(excp
);
321 gen_helper_raise_exception(cpu_env
, t0
);
322 tcg_temp_free_i32(t0
);
323 ctx
->exception
= (excp
);
326 static void gen_debug_exception(DisasContext
*ctx
)
330 /* These are all synchronous exceptions, we set the PC back to
331 * the faulting instruction
333 if ((ctx
->exception
!= POWERPC_EXCP_BRANCH
) &&
334 (ctx
->exception
!= POWERPC_EXCP_SYNC
)) {
335 gen_update_nip(ctx
, ctx
->nip
);
337 t0
= tcg_const_i32(EXCP_DEBUG
);
338 gen_helper_raise_exception(cpu_env
, t0
);
339 tcg_temp_free_i32(t0
);
342 static inline void gen_inval_exception(DisasContext
*ctx
, uint32_t error
)
344 /* Will be converted to program check if needed */
345 gen_exception_err(ctx
, POWERPC_EXCP_HV_EMU
, POWERPC_EXCP_INVAL
| error
);
348 static inline void gen_priv_exception(DisasContext
*ctx
, uint32_t error
)
350 gen_exception_err(ctx
, POWERPC_EXCP_PROGRAM
, POWERPC_EXCP_PRIV
| error
);
353 static inline void gen_hvpriv_exception(DisasContext
*ctx
, uint32_t error
)
355 /* Will be converted to program check if needed */
356 gen_exception_err(ctx
, POWERPC_EXCP_HV_EMU
, POWERPC_EXCP_PRIV
| error
);
359 /* Stop translation */
360 static inline void gen_stop_exception(DisasContext
*ctx
)
362 gen_update_nip(ctx
, ctx
->nip
);
363 ctx
->exception
= POWERPC_EXCP_STOP
;
366 #ifndef CONFIG_USER_ONLY
367 /* No need to update nip here, as execution flow will change */
368 static inline void gen_sync_exception(DisasContext
*ctx
)
370 ctx
->exception
= POWERPC_EXCP_SYNC
;
374 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
375 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
377 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
378 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
380 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
381 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
383 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
384 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
386 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
387 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
389 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \
390 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2)
392 typedef struct opcode_t
{
393 unsigned char opc1
, opc2
, opc3
, opc4
;
394 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
395 unsigned char pad
[4];
397 opc_handler_t handler
;
401 /* Helpers for priv. check */
404 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
407 #if defined(CONFIG_USER_ONLY)
408 #define CHK_HV GEN_PRIV
409 #define CHK_SV GEN_PRIV
410 #define CHK_HVRM GEN_PRIV
414 if (unlikely(ctx->pr || !ctx->hv)) { \
420 if (unlikely(ctx->pr)) { \
426 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
434 /*****************************************************************************/
435 /* PowerPC instructions table */
437 #if defined(DO_PPC_STATISTICS)
438 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
448 .handler = &gen_##name, \
449 .oname = stringify(name), \
451 .oname = stringify(name), \
453 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
464 .handler = &gen_##name, \
465 .oname = stringify(name), \
467 .oname = stringify(name), \
469 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
479 .handler = &gen_##name, \
484 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
494 .handler = &gen_##name, \
495 .oname = stringify(name), \
497 .oname = stringify(name), \
499 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
509 .handler = &gen_##name, \
515 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
525 .handler = &gen_##name, \
527 .oname = stringify(name), \
529 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
540 .handler = &gen_##name, \
542 .oname = stringify(name), \
544 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
554 .handler = &gen_##name, \
558 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
568 .handler = &gen_##name, \
570 .oname = stringify(name), \
572 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
582 .handler = &gen_##name, \
588 /* SPR load/store helpers */
589 static inline void gen_load_spr(TCGv t
, int reg
)
591 tcg_gen_ld_tl(t
, cpu_env
, offsetof(CPUPPCState
, spr
[reg
]));
594 static inline void gen_store_spr(int reg
, TCGv t
)
596 tcg_gen_st_tl(t
, cpu_env
, offsetof(CPUPPCState
, spr
[reg
]));
599 /* Invalid instruction */
600 static void gen_invalid(DisasContext
*ctx
)
602 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
605 static opc_handler_t invalid_handler
= {
606 .inval1
= 0xFFFFFFFF,
607 .inval2
= 0xFFFFFFFF,
610 .handler
= gen_invalid
,
613 /*** Integer comparison ***/
615 static inline void gen_op_cmp(TCGv arg0
, TCGv arg1
, int s
, int crf
)
617 TCGv t0
= tcg_temp_new();
618 TCGv_i32 t1
= tcg_temp_new_i32();
620 tcg_gen_trunc_tl_i32(cpu_crf
[crf
], cpu_so
);
622 tcg_gen_setcond_tl((s
? TCG_COND_LT
: TCG_COND_LTU
), t0
, arg0
, arg1
);
623 tcg_gen_trunc_tl_i32(t1
, t0
);
624 tcg_gen_shli_i32(t1
, t1
, CRF_LT_BIT
);
625 tcg_gen_or_i32(cpu_crf
[crf
], cpu_crf
[crf
], t1
);
627 tcg_gen_setcond_tl((s
? TCG_COND_GT
: TCG_COND_GTU
), t0
, arg0
, arg1
);
628 tcg_gen_trunc_tl_i32(t1
, t0
);
629 tcg_gen_shli_i32(t1
, t1
, CRF_GT_BIT
);
630 tcg_gen_or_i32(cpu_crf
[crf
], cpu_crf
[crf
], t1
);
632 tcg_gen_setcond_tl(TCG_COND_EQ
, t0
, arg0
, arg1
);
633 tcg_gen_trunc_tl_i32(t1
, t0
);
634 tcg_gen_shli_i32(t1
, t1
, CRF_EQ_BIT
);
635 tcg_gen_or_i32(cpu_crf
[crf
], cpu_crf
[crf
], t1
);
638 tcg_temp_free_i32(t1
);
641 static inline void gen_op_cmpi(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
643 TCGv t0
= tcg_const_tl(arg1
);
644 gen_op_cmp(arg0
, t0
, s
, crf
);
648 static inline void gen_op_cmp32(TCGv arg0
, TCGv arg1
, int s
, int crf
)
654 tcg_gen_ext32s_tl(t0
, arg0
);
655 tcg_gen_ext32s_tl(t1
, arg1
);
657 tcg_gen_ext32u_tl(t0
, arg0
);
658 tcg_gen_ext32u_tl(t1
, arg1
);
660 gen_op_cmp(t0
, t1
, s
, crf
);
665 static inline void gen_op_cmpi32(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
667 TCGv t0
= tcg_const_tl(arg1
);
668 gen_op_cmp32(arg0
, t0
, s
, crf
);
672 static inline void gen_set_Rc0(DisasContext
*ctx
, TCGv reg
)
674 if (NARROW_MODE(ctx
)) {
675 gen_op_cmpi32(reg
, 0, 1, 0);
677 gen_op_cmpi(reg
, 0, 1, 0);
682 static void gen_cmp(DisasContext
*ctx
)
684 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
685 gen_op_cmp(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
686 1, crfD(ctx
->opcode
));
688 gen_op_cmp32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
689 1, crfD(ctx
->opcode
));
694 static void gen_cmpi(DisasContext
*ctx
)
696 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
697 gen_op_cmpi(cpu_gpr
[rA(ctx
->opcode
)], SIMM(ctx
->opcode
),
698 1, crfD(ctx
->opcode
));
700 gen_op_cmpi32(cpu_gpr
[rA(ctx
->opcode
)], SIMM(ctx
->opcode
),
701 1, crfD(ctx
->opcode
));
706 static void gen_cmpl(DisasContext
*ctx
)
708 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
709 gen_op_cmp(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
710 0, crfD(ctx
->opcode
));
712 gen_op_cmp32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
713 0, crfD(ctx
->opcode
));
718 static void gen_cmpli(DisasContext
*ctx
)
720 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
721 gen_op_cmpi(cpu_gpr
[rA(ctx
->opcode
)], UIMM(ctx
->opcode
),
722 0, crfD(ctx
->opcode
));
724 gen_op_cmpi32(cpu_gpr
[rA(ctx
->opcode
)], UIMM(ctx
->opcode
),
725 0, crfD(ctx
->opcode
));
729 /* cmprb - range comparison: isupper, isaplha, islower*/
730 static void gen_cmprb(DisasContext
*ctx
)
732 TCGv_i32 src1
= tcg_temp_new_i32();
733 TCGv_i32 src2
= tcg_temp_new_i32();
734 TCGv_i32 src2lo
= tcg_temp_new_i32();
735 TCGv_i32 src2hi
= tcg_temp_new_i32();
736 TCGv_i32 crf
= cpu_crf
[crfD(ctx
->opcode
)];
738 tcg_gen_trunc_tl_i32(src1
, cpu_gpr
[rA(ctx
->opcode
)]);
739 tcg_gen_trunc_tl_i32(src2
, cpu_gpr
[rB(ctx
->opcode
)]);
741 tcg_gen_andi_i32(src1
, src1
, 0xFF);
742 tcg_gen_ext8u_i32(src2lo
, src2
);
743 tcg_gen_shri_i32(src2
, src2
, 8);
744 tcg_gen_ext8u_i32(src2hi
, src2
);
746 tcg_gen_setcond_i32(TCG_COND_LEU
, src2lo
, src2lo
, src1
);
747 tcg_gen_setcond_i32(TCG_COND_LEU
, src2hi
, src1
, src2hi
);
748 tcg_gen_and_i32(crf
, src2lo
, src2hi
);
750 if (ctx
->opcode
& 0x00200000) {
751 tcg_gen_shri_i32(src2
, src2
, 8);
752 tcg_gen_ext8u_i32(src2lo
, src2
);
753 tcg_gen_shri_i32(src2
, src2
, 8);
754 tcg_gen_ext8u_i32(src2hi
, src2
);
755 tcg_gen_setcond_i32(TCG_COND_LEU
, src2lo
, src2lo
, src1
);
756 tcg_gen_setcond_i32(TCG_COND_LEU
, src2hi
, src1
, src2hi
);
757 tcg_gen_and_i32(src2lo
, src2lo
, src2hi
);
758 tcg_gen_or_i32(crf
, crf
, src2lo
);
760 tcg_gen_shli_i32(crf
, crf
, CRF_GT_BIT
);
761 tcg_temp_free_i32(src1
);
762 tcg_temp_free_i32(src2
);
763 tcg_temp_free_i32(src2lo
);
764 tcg_temp_free_i32(src2hi
);
767 #if defined(TARGET_PPC64)
769 static void gen_cmpeqb(DisasContext
*ctx
)
771 gen_helper_cmpeqb(cpu_crf
[crfD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
772 cpu_gpr
[rB(ctx
->opcode
)]);
776 /* isel (PowerPC 2.03 specification) */
777 static void gen_isel(DisasContext
*ctx
)
779 uint32_t bi
= rC(ctx
->opcode
);
780 uint32_t mask
= 0x08 >> (bi
& 0x03);
781 TCGv t0
= tcg_temp_new();
784 tcg_gen_extu_i32_tl(t0
, cpu_crf
[bi
>> 2]);
785 tcg_gen_andi_tl(t0
, t0
, mask
);
787 zr
= tcg_const_tl(0);
788 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_gpr
[rD(ctx
->opcode
)], t0
, zr
,
789 rA(ctx
->opcode
) ? cpu_gpr
[rA(ctx
->opcode
)] : zr
,
790 cpu_gpr
[rB(ctx
->opcode
)]);
795 /* cmpb: PowerPC 2.05 specification */
796 static void gen_cmpb(DisasContext
*ctx
)
798 gen_helper_cmpb(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)],
799 cpu_gpr
[rB(ctx
->opcode
)]);
802 /*** Integer arithmetic ***/
804 static inline void gen_op_arith_compute_ov(DisasContext
*ctx
, TCGv arg0
,
805 TCGv arg1
, TCGv arg2
, int sub
)
807 TCGv t0
= tcg_temp_new();
809 tcg_gen_xor_tl(cpu_ov
, arg0
, arg2
);
810 tcg_gen_xor_tl(t0
, arg1
, arg2
);
812 tcg_gen_and_tl(cpu_ov
, cpu_ov
, t0
);
814 tcg_gen_andc_tl(cpu_ov
, cpu_ov
, t0
);
817 if (NARROW_MODE(ctx
)) {
818 tcg_gen_extract_tl(cpu_ov
, cpu_ov
, 31, 1);
819 if (is_isa300(ctx
)) {
820 tcg_gen_mov_tl(cpu_ov32
, cpu_ov
);
823 if (is_isa300(ctx
)) {
824 tcg_gen_extract_tl(cpu_ov32
, cpu_ov
, 31, 1);
826 tcg_gen_extract_tl(cpu_ov
, cpu_ov
, TARGET_LONG_BITS
- 1, 1);
828 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
831 static inline void gen_op_arith_compute_ca32(DisasContext
*ctx
,
832 TCGv res
, TCGv arg0
, TCGv arg1
,
837 if (!is_isa300(ctx
)) {
843 tcg_gen_eqv_tl(t0
, arg0
, arg1
);
845 tcg_gen_xor_tl(t0
, arg0
, arg1
);
847 tcg_gen_xor_tl(t0
, t0
, res
);
848 tcg_gen_extract_tl(cpu_ca32
, t0
, 32, 1);
852 /* Common add function */
853 static inline void gen_op_arith_add(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
854 TCGv arg2
, bool add_ca
, bool compute_ca
,
855 bool compute_ov
, bool compute_rc0
)
859 if (compute_ca
|| compute_ov
) {
864 if (NARROW_MODE(ctx
)) {
865 /* Caution: a non-obvious corner case of the spec is that we
866 must produce the *entire* 64-bit addition, but produce the
867 carry into bit 32. */
868 TCGv t1
= tcg_temp_new();
869 tcg_gen_xor_tl(t1
, arg1
, arg2
); /* add without carry */
870 tcg_gen_add_tl(t0
, arg1
, arg2
);
872 tcg_gen_add_tl(t0
, t0
, cpu_ca
);
874 tcg_gen_xor_tl(cpu_ca
, t0
, t1
); /* bits changed w/ carry */
876 tcg_gen_extract_tl(cpu_ca
, cpu_ca
, 32, 1);
877 if (is_isa300(ctx
)) {
878 tcg_gen_mov_tl(cpu_ca32
, cpu_ca
);
881 TCGv zero
= tcg_const_tl(0);
883 tcg_gen_add2_tl(t0
, cpu_ca
, arg1
, zero
, cpu_ca
, zero
);
884 tcg_gen_add2_tl(t0
, cpu_ca
, t0
, cpu_ca
, arg2
, zero
);
886 tcg_gen_add2_tl(t0
, cpu_ca
, arg1
, zero
, arg2
, zero
);
888 gen_op_arith_compute_ca32(ctx
, t0
, arg1
, arg2
, 0);
892 tcg_gen_add_tl(t0
, arg1
, arg2
);
894 tcg_gen_add_tl(t0
, t0
, cpu_ca
);
899 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 0);
901 if (unlikely(compute_rc0
)) {
902 gen_set_Rc0(ctx
, t0
);
905 if (!TCGV_EQUAL(t0
, ret
)) {
906 tcg_gen_mov_tl(ret
, t0
);
910 /* Add functions with two operands */
911 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
912 static void glue(gen_, name)(DisasContext *ctx) \
914 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
915 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
916 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
918 /* Add functions with one operand and one immediate */
919 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
920 add_ca, compute_ca, compute_ov) \
921 static void glue(gen_, name)(DisasContext *ctx) \
923 TCGv t0 = tcg_const_tl(const_val); \
924 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
925 cpu_gpr[rA(ctx->opcode)], t0, \
926 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
930 /* add add. addo addo. */
931 GEN_INT_ARITH_ADD(add
, 0x08, 0, 0, 0)
932 GEN_INT_ARITH_ADD(addo
, 0x18, 0, 0, 1)
933 /* addc addc. addco addco. */
934 GEN_INT_ARITH_ADD(addc
, 0x00, 0, 1, 0)
935 GEN_INT_ARITH_ADD(addco
, 0x10, 0, 1, 1)
936 /* adde adde. addeo addeo. */
937 GEN_INT_ARITH_ADD(adde
, 0x04, 1, 1, 0)
938 GEN_INT_ARITH_ADD(addeo
, 0x14, 1, 1, 1)
939 /* addme addme. addmeo addmeo. */
940 GEN_INT_ARITH_ADD_CONST(addme
, 0x07, -1LL, 1, 1, 0)
941 GEN_INT_ARITH_ADD_CONST(addmeo
, 0x17, -1LL, 1, 1, 1)
942 /* addze addze. addzeo addzeo.*/
943 GEN_INT_ARITH_ADD_CONST(addze
, 0x06, 0, 1, 1, 0)
944 GEN_INT_ARITH_ADD_CONST(addzeo
, 0x16, 0, 1, 1, 1)
946 static void gen_addi(DisasContext
*ctx
)
948 target_long simm
= SIMM(ctx
->opcode
);
950 if (rA(ctx
->opcode
) == 0) {
952 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
);
954 tcg_gen_addi_tl(cpu_gpr
[rD(ctx
->opcode
)],
955 cpu_gpr
[rA(ctx
->opcode
)], simm
);
959 static inline void gen_op_addic(DisasContext
*ctx
, bool compute_rc0
)
961 TCGv c
= tcg_const_tl(SIMM(ctx
->opcode
));
962 gen_op_arith_add(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
963 c
, 0, 1, 0, compute_rc0
);
967 static void gen_addic(DisasContext
*ctx
)
969 gen_op_addic(ctx
, 0);
972 static void gen_addic_(DisasContext
*ctx
)
974 gen_op_addic(ctx
, 1);
978 static void gen_addis(DisasContext
*ctx
)
980 target_long simm
= SIMM(ctx
->opcode
);
982 if (rA(ctx
->opcode
) == 0) {
984 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
<< 16);
986 tcg_gen_addi_tl(cpu_gpr
[rD(ctx
->opcode
)],
987 cpu_gpr
[rA(ctx
->opcode
)], simm
<< 16);
992 static void gen_addpcis(DisasContext
*ctx
)
994 target_long d
= DX(ctx
->opcode
);
996 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], ctx
->nip
+ (d
<< 16));
999 static inline void gen_op_arith_divw(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1000 TCGv arg2
, int sign
, int compute_ov
)
1002 TCGv_i32 t0
= tcg_temp_new_i32();
1003 TCGv_i32 t1
= tcg_temp_new_i32();
1004 TCGv_i32 t2
= tcg_temp_new_i32();
1005 TCGv_i32 t3
= tcg_temp_new_i32();
1007 tcg_gen_trunc_tl_i32(t0
, arg1
);
1008 tcg_gen_trunc_tl_i32(t1
, arg2
);
1010 tcg_gen_setcondi_i32(TCG_COND_EQ
, t2
, t0
, INT_MIN
);
1011 tcg_gen_setcondi_i32(TCG_COND_EQ
, t3
, t1
, -1);
1012 tcg_gen_and_i32(t2
, t2
, t3
);
1013 tcg_gen_setcondi_i32(TCG_COND_EQ
, t3
, t1
, 0);
1014 tcg_gen_or_i32(t2
, t2
, t3
);
1015 tcg_gen_movi_i32(t3
, 0);
1016 tcg_gen_movcond_i32(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1017 tcg_gen_div_i32(t3
, t0
, t1
);
1018 tcg_gen_extu_i32_tl(ret
, t3
);
1020 tcg_gen_setcondi_i32(TCG_COND_EQ
, t2
, t1
, 0);
1021 tcg_gen_movi_i32(t3
, 0);
1022 tcg_gen_movcond_i32(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1023 tcg_gen_divu_i32(t3
, t0
, t1
);
1024 tcg_gen_extu_i32_tl(ret
, t3
);
1027 tcg_gen_extu_i32_tl(cpu_ov
, t2
);
1028 if (is_isa300(ctx
)) {
1029 tcg_gen_extu_i32_tl(cpu_ov32
, t2
);
1031 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1033 tcg_temp_free_i32(t0
);
1034 tcg_temp_free_i32(t1
);
1035 tcg_temp_free_i32(t2
);
1036 tcg_temp_free_i32(t3
);
1038 if (unlikely(Rc(ctx
->opcode
) != 0))
1039 gen_set_Rc0(ctx
, ret
);
1042 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1043 static void glue(gen_, name)(DisasContext *ctx) \
1045 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1046 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1047 sign, compute_ov); \
1049 /* divwu divwu. divwuo divwuo. */
1050 GEN_INT_ARITH_DIVW(divwu
, 0x0E, 0, 0);
1051 GEN_INT_ARITH_DIVW(divwuo
, 0x1E, 0, 1);
1052 /* divw divw. divwo divwo. */
1053 GEN_INT_ARITH_DIVW(divw
, 0x0F, 1, 0);
1054 GEN_INT_ARITH_DIVW(divwo
, 0x1F, 1, 1);
1056 /* div[wd]eu[o][.] */
1057 #define GEN_DIVE(name, hlpr, compute_ov) \
1058 static void gen_##name(DisasContext *ctx) \
1060 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1061 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1062 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1063 tcg_temp_free_i32(t0); \
1064 if (unlikely(Rc(ctx->opcode) != 0)) { \
1065 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1069 GEN_DIVE(divweu
, divweu
, 0);
1070 GEN_DIVE(divweuo
, divweu
, 1);
1071 GEN_DIVE(divwe
, divwe
, 0);
1072 GEN_DIVE(divweo
, divwe
, 1);
1074 #if defined(TARGET_PPC64)
1075 static inline void gen_op_arith_divd(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1076 TCGv arg2
, int sign
, int compute_ov
)
1078 TCGv_i64 t0
= tcg_temp_new_i64();
1079 TCGv_i64 t1
= tcg_temp_new_i64();
1080 TCGv_i64 t2
= tcg_temp_new_i64();
1081 TCGv_i64 t3
= tcg_temp_new_i64();
1083 tcg_gen_mov_i64(t0
, arg1
);
1084 tcg_gen_mov_i64(t1
, arg2
);
1086 tcg_gen_setcondi_i64(TCG_COND_EQ
, t2
, t0
, INT64_MIN
);
1087 tcg_gen_setcondi_i64(TCG_COND_EQ
, t3
, t1
, -1);
1088 tcg_gen_and_i64(t2
, t2
, t3
);
1089 tcg_gen_setcondi_i64(TCG_COND_EQ
, t3
, t1
, 0);
1090 tcg_gen_or_i64(t2
, t2
, t3
);
1091 tcg_gen_movi_i64(t3
, 0);
1092 tcg_gen_movcond_i64(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1093 tcg_gen_div_i64(ret
, t0
, t1
);
1095 tcg_gen_setcondi_i64(TCG_COND_EQ
, t2
, t1
, 0);
1096 tcg_gen_movi_i64(t3
, 0);
1097 tcg_gen_movcond_i64(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1098 tcg_gen_divu_i64(ret
, t0
, t1
);
1101 tcg_gen_mov_tl(cpu_ov
, t2
);
1102 if (is_isa300(ctx
)) {
1103 tcg_gen_mov_tl(cpu_ov32
, t2
);
1105 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1107 tcg_temp_free_i64(t0
);
1108 tcg_temp_free_i64(t1
);
1109 tcg_temp_free_i64(t2
);
1110 tcg_temp_free_i64(t3
);
1112 if (unlikely(Rc(ctx
->opcode
) != 0))
1113 gen_set_Rc0(ctx
, ret
);
1116 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1117 static void glue(gen_, name)(DisasContext *ctx) \
1119 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1120 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1121 sign, compute_ov); \
1123 /* divdu divdu. divduo divduo. */
1124 GEN_INT_ARITH_DIVD(divdu
, 0x0E, 0, 0);
1125 GEN_INT_ARITH_DIVD(divduo
, 0x1E, 0, 1);
1126 /* divd divd. divdo divdo. */
1127 GEN_INT_ARITH_DIVD(divd
, 0x0F, 1, 0);
1128 GEN_INT_ARITH_DIVD(divdo
, 0x1F, 1, 1);
1130 GEN_DIVE(divdeu
, divdeu
, 0);
1131 GEN_DIVE(divdeuo
, divdeu
, 1);
1132 GEN_DIVE(divde
, divde
, 0);
1133 GEN_DIVE(divdeo
, divde
, 1);
1136 static inline void gen_op_arith_modw(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1137 TCGv arg2
, int sign
)
1139 TCGv_i32 t0
= tcg_temp_new_i32();
1140 TCGv_i32 t1
= tcg_temp_new_i32();
1142 tcg_gen_trunc_tl_i32(t0
, arg1
);
1143 tcg_gen_trunc_tl_i32(t1
, arg2
);
1145 TCGv_i32 t2
= tcg_temp_new_i32();
1146 TCGv_i32 t3
= tcg_temp_new_i32();
1147 tcg_gen_setcondi_i32(TCG_COND_EQ
, t2
, t0
, INT_MIN
);
1148 tcg_gen_setcondi_i32(TCG_COND_EQ
, t3
, t1
, -1);
1149 tcg_gen_and_i32(t2
, t2
, t3
);
1150 tcg_gen_setcondi_i32(TCG_COND_EQ
, t3
, t1
, 0);
1151 tcg_gen_or_i32(t2
, t2
, t3
);
1152 tcg_gen_movi_i32(t3
, 0);
1153 tcg_gen_movcond_i32(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1154 tcg_gen_rem_i32(t3
, t0
, t1
);
1155 tcg_gen_ext_i32_tl(ret
, t3
);
1156 tcg_temp_free_i32(t2
);
1157 tcg_temp_free_i32(t3
);
1159 TCGv_i32 t2
= tcg_const_i32(1);
1160 TCGv_i32 t3
= tcg_const_i32(0);
1161 tcg_gen_movcond_i32(TCG_COND_EQ
, t1
, t1
, t3
, t2
, t1
);
1162 tcg_gen_remu_i32(t3
, t0
, t1
);
1163 tcg_gen_extu_i32_tl(ret
, t3
);
1164 tcg_temp_free_i32(t2
);
1165 tcg_temp_free_i32(t3
);
1167 tcg_temp_free_i32(t0
);
1168 tcg_temp_free_i32(t1
);
1171 #define GEN_INT_ARITH_MODW(name, opc3, sign) \
1172 static void glue(gen_, name)(DisasContext *ctx) \
1174 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
1175 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1179 GEN_INT_ARITH_MODW(moduw
, 0x08, 0);
1180 GEN_INT_ARITH_MODW(modsw
, 0x18, 1);
1182 #if defined(TARGET_PPC64)
1183 static inline void gen_op_arith_modd(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1184 TCGv arg2
, int sign
)
1186 TCGv_i64 t0
= tcg_temp_new_i64();
1187 TCGv_i64 t1
= tcg_temp_new_i64();
1189 tcg_gen_mov_i64(t0
, arg1
);
1190 tcg_gen_mov_i64(t1
, arg2
);
1192 TCGv_i64 t2
= tcg_temp_new_i64();
1193 TCGv_i64 t3
= tcg_temp_new_i64();
1194 tcg_gen_setcondi_i64(TCG_COND_EQ
, t2
, t0
, INT64_MIN
);
1195 tcg_gen_setcondi_i64(TCG_COND_EQ
, t3
, t1
, -1);
1196 tcg_gen_and_i64(t2
, t2
, t3
);
1197 tcg_gen_setcondi_i64(TCG_COND_EQ
, t3
, t1
, 0);
1198 tcg_gen_or_i64(t2
, t2
, t3
);
1199 tcg_gen_movi_i64(t3
, 0);
1200 tcg_gen_movcond_i64(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1201 tcg_gen_rem_i64(ret
, t0
, t1
);
1202 tcg_temp_free_i64(t2
);
1203 tcg_temp_free_i64(t3
);
1205 TCGv_i64 t2
= tcg_const_i64(1);
1206 TCGv_i64 t3
= tcg_const_i64(0);
1207 tcg_gen_movcond_i64(TCG_COND_EQ
, t1
, t1
, t3
, t2
, t1
);
1208 tcg_gen_remu_i64(ret
, t0
, t1
);
1209 tcg_temp_free_i64(t2
);
1210 tcg_temp_free_i64(t3
);
1212 tcg_temp_free_i64(t0
);
1213 tcg_temp_free_i64(t1
);
1216 #define GEN_INT_ARITH_MODD(name, opc3, sign) \
1217 static void glue(gen_, name)(DisasContext *ctx) \
1219 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
1220 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1224 GEN_INT_ARITH_MODD(modud
, 0x08, 0);
1225 GEN_INT_ARITH_MODD(modsd
, 0x18, 1);
1229 static void gen_mulhw(DisasContext
*ctx
)
1231 TCGv_i32 t0
= tcg_temp_new_i32();
1232 TCGv_i32 t1
= tcg_temp_new_i32();
1234 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1235 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1236 tcg_gen_muls2_i32(t0
, t1
, t0
, t1
);
1237 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
1238 tcg_temp_free_i32(t0
);
1239 tcg_temp_free_i32(t1
);
1240 if (unlikely(Rc(ctx
->opcode
) != 0))
1241 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1244 /* mulhwu mulhwu. */
1245 static void gen_mulhwu(DisasContext
*ctx
)
1247 TCGv_i32 t0
= tcg_temp_new_i32();
1248 TCGv_i32 t1
= tcg_temp_new_i32();
1250 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1251 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1252 tcg_gen_mulu2_i32(t0
, t1
, t0
, t1
);
1253 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
1254 tcg_temp_free_i32(t0
);
1255 tcg_temp_free_i32(t1
);
1256 if (unlikely(Rc(ctx
->opcode
) != 0))
1257 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1261 static void gen_mullw(DisasContext
*ctx
)
1263 #if defined(TARGET_PPC64)
1265 t0
= tcg_temp_new_i64();
1266 t1
= tcg_temp_new_i64();
1267 tcg_gen_ext32s_tl(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1268 tcg_gen_ext32s_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1269 tcg_gen_mul_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
1273 tcg_gen_mul_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1274 cpu_gpr
[rB(ctx
->opcode
)]);
1276 if (unlikely(Rc(ctx
->opcode
) != 0))
1277 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1280 /* mullwo mullwo. */
1281 static void gen_mullwo(DisasContext
*ctx
)
1283 TCGv_i32 t0
= tcg_temp_new_i32();
1284 TCGv_i32 t1
= tcg_temp_new_i32();
1286 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1287 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1288 tcg_gen_muls2_i32(t0
, t1
, t0
, t1
);
1289 #if defined(TARGET_PPC64)
1290 tcg_gen_concat_i32_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
1292 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1295 tcg_gen_sari_i32(t0
, t0
, 31);
1296 tcg_gen_setcond_i32(TCG_COND_NE
, t0
, t0
, t1
);
1297 tcg_gen_extu_i32_tl(cpu_ov
, t0
);
1298 if (is_isa300(ctx
)) {
1299 tcg_gen_mov_tl(cpu_ov32
, cpu_ov
);
1301 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1303 tcg_temp_free_i32(t0
);
1304 tcg_temp_free_i32(t1
);
1305 if (unlikely(Rc(ctx
->opcode
) != 0))
1306 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1310 static void gen_mulli(DisasContext
*ctx
)
1312 tcg_gen_muli_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1316 #if defined(TARGET_PPC64)
1318 static void gen_mulhd(DisasContext
*ctx
)
1320 TCGv lo
= tcg_temp_new();
1321 tcg_gen_muls2_tl(lo
, cpu_gpr
[rD(ctx
->opcode
)],
1322 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1324 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1325 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1329 /* mulhdu mulhdu. */
1330 static void gen_mulhdu(DisasContext
*ctx
)
1332 TCGv lo
= tcg_temp_new();
1333 tcg_gen_mulu2_tl(lo
, cpu_gpr
[rD(ctx
->opcode
)],
1334 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1336 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1337 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1342 static void gen_mulld(DisasContext
*ctx
)
1344 tcg_gen_mul_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1345 cpu_gpr
[rB(ctx
->opcode
)]);
1346 if (unlikely(Rc(ctx
->opcode
) != 0))
1347 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1350 /* mulldo mulldo. */
1351 static void gen_mulldo(DisasContext
*ctx
)
1353 TCGv_i64 t0
= tcg_temp_new_i64();
1354 TCGv_i64 t1
= tcg_temp_new_i64();
1356 tcg_gen_muls2_i64(t0
, t1
, cpu_gpr
[rA(ctx
->opcode
)],
1357 cpu_gpr
[rB(ctx
->opcode
)]);
1358 tcg_gen_mov_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1360 tcg_gen_sari_i64(t0
, t0
, 63);
1361 tcg_gen_setcond_i64(TCG_COND_NE
, cpu_ov
, t0
, t1
);
1362 if (is_isa300(ctx
)) {
1363 tcg_gen_mov_tl(cpu_ov32
, cpu_ov
);
1365 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1367 tcg_temp_free_i64(t0
);
1368 tcg_temp_free_i64(t1
);
1370 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1371 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1376 /* Common subf function */
1377 static inline void gen_op_arith_subf(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1378 TCGv arg2
, bool add_ca
, bool compute_ca
,
1379 bool compute_ov
, bool compute_rc0
)
1383 if (compute_ca
|| compute_ov
) {
1384 t0
= tcg_temp_new();
1388 /* dest = ~arg1 + arg2 [+ ca]. */
1389 if (NARROW_MODE(ctx
)) {
1390 /* Caution: a non-obvious corner case of the spec is that we
1391 must produce the *entire* 64-bit addition, but produce the
1392 carry into bit 32. */
1393 TCGv inv1
= tcg_temp_new();
1394 TCGv t1
= tcg_temp_new();
1395 tcg_gen_not_tl(inv1
, arg1
);
1397 tcg_gen_add_tl(t0
, arg2
, cpu_ca
);
1399 tcg_gen_addi_tl(t0
, arg2
, 1);
1401 tcg_gen_xor_tl(t1
, arg2
, inv1
); /* add without carry */
1402 tcg_gen_add_tl(t0
, t0
, inv1
);
1403 tcg_temp_free(inv1
);
1404 tcg_gen_xor_tl(cpu_ca
, t0
, t1
); /* bits changes w/ carry */
1406 tcg_gen_extract_tl(cpu_ca
, cpu_ca
, 32, 1);
1407 if (is_isa300(ctx
)) {
1408 tcg_gen_mov_tl(cpu_ca32
, cpu_ca
);
1410 } else if (add_ca
) {
1411 TCGv zero
, inv1
= tcg_temp_new();
1412 tcg_gen_not_tl(inv1
, arg1
);
1413 zero
= tcg_const_tl(0);
1414 tcg_gen_add2_tl(t0
, cpu_ca
, arg2
, zero
, cpu_ca
, zero
);
1415 tcg_gen_add2_tl(t0
, cpu_ca
, t0
, cpu_ca
, inv1
, zero
);
1416 gen_op_arith_compute_ca32(ctx
, t0
, inv1
, arg2
, 0);
1417 tcg_temp_free(zero
);
1418 tcg_temp_free(inv1
);
1420 tcg_gen_setcond_tl(TCG_COND_GEU
, cpu_ca
, arg2
, arg1
);
1421 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1422 gen_op_arith_compute_ca32(ctx
, t0
, arg1
, arg2
, 1);
1424 } else if (add_ca
) {
1425 /* Since we're ignoring carry-out, we can simplify the
1426 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1427 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1428 tcg_gen_add_tl(t0
, t0
, cpu_ca
);
1429 tcg_gen_subi_tl(t0
, t0
, 1);
1431 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1435 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 1);
1437 if (unlikely(compute_rc0
)) {
1438 gen_set_Rc0(ctx
, t0
);
1441 if (!TCGV_EQUAL(t0
, ret
)) {
1442 tcg_gen_mov_tl(ret
, t0
);
1446 /* Sub functions with Two operands functions */
1447 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1448 static void glue(gen_, name)(DisasContext *ctx) \
1450 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1451 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1452 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1454 /* Sub functions with one operand and one immediate */
1455 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1456 add_ca, compute_ca, compute_ov) \
1457 static void glue(gen_, name)(DisasContext *ctx) \
1459 TCGv t0 = tcg_const_tl(const_val); \
1460 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1461 cpu_gpr[rA(ctx->opcode)], t0, \
1462 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1463 tcg_temp_free(t0); \
1465 /* subf subf. subfo subfo. */
1466 GEN_INT_ARITH_SUBF(subf
, 0x01, 0, 0, 0)
1467 GEN_INT_ARITH_SUBF(subfo
, 0x11, 0, 0, 1)
1468 /* subfc subfc. subfco subfco. */
1469 GEN_INT_ARITH_SUBF(subfc
, 0x00, 0, 1, 0)
1470 GEN_INT_ARITH_SUBF(subfco
, 0x10, 0, 1, 1)
1471 /* subfe subfe. subfeo subfo. */
1472 GEN_INT_ARITH_SUBF(subfe
, 0x04, 1, 1, 0)
1473 GEN_INT_ARITH_SUBF(subfeo
, 0x14, 1, 1, 1)
1474 /* subfme subfme. subfmeo subfmeo. */
1475 GEN_INT_ARITH_SUBF_CONST(subfme
, 0x07, -1LL, 1, 1, 0)
1476 GEN_INT_ARITH_SUBF_CONST(subfmeo
, 0x17, -1LL, 1, 1, 1)
1477 /* subfze subfze. subfzeo subfzeo.*/
1478 GEN_INT_ARITH_SUBF_CONST(subfze
, 0x06, 0, 1, 1, 0)
1479 GEN_INT_ARITH_SUBF_CONST(subfzeo
, 0x16, 0, 1, 1, 1)
1482 static void gen_subfic(DisasContext
*ctx
)
1484 TCGv c
= tcg_const_tl(SIMM(ctx
->opcode
));
1485 gen_op_arith_subf(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1490 /* neg neg. nego nego. */
1491 static inline void gen_op_arith_neg(DisasContext
*ctx
, bool compute_ov
)
1493 TCGv zero
= tcg_const_tl(0);
1494 gen_op_arith_subf(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1495 zero
, 0, 0, compute_ov
, Rc(ctx
->opcode
));
1496 tcg_temp_free(zero
);
1499 static void gen_neg(DisasContext
*ctx
)
1501 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
1502 if (unlikely(Rc(ctx
->opcode
))) {
1503 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1507 static void gen_nego(DisasContext
*ctx
)
1509 gen_op_arith_neg(ctx
, 1);
1512 /*** Integer logical ***/
1513 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1514 static void glue(gen_, name)(DisasContext *ctx) \
1516 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1517 cpu_gpr[rB(ctx->opcode)]); \
1518 if (unlikely(Rc(ctx->opcode) != 0)) \
1519 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1522 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1523 static void glue(gen_, name)(DisasContext *ctx) \
1525 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1526 if (unlikely(Rc(ctx->opcode) != 0)) \
1527 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1531 GEN_LOGICAL2(and, tcg_gen_and_tl
, 0x00, PPC_INTEGER
);
1533 GEN_LOGICAL2(andc
, tcg_gen_andc_tl
, 0x01, PPC_INTEGER
);
1536 static void gen_andi_(DisasContext
*ctx
)
1538 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], UIMM(ctx
->opcode
));
1539 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1543 static void gen_andis_(DisasContext
*ctx
)
1545 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], UIMM(ctx
->opcode
) << 16);
1546 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1550 static void gen_cntlzw(DisasContext
*ctx
)
1552 TCGv_i32 t
= tcg_temp_new_i32();
1554 tcg_gen_trunc_tl_i32(t
, cpu_gpr
[rS(ctx
->opcode
)]);
1555 tcg_gen_clzi_i32(t
, t
, 32);
1556 tcg_gen_extu_i32_tl(cpu_gpr
[rA(ctx
->opcode
)], t
);
1557 tcg_temp_free_i32(t
);
1559 if (unlikely(Rc(ctx
->opcode
) != 0))
1560 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1564 static void gen_cnttzw(DisasContext
*ctx
)
1566 TCGv_i32 t
= tcg_temp_new_i32();
1568 tcg_gen_trunc_tl_i32(t
, cpu_gpr
[rS(ctx
->opcode
)]);
1569 tcg_gen_ctzi_i32(t
, t
, 32);
1570 tcg_gen_extu_i32_tl(cpu_gpr
[rA(ctx
->opcode
)], t
);
1571 tcg_temp_free_i32(t
);
1573 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1574 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1579 GEN_LOGICAL2(eqv
, tcg_gen_eqv_tl
, 0x08, PPC_INTEGER
);
1580 /* extsb & extsb. */
1581 GEN_LOGICAL1(extsb
, tcg_gen_ext8s_tl
, 0x1D, PPC_INTEGER
);
1582 /* extsh & extsh. */
1583 GEN_LOGICAL1(extsh
, tcg_gen_ext16s_tl
, 0x1C, PPC_INTEGER
);
1585 GEN_LOGICAL2(nand
, tcg_gen_nand_tl
, 0x0E, PPC_INTEGER
);
1587 GEN_LOGICAL2(nor
, tcg_gen_nor_tl
, 0x03, PPC_INTEGER
);
1589 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1590 static void gen_pause(DisasContext
*ctx
)
1592 TCGv_i32 t0
= tcg_const_i32(0);
1593 tcg_gen_st_i32(t0
, cpu_env
,
1594 -offsetof(PowerPCCPU
, env
) + offsetof(CPUState
, halted
));
1595 tcg_temp_free_i32(t0
);
1597 /* Stop translation, this gives other CPUs a chance to run */
1598 gen_exception_nip(ctx
, EXCP_HLT
, ctx
->nip
);
1600 #endif /* defined(TARGET_PPC64) */
1603 static void gen_or(DisasContext
*ctx
)
1607 rs
= rS(ctx
->opcode
);
1608 ra
= rA(ctx
->opcode
);
1609 rb
= rB(ctx
->opcode
);
1610 /* Optimisation for mr. ri case */
1611 if (rs
!= ra
|| rs
!= rb
) {
1613 tcg_gen_or_tl(cpu_gpr
[ra
], cpu_gpr
[rs
], cpu_gpr
[rb
]);
1615 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rs
]);
1616 if (unlikely(Rc(ctx
->opcode
) != 0))
1617 gen_set_Rc0(ctx
, cpu_gpr
[ra
]);
1618 } else if (unlikely(Rc(ctx
->opcode
) != 0)) {
1619 gen_set_Rc0(ctx
, cpu_gpr
[rs
]);
1620 #if defined(TARGET_PPC64)
1621 } else if (rs
!= 0) { /* 0 is nop */
1626 /* Set process priority to low */
1630 /* Set process priority to medium-low */
1634 /* Set process priority to normal */
1637 #if !defined(CONFIG_USER_ONLY)
1640 /* Set process priority to very low */
1646 /* Set process priority to medium-hight */
1652 /* Set process priority to high */
1657 if (ctx
->hv
&& !ctx
->pr
) {
1658 /* Set process priority to very high */
1667 TCGv t0
= tcg_temp_new();
1668 gen_load_spr(t0
, SPR_PPR
);
1669 tcg_gen_andi_tl(t0
, t0
, ~0x001C000000000000ULL
);
1670 tcg_gen_ori_tl(t0
, t0
, ((uint64_t)prio
) << 50);
1671 gen_store_spr(SPR_PPR
, t0
);
1674 #if !defined(CONFIG_USER_ONLY)
1675 /* Pause out of TCG otherwise spin loops with smt_low eat too much
1676 * CPU and the kernel hangs. This applies to all encodings other
1677 * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30),
1678 * and all currently undefined.
1686 GEN_LOGICAL2(orc
, tcg_gen_orc_tl
, 0x0C, PPC_INTEGER
);
1689 static void gen_xor(DisasContext
*ctx
)
1691 /* Optimisation for "set to zero" case */
1692 if (rS(ctx
->opcode
) != rB(ctx
->opcode
))
1693 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1695 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
1696 if (unlikely(Rc(ctx
->opcode
) != 0))
1697 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1701 static void gen_ori(DisasContext
*ctx
)
1703 target_ulong uimm
= UIMM(ctx
->opcode
);
1705 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1708 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
1712 static void gen_oris(DisasContext
*ctx
)
1714 target_ulong uimm
= UIMM(ctx
->opcode
);
1716 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1720 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
<< 16);
1724 static void gen_xori(DisasContext
*ctx
)
1726 target_ulong uimm
= UIMM(ctx
->opcode
);
1728 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1732 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
1736 static void gen_xoris(DisasContext
*ctx
)
1738 target_ulong uimm
= UIMM(ctx
->opcode
);
1740 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1744 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
<< 16);
1747 /* popcntb : PowerPC 2.03 specification */
1748 static void gen_popcntb(DisasContext
*ctx
)
1750 gen_helper_popcntb(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1753 static void gen_popcntw(DisasContext
*ctx
)
1755 #if defined(TARGET_PPC64)
1756 gen_helper_popcntw(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1758 tcg_gen_ctpop_i32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1762 #if defined(TARGET_PPC64)
1763 /* popcntd: PowerPC 2.06 specification */
1764 static void gen_popcntd(DisasContext
*ctx
)
1766 tcg_gen_ctpop_i64(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1770 /* prtyw: PowerPC 2.05 specification */
1771 static void gen_prtyw(DisasContext
*ctx
)
1773 TCGv ra
= cpu_gpr
[rA(ctx
->opcode
)];
1774 TCGv rs
= cpu_gpr
[rS(ctx
->opcode
)];
1775 TCGv t0
= tcg_temp_new();
1776 tcg_gen_shri_tl(t0
, rs
, 16);
1777 tcg_gen_xor_tl(ra
, rs
, t0
);
1778 tcg_gen_shri_tl(t0
, ra
, 8);
1779 tcg_gen_xor_tl(ra
, ra
, t0
);
1780 tcg_gen_andi_tl(ra
, ra
, (target_ulong
)0x100000001ULL
);
1784 #if defined(TARGET_PPC64)
1785 /* prtyd: PowerPC 2.05 specification */
1786 static void gen_prtyd(DisasContext
*ctx
)
1788 TCGv ra
= cpu_gpr
[rA(ctx
->opcode
)];
1789 TCGv rs
= cpu_gpr
[rS(ctx
->opcode
)];
1790 TCGv t0
= tcg_temp_new();
1791 tcg_gen_shri_tl(t0
, rs
, 32);
1792 tcg_gen_xor_tl(ra
, rs
, t0
);
1793 tcg_gen_shri_tl(t0
, ra
, 16);
1794 tcg_gen_xor_tl(ra
, ra
, t0
);
1795 tcg_gen_shri_tl(t0
, ra
, 8);
1796 tcg_gen_xor_tl(ra
, ra
, t0
);
1797 tcg_gen_andi_tl(ra
, ra
, 1);
1802 #if defined(TARGET_PPC64)
1804 static void gen_bpermd(DisasContext
*ctx
)
1806 gen_helper_bpermd(cpu_gpr
[rA(ctx
->opcode
)],
1807 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1811 #if defined(TARGET_PPC64)
1812 /* extsw & extsw. */
1813 GEN_LOGICAL1(extsw
, tcg_gen_ext32s_tl
, 0x1E, PPC_64B
);
1816 static void gen_cntlzd(DisasContext
*ctx
)
1818 tcg_gen_clzi_i64(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], 64);
1819 if (unlikely(Rc(ctx
->opcode
) != 0))
1820 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1824 static void gen_cnttzd(DisasContext
*ctx
)
1826 tcg_gen_ctzi_i64(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], 64);
1827 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1828 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1833 static void gen_darn(DisasContext
*ctx
)
1835 int l
= L(ctx
->opcode
);
1838 gen_helper_darn32(cpu_gpr
[rD(ctx
->opcode
)]);
1839 } else if (l
<= 2) {
1840 /* Return 64-bit random for both CRN and RRN */
1841 gen_helper_darn64(cpu_gpr
[rD(ctx
->opcode
)]);
1843 tcg_gen_movi_i64(cpu_gpr
[rD(ctx
->opcode
)], -1);
1848 /*** Integer rotate ***/
1850 /* rlwimi & rlwimi. */
1851 static void gen_rlwimi(DisasContext
*ctx
)
1853 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
1854 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
1855 uint32_t sh
= SH(ctx
->opcode
);
1856 uint32_t mb
= MB(ctx
->opcode
);
1857 uint32_t me
= ME(ctx
->opcode
);
1859 if (sh
== (31-me
) && mb
<= me
) {
1860 tcg_gen_deposit_tl(t_ra
, t_ra
, t_rs
, sh
, me
- mb
+ 1);
1865 #if defined(TARGET_PPC64)
1869 mask
= MASK(mb
, me
);
1871 t1
= tcg_temp_new();
1872 if (mask
<= 0xffffffffu
) {
1873 TCGv_i32 t0
= tcg_temp_new_i32();
1874 tcg_gen_trunc_tl_i32(t0
, t_rs
);
1875 tcg_gen_rotli_i32(t0
, t0
, sh
);
1876 tcg_gen_extu_i32_tl(t1
, t0
);
1877 tcg_temp_free_i32(t0
);
1879 #if defined(TARGET_PPC64)
1880 tcg_gen_deposit_i64(t1
, t_rs
, t_rs
, 32, 32);
1881 tcg_gen_rotli_i64(t1
, t1
, sh
);
1883 g_assert_not_reached();
1887 tcg_gen_andi_tl(t1
, t1
, mask
);
1888 tcg_gen_andi_tl(t_ra
, t_ra
, ~mask
);
1889 tcg_gen_or_tl(t_ra
, t_ra
, t1
);
1892 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1893 gen_set_Rc0(ctx
, t_ra
);
1897 /* rlwinm & rlwinm. */
1898 static void gen_rlwinm(DisasContext
*ctx
)
1900 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
1901 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
1902 int sh
= SH(ctx
->opcode
);
1903 int mb
= MB(ctx
->opcode
);
1904 int me
= ME(ctx
->opcode
);
1905 int len
= me
- mb
+ 1;
1906 int rsh
= (32 - sh
) & 31;
1908 if (sh
!= 0 && len
> 0 && me
== (31 - sh
)) {
1909 tcg_gen_deposit_z_tl(t_ra
, t_rs
, sh
, len
);
1910 } else if (me
== 31 && rsh
+ len
<= 32) {
1911 tcg_gen_extract_tl(t_ra
, t_rs
, rsh
, len
);
1914 #if defined(TARGET_PPC64)
1918 mask
= MASK(mb
, me
);
1920 tcg_gen_andi_tl(t_ra
, t_rs
, mask
);
1921 } else if (mask
<= 0xffffffffu
) {
1922 TCGv_i32 t0
= tcg_temp_new_i32();
1923 tcg_gen_trunc_tl_i32(t0
, t_rs
);
1924 tcg_gen_rotli_i32(t0
, t0
, sh
);
1925 tcg_gen_andi_i32(t0
, t0
, mask
);
1926 tcg_gen_extu_i32_tl(t_ra
, t0
);
1927 tcg_temp_free_i32(t0
);
1929 #if defined(TARGET_PPC64)
1930 tcg_gen_deposit_i64(t_ra
, t_rs
, t_rs
, 32, 32);
1931 tcg_gen_rotli_i64(t_ra
, t_ra
, sh
);
1932 tcg_gen_andi_i64(t_ra
, t_ra
, mask
);
1934 g_assert_not_reached();
1938 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1939 gen_set_Rc0(ctx
, t_ra
);
1943 /* rlwnm & rlwnm. */
1944 static void gen_rlwnm(DisasContext
*ctx
)
1946 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
1947 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
1948 TCGv t_rb
= cpu_gpr
[rB(ctx
->opcode
)];
1949 uint32_t mb
= MB(ctx
->opcode
);
1950 uint32_t me
= ME(ctx
->opcode
);
1953 #if defined(TARGET_PPC64)
1957 mask
= MASK(mb
, me
);
1959 if (mask
<= 0xffffffffu
) {
1960 TCGv_i32 t0
= tcg_temp_new_i32();
1961 TCGv_i32 t1
= tcg_temp_new_i32();
1962 tcg_gen_trunc_tl_i32(t0
, t_rb
);
1963 tcg_gen_trunc_tl_i32(t1
, t_rs
);
1964 tcg_gen_andi_i32(t0
, t0
, 0x1f);
1965 tcg_gen_rotl_i32(t1
, t1
, t0
);
1966 tcg_gen_extu_i32_tl(t_ra
, t1
);
1967 tcg_temp_free_i32(t0
);
1968 tcg_temp_free_i32(t1
);
1970 #if defined(TARGET_PPC64)
1971 TCGv_i64 t0
= tcg_temp_new_i64();
1972 tcg_gen_andi_i64(t0
, t_rb
, 0x1f);
1973 tcg_gen_deposit_i64(t_ra
, t_rs
, t_rs
, 32, 32);
1974 tcg_gen_rotl_i64(t_ra
, t_ra
, t0
);
1975 tcg_temp_free_i64(t0
);
1977 g_assert_not_reached();
1981 tcg_gen_andi_tl(t_ra
, t_ra
, mask
);
1983 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1984 gen_set_Rc0(ctx
, t_ra
);
1988 #if defined(TARGET_PPC64)
1989 #define GEN_PPC64_R2(name, opc1, opc2) \
1990 static void glue(gen_, name##0)(DisasContext *ctx) \
1992 gen_##name(ctx, 0); \
1995 static void glue(gen_, name##1)(DisasContext *ctx) \
1997 gen_##name(ctx, 1); \
1999 #define GEN_PPC64_R4(name, opc1, opc2) \
2000 static void glue(gen_, name##0)(DisasContext *ctx) \
2002 gen_##name(ctx, 0, 0); \
2005 static void glue(gen_, name##1)(DisasContext *ctx) \
2007 gen_##name(ctx, 0, 1); \
2010 static void glue(gen_, name##2)(DisasContext *ctx) \
2012 gen_##name(ctx, 1, 0); \
2015 static void glue(gen_, name##3)(DisasContext *ctx) \
2017 gen_##name(ctx, 1, 1); \
2020 static void gen_rldinm(DisasContext
*ctx
, int mb
, int me
, int sh
)
2022 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
2023 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
2024 int len
= me
- mb
+ 1;
2025 int rsh
= (64 - sh
) & 63;
2027 if (sh
!= 0 && len
> 0 && me
== (63 - sh
)) {
2028 tcg_gen_deposit_z_tl(t_ra
, t_rs
, sh
, len
);
2029 } else if (me
== 63 && rsh
+ len
<= 64) {
2030 tcg_gen_extract_tl(t_ra
, t_rs
, rsh
, len
);
2032 tcg_gen_rotli_tl(t_ra
, t_rs
, sh
);
2033 tcg_gen_andi_tl(t_ra
, t_ra
, MASK(mb
, me
));
2035 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2036 gen_set_Rc0(ctx
, t_ra
);
2040 /* rldicl - rldicl. */
2041 static inline void gen_rldicl(DisasContext
*ctx
, int mbn
, int shn
)
2045 sh
= SH(ctx
->opcode
) | (shn
<< 5);
2046 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
2047 gen_rldinm(ctx
, mb
, 63, sh
);
2049 GEN_PPC64_R4(rldicl
, 0x1E, 0x00);
2051 /* rldicr - rldicr. */
2052 static inline void gen_rldicr(DisasContext
*ctx
, int men
, int shn
)
2056 sh
= SH(ctx
->opcode
) | (shn
<< 5);
2057 me
= MB(ctx
->opcode
) | (men
<< 5);
2058 gen_rldinm(ctx
, 0, me
, sh
);
2060 GEN_PPC64_R4(rldicr
, 0x1E, 0x02);
2062 /* rldic - rldic. */
2063 static inline void gen_rldic(DisasContext
*ctx
, int mbn
, int shn
)
2067 sh
= SH(ctx
->opcode
) | (shn
<< 5);
2068 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
2069 gen_rldinm(ctx
, mb
, 63 - sh
, sh
);
2071 GEN_PPC64_R4(rldic
, 0x1E, 0x04);
2073 static void gen_rldnm(DisasContext
*ctx
, int mb
, int me
)
2075 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
2076 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
2077 TCGv t_rb
= cpu_gpr
[rB(ctx
->opcode
)];
2080 t0
= tcg_temp_new();
2081 tcg_gen_andi_tl(t0
, t_rb
, 0x3f);
2082 tcg_gen_rotl_tl(t_ra
, t_rs
, t0
);
2085 tcg_gen_andi_tl(t_ra
, t_ra
, MASK(mb
, me
));
2086 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2087 gen_set_Rc0(ctx
, t_ra
);
2091 /* rldcl - rldcl. */
2092 static inline void gen_rldcl(DisasContext
*ctx
, int mbn
)
2096 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
2097 gen_rldnm(ctx
, mb
, 63);
2099 GEN_PPC64_R2(rldcl
, 0x1E, 0x08);
2101 /* rldcr - rldcr. */
2102 static inline void gen_rldcr(DisasContext
*ctx
, int men
)
2106 me
= MB(ctx
->opcode
) | (men
<< 5);
2107 gen_rldnm(ctx
, 0, me
);
2109 GEN_PPC64_R2(rldcr
, 0x1E, 0x09);
2111 /* rldimi - rldimi. */
2112 static void gen_rldimi(DisasContext
*ctx
, int mbn
, int shn
)
2114 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
2115 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
2116 uint32_t sh
= SH(ctx
->opcode
) | (shn
<< 5);
2117 uint32_t mb
= MB(ctx
->opcode
) | (mbn
<< 5);
2118 uint32_t me
= 63 - sh
;
2121 tcg_gen_deposit_tl(t_ra
, t_ra
, t_rs
, sh
, me
- mb
+ 1);
2123 target_ulong mask
= MASK(mb
, me
);
2124 TCGv t1
= tcg_temp_new();
2126 tcg_gen_rotli_tl(t1
, t_rs
, sh
);
2127 tcg_gen_andi_tl(t1
, t1
, mask
);
2128 tcg_gen_andi_tl(t_ra
, t_ra
, ~mask
);
2129 tcg_gen_or_tl(t_ra
, t_ra
, t1
);
2132 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2133 gen_set_Rc0(ctx
, t_ra
);
2136 GEN_PPC64_R4(rldimi
, 0x1E, 0x06);
2139 /*** Integer shift ***/
2142 static void gen_slw(DisasContext
*ctx
)
2146 t0
= tcg_temp_new();
2147 /* AND rS with a mask that is 0 when rB >= 0x20 */
2148 #if defined(TARGET_PPC64)
2149 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3a);
2150 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2152 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1a);
2153 tcg_gen_sari_tl(t0
, t0
, 0x1f);
2155 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2156 t1
= tcg_temp_new();
2157 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
2158 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2161 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
2162 if (unlikely(Rc(ctx
->opcode
) != 0))
2163 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2167 static void gen_sraw(DisasContext
*ctx
)
2169 gen_helper_sraw(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
2170 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2171 if (unlikely(Rc(ctx
->opcode
) != 0))
2172 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2175 /* srawi & srawi. */
2176 static void gen_srawi(DisasContext
*ctx
)
2178 int sh
= SH(ctx
->opcode
);
2179 TCGv dst
= cpu_gpr
[rA(ctx
->opcode
)];
2180 TCGv src
= cpu_gpr
[rS(ctx
->opcode
)];
2182 tcg_gen_ext32s_tl(dst
, src
);
2183 tcg_gen_movi_tl(cpu_ca
, 0);
2184 if (is_isa300(ctx
)) {
2185 tcg_gen_movi_tl(cpu_ca32
, 0);
2189 tcg_gen_ext32s_tl(dst
, src
);
2190 tcg_gen_andi_tl(cpu_ca
, dst
, (1ULL << sh
) - 1);
2191 t0
= tcg_temp_new();
2192 tcg_gen_sari_tl(t0
, dst
, TARGET_LONG_BITS
- 1);
2193 tcg_gen_and_tl(cpu_ca
, cpu_ca
, t0
);
2195 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_ca
, cpu_ca
, 0);
2196 if (is_isa300(ctx
)) {
2197 tcg_gen_mov_tl(cpu_ca32
, cpu_ca
);
2199 tcg_gen_sari_tl(dst
, dst
, sh
);
2201 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2202 gen_set_Rc0(ctx
, dst
);
2207 static void gen_srw(DisasContext
*ctx
)
2211 t0
= tcg_temp_new();
2212 /* AND rS with a mask that is 0 when rB >= 0x20 */
2213 #if defined(TARGET_PPC64)
2214 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3a);
2215 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2217 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1a);
2218 tcg_gen_sari_tl(t0
, t0
, 0x1f);
2220 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2221 tcg_gen_ext32u_tl(t0
, t0
);
2222 t1
= tcg_temp_new();
2223 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
2224 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2227 if (unlikely(Rc(ctx
->opcode
) != 0))
2228 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2231 #if defined(TARGET_PPC64)
2233 static void gen_sld(DisasContext
*ctx
)
2237 t0
= tcg_temp_new();
2238 /* AND rS with a mask that is 0 when rB >= 0x40 */
2239 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x39);
2240 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2241 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2242 t1
= tcg_temp_new();
2243 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
2244 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2247 if (unlikely(Rc(ctx
->opcode
) != 0))
2248 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2252 static void gen_srad(DisasContext
*ctx
)
2254 gen_helper_srad(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
2255 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2256 if (unlikely(Rc(ctx
->opcode
) != 0))
2257 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2259 /* sradi & sradi. */
2260 static inline void gen_sradi(DisasContext
*ctx
, int n
)
2262 int sh
= SH(ctx
->opcode
) + (n
<< 5);
2263 TCGv dst
= cpu_gpr
[rA(ctx
->opcode
)];
2264 TCGv src
= cpu_gpr
[rS(ctx
->opcode
)];
2266 tcg_gen_mov_tl(dst
, src
);
2267 tcg_gen_movi_tl(cpu_ca
, 0);
2268 if (is_isa300(ctx
)) {
2269 tcg_gen_movi_tl(cpu_ca32
, 0);
2273 tcg_gen_andi_tl(cpu_ca
, src
, (1ULL << sh
) - 1);
2274 t0
= tcg_temp_new();
2275 tcg_gen_sari_tl(t0
, src
, TARGET_LONG_BITS
- 1);
2276 tcg_gen_and_tl(cpu_ca
, cpu_ca
, t0
);
2278 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_ca
, cpu_ca
, 0);
2279 if (is_isa300(ctx
)) {
2280 tcg_gen_mov_tl(cpu_ca32
, cpu_ca
);
2282 tcg_gen_sari_tl(dst
, src
, sh
);
2284 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2285 gen_set_Rc0(ctx
, dst
);
2289 static void gen_sradi0(DisasContext
*ctx
)
2294 static void gen_sradi1(DisasContext
*ctx
)
2299 /* extswsli & extswsli. */
2300 static inline void gen_extswsli(DisasContext
*ctx
, int n
)
2302 int sh
= SH(ctx
->opcode
) + (n
<< 5);
2303 TCGv dst
= cpu_gpr
[rA(ctx
->opcode
)];
2304 TCGv src
= cpu_gpr
[rS(ctx
->opcode
)];
2306 tcg_gen_ext32s_tl(dst
, src
);
2307 tcg_gen_shli_tl(dst
, dst
, sh
);
2308 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2309 gen_set_Rc0(ctx
, dst
);
2313 static void gen_extswsli0(DisasContext
*ctx
)
2315 gen_extswsli(ctx
, 0);
2318 static void gen_extswsli1(DisasContext
*ctx
)
2320 gen_extswsli(ctx
, 1);
2324 static void gen_srd(DisasContext
*ctx
)
2328 t0
= tcg_temp_new();
2329 /* AND rS with a mask that is 0 when rB >= 0x40 */
2330 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x39);
2331 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2332 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2333 t1
= tcg_temp_new();
2334 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
2335 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2338 if (unlikely(Rc(ctx
->opcode
) != 0))
2339 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2343 /*** Addressing modes ***/
2344 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2345 static inline void gen_addr_imm_index(DisasContext
*ctx
, TCGv EA
,
2348 target_long simm
= SIMM(ctx
->opcode
);
2351 if (rA(ctx
->opcode
) == 0) {
2352 if (NARROW_MODE(ctx
)) {
2353 simm
= (uint32_t)simm
;
2355 tcg_gen_movi_tl(EA
, simm
);
2356 } else if (likely(simm
!= 0)) {
2357 tcg_gen_addi_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], simm
);
2358 if (NARROW_MODE(ctx
)) {
2359 tcg_gen_ext32u_tl(EA
, EA
);
2362 if (NARROW_MODE(ctx
)) {
2363 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2365 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2370 static inline void gen_addr_reg_index(DisasContext
*ctx
, TCGv EA
)
2372 if (rA(ctx
->opcode
) == 0) {
2373 if (NARROW_MODE(ctx
)) {
2374 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
2376 tcg_gen_mov_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
2379 tcg_gen_add_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2380 if (NARROW_MODE(ctx
)) {
2381 tcg_gen_ext32u_tl(EA
, EA
);
2386 static inline void gen_addr_register(DisasContext
*ctx
, TCGv EA
)
2388 if (rA(ctx
->opcode
) == 0) {
2389 tcg_gen_movi_tl(EA
, 0);
2390 } else if (NARROW_MODE(ctx
)) {
2391 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2393 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2397 static inline void gen_addr_add(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
2400 tcg_gen_addi_tl(ret
, arg1
, val
);
2401 if (NARROW_MODE(ctx
)) {
2402 tcg_gen_ext32u_tl(ret
, ret
);
2406 static inline void gen_check_align(DisasContext
*ctx
, TCGv EA
, int mask
)
2408 TCGLabel
*l1
= gen_new_label();
2409 TCGv t0
= tcg_temp_new();
2411 tcg_gen_andi_tl(t0
, EA
, mask
);
2412 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
2413 t1
= tcg_const_i32(POWERPC_EXCP_ALIGN
);
2414 t2
= tcg_const_i32(ctx
->opcode
& 0x03FF0000);
2415 gen_update_nip(ctx
, ctx
->nip
- 4);
2416 gen_helper_raise_exception_err(cpu_env
, t1
, t2
);
2417 tcg_temp_free_i32(t1
);
2418 tcg_temp_free_i32(t2
);
2423 static inline void gen_align_no_le(DisasContext
*ctx
)
2425 gen_exception_err(ctx
, POWERPC_EXCP_ALIGN
,
2426 (ctx
->opcode
& 0x03FF0000) | POWERPC_EXCP_ALIGN_LE
);
2429 /*** Integer load ***/
2430 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask)
2431 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP))
2433 #define GEN_QEMU_LOAD_TL(ldop, op) \
2434 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \
2438 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \
2441 GEN_QEMU_LOAD_TL(ld8u
, DEF_MEMOP(MO_UB
))
2442 GEN_QEMU_LOAD_TL(ld16u
, DEF_MEMOP(MO_UW
))
2443 GEN_QEMU_LOAD_TL(ld16s
, DEF_MEMOP(MO_SW
))
2444 GEN_QEMU_LOAD_TL(ld32u
, DEF_MEMOP(MO_UL
))
2445 GEN_QEMU_LOAD_TL(ld32s
, DEF_MEMOP(MO_SL
))
2447 GEN_QEMU_LOAD_TL(ld16ur
, BSWAP_MEMOP(MO_UW
))
2448 GEN_QEMU_LOAD_TL(ld32ur
, BSWAP_MEMOP(MO_UL
))
2450 #define GEN_QEMU_LOAD_64(ldop, op) \
2451 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \
2455 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \
2458 GEN_QEMU_LOAD_64(ld8u
, DEF_MEMOP(MO_UB
))
2459 GEN_QEMU_LOAD_64(ld16u
, DEF_MEMOP(MO_UW
))
2460 GEN_QEMU_LOAD_64(ld32u
, DEF_MEMOP(MO_UL
))
2461 GEN_QEMU_LOAD_64(ld32s
, DEF_MEMOP(MO_SL
))
2462 GEN_QEMU_LOAD_64(ld64
, DEF_MEMOP(MO_Q
))
2464 #if defined(TARGET_PPC64)
2465 GEN_QEMU_LOAD_64(ld64ur
, BSWAP_MEMOP(MO_Q
))
2468 #define GEN_QEMU_STORE_TL(stop, op) \
2469 static void glue(gen_qemu_, stop)(DisasContext *ctx, \
2473 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
2476 GEN_QEMU_STORE_TL(st8
, DEF_MEMOP(MO_UB
))
2477 GEN_QEMU_STORE_TL(st16
, DEF_MEMOP(MO_UW
))
2478 GEN_QEMU_STORE_TL(st32
, DEF_MEMOP(MO_UL
))
2480 GEN_QEMU_STORE_TL(st16r
, BSWAP_MEMOP(MO_UW
))
2481 GEN_QEMU_STORE_TL(st32r
, BSWAP_MEMOP(MO_UL
))
2483 #define GEN_QEMU_STORE_64(stop, op) \
2484 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \
2488 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \
2491 GEN_QEMU_STORE_64(st8
, DEF_MEMOP(MO_UB
))
2492 GEN_QEMU_STORE_64(st16
, DEF_MEMOP(MO_UW
))
2493 GEN_QEMU_STORE_64(st32
, DEF_MEMOP(MO_UL
))
2494 GEN_QEMU_STORE_64(st64
, DEF_MEMOP(MO_Q
))
2496 #if defined(TARGET_PPC64)
2497 GEN_QEMU_STORE_64(st64r
, BSWAP_MEMOP(MO_Q
))
2500 #define GEN_LD(name, ldop, opc, type) \
2501 static void glue(gen_, name)(DisasContext *ctx) \
2504 gen_set_access_type(ctx, ACCESS_INT); \
2505 EA = tcg_temp_new(); \
2506 gen_addr_imm_index(ctx, EA, 0); \
2507 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2508 tcg_temp_free(EA); \
2511 #define GEN_LDU(name, ldop, opc, type) \
2512 static void glue(gen_, name##u)(DisasContext *ctx) \
2515 if (unlikely(rA(ctx->opcode) == 0 || \
2516 rA(ctx->opcode) == rD(ctx->opcode))) { \
2517 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2520 gen_set_access_type(ctx, ACCESS_INT); \
2521 EA = tcg_temp_new(); \
2522 if (type == PPC_64B) \
2523 gen_addr_imm_index(ctx, EA, 0x03); \
2525 gen_addr_imm_index(ctx, EA, 0); \
2526 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2527 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2528 tcg_temp_free(EA); \
2531 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2532 static void glue(gen_, name##ux)(DisasContext *ctx) \
2535 if (unlikely(rA(ctx->opcode) == 0 || \
2536 rA(ctx->opcode) == rD(ctx->opcode))) { \
2537 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2540 gen_set_access_type(ctx, ACCESS_INT); \
2541 EA = tcg_temp_new(); \
2542 gen_addr_reg_index(ctx, EA); \
2543 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2544 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2545 tcg_temp_free(EA); \
2548 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
2549 static void glue(gen_, name##x)(DisasContext *ctx) \
2553 gen_set_access_type(ctx, ACCESS_INT); \
2554 EA = tcg_temp_new(); \
2555 gen_addr_reg_index(ctx, EA); \
2556 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2557 tcg_temp_free(EA); \
2560 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2561 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2563 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
2564 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2566 #define GEN_LDS(name, ldop, op, type) \
2567 GEN_LD(name, ldop, op | 0x20, type); \
2568 GEN_LDU(name, ldop, op | 0x21, type); \
2569 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2570 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2572 /* lbz lbzu lbzux lbzx */
2573 GEN_LDS(lbz
, ld8u
, 0x02, PPC_INTEGER
);
2574 /* lha lhau lhaux lhax */
2575 GEN_LDS(lha
, ld16s
, 0x0A, PPC_INTEGER
);
2576 /* lhz lhzu lhzux lhzx */
2577 GEN_LDS(lhz
, ld16u
, 0x08, PPC_INTEGER
);
2578 /* lwz lwzu lwzux lwzx */
2579 GEN_LDS(lwz
, ld32u
, 0x00, PPC_INTEGER
);
2580 #if defined(TARGET_PPC64)
2582 GEN_LDUX(lwa
, ld32s
, 0x15, 0x0B, PPC_64B
);
2584 GEN_LDX(lwa
, ld32s
, 0x15, 0x0A, PPC_64B
);
2586 GEN_LDUX(ld
, ld64_i64
, 0x15, 0x01, PPC_64B
);
2588 GEN_LDX(ld
, ld64_i64
, 0x15, 0x00, PPC_64B
);
2590 /* CI load/store variants */
2591 GEN_LDX_HVRM(ldcix
, ld64_i64
, 0x15, 0x1b, PPC_CILDST
)
2592 GEN_LDX_HVRM(lwzcix
, ld32u
, 0x15, 0x15, PPC_CILDST
)
2593 GEN_LDX_HVRM(lhzcix
, ld16u
, 0x15, 0x19, PPC_CILDST
)
2594 GEN_LDX_HVRM(lbzcix
, ld8u
, 0x15, 0x1a, PPC_CILDST
)
2596 static void gen_ld(DisasContext
*ctx
)
2599 if (Rc(ctx
->opcode
)) {
2600 if (unlikely(rA(ctx
->opcode
) == 0 ||
2601 rA(ctx
->opcode
) == rD(ctx
->opcode
))) {
2602 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2606 gen_set_access_type(ctx
, ACCESS_INT
);
2607 EA
= tcg_temp_new();
2608 gen_addr_imm_index(ctx
, EA
, 0x03);
2609 if (ctx
->opcode
& 0x02) {
2610 /* lwa (lwau is undefined) */
2611 gen_qemu_ld32s(ctx
, cpu_gpr
[rD(ctx
->opcode
)], EA
);
2614 gen_qemu_ld64_i64(ctx
, cpu_gpr
[rD(ctx
->opcode
)], EA
);
2616 if (Rc(ctx
->opcode
))
2617 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
2622 static void gen_lq(DisasContext
*ctx
)
2627 /* lq is a legal user mode instruction starting in ISA 2.07 */
2628 bool legal_in_user_mode
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
2629 bool le_is_supported
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
2631 if (!legal_in_user_mode
&& ctx
->pr
) {
2632 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2636 if (!le_is_supported
&& ctx
->le_mode
) {
2637 gen_align_no_le(ctx
);
2640 ra
= rA(ctx
->opcode
);
2641 rd
= rD(ctx
->opcode
);
2642 if (unlikely((rd
& 1) || rd
== ra
)) {
2643 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2647 gen_set_access_type(ctx
, ACCESS_INT
);
2648 EA
= tcg_temp_new();
2649 gen_addr_imm_index(ctx
, EA
, 0x0F);
2651 /* We only need to swap high and low halves. gen_qemu_ld64_i64 does
2652 necessary 64-bit byteswap already. */
2653 if (unlikely(ctx
->le_mode
)) {
2654 gen_qemu_ld64_i64(ctx
, cpu_gpr
[rd
+ 1], EA
);
2655 gen_addr_add(ctx
, EA
, EA
, 8);
2656 gen_qemu_ld64_i64(ctx
, cpu_gpr
[rd
], EA
);
2658 gen_qemu_ld64_i64(ctx
, cpu_gpr
[rd
], EA
);
2659 gen_addr_add(ctx
, EA
, EA
, 8);
2660 gen_qemu_ld64_i64(ctx
, cpu_gpr
[rd
+ 1], EA
);
2666 /*** Integer store ***/
2667 #define GEN_ST(name, stop, opc, type) \
2668 static void glue(gen_, name)(DisasContext *ctx) \
2671 gen_set_access_type(ctx, ACCESS_INT); \
2672 EA = tcg_temp_new(); \
2673 gen_addr_imm_index(ctx, EA, 0); \
2674 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2675 tcg_temp_free(EA); \
2678 #define GEN_STU(name, stop, opc, type) \
2679 static void glue(gen_, stop##u)(DisasContext *ctx) \
2682 if (unlikely(rA(ctx->opcode) == 0)) { \
2683 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2686 gen_set_access_type(ctx, ACCESS_INT); \
2687 EA = tcg_temp_new(); \
2688 if (type == PPC_64B) \
2689 gen_addr_imm_index(ctx, EA, 0x03); \
2691 gen_addr_imm_index(ctx, EA, 0); \
2692 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2693 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2694 tcg_temp_free(EA); \
2697 #define GEN_STUX(name, stop, opc2, opc3, type) \
2698 static void glue(gen_, name##ux)(DisasContext *ctx) \
2701 if (unlikely(rA(ctx->opcode) == 0)) { \
2702 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2705 gen_set_access_type(ctx, ACCESS_INT); \
2706 EA = tcg_temp_new(); \
2707 gen_addr_reg_index(ctx, EA); \
2708 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2709 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2710 tcg_temp_free(EA); \
2713 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
2714 static void glue(gen_, name##x)(DisasContext *ctx) \
2718 gen_set_access_type(ctx, ACCESS_INT); \
2719 EA = tcg_temp_new(); \
2720 gen_addr_reg_index(ctx, EA); \
2721 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2722 tcg_temp_free(EA); \
2724 #define GEN_STX(name, stop, opc2, opc3, type) \
2725 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2727 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
2728 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2730 #define GEN_STS(name, stop, op, type) \
2731 GEN_ST(name, stop, op | 0x20, type); \
2732 GEN_STU(name, stop, op | 0x21, type); \
2733 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2734 GEN_STX(name, stop, 0x17, op | 0x00, type)
2736 /* stb stbu stbux stbx */
2737 GEN_STS(stb
, st8
, 0x06, PPC_INTEGER
);
2738 /* sth sthu sthux sthx */
2739 GEN_STS(sth
, st16
, 0x0C, PPC_INTEGER
);
2740 /* stw stwu stwux stwx */
2741 GEN_STS(stw
, st32
, 0x04, PPC_INTEGER
);
2742 #if defined(TARGET_PPC64)
2743 GEN_STUX(std
, st64_i64
, 0x15, 0x05, PPC_64B
);
2744 GEN_STX(std
, st64_i64
, 0x15, 0x04, PPC_64B
);
2745 GEN_STX_HVRM(stdcix
, st64_i64
, 0x15, 0x1f, PPC_CILDST
)
2746 GEN_STX_HVRM(stwcix
, st32
, 0x15, 0x1c, PPC_CILDST
)
2747 GEN_STX_HVRM(sthcix
, st16
, 0x15, 0x1d, PPC_CILDST
)
2748 GEN_STX_HVRM(stbcix
, st8
, 0x15, 0x1e, PPC_CILDST
)
2750 static void gen_std(DisasContext
*ctx
)
2755 rs
= rS(ctx
->opcode
);
2756 if ((ctx
->opcode
& 0x3) == 0x2) { /* stq */
2757 bool legal_in_user_mode
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
2758 bool le_is_supported
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
2760 if (!(ctx
->insns_flags
& PPC_64BX
)) {
2761 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2764 if (!legal_in_user_mode
&& ctx
->pr
) {
2765 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2769 if (!le_is_supported
&& ctx
->le_mode
) {
2770 gen_align_no_le(ctx
);
2774 if (unlikely(rs
& 1)) {
2775 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2778 gen_set_access_type(ctx
, ACCESS_INT
);
2779 EA
= tcg_temp_new();
2780 gen_addr_imm_index(ctx
, EA
, 0x03);
2782 /* We only need to swap high and low halves. gen_qemu_st64_i64 does
2783 necessary 64-bit byteswap already. */
2784 if (unlikely(ctx
->le_mode
)) {
2785 gen_qemu_st64_i64(ctx
, cpu_gpr
[rs
+ 1], EA
);
2786 gen_addr_add(ctx
, EA
, EA
, 8);
2787 gen_qemu_st64_i64(ctx
, cpu_gpr
[rs
], EA
);
2789 gen_qemu_st64_i64(ctx
, cpu_gpr
[rs
], EA
);
2790 gen_addr_add(ctx
, EA
, EA
, 8);
2791 gen_qemu_st64_i64(ctx
, cpu_gpr
[rs
+ 1], EA
);
2796 if (Rc(ctx
->opcode
)) {
2797 if (unlikely(rA(ctx
->opcode
) == 0)) {
2798 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2802 gen_set_access_type(ctx
, ACCESS_INT
);
2803 EA
= tcg_temp_new();
2804 gen_addr_imm_index(ctx
, EA
, 0x03);
2805 gen_qemu_st64_i64(ctx
, cpu_gpr
[rs
], EA
);
2806 if (Rc(ctx
->opcode
))
2807 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
2812 /*** Integer load and store with byte reverse ***/
2815 GEN_LDX(lhbr
, ld16ur
, 0x16, 0x18, PPC_INTEGER
);
2818 GEN_LDX(lwbr
, ld32ur
, 0x16, 0x10, PPC_INTEGER
);
2820 #if defined(TARGET_PPC64)
2822 GEN_LDX_E(ldbr
, ld64ur_i64
, 0x14, 0x10, PPC_NONE
, PPC2_DBRX
, CHK_NONE
);
2824 GEN_STX_E(stdbr
, st64r_i64
, 0x14, 0x14, PPC_NONE
, PPC2_DBRX
, CHK_NONE
);
2825 #endif /* TARGET_PPC64 */
2828 GEN_STX(sthbr
, st16r
, 0x16, 0x1C, PPC_INTEGER
);
2830 GEN_STX(stwbr
, st32r
, 0x16, 0x14, PPC_INTEGER
);
2832 /*** Integer load and store multiple ***/
2835 static void gen_lmw(DisasContext
*ctx
)
2841 gen_align_no_le(ctx
);
2844 gen_set_access_type(ctx
, ACCESS_INT
);
2845 t0
= tcg_temp_new();
2846 t1
= tcg_const_i32(rD(ctx
->opcode
));
2847 gen_addr_imm_index(ctx
, t0
, 0);
2848 gen_helper_lmw(cpu_env
, t0
, t1
);
2850 tcg_temp_free_i32(t1
);
2854 static void gen_stmw(DisasContext
*ctx
)
2860 gen_align_no_le(ctx
);
2863 gen_set_access_type(ctx
, ACCESS_INT
);
2864 t0
= tcg_temp_new();
2865 t1
= tcg_const_i32(rS(ctx
->opcode
));
2866 gen_addr_imm_index(ctx
, t0
, 0);
2867 gen_helper_stmw(cpu_env
, t0
, t1
);
2869 tcg_temp_free_i32(t1
);
2872 /*** Integer load and store strings ***/
2875 /* PowerPC32 specification says we must generate an exception if
2876 * rA is in the range of registers to be loaded.
2877 * In an other hand, IBM says this is valid, but rA won't be loaded.
2878 * For now, I'll follow the spec...
2880 static void gen_lswi(DisasContext
*ctx
)
2884 int nb
= NB(ctx
->opcode
);
2885 int start
= rD(ctx
->opcode
);
2886 int ra
= rA(ctx
->opcode
);
2890 gen_align_no_le(ctx
);
2895 nr
= DIV_ROUND_UP(nb
, 4);
2896 if (unlikely(lsw_reg_in_range(start
, nr
, ra
))) {
2897 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
2900 gen_set_access_type(ctx
, ACCESS_INT
);
2901 t0
= tcg_temp_new();
2902 gen_addr_register(ctx
, t0
);
2903 t1
= tcg_const_i32(nb
);
2904 t2
= tcg_const_i32(start
);
2905 gen_helper_lsw(cpu_env
, t0
, t1
, t2
);
2907 tcg_temp_free_i32(t1
);
2908 tcg_temp_free_i32(t2
);
2912 static void gen_lswx(DisasContext
*ctx
)
2915 TCGv_i32 t1
, t2
, t3
;
2918 gen_align_no_le(ctx
);
2921 gen_set_access_type(ctx
, ACCESS_INT
);
2922 t0
= tcg_temp_new();
2923 gen_addr_reg_index(ctx
, t0
);
2924 t1
= tcg_const_i32(rD(ctx
->opcode
));
2925 t2
= tcg_const_i32(rA(ctx
->opcode
));
2926 t3
= tcg_const_i32(rB(ctx
->opcode
));
2927 gen_helper_lswx(cpu_env
, t0
, t1
, t2
, t3
);
2929 tcg_temp_free_i32(t1
);
2930 tcg_temp_free_i32(t2
);
2931 tcg_temp_free_i32(t3
);
2935 static void gen_stswi(DisasContext
*ctx
)
2939 int nb
= NB(ctx
->opcode
);
2942 gen_align_no_le(ctx
);
2945 gen_set_access_type(ctx
, ACCESS_INT
);
2946 t0
= tcg_temp_new();
2947 gen_addr_register(ctx
, t0
);
2950 t1
= tcg_const_i32(nb
);
2951 t2
= tcg_const_i32(rS(ctx
->opcode
));
2952 gen_helper_stsw(cpu_env
, t0
, t1
, t2
);
2954 tcg_temp_free_i32(t1
);
2955 tcg_temp_free_i32(t2
);
2959 static void gen_stswx(DisasContext
*ctx
)
2965 gen_align_no_le(ctx
);
2968 gen_set_access_type(ctx
, ACCESS_INT
);
2969 t0
= tcg_temp_new();
2970 gen_addr_reg_index(ctx
, t0
);
2971 t1
= tcg_temp_new_i32();
2972 tcg_gen_trunc_tl_i32(t1
, cpu_xer
);
2973 tcg_gen_andi_i32(t1
, t1
, 0x7F);
2974 t2
= tcg_const_i32(rS(ctx
->opcode
));
2975 gen_helper_stsw(cpu_env
, t0
, t1
, t2
);
2977 tcg_temp_free_i32(t1
);
2978 tcg_temp_free_i32(t2
);
2981 /*** Memory synchronisation ***/
2983 static void gen_eieio(DisasContext
*ctx
)
2985 tcg_gen_mb(TCG_MO_LD_ST
| TCG_BAR_SC
);
2988 #if !defined(CONFIG_USER_ONLY)
2989 static inline void gen_check_tlb_flush(DisasContext
*ctx
, bool global
)
2994 if (!ctx
->lazy_tlb_flush
) {
2997 l
= gen_new_label();
2998 t
= tcg_temp_new_i32();
2999 tcg_gen_ld_i32(t
, cpu_env
, offsetof(CPUPPCState
, tlb_need_flush
));
3000 tcg_gen_brcondi_i32(TCG_COND_EQ
, t
, 0, l
);
3002 gen_helper_check_tlb_flush_global(cpu_env
);
3004 gen_helper_check_tlb_flush_local(cpu_env
);
3007 tcg_temp_free_i32(t
);
3010 static inline void gen_check_tlb_flush(DisasContext
*ctx
, bool global
) { }
3014 static void gen_isync(DisasContext
*ctx
)
3017 * We need to check for a pending TLB flush. This can only happen in
3018 * kernel mode however so check MSR_PR
3021 gen_check_tlb_flush(ctx
, false);
3023 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
3024 gen_stop_exception(ctx
);
3027 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))
3029 #define LARX(name, memop) \
3030 static void gen_##name(DisasContext *ctx) \
3033 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3034 int len = MEMOP_GET_SIZE(memop); \
3035 gen_set_access_type(ctx, ACCESS_RES); \
3036 t0 = tcg_temp_local_new(); \
3037 gen_addr_reg_index(ctx, t0); \
3039 gen_check_align(ctx, t0, (len)-1); \
3041 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop); \
3042 tcg_gen_mov_tl(cpu_reserve, t0); \
3043 tcg_gen_mov_tl(cpu_reserve_val, gpr); \
3044 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); \
3045 tcg_temp_free(t0); \
3049 LARX(lbarx
, DEF_MEMOP(MO_UB
))
3050 LARX(lharx
, DEF_MEMOP(MO_UW
))
3051 LARX(lwarx
, DEF_MEMOP(MO_UL
))
3053 #define LD_ATOMIC(name, memop, tp, op, eop) \
3054 static void gen_##name(DisasContext *ctx) \
3056 int len = MEMOP_GET_SIZE(memop); \
3057 uint32_t gpr_FC = FC(ctx->opcode); \
3058 TCGv EA = tcg_temp_local_new(); \
3061 gen_addr_register(ctx, EA); \
3063 gen_check_align(ctx, EA, len - 1); \
3065 t0 = tcg_temp_new_##tp(); \
3066 t1 = tcg_temp_new_##tp(); \
3067 tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \
3070 case 0: /* Fetch and add */ \
3071 tcg_gen_atomic_fetch_add_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3073 case 1: /* Fetch and xor */ \
3074 tcg_gen_atomic_fetch_xor_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3076 case 2: /* Fetch and or */ \
3077 tcg_gen_atomic_fetch_or_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3079 case 3: /* Fetch and 'and' */ \
3080 tcg_gen_atomic_fetch_and_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3082 case 8: /* Swap */ \
3083 tcg_gen_atomic_xchg_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3085 case 4: /* Fetch and max unsigned */ \
3086 case 5: /* Fetch and max signed */ \
3087 case 6: /* Fetch and min unsigned */ \
3088 case 7: /* Fetch and min signed */ \
3089 case 16: /* compare and swap not equal */ \
3090 case 24: /* Fetch and increment bounded */ \
3091 case 25: /* Fetch and increment equal */ \
3092 case 28: /* Fetch and decrement bounded */ \
3096 /* invoke data storage error handler */ \
3097 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \
3099 tcg_gen_##eop(cpu_gpr[rD(ctx->opcode)], t1); \
3100 tcg_temp_free_##tp(t0); \
3101 tcg_temp_free_##tp(t1); \
3102 tcg_temp_free(EA); \
3105 LD_ATOMIC(lwat
, DEF_MEMOP(MO_UL
), i32
, trunc_tl_i32
, extu_i32_tl
)
3106 #if defined(TARGET_PPC64)
3107 LD_ATOMIC(ldat
, DEF_MEMOP(MO_Q
), i64
, mov_i64
, mov_i64
)
3110 #define ST_ATOMIC(name, memop, tp, op) \
3111 static void gen_##name(DisasContext *ctx) \
3113 int len = MEMOP_GET_SIZE(memop); \
3114 uint32_t gpr_FC = FC(ctx->opcode); \
3115 TCGv EA = tcg_temp_local_new(); \
3118 gen_addr_register(ctx, EA); \
3120 gen_check_align(ctx, EA, len - 1); \
3122 t0 = tcg_temp_new_##tp(); \
3123 t1 = tcg_temp_new_##tp(); \
3124 tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \
3127 case 0: /* add and Store */ \
3128 tcg_gen_atomic_add_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3130 case 1: /* xor and Store */ \
3131 tcg_gen_atomic_xor_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3133 case 2: /* Or and Store */ \
3134 tcg_gen_atomic_or_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3136 case 3: /* 'and' and Store */ \
3137 tcg_gen_atomic_and_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3139 case 4: /* Store max unsigned */ \
3140 case 5: /* Store max signed */ \
3141 case 6: /* Store min unsigned */ \
3142 case 7: /* Store min signed */ \
3143 case 24: /* Store twin */ \
3147 /* invoke data storage error handler */ \
3148 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \
3150 tcg_temp_free_##tp(t0); \
3151 tcg_temp_free_##tp(t1); \
3152 tcg_temp_free(EA); \
3155 ST_ATOMIC(stwat
, DEF_MEMOP(MO_UL
), i32
, trunc_tl_i32
)
3156 #if defined(TARGET_PPC64)
3157 ST_ATOMIC(stdat
, DEF_MEMOP(MO_Q
), i64
, mov_i64
)
3160 #if defined(CONFIG_USER_ONLY)
3161 static void gen_conditional_store(DisasContext
*ctx
, TCGv EA
,
3164 TCGv t0
= tcg_temp_new();
3166 tcg_gen_st_tl(EA
, cpu_env
, offsetof(CPUPPCState
, reserve_ea
));
3167 tcg_gen_movi_tl(t0
, (MEMOP_GET_SIZE(memop
) << 5) | reg
);
3168 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUPPCState
, reserve_info
));
3170 gen_exception_err(ctx
, POWERPC_EXCP_STCX
, 0);
3173 static void gen_conditional_store(DisasContext
*ctx
, TCGv EA
,
3176 TCGLabel
*l1
= gen_new_label();
3177 TCGLabel
*l2
= gen_new_label();
3180 tcg_gen_brcond_tl(TCG_COND_NE
, EA
, cpu_reserve
, l1
);
3182 t0
= tcg_temp_new();
3183 tcg_gen_atomic_cmpxchg_tl(t0
, cpu_reserve
, cpu_reserve_val
,
3184 cpu_gpr
[reg
], ctx
->mem_idx
,
3185 DEF_MEMOP(memop
) | MO_ALIGN
);
3186 tcg_gen_setcond_tl(TCG_COND_EQ
, t0
, t0
, cpu_reserve_val
);
3187 tcg_gen_shli_tl(t0
, t0
, CRF_EQ_BIT
);
3188 tcg_gen_or_tl(t0
, t0
, cpu_so
);
3189 tcg_gen_trunc_tl_i32(cpu_crf
[0], t0
);
3195 /* Address mismatch implies failure. But we still need to provide the
3196 memory barrier semantics of the instruction. */
3197 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
3198 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
3201 tcg_gen_movi_tl(cpu_reserve
, -1);
3205 #define STCX(name, memop) \
3206 static void gen_##name(DisasContext *ctx) \
3209 int len = MEMOP_GET_SIZE(memop); \
3210 gen_set_access_type(ctx, ACCESS_RES); \
3211 t0 = tcg_temp_local_new(); \
3212 gen_addr_reg_index(ctx, t0); \
3214 gen_check_align(ctx, t0, (len) - 1); \
3216 gen_conditional_store(ctx, t0, rS(ctx->opcode), memop); \
3217 tcg_temp_free(t0); \
3220 STCX(stbcx_
, DEF_MEMOP(MO_UB
))
3221 STCX(sthcx_
, DEF_MEMOP(MO_UW
))
3222 STCX(stwcx_
, DEF_MEMOP(MO_UL
))
3224 #if defined(TARGET_PPC64)
3226 LARX(ldarx
, DEF_MEMOP(MO_Q
))
3228 STCX(stdcx_
, DEF_MEMOP(MO_Q
))
3231 static void gen_lqarx(DisasContext
*ctx
)
3234 int rd
= rD(ctx
->opcode
);
3237 if (unlikely((rd
& 1) || (rd
== rA(ctx
->opcode
)) ||
3238 (rd
== rB(ctx
->opcode
)))) {
3239 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3243 gen_set_access_type(ctx
, ACCESS_RES
);
3244 EA
= tcg_temp_local_new();
3245 gen_addr_reg_index(ctx
, EA
);
3246 gen_check_align(ctx
, EA
, 15);
3247 if (unlikely(ctx
->le_mode
)) {
3248 gpr1
= cpu_gpr
[rd
+1];
3252 gpr2
= cpu_gpr
[rd
+1];
3254 tcg_gen_qemu_ld_i64(gpr1
, EA
, ctx
->mem_idx
, DEF_MEMOP(MO_Q
));
3255 tcg_gen_mov_tl(cpu_reserve
, EA
);
3256 gen_addr_add(ctx
, EA
, EA
, 8);
3257 tcg_gen_qemu_ld_i64(gpr2
, EA
, ctx
->mem_idx
, DEF_MEMOP(MO_Q
));
3259 tcg_gen_st_tl(gpr1
, cpu_env
, offsetof(CPUPPCState
, reserve_val
));
3260 tcg_gen_st_tl(gpr2
, cpu_env
, offsetof(CPUPPCState
, reserve_val2
));
3265 static void gen_stqcx_(DisasContext
*ctx
)
3268 int reg
= rS(ctx
->opcode
);
3270 #if !defined(CONFIG_USER_ONLY)
3275 if (unlikely((rD(ctx
->opcode
) & 1))) {
3276 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3279 gen_set_access_type(ctx
, ACCESS_RES
);
3280 EA
= tcg_temp_local_new();
3281 gen_addr_reg_index(ctx
, EA
);
3283 gen_check_align(ctx
, EA
, (len
) - 1);
3286 #if defined(CONFIG_USER_ONLY)
3287 gen_conditional_store(ctx
, EA
, reg
, 16);
3289 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
3290 l1
= gen_new_label();
3291 tcg_gen_brcond_tl(TCG_COND_NE
, EA
, cpu_reserve
, l1
);
3292 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], CRF_EQ
);
3294 if (unlikely(ctx
->le_mode
)) {
3295 gpr1
= cpu_gpr
[reg
+ 1];
3296 gpr2
= cpu_gpr
[reg
];
3298 gpr1
= cpu_gpr
[reg
];
3299 gpr2
= cpu_gpr
[reg
+ 1];
3301 tcg_gen_qemu_st_tl(gpr1
, EA
, ctx
->mem_idx
, DEF_MEMOP(MO_Q
));
3302 gen_addr_add(ctx
, EA
, EA
, 8);
3303 tcg_gen_qemu_st_tl(gpr2
, EA
, ctx
->mem_idx
, DEF_MEMOP(MO_Q
));
3306 tcg_gen_movi_tl(cpu_reserve
, -1);
3311 #endif /* defined(TARGET_PPC64) */
3314 static void gen_sync(DisasContext
*ctx
)
3316 uint32_t l
= (ctx
->opcode
>> 21) & 3;
3319 * We may need to check for a pending TLB flush.
3321 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3323 * Additionally, this can only happen in kernel mode however so
3324 * check MSR_PR as well.
3326 if (((l
== 2) || !(ctx
->insns_flags
& PPC_64B
)) && !ctx
->pr
) {
3327 gen_check_tlb_flush(ctx
, true);
3329 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
3333 static void gen_wait(DisasContext
*ctx
)
3335 TCGv_i32 t0
= tcg_const_i32(1);
3336 tcg_gen_st_i32(t0
, cpu_env
,
3337 -offsetof(PowerPCCPU
, env
) + offsetof(CPUState
, halted
));
3338 tcg_temp_free_i32(t0
);
3339 /* Stop translation, as the CPU is supposed to sleep from now */
3340 gen_exception_nip(ctx
, EXCP_HLT
, ctx
->nip
);
3343 #if defined(TARGET_PPC64)
3344 static void gen_doze(DisasContext
*ctx
)
3346 #if defined(CONFIG_USER_ONLY)
3352 t
= tcg_const_i32(PPC_PM_DOZE
);
3353 gen_helper_pminsn(cpu_env
, t
);
3354 tcg_temp_free_i32(t
);
3355 gen_stop_exception(ctx
);
3356 #endif /* defined(CONFIG_USER_ONLY) */
3359 static void gen_nap(DisasContext
*ctx
)
3361 #if defined(CONFIG_USER_ONLY)
3367 t
= tcg_const_i32(PPC_PM_NAP
);
3368 gen_helper_pminsn(cpu_env
, t
);
3369 tcg_temp_free_i32(t
);
3370 gen_stop_exception(ctx
);
3371 #endif /* defined(CONFIG_USER_ONLY) */
3374 static void gen_stop(DisasContext
*ctx
)
3379 static void gen_sleep(DisasContext
*ctx
)
3381 #if defined(CONFIG_USER_ONLY)
3387 t
= tcg_const_i32(PPC_PM_SLEEP
);
3388 gen_helper_pminsn(cpu_env
, t
);
3389 tcg_temp_free_i32(t
);
3390 gen_stop_exception(ctx
);
3391 #endif /* defined(CONFIG_USER_ONLY) */
3394 static void gen_rvwinkle(DisasContext
*ctx
)
3396 #if defined(CONFIG_USER_ONLY)
3402 t
= tcg_const_i32(PPC_PM_RVWINKLE
);
3403 gen_helper_pminsn(cpu_env
, t
);
3404 tcg_temp_free_i32(t
);
3405 gen_stop_exception(ctx
);
3406 #endif /* defined(CONFIG_USER_ONLY) */
3408 #endif /* #if defined(TARGET_PPC64) */
3410 static inline void gen_update_cfar(DisasContext
*ctx
, target_ulong nip
)
3412 #if defined(TARGET_PPC64)
3414 tcg_gen_movi_tl(cpu_cfar
, nip
);
3418 static inline bool use_goto_tb(DisasContext
*ctx
, target_ulong dest
)
3420 if (unlikely(ctx
->singlestep_enabled
)) {
3424 #ifndef CONFIG_USER_ONLY
3425 return (ctx
->tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
3432 static inline void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
3434 if (NARROW_MODE(ctx
)) {
3435 dest
= (uint32_t) dest
;
3437 if (use_goto_tb(ctx
, dest
)) {
3439 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
3440 tcg_gen_exit_tb((uintptr_t)ctx
->tb
+ n
);
3442 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
3443 if (unlikely(ctx
->singlestep_enabled
)) {
3444 if ((ctx
->singlestep_enabled
&
3445 (CPU_BRANCH_STEP
| CPU_SINGLE_STEP
)) &&
3446 (ctx
->exception
== POWERPC_EXCP_BRANCH
||
3447 ctx
->exception
== POWERPC_EXCP_TRACE
)) {
3448 gen_exception_nip(ctx
, POWERPC_EXCP_TRACE
, dest
);
3450 if (ctx
->singlestep_enabled
& GDBSTUB_SINGLE_STEP
) {
3451 gen_debug_exception(ctx
);
3458 static inline void gen_setlr(DisasContext
*ctx
, target_ulong nip
)
3460 if (NARROW_MODE(ctx
)) {
3461 nip
= (uint32_t)nip
;
3463 tcg_gen_movi_tl(cpu_lr
, nip
);
3467 static void gen_b(DisasContext
*ctx
)
3469 target_ulong li
, target
;
3471 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3472 /* sign extend LI */
3473 li
= LI(ctx
->opcode
);
3474 li
= (li
^ 0x02000000) - 0x02000000;
3475 if (likely(AA(ctx
->opcode
) == 0)) {
3476 target
= ctx
->nip
+ li
- 4;
3480 if (LK(ctx
->opcode
)) {
3481 gen_setlr(ctx
, ctx
->nip
);
3483 gen_update_cfar(ctx
, ctx
->nip
- 4);
3484 gen_goto_tb(ctx
, 0, target
);
3492 static inline void gen_bcond(DisasContext
*ctx
, int type
)
3494 uint32_t bo
= BO(ctx
->opcode
);
3498 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3499 if (type
== BCOND_LR
|| type
== BCOND_CTR
|| type
== BCOND_TAR
) {
3500 target
= tcg_temp_local_new();
3501 if (type
== BCOND_CTR
)
3502 tcg_gen_mov_tl(target
, cpu_ctr
);
3503 else if (type
== BCOND_TAR
)
3504 gen_load_spr(target
, SPR_TAR
);
3506 tcg_gen_mov_tl(target
, cpu_lr
);
3508 TCGV_UNUSED(target
);
3510 if (LK(ctx
->opcode
))
3511 gen_setlr(ctx
, ctx
->nip
);
3512 l1
= gen_new_label();
3513 if ((bo
& 0x4) == 0) {
3514 /* Decrement and test CTR */
3515 TCGv temp
= tcg_temp_new();
3516 if (unlikely(type
== BCOND_CTR
)) {
3517 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3520 tcg_gen_subi_tl(cpu_ctr
, cpu_ctr
, 1);
3521 if (NARROW_MODE(ctx
)) {
3522 tcg_gen_ext32u_tl(temp
, cpu_ctr
);
3524 tcg_gen_mov_tl(temp
, cpu_ctr
);
3527 tcg_gen_brcondi_tl(TCG_COND_NE
, temp
, 0, l1
);
3529 tcg_gen_brcondi_tl(TCG_COND_EQ
, temp
, 0, l1
);
3531 tcg_temp_free(temp
);
3533 if ((bo
& 0x10) == 0) {
3535 uint32_t bi
= BI(ctx
->opcode
);
3536 uint32_t mask
= 0x08 >> (bi
& 0x03);
3537 TCGv_i32 temp
= tcg_temp_new_i32();
3540 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
3541 tcg_gen_brcondi_i32(TCG_COND_EQ
, temp
, 0, l1
);
3543 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
3544 tcg_gen_brcondi_i32(TCG_COND_NE
, temp
, 0, l1
);
3546 tcg_temp_free_i32(temp
);
3548 gen_update_cfar(ctx
, ctx
->nip
- 4);
3549 if (type
== BCOND_IM
) {
3550 target_ulong li
= (target_long
)((int16_t)(BD(ctx
->opcode
)));
3551 if (likely(AA(ctx
->opcode
) == 0)) {
3552 gen_goto_tb(ctx
, 0, ctx
->nip
+ li
- 4);
3554 gen_goto_tb(ctx
, 0, li
);
3556 if ((bo
& 0x14) != 0x14) {
3558 gen_goto_tb(ctx
, 1, ctx
->nip
);
3561 if (NARROW_MODE(ctx
)) {
3562 tcg_gen_andi_tl(cpu_nip
, target
, (uint32_t)~3);
3564 tcg_gen_andi_tl(cpu_nip
, target
, ~3);
3567 if ((bo
& 0x14) != 0x14) {
3569 gen_update_nip(ctx
, ctx
->nip
);
3573 if (type
== BCOND_LR
|| type
== BCOND_CTR
|| type
== BCOND_TAR
) {
3574 tcg_temp_free(target
);
3578 static void gen_bc(DisasContext
*ctx
)
3580 gen_bcond(ctx
, BCOND_IM
);
3583 static void gen_bcctr(DisasContext
*ctx
)
3585 gen_bcond(ctx
, BCOND_CTR
);
3588 static void gen_bclr(DisasContext
*ctx
)
3590 gen_bcond(ctx
, BCOND_LR
);
3593 static void gen_bctar(DisasContext
*ctx
)
3595 gen_bcond(ctx
, BCOND_TAR
);
3598 /*** Condition register logical ***/
3599 #define GEN_CRLOGIC(name, tcg_op, opc) \
3600 static void glue(gen_, name)(DisasContext *ctx) \
3605 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3606 t0 = tcg_temp_new_i32(); \
3608 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3610 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3612 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3613 t1 = tcg_temp_new_i32(); \
3614 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3616 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3618 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3620 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3621 tcg_op(t0, t0, t1); \
3622 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
3623 tcg_gen_andi_i32(t0, t0, bitmask); \
3624 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3625 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3626 tcg_temp_free_i32(t0); \
3627 tcg_temp_free_i32(t1); \
3631 GEN_CRLOGIC(crand
, tcg_gen_and_i32
, 0x08);
3633 GEN_CRLOGIC(crandc
, tcg_gen_andc_i32
, 0x04);
3635 GEN_CRLOGIC(creqv
, tcg_gen_eqv_i32
, 0x09);
3637 GEN_CRLOGIC(crnand
, tcg_gen_nand_i32
, 0x07);
3639 GEN_CRLOGIC(crnor
, tcg_gen_nor_i32
, 0x01);
3641 GEN_CRLOGIC(cror
, tcg_gen_or_i32
, 0x0E);
3643 GEN_CRLOGIC(crorc
, tcg_gen_orc_i32
, 0x0D);
3645 GEN_CRLOGIC(crxor
, tcg_gen_xor_i32
, 0x06);
3648 static void gen_mcrf(DisasContext
*ctx
)
3650 tcg_gen_mov_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_crf
[crfS(ctx
->opcode
)]);
3653 /*** System linkage ***/
3655 /* rfi (supervisor only) */
3656 static void gen_rfi(DisasContext
*ctx
)
3658 #if defined(CONFIG_USER_ONLY)
3661 /* This instruction doesn't exist anymore on 64-bit server
3662 * processors compliant with arch 2.x
3664 if (ctx
->insns_flags
& PPC_SEGMENT_64B
) {
3665 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3668 /* Restore CPU state */
3670 gen_update_cfar(ctx
, ctx
->nip
- 4);
3671 gen_helper_rfi(cpu_env
);
3672 gen_sync_exception(ctx
);
3676 #if defined(TARGET_PPC64)
3677 static void gen_rfid(DisasContext
*ctx
)
3679 #if defined(CONFIG_USER_ONLY)
3682 /* Restore CPU state */
3684 gen_update_cfar(ctx
, ctx
->nip
- 4);
3685 gen_helper_rfid(cpu_env
);
3686 gen_sync_exception(ctx
);
3690 static void gen_hrfid(DisasContext
*ctx
)
3692 #if defined(CONFIG_USER_ONLY)
3695 /* Restore CPU state */
3697 gen_helper_hrfid(cpu_env
);
3698 gen_sync_exception(ctx
);
3704 #if defined(CONFIG_USER_ONLY)
3705 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3707 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3709 static void gen_sc(DisasContext
*ctx
)
3713 lev
= (ctx
->opcode
>> 5) & 0x7F;
3714 gen_exception_err(ctx
, POWERPC_SYSCALL
, lev
);
3719 /* Check for unconditional traps (always or never) */
3720 static bool check_unconditional_trap(DisasContext
*ctx
)
3723 if (TO(ctx
->opcode
) == 0) {
3727 if (TO(ctx
->opcode
) == 31) {
3728 gen_exception_err(ctx
, POWERPC_EXCP_PROGRAM
, POWERPC_EXCP_TRAP
);
3735 static void gen_tw(DisasContext
*ctx
)
3739 if (check_unconditional_trap(ctx
)) {
3742 t0
= tcg_const_i32(TO(ctx
->opcode
));
3743 gen_helper_tw(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
3745 tcg_temp_free_i32(t0
);
3749 static void gen_twi(DisasContext
*ctx
)
3754 if (check_unconditional_trap(ctx
)) {
3757 t0
= tcg_const_tl(SIMM(ctx
->opcode
));
3758 t1
= tcg_const_i32(TO(ctx
->opcode
));
3759 gen_helper_tw(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
3761 tcg_temp_free_i32(t1
);
3764 #if defined(TARGET_PPC64)
3766 static void gen_td(DisasContext
*ctx
)
3770 if (check_unconditional_trap(ctx
)) {
3773 t0
= tcg_const_i32(TO(ctx
->opcode
));
3774 gen_helper_td(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
3776 tcg_temp_free_i32(t0
);
3780 static void gen_tdi(DisasContext
*ctx
)
3785 if (check_unconditional_trap(ctx
)) {
3788 t0
= tcg_const_tl(SIMM(ctx
->opcode
));
3789 t1
= tcg_const_i32(TO(ctx
->opcode
));
3790 gen_helper_td(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
3792 tcg_temp_free_i32(t1
);
3796 /*** Processor control ***/
3798 static void gen_read_xer(DisasContext
*ctx
, TCGv dst
)
3800 TCGv t0
= tcg_temp_new();
3801 TCGv t1
= tcg_temp_new();
3802 TCGv t2
= tcg_temp_new();
3803 tcg_gen_mov_tl(dst
, cpu_xer
);
3804 tcg_gen_shli_tl(t0
, cpu_so
, XER_SO
);
3805 tcg_gen_shli_tl(t1
, cpu_ov
, XER_OV
);
3806 tcg_gen_shli_tl(t2
, cpu_ca
, XER_CA
);
3807 tcg_gen_or_tl(t0
, t0
, t1
);
3808 tcg_gen_or_tl(dst
, dst
, t2
);
3809 tcg_gen_or_tl(dst
, dst
, t0
);
3810 if (is_isa300(ctx
)) {
3811 tcg_gen_shli_tl(t0
, cpu_ov32
, XER_OV32
);
3812 tcg_gen_or_tl(dst
, dst
, t0
);
3813 tcg_gen_shli_tl(t0
, cpu_ca32
, XER_CA32
);
3814 tcg_gen_or_tl(dst
, dst
, t0
);
3821 static void gen_write_xer(TCGv src
)
3823 /* Write all flags, while reading back check for isa300 */
3824 tcg_gen_andi_tl(cpu_xer
, src
,
3826 (1u << XER_OV
) | (1u << XER_OV32
) |
3827 (1u << XER_CA
) | (1u << XER_CA32
)));
3828 tcg_gen_extract_tl(cpu_ov32
, src
, XER_OV32
, 1);
3829 tcg_gen_extract_tl(cpu_ca32
, src
, XER_CA32
, 1);
3830 tcg_gen_extract_tl(cpu_so
, src
, XER_SO
, 1);
3831 tcg_gen_extract_tl(cpu_ov
, src
, XER_OV
, 1);
3832 tcg_gen_extract_tl(cpu_ca
, src
, XER_CA
, 1);
3836 static void gen_mcrxr(DisasContext
*ctx
)
3838 TCGv_i32 t0
= tcg_temp_new_i32();
3839 TCGv_i32 t1
= tcg_temp_new_i32();
3840 TCGv_i32 dst
= cpu_crf
[crfD(ctx
->opcode
)];
3842 tcg_gen_trunc_tl_i32(t0
, cpu_so
);
3843 tcg_gen_trunc_tl_i32(t1
, cpu_ov
);
3844 tcg_gen_trunc_tl_i32(dst
, cpu_ca
);
3845 tcg_gen_shli_i32(t0
, t0
, 3);
3846 tcg_gen_shli_i32(t1
, t1
, 2);
3847 tcg_gen_shli_i32(dst
, dst
, 1);
3848 tcg_gen_or_i32(dst
, dst
, t0
);
3849 tcg_gen_or_i32(dst
, dst
, t1
);
3850 tcg_temp_free_i32(t0
);
3851 tcg_temp_free_i32(t1
);
3853 tcg_gen_movi_tl(cpu_so
, 0);
3854 tcg_gen_movi_tl(cpu_ov
, 0);
3855 tcg_gen_movi_tl(cpu_ca
, 0);
3860 static void gen_mcrxrx(DisasContext
*ctx
)
3862 TCGv t0
= tcg_temp_new();
3863 TCGv t1
= tcg_temp_new();
3864 TCGv_i32 dst
= cpu_crf
[crfD(ctx
->opcode
)];
3866 /* copy OV and OV32 */
3867 tcg_gen_shli_tl(t0
, cpu_ov
, 1);
3868 tcg_gen_or_tl(t0
, t0
, cpu_ov32
);
3869 tcg_gen_shli_tl(t0
, t0
, 2);
3870 /* copy CA and CA32 */
3871 tcg_gen_shli_tl(t1
, cpu_ca
, 1);
3872 tcg_gen_or_tl(t1
, t1
, cpu_ca32
);
3873 tcg_gen_or_tl(t0
, t0
, t1
);
3874 tcg_gen_trunc_tl_i32(dst
, t0
);
3881 static void gen_mfcr(DisasContext
*ctx
)
3885 if (likely(ctx
->opcode
& 0x00100000)) {
3886 crm
= CRM(ctx
->opcode
);
3887 if (likely(crm
&& ((crm
& (crm
- 1)) == 0))) {
3889 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_crf
[7 - crn
]);
3890 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)],
3891 cpu_gpr
[rD(ctx
->opcode
)], crn
* 4);
3894 TCGv_i32 t0
= tcg_temp_new_i32();
3895 tcg_gen_mov_i32(t0
, cpu_crf
[0]);
3896 tcg_gen_shli_i32(t0
, t0
, 4);
3897 tcg_gen_or_i32(t0
, t0
, cpu_crf
[1]);
3898 tcg_gen_shli_i32(t0
, t0
, 4);
3899 tcg_gen_or_i32(t0
, t0
, cpu_crf
[2]);
3900 tcg_gen_shli_i32(t0
, t0
, 4);
3901 tcg_gen_or_i32(t0
, t0
, cpu_crf
[3]);
3902 tcg_gen_shli_i32(t0
, t0
, 4);
3903 tcg_gen_or_i32(t0
, t0
, cpu_crf
[4]);
3904 tcg_gen_shli_i32(t0
, t0
, 4);
3905 tcg_gen_or_i32(t0
, t0
, cpu_crf
[5]);
3906 tcg_gen_shli_i32(t0
, t0
, 4);
3907 tcg_gen_or_i32(t0
, t0
, cpu_crf
[6]);
3908 tcg_gen_shli_i32(t0
, t0
, 4);
3909 tcg_gen_or_i32(t0
, t0
, cpu_crf
[7]);
3910 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
3911 tcg_temp_free_i32(t0
);
3916 static void gen_mfmsr(DisasContext
*ctx
)
3919 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_msr
);
3922 static void spr_noaccess(DisasContext
*ctx
, int gprn
, int sprn
)
3925 sprn
= ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
3926 printf("ERROR: try to access SPR %d !\n", sprn
);
3929 #define SPR_NOACCESS (&spr_noaccess)
3932 static inline void gen_op_mfspr(DisasContext
*ctx
)
3934 void (*read_cb
)(DisasContext
*ctx
, int gprn
, int sprn
);
3935 uint32_t sprn
= SPR(ctx
->opcode
);
3937 #if defined(CONFIG_USER_ONLY)
3938 read_cb
= ctx
->spr_cb
[sprn
].uea_read
;
3941 read_cb
= ctx
->spr_cb
[sprn
].uea_read
;
3942 } else if (ctx
->hv
) {
3943 read_cb
= ctx
->spr_cb
[sprn
].hea_read
;
3945 read_cb
= ctx
->spr_cb
[sprn
].oea_read
;
3948 if (likely(read_cb
!= NULL
)) {
3949 if (likely(read_cb
!= SPR_NOACCESS
)) {
3950 (*read_cb
)(ctx
, rD(ctx
->opcode
), sprn
);
3952 /* Privilege exception */
3953 /* This is a hack to avoid warnings when running Linux:
3954 * this OS breaks the PowerPC virtualisation model,
3955 * allowing userland application to read the PVR
3957 if (sprn
!= SPR_PVR
) {
3958 fprintf(stderr
, "Trying to read privileged spr %d (0x%03x) at "
3959 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
3960 if (qemu_log_separate()) {
3961 qemu_log("Trying to read privileged spr %d (0x%03x) at "
3962 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
3965 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3968 /* ISA 2.07 defines these as no-ops */
3969 if ((ctx
->insns_flags2
& PPC2_ISA207S
) &&
3970 (sprn
>= 808 && sprn
<= 811)) {
3975 fprintf(stderr
, "Trying to read invalid spr %d (0x%03x) at "
3976 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
3977 if (qemu_log_separate()) {
3978 qemu_log("Trying to read invalid spr %d (0x%03x) at "
3979 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
3982 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
3983 * it can generate a priv, a hv emu or a no-op
3987 gen_priv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
3990 if (ctx
->pr
|| sprn
== 0 || sprn
== 4 || sprn
== 5 || sprn
== 6) {
3991 gen_hvpriv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
3997 static void gen_mfspr(DisasContext
*ctx
)
4003 static void gen_mftb(DisasContext
*ctx
)
4009 static void gen_mtcrf(DisasContext
*ctx
)
4013 crm
= CRM(ctx
->opcode
);
4014 if (likely((ctx
->opcode
& 0x00100000))) {
4015 if (crm
&& ((crm
& (crm
- 1)) == 0)) {
4016 TCGv_i32 temp
= tcg_temp_new_i32();
4018 tcg_gen_trunc_tl_i32(temp
, cpu_gpr
[rS(ctx
->opcode
)]);
4019 tcg_gen_shri_i32(temp
, temp
, crn
* 4);
4020 tcg_gen_andi_i32(cpu_crf
[7 - crn
], temp
, 0xf);
4021 tcg_temp_free_i32(temp
);
4024 TCGv_i32 temp
= tcg_temp_new_i32();
4025 tcg_gen_trunc_tl_i32(temp
, cpu_gpr
[rS(ctx
->opcode
)]);
4026 for (crn
= 0 ; crn
< 8 ; crn
++) {
4027 if (crm
& (1 << crn
)) {
4028 tcg_gen_shri_i32(cpu_crf
[7 - crn
], temp
, crn
* 4);
4029 tcg_gen_andi_i32(cpu_crf
[7 - crn
], cpu_crf
[7 - crn
], 0xf);
4032 tcg_temp_free_i32(temp
);
4037 #if defined(TARGET_PPC64)
4038 static void gen_mtmsrd(DisasContext
*ctx
)
4042 #if !defined(CONFIG_USER_ONLY)
4043 if (ctx
->opcode
& 0x00010000) {
4044 /* Special form that does not need any synchronisation */
4045 TCGv t0
= tcg_temp_new();
4046 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1 << MSR_RI
) | (1 << MSR_EE
));
4047 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(target_ulong
)((1 << MSR_RI
) | (1 << MSR_EE
)));
4048 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
4051 /* XXX: we need to update nip before the store
4052 * if we enter power saving mode, we will exit the loop
4053 * directly from ppc_store_msr
4055 gen_update_nip(ctx
, ctx
->nip
);
4056 gen_helper_store_msr(cpu_env
, cpu_gpr
[rS(ctx
->opcode
)]);
4057 /* Must stop the translation as machine state (may have) changed */
4058 /* Note that mtmsr is not always defined as context-synchronizing */
4059 gen_stop_exception(ctx
);
4061 #endif /* !defined(CONFIG_USER_ONLY) */
4063 #endif /* defined(TARGET_PPC64) */
4065 static void gen_mtmsr(DisasContext
*ctx
)
4069 #if !defined(CONFIG_USER_ONLY)
4070 if (ctx
->opcode
& 0x00010000) {
4071 /* Special form that does not need any synchronisation */
4072 TCGv t0
= tcg_temp_new();
4073 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1 << MSR_RI
) | (1 << MSR_EE
));
4074 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(target_ulong
)((1 << MSR_RI
) | (1 << MSR_EE
)));
4075 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
4078 TCGv msr
= tcg_temp_new();
4080 /* XXX: we need to update nip before the store
4081 * if we enter power saving mode, we will exit the loop
4082 * directly from ppc_store_msr
4084 gen_update_nip(ctx
, ctx
->nip
);
4085 #if defined(TARGET_PPC64)
4086 tcg_gen_deposit_tl(msr
, cpu_msr
, cpu_gpr
[rS(ctx
->opcode
)], 0, 32);
4088 tcg_gen_mov_tl(msr
, cpu_gpr
[rS(ctx
->opcode
)]);
4090 gen_helper_store_msr(cpu_env
, msr
);
4092 /* Must stop the translation as machine state (may have) changed */
4093 /* Note that mtmsr is not always defined as context-synchronizing */
4094 gen_stop_exception(ctx
);
4100 static void gen_mtspr(DisasContext
*ctx
)
4102 void (*write_cb
)(DisasContext
*ctx
, int sprn
, int gprn
);
4103 uint32_t sprn
= SPR(ctx
->opcode
);
4105 #if defined(CONFIG_USER_ONLY)
4106 write_cb
= ctx
->spr_cb
[sprn
].uea_write
;
4109 write_cb
= ctx
->spr_cb
[sprn
].uea_write
;
4110 } else if (ctx
->hv
) {
4111 write_cb
= ctx
->spr_cb
[sprn
].hea_write
;
4113 write_cb
= ctx
->spr_cb
[sprn
].oea_write
;
4116 if (likely(write_cb
!= NULL
)) {
4117 if (likely(write_cb
!= SPR_NOACCESS
)) {
4118 (*write_cb
)(ctx
, sprn
, rS(ctx
->opcode
));
4120 /* Privilege exception */
4121 fprintf(stderr
, "Trying to write privileged spr %d (0x%03x) at "
4122 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4123 if (qemu_log_separate()) {
4124 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4125 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4127 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4130 /* ISA 2.07 defines these as no-ops */
4131 if ((ctx
->insns_flags2
& PPC2_ISA207S
) &&
4132 (sprn
>= 808 && sprn
<= 811)) {
4138 if (qemu_log_separate()) {
4139 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4140 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4142 fprintf(stderr
, "Trying to write invalid spr %d (0x%03x) at "
4143 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4146 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
4147 * it can generate a priv, a hv emu or a no-op
4151 gen_priv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
4154 if (ctx
->pr
|| sprn
== 0) {
4155 gen_hvpriv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
4161 #if defined(TARGET_PPC64)
4163 static void gen_setb(DisasContext
*ctx
)
4165 TCGv_i32 t0
= tcg_temp_new_i32();
4166 TCGv_i32 t8
= tcg_temp_new_i32();
4167 TCGv_i32 tm1
= tcg_temp_new_i32();
4168 int crf
= crfS(ctx
->opcode
);
4170 tcg_gen_setcondi_i32(TCG_COND_GEU
, t0
, cpu_crf
[crf
], 4);
4171 tcg_gen_movi_i32(t8
, 8);
4172 tcg_gen_movi_i32(tm1
, -1);
4173 tcg_gen_movcond_i32(TCG_COND_GEU
, t0
, cpu_crf
[crf
], t8
, tm1
, t0
);
4174 tcg_gen_ext_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4176 tcg_temp_free_i32(t0
);
4177 tcg_temp_free_i32(t8
);
4178 tcg_temp_free_i32(tm1
);
4182 /*** Cache management ***/
4185 static void gen_dcbf(DisasContext
*ctx
)
4187 /* XXX: specification says this is treated as a load by the MMU */
4189 gen_set_access_type(ctx
, ACCESS_CACHE
);
4190 t0
= tcg_temp_new();
4191 gen_addr_reg_index(ctx
, t0
);
4192 gen_qemu_ld8u(ctx
, t0
, t0
);
4196 /* dcbi (Supervisor only) */
4197 static void gen_dcbi(DisasContext
*ctx
)
4199 #if defined(CONFIG_USER_ONLY)
4205 EA
= tcg_temp_new();
4206 gen_set_access_type(ctx
, ACCESS_CACHE
);
4207 gen_addr_reg_index(ctx
, EA
);
4208 val
= tcg_temp_new();
4209 /* XXX: specification says this should be treated as a store by the MMU */
4210 gen_qemu_ld8u(ctx
, val
, EA
);
4211 gen_qemu_st8(ctx
, val
, EA
);
4214 #endif /* defined(CONFIG_USER_ONLY) */
4218 static void gen_dcbst(DisasContext
*ctx
)
4220 /* XXX: specification say this is treated as a load by the MMU */
4222 gen_set_access_type(ctx
, ACCESS_CACHE
);
4223 t0
= tcg_temp_new();
4224 gen_addr_reg_index(ctx
, t0
);
4225 gen_qemu_ld8u(ctx
, t0
, t0
);
4230 static void gen_dcbt(DisasContext
*ctx
)
4232 /* interpreted as no-op */
4233 /* XXX: specification say this is treated as a load by the MMU
4234 * but does not generate any exception
4239 static void gen_dcbtst(DisasContext
*ctx
)
4241 /* interpreted as no-op */
4242 /* XXX: specification say this is treated as a load by the MMU
4243 * but does not generate any exception
4248 static void gen_dcbtls(DisasContext
*ctx
)
4250 /* Always fails locking the cache */
4251 TCGv t0
= tcg_temp_new();
4252 gen_load_spr(t0
, SPR_Exxx_L1CSR0
);
4253 tcg_gen_ori_tl(t0
, t0
, L1CSR0_CUL
);
4254 gen_store_spr(SPR_Exxx_L1CSR0
, t0
);
4259 static void gen_dcbz(DisasContext
*ctx
)
4264 gen_set_access_type(ctx
, ACCESS_CACHE
);
4265 tcgv_addr
= tcg_temp_new();
4266 tcgv_op
= tcg_const_i32(ctx
->opcode
& 0x03FF000);
4267 gen_addr_reg_index(ctx
, tcgv_addr
);
4268 gen_helper_dcbz(cpu_env
, tcgv_addr
, tcgv_op
);
4269 tcg_temp_free(tcgv_addr
);
4270 tcg_temp_free_i32(tcgv_op
);
4274 static void gen_dst(DisasContext
*ctx
)
4276 if (rA(ctx
->opcode
) == 0) {
4277 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
4279 /* interpreted as no-op */
4284 static void gen_dstst(DisasContext
*ctx
)
4286 if (rA(ctx
->opcode
) == 0) {
4287 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
4289 /* interpreted as no-op */
4295 static void gen_dss(DisasContext
*ctx
)
4297 /* interpreted as no-op */
4301 static void gen_icbi(DisasContext
*ctx
)
4304 gen_set_access_type(ctx
, ACCESS_CACHE
);
4305 t0
= tcg_temp_new();
4306 gen_addr_reg_index(ctx
, t0
);
4307 gen_helper_icbi(cpu_env
, t0
);
4313 static void gen_dcba(DisasContext
*ctx
)
4315 /* interpreted as no-op */
4316 /* XXX: specification say this is treated as a store by the MMU
4317 * but does not generate any exception
4321 /*** Segment register manipulation ***/
4322 /* Supervisor only: */
4325 static void gen_mfsr(DisasContext
*ctx
)
4327 #if defined(CONFIG_USER_ONLY)
4333 t0
= tcg_const_tl(SR(ctx
->opcode
));
4334 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4336 #endif /* defined(CONFIG_USER_ONLY) */
4340 static void gen_mfsrin(DisasContext
*ctx
)
4342 #if defined(CONFIG_USER_ONLY)
4348 t0
= tcg_temp_new();
4349 tcg_gen_extract_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28, 4);
4350 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4352 #endif /* defined(CONFIG_USER_ONLY) */
4356 static void gen_mtsr(DisasContext
*ctx
)
4358 #if defined(CONFIG_USER_ONLY)
4364 t0
= tcg_const_tl(SR(ctx
->opcode
));
4365 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4367 #endif /* defined(CONFIG_USER_ONLY) */
4371 static void gen_mtsrin(DisasContext
*ctx
)
4373 #if defined(CONFIG_USER_ONLY)
4379 t0
= tcg_temp_new();
4380 tcg_gen_extract_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28, 4);
4381 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rD(ctx
->opcode
)]);
4383 #endif /* defined(CONFIG_USER_ONLY) */
4386 #if defined(TARGET_PPC64)
4387 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4390 static void gen_mfsr_64b(DisasContext
*ctx
)
4392 #if defined(CONFIG_USER_ONLY)
4398 t0
= tcg_const_tl(SR(ctx
->opcode
));
4399 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4401 #endif /* defined(CONFIG_USER_ONLY) */
4405 static void gen_mfsrin_64b(DisasContext
*ctx
)
4407 #if defined(CONFIG_USER_ONLY)
4413 t0
= tcg_temp_new();
4414 tcg_gen_extract_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28, 4);
4415 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4417 #endif /* defined(CONFIG_USER_ONLY) */
4421 static void gen_mtsr_64b(DisasContext
*ctx
)
4423 #if defined(CONFIG_USER_ONLY)
4429 t0
= tcg_const_tl(SR(ctx
->opcode
));
4430 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4432 #endif /* defined(CONFIG_USER_ONLY) */
4436 static void gen_mtsrin_64b(DisasContext
*ctx
)
4438 #if defined(CONFIG_USER_ONLY)
4444 t0
= tcg_temp_new();
4445 tcg_gen_extract_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28, 4);
4446 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4448 #endif /* defined(CONFIG_USER_ONLY) */
4452 static void gen_slbmte(DisasContext
*ctx
)
4454 #if defined(CONFIG_USER_ONLY)
4459 gen_helper_store_slb(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)],
4460 cpu_gpr
[rS(ctx
->opcode
)]);
4461 #endif /* defined(CONFIG_USER_ONLY) */
4464 static void gen_slbmfee(DisasContext
*ctx
)
4466 #if defined(CONFIG_USER_ONLY)
4471 gen_helper_load_slb_esid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4472 cpu_gpr
[rB(ctx
->opcode
)]);
4473 #endif /* defined(CONFIG_USER_ONLY) */
4476 static void gen_slbmfev(DisasContext
*ctx
)
4478 #if defined(CONFIG_USER_ONLY)
4483 gen_helper_load_slb_vsid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4484 cpu_gpr
[rB(ctx
->opcode
)]);
4485 #endif /* defined(CONFIG_USER_ONLY) */
4488 static void gen_slbfee_(DisasContext
*ctx
)
4490 #if defined(CONFIG_USER_ONLY)
4491 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4495 if (unlikely(ctx
->pr
)) {
4496 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4499 gen_helper_find_slb_vsid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4500 cpu_gpr
[rB(ctx
->opcode
)]);
4501 l1
= gen_new_label();
4502 l2
= gen_new_label();
4503 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
4504 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rS(ctx
->opcode
)], -1, l1
);
4505 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], CRF_EQ
);
4508 tcg_gen_movi_tl(cpu_gpr
[rS(ctx
->opcode
)], 0);
4512 #endif /* defined(TARGET_PPC64) */
4514 /*** Lookaside buffer management ***/
4515 /* Optional & supervisor only: */
4518 static void gen_tlbia(DisasContext
*ctx
)
4520 #if defined(CONFIG_USER_ONLY)
4525 gen_helper_tlbia(cpu_env
);
4526 #endif /* defined(CONFIG_USER_ONLY) */
4530 static void gen_tlbiel(DisasContext
*ctx
)
4532 #if defined(CONFIG_USER_ONLY)
4537 gen_helper_tlbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4538 #endif /* defined(CONFIG_USER_ONLY) */
4542 static void gen_tlbie(DisasContext
*ctx
)
4544 #if defined(CONFIG_USER_ONLY)
4550 CHK_SV
; /* If gtse is set then tblie is supervisor privileged */
4552 CHK_HV
; /* Else hypervisor privileged */
4555 if (NARROW_MODE(ctx
)) {
4556 TCGv t0
= tcg_temp_new();
4557 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)]);
4558 gen_helper_tlbie(cpu_env
, t0
);
4561 gen_helper_tlbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4563 t1
= tcg_temp_new_i32();
4564 tcg_gen_ld_i32(t1
, cpu_env
, offsetof(CPUPPCState
, tlb_need_flush
));
4565 tcg_gen_ori_i32(t1
, t1
, TLB_NEED_GLOBAL_FLUSH
);
4566 tcg_gen_st_i32(t1
, cpu_env
, offsetof(CPUPPCState
, tlb_need_flush
));
4567 tcg_temp_free_i32(t1
);
4568 #endif /* defined(CONFIG_USER_ONLY) */
4572 static void gen_tlbsync(DisasContext
*ctx
)
4574 #if defined(CONFIG_USER_ONLY)
4579 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */
4580 if (ctx
->insns_flags
& PPC_BOOKE
) {
4581 gen_check_tlb_flush(ctx
, true);
4583 #endif /* defined(CONFIG_USER_ONLY) */
4586 #if defined(TARGET_PPC64)
4588 static void gen_slbia(DisasContext
*ctx
)
4590 #if defined(CONFIG_USER_ONLY)
4595 gen_helper_slbia(cpu_env
);
4596 #endif /* defined(CONFIG_USER_ONLY) */
4600 static void gen_slbie(DisasContext
*ctx
)
4602 #if defined(CONFIG_USER_ONLY)
4607 gen_helper_slbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4608 #endif /* defined(CONFIG_USER_ONLY) */
4612 static void gen_slbieg(DisasContext
*ctx
)
4614 #if defined(CONFIG_USER_ONLY)
4619 gen_helper_slbieg(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4620 #endif /* defined(CONFIG_USER_ONLY) */
4624 static void gen_slbsync(DisasContext
*ctx
)
4626 #if defined(CONFIG_USER_ONLY)
4630 gen_check_tlb_flush(ctx
, true);
4631 #endif /* defined(CONFIG_USER_ONLY) */
4634 #endif /* defined(TARGET_PPC64) */
4636 /*** External control ***/
4640 static void gen_eciwx(DisasContext
*ctx
)
4643 /* Should check EAR[E] ! */
4644 gen_set_access_type(ctx
, ACCESS_EXT
);
4645 t0
= tcg_temp_new();
4646 gen_addr_reg_index(ctx
, t0
);
4647 gen_check_align(ctx
, t0
, 0x03);
4648 gen_qemu_ld32u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], t0
);
4653 static void gen_ecowx(DisasContext
*ctx
)
4656 /* Should check EAR[E] ! */
4657 gen_set_access_type(ctx
, ACCESS_EXT
);
4658 t0
= tcg_temp_new();
4659 gen_addr_reg_index(ctx
, t0
);
4660 gen_check_align(ctx
, t0
, 0x03);
4661 gen_qemu_st32(ctx
, cpu_gpr
[rD(ctx
->opcode
)], t0
);
4665 /* PowerPC 601 specific instructions */
4668 static void gen_abs(DisasContext
*ctx
)
4670 TCGLabel
*l1
= gen_new_label();
4671 TCGLabel
*l2
= gen_new_label();
4672 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
4673 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4676 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4678 if (unlikely(Rc(ctx
->opcode
) != 0))
4679 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4683 static void gen_abso(DisasContext
*ctx
)
4685 TCGLabel
*l1
= gen_new_label();
4686 TCGLabel
*l2
= gen_new_label();
4687 TCGLabel
*l3
= gen_new_label();
4688 /* Start with XER OV disabled, the most likely case */
4689 tcg_gen_movi_tl(cpu_ov
, 0);
4690 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rA(ctx
->opcode
)], 0, l2
);
4691 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[rA(ctx
->opcode
)], 0x80000000, l1
);
4692 tcg_gen_movi_tl(cpu_ov
, 1);
4693 tcg_gen_movi_tl(cpu_so
, 1);
4696 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4699 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4701 if (unlikely(Rc(ctx
->opcode
) != 0))
4702 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4706 static void gen_clcs(DisasContext
*ctx
)
4708 TCGv_i32 t0
= tcg_const_i32(rA(ctx
->opcode
));
4709 gen_helper_clcs(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4710 tcg_temp_free_i32(t0
);
4711 /* Rc=1 sets CR0 to an undefined state */
4715 static void gen_div(DisasContext
*ctx
)
4717 gen_helper_div(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
4718 cpu_gpr
[rB(ctx
->opcode
)]);
4719 if (unlikely(Rc(ctx
->opcode
) != 0))
4720 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4724 static void gen_divo(DisasContext
*ctx
)
4726 gen_helper_divo(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
4727 cpu_gpr
[rB(ctx
->opcode
)]);
4728 if (unlikely(Rc(ctx
->opcode
) != 0))
4729 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4733 static void gen_divs(DisasContext
*ctx
)
4735 gen_helper_divs(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
4736 cpu_gpr
[rB(ctx
->opcode
)]);
4737 if (unlikely(Rc(ctx
->opcode
) != 0))
4738 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4741 /* divso - divso. */
4742 static void gen_divso(DisasContext
*ctx
)
4744 gen_helper_divso(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
4745 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4746 if (unlikely(Rc(ctx
->opcode
) != 0))
4747 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4751 static void gen_doz(DisasContext
*ctx
)
4753 TCGLabel
*l1
= gen_new_label();
4754 TCGLabel
*l2
= gen_new_label();
4755 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], l1
);
4756 tcg_gen_sub_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4759 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
4761 if (unlikely(Rc(ctx
->opcode
) != 0))
4762 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4766 static void gen_dozo(DisasContext
*ctx
)
4768 TCGLabel
*l1
= gen_new_label();
4769 TCGLabel
*l2
= gen_new_label();
4770 TCGv t0
= tcg_temp_new();
4771 TCGv t1
= tcg_temp_new();
4772 TCGv t2
= tcg_temp_new();
4773 /* Start with XER OV disabled, the most likely case */
4774 tcg_gen_movi_tl(cpu_ov
, 0);
4775 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], l1
);
4776 tcg_gen_sub_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4777 tcg_gen_xor_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4778 tcg_gen_xor_tl(t2
, cpu_gpr
[rA(ctx
->opcode
)], t0
);
4779 tcg_gen_andc_tl(t1
, t1
, t2
);
4780 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4781 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
4782 tcg_gen_movi_tl(cpu_ov
, 1);
4783 tcg_gen_movi_tl(cpu_so
, 1);
4786 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
4791 if (unlikely(Rc(ctx
->opcode
) != 0))
4792 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4796 static void gen_dozi(DisasContext
*ctx
)
4798 target_long simm
= SIMM(ctx
->opcode
);
4799 TCGLabel
*l1
= gen_new_label();
4800 TCGLabel
*l2
= gen_new_label();
4801 tcg_gen_brcondi_tl(TCG_COND_LT
, cpu_gpr
[rA(ctx
->opcode
)], simm
, l1
);
4802 tcg_gen_subfi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
, cpu_gpr
[rA(ctx
->opcode
)]);
4805 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
4807 if (unlikely(Rc(ctx
->opcode
) != 0))
4808 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4811 /* lscbx - lscbx. */
4812 static void gen_lscbx(DisasContext
*ctx
)
4814 TCGv t0
= tcg_temp_new();
4815 TCGv_i32 t1
= tcg_const_i32(rD(ctx
->opcode
));
4816 TCGv_i32 t2
= tcg_const_i32(rA(ctx
->opcode
));
4817 TCGv_i32 t3
= tcg_const_i32(rB(ctx
->opcode
));
4819 gen_addr_reg_index(ctx
, t0
);
4820 gen_helper_lscbx(t0
, cpu_env
, t0
, t1
, t2
, t3
);
4821 tcg_temp_free_i32(t1
);
4822 tcg_temp_free_i32(t2
);
4823 tcg_temp_free_i32(t3
);
4824 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~0x7F);
4825 tcg_gen_or_tl(cpu_xer
, cpu_xer
, t0
);
4826 if (unlikely(Rc(ctx
->opcode
) != 0))
4827 gen_set_Rc0(ctx
, t0
);
4831 /* maskg - maskg. */
4832 static void gen_maskg(DisasContext
*ctx
)
4834 TCGLabel
*l1
= gen_new_label();
4835 TCGv t0
= tcg_temp_new();
4836 TCGv t1
= tcg_temp_new();
4837 TCGv t2
= tcg_temp_new();
4838 TCGv t3
= tcg_temp_new();
4839 tcg_gen_movi_tl(t3
, 0xFFFFFFFF);
4840 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4841 tcg_gen_andi_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 0x1F);
4842 tcg_gen_addi_tl(t2
, t0
, 1);
4843 tcg_gen_shr_tl(t2
, t3
, t2
);
4844 tcg_gen_shr_tl(t3
, t3
, t1
);
4845 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], t2
, t3
);
4846 tcg_gen_brcond_tl(TCG_COND_GE
, t0
, t1
, l1
);
4847 tcg_gen_neg_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4853 if (unlikely(Rc(ctx
->opcode
) != 0))
4854 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4857 /* maskir - maskir. */
4858 static void gen_maskir(DisasContext
*ctx
)
4860 TCGv t0
= tcg_temp_new();
4861 TCGv t1
= tcg_temp_new();
4862 tcg_gen_and_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4863 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4864 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4867 if (unlikely(Rc(ctx
->opcode
) != 0))
4868 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4872 static void gen_mul(DisasContext
*ctx
)
4874 TCGv_i64 t0
= tcg_temp_new_i64();
4875 TCGv_i64 t1
= tcg_temp_new_i64();
4876 TCGv t2
= tcg_temp_new();
4877 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
4878 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
4879 tcg_gen_mul_i64(t0
, t0
, t1
);
4880 tcg_gen_trunc_i64_tl(t2
, t0
);
4881 gen_store_spr(SPR_MQ
, t2
);
4882 tcg_gen_shri_i64(t1
, t0
, 32);
4883 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
4884 tcg_temp_free_i64(t0
);
4885 tcg_temp_free_i64(t1
);
4887 if (unlikely(Rc(ctx
->opcode
) != 0))
4888 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4892 static void gen_mulo(DisasContext
*ctx
)
4894 TCGLabel
*l1
= gen_new_label();
4895 TCGv_i64 t0
= tcg_temp_new_i64();
4896 TCGv_i64 t1
= tcg_temp_new_i64();
4897 TCGv t2
= tcg_temp_new();
4898 /* Start with XER OV disabled, the most likely case */
4899 tcg_gen_movi_tl(cpu_ov
, 0);
4900 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
4901 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
4902 tcg_gen_mul_i64(t0
, t0
, t1
);
4903 tcg_gen_trunc_i64_tl(t2
, t0
);
4904 gen_store_spr(SPR_MQ
, t2
);
4905 tcg_gen_shri_i64(t1
, t0
, 32);
4906 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
4907 tcg_gen_ext32s_i64(t1
, t0
);
4908 tcg_gen_brcond_i64(TCG_COND_EQ
, t0
, t1
, l1
);
4909 tcg_gen_movi_tl(cpu_ov
, 1);
4910 tcg_gen_movi_tl(cpu_so
, 1);
4912 tcg_temp_free_i64(t0
);
4913 tcg_temp_free_i64(t1
);
4915 if (unlikely(Rc(ctx
->opcode
) != 0))
4916 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4920 static void gen_nabs(DisasContext
*ctx
)
4922 TCGLabel
*l1
= gen_new_label();
4923 TCGLabel
*l2
= gen_new_label();
4924 tcg_gen_brcondi_tl(TCG_COND_GT
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
4925 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4928 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4930 if (unlikely(Rc(ctx
->opcode
) != 0))
4931 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4934 /* nabso - nabso. */
4935 static void gen_nabso(DisasContext
*ctx
)
4937 TCGLabel
*l1
= gen_new_label();
4938 TCGLabel
*l2
= gen_new_label();
4939 tcg_gen_brcondi_tl(TCG_COND_GT
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
4940 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4943 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4945 /* nabs never overflows */
4946 tcg_gen_movi_tl(cpu_ov
, 0);
4947 if (unlikely(Rc(ctx
->opcode
) != 0))
4948 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4952 static void gen_rlmi(DisasContext
*ctx
)
4954 uint32_t mb
= MB(ctx
->opcode
);
4955 uint32_t me
= ME(ctx
->opcode
);
4956 TCGv t0
= tcg_temp_new();
4957 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4958 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
4959 tcg_gen_andi_tl(t0
, t0
, MASK(mb
, me
));
4960 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], ~MASK(mb
, me
));
4961 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], t0
);
4963 if (unlikely(Rc(ctx
->opcode
) != 0))
4964 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4968 static void gen_rrib(DisasContext
*ctx
)
4970 TCGv t0
= tcg_temp_new();
4971 TCGv t1
= tcg_temp_new();
4972 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4973 tcg_gen_movi_tl(t1
, 0x80000000);
4974 tcg_gen_shr_tl(t1
, t1
, t0
);
4975 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
4976 tcg_gen_and_tl(t0
, t0
, t1
);
4977 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], t1
);
4978 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4981 if (unlikely(Rc(ctx
->opcode
) != 0))
4982 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4986 static void gen_sle(DisasContext
*ctx
)
4988 TCGv t0
= tcg_temp_new();
4989 TCGv t1
= tcg_temp_new();
4990 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4991 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4992 tcg_gen_subfi_tl(t1
, 32, t1
);
4993 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4994 tcg_gen_or_tl(t1
, t0
, t1
);
4995 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
4996 gen_store_spr(SPR_MQ
, t1
);
4999 if (unlikely(Rc(ctx
->opcode
) != 0))
5000 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5004 static void gen_sleq(DisasContext
*ctx
)
5006 TCGv t0
= tcg_temp_new();
5007 TCGv t1
= tcg_temp_new();
5008 TCGv t2
= tcg_temp_new();
5009 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5010 tcg_gen_movi_tl(t2
, 0xFFFFFFFF);
5011 tcg_gen_shl_tl(t2
, t2
, t0
);
5012 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5013 gen_load_spr(t1
, SPR_MQ
);
5014 gen_store_spr(SPR_MQ
, t0
);
5015 tcg_gen_and_tl(t0
, t0
, t2
);
5016 tcg_gen_andc_tl(t1
, t1
, t2
);
5017 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5021 if (unlikely(Rc(ctx
->opcode
) != 0))
5022 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5026 static void gen_sliq(DisasContext
*ctx
)
5028 int sh
= SH(ctx
->opcode
);
5029 TCGv t0
= tcg_temp_new();
5030 TCGv t1
= tcg_temp_new();
5031 tcg_gen_shli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5032 tcg_gen_shri_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
5033 tcg_gen_or_tl(t1
, t0
, t1
);
5034 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5035 gen_store_spr(SPR_MQ
, t1
);
5038 if (unlikely(Rc(ctx
->opcode
) != 0))
5039 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5042 /* slliq - slliq. */
5043 static void gen_slliq(DisasContext
*ctx
)
5045 int sh
= SH(ctx
->opcode
);
5046 TCGv t0
= tcg_temp_new();
5047 TCGv t1
= tcg_temp_new();
5048 tcg_gen_rotli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5049 gen_load_spr(t1
, SPR_MQ
);
5050 gen_store_spr(SPR_MQ
, t0
);
5051 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
<< sh
));
5052 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
<< sh
));
5053 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5056 if (unlikely(Rc(ctx
->opcode
) != 0))
5057 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5061 static void gen_sllq(DisasContext
*ctx
)
5063 TCGLabel
*l1
= gen_new_label();
5064 TCGLabel
*l2
= gen_new_label();
5065 TCGv t0
= tcg_temp_local_new();
5066 TCGv t1
= tcg_temp_local_new();
5067 TCGv t2
= tcg_temp_local_new();
5068 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5069 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5070 tcg_gen_shl_tl(t1
, t1
, t2
);
5071 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5072 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5073 gen_load_spr(t0
, SPR_MQ
);
5074 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5077 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5078 gen_load_spr(t2
, SPR_MQ
);
5079 tcg_gen_andc_tl(t1
, t2
, t1
);
5080 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5085 if (unlikely(Rc(ctx
->opcode
) != 0))
5086 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5090 static void gen_slq(DisasContext
*ctx
)
5092 TCGLabel
*l1
= gen_new_label();
5093 TCGv t0
= tcg_temp_new();
5094 TCGv t1
= tcg_temp_new();
5095 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5096 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5097 tcg_gen_subfi_tl(t1
, 32, t1
);
5098 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5099 tcg_gen_or_tl(t1
, t0
, t1
);
5100 gen_store_spr(SPR_MQ
, t1
);
5101 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5102 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5103 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
5104 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
5108 if (unlikely(Rc(ctx
->opcode
) != 0))
5109 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5112 /* sraiq - sraiq. */
5113 static void gen_sraiq(DisasContext
*ctx
)
5115 int sh
= SH(ctx
->opcode
);
5116 TCGLabel
*l1
= gen_new_label();
5117 TCGv t0
= tcg_temp_new();
5118 TCGv t1
= tcg_temp_new();
5119 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5120 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
5121 tcg_gen_or_tl(t0
, t0
, t1
);
5122 gen_store_spr(SPR_MQ
, t0
);
5123 tcg_gen_movi_tl(cpu_ca
, 0);
5124 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
5125 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rS(ctx
->opcode
)], 0, l1
);
5126 tcg_gen_movi_tl(cpu_ca
, 1);
5128 tcg_gen_sari_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], sh
);
5131 if (unlikely(Rc(ctx
->opcode
) != 0))
5132 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5136 static void gen_sraq(DisasContext
*ctx
)
5138 TCGLabel
*l1
= gen_new_label();
5139 TCGLabel
*l2
= gen_new_label();
5140 TCGv t0
= tcg_temp_new();
5141 TCGv t1
= tcg_temp_local_new();
5142 TCGv t2
= tcg_temp_local_new();
5143 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5144 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5145 tcg_gen_sar_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5146 tcg_gen_subfi_tl(t2
, 32, t2
);
5147 tcg_gen_shl_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5148 tcg_gen_or_tl(t0
, t0
, t2
);
5149 gen_store_spr(SPR_MQ
, t0
);
5150 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5151 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l1
);
5152 tcg_gen_mov_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)]);
5153 tcg_gen_sari_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 31);
5156 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t1
);
5157 tcg_gen_movi_tl(cpu_ca
, 0);
5158 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
5159 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l2
);
5160 tcg_gen_movi_tl(cpu_ca
, 1);
5164 if (unlikely(Rc(ctx
->opcode
) != 0))
5165 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5169 static void gen_sre(DisasContext
*ctx
)
5171 TCGv t0
= tcg_temp_new();
5172 TCGv t1
= tcg_temp_new();
5173 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5174 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5175 tcg_gen_subfi_tl(t1
, 32, t1
);
5176 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5177 tcg_gen_or_tl(t1
, t0
, t1
);
5178 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5179 gen_store_spr(SPR_MQ
, t1
);
5182 if (unlikely(Rc(ctx
->opcode
) != 0))
5183 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5187 static void gen_srea(DisasContext
*ctx
)
5189 TCGv t0
= tcg_temp_new();
5190 TCGv t1
= tcg_temp_new();
5191 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5192 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5193 gen_store_spr(SPR_MQ
, t0
);
5194 tcg_gen_sar_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], t1
);
5197 if (unlikely(Rc(ctx
->opcode
) != 0))
5198 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5202 static void gen_sreq(DisasContext
*ctx
)
5204 TCGv t0
= tcg_temp_new();
5205 TCGv t1
= tcg_temp_new();
5206 TCGv t2
= tcg_temp_new();
5207 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5208 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5209 tcg_gen_shr_tl(t1
, t1
, t0
);
5210 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5211 gen_load_spr(t2
, SPR_MQ
);
5212 gen_store_spr(SPR_MQ
, t0
);
5213 tcg_gen_and_tl(t0
, t0
, t1
);
5214 tcg_gen_andc_tl(t2
, t2
, t1
);
5215 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
5219 if (unlikely(Rc(ctx
->opcode
) != 0))
5220 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5224 static void gen_sriq(DisasContext
*ctx
)
5226 int sh
= SH(ctx
->opcode
);
5227 TCGv t0
= tcg_temp_new();
5228 TCGv t1
= tcg_temp_new();
5229 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5230 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
5231 tcg_gen_or_tl(t1
, t0
, t1
);
5232 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5233 gen_store_spr(SPR_MQ
, t1
);
5236 if (unlikely(Rc(ctx
->opcode
) != 0))
5237 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5241 static void gen_srliq(DisasContext
*ctx
)
5243 int sh
= SH(ctx
->opcode
);
5244 TCGv t0
= tcg_temp_new();
5245 TCGv t1
= tcg_temp_new();
5246 tcg_gen_rotri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5247 gen_load_spr(t1
, SPR_MQ
);
5248 gen_store_spr(SPR_MQ
, t0
);
5249 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
>> sh
));
5250 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
>> sh
));
5251 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5254 if (unlikely(Rc(ctx
->opcode
) != 0))
5255 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5259 static void gen_srlq(DisasContext
*ctx
)
5261 TCGLabel
*l1
= gen_new_label();
5262 TCGLabel
*l2
= gen_new_label();
5263 TCGv t0
= tcg_temp_local_new();
5264 TCGv t1
= tcg_temp_local_new();
5265 TCGv t2
= tcg_temp_local_new();
5266 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5267 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5268 tcg_gen_shr_tl(t2
, t1
, t2
);
5269 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5270 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5271 gen_load_spr(t0
, SPR_MQ
);
5272 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
5275 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5276 tcg_gen_and_tl(t0
, t0
, t2
);
5277 gen_load_spr(t1
, SPR_MQ
);
5278 tcg_gen_andc_tl(t1
, t1
, t2
);
5279 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5284 if (unlikely(Rc(ctx
->opcode
) != 0))
5285 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5289 static void gen_srq(DisasContext
*ctx
)
5291 TCGLabel
*l1
= gen_new_label();
5292 TCGv t0
= tcg_temp_new();
5293 TCGv t1
= tcg_temp_new();
5294 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5295 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5296 tcg_gen_subfi_tl(t1
, 32, t1
);
5297 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5298 tcg_gen_or_tl(t1
, t0
, t1
);
5299 gen_store_spr(SPR_MQ
, t1
);
5300 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5301 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5302 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5303 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
5307 if (unlikely(Rc(ctx
->opcode
) != 0))
5308 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5311 /* PowerPC 602 specific instructions */
5314 static void gen_dsa(DisasContext
*ctx
)
5317 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5321 static void gen_esa(DisasContext
*ctx
)
5324 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5328 static void gen_mfrom(DisasContext
*ctx
)
5330 #if defined(CONFIG_USER_ONLY)
5334 gen_helper_602_mfrom(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5335 #endif /* defined(CONFIG_USER_ONLY) */
5338 /* 602 - 603 - G2 TLB management */
5341 static void gen_tlbld_6xx(DisasContext
*ctx
)
5343 #if defined(CONFIG_USER_ONLY)
5347 gen_helper_6xx_tlbd(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5348 #endif /* defined(CONFIG_USER_ONLY) */
5352 static void gen_tlbli_6xx(DisasContext
*ctx
)
5354 #if defined(CONFIG_USER_ONLY)
5358 gen_helper_6xx_tlbi(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5359 #endif /* defined(CONFIG_USER_ONLY) */
5362 /* 74xx TLB management */
5365 static void gen_tlbld_74xx(DisasContext
*ctx
)
5367 #if defined(CONFIG_USER_ONLY)
5371 gen_helper_74xx_tlbd(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5372 #endif /* defined(CONFIG_USER_ONLY) */
5376 static void gen_tlbli_74xx(DisasContext
*ctx
)
5378 #if defined(CONFIG_USER_ONLY)
5382 gen_helper_74xx_tlbi(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5383 #endif /* defined(CONFIG_USER_ONLY) */
5386 /* POWER instructions not in PowerPC 601 */
5389 static void gen_clf(DisasContext
*ctx
)
5391 /* Cache line flush: implemented as no-op */
5395 static void gen_cli(DisasContext
*ctx
)
5397 #if defined(CONFIG_USER_ONLY)
5400 /* Cache line invalidate: privileged and treated as no-op */
5402 #endif /* defined(CONFIG_USER_ONLY) */
5406 static void gen_dclst(DisasContext
*ctx
)
5408 /* Data cache line store: treated as no-op */
5411 static void gen_mfsri(DisasContext
*ctx
)
5413 #if defined(CONFIG_USER_ONLY)
5416 int ra
= rA(ctx
->opcode
);
5417 int rd
= rD(ctx
->opcode
);
5421 t0
= tcg_temp_new();
5422 gen_addr_reg_index(ctx
, t0
);
5423 tcg_gen_extract_tl(t0
, t0
, 28, 4);
5424 gen_helper_load_sr(cpu_gpr
[rd
], cpu_env
, t0
);
5426 if (ra
!= 0 && ra
!= rd
)
5427 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rd
]);
5428 #endif /* defined(CONFIG_USER_ONLY) */
5431 static void gen_rac(DisasContext
*ctx
)
5433 #if defined(CONFIG_USER_ONLY)
5439 t0
= tcg_temp_new();
5440 gen_addr_reg_index(ctx
, t0
);
5441 gen_helper_rac(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
5443 #endif /* defined(CONFIG_USER_ONLY) */
5446 static void gen_rfsvc(DisasContext
*ctx
)
5448 #if defined(CONFIG_USER_ONLY)
5453 gen_helper_rfsvc(cpu_env
);
5454 gen_sync_exception(ctx
);
5455 #endif /* defined(CONFIG_USER_ONLY) */
5458 /* svc is not implemented for now */
5460 /* BookE specific instructions */
5462 /* XXX: not implemented on 440 ? */
5463 static void gen_mfapidi(DisasContext
*ctx
)
5466 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5469 /* XXX: not implemented on 440 ? */
5470 static void gen_tlbiva(DisasContext
*ctx
)
5472 #if defined(CONFIG_USER_ONLY)
5478 t0
= tcg_temp_new();
5479 gen_addr_reg_index(ctx
, t0
);
5480 gen_helper_tlbiva(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5482 #endif /* defined(CONFIG_USER_ONLY) */
5485 /* All 405 MAC instructions are translated here */
5486 static inline void gen_405_mulladd_insn(DisasContext
*ctx
, int opc2
, int opc3
,
5487 int ra
, int rb
, int rt
, int Rc
)
5491 t0
= tcg_temp_local_new();
5492 t1
= tcg_temp_local_new();
5494 switch (opc3
& 0x0D) {
5496 /* macchw - macchw. - macchwo - macchwo. */
5497 /* macchws - macchws. - macchwso - macchwso. */
5498 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5499 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5500 /* mulchw - mulchw. */
5501 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
5502 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
5503 tcg_gen_ext16s_tl(t1
, t1
);
5506 /* macchwu - macchwu. - macchwuo - macchwuo. */
5507 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5508 /* mulchwu - mulchwu. */
5509 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
5510 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
5511 tcg_gen_ext16u_tl(t1
, t1
);
5514 /* machhw - machhw. - machhwo - machhwo. */
5515 /* machhws - machhws. - machhwso - machhwso. */
5516 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5517 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5518 /* mulhhw - mulhhw. */
5519 tcg_gen_sari_tl(t0
, cpu_gpr
[ra
], 16);
5520 tcg_gen_ext16s_tl(t0
, t0
);
5521 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
5522 tcg_gen_ext16s_tl(t1
, t1
);
5525 /* machhwu - machhwu. - machhwuo - machhwuo. */
5526 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5527 /* mulhhwu - mulhhwu. */
5528 tcg_gen_shri_tl(t0
, cpu_gpr
[ra
], 16);
5529 tcg_gen_ext16u_tl(t0
, t0
);
5530 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
5531 tcg_gen_ext16u_tl(t1
, t1
);
5534 /* maclhw - maclhw. - maclhwo - maclhwo. */
5535 /* maclhws - maclhws. - maclhwso - maclhwso. */
5536 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5537 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5538 /* mullhw - mullhw. */
5539 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
5540 tcg_gen_ext16s_tl(t1
, cpu_gpr
[rb
]);
5543 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5544 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5545 /* mullhwu - mullhwu. */
5546 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
5547 tcg_gen_ext16u_tl(t1
, cpu_gpr
[rb
]);
5551 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5552 tcg_gen_mul_tl(t1
, t0
, t1
);
5554 /* nmultiply-and-accumulate (0x0E) */
5555 tcg_gen_sub_tl(t0
, cpu_gpr
[rt
], t1
);
5557 /* multiply-and-accumulate (0x0C) */
5558 tcg_gen_add_tl(t0
, cpu_gpr
[rt
], t1
);
5562 /* Check overflow and/or saturate */
5563 TCGLabel
*l1
= gen_new_label();
5566 /* Start with XER OV disabled, the most likely case */
5567 tcg_gen_movi_tl(cpu_ov
, 0);
5571 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t1
);
5572 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
5573 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t0
);
5574 tcg_gen_brcondi_tl(TCG_COND_LT
, t1
, 0, l1
);
5577 tcg_gen_sari_tl(t0
, cpu_gpr
[rt
], 31);
5578 tcg_gen_xori_tl(t0
, t0
, 0x7fffffff);
5582 tcg_gen_brcond_tl(TCG_COND_GEU
, t0
, t1
, l1
);
5585 tcg_gen_movi_tl(t0
, UINT32_MAX
);
5589 /* Check overflow */
5590 tcg_gen_movi_tl(cpu_ov
, 1);
5591 tcg_gen_movi_tl(cpu_so
, 1);
5594 tcg_gen_mov_tl(cpu_gpr
[rt
], t0
);
5597 tcg_gen_mul_tl(cpu_gpr
[rt
], t0
, t1
);
5601 if (unlikely(Rc
) != 0) {
5603 gen_set_Rc0(ctx
, cpu_gpr
[rt
]);
5607 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5608 static void glue(gen_, name)(DisasContext *ctx) \
5610 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5611 rD(ctx->opcode), Rc(ctx->opcode)); \
5614 /* macchw - macchw. */
5615 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05);
5616 /* macchwo - macchwo. */
5617 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15);
5618 /* macchws - macchws. */
5619 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07);
5620 /* macchwso - macchwso. */
5621 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17);
5622 /* macchwsu - macchwsu. */
5623 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06);
5624 /* macchwsuo - macchwsuo. */
5625 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16);
5626 /* macchwu - macchwu. */
5627 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04);
5628 /* macchwuo - macchwuo. */
5629 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14);
5630 /* machhw - machhw. */
5631 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01);
5632 /* machhwo - machhwo. */
5633 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11);
5634 /* machhws - machhws. */
5635 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03);
5636 /* machhwso - machhwso. */
5637 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13);
5638 /* machhwsu - machhwsu. */
5639 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02);
5640 /* machhwsuo - machhwsuo. */
5641 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12);
5642 /* machhwu - machhwu. */
5643 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00);
5644 /* machhwuo - machhwuo. */
5645 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10);
5646 /* maclhw - maclhw. */
5647 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D);
5648 /* maclhwo - maclhwo. */
5649 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D);
5650 /* maclhws - maclhws. */
5651 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F);
5652 /* maclhwso - maclhwso. */
5653 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F);
5654 /* maclhwu - maclhwu. */
5655 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C);
5656 /* maclhwuo - maclhwuo. */
5657 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C);
5658 /* maclhwsu - maclhwsu. */
5659 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E);
5660 /* maclhwsuo - maclhwsuo. */
5661 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E);
5662 /* nmacchw - nmacchw. */
5663 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05);
5664 /* nmacchwo - nmacchwo. */
5665 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15);
5666 /* nmacchws - nmacchws. */
5667 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07);
5668 /* nmacchwso - nmacchwso. */
5669 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17);
5670 /* nmachhw - nmachhw. */
5671 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01);
5672 /* nmachhwo - nmachhwo. */
5673 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11);
5674 /* nmachhws - nmachhws. */
5675 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03);
5676 /* nmachhwso - nmachhwso. */
5677 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13);
5678 /* nmaclhw - nmaclhw. */
5679 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D);
5680 /* nmaclhwo - nmaclhwo. */
5681 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D);
5682 /* nmaclhws - nmaclhws. */
5683 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F);
5684 /* nmaclhwso - nmaclhwso. */
5685 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F);
5687 /* mulchw - mulchw. */
5688 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05);
5689 /* mulchwu - mulchwu. */
5690 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04);
5691 /* mulhhw - mulhhw. */
5692 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01);
5693 /* mulhhwu - mulhhwu. */
5694 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00);
5695 /* mullhw - mullhw. */
5696 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D);
5697 /* mullhwu - mullhwu. */
5698 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C);
5701 static void gen_mfdcr(DisasContext
*ctx
)
5703 #if defined(CONFIG_USER_ONLY)
5709 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
5710 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, dcrn
);
5711 tcg_temp_free(dcrn
);
5712 #endif /* defined(CONFIG_USER_ONLY) */
5716 static void gen_mtdcr(DisasContext
*ctx
)
5718 #if defined(CONFIG_USER_ONLY)
5724 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
5725 gen_helper_store_dcr(cpu_env
, dcrn
, cpu_gpr
[rS(ctx
->opcode
)]);
5726 tcg_temp_free(dcrn
);
5727 #endif /* defined(CONFIG_USER_ONLY) */
5731 /* XXX: not implemented on 440 ? */
5732 static void gen_mfdcrx(DisasContext
*ctx
)
5734 #if defined(CONFIG_USER_ONLY)
5738 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5739 cpu_gpr
[rA(ctx
->opcode
)]);
5740 /* Note: Rc update flag set leads to undefined state of Rc0 */
5741 #endif /* defined(CONFIG_USER_ONLY) */
5745 /* XXX: not implemented on 440 ? */
5746 static void gen_mtdcrx(DisasContext
*ctx
)
5748 #if defined(CONFIG_USER_ONLY)
5752 gen_helper_store_dcr(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5753 cpu_gpr
[rS(ctx
->opcode
)]);
5754 /* Note: Rc update flag set leads to undefined state of Rc0 */
5755 #endif /* defined(CONFIG_USER_ONLY) */
5758 /* mfdcrux (PPC 460) : user-mode access to DCR */
5759 static void gen_mfdcrux(DisasContext
*ctx
)
5761 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5762 cpu_gpr
[rA(ctx
->opcode
)]);
5763 /* Note: Rc update flag set leads to undefined state of Rc0 */
5766 /* mtdcrux (PPC 460) : user-mode access to DCR */
5767 static void gen_mtdcrux(DisasContext
*ctx
)
5769 gen_helper_store_dcr(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5770 cpu_gpr
[rS(ctx
->opcode
)]);
5771 /* Note: Rc update flag set leads to undefined state of Rc0 */
5775 static void gen_dccci(DisasContext
*ctx
)
5778 /* interpreted as no-op */
5782 static void gen_dcread(DisasContext
*ctx
)
5784 #if defined(CONFIG_USER_ONLY)
5790 gen_set_access_type(ctx
, ACCESS_CACHE
);
5791 EA
= tcg_temp_new();
5792 gen_addr_reg_index(ctx
, EA
);
5793 val
= tcg_temp_new();
5794 gen_qemu_ld32u(ctx
, val
, EA
);
5796 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], EA
);
5798 #endif /* defined(CONFIG_USER_ONLY) */
5802 static void gen_icbt_40x(DisasContext
*ctx
)
5804 /* interpreted as no-op */
5805 /* XXX: specification say this is treated as a load by the MMU
5806 * but does not generate any exception
5811 static void gen_iccci(DisasContext
*ctx
)
5814 /* interpreted as no-op */
5818 static void gen_icread(DisasContext
*ctx
)
5821 /* interpreted as no-op */
5824 /* rfci (supervisor only) */
5825 static void gen_rfci_40x(DisasContext
*ctx
)
5827 #if defined(CONFIG_USER_ONLY)
5831 /* Restore CPU state */
5832 gen_helper_40x_rfci(cpu_env
);
5833 gen_sync_exception(ctx
);
5834 #endif /* defined(CONFIG_USER_ONLY) */
5837 static void gen_rfci(DisasContext
*ctx
)
5839 #if defined(CONFIG_USER_ONLY)
5843 /* Restore CPU state */
5844 gen_helper_rfci(cpu_env
);
5845 gen_sync_exception(ctx
);
5846 #endif /* defined(CONFIG_USER_ONLY) */
5849 /* BookE specific */
5851 /* XXX: not implemented on 440 ? */
5852 static void gen_rfdi(DisasContext
*ctx
)
5854 #if defined(CONFIG_USER_ONLY)
5858 /* Restore CPU state */
5859 gen_helper_rfdi(cpu_env
);
5860 gen_sync_exception(ctx
);
5861 #endif /* defined(CONFIG_USER_ONLY) */
5864 /* XXX: not implemented on 440 ? */
5865 static void gen_rfmci(DisasContext
*ctx
)
5867 #if defined(CONFIG_USER_ONLY)
5871 /* Restore CPU state */
5872 gen_helper_rfmci(cpu_env
);
5873 gen_sync_exception(ctx
);
5874 #endif /* defined(CONFIG_USER_ONLY) */
5877 /* TLB management - PowerPC 405 implementation */
5880 static void gen_tlbre_40x(DisasContext
*ctx
)
5882 #if defined(CONFIG_USER_ONLY)
5886 switch (rB(ctx
->opcode
)) {
5888 gen_helper_4xx_tlbre_hi(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5889 cpu_gpr
[rA(ctx
->opcode
)]);
5892 gen_helper_4xx_tlbre_lo(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5893 cpu_gpr
[rA(ctx
->opcode
)]);
5896 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5899 #endif /* defined(CONFIG_USER_ONLY) */
5902 /* tlbsx - tlbsx. */
5903 static void gen_tlbsx_40x(DisasContext
*ctx
)
5905 #if defined(CONFIG_USER_ONLY)
5911 t0
= tcg_temp_new();
5912 gen_addr_reg_index(ctx
, t0
);
5913 gen_helper_4xx_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
5915 if (Rc(ctx
->opcode
)) {
5916 TCGLabel
*l1
= gen_new_label();
5917 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
5918 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
5919 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
5922 #endif /* defined(CONFIG_USER_ONLY) */
5926 static void gen_tlbwe_40x(DisasContext
*ctx
)
5928 #if defined(CONFIG_USER_ONLY)
5933 switch (rB(ctx
->opcode
)) {
5935 gen_helper_4xx_tlbwe_hi(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5936 cpu_gpr
[rS(ctx
->opcode
)]);
5939 gen_helper_4xx_tlbwe_lo(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5940 cpu_gpr
[rS(ctx
->opcode
)]);
5943 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5946 #endif /* defined(CONFIG_USER_ONLY) */
5949 /* TLB management - PowerPC 440 implementation */
5952 static void gen_tlbre_440(DisasContext
*ctx
)
5954 #if defined(CONFIG_USER_ONLY)
5959 switch (rB(ctx
->opcode
)) {
5964 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
5965 gen_helper_440_tlbre(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5966 t0
, cpu_gpr
[rA(ctx
->opcode
)]);
5967 tcg_temp_free_i32(t0
);
5971 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5974 #endif /* defined(CONFIG_USER_ONLY) */
5977 /* tlbsx - tlbsx. */
5978 static void gen_tlbsx_440(DisasContext
*ctx
)
5980 #if defined(CONFIG_USER_ONLY)
5986 t0
= tcg_temp_new();
5987 gen_addr_reg_index(ctx
, t0
);
5988 gen_helper_440_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
5990 if (Rc(ctx
->opcode
)) {
5991 TCGLabel
*l1
= gen_new_label();
5992 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
5993 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
5994 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
5997 #endif /* defined(CONFIG_USER_ONLY) */
6001 static void gen_tlbwe_440(DisasContext
*ctx
)
6003 #if defined(CONFIG_USER_ONLY)
6007 switch (rB(ctx
->opcode
)) {
6012 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
6013 gen_helper_440_tlbwe(cpu_env
, t0
, cpu_gpr
[rA(ctx
->opcode
)],
6014 cpu_gpr
[rS(ctx
->opcode
)]);
6015 tcg_temp_free_i32(t0
);
6019 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6022 #endif /* defined(CONFIG_USER_ONLY) */
6025 /* TLB management - PowerPC BookE 2.06 implementation */
6028 static void gen_tlbre_booke206(DisasContext
*ctx
)
6030 #if defined(CONFIG_USER_ONLY)
6034 gen_helper_booke206_tlbre(cpu_env
);
6035 #endif /* defined(CONFIG_USER_ONLY) */
6038 /* tlbsx - tlbsx. */
6039 static void gen_tlbsx_booke206(DisasContext
*ctx
)
6041 #if defined(CONFIG_USER_ONLY)
6047 if (rA(ctx
->opcode
)) {
6048 t0
= tcg_temp_new();
6049 tcg_gen_mov_tl(t0
, cpu_gpr
[rD(ctx
->opcode
)]);
6051 t0
= tcg_const_tl(0);
6054 tcg_gen_add_tl(t0
, t0
, cpu_gpr
[rB(ctx
->opcode
)]);
6055 gen_helper_booke206_tlbsx(cpu_env
, t0
);
6057 #endif /* defined(CONFIG_USER_ONLY) */
6061 static void gen_tlbwe_booke206(DisasContext
*ctx
)
6063 #if defined(CONFIG_USER_ONLY)
6067 gen_helper_booke206_tlbwe(cpu_env
);
6068 #endif /* defined(CONFIG_USER_ONLY) */
6071 static void gen_tlbivax_booke206(DisasContext
*ctx
)
6073 #if defined(CONFIG_USER_ONLY)
6079 t0
= tcg_temp_new();
6080 gen_addr_reg_index(ctx
, t0
);
6081 gen_helper_booke206_tlbivax(cpu_env
, t0
);
6083 #endif /* defined(CONFIG_USER_ONLY) */
6086 static void gen_tlbilx_booke206(DisasContext
*ctx
)
6088 #if defined(CONFIG_USER_ONLY)
6094 t0
= tcg_temp_new();
6095 gen_addr_reg_index(ctx
, t0
);
6097 switch((ctx
->opcode
>> 21) & 0x3) {
6099 gen_helper_booke206_tlbilx0(cpu_env
, t0
);
6102 gen_helper_booke206_tlbilx1(cpu_env
, t0
);
6105 gen_helper_booke206_tlbilx3(cpu_env
, t0
);
6108 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6113 #endif /* defined(CONFIG_USER_ONLY) */
6118 static void gen_wrtee(DisasContext
*ctx
)
6120 #if defined(CONFIG_USER_ONLY)
6126 t0
= tcg_temp_new();
6127 tcg_gen_andi_tl(t0
, cpu_gpr
[rD(ctx
->opcode
)], (1 << MSR_EE
));
6128 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
6129 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
6131 /* Stop translation to have a chance to raise an exception
6132 * if we just set msr_ee to 1
6134 gen_stop_exception(ctx
);
6135 #endif /* defined(CONFIG_USER_ONLY) */
6139 static void gen_wrteei(DisasContext
*ctx
)
6141 #if defined(CONFIG_USER_ONLY)
6145 if (ctx
->opcode
& 0x00008000) {
6146 tcg_gen_ori_tl(cpu_msr
, cpu_msr
, (1 << MSR_EE
));
6147 /* Stop translation to have a chance to raise an exception */
6148 gen_stop_exception(ctx
);
6150 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
6152 #endif /* defined(CONFIG_USER_ONLY) */
6155 /* PowerPC 440 specific instructions */
6158 static void gen_dlmzb(DisasContext
*ctx
)
6160 TCGv_i32 t0
= tcg_const_i32(Rc(ctx
->opcode
));
6161 gen_helper_dlmzb(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
6162 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], t0
);
6163 tcg_temp_free_i32(t0
);
6166 /* mbar replaces eieio on 440 */
6167 static void gen_mbar(DisasContext
*ctx
)
6169 /* interpreted as no-op */
6172 /* msync replaces sync on 440 */
6173 static void gen_msync_4xx(DisasContext
*ctx
)
6175 /* interpreted as no-op */
6179 static void gen_icbt_440(DisasContext
*ctx
)
6181 /* interpreted as no-op */
6182 /* XXX: specification say this is treated as a load by the MMU
6183 * but does not generate any exception
6187 /* Embedded.Processor Control */
6189 static void gen_msgclr(DisasContext
*ctx
)
6191 #if defined(CONFIG_USER_ONLY)
6195 gen_helper_msgclr(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
6196 #endif /* defined(CONFIG_USER_ONLY) */
6199 static void gen_msgsnd(DisasContext
*ctx
)
6201 #if defined(CONFIG_USER_ONLY)
6205 gen_helper_msgsnd(cpu_gpr
[rB(ctx
->opcode
)]);
6206 #endif /* defined(CONFIG_USER_ONLY) */
6210 #if defined(TARGET_PPC64)
6211 static void gen_maddld(DisasContext
*ctx
)
6213 TCGv_i64 t1
= tcg_temp_new_i64();
6215 tcg_gen_mul_i64(t1
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
6216 tcg_gen_add_i64(cpu_gpr
[rD(ctx
->opcode
)], t1
, cpu_gpr
[rC(ctx
->opcode
)]);
6217 tcg_temp_free_i64(t1
);
6220 /* maddhd maddhdu */
6221 static void gen_maddhd_maddhdu(DisasContext
*ctx
)
6223 TCGv_i64 lo
= tcg_temp_new_i64();
6224 TCGv_i64 hi
= tcg_temp_new_i64();
6225 TCGv_i64 t1
= tcg_temp_new_i64();
6227 if (Rc(ctx
->opcode
)) {
6228 tcg_gen_mulu2_i64(lo
, hi
, cpu_gpr
[rA(ctx
->opcode
)],
6229 cpu_gpr
[rB(ctx
->opcode
)]);
6230 tcg_gen_movi_i64(t1
, 0);
6232 tcg_gen_muls2_i64(lo
, hi
, cpu_gpr
[rA(ctx
->opcode
)],
6233 cpu_gpr
[rB(ctx
->opcode
)]);
6234 tcg_gen_sari_i64(t1
, cpu_gpr
[rC(ctx
->opcode
)], 63);
6236 tcg_gen_add2_i64(t1
, cpu_gpr
[rD(ctx
->opcode
)], lo
, hi
,
6237 cpu_gpr
[rC(ctx
->opcode
)], t1
);
6238 tcg_temp_free_i64(lo
);
6239 tcg_temp_free_i64(hi
);
6240 tcg_temp_free_i64(t1
);
6242 #endif /* defined(TARGET_PPC64) */
6244 static void gen_tbegin(DisasContext
*ctx
)
6246 if (unlikely(!ctx
->tm_enabled
)) {
6247 gen_exception_err(ctx
, POWERPC_EXCP_FU
, FSCR_IC_TM
);
6250 gen_helper_tbegin(cpu_env
);
6253 #define GEN_TM_NOOP(name) \
6254 static inline void gen_##name(DisasContext *ctx) \
6256 if (unlikely(!ctx->tm_enabled)) { \
6257 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6260 /* Because tbegin always fails in QEMU, these user \
6261 * space instructions all have a simple implementation: \
6263 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6264 * = 0b0 || 0b00 || 0b0 \
6266 tcg_gen_movi_i32(cpu_crf[0], 0); \
6270 GEN_TM_NOOP(tabort
);
6271 GEN_TM_NOOP(tabortwc
);
6272 GEN_TM_NOOP(tabortwci
);
6273 GEN_TM_NOOP(tabortdc
);
6274 GEN_TM_NOOP(tabortdci
);
6276 static inline void gen_cp_abort(DisasContext
*ctx
)
6281 #define GEN_CP_PASTE_NOOP(name) \
6282 static inline void gen_##name(DisasContext *ctx) \
6284 /* Generate invalid exception until \
6285 * we have an implementation of the copy \
6291 GEN_CP_PASTE_NOOP(copy
)
6292 GEN_CP_PASTE_NOOP(paste
)
6294 static void gen_tcheck(DisasContext
*ctx
)
6296 if (unlikely(!ctx
->tm_enabled
)) {
6297 gen_exception_err(ctx
, POWERPC_EXCP_FU
, FSCR_IC_TM
);
6300 /* Because tbegin always fails, the tcheck implementation
6303 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
6304 * = 0b1 || 0b00 || 0b0
6306 tcg_gen_movi_i32(cpu_crf
[crfD(ctx
->opcode
)], 0x8);
6309 #if defined(CONFIG_USER_ONLY)
6310 #define GEN_TM_PRIV_NOOP(name) \
6311 static inline void gen_##name(DisasContext *ctx) \
6313 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
6318 #define GEN_TM_PRIV_NOOP(name) \
6319 static inline void gen_##name(DisasContext *ctx) \
6322 if (unlikely(!ctx->tm_enabled)) { \
6323 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6326 /* Because tbegin always fails, the implementation is \
6329 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6330 * = 0b0 || 0b00 | 0b0 \
6332 tcg_gen_movi_i32(cpu_crf[0], 0); \
6337 GEN_TM_PRIV_NOOP(treclaim
);
6338 GEN_TM_PRIV_NOOP(trechkpt
);
6340 #include "translate/fp-impl.inc.c"
6342 #include "translate/vmx-impl.inc.c"
6344 #include "translate/vsx-impl.inc.c"
6346 #include "translate/dfp-impl.inc.c"
6348 #include "translate/spe-impl.inc.c"
6350 /* Handles lfdp, lxsd, lxssp */
6351 static void gen_dform39(DisasContext
*ctx
)
6353 switch (ctx
->opcode
& 0x3) {
6355 if (ctx
->insns_flags2
& PPC2_ISA205
) {
6356 return gen_lfdp(ctx
);
6360 if (ctx
->insns_flags2
& PPC2_ISA300
) {
6361 return gen_lxsd(ctx
);
6365 if (ctx
->insns_flags2
& PPC2_ISA300
) {
6366 return gen_lxssp(ctx
);
6370 return gen_invalid(ctx
);
6373 /* handles stfdp, lxv, stxsd, stxssp lxvx */
6374 static void gen_dform3D(DisasContext
*ctx
)
6376 if ((ctx
->opcode
& 3) == 1) { /* DQ-FORM */
6377 switch (ctx
->opcode
& 0x7) {
6379 if (ctx
->insns_flags2
& PPC2_ISA300
) {
6380 return gen_lxv(ctx
);
6384 if (ctx
->insns_flags2
& PPC2_ISA300
) {
6385 return gen_stxv(ctx
);
6389 } else { /* DS-FORM */
6390 switch (ctx
->opcode
& 0x3) {
6392 if (ctx
->insns_flags2
& PPC2_ISA205
) {
6393 return gen_stfdp(ctx
);
6397 if (ctx
->insns_flags2
& PPC2_ISA300
) {
6398 return gen_stxsd(ctx
);
6401 case 3: /* stxssp */
6402 if (ctx
->insns_flags2
& PPC2_ISA300
) {
6403 return gen_stxssp(ctx
);
6408 return gen_invalid(ctx
);
6411 static opcode_t opcodes
[] = {
6412 GEN_HANDLER(invalid
, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE
),
6413 GEN_HANDLER(cmp
, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER
),
6414 GEN_HANDLER(cmpi
, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
),
6415 GEN_HANDLER(cmpl
, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER
),
6416 GEN_HANDLER(cmpli
, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
),
6417 #if defined(TARGET_PPC64)
6418 GEN_HANDLER_E(cmpeqb
, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE
, PPC2_ISA300
),
6420 GEN_HANDLER_E(cmpb
, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE
, PPC2_ISA205
),
6421 GEN_HANDLER_E(cmprb
, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE
, PPC2_ISA300
),
6422 GEN_HANDLER(isel
, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL
),
6423 GEN_HANDLER(addi
, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6424 GEN_HANDLER(addic
, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6425 GEN_HANDLER2(addic_
, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6426 GEN_HANDLER(addis
, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6427 GEN_HANDLER_E(addpcis
, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE
, PPC2_ISA300
),
6428 GEN_HANDLER(mulhw
, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER
),
6429 GEN_HANDLER(mulhwu
, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER
),
6430 GEN_HANDLER(mullw
, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER
),
6431 GEN_HANDLER(mullwo
, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER
),
6432 GEN_HANDLER(mulli
, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6433 #if defined(TARGET_PPC64)
6434 GEN_HANDLER(mulld
, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B
),
6436 GEN_HANDLER(neg
, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER
),
6437 GEN_HANDLER(nego
, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER
),
6438 GEN_HANDLER(subfic
, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6439 GEN_HANDLER2(andi_
, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6440 GEN_HANDLER2(andis_
, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6441 GEN_HANDLER(cntlzw
, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER
),
6442 GEN_HANDLER_E(cnttzw
, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE
, PPC2_ISA300
),
6443 GEN_HANDLER_E(copy
, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE
, PPC2_ISA300
),
6444 GEN_HANDLER_E(cp_abort
, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE
, PPC2_ISA300
),
6445 GEN_HANDLER_E(paste
, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE
, PPC2_ISA300
),
6446 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER
),
6447 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER
),
6448 GEN_HANDLER(ori
, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6449 GEN_HANDLER(oris
, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6450 GEN_HANDLER(xori
, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6451 GEN_HANDLER(xoris
, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6452 GEN_HANDLER(popcntb
, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB
),
6453 GEN_HANDLER(popcntw
, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD
),
6454 GEN_HANDLER_E(prtyw
, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE
, PPC2_ISA205
),
6455 #if defined(TARGET_PPC64)
6456 GEN_HANDLER(popcntd
, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD
),
6457 GEN_HANDLER(cntlzd
, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B
),
6458 GEN_HANDLER_E(cnttzd
, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE
, PPC2_ISA300
),
6459 GEN_HANDLER_E(darn
, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE
, PPC2_ISA300
),
6460 GEN_HANDLER_E(prtyd
, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE
, PPC2_ISA205
),
6461 GEN_HANDLER_E(bpermd
, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE
, PPC2_PERM_ISA206
),
6463 GEN_HANDLER(rlwimi
, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6464 GEN_HANDLER(rlwinm
, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6465 GEN_HANDLER(rlwnm
, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6466 GEN_HANDLER(slw
, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER
),
6467 GEN_HANDLER(sraw
, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER
),
6468 GEN_HANDLER(srawi
, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER
),
6469 GEN_HANDLER(srw
, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER
),
6470 #if defined(TARGET_PPC64)
6471 GEN_HANDLER(sld
, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B
),
6472 GEN_HANDLER(srad
, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B
),
6473 GEN_HANDLER2(sradi0
, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B
),
6474 GEN_HANDLER2(sradi1
, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B
),
6475 GEN_HANDLER(srd
, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B
),
6476 GEN_HANDLER2_E(extswsli0
, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
6477 PPC_NONE
, PPC2_ISA300
),
6478 GEN_HANDLER2_E(extswsli1
, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
6479 PPC_NONE
, PPC2_ISA300
),
6481 #if defined(TARGET_PPC64)
6482 GEN_HANDLER(ld
, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B
),
6483 GEN_HANDLER(lq
, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX
),
6484 GEN_HANDLER(std
, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B
),
6486 /* handles lfdp, lxsd, lxssp */
6487 GEN_HANDLER_E(dform39
, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE
, PPC2_ISA205
),
6488 /* handles stfdp, lxv, stxsd, stxssp, stxv */
6489 GEN_HANDLER_E(dform3D
, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE
, PPC2_ISA205
),
6490 GEN_HANDLER(lmw
, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6491 GEN_HANDLER(stmw
, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6492 GEN_HANDLER(lswi
, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING
),
6493 GEN_HANDLER(lswx
, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING
),
6494 GEN_HANDLER(stswi
, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING
),
6495 GEN_HANDLER(stswx
, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING
),
6496 GEN_HANDLER(eieio
, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO
),
6497 GEN_HANDLER(isync
, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM
),
6498 GEN_HANDLER_E(lbarx
, 0x1F, 0x14, 0x01, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
6499 GEN_HANDLER_E(lharx
, 0x1F, 0x14, 0x03, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
6500 GEN_HANDLER(lwarx
, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES
),
6501 GEN_HANDLER_E(lwat
, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE
, PPC2_ISA300
),
6502 GEN_HANDLER_E(stwat
, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE
, PPC2_ISA300
),
6503 GEN_HANDLER_E(stbcx_
, 0x1F, 0x16, 0x15, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
6504 GEN_HANDLER_E(sthcx_
, 0x1F, 0x16, 0x16, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
6505 GEN_HANDLER2(stwcx_
, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES
),
6506 #if defined(TARGET_PPC64)
6507 GEN_HANDLER_E(ldat
, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE
, PPC2_ISA300
),
6508 GEN_HANDLER_E(stdat
, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE
, PPC2_ISA300
),
6509 GEN_HANDLER(ldarx
, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B
),
6510 GEN_HANDLER_E(lqarx
, 0x1F, 0x14, 0x08, 0, PPC_NONE
, PPC2_LSQ_ISA207
),
6511 GEN_HANDLER2(stdcx_
, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B
),
6512 GEN_HANDLER_E(stqcx_
, 0x1F, 0x16, 0x05, 0, PPC_NONE
, PPC2_LSQ_ISA207
),
6514 GEN_HANDLER(sync
, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC
),
6515 GEN_HANDLER(wait
, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT
),
6516 GEN_HANDLER_E(wait
, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE
, PPC2_ISA300
),
6517 GEN_HANDLER(b
, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
6518 GEN_HANDLER(bc
, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
6519 GEN_HANDLER(bcctr
, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW
),
6520 GEN_HANDLER(bclr
, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW
),
6521 GEN_HANDLER_E(bctar
, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE
, PPC2_BCTAR_ISA207
),
6522 GEN_HANDLER(mcrf
, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER
),
6523 GEN_HANDLER(rfi
, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW
),
6524 #if defined(TARGET_PPC64)
6525 GEN_HANDLER(rfid
, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B
),
6526 GEN_HANDLER_E(stop
, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE
, PPC2_ISA300
),
6527 GEN_HANDLER_E(doze
, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE
, PPC2_PM_ISA206
),
6528 GEN_HANDLER_E(nap
, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE
, PPC2_PM_ISA206
),
6529 GEN_HANDLER_E(sleep
, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE
, PPC2_PM_ISA206
),
6530 GEN_HANDLER_E(rvwinkle
, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE
, PPC2_PM_ISA206
),
6531 GEN_HANDLER(hrfid
, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H
),
6533 GEN_HANDLER(sc
, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW
),
6534 GEN_HANDLER(tw
, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW
),
6535 GEN_HANDLER(twi
, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
6536 #if defined(TARGET_PPC64)
6537 GEN_HANDLER(td
, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B
),
6538 GEN_HANDLER(tdi
, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B
),
6540 GEN_HANDLER(mcrxr
, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC
),
6541 GEN_HANDLER(mfcr
, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC
),
6542 GEN_HANDLER(mfmsr
, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC
),
6543 GEN_HANDLER(mfspr
, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC
),
6544 GEN_HANDLER(mftb
, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB
),
6545 GEN_HANDLER(mtcrf
, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC
),
6546 #if defined(TARGET_PPC64)
6547 GEN_HANDLER(mtmsrd
, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B
),
6548 GEN_HANDLER_E(setb
, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE
, PPC2_ISA300
),
6549 GEN_HANDLER_E(mcrxrx
, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE
, PPC2_ISA300
),
6551 GEN_HANDLER(mtmsr
, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC
),
6552 GEN_HANDLER(mtspr
, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC
),
6553 GEN_HANDLER(dcbf
, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE
),
6554 GEN_HANDLER(dcbi
, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE
),
6555 GEN_HANDLER(dcbst
, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE
),
6556 GEN_HANDLER(dcbt
, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE
),
6557 GEN_HANDLER(dcbtst
, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE
),
6558 GEN_HANDLER_E(dcbtls
, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE
, PPC2_BOOKE206
),
6559 GEN_HANDLER(dcbz
, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ
),
6560 GEN_HANDLER(dst
, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC
),
6561 GEN_HANDLER(dstst
, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC
),
6562 GEN_HANDLER(dss
, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC
),
6563 GEN_HANDLER(icbi
, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI
),
6564 GEN_HANDLER(dcba
, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA
),
6565 GEN_HANDLER(mfsr
, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT
),
6566 GEN_HANDLER(mfsrin
, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT
),
6567 GEN_HANDLER(mtsr
, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT
),
6568 GEN_HANDLER(mtsrin
, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT
),
6569 #if defined(TARGET_PPC64)
6570 GEN_HANDLER2(mfsr_64b
, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B
),
6571 GEN_HANDLER2(mfsrin_64b
, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
6573 GEN_HANDLER2(mtsr_64b
, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B
),
6574 GEN_HANDLER2(mtsrin_64b
, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
6576 GEN_HANDLER2(slbmte
, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B
),
6577 GEN_HANDLER2(slbmfee
, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B
),
6578 GEN_HANDLER2(slbmfev
, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B
),
6579 GEN_HANDLER2(slbfee_
, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B
),
6581 GEN_HANDLER(tlbia
, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA
),
6582 /* XXX Those instructions will need to be handled differently for
6583 * different ISA versions */
6584 GEN_HANDLER(tlbiel
, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE
),
6585 GEN_HANDLER(tlbie
, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE
),
6586 GEN_HANDLER_E(tlbiel
, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE
, PPC2_ISA300
),
6587 GEN_HANDLER_E(tlbie
, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE
, PPC2_ISA300
),
6588 GEN_HANDLER(tlbsync
, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC
),
6589 #if defined(TARGET_PPC64)
6590 GEN_HANDLER(slbia
, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI
),
6591 GEN_HANDLER(slbie
, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI
),
6592 GEN_HANDLER_E(slbieg
, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE
, PPC2_ISA300
),
6593 GEN_HANDLER_E(slbsync
, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE
, PPC2_ISA300
),
6595 GEN_HANDLER(eciwx
, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN
),
6596 GEN_HANDLER(ecowx
, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN
),
6597 GEN_HANDLER(abs
, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR
),
6598 GEN_HANDLER(abso
, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR
),
6599 GEN_HANDLER(clcs
, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR
),
6600 GEN_HANDLER(div
, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR
),
6601 GEN_HANDLER(divo
, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR
),
6602 GEN_HANDLER(divs
, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR
),
6603 GEN_HANDLER(divso
, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR
),
6604 GEN_HANDLER(doz
, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR
),
6605 GEN_HANDLER(dozo
, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR
),
6606 GEN_HANDLER(dozi
, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
),
6607 GEN_HANDLER(lscbx
, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR
),
6608 GEN_HANDLER(maskg
, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR
),
6609 GEN_HANDLER(maskir
, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR
),
6610 GEN_HANDLER(mul
, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR
),
6611 GEN_HANDLER(mulo
, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR
),
6612 GEN_HANDLER(nabs
, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR
),
6613 GEN_HANDLER(nabso
, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR
),
6614 GEN_HANDLER(rlmi
, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
),
6615 GEN_HANDLER(rrib
, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR
),
6616 GEN_HANDLER(sle
, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR
),
6617 GEN_HANDLER(sleq
, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR
),
6618 GEN_HANDLER(sliq
, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR
),
6619 GEN_HANDLER(slliq
, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR
),
6620 GEN_HANDLER(sllq
, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR
),
6621 GEN_HANDLER(slq
, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR
),
6622 GEN_HANDLER(sraiq
, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR
),
6623 GEN_HANDLER(sraq
, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR
),
6624 GEN_HANDLER(sre
, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR
),
6625 GEN_HANDLER(srea
, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR
),
6626 GEN_HANDLER(sreq
, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR
),
6627 GEN_HANDLER(sriq
, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR
),
6628 GEN_HANDLER(srliq
, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR
),
6629 GEN_HANDLER(srlq
, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR
),
6630 GEN_HANDLER(srq
, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR
),
6631 GEN_HANDLER(dsa
, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC
),
6632 GEN_HANDLER(esa
, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC
),
6633 GEN_HANDLER(mfrom
, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC
),
6634 GEN_HANDLER2(tlbld_6xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB
),
6635 GEN_HANDLER2(tlbli_6xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB
),
6636 GEN_HANDLER2(tlbld_74xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB
),
6637 GEN_HANDLER2(tlbli_74xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB
),
6638 GEN_HANDLER(clf
, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER
),
6639 GEN_HANDLER(cli
, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER
),
6640 GEN_HANDLER(dclst
, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER
),
6641 GEN_HANDLER(mfsri
, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER
),
6642 GEN_HANDLER(rac
, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER
),
6643 GEN_HANDLER(rfsvc
, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER
),
6644 GEN_HANDLER(lfq
, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
6645 GEN_HANDLER(lfqu
, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
6646 GEN_HANDLER(lfqux
, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2
),
6647 GEN_HANDLER(lfqx
, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2
),
6648 GEN_HANDLER(stfq
, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
6649 GEN_HANDLER(stfqu
, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
6650 GEN_HANDLER(stfqux
, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2
),
6651 GEN_HANDLER(stfqx
, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2
),
6652 GEN_HANDLER(mfapidi
, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI
),
6653 GEN_HANDLER(tlbiva
, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA
),
6654 GEN_HANDLER(mfdcr
, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR
),
6655 GEN_HANDLER(mtdcr
, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR
),
6656 GEN_HANDLER(mfdcrx
, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX
),
6657 GEN_HANDLER(mtdcrx
, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX
),
6658 GEN_HANDLER(mfdcrux
, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX
),
6659 GEN_HANDLER(mtdcrux
, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX
),
6660 GEN_HANDLER(dccci
, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON
),
6661 GEN_HANDLER(dcread
, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON
),
6662 GEN_HANDLER2(icbt_40x
, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT
),
6663 GEN_HANDLER(iccci
, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON
),
6664 GEN_HANDLER(icread
, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON
),
6665 GEN_HANDLER2(rfci_40x
, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP
),
6666 GEN_HANDLER_E(rfci
, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE
, PPC2_BOOKE206
),
6667 GEN_HANDLER(rfdi
, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI
),
6668 GEN_HANDLER(rfmci
, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI
),
6669 GEN_HANDLER2(tlbre_40x
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB
),
6670 GEN_HANDLER2(tlbsx_40x
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB
),
6671 GEN_HANDLER2(tlbwe_40x
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB
),
6672 GEN_HANDLER2(tlbre_440
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE
),
6673 GEN_HANDLER2(tlbsx_440
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE
),
6674 GEN_HANDLER2(tlbwe_440
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE
),
6675 GEN_HANDLER2_E(tlbre_booke206
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
6676 PPC_NONE
, PPC2_BOOKE206
),
6677 GEN_HANDLER2_E(tlbsx_booke206
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
6678 PPC_NONE
, PPC2_BOOKE206
),
6679 GEN_HANDLER2_E(tlbwe_booke206
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
6680 PPC_NONE
, PPC2_BOOKE206
),
6681 GEN_HANDLER2_E(tlbivax_booke206
, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
6682 PPC_NONE
, PPC2_BOOKE206
),
6683 GEN_HANDLER2_E(tlbilx_booke206
, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
6684 PPC_NONE
, PPC2_BOOKE206
),
6685 GEN_HANDLER2_E(msgsnd
, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
6686 PPC_NONE
, PPC2_PRCNTL
),
6687 GEN_HANDLER2_E(msgclr
, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
6688 PPC_NONE
, PPC2_PRCNTL
),
6689 GEN_HANDLER(wrtee
, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE
),
6690 GEN_HANDLER(wrteei
, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE
),
6691 GEN_HANDLER(dlmzb
, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC
),
6692 GEN_HANDLER_E(mbar
, 0x1F, 0x16, 0x1a, 0x001FF801,
6693 PPC_BOOKE
, PPC2_BOOKE206
),
6694 GEN_HANDLER(msync_4xx
, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE
),
6695 GEN_HANDLER2_E(icbt_440
, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
6696 PPC_BOOKE
, PPC2_BOOKE206
),
6697 GEN_HANDLER(lvsl
, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC
),
6698 GEN_HANDLER(lvsr
, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC
),
6699 GEN_HANDLER(mfvscr
, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC
),
6700 GEN_HANDLER(mtvscr
, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC
),
6701 GEN_HANDLER(vmladduhm
, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC
),
6702 #if defined(TARGET_PPC64)
6703 GEN_HANDLER_E(maddhd_maddhdu
, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE
,
6705 GEN_HANDLER_E(maddld
, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE
, PPC2_ISA300
),
6708 #undef GEN_INT_ARITH_ADD
6709 #undef GEN_INT_ARITH_ADD_CONST
6710 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
6711 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
6712 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
6713 add_ca, compute_ca, compute_ov) \
6714 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
6715 GEN_INT_ARITH_ADD(add
, 0x08, 0, 0, 0)
6716 GEN_INT_ARITH_ADD(addo
, 0x18, 0, 0, 1)
6717 GEN_INT_ARITH_ADD(addc
, 0x00, 0, 1, 0)
6718 GEN_INT_ARITH_ADD(addco
, 0x10, 0, 1, 1)
6719 GEN_INT_ARITH_ADD(adde
, 0x04, 1, 1, 0)
6720 GEN_INT_ARITH_ADD(addeo
, 0x14, 1, 1, 1)
6721 GEN_INT_ARITH_ADD_CONST(addme
, 0x07, -1LL, 1, 1, 0)
6722 GEN_INT_ARITH_ADD_CONST(addmeo
, 0x17, -1LL, 1, 1, 1)
6723 GEN_INT_ARITH_ADD_CONST(addze
, 0x06, 0, 1, 1, 0)
6724 GEN_INT_ARITH_ADD_CONST(addzeo
, 0x16, 0, 1, 1, 1)
6726 #undef GEN_INT_ARITH_DIVW
6727 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
6728 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
6729 GEN_INT_ARITH_DIVW(divwu
, 0x0E, 0, 0),
6730 GEN_INT_ARITH_DIVW(divwuo
, 0x1E, 0, 1),
6731 GEN_INT_ARITH_DIVW(divw
, 0x0F, 1, 0),
6732 GEN_INT_ARITH_DIVW(divwo
, 0x1F, 1, 1),
6733 GEN_HANDLER_E(divwe
, 0x1F, 0x0B, 0x0D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
6734 GEN_HANDLER_E(divweo
, 0x1F, 0x0B, 0x1D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
6735 GEN_HANDLER_E(divweu
, 0x1F, 0x0B, 0x0C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
6736 GEN_HANDLER_E(divweuo
, 0x1F, 0x0B, 0x1C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
6737 GEN_HANDLER_E(modsw
, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE
, PPC2_ISA300
),
6738 GEN_HANDLER_E(moduw
, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE
, PPC2_ISA300
),
6740 #if defined(TARGET_PPC64)
6741 #undef GEN_INT_ARITH_DIVD
6742 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
6743 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6744 GEN_INT_ARITH_DIVD(divdu
, 0x0E, 0, 0),
6745 GEN_INT_ARITH_DIVD(divduo
, 0x1E, 0, 1),
6746 GEN_INT_ARITH_DIVD(divd
, 0x0F, 1, 0),
6747 GEN_INT_ARITH_DIVD(divdo
, 0x1F, 1, 1),
6749 GEN_HANDLER_E(divdeu
, 0x1F, 0x09, 0x0C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
6750 GEN_HANDLER_E(divdeuo
, 0x1F, 0x09, 0x1C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
6751 GEN_HANDLER_E(divde
, 0x1F, 0x09, 0x0D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
6752 GEN_HANDLER_E(divdeo
, 0x1F, 0x09, 0x1D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
6753 GEN_HANDLER_E(modsd
, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE
, PPC2_ISA300
),
6754 GEN_HANDLER_E(modud
, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE
, PPC2_ISA300
),
6756 #undef GEN_INT_ARITH_MUL_HELPER
6757 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
6758 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6759 GEN_INT_ARITH_MUL_HELPER(mulhdu
, 0x00),
6760 GEN_INT_ARITH_MUL_HELPER(mulhd
, 0x02),
6761 GEN_INT_ARITH_MUL_HELPER(mulldo
, 0x17),
6764 #undef GEN_INT_ARITH_SUBF
6765 #undef GEN_INT_ARITH_SUBF_CONST
6766 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
6767 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
6768 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
6769 add_ca, compute_ca, compute_ov) \
6770 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
6771 GEN_INT_ARITH_SUBF(subf
, 0x01, 0, 0, 0)
6772 GEN_INT_ARITH_SUBF(subfo
, 0x11, 0, 0, 1)
6773 GEN_INT_ARITH_SUBF(subfc
, 0x00, 0, 1, 0)
6774 GEN_INT_ARITH_SUBF(subfco
, 0x10, 0, 1, 1)
6775 GEN_INT_ARITH_SUBF(subfe
, 0x04, 1, 1, 0)
6776 GEN_INT_ARITH_SUBF(subfeo
, 0x14, 1, 1, 1)
6777 GEN_INT_ARITH_SUBF_CONST(subfme
, 0x07, -1LL, 1, 1, 0)
6778 GEN_INT_ARITH_SUBF_CONST(subfmeo
, 0x17, -1LL, 1, 1, 1)
6779 GEN_INT_ARITH_SUBF_CONST(subfze
, 0x06, 0, 1, 1, 0)
6780 GEN_INT_ARITH_SUBF_CONST(subfzeo
, 0x16, 0, 1, 1, 1)
6784 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
6785 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
6786 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
6787 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
6788 GEN_LOGICAL2(and, tcg_gen_and_tl
, 0x00, PPC_INTEGER
),
6789 GEN_LOGICAL2(andc
, tcg_gen_andc_tl
, 0x01, PPC_INTEGER
),
6790 GEN_LOGICAL2(eqv
, tcg_gen_eqv_tl
, 0x08, PPC_INTEGER
),
6791 GEN_LOGICAL1(extsb
, tcg_gen_ext8s_tl
, 0x1D, PPC_INTEGER
),
6792 GEN_LOGICAL1(extsh
, tcg_gen_ext16s_tl
, 0x1C, PPC_INTEGER
),
6793 GEN_LOGICAL2(nand
, tcg_gen_nand_tl
, 0x0E, PPC_INTEGER
),
6794 GEN_LOGICAL2(nor
, tcg_gen_nor_tl
, 0x03, PPC_INTEGER
),
6795 GEN_LOGICAL2(orc
, tcg_gen_orc_tl
, 0x0C, PPC_INTEGER
),
6796 #if defined(TARGET_PPC64)
6797 GEN_LOGICAL1(extsw
, tcg_gen_ext32s_tl
, 0x1E, PPC_64B
),
6800 #if defined(TARGET_PPC64)
6803 #define GEN_PPC64_R2(name, opc1, opc2) \
6804 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6805 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6807 #define GEN_PPC64_R4(name, opc1, opc2) \
6808 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6809 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
6811 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6813 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
6815 GEN_PPC64_R4(rldicl
, 0x1E, 0x00),
6816 GEN_PPC64_R4(rldicr
, 0x1E, 0x02),
6817 GEN_PPC64_R4(rldic
, 0x1E, 0x04),
6818 GEN_PPC64_R2(rldcl
, 0x1E, 0x08),
6819 GEN_PPC64_R2(rldcr
, 0x1E, 0x09),
6820 GEN_PPC64_R4(rldimi
, 0x1E, 0x06),
6828 #define GEN_LD(name, ldop, opc, type) \
6829 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6830 #define GEN_LDU(name, ldop, opc, type) \
6831 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
6832 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
6833 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6834 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
6835 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6836 #define GEN_LDS(name, ldop, op, type) \
6837 GEN_LD(name, ldop, op | 0x20, type) \
6838 GEN_LDU(name, ldop, op | 0x21, type) \
6839 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
6840 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
6842 GEN_LDS(lbz
, ld8u
, 0x02, PPC_INTEGER
)
6843 GEN_LDS(lha
, ld16s
, 0x0A, PPC_INTEGER
)
6844 GEN_LDS(lhz
, ld16u
, 0x08, PPC_INTEGER
)
6845 GEN_LDS(lwz
, ld32u
, 0x00, PPC_INTEGER
)
6846 #if defined(TARGET_PPC64)
6847 GEN_LDUX(lwa
, ld32s
, 0x15, 0x0B, PPC_64B
)
6848 GEN_LDX(lwa
, ld32s
, 0x15, 0x0A, PPC_64B
)
6849 GEN_LDUX(ld
, ld64_i64
, 0x15, 0x01, PPC_64B
)
6850 GEN_LDX(ld
, ld64_i64
, 0x15, 0x00, PPC_64B
)
6851 GEN_LDX_E(ldbr
, ld64ur_i64
, 0x14, 0x10, PPC_NONE
, PPC2_DBRX
, CHK_NONE
)
6853 /* HV/P7 and later only */
6854 GEN_LDX_HVRM(ldcix
, ld64_i64
, 0x15, 0x1b, PPC_CILDST
)
6855 GEN_LDX_HVRM(lwzcix
, ld32u
, 0x15, 0x18, PPC_CILDST
)
6856 GEN_LDX_HVRM(lhzcix
, ld16u
, 0x15, 0x19, PPC_CILDST
)
6857 GEN_LDX_HVRM(lbzcix
, ld8u
, 0x15, 0x1a, PPC_CILDST
)
6859 GEN_LDX(lhbr
, ld16ur
, 0x16, 0x18, PPC_INTEGER
)
6860 GEN_LDX(lwbr
, ld32ur
, 0x16, 0x10, PPC_INTEGER
)
6867 #define GEN_ST(name, stop, opc, type) \
6868 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6869 #define GEN_STU(name, stop, opc, type) \
6870 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
6871 #define GEN_STUX(name, stop, opc2, opc3, type) \
6872 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6873 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
6874 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6875 #define GEN_STS(name, stop, op, type) \
6876 GEN_ST(name, stop, op | 0x20, type) \
6877 GEN_STU(name, stop, op | 0x21, type) \
6878 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
6879 GEN_STX(name, stop, 0x17, op | 0x00, type)
6881 GEN_STS(stb
, st8
, 0x06, PPC_INTEGER
)
6882 GEN_STS(sth
, st16
, 0x0C, PPC_INTEGER
)
6883 GEN_STS(stw
, st32
, 0x04, PPC_INTEGER
)
6884 #if defined(TARGET_PPC64)
6885 GEN_STUX(std
, st64_i64
, 0x15, 0x05, PPC_64B
)
6886 GEN_STX(std
, st64_i64
, 0x15, 0x04, PPC_64B
)
6887 GEN_STX_E(stdbr
, st64r_i64
, 0x14, 0x14, PPC_NONE
, PPC2_DBRX
, CHK_NONE
)
6888 GEN_STX_HVRM(stdcix
, st64_i64
, 0x15, 0x1f, PPC_CILDST
)
6889 GEN_STX_HVRM(stwcix
, st32
, 0x15, 0x1c, PPC_CILDST
)
6890 GEN_STX_HVRM(sthcix
, st16
, 0x15, 0x1d, PPC_CILDST
)
6891 GEN_STX_HVRM(stbcix
, st8
, 0x15, 0x1e, PPC_CILDST
)
6893 GEN_STX(sthbr
, st16r
, 0x16, 0x1C, PPC_INTEGER
)
6894 GEN_STX(stwbr
, st32r
, 0x16, 0x14, PPC_INTEGER
)
6897 #define GEN_CRLOGIC(name, tcg_op, opc) \
6898 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
6899 GEN_CRLOGIC(crand
, tcg_gen_and_i32
, 0x08),
6900 GEN_CRLOGIC(crandc
, tcg_gen_andc_i32
, 0x04),
6901 GEN_CRLOGIC(creqv
, tcg_gen_eqv_i32
, 0x09),
6902 GEN_CRLOGIC(crnand
, tcg_gen_nand_i32
, 0x07),
6903 GEN_CRLOGIC(crnor
, tcg_gen_nor_i32
, 0x01),
6904 GEN_CRLOGIC(cror
, tcg_gen_or_i32
, 0x0E),
6905 GEN_CRLOGIC(crorc
, tcg_gen_orc_i32
, 0x0D),
6906 GEN_CRLOGIC(crxor
, tcg_gen_xor_i32
, 0x06),
6908 #undef GEN_MAC_HANDLER
6909 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6910 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
6911 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05),
6912 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15),
6913 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07),
6914 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17),
6915 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06),
6916 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16),
6917 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04),
6918 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14),
6919 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01),
6920 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11),
6921 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03),
6922 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13),
6923 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02),
6924 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12),
6925 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00),
6926 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10),
6927 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D),
6928 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D),
6929 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F),
6930 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F),
6931 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C),
6932 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C),
6933 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E),
6934 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E),
6935 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05),
6936 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15),
6937 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07),
6938 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17),
6939 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01),
6940 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11),
6941 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03),
6942 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13),
6943 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D),
6944 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D),
6945 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F),
6946 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F),
6947 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05),
6948 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04),
6949 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01),
6950 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00),
6951 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D),
6952 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C),
6954 GEN_HANDLER2_E(tbegin
, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
6956 GEN_HANDLER2_E(tend
, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
6958 GEN_HANDLER2_E(tabort
, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
6960 GEN_HANDLER2_E(tabortwc
, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
6962 GEN_HANDLER2_E(tabortwci
, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
6964 GEN_HANDLER2_E(tabortdc
, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
6966 GEN_HANDLER2_E(tabortdci
, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
6968 GEN_HANDLER2_E(tsr
, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
6970 GEN_HANDLER2_E(tcheck
, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
6972 GEN_HANDLER2_E(treclaim
, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
6974 GEN_HANDLER2_E(trechkpt
, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
6977 #include "translate/fp-ops.inc.c"
6979 #include "translate/vmx-ops.inc.c"
6981 #include "translate/vsx-ops.inc.c"
6983 #include "translate/dfp-ops.inc.c"
6985 #include "translate/spe-ops.inc.c"
6988 #include "helper_regs.h"
6989 #include "translate_init.c"
6991 /*****************************************************************************/
6992 /* Misc PowerPC helpers */
6993 void ppc_cpu_dump_state(CPUState
*cs
, FILE *f
, fprintf_function cpu_fprintf
,
6999 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
7000 CPUPPCState
*env
= &cpu
->env
;
7003 cpu_fprintf(f
, "NIP " TARGET_FMT_lx
" LR " TARGET_FMT_lx
" CTR "
7004 TARGET_FMT_lx
" XER " TARGET_FMT_lx
" CPU#%d\n",
7005 env
->nip
, env
->lr
, env
->ctr
, cpu_read_xer(env
),
7007 cpu_fprintf(f
, "MSR " TARGET_FMT_lx
" HID0 " TARGET_FMT_lx
" HF "
7008 TARGET_FMT_lx
" iidx %d didx %d\n",
7009 env
->msr
, env
->spr
[SPR_HID0
],
7010 env
->hflags
, env
->immu_idx
, env
->dmmu_idx
);
7011 #if !defined(NO_TIMER_DUMP)
7012 cpu_fprintf(f
, "TB %08" PRIu32
" %08" PRIu64
7013 #if !defined(CONFIG_USER_ONLY)
7017 cpu_ppc_load_tbu(env
), cpu_ppc_load_tbl(env
)
7018 #if !defined(CONFIG_USER_ONLY)
7019 , cpu_ppc_load_decr(env
)
7023 for (i
= 0; i
< 32; i
++) {
7024 if ((i
& (RGPL
- 1)) == 0)
7025 cpu_fprintf(f
, "GPR%02d", i
);
7026 cpu_fprintf(f
, " %016" PRIx64
, ppc_dump_gpr(env
, i
));
7027 if ((i
& (RGPL
- 1)) == (RGPL
- 1))
7028 cpu_fprintf(f
, "\n");
7030 cpu_fprintf(f
, "CR ");
7031 for (i
= 0; i
< 8; i
++)
7032 cpu_fprintf(f
, "%01x", env
->crf
[i
]);
7033 cpu_fprintf(f
, " [");
7034 for (i
= 0; i
< 8; i
++) {
7036 if (env
->crf
[i
] & 0x08)
7038 else if (env
->crf
[i
] & 0x04)
7040 else if (env
->crf
[i
] & 0x02)
7042 cpu_fprintf(f
, " %c%c", a
, env
->crf
[i
] & 0x01 ? 'O' : ' ');
7044 cpu_fprintf(f
, " ] RES " TARGET_FMT_lx
"\n",
7046 for (i
= 0; i
< 32; i
++) {
7047 if ((i
& (RFPL
- 1)) == 0)
7048 cpu_fprintf(f
, "FPR%02d", i
);
7049 cpu_fprintf(f
, " %016" PRIx64
, *((uint64_t *)&env
->fpr
[i
]));
7050 if ((i
& (RFPL
- 1)) == (RFPL
- 1))
7051 cpu_fprintf(f
, "\n");
7053 cpu_fprintf(f
, "FPSCR " TARGET_FMT_lx
"\n", env
->fpscr
);
7054 #if !defined(CONFIG_USER_ONLY)
7055 cpu_fprintf(f
, " SRR0 " TARGET_FMT_lx
" SRR1 " TARGET_FMT_lx
7056 " PVR " TARGET_FMT_lx
" VRSAVE " TARGET_FMT_lx
"\n",
7057 env
->spr
[SPR_SRR0
], env
->spr
[SPR_SRR1
],
7058 env
->spr
[SPR_PVR
], env
->spr
[SPR_VRSAVE
]);
7060 cpu_fprintf(f
, "SPRG0 " TARGET_FMT_lx
" SPRG1 " TARGET_FMT_lx
7061 " SPRG2 " TARGET_FMT_lx
" SPRG3 " TARGET_FMT_lx
"\n",
7062 env
->spr
[SPR_SPRG0
], env
->spr
[SPR_SPRG1
],
7063 env
->spr
[SPR_SPRG2
], env
->spr
[SPR_SPRG3
]);
7065 cpu_fprintf(f
, "SPRG4 " TARGET_FMT_lx
" SPRG5 " TARGET_FMT_lx
7066 " SPRG6 " TARGET_FMT_lx
" SPRG7 " TARGET_FMT_lx
"\n",
7067 env
->spr
[SPR_SPRG4
], env
->spr
[SPR_SPRG5
],
7068 env
->spr
[SPR_SPRG6
], env
->spr
[SPR_SPRG7
]);
7070 #if defined(TARGET_PPC64)
7071 if (env
->excp_model
== POWERPC_EXCP_POWER7
||
7072 env
->excp_model
== POWERPC_EXCP_POWER8
) {
7073 cpu_fprintf(f
, "HSRR0 " TARGET_FMT_lx
" HSRR1 " TARGET_FMT_lx
"\n",
7074 env
->spr
[SPR_HSRR0
], env
->spr
[SPR_HSRR1
]);
7077 if (env
->excp_model
== POWERPC_EXCP_BOOKE
) {
7078 cpu_fprintf(f
, "CSRR0 " TARGET_FMT_lx
" CSRR1 " TARGET_FMT_lx
7079 " MCSRR0 " TARGET_FMT_lx
" MCSRR1 " TARGET_FMT_lx
"\n",
7080 env
->spr
[SPR_BOOKE_CSRR0
], env
->spr
[SPR_BOOKE_CSRR1
],
7081 env
->spr
[SPR_BOOKE_MCSRR0
], env
->spr
[SPR_BOOKE_MCSRR1
]);
7083 cpu_fprintf(f
, " TCR " TARGET_FMT_lx
" TSR " TARGET_FMT_lx
7084 " ESR " TARGET_FMT_lx
" DEAR " TARGET_FMT_lx
"\n",
7085 env
->spr
[SPR_BOOKE_TCR
], env
->spr
[SPR_BOOKE_TSR
],
7086 env
->spr
[SPR_BOOKE_ESR
], env
->spr
[SPR_BOOKE_DEAR
]);
7088 cpu_fprintf(f
, " PIR " TARGET_FMT_lx
" DECAR " TARGET_FMT_lx
7089 " IVPR " TARGET_FMT_lx
" EPCR " TARGET_FMT_lx
"\n",
7090 env
->spr
[SPR_BOOKE_PIR
], env
->spr
[SPR_BOOKE_DECAR
],
7091 env
->spr
[SPR_BOOKE_IVPR
], env
->spr
[SPR_BOOKE_EPCR
]);
7093 cpu_fprintf(f
, " MCSR " TARGET_FMT_lx
" SPRG8 " TARGET_FMT_lx
7094 " EPR " TARGET_FMT_lx
"\n",
7095 env
->spr
[SPR_BOOKE_MCSR
], env
->spr
[SPR_BOOKE_SPRG8
],
7096 env
->spr
[SPR_BOOKE_EPR
]);
7099 cpu_fprintf(f
, " MCAR " TARGET_FMT_lx
" PID1 " TARGET_FMT_lx
7100 " PID2 " TARGET_FMT_lx
" SVR " TARGET_FMT_lx
"\n",
7101 env
->spr
[SPR_Exxx_MCAR
], env
->spr
[SPR_BOOKE_PID1
],
7102 env
->spr
[SPR_BOOKE_PID2
], env
->spr
[SPR_E500_SVR
]);
7105 * IVORs are left out as they are large and do not change often --
7106 * they can be read with "p $ivor0", "p $ivor1", etc.
7110 #if defined(TARGET_PPC64)
7111 if (env
->flags
& POWERPC_FLAG_CFAR
) {
7112 cpu_fprintf(f
, " CFAR " TARGET_FMT_lx
"\n", env
->cfar
);
7116 if (env
->spr_cb
[SPR_LPCR
].name
)
7117 cpu_fprintf(f
, " LPCR " TARGET_FMT_lx
"\n", env
->spr
[SPR_LPCR
]);
7119 switch (POWERPC_MMU_VER(env
->mmu_model
)) {
7120 case POWERPC_MMU_32B
:
7121 case POWERPC_MMU_601
:
7122 case POWERPC_MMU_SOFT_6xx
:
7123 case POWERPC_MMU_SOFT_74xx
:
7124 #if defined(TARGET_PPC64)
7125 case POWERPC_MMU_VER_64B
:
7126 case POWERPC_MMU_VER_2_03
:
7127 case POWERPC_MMU_VER_2_06
:
7128 case POWERPC_MMU_VER_2_07
:
7129 case POWERPC_MMU_VER_3_00
:
7131 if (env
->spr_cb
[SPR_SDR1
].name
) { /* SDR1 Exists */
7132 cpu_fprintf(f
, " SDR1 " TARGET_FMT_lx
" ", env
->spr
[SPR_SDR1
]);
7134 cpu_fprintf(f
, " DAR " TARGET_FMT_lx
" DSISR " TARGET_FMT_lx
"\n",
7135 env
->spr
[SPR_DAR
], env
->spr
[SPR_DSISR
]);
7137 case POWERPC_MMU_BOOKE206
:
7138 cpu_fprintf(f
, " MAS0 " TARGET_FMT_lx
" MAS1 " TARGET_FMT_lx
7139 " MAS2 " TARGET_FMT_lx
" MAS3 " TARGET_FMT_lx
"\n",
7140 env
->spr
[SPR_BOOKE_MAS0
], env
->spr
[SPR_BOOKE_MAS1
],
7141 env
->spr
[SPR_BOOKE_MAS2
], env
->spr
[SPR_BOOKE_MAS3
]);
7143 cpu_fprintf(f
, " MAS4 " TARGET_FMT_lx
" MAS6 " TARGET_FMT_lx
7144 " MAS7 " TARGET_FMT_lx
" PID " TARGET_FMT_lx
"\n",
7145 env
->spr
[SPR_BOOKE_MAS4
], env
->spr
[SPR_BOOKE_MAS6
],
7146 env
->spr
[SPR_BOOKE_MAS7
], env
->spr
[SPR_BOOKE_PID
]);
7148 cpu_fprintf(f
, "MMUCFG " TARGET_FMT_lx
" TLB0CFG " TARGET_FMT_lx
7149 " TLB1CFG " TARGET_FMT_lx
"\n",
7150 env
->spr
[SPR_MMUCFG
], env
->spr
[SPR_BOOKE_TLB0CFG
],
7151 env
->spr
[SPR_BOOKE_TLB1CFG
]);
7162 void ppc_cpu_dump_statistics(CPUState
*cs
, FILE*f
,
7163 fprintf_function cpu_fprintf
, int flags
)
7165 #if defined(DO_PPC_STATISTICS)
7166 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
7167 opc_handler_t
**t1
, **t2
, **t3
, *handler
;
7170 t1
= cpu
->env
.opcodes
;
7171 for (op1
= 0; op1
< 64; op1
++) {
7173 if (is_indirect_opcode(handler
)) {
7174 t2
= ind_table(handler
);
7175 for (op2
= 0; op2
< 32; op2
++) {
7177 if (is_indirect_opcode(handler
)) {
7178 t3
= ind_table(handler
);
7179 for (op3
= 0; op3
< 32; op3
++) {
7181 if (handler
->count
== 0)
7183 cpu_fprintf(f
, "%02x %02x %02x (%02x %04d) %16s: "
7184 "%016" PRIx64
" %" PRId64
"\n",
7185 op1
, op2
, op3
, op1
, (op3
<< 5) | op2
,
7187 handler
->count
, handler
->count
);
7190 if (handler
->count
== 0)
7192 cpu_fprintf(f
, "%02x %02x (%02x %04d) %16s: "
7193 "%016" PRIx64
" %" PRId64
"\n",
7194 op1
, op2
, op1
, op2
, handler
->oname
,
7195 handler
->count
, handler
->count
);
7199 if (handler
->count
== 0)
7201 cpu_fprintf(f
, "%02x (%02x ) %16s: %016" PRIx64
7203 op1
, op1
, handler
->oname
,
7204 handler
->count
, handler
->count
);
7210 /*****************************************************************************/
7211 void gen_intermediate_code(CPUState
*cs
, struct TranslationBlock
*tb
)
7213 CPUPPCState
*env
= cs
->env_ptr
;
7214 DisasContext ctx
, *ctxp
= &ctx
;
7215 opc_handler_t
**table
, *handler
;
7216 target_ulong pc_start
;
7223 ctx
.exception
= POWERPC_EXCP_NONE
;
7224 ctx
.spr_cb
= env
->spr_cb
;
7226 ctx
.mem_idx
= env
->dmmu_idx
;
7228 #if !defined(CONFIG_USER_ONLY)
7229 ctx
.hv
= msr_hv
|| !env
->has_hv_mode
;
7231 ctx
.insns_flags
= env
->insns_flags
;
7232 ctx
.insns_flags2
= env
->insns_flags2
;
7233 ctx
.access_type
= -1;
7234 ctx
.need_access_type
= !(env
->mmu_model
& POWERPC_MMU_64B
);
7235 ctx
.le_mode
= !!(env
->hflags
& (1 << MSR_LE
));
7236 ctx
.default_tcg_memop_mask
= ctx
.le_mode
? MO_LE
: MO_BE
;
7237 #if defined(TARGET_PPC64)
7238 ctx
.sf_mode
= msr_is_64bit(env
, env
->msr
);
7239 ctx
.has_cfar
= !!(env
->flags
& POWERPC_FLAG_CFAR
);
7241 if (env
->mmu_model
== POWERPC_MMU_32B
||
7242 env
->mmu_model
== POWERPC_MMU_601
||
7243 (env
->mmu_model
& POWERPC_MMU_64B
))
7244 ctx
.lazy_tlb_flush
= true;
7246 ctx
.fpu_enabled
= !!msr_fp
;
7247 if ((env
->flags
& POWERPC_FLAG_SPE
) && msr_spe
)
7248 ctx
.spe_enabled
= !!msr_spe
;
7250 ctx
.spe_enabled
= false;
7251 if ((env
->flags
& POWERPC_FLAG_VRE
) && msr_vr
)
7252 ctx
.altivec_enabled
= !!msr_vr
;
7254 ctx
.altivec_enabled
= false;
7255 if ((env
->flags
& POWERPC_FLAG_VSX
) && msr_vsx
) {
7256 ctx
.vsx_enabled
= !!msr_vsx
;
7258 ctx
.vsx_enabled
= false;
7260 #if defined(TARGET_PPC64)
7261 if ((env
->flags
& POWERPC_FLAG_TM
) && msr_tm
) {
7262 ctx
.tm_enabled
= !!msr_tm
;
7264 ctx
.tm_enabled
= false;
7267 ctx
.gtse
= !!(env
->spr
[SPR_LPCR
] & LPCR_GTSE
);
7268 if ((env
->flags
& POWERPC_FLAG_SE
) && msr_se
)
7269 ctx
.singlestep_enabled
= CPU_SINGLE_STEP
;
7271 ctx
.singlestep_enabled
= 0;
7272 if ((env
->flags
& POWERPC_FLAG_BE
) && msr_be
)
7273 ctx
.singlestep_enabled
|= CPU_BRANCH_STEP
;
7274 if (unlikely(cs
->singlestep_enabled
)) {
7275 ctx
.singlestep_enabled
|= GDBSTUB_SINGLE_STEP
;
7277 #if defined (DO_SINGLE_STEP) && 0
7278 /* Single step trace mode */
7282 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
7283 if (max_insns
== 0) {
7284 max_insns
= CF_COUNT_MASK
;
7286 if (max_insns
> TCG_MAX_INSNS
) {
7287 max_insns
= TCG_MAX_INSNS
;
7291 tcg_clear_temp_count();
7292 /* Set env in case of segfault during code fetch */
7293 while (ctx
.exception
== POWERPC_EXCP_NONE
&& !tcg_op_buf_full()) {
7294 tcg_gen_insn_start(ctx
.nip
);
7297 if (unlikely(cpu_breakpoint_test(cs
, ctx
.nip
, BP_ANY
))) {
7298 gen_debug_exception(ctxp
);
7299 /* The address covered by the breakpoint must be included in
7300 [tb->pc, tb->pc + tb->size) in order to for it to be
7301 properly cleared -- thus we increment the PC here so that
7302 the logic setting tb->size below does the right thing. */
7307 LOG_DISAS("----------------\n");
7308 LOG_DISAS("nip=" TARGET_FMT_lx
" super=%d ir=%d\n",
7309 ctx
.nip
, ctx
.mem_idx
, (int)msr_ir
);
7310 if (num_insns
== max_insns
&& (tb
->cflags
& CF_LAST_IO
))
7312 if (unlikely(need_byteswap(&ctx
))) {
7313 ctx
.opcode
= bswap32(cpu_ldl_code(env
, ctx
.nip
));
7315 ctx
.opcode
= cpu_ldl_code(env
, ctx
.nip
);
7317 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
7318 ctx
.opcode
, opc1(ctx
.opcode
), opc2(ctx
.opcode
),
7319 opc3(ctx
.opcode
), opc4(ctx
.opcode
),
7320 ctx
.le_mode
? "little" : "big");
7322 table
= env
->opcodes
;
7323 handler
= table
[opc1(ctx
.opcode
)];
7324 if (is_indirect_opcode(handler
)) {
7325 table
= ind_table(handler
);
7326 handler
= table
[opc2(ctx
.opcode
)];
7327 if (is_indirect_opcode(handler
)) {
7328 table
= ind_table(handler
);
7329 handler
= table
[opc3(ctx
.opcode
)];
7330 if (is_indirect_opcode(handler
)) {
7331 table
= ind_table(handler
);
7332 handler
= table
[opc4(ctx
.opcode
)];
7336 /* Is opcode *REALLY* valid ? */
7337 if (unlikely(handler
->handler
== &gen_invalid
)) {
7338 qemu_log_mask(LOG_GUEST_ERROR
, "invalid/unsupported opcode: "
7339 "%02x - %02x - %02x - %02x (%08x) "
7340 TARGET_FMT_lx
" %d\n",
7341 opc1(ctx
.opcode
), opc2(ctx
.opcode
),
7342 opc3(ctx
.opcode
), opc4(ctx
.opcode
),
7343 ctx
.opcode
, ctx
.nip
- 4, (int)msr_ir
);
7347 if (unlikely(handler
->type
& (PPC_SPE
| PPC_SPE_SINGLE
| PPC_SPE_DOUBLE
) && Rc(ctx
.opcode
))) {
7348 inval
= handler
->inval2
;
7350 inval
= handler
->inval1
;
7353 if (unlikely((ctx
.opcode
& inval
) != 0)) {
7354 qemu_log_mask(LOG_GUEST_ERROR
, "invalid bits: %08x for opcode: "
7355 "%02x - %02x - %02x - %02x (%08x) "
7356 TARGET_FMT_lx
"\n", ctx
.opcode
& inval
,
7357 opc1(ctx
.opcode
), opc2(ctx
.opcode
),
7358 opc3(ctx
.opcode
), opc4(ctx
.opcode
),
7359 ctx
.opcode
, ctx
.nip
- 4);
7360 gen_inval_exception(ctxp
, POWERPC_EXCP_INVAL_INVAL
);
7364 (*(handler
->handler
))(&ctx
);
7365 #if defined(DO_PPC_STATISTICS)
7368 /* Check trace mode exceptions */
7369 if (unlikely(ctx
.singlestep_enabled
& CPU_SINGLE_STEP
&&
7370 (ctx
.nip
<= 0x100 || ctx
.nip
> 0xF00) &&
7371 ctx
.exception
!= POWERPC_SYSCALL
&&
7372 ctx
.exception
!= POWERPC_EXCP_TRAP
&&
7373 ctx
.exception
!= POWERPC_EXCP_BRANCH
)) {
7374 gen_exception_nip(ctxp
, POWERPC_EXCP_TRACE
, ctx
.nip
);
7375 } else if (unlikely(((ctx
.nip
& (TARGET_PAGE_SIZE
- 1)) == 0) ||
7376 (cs
->singlestep_enabled
) ||
7378 num_insns
>= max_insns
)) {
7379 /* if we reach a page boundary or are single stepping, stop
7384 if (tcg_check_temp_count()) {
7385 fprintf(stderr
, "Opcode %02x %02x %02x %02x (%08x) leaked "
7386 "temporaries\n", opc1(ctx
.opcode
), opc2(ctx
.opcode
),
7387 opc3(ctx
.opcode
), opc4(ctx
.opcode
), ctx
.opcode
);
7391 if (tb
->cflags
& CF_LAST_IO
)
7393 if (ctx
.exception
== POWERPC_EXCP_NONE
) {
7394 gen_goto_tb(&ctx
, 0, ctx
.nip
);
7395 } else if (ctx
.exception
!= POWERPC_EXCP_BRANCH
) {
7396 if (unlikely(cs
->singlestep_enabled
)) {
7397 gen_debug_exception(ctxp
);
7399 /* Generate the return instruction */
7402 gen_tb_end(tb
, num_insns
);
7404 tb
->size
= ctx
.nip
- pc_start
;
7405 tb
->icount
= num_insns
;
7407 #if defined(DEBUG_DISAS)
7408 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)
7409 && qemu_log_in_addr_range(pc_start
)) {
7411 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
7412 log_target_disas(cs
, pc_start
, ctx
.nip
- pc_start
, 0);
7419 void restore_state_to_opc(CPUPPCState
*env
, TranslationBlock
*tb
,