hw/xilinx_uartlite.c

   1 /*
   2  * QEMU model of Xilinx uartlite.
   3  *
   4  * Copyright (c) 2009 Edgar E. Iglesias.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "sysbus.h"
  26 #include "qemu-char.h"
  27
  28 #define DUART(x)
  29
  30 #define R_RX            0
  31 #define R_TX            1
  32 #define R_STATUS        2
  33 #define R_CTRL          3
  34 #define R_MAX           4
  35
  36 #define STATUS_RXVALID    0x01
  37 #define STATUS_RXFULL     0x02
  38 #define STATUS_TXEMPTY    0x04
  39 #define STATUS_TXFULL     0x08
  40 #define STATUS_IE         0x10
  41 #define STATUS_OVERRUN    0x20
  42 #define STATUS_FRAME      0x40
  43 #define STATUS_PARITY     0x80
  44
  45 #define CONTROL_RST_TX    0x01
  46 #define CONTROL_RST_RX    0x02
  47 #define CONTROL_IE        0x10
  48
  49 struct xlx_uartlite
  50 {
  51     SysBusDevice busdev;
  52     MemoryRegion mmio;
  53     CharDriverState *chr;
  54     qemu_irq irq;
  55
  56     uint8_t rx_fifo[8];
  57     unsigned int rx_fifo_pos;
  58     unsigned int rx_fifo_len;
  59
  60     uint32_t regs[R_MAX];
  61 };
  62
  63 static void uart_update_irq(struct xlx_uartlite *s)
  64 {
  65     unsigned int irq;
  66
  67     if (s->rx_fifo_len)
  68         s->regs[R_STATUS] |= STATUS_IE;
  69
  70     irq = (s->regs[R_STATUS] & STATUS_IE) && (s->regs[R_CTRL] & CONTROL_IE);
  71     qemu_set_irq(s->irq, irq);
  72 }
  73
  74 static void uart_update_status(struct xlx_uartlite *s)
  75 {
  76     uint32_t r;
  77
  78     r = s->regs[R_STATUS];
  79     r &= ~7;
  80     r |= 1 << 2; /* Tx fifo is always empty. We are fast :) */
  81     r |= (s->rx_fifo_len == sizeof (s->rx_fifo)) << 1;
  82     r |= (!!s->rx_fifo_len);
  83     s->regs[R_STATUS] = r;
  84 }
  85
  86 static uint64_t
  87 uart_read(void *opaque, target_phys_addr_t addr, unsigned int size)
  88 {
  89     struct xlx_uartlite *s = opaque;
  90     uint32_t r = 0;
  91     addr >>= 2;
  92     switch (addr)
  93     {
  94         case R_RX:
  95             r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 7];
  96             if (s->rx_fifo_len)
  97                 s->rx_fifo_len--;
  98             uart_update_status(s);
  99             uart_update_irq(s);
 100             break;
 101
 102         default:
 103             if (addr < ARRAY_SIZE(s->regs))
 104                 r = s->regs[addr];
 105             DUART(qemu_log("%s addr=%x v=%x\n", __func__, addr, r));
 106             break;
 107     }
 108     return r;
 109 }
 110
 111 static void
 112 uart_write(void *opaque, target_phys_addr_t addr,
 113            uint64_t val64, unsigned int size)
 114 {
 115     struct xlx_uartlite *s = opaque;
 116     uint32_t value = val64;
 117     unsigned char ch = value;
 118
 119     addr >>= 2;
 120     switch (addr)
 121     {
 122         case R_STATUS:
 123             hw_error("write to UART STATUS?\n");
 124             break;
 125
 126         case R_CTRL:
 127             if (value & CONTROL_RST_RX) {
 128                 s->rx_fifo_pos = 0;
 129                 s->rx_fifo_len = 0;
 130             }
 131             s->regs[addr] = value;
 132             break;
 133
 134         case R_TX:
 135             if (s->chr)
 136                 qemu_chr_fe_write(s->chr, &ch, 1);
 137
 138             s->regs[addr] = value;
 139
 140             /* hax.  */
 141             s->regs[R_STATUS] |= STATUS_IE;
 142             break;
 143
 144         default:
 145             DUART(printf("%s addr=%x v=%x\n", __func__, addr, value));
 146             if (addr < ARRAY_SIZE(s->regs))
 147                 s->regs[addr] = value;
 148             break;
 149     }
 150     uart_update_status(s);
 151     uart_update_irq(s);
 152 }
 153
 154 static const MemoryRegionOps uart_ops = {
 155     .read = uart_read,
 156     .write = uart_write,
 157     .endianness = DEVICE_NATIVE_ENDIAN,
 158     .valid = {
 159         .min_access_size = 1,
 160         .max_access_size = 4
 161     }
 162 };
 163
 164 static void uart_rx(void *opaque, const uint8_t *buf, int size)
 165 {
 166     struct xlx_uartlite *s = opaque;
 167
 168     /* Got a byte.  */
 169     if (s->rx_fifo_len >= 8) {
 170         printf("WARNING: UART dropped char.\n");
 171         return;
 172     }
 173     s->rx_fifo[s->rx_fifo_pos] = *buf;
 174     s->rx_fifo_pos++;
 175     s->rx_fifo_pos &= 0x7;
 176     s->rx_fifo_len++;
 177
 178     uart_update_status(s);
 179     uart_update_irq(s);
 180 }
 181
 182 static int uart_can_rx(void *opaque)
 183 {
 184     struct xlx_uartlite *s = opaque;
 185     int r;
 186
 187     r = s->rx_fifo_len < sizeof(s->rx_fifo);
 188     if (!r)
 189         printf("cannot receive!\n");
 190     return r;
 191 }
 192
 193 static void uart_event(void *opaque, int event)
 194 {
 195
 196 }
 197
 198 static int xilinx_uartlite_init(SysBusDevice *dev)
 199 {
 200     struct xlx_uartlite *s = FROM_SYSBUS(typeof (*s), dev);
 201
 202     sysbus_init_irq(dev, &s->irq);
 203
 204     uart_update_status(s);
 205     memory_region_init_io(&s->mmio, &uart_ops, s, "xilinx-uartlite", R_MAX * 4);
 206     sysbus_init_mmio(dev, &s->mmio);
 207
 208     s->chr = qemu_char_get_next_serial();
 209     if (s->chr)
 210         qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s);
 211     return 0;
 212 }
 213
 214 static void xilinx_uartlite_class_init(ObjectClass *klass, void *data)
 215 {
 216     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
 217
 218     sdc->init = xilinx_uartlite_init;
 219 }
 220
 221 static TypeInfo xilinx_uartlite_info = {
 222     .name          = "xilinx,uartlite",
 223     .parent        = TYPE_SYS_BUS_DEVICE,
 224     .instance_size = sizeof (struct xlx_uartlite),
 225     .class_init    = xilinx_uartlite_class_init,
 226 };
 227
 228 static void xilinx_uart_register_types(void)
 229 {
 230     type_register_static(&xilinx_uartlite_info);
 231 }
 232
 233 type_init(xilinx_uart_register_types)