4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "qemu/osdep.h"
22 #include "qemu/error-report.h"
23 #include "qapi/error.h"
25 #include "internals.h"
26 #include "qemu-common.h"
27 #include "exec/exec-all.h"
28 #include "hw/qdev-properties.h"
29 #if !defined(CONFIG_USER_ONLY)
30 #include "hw/loader.h"
32 #include "hw/arm/arm.h"
33 #include "sysemu/sysemu.h"
34 #include "sysemu/hw_accel.h"
37 static void arm_cpu_set_pc(CPUState
*cs
, vaddr value
)
39 ARMCPU
*cpu
= ARM_CPU(cs
);
41 cpu
->env
.regs
[15] = value
;
44 static bool arm_cpu_has_work(CPUState
*cs
)
46 ARMCPU
*cpu
= ARM_CPU(cs
);
48 return (cpu
->power_state
!= PSCI_OFF
)
49 && cs
->interrupt_request
&
50 (CPU_INTERRUPT_FIQ
| CPU_INTERRUPT_HARD
51 | CPU_INTERRUPT_VFIQ
| CPU_INTERRUPT_VIRQ
52 | CPU_INTERRUPT_EXITTB
);
55 void arm_register_el_change_hook(ARMCPU
*cpu
, ARMELChangeHook
*hook
,
58 /* We currently only support registering a single hook function */
59 assert(!cpu
->el_change_hook
);
60 cpu
->el_change_hook
= hook
;
61 cpu
->el_change_hook_opaque
= opaque
;
64 static void cp_reg_reset(gpointer key
, gpointer value
, gpointer opaque
)
66 /* Reset a single ARMCPRegInfo register */
67 ARMCPRegInfo
*ri
= value
;
70 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
)) {
75 ri
->resetfn(&cpu
->env
, ri
);
79 /* A zero offset is never possible as it would be regs[0]
80 * so we use it to indicate that reset is being handled elsewhere.
81 * This is basically only used for fields in non-core coprocessors
82 * (like the pxa2xx ones).
84 if (!ri
->fieldoffset
) {
88 if (cpreg_field_is_64bit(ri
)) {
89 CPREG_FIELD64(&cpu
->env
, ri
) = ri
->resetvalue
;
91 CPREG_FIELD32(&cpu
->env
, ri
) = ri
->resetvalue
;
95 static void cp_reg_check_reset(gpointer key
, gpointer value
, gpointer opaque
)
97 /* Purely an assertion check: we've already done reset once,
98 * so now check that running the reset for the cpreg doesn't
99 * change its value. This traps bugs where two different cpregs
100 * both try to reset the same state field but to different values.
102 ARMCPRegInfo
*ri
= value
;
103 ARMCPU
*cpu
= opaque
;
104 uint64_t oldvalue
, newvalue
;
106 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
| ARM_CP_NO_RAW
)) {
110 oldvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
111 cp_reg_reset(key
, value
, opaque
);
112 newvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
113 assert(oldvalue
== newvalue
);
116 /* CPUClass::reset() */
117 static void arm_cpu_reset(CPUState
*s
)
119 ARMCPU
*cpu
= ARM_CPU(s
);
120 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(cpu
);
121 CPUARMState
*env
= &cpu
->env
;
123 acc
->parent_reset(s
);
125 memset(env
, 0, offsetof(CPUARMState
, end_reset_fields
));
127 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_reset
, cpu
);
128 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_check_reset
, cpu
);
130 env
->vfp
.xregs
[ARM_VFP_FPSID
] = cpu
->reset_fpsid
;
131 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = cpu
->mvfr0
;
132 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = cpu
->mvfr1
;
133 env
->vfp
.xregs
[ARM_VFP_MVFR2
] = cpu
->mvfr2
;
135 cpu
->power_state
= cpu
->start_powered_off
? PSCI_OFF
: PSCI_ON
;
136 s
->halted
= cpu
->start_powered_off
;
138 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
139 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
142 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
143 /* 64 bit CPUs always start in 64 bit mode */
145 #if defined(CONFIG_USER_ONLY)
146 env
->pstate
= PSTATE_MODE_EL0t
;
147 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
148 env
->cp15
.sctlr_el
[1] |= SCTLR_UCT
| SCTLR_UCI
| SCTLR_DZE
;
149 /* and to the FP/Neon instructions */
150 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 2, 3);
152 /* Reset into the highest available EL */
153 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
154 env
->pstate
= PSTATE_MODE_EL3h
;
155 } else if (arm_feature(env
, ARM_FEATURE_EL2
)) {
156 env
->pstate
= PSTATE_MODE_EL2h
;
158 env
->pstate
= PSTATE_MODE_EL1h
;
160 env
->pc
= cpu
->rvbar
;
163 #if defined(CONFIG_USER_ONLY)
164 /* Userspace expects access to cp10 and cp11 for FP/Neon */
165 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 4, 0xf);
169 #if defined(CONFIG_USER_ONLY)
170 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
171 /* For user mode we must enable access to coprocessors */
172 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
173 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
174 env
->cp15
.c15_cpar
= 3;
175 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
176 env
->cp15
.c15_cpar
= 1;
179 /* SVC mode with interrupts disabled. */
180 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
;
181 env
->daif
= PSTATE_D
| PSTATE_A
| PSTATE_I
| PSTATE_F
;
183 if (arm_feature(env
, ARM_FEATURE_M
)) {
184 uint32_t initial_msp
; /* Loaded from 0x0 */
185 uint32_t initial_pc
; /* Loaded from 0x4 */
188 /* The reset value of this bit is IMPDEF, but ARM recommends
189 * that it resets to 1, so QEMU always does that rather than making
190 * it dependent on CPU model.
192 env
->v7m
.ccr
= R_V7M_CCR_STKALIGN_MASK
;
194 /* Unlike A/R profile, M profile defines the reset LR value */
195 env
->regs
[14] = 0xffffffff;
197 /* Load the initial SP and PC from the vector table at address 0 */
200 /* Address zero is covered by ROM which hasn't yet been
201 * copied into physical memory.
203 initial_msp
= ldl_p(rom
);
204 initial_pc
= ldl_p(rom
+ 4);
206 /* Address zero not covered by a ROM blob, or the ROM blob
207 * is in non-modifiable memory and this is a second reset after
208 * it got copied into memory. In the latter case, rom_ptr
209 * will return a NULL pointer and we should use ldl_phys instead.
211 initial_msp
= ldl_phys(s
->as
, 0);
212 initial_pc
= ldl_phys(s
->as
, 4);
215 env
->regs
[13] = initial_msp
& 0xFFFFFFFC;
216 env
->regs
[15] = initial_pc
& ~1;
217 env
->thumb
= initial_pc
& 1;
220 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
221 * executing as AArch32 then check if highvecs are enabled and
222 * adjust the PC accordingly.
224 if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
225 env
->regs
[15] = 0xFFFF0000;
228 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
231 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
232 if (cpu
->pmsav7_dregion
> 0) {
233 if (arm_feature(env
, ARM_FEATURE_V8
)) {
234 memset(env
->pmsav8
.rbar
, 0,
235 sizeof(*env
->pmsav8
.rbar
) * cpu
->pmsav7_dregion
);
236 memset(env
->pmsav8
.rlar
, 0,
237 sizeof(*env
->pmsav8
.rlar
) * cpu
->pmsav7_dregion
);
238 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
239 memset(env
->pmsav7
.drbar
, 0,
240 sizeof(*env
->pmsav7
.drbar
) * cpu
->pmsav7_dregion
);
241 memset(env
->pmsav7
.drsr
, 0,
242 sizeof(*env
->pmsav7
.drsr
) * cpu
->pmsav7_dregion
);
243 memset(env
->pmsav7
.dracr
, 0,
244 sizeof(*env
->pmsav7
.dracr
) * cpu
->pmsav7_dregion
);
248 env
->pmsav8
.mair0
= 0;
249 env
->pmsav8
.mair1
= 0;
252 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
253 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
254 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
255 set_float_detect_tininess(float_tininess_before_rounding
,
256 &env
->vfp
.fp_status
);
257 set_float_detect_tininess(float_tininess_before_rounding
,
258 &env
->vfp
.standard_fp_status
);
259 #ifndef CONFIG_USER_ONLY
261 kvm_arm_reset_vcpu(cpu
);
265 hw_breakpoint_update_all(cpu
);
266 hw_watchpoint_update_all(cpu
);
269 bool arm_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
271 CPUClass
*cc
= CPU_GET_CLASS(cs
);
272 CPUARMState
*env
= cs
->env_ptr
;
273 uint32_t cur_el
= arm_current_el(env
);
274 bool secure
= arm_is_secure(env
);
279 if (interrupt_request
& CPU_INTERRUPT_FIQ
) {
281 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
282 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
283 cs
->exception_index
= excp_idx
;
284 env
->exception
.target_el
= target_el
;
285 cc
->do_interrupt(cs
);
289 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
291 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
292 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
293 cs
->exception_index
= excp_idx
;
294 env
->exception
.target_el
= target_el
;
295 cc
->do_interrupt(cs
);
299 if (interrupt_request
& CPU_INTERRUPT_VIRQ
) {
300 excp_idx
= EXCP_VIRQ
;
302 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
303 cs
->exception_index
= excp_idx
;
304 env
->exception
.target_el
= target_el
;
305 cc
->do_interrupt(cs
);
309 if (interrupt_request
& CPU_INTERRUPT_VFIQ
) {
310 excp_idx
= EXCP_VFIQ
;
312 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
313 cs
->exception_index
= excp_idx
;
314 env
->exception
.target_el
= target_el
;
315 cc
->do_interrupt(cs
);
323 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
324 static bool arm_v7m_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
326 CPUClass
*cc
= CPU_GET_CLASS(cs
);
327 ARMCPU
*cpu
= ARM_CPU(cs
);
328 CPUARMState
*env
= &cpu
->env
;
331 /* ARMv7-M interrupt masking works differently than -A or -R.
332 * There is no FIQ/IRQ distinction. Instead of I and F bits
333 * masking FIQ and IRQ interrupts, an exception is taken only
334 * if it is higher priority than the current execution priority
335 * (which depends on state like BASEPRI, FAULTMASK and the
336 * currently active exception).
338 if (interrupt_request
& CPU_INTERRUPT_HARD
339 && (armv7m_nvic_can_take_pending_exception(env
->nvic
))) {
340 cs
->exception_index
= EXCP_IRQ
;
341 cc
->do_interrupt(cs
);
348 #ifndef CONFIG_USER_ONLY
349 static void arm_cpu_set_irq(void *opaque
, int irq
, int level
)
351 ARMCPU
*cpu
= opaque
;
352 CPUARMState
*env
= &cpu
->env
;
353 CPUState
*cs
= CPU(cpu
);
354 static const int mask
[] = {
355 [ARM_CPU_IRQ
] = CPU_INTERRUPT_HARD
,
356 [ARM_CPU_FIQ
] = CPU_INTERRUPT_FIQ
,
357 [ARM_CPU_VIRQ
] = CPU_INTERRUPT_VIRQ
,
358 [ARM_CPU_VFIQ
] = CPU_INTERRUPT_VFIQ
364 assert(arm_feature(env
, ARM_FEATURE_EL2
));
369 cpu_interrupt(cs
, mask
[irq
]);
371 cpu_reset_interrupt(cs
, mask
[irq
]);
375 g_assert_not_reached();
379 static void arm_cpu_kvm_set_irq(void *opaque
, int irq
, int level
)
382 ARMCPU
*cpu
= opaque
;
383 CPUState
*cs
= CPU(cpu
);
384 int kvm_irq
= KVM_ARM_IRQ_TYPE_CPU
<< KVM_ARM_IRQ_TYPE_SHIFT
;
388 kvm_irq
|= KVM_ARM_IRQ_CPU_IRQ
;
391 kvm_irq
|= KVM_ARM_IRQ_CPU_FIQ
;
394 g_assert_not_reached();
396 kvm_irq
|= cs
->cpu_index
<< KVM_ARM_IRQ_VCPU_SHIFT
;
397 kvm_set_irq(kvm_state
, kvm_irq
, level
? 1 : 0);
401 static bool arm_cpu_virtio_is_big_endian(CPUState
*cs
)
403 ARMCPU
*cpu
= ARM_CPU(cs
);
404 CPUARMState
*env
= &cpu
->env
;
406 cpu_synchronize_state(cs
);
407 return arm_cpu_data_is_big_endian(env
);
412 static inline void set_feature(CPUARMState
*env
, int feature
)
414 env
->features
|= 1ULL << feature
;
417 static inline void unset_feature(CPUARMState
*env
, int feature
)
419 env
->features
&= ~(1ULL << feature
);
423 print_insn_thumb1(bfd_vma pc
, disassemble_info
*info
)
425 return print_insn_arm(pc
| 1, info
);
428 static int arm_read_memory_func(bfd_vma memaddr
, bfd_byte
*b
,
429 int length
, struct disassemble_info
*info
)
431 assert(info
->read_memory_inner_func
);
432 assert((info
->flags
& INSN_ARM_BE32
) == 0 || length
== 2 || length
== 4);
434 if ((info
->flags
& INSN_ARM_BE32
) != 0 && length
== 2) {
435 assert(info
->endian
== BFD_ENDIAN_LITTLE
);
436 return info
->read_memory_inner_func(memaddr
^ 2, (bfd_byte
*)b
, 2,
439 return info
->read_memory_inner_func(memaddr
, b
, length
, info
);
443 static void arm_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
445 ARMCPU
*ac
= ARM_CPU(cpu
);
446 CPUARMState
*env
= &ac
->env
;
449 /* We might not be compiled with the A64 disassembler
450 * because it needs a C++ compiler. Leave print_insn
451 * unset in this case to use the caller default behaviour.
453 #if defined(CONFIG_ARM_A64_DIS)
454 info
->print_insn
= print_insn_arm_a64
;
456 } else if (env
->thumb
) {
457 info
->print_insn
= print_insn_thumb1
;
459 info
->print_insn
= print_insn_arm
;
461 if (bswap_code(arm_sctlr_b(env
))) {
462 #ifdef TARGET_WORDS_BIGENDIAN
463 info
->endian
= BFD_ENDIAN_LITTLE
;
465 info
->endian
= BFD_ENDIAN_BIG
;
468 if (info
->read_memory_inner_func
== NULL
) {
469 info
->read_memory_inner_func
= info
->read_memory_func
;
470 info
->read_memory_func
= arm_read_memory_func
;
472 info
->flags
&= ~INSN_ARM_BE32
;
473 if (arm_sctlr_b(env
)) {
474 info
->flags
|= INSN_ARM_BE32
;
478 uint64_t arm_cpu_mp_affinity(int idx
, uint8_t clustersz
)
480 uint32_t Aff1
= idx
/ clustersz
;
481 uint32_t Aff0
= idx
% clustersz
;
482 return (Aff1
<< ARM_AFF1_SHIFT
) | Aff0
;
485 static void arm_cpu_initfn(Object
*obj
)
487 CPUState
*cs
= CPU(obj
);
488 ARMCPU
*cpu
= ARM_CPU(obj
);
491 cs
->env_ptr
= &cpu
->env
;
492 cpu
->cp_regs
= g_hash_table_new_full(g_int_hash
, g_int_equal
,
495 #ifndef CONFIG_USER_ONLY
496 /* Our inbound IRQ and FIQ lines */
498 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
499 * the same interface as non-KVM CPUs.
501 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_kvm_set_irq
, 4);
503 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_set_irq
, 4);
506 cpu
->gt_timer
[GTIMER_PHYS
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
507 arm_gt_ptimer_cb
, cpu
);
508 cpu
->gt_timer
[GTIMER_VIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
509 arm_gt_vtimer_cb
, cpu
);
510 cpu
->gt_timer
[GTIMER_HYP
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
511 arm_gt_htimer_cb
, cpu
);
512 cpu
->gt_timer
[GTIMER_SEC
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
513 arm_gt_stimer_cb
, cpu
);
514 qdev_init_gpio_out(DEVICE(cpu
), cpu
->gt_timer_outputs
,
515 ARRAY_SIZE(cpu
->gt_timer_outputs
));
517 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->gicv3_maintenance_interrupt
,
518 "gicv3-maintenance-interrupt", 1);
519 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->pmu_interrupt
,
523 /* DTB consumers generally don't in fact care what the 'compatible'
524 * string is, so always provide some string and trust that a hypothetical
525 * picky DTB consumer will also provide a helpful error message.
527 cpu
->dtb_compatible
= "qemu,unknown";
528 cpu
->psci_version
= 1; /* By default assume PSCI v0.1 */
529 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_NONE
;
532 cpu
->psci_version
= 2; /* TCG implements PSCI 0.2 */
535 arm_translate_init();
540 static Property arm_cpu_reset_cbar_property
=
541 DEFINE_PROP_UINT64("reset-cbar", ARMCPU
, reset_cbar
, 0);
543 static Property arm_cpu_reset_hivecs_property
=
544 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU
, reset_hivecs
, false);
546 static Property arm_cpu_rvbar_property
=
547 DEFINE_PROP_UINT64("rvbar", ARMCPU
, rvbar
, 0);
549 static Property arm_cpu_has_el2_property
=
550 DEFINE_PROP_BOOL("has_el2", ARMCPU
, has_el2
, true);
552 static Property arm_cpu_has_el3_property
=
553 DEFINE_PROP_BOOL("has_el3", ARMCPU
, has_el3
, true);
555 static Property arm_cpu_cfgend_property
=
556 DEFINE_PROP_BOOL("cfgend", ARMCPU
, cfgend
, false);
558 /* use property name "pmu" to match other archs and virt tools */
559 static Property arm_cpu_has_pmu_property
=
560 DEFINE_PROP_BOOL("pmu", ARMCPU
, has_pmu
, true);
562 static Property arm_cpu_has_mpu_property
=
563 DEFINE_PROP_BOOL("has-mpu", ARMCPU
, has_mpu
, true);
565 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
566 * because the CPU initfn will have already set cpu->pmsav7_dregion to
567 * the right value for that particular CPU type, and we don't want
568 * to override that with an incorrect constant value.
570 static Property arm_cpu_pmsav7_dregion_property
=
571 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU
,
573 qdev_prop_uint32
, uint32_t);
575 static void arm_cpu_post_init(Object
*obj
)
577 ARMCPU
*cpu
= ARM_CPU(obj
);
579 /* M profile implies PMSA. We have to do this here rather than
580 * in realize with the other feature-implication checks because
581 * we look at the PMSA bit to see if we should add some properties.
583 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
584 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
587 if (arm_feature(&cpu
->env
, ARM_FEATURE_CBAR
) ||
588 arm_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
)) {
589 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_cbar_property
,
593 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
594 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_hivecs_property
,
598 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
599 qdev_property_add_static(DEVICE(obj
), &arm_cpu_rvbar_property
,
603 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
604 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
605 * prevent "has_el3" from existing on CPUs which cannot support EL3.
607 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el3_property
,
610 #ifndef CONFIG_USER_ONLY
611 object_property_add_link(obj
, "secure-memory",
613 (Object
**)&cpu
->secure_memory
,
614 qdev_prop_allow_set_link_before_realize
,
615 OBJ_PROP_LINK_UNREF_ON_RELEASE
,
620 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
)) {
621 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el2_property
,
625 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMU
)) {
626 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_pmu_property
,
630 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMSA
)) {
631 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_mpu_property
,
633 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
634 qdev_property_add_static(DEVICE(obj
),
635 &arm_cpu_pmsav7_dregion_property
,
640 qdev_property_add_static(DEVICE(obj
), &arm_cpu_cfgend_property
,
644 static void arm_cpu_finalizefn(Object
*obj
)
646 ARMCPU
*cpu
= ARM_CPU(obj
);
647 g_hash_table_destroy(cpu
->cp_regs
);
650 static void arm_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
652 CPUState
*cs
= CPU(dev
);
653 ARMCPU
*cpu
= ARM_CPU(dev
);
654 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(dev
);
655 CPUARMState
*env
= &cpu
->env
;
657 Error
*local_err
= NULL
;
659 cpu_exec_realizefn(cs
, &local_err
);
660 if (local_err
!= NULL
) {
661 error_propagate(errp
, local_err
);
665 /* Some features automatically imply others: */
666 if (arm_feature(env
, ARM_FEATURE_V8
)) {
667 set_feature(env
, ARM_FEATURE_V7
);
668 set_feature(env
, ARM_FEATURE_ARM_DIV
);
669 set_feature(env
, ARM_FEATURE_LPAE
);
671 if (arm_feature(env
, ARM_FEATURE_V7
)) {
672 set_feature(env
, ARM_FEATURE_VAPA
);
673 set_feature(env
, ARM_FEATURE_THUMB2
);
674 set_feature(env
, ARM_FEATURE_MPIDR
);
675 if (!arm_feature(env
, ARM_FEATURE_M
)) {
676 set_feature(env
, ARM_FEATURE_V6K
);
678 set_feature(env
, ARM_FEATURE_V6
);
681 /* Always define VBAR for V7 CPUs even if it doesn't exist in
682 * non-EL3 configs. This is needed by some legacy boards.
684 set_feature(env
, ARM_FEATURE_VBAR
);
686 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
687 set_feature(env
, ARM_FEATURE_V6
);
688 set_feature(env
, ARM_FEATURE_MVFR
);
690 if (arm_feature(env
, ARM_FEATURE_V6
)) {
691 set_feature(env
, ARM_FEATURE_V5
);
692 if (!arm_feature(env
, ARM_FEATURE_M
)) {
693 set_feature(env
, ARM_FEATURE_AUXCR
);
696 if (arm_feature(env
, ARM_FEATURE_V5
)) {
697 set_feature(env
, ARM_FEATURE_V4T
);
699 if (arm_feature(env
, ARM_FEATURE_M
)) {
700 set_feature(env
, ARM_FEATURE_THUMB_DIV
);
702 if (arm_feature(env
, ARM_FEATURE_ARM_DIV
)) {
703 set_feature(env
, ARM_FEATURE_THUMB_DIV
);
705 if (arm_feature(env
, ARM_FEATURE_VFP4
)) {
706 set_feature(env
, ARM_FEATURE_VFP3
);
707 set_feature(env
, ARM_FEATURE_VFP_FP16
);
709 if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
710 set_feature(env
, ARM_FEATURE_VFP
);
712 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
713 set_feature(env
, ARM_FEATURE_V7MP
);
714 set_feature(env
, ARM_FEATURE_PXN
);
716 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
717 set_feature(env
, ARM_FEATURE_CBAR
);
719 if (arm_feature(env
, ARM_FEATURE_THUMB2
) &&
720 !arm_feature(env
, ARM_FEATURE_M
)) {
721 set_feature(env
, ARM_FEATURE_THUMB_DSP
);
724 if (arm_feature(env
, ARM_FEATURE_V7
) &&
725 !arm_feature(env
, ARM_FEATURE_M
) &&
726 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
727 /* v7VMSA drops support for the old ARMv5 tiny pages, so we
732 /* For CPUs which might have tiny 1K pages, or which have an
733 * MPU and might have small region sizes, stick with 1K pages.
737 if (!set_preferred_target_page_bits(pagebits
)) {
738 /* This can only ever happen for hotplugging a CPU, or if
739 * the board code incorrectly creates a CPU which it has
740 * promised via minimum_page_size that it will not.
742 error_setg(errp
, "This CPU requires a smaller page size than the "
747 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
748 * We don't support setting cluster ID ([16..23]) (known as Aff2
749 * in later ARM ARM versions), or any of the higher affinity level fields,
750 * so these bits always RAZ.
752 if (cpu
->mp_affinity
== ARM64_AFFINITY_INVALID
) {
753 cpu
->mp_affinity
= arm_cpu_mp_affinity(cs
->cpu_index
,
754 ARM_DEFAULT_CPUS_PER_CLUSTER
);
757 if (cpu
->reset_hivecs
) {
758 cpu
->reset_sctlr
|= (1 << 13);
762 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
763 cpu
->reset_sctlr
|= SCTLR_EE
;
765 cpu
->reset_sctlr
|= SCTLR_B
;
770 /* If the has_el3 CPU property is disabled then we need to disable the
773 unset_feature(env
, ARM_FEATURE_EL3
);
775 /* Disable the security extension feature bits in the processor feature
776 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
778 cpu
->id_pfr1
&= ~0xf0;
779 cpu
->id_aa64pfr0
&= ~0xf000;
783 unset_feature(env
, ARM_FEATURE_EL2
);
787 unset_feature(env
, ARM_FEATURE_PMU
);
788 cpu
->id_aa64dfr0
&= ~0xf00;
791 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
792 /* Disable the hypervisor feature bits in the processor feature
793 * registers if we don't have EL2. These are id_pfr1[15:12] and
794 * id_aa64pfr0_el1[11:8].
796 cpu
->id_aa64pfr0
&= ~0xf00;
797 cpu
->id_pfr1
&= ~0xf000;
800 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
801 * to false or by setting pmsav7-dregion to 0.
804 cpu
->pmsav7_dregion
= 0;
806 if (cpu
->pmsav7_dregion
== 0) {
807 cpu
->has_mpu
= false;
810 if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
811 arm_feature(env
, ARM_FEATURE_V7
)) {
812 uint32_t nr
= cpu
->pmsav7_dregion
;
815 error_setg(errp
, "PMSAv7 MPU #regions invalid %" PRIu32
, nr
);
820 if (arm_feature(env
, ARM_FEATURE_V8
)) {
822 env
->pmsav8
.rbar
= g_new0(uint32_t, nr
);
823 env
->pmsav8
.rlar
= g_new0(uint32_t, nr
);
825 env
->pmsav7
.drbar
= g_new0(uint32_t, nr
);
826 env
->pmsav7
.drsr
= g_new0(uint32_t, nr
);
827 env
->pmsav7
.dracr
= g_new0(uint32_t, nr
);
832 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
833 set_feature(env
, ARM_FEATURE_VBAR
);
836 register_cp_regs_for_features(cpu
);
837 arm_cpu_register_gdb_regs_for_features(cpu
);
839 init_cpreg_list(cpu
);
841 #ifndef CONFIG_USER_ONLY
851 if (!cpu
->secure_memory
) {
852 cpu
->secure_memory
= cs
->memory
;
854 as
= address_space_init_shareable(cpu
->secure_memory
,
855 "cpu-secure-memory");
856 cpu_address_space_init(cs
, as
, ARMASIdx_S
);
858 cpu_address_space_init(cs
,
859 address_space_init_shareable(cs
->memory
,
867 acc
->parent_realize(dev
, errp
);
870 static ObjectClass
*arm_cpu_class_by_name(const char *cpu_model
)
880 cpuname
= g_strsplit(cpu_model
, ",", 1);
881 typename
= g_strdup_printf("%s-" TYPE_ARM_CPU
, cpuname
[0]);
882 oc
= object_class_by_name(typename
);
885 if (!oc
|| !object_class_dynamic_cast(oc
, TYPE_ARM_CPU
) ||
886 object_class_is_abstract(oc
)) {
892 /* CPU models. These are not needed for the AArch64 linux-user build. */
893 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
895 static void arm926_initfn(Object
*obj
)
897 ARMCPU
*cpu
= ARM_CPU(obj
);
899 cpu
->dtb_compatible
= "arm,arm926";
900 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
901 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
902 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
903 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
904 cpu
->midr
= 0x41069265;
905 cpu
->reset_fpsid
= 0x41011090;
906 cpu
->ctr
= 0x1dd20d2;
907 cpu
->reset_sctlr
= 0x00090078;
910 static void arm946_initfn(Object
*obj
)
912 ARMCPU
*cpu
= ARM_CPU(obj
);
914 cpu
->dtb_compatible
= "arm,arm946";
915 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
916 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
917 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
918 cpu
->midr
= 0x41059461;
919 cpu
->ctr
= 0x0f004006;
920 cpu
->reset_sctlr
= 0x00000078;
923 static void arm1026_initfn(Object
*obj
)
925 ARMCPU
*cpu
= ARM_CPU(obj
);
927 cpu
->dtb_compatible
= "arm,arm1026";
928 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
929 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
930 set_feature(&cpu
->env
, ARM_FEATURE_AUXCR
);
931 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
932 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
933 cpu
->midr
= 0x4106a262;
934 cpu
->reset_fpsid
= 0x410110a0;
935 cpu
->ctr
= 0x1dd20d2;
936 cpu
->reset_sctlr
= 0x00090078;
937 cpu
->reset_auxcr
= 1;
939 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
940 ARMCPRegInfo ifar
= {
941 .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
943 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifar_ns
),
946 define_one_arm_cp_reg(cpu
, &ifar
);
950 static void arm1136_r2_initfn(Object
*obj
)
952 ARMCPU
*cpu
= ARM_CPU(obj
);
953 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
954 * older core than plain "arm1136". In particular this does not
955 * have the v6K features.
956 * These ID register values are correct for 1136 but may be wrong
957 * for 1136_r2 (in particular r0p2 does not actually implement most
958 * of the ID registers).
961 cpu
->dtb_compatible
= "arm,arm1136";
962 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
963 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
964 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
965 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
966 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
967 cpu
->midr
= 0x4107b362;
968 cpu
->reset_fpsid
= 0x410120b4;
969 cpu
->mvfr0
= 0x11111111;
970 cpu
->mvfr1
= 0x00000000;
971 cpu
->ctr
= 0x1dd20d2;
972 cpu
->reset_sctlr
= 0x00050078;
973 cpu
->id_pfr0
= 0x111;
977 cpu
->id_mmfr0
= 0x01130003;
978 cpu
->id_mmfr1
= 0x10030302;
979 cpu
->id_mmfr2
= 0x01222110;
980 cpu
->id_isar0
= 0x00140011;
981 cpu
->id_isar1
= 0x12002111;
982 cpu
->id_isar2
= 0x11231111;
983 cpu
->id_isar3
= 0x01102131;
984 cpu
->id_isar4
= 0x141;
985 cpu
->reset_auxcr
= 7;
988 static void arm1136_initfn(Object
*obj
)
990 ARMCPU
*cpu
= ARM_CPU(obj
);
992 cpu
->dtb_compatible
= "arm,arm1136";
993 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
994 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
995 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
996 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
997 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
998 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
999 cpu
->midr
= 0x4117b363;
1000 cpu
->reset_fpsid
= 0x410120b4;
1001 cpu
->mvfr0
= 0x11111111;
1002 cpu
->mvfr1
= 0x00000000;
1003 cpu
->ctr
= 0x1dd20d2;
1004 cpu
->reset_sctlr
= 0x00050078;
1005 cpu
->id_pfr0
= 0x111;
1009 cpu
->id_mmfr0
= 0x01130003;
1010 cpu
->id_mmfr1
= 0x10030302;
1011 cpu
->id_mmfr2
= 0x01222110;
1012 cpu
->id_isar0
= 0x00140011;
1013 cpu
->id_isar1
= 0x12002111;
1014 cpu
->id_isar2
= 0x11231111;
1015 cpu
->id_isar3
= 0x01102131;
1016 cpu
->id_isar4
= 0x141;
1017 cpu
->reset_auxcr
= 7;
1020 static void arm1176_initfn(Object
*obj
)
1022 ARMCPU
*cpu
= ARM_CPU(obj
);
1024 cpu
->dtb_compatible
= "arm,arm1176";
1025 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
1026 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1027 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
1028 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1029 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
1030 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
1031 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1032 cpu
->midr
= 0x410fb767;
1033 cpu
->reset_fpsid
= 0x410120b5;
1034 cpu
->mvfr0
= 0x11111111;
1035 cpu
->mvfr1
= 0x00000000;
1036 cpu
->ctr
= 0x1dd20d2;
1037 cpu
->reset_sctlr
= 0x00050078;
1038 cpu
->id_pfr0
= 0x111;
1039 cpu
->id_pfr1
= 0x11;
1040 cpu
->id_dfr0
= 0x33;
1042 cpu
->id_mmfr0
= 0x01130003;
1043 cpu
->id_mmfr1
= 0x10030302;
1044 cpu
->id_mmfr2
= 0x01222100;
1045 cpu
->id_isar0
= 0x0140011;
1046 cpu
->id_isar1
= 0x12002111;
1047 cpu
->id_isar2
= 0x11231121;
1048 cpu
->id_isar3
= 0x01102131;
1049 cpu
->id_isar4
= 0x01141;
1050 cpu
->reset_auxcr
= 7;
1053 static void arm11mpcore_initfn(Object
*obj
)
1055 ARMCPU
*cpu
= ARM_CPU(obj
);
1057 cpu
->dtb_compatible
= "arm,arm11mpcore";
1058 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
1059 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1060 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
1061 set_feature(&cpu
->env
, ARM_FEATURE_MPIDR
);
1062 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1063 cpu
->midr
= 0x410fb022;
1064 cpu
->reset_fpsid
= 0x410120b4;
1065 cpu
->mvfr0
= 0x11111111;
1066 cpu
->mvfr1
= 0x00000000;
1067 cpu
->ctr
= 0x1d192992; /* 32K icache 32K dcache */
1068 cpu
->id_pfr0
= 0x111;
1072 cpu
->id_mmfr0
= 0x01100103;
1073 cpu
->id_mmfr1
= 0x10020302;
1074 cpu
->id_mmfr2
= 0x01222000;
1075 cpu
->id_isar0
= 0x00100011;
1076 cpu
->id_isar1
= 0x12002111;
1077 cpu
->id_isar2
= 0x11221011;
1078 cpu
->id_isar3
= 0x01102131;
1079 cpu
->id_isar4
= 0x141;
1080 cpu
->reset_auxcr
= 1;
1083 static void cortex_m3_initfn(Object
*obj
)
1085 ARMCPU
*cpu
= ARM_CPU(obj
);
1086 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1087 set_feature(&cpu
->env
, ARM_FEATURE_M
);
1088 cpu
->midr
= 0x410fc231;
1089 cpu
->pmsav7_dregion
= 8;
1092 static void cortex_m4_initfn(Object
*obj
)
1094 ARMCPU
*cpu
= ARM_CPU(obj
);
1096 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1097 set_feature(&cpu
->env
, ARM_FEATURE_M
);
1098 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
);
1099 cpu
->midr
= 0x410fc240; /* r0p0 */
1100 cpu
->pmsav7_dregion
= 8;
1102 static void arm_v7m_class_init(ObjectClass
*oc
, void *data
)
1104 CPUClass
*cc
= CPU_CLASS(oc
);
1106 #ifndef CONFIG_USER_ONLY
1107 cc
->do_interrupt
= arm_v7m_cpu_do_interrupt
;
1110 cc
->cpu_exec_interrupt
= arm_v7m_cpu_exec_interrupt
;
1113 static const ARMCPRegInfo cortexr5_cp_reginfo
[] = {
1114 /* Dummy the TCM region regs for the moment */
1115 { .name
= "ATCM", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
1116 .access
= PL1_RW
, .type
= ARM_CP_CONST
},
1117 { .name
= "BTCM", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
1118 .access
= PL1_RW
, .type
= ARM_CP_CONST
},
1119 { .name
= "DCACHE_INVAL", .cp
= 15, .opc1
= 0, .crn
= 15, .crm
= 5,
1120 .opc2
= 0, .access
= PL1_W
, .type
= ARM_CP_NOP
},
1124 static void cortex_r5_initfn(Object
*obj
)
1126 ARMCPU
*cpu
= ARM_CPU(obj
);
1128 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1129 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DIV
);
1130 set_feature(&cpu
->env
, ARM_FEATURE_ARM_DIV
);
1131 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
1132 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
1133 cpu
->midr
= 0x411fc153; /* r1p3 */
1134 cpu
->id_pfr0
= 0x0131;
1135 cpu
->id_pfr1
= 0x001;
1136 cpu
->id_dfr0
= 0x010400;
1138 cpu
->id_mmfr0
= 0x0210030;
1139 cpu
->id_mmfr1
= 0x00000000;
1140 cpu
->id_mmfr2
= 0x01200000;
1141 cpu
->id_mmfr3
= 0x0211;
1142 cpu
->id_isar0
= 0x2101111;
1143 cpu
->id_isar1
= 0x13112111;
1144 cpu
->id_isar2
= 0x21232141;
1145 cpu
->id_isar3
= 0x01112131;
1146 cpu
->id_isar4
= 0x0010142;
1147 cpu
->id_isar5
= 0x0;
1148 cpu
->mp_is_up
= true;
1149 cpu
->pmsav7_dregion
= 16;
1150 define_arm_cp_regs(cpu
, cortexr5_cp_reginfo
);
1153 static const ARMCPRegInfo cortexa8_cp_reginfo
[] = {
1154 { .name
= "L2LOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 0,
1155 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1156 { .name
= "L2AUXCR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
1157 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1161 static void cortex_a8_initfn(Object
*obj
)
1163 ARMCPU
*cpu
= ARM_CPU(obj
);
1165 cpu
->dtb_compatible
= "arm,cortex-a8";
1166 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1167 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
1168 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1169 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1170 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1171 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1172 cpu
->midr
= 0x410fc080;
1173 cpu
->reset_fpsid
= 0x410330c0;
1174 cpu
->mvfr0
= 0x11110222;
1175 cpu
->mvfr1
= 0x00011111;
1176 cpu
->ctr
= 0x82048004;
1177 cpu
->reset_sctlr
= 0x00c50078;
1178 cpu
->id_pfr0
= 0x1031;
1179 cpu
->id_pfr1
= 0x11;
1180 cpu
->id_dfr0
= 0x400;
1182 cpu
->id_mmfr0
= 0x31100003;
1183 cpu
->id_mmfr1
= 0x20000000;
1184 cpu
->id_mmfr2
= 0x01202000;
1185 cpu
->id_mmfr3
= 0x11;
1186 cpu
->id_isar0
= 0x00101111;
1187 cpu
->id_isar1
= 0x12112111;
1188 cpu
->id_isar2
= 0x21232031;
1189 cpu
->id_isar3
= 0x11112131;
1190 cpu
->id_isar4
= 0x00111142;
1191 cpu
->dbgdidr
= 0x15141000;
1192 cpu
->clidr
= (1 << 27) | (2 << 24) | 3;
1193 cpu
->ccsidr
[0] = 0xe007e01a; /* 16k L1 dcache. */
1194 cpu
->ccsidr
[1] = 0x2007e01a; /* 16k L1 icache. */
1195 cpu
->ccsidr
[2] = 0xf0000000; /* No L2 icache. */
1196 cpu
->reset_auxcr
= 2;
1197 define_arm_cp_regs(cpu
, cortexa8_cp_reginfo
);
1200 static const ARMCPRegInfo cortexa9_cp_reginfo
[] = {
1201 /* power_control should be set to maximum latency. Again,
1202 * default to 0 and set by private hook
1204 { .name
= "A9_PWRCTL", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
1205 .access
= PL1_RW
, .resetvalue
= 0,
1206 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_control
) },
1207 { .name
= "A9_DIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 1,
1208 .access
= PL1_RW
, .resetvalue
= 0,
1209 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_diagnostic
) },
1210 { .name
= "A9_PWRDIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 2,
1211 .access
= PL1_RW
, .resetvalue
= 0,
1212 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_diagnostic
) },
1213 { .name
= "NEONBUSY", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
1214 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1215 /* TLB lockdown control */
1216 { .name
= "TLB_LOCKR", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 2,
1217 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
1218 { .name
= "TLB_LOCKW", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 4,
1219 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
1220 { .name
= "TLB_VA", .cp
= 15, .crn
= 15, .crm
= 5, .opc1
= 5, .opc2
= 2,
1221 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1222 { .name
= "TLB_PA", .cp
= 15, .crn
= 15, .crm
= 6, .opc1
= 5, .opc2
= 2,
1223 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1224 { .name
= "TLB_ATTR", .cp
= 15, .crn
= 15, .crm
= 7, .opc1
= 5, .opc2
= 2,
1225 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1229 static void cortex_a9_initfn(Object
*obj
)
1231 ARMCPU
*cpu
= ARM_CPU(obj
);
1233 cpu
->dtb_compatible
= "arm,cortex-a9";
1234 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1235 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
1236 set_feature(&cpu
->env
, ARM_FEATURE_VFP_FP16
);
1237 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1238 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1239 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1240 /* Note that A9 supports the MP extensions even for
1241 * A9UP and single-core A9MP (which are both different
1242 * and valid configurations; we don't model A9UP).
1244 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
1245 set_feature(&cpu
->env
, ARM_FEATURE_CBAR
);
1246 cpu
->midr
= 0x410fc090;
1247 cpu
->reset_fpsid
= 0x41033090;
1248 cpu
->mvfr0
= 0x11110222;
1249 cpu
->mvfr1
= 0x01111111;
1250 cpu
->ctr
= 0x80038003;
1251 cpu
->reset_sctlr
= 0x00c50078;
1252 cpu
->id_pfr0
= 0x1031;
1253 cpu
->id_pfr1
= 0x11;
1254 cpu
->id_dfr0
= 0x000;
1256 cpu
->id_mmfr0
= 0x00100103;
1257 cpu
->id_mmfr1
= 0x20000000;
1258 cpu
->id_mmfr2
= 0x01230000;
1259 cpu
->id_mmfr3
= 0x00002111;
1260 cpu
->id_isar0
= 0x00101111;
1261 cpu
->id_isar1
= 0x13112111;
1262 cpu
->id_isar2
= 0x21232041;
1263 cpu
->id_isar3
= 0x11112131;
1264 cpu
->id_isar4
= 0x00111142;
1265 cpu
->dbgdidr
= 0x35141000;
1266 cpu
->clidr
= (1 << 27) | (1 << 24) | 3;
1267 cpu
->ccsidr
[0] = 0xe00fe019; /* 16k L1 dcache. */
1268 cpu
->ccsidr
[1] = 0x200fe019; /* 16k L1 icache. */
1269 define_arm_cp_regs(cpu
, cortexa9_cp_reginfo
);
1272 #ifndef CONFIG_USER_ONLY
1273 static uint64_t a15_l2ctlr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1275 /* Linux wants the number of processors from here.
1276 * Might as well set the interrupt-controller bit too.
1278 return ((smp_cpus
- 1) << 24) | (1 << 23);
1282 static const ARMCPRegInfo cortexa15_cp_reginfo
[] = {
1283 #ifndef CONFIG_USER_ONLY
1284 { .name
= "L2CTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
1285 .access
= PL1_RW
, .resetvalue
= 0, .readfn
= a15_l2ctlr_read
,
1286 .writefn
= arm_cp_write_ignore
, },
1288 { .name
= "L2ECTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 3,
1289 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1293 static void cortex_a7_initfn(Object
*obj
)
1295 ARMCPU
*cpu
= ARM_CPU(obj
);
1297 cpu
->dtb_compatible
= "arm,cortex-a7";
1298 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1299 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
1300 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1301 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1302 set_feature(&cpu
->env
, ARM_FEATURE_ARM_DIV
);
1303 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
1304 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1305 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
1306 set_feature(&cpu
->env
, ARM_FEATURE_LPAE
);
1307 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1308 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A7
;
1309 cpu
->midr
= 0x410fc075;
1310 cpu
->reset_fpsid
= 0x41023075;
1311 cpu
->mvfr0
= 0x10110222;
1312 cpu
->mvfr1
= 0x11111111;
1313 cpu
->ctr
= 0x84448003;
1314 cpu
->reset_sctlr
= 0x00c50078;
1315 cpu
->id_pfr0
= 0x00001131;
1316 cpu
->id_pfr1
= 0x00011011;
1317 cpu
->id_dfr0
= 0x02010555;
1318 cpu
->pmceid0
= 0x00000000;
1319 cpu
->pmceid1
= 0x00000000;
1320 cpu
->id_afr0
= 0x00000000;
1321 cpu
->id_mmfr0
= 0x10101105;
1322 cpu
->id_mmfr1
= 0x40000000;
1323 cpu
->id_mmfr2
= 0x01240000;
1324 cpu
->id_mmfr3
= 0x02102211;
1325 cpu
->id_isar0
= 0x01101110;
1326 cpu
->id_isar1
= 0x13112111;
1327 cpu
->id_isar2
= 0x21232041;
1328 cpu
->id_isar3
= 0x11112131;
1329 cpu
->id_isar4
= 0x10011142;
1330 cpu
->dbgdidr
= 0x3515f005;
1331 cpu
->clidr
= 0x0a200023;
1332 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
1333 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
1334 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
1335 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
); /* Same as A15 */
1338 static void cortex_a15_initfn(Object
*obj
)
1340 ARMCPU
*cpu
= ARM_CPU(obj
);
1342 cpu
->dtb_compatible
= "arm,cortex-a15";
1343 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1344 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
1345 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1346 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1347 set_feature(&cpu
->env
, ARM_FEATURE_ARM_DIV
);
1348 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
1349 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1350 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
1351 set_feature(&cpu
->env
, ARM_FEATURE_LPAE
);
1352 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1353 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A15
;
1354 cpu
->midr
= 0x412fc0f1;
1355 cpu
->reset_fpsid
= 0x410430f0;
1356 cpu
->mvfr0
= 0x10110222;
1357 cpu
->mvfr1
= 0x11111111;
1358 cpu
->ctr
= 0x8444c004;
1359 cpu
->reset_sctlr
= 0x00c50078;
1360 cpu
->id_pfr0
= 0x00001131;
1361 cpu
->id_pfr1
= 0x00011011;
1362 cpu
->id_dfr0
= 0x02010555;
1363 cpu
->pmceid0
= 0x0000000;
1364 cpu
->pmceid1
= 0x00000000;
1365 cpu
->id_afr0
= 0x00000000;
1366 cpu
->id_mmfr0
= 0x10201105;
1367 cpu
->id_mmfr1
= 0x20000000;
1368 cpu
->id_mmfr2
= 0x01240000;
1369 cpu
->id_mmfr3
= 0x02102211;
1370 cpu
->id_isar0
= 0x02101110;
1371 cpu
->id_isar1
= 0x13112111;
1372 cpu
->id_isar2
= 0x21232041;
1373 cpu
->id_isar3
= 0x11112131;
1374 cpu
->id_isar4
= 0x10011142;
1375 cpu
->dbgdidr
= 0x3515f021;
1376 cpu
->clidr
= 0x0a200023;
1377 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
1378 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
1379 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
1380 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
);
1383 static void ti925t_initfn(Object
*obj
)
1385 ARMCPU
*cpu
= ARM_CPU(obj
);
1386 set_feature(&cpu
->env
, ARM_FEATURE_V4T
);
1387 set_feature(&cpu
->env
, ARM_FEATURE_OMAPCP
);
1388 cpu
->midr
= ARM_CPUID_TI925T
;
1389 cpu
->ctr
= 0x5109149;
1390 cpu
->reset_sctlr
= 0x00000070;
1393 static void sa1100_initfn(Object
*obj
)
1395 ARMCPU
*cpu
= ARM_CPU(obj
);
1397 cpu
->dtb_compatible
= "intel,sa1100";
1398 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
1399 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1400 cpu
->midr
= 0x4401A11B;
1401 cpu
->reset_sctlr
= 0x00000070;
1404 static void sa1110_initfn(Object
*obj
)
1406 ARMCPU
*cpu
= ARM_CPU(obj
);
1407 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
1408 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1409 cpu
->midr
= 0x6901B119;
1410 cpu
->reset_sctlr
= 0x00000070;
1413 static void pxa250_initfn(Object
*obj
)
1415 ARMCPU
*cpu
= ARM_CPU(obj
);
1417 cpu
->dtb_compatible
= "marvell,xscale";
1418 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1419 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1420 cpu
->midr
= 0x69052100;
1421 cpu
->ctr
= 0xd172172;
1422 cpu
->reset_sctlr
= 0x00000078;
1425 static void pxa255_initfn(Object
*obj
)
1427 ARMCPU
*cpu
= ARM_CPU(obj
);
1429 cpu
->dtb_compatible
= "marvell,xscale";
1430 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1431 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1432 cpu
->midr
= 0x69052d00;
1433 cpu
->ctr
= 0xd172172;
1434 cpu
->reset_sctlr
= 0x00000078;
1437 static void pxa260_initfn(Object
*obj
)
1439 ARMCPU
*cpu
= ARM_CPU(obj
);
1441 cpu
->dtb_compatible
= "marvell,xscale";
1442 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1443 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1444 cpu
->midr
= 0x69052903;
1445 cpu
->ctr
= 0xd172172;
1446 cpu
->reset_sctlr
= 0x00000078;
1449 static void pxa261_initfn(Object
*obj
)
1451 ARMCPU
*cpu
= ARM_CPU(obj
);
1453 cpu
->dtb_compatible
= "marvell,xscale";
1454 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1455 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1456 cpu
->midr
= 0x69052d05;
1457 cpu
->ctr
= 0xd172172;
1458 cpu
->reset_sctlr
= 0x00000078;
1461 static void pxa262_initfn(Object
*obj
)
1463 ARMCPU
*cpu
= ARM_CPU(obj
);
1465 cpu
->dtb_compatible
= "marvell,xscale";
1466 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1467 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1468 cpu
->midr
= 0x69052d06;
1469 cpu
->ctr
= 0xd172172;
1470 cpu
->reset_sctlr
= 0x00000078;
1473 static void pxa270a0_initfn(Object
*obj
)
1475 ARMCPU
*cpu
= ARM_CPU(obj
);
1477 cpu
->dtb_compatible
= "marvell,xscale";
1478 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1479 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1480 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1481 cpu
->midr
= 0x69054110;
1482 cpu
->ctr
= 0xd172172;
1483 cpu
->reset_sctlr
= 0x00000078;
1486 static void pxa270a1_initfn(Object
*obj
)
1488 ARMCPU
*cpu
= ARM_CPU(obj
);
1490 cpu
->dtb_compatible
= "marvell,xscale";
1491 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1492 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1493 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1494 cpu
->midr
= 0x69054111;
1495 cpu
->ctr
= 0xd172172;
1496 cpu
->reset_sctlr
= 0x00000078;
1499 static void pxa270b0_initfn(Object
*obj
)
1501 ARMCPU
*cpu
= ARM_CPU(obj
);
1503 cpu
->dtb_compatible
= "marvell,xscale";
1504 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1505 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1506 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1507 cpu
->midr
= 0x69054112;
1508 cpu
->ctr
= 0xd172172;
1509 cpu
->reset_sctlr
= 0x00000078;
1512 static void pxa270b1_initfn(Object
*obj
)
1514 ARMCPU
*cpu
= ARM_CPU(obj
);
1516 cpu
->dtb_compatible
= "marvell,xscale";
1517 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1518 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1519 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1520 cpu
->midr
= 0x69054113;
1521 cpu
->ctr
= 0xd172172;
1522 cpu
->reset_sctlr
= 0x00000078;
1525 static void pxa270c0_initfn(Object
*obj
)
1527 ARMCPU
*cpu
= ARM_CPU(obj
);
1529 cpu
->dtb_compatible
= "marvell,xscale";
1530 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1531 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1532 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1533 cpu
->midr
= 0x69054114;
1534 cpu
->ctr
= 0xd172172;
1535 cpu
->reset_sctlr
= 0x00000078;
1538 static void pxa270c5_initfn(Object
*obj
)
1540 ARMCPU
*cpu
= ARM_CPU(obj
);
1542 cpu
->dtb_compatible
= "marvell,xscale";
1543 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1544 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1545 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1546 cpu
->midr
= 0x69054117;
1547 cpu
->ctr
= 0xd172172;
1548 cpu
->reset_sctlr
= 0x00000078;
1551 #ifdef CONFIG_USER_ONLY
1552 static void arm_any_initfn(Object
*obj
)
1554 ARMCPU
*cpu
= ARM_CPU(obj
);
1555 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
1556 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
1557 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1558 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1559 set_feature(&cpu
->env
, ARM_FEATURE_V8_AES
);
1560 set_feature(&cpu
->env
, ARM_FEATURE_V8_SHA1
);
1561 set_feature(&cpu
->env
, ARM_FEATURE_V8_SHA256
);
1562 set_feature(&cpu
->env
, ARM_FEATURE_V8_PMULL
);
1563 set_feature(&cpu
->env
, ARM_FEATURE_CRC
);
1564 cpu
->midr
= 0xffffffff;
1568 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1570 typedef struct ARMCPUInfo
{
1572 void (*initfn
)(Object
*obj
);
1573 void (*class_init
)(ObjectClass
*oc
, void *data
);
1576 static const ARMCPUInfo arm_cpus
[] = {
1577 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1578 { .name
= "arm926", .initfn
= arm926_initfn
},
1579 { .name
= "arm946", .initfn
= arm946_initfn
},
1580 { .name
= "arm1026", .initfn
= arm1026_initfn
},
1581 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1582 * older core than plain "arm1136". In particular this does not
1583 * have the v6K features.
1585 { .name
= "arm1136-r2", .initfn
= arm1136_r2_initfn
},
1586 { .name
= "arm1136", .initfn
= arm1136_initfn
},
1587 { .name
= "arm1176", .initfn
= arm1176_initfn
},
1588 { .name
= "arm11mpcore", .initfn
= arm11mpcore_initfn
},
1589 { .name
= "cortex-m3", .initfn
= cortex_m3_initfn
,
1590 .class_init
= arm_v7m_class_init
},
1591 { .name
= "cortex-m4", .initfn
= cortex_m4_initfn
,
1592 .class_init
= arm_v7m_class_init
},
1593 { .name
= "cortex-r5", .initfn
= cortex_r5_initfn
},
1594 { .name
= "cortex-a7", .initfn
= cortex_a7_initfn
},
1595 { .name
= "cortex-a8", .initfn
= cortex_a8_initfn
},
1596 { .name
= "cortex-a9", .initfn
= cortex_a9_initfn
},
1597 { .name
= "cortex-a15", .initfn
= cortex_a15_initfn
},
1598 { .name
= "ti925t", .initfn
= ti925t_initfn
},
1599 { .name
= "sa1100", .initfn
= sa1100_initfn
},
1600 { .name
= "sa1110", .initfn
= sa1110_initfn
},
1601 { .name
= "pxa250", .initfn
= pxa250_initfn
},
1602 { .name
= "pxa255", .initfn
= pxa255_initfn
},
1603 { .name
= "pxa260", .initfn
= pxa260_initfn
},
1604 { .name
= "pxa261", .initfn
= pxa261_initfn
},
1605 { .name
= "pxa262", .initfn
= pxa262_initfn
},
1606 /* "pxa270" is an alias for "pxa270-a0" */
1607 { .name
= "pxa270", .initfn
= pxa270a0_initfn
},
1608 { .name
= "pxa270-a0", .initfn
= pxa270a0_initfn
},
1609 { .name
= "pxa270-a1", .initfn
= pxa270a1_initfn
},
1610 { .name
= "pxa270-b0", .initfn
= pxa270b0_initfn
},
1611 { .name
= "pxa270-b1", .initfn
= pxa270b1_initfn
},
1612 { .name
= "pxa270-c0", .initfn
= pxa270c0_initfn
},
1613 { .name
= "pxa270-c5", .initfn
= pxa270c5_initfn
},
1614 #ifdef CONFIG_USER_ONLY
1615 { .name
= "any", .initfn
= arm_any_initfn
},
1621 static Property arm_cpu_properties
[] = {
1622 DEFINE_PROP_BOOL("start-powered-off", ARMCPU
, start_powered_off
, false),
1623 DEFINE_PROP_UINT32("psci-conduit", ARMCPU
, psci_conduit
, 0),
1624 DEFINE_PROP_UINT32("midr", ARMCPU
, midr
, 0),
1625 DEFINE_PROP_UINT64("mp-affinity", ARMCPU
,
1626 mp_affinity
, ARM64_AFFINITY_INVALID
),
1627 DEFINE_PROP_INT32("node-id", ARMCPU
, node_id
, CPU_UNSET_NUMA_NODE_ID
),
1628 DEFINE_PROP_END_OF_LIST()
1631 #ifdef CONFIG_USER_ONLY
1632 static int arm_cpu_handle_mmu_fault(CPUState
*cs
, vaddr address
, int rw
,
1635 ARMCPU
*cpu
= ARM_CPU(cs
);
1636 CPUARMState
*env
= &cpu
->env
;
1638 env
->exception
.vaddress
= address
;
1640 cs
->exception_index
= EXCP_PREFETCH_ABORT
;
1642 cs
->exception_index
= EXCP_DATA_ABORT
;
1648 static gchar
*arm_gdb_arch_name(CPUState
*cs
)
1650 ARMCPU
*cpu
= ARM_CPU(cs
);
1651 CPUARMState
*env
= &cpu
->env
;
1653 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
1654 return g_strdup("iwmmxt");
1656 return g_strdup("arm");
1659 static void arm_cpu_class_init(ObjectClass
*oc
, void *data
)
1661 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
1662 CPUClass
*cc
= CPU_CLASS(acc
);
1663 DeviceClass
*dc
= DEVICE_CLASS(oc
);
1665 acc
->parent_realize
= dc
->realize
;
1666 dc
->realize
= arm_cpu_realizefn
;
1667 dc
->props
= arm_cpu_properties
;
1669 acc
->parent_reset
= cc
->reset
;
1670 cc
->reset
= arm_cpu_reset
;
1672 cc
->class_by_name
= arm_cpu_class_by_name
;
1673 cc
->has_work
= arm_cpu_has_work
;
1674 cc
->cpu_exec_interrupt
= arm_cpu_exec_interrupt
;
1675 cc
->dump_state
= arm_cpu_dump_state
;
1676 cc
->set_pc
= arm_cpu_set_pc
;
1677 cc
->gdb_read_register
= arm_cpu_gdb_read_register
;
1678 cc
->gdb_write_register
= arm_cpu_gdb_write_register
;
1679 #ifdef CONFIG_USER_ONLY
1680 cc
->handle_mmu_fault
= arm_cpu_handle_mmu_fault
;
1682 cc
->do_interrupt
= arm_cpu_do_interrupt
;
1683 cc
->do_unaligned_access
= arm_cpu_do_unaligned_access
;
1684 cc
->get_phys_page_attrs_debug
= arm_cpu_get_phys_page_attrs_debug
;
1685 cc
->asidx_from_attrs
= arm_asidx_from_attrs
;
1686 cc
->vmsd
= &vmstate_arm_cpu
;
1687 cc
->virtio_is_big_endian
= arm_cpu_virtio_is_big_endian
;
1688 cc
->write_elf64_note
= arm_cpu_write_elf64_note
;
1689 cc
->write_elf32_note
= arm_cpu_write_elf32_note
;
1691 cc
->gdb_num_core_regs
= 26;
1692 cc
->gdb_core_xml_file
= "arm-core.xml";
1693 cc
->gdb_arch_name
= arm_gdb_arch_name
;
1694 cc
->gdb_stop_before_watchpoint
= true;
1695 cc
->debug_excp_handler
= arm_debug_excp_handler
;
1696 cc
->debug_check_watchpoint
= arm_debug_check_watchpoint
;
1697 #if !defined(CONFIG_USER_ONLY)
1698 cc
->adjust_watchpoint_address
= arm_adjust_watchpoint_address
;
1701 cc
->disas_set_info
= arm_disas_set_info
;
1704 static void cpu_register(const ARMCPUInfo
*info
)
1706 TypeInfo type_info
= {
1707 .parent
= TYPE_ARM_CPU
,
1708 .instance_size
= sizeof(ARMCPU
),
1709 .instance_init
= info
->initfn
,
1710 .class_size
= sizeof(ARMCPUClass
),
1711 .class_init
= info
->class_init
,
1714 type_info
.name
= g_strdup_printf("%s-" TYPE_ARM_CPU
, info
->name
);
1715 type_register(&type_info
);
1716 g_free((void *)type_info
.name
);
1719 static const TypeInfo arm_cpu_type_info
= {
1720 .name
= TYPE_ARM_CPU
,
1722 .instance_size
= sizeof(ARMCPU
),
1723 .instance_init
= arm_cpu_initfn
,
1724 .instance_post_init
= arm_cpu_post_init
,
1725 .instance_finalize
= arm_cpu_finalizefn
,
1727 .class_size
= sizeof(ARMCPUClass
),
1728 .class_init
= arm_cpu_class_init
,
1731 static void arm_cpu_register_types(void)
1733 const ARMCPUInfo
*info
= arm_cpus
;
1735 type_register_static(&arm_cpu_type_info
);
1737 while (info
->name
) {
1743 type_init(arm_cpu_register_types
)