2 * QEMU VMWARE VMXNET3 paravirtual NIC
4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
6 * Developed by Daynix Computing LTD (http://www.daynix.com)
9 * Dmitry Fleytman <dmitry@daynix.com>
10 * Tamir Shomer <tamirs@daynix.com>
11 * Yan Vugenfirer <yan@daynix.com>
13 * This work is licensed under the terms of the GNU GPL, version 2.
14 * See the COPYING file in the top-level directory.
18 #include "qemu/osdep.h"
20 #include "hw/pci/pci.h"
23 #include "net/checksum.h"
24 #include "sysemu/sysemu.h"
25 #include "qemu-common.h"
26 #include "qemu/bswap.h"
27 #include "hw/pci/msix.h"
28 #include "hw/pci/msi.h"
29 #include "migration/register.h"
32 #include "vmxnet_debug.h"
33 #include "vmware_utils.h"
34 #include "net_tx_pkt.h"
35 #include "net_rx_pkt.h"
37 #define PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION 0x1
38 #define VMXNET3_MSIX_BAR_SIZE 0x2000
39 #define MIN_BUF_SIZE 60
41 /* Compatibility flags for migration */
42 #define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT 0
43 #define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS \
44 (1 << VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT)
45 #define VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT 1
46 #define VMXNET3_COMPAT_FLAG_DISABLE_PCIE \
47 (1 << VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT)
49 #define VMXNET3_EXP_EP_OFFSET (0x48)
50 #define VMXNET3_MSI_OFFSET(s) \
51 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x50 : 0x84)
52 #define VMXNET3_MSIX_OFFSET(s) \
53 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0 : 0x9c)
54 #define VMXNET3_DSN_OFFSET (0x100)
56 #define VMXNET3_BAR0_IDX (0)
57 #define VMXNET3_BAR1_IDX (1)
58 #define VMXNET3_MSIX_BAR_IDX (2)
60 #define VMXNET3_OFF_MSIX_TABLE (0x000)
61 #define VMXNET3_OFF_MSIX_PBA(s) \
62 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x800 : 0x1000)
64 /* Link speed in Mbps should be shifted by 16 */
65 #define VMXNET3_LINK_SPEED (1000 << 16)
67 /* Link status: 1 - up, 0 - down. */
68 #define VMXNET3_LINK_STATUS_UP 0x1
70 /* Least significant bit should be set for revision and version */
71 #define VMXNET3_UPT_REVISION 0x1
72 #define VMXNET3_DEVICE_REVISION 0x1
74 /* Number of interrupt vectors for non-MSIx modes */
75 #define VMXNET3_MAX_NMSIX_INTRS (1)
77 /* Macros for rings descriptors access */
78 #define VMXNET3_READ_TX_QUEUE_DESCR8(_d, dpa, field) \
79 (vmw_shmem_ld8(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
81 #define VMXNET3_WRITE_TX_QUEUE_DESCR8(_d, dpa, field, value) \
82 (vmw_shmem_st8(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field, value)))
84 #define VMXNET3_READ_TX_QUEUE_DESCR32(_d, dpa, field) \
85 (vmw_shmem_ld32(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
87 #define VMXNET3_WRITE_TX_QUEUE_DESCR32(_d, dpa, field, value) \
88 (vmw_shmem_st32(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value))
90 #define VMXNET3_READ_TX_QUEUE_DESCR64(_d, dpa, field) \
91 (vmw_shmem_ld64(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
93 #define VMXNET3_WRITE_TX_QUEUE_DESCR64(_d, dpa, field, value) \
94 (vmw_shmem_st64(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value))
96 #define VMXNET3_READ_RX_QUEUE_DESCR64(_d, dpa, field) \
97 (vmw_shmem_ld64(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field)))
99 #define VMXNET3_READ_RX_QUEUE_DESCR32(_d, dpa, field) \
100 (vmw_shmem_ld32(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field)))
102 #define VMXNET3_WRITE_RX_QUEUE_DESCR64(_d, dpa, field, value) \
103 (vmw_shmem_st64(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value))
105 #define VMXNET3_WRITE_RX_QUEUE_DESCR8(_d, dpa, field, value) \
106 (vmw_shmem_st8(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value))
108 /* Macros for guest driver shared area access */
109 #define VMXNET3_READ_DRV_SHARED64(_d, shpa, field) \
110 (vmw_shmem_ld64(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field)))
112 #define VMXNET3_READ_DRV_SHARED32(_d, shpa, field) \
113 (vmw_shmem_ld32(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field)))
115 #define VMXNET3_WRITE_DRV_SHARED32(_d, shpa, field, val) \
116 (vmw_shmem_st32(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field), val))
118 #define VMXNET3_READ_DRV_SHARED16(_d, shpa, field) \
119 (vmw_shmem_ld16(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field)))
121 #define VMXNET3_READ_DRV_SHARED8(_d, shpa, field) \
122 (vmw_shmem_ld8(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field)))
124 #define VMXNET3_READ_DRV_SHARED(_d, shpa, field, b, l) \
125 (vmw_shmem_read(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field), b, l))
127 #define VMXNET_FLAG_IS_SET(field, flag) (((field) & (flag)) == (flag))
129 typedef struct VMXNET3Class
{
130 PCIDeviceClass parent_class
;
131 DeviceRealize parent_dc_realize
;
134 #define TYPE_VMXNET3 "vmxnet3"
135 #define VMXNET3(obj) OBJECT_CHECK(VMXNET3State, (obj), TYPE_VMXNET3)
137 #define VMXNET3_DEVICE_CLASS(klass) \
138 OBJECT_CLASS_CHECK(VMXNET3Class, (klass), TYPE_VMXNET3)
139 #define VMXNET3_DEVICE_GET_CLASS(obj) \
140 OBJECT_GET_CLASS(VMXNET3Class, (obj), TYPE_VMXNET3)
142 /* Cyclic ring abstraction */
151 static inline void vmxnet3_ring_init(PCIDevice
*d
,
160 ring
->cell_size
= cell_size
;
161 ring
->gen
= VMXNET3_INIT_GEN
;
165 vmw_shmem_set(d
, pa
, 0, size
* cell_size
);
169 #define VMXNET3_RING_DUMP(macro, ring_name, ridx, r) \
170 macro("%s#%d: base %" PRIx64 " size %u cell_size %u gen %d next %u", \
171 (ring_name), (ridx), \
172 (r)->pa, (r)->size, (r)->cell_size, (r)->gen, (r)->next)
174 static inline void vmxnet3_ring_inc(Vmxnet3Ring
*ring
)
176 if (++ring
->next
>= ring
->size
) {
182 static inline void vmxnet3_ring_dec(Vmxnet3Ring
*ring
)
184 if (ring
->next
-- == 0) {
185 ring
->next
= ring
->size
- 1;
190 static inline hwaddr
vmxnet3_ring_curr_cell_pa(Vmxnet3Ring
*ring
)
192 return ring
->pa
+ ring
->next
* ring
->cell_size
;
195 static inline void vmxnet3_ring_read_curr_cell(PCIDevice
*d
, Vmxnet3Ring
*ring
,
198 vmw_shmem_read(d
, vmxnet3_ring_curr_cell_pa(ring
), buff
, ring
->cell_size
);
201 static inline void vmxnet3_ring_write_curr_cell(PCIDevice
*d
, Vmxnet3Ring
*ring
,
204 vmw_shmem_write(d
, vmxnet3_ring_curr_cell_pa(ring
), buff
, ring
->cell_size
);
207 static inline size_t vmxnet3_ring_curr_cell_idx(Vmxnet3Ring
*ring
)
212 static inline uint8_t vmxnet3_ring_curr_gen(Vmxnet3Ring
*ring
)
217 /* Debug trace-related functions */
219 vmxnet3_dump_tx_descr(struct Vmxnet3_TxDesc
*descr
)
221 VMW_PKPRN("TX DESCR: "
222 "addr %" PRIx64
", len: %d, gen: %d, rsvd: %d, "
223 "dtype: %d, ext1: %d, msscof: %d, hlen: %d, om: %d, "
224 "eop: %d, cq: %d, ext2: %d, ti: %d, tci: %d",
225 le64_to_cpu(descr
->addr
), descr
->len
, descr
->gen
, descr
->rsvd
,
226 descr
->dtype
, descr
->ext1
, descr
->msscof
, descr
->hlen
, descr
->om
,
227 descr
->eop
, descr
->cq
, descr
->ext2
, descr
->ti
, descr
->tci
);
231 vmxnet3_dump_virt_hdr(struct virtio_net_hdr
*vhdr
)
233 VMW_PKPRN("VHDR: flags 0x%x, gso_type: 0x%x, hdr_len: %d, gso_size: %d, "
234 "csum_start: %d, csum_offset: %d",
235 vhdr
->flags
, vhdr
->gso_type
, vhdr
->hdr_len
, vhdr
->gso_size
,
236 vhdr
->csum_start
, vhdr
->csum_offset
);
240 vmxnet3_dump_rx_descr(struct Vmxnet3_RxDesc
*descr
)
242 VMW_PKPRN("RX DESCR: addr %" PRIx64
", len: %d, gen: %d, rsvd: %d, "
243 "dtype: %d, ext1: %d, btype: %d",
244 le64_to_cpu(descr
->addr
), descr
->len
, descr
->gen
,
245 descr
->rsvd
, descr
->dtype
, descr
->ext1
, descr
->btype
);
248 /* Device state and helper functions */
249 #define VMXNET3_RX_RINGS_PER_QUEUE (2)
253 Vmxnet3Ring comp_ring
;
257 struct UPT1_TxStats txq_stats
;
261 Vmxnet3Ring rx_ring
[VMXNET3_RX_RINGS_PER_QUEUE
];
262 Vmxnet3Ring comp_ring
;
265 struct UPT1_RxStats rxq_stats
;
275 PCIDevice parent_obj
;
280 MemoryRegion msix_bar
;
282 Vmxnet3RxqDescr rxq_descr
[VMXNET3_DEVICE_MAX_RX_QUEUES
];
283 Vmxnet3TxqDescr txq_descr
[VMXNET3_DEVICE_MAX_TX_QUEUES
];
285 /* Whether MSI-X support was installed successfully */
288 hwaddr temp_shared_guest_driver_memory
;
292 /* This boolean tells whether RX packet being indicated has to */
293 /* be split into head and body chunks from different RX rings */
294 bool rx_packets_compound
;
296 bool rx_vlan_stripping
;
304 /* Maximum number of fragments for indicated TX packets */
305 uint32_t max_tx_frags
;
307 /* Maximum number of fragments for indicated RX packets */
308 uint16_t max_rx_frags
;
310 /* Index for events interrupt */
311 uint8_t event_int_idx
;
313 /* Whether automatic interrupts masking enabled */
314 bool auto_int_masking
;
318 /* TX packets to QEMU interface */
319 struct NetTxPkt
*tx_pkt
;
320 uint32_t offload_mode
;
321 uint32_t cso_or_gso_size
;
325 struct NetRxPkt
*rx_pkt
;
328 bool skip_current_tx_pkt
;
330 uint32_t device_active
;
331 uint32_t last_command
;
333 uint32_t link_status_and_speed
;
335 Vmxnet3IntState interrupt_states
[VMXNET3_MAX_INTRS
];
337 uint32_t temp_mac
; /* To store the low part first */
340 uint32_t vlan_table
[VMXNET3_VFT_SIZE
];
343 uint32_t mcast_list_len
;
344 uint32_t mcast_list_buff_size
; /* needed for live migration. */
346 /* Compatibility flags for migration */
347 uint32_t compat_flags
;
350 /* Interrupt management */
353 * This function returns sign whether interrupt line is in asserted state
354 * This depends on the type of interrupt used. For INTX interrupt line will
355 * be asserted until explicit deassertion, for MSI(X) interrupt line will
356 * be deasserted automatically due to notification semantics of the MSI(X)
359 static bool _vmxnet3_assert_interrupt_line(VMXNET3State
*s
, uint32_t int_idx
)
361 PCIDevice
*d
= PCI_DEVICE(s
);
363 if (s
->msix_used
&& msix_enabled(d
)) {
364 VMW_IRPRN("Sending MSI-X notification for vector %u", int_idx
);
365 msix_notify(d
, int_idx
);
368 if (msi_enabled(d
)) {
369 VMW_IRPRN("Sending MSI notification for vector %u", int_idx
);
370 msi_notify(d
, int_idx
);
374 VMW_IRPRN("Asserting line for interrupt %u", int_idx
);
379 static void _vmxnet3_deassert_interrupt_line(VMXNET3State
*s
, int lidx
)
381 PCIDevice
*d
= PCI_DEVICE(s
);
384 * This function should never be called for MSI(X) interrupts
385 * because deassertion never required for message interrupts
387 assert(!s
->msix_used
|| !msix_enabled(d
));
389 * This function should never be called for MSI(X) interrupts
390 * because deassertion never required for message interrupts
392 assert(!msi_enabled(d
));
394 VMW_IRPRN("Deasserting line for interrupt %u", lidx
);
398 static void vmxnet3_update_interrupt_line_state(VMXNET3State
*s
, int lidx
)
400 if (!s
->interrupt_states
[lidx
].is_pending
&&
401 s
->interrupt_states
[lidx
].is_asserted
) {
402 VMW_IRPRN("New interrupt line state for index %d is DOWN", lidx
);
403 _vmxnet3_deassert_interrupt_line(s
, lidx
);
404 s
->interrupt_states
[lidx
].is_asserted
= false;
408 if (s
->interrupt_states
[lidx
].is_pending
&&
409 !s
->interrupt_states
[lidx
].is_masked
&&
410 !s
->interrupt_states
[lidx
].is_asserted
) {
411 VMW_IRPRN("New interrupt line state for index %d is UP", lidx
);
412 s
->interrupt_states
[lidx
].is_asserted
=
413 _vmxnet3_assert_interrupt_line(s
, lidx
);
414 s
->interrupt_states
[lidx
].is_pending
= false;
419 static void vmxnet3_trigger_interrupt(VMXNET3State
*s
, int lidx
)
421 PCIDevice
*d
= PCI_DEVICE(s
);
422 s
->interrupt_states
[lidx
].is_pending
= true;
423 vmxnet3_update_interrupt_line_state(s
, lidx
);
425 if (s
->msix_used
&& msix_enabled(d
) && s
->auto_int_masking
) {
429 if (msi_enabled(d
) && s
->auto_int_masking
) {
436 s
->interrupt_states
[lidx
].is_masked
= true;
437 vmxnet3_update_interrupt_line_state(s
, lidx
);
440 static bool vmxnet3_interrupt_asserted(VMXNET3State
*s
, int lidx
)
442 return s
->interrupt_states
[lidx
].is_asserted
;
445 static void vmxnet3_clear_interrupt(VMXNET3State
*s
, int int_idx
)
447 s
->interrupt_states
[int_idx
].is_pending
= false;
448 if (s
->auto_int_masking
) {
449 s
->interrupt_states
[int_idx
].is_masked
= true;
451 vmxnet3_update_interrupt_line_state(s
, int_idx
);
455 vmxnet3_on_interrupt_mask_changed(VMXNET3State
*s
, int lidx
, bool is_masked
)
457 s
->interrupt_states
[lidx
].is_masked
= is_masked
;
458 vmxnet3_update_interrupt_line_state(s
, lidx
);
461 static bool vmxnet3_verify_driver_magic(PCIDevice
*d
, hwaddr dshmem
)
463 return (VMXNET3_READ_DRV_SHARED32(d
, dshmem
, magic
) == VMXNET3_REV1_MAGIC
);
466 #define VMXNET3_GET_BYTE(x, byte_num) (((x) >> (byte_num)*8) & 0xFF)
467 #define VMXNET3_MAKE_BYTE(byte_num, val) \
468 (((uint32_t)((val) & 0xFF)) << (byte_num)*8)
470 static void vmxnet3_set_variable_mac(VMXNET3State
*s
, uint32_t h
, uint32_t l
)
472 s
->conf
.macaddr
.a
[0] = VMXNET3_GET_BYTE(l
, 0);
473 s
->conf
.macaddr
.a
[1] = VMXNET3_GET_BYTE(l
, 1);
474 s
->conf
.macaddr
.a
[2] = VMXNET3_GET_BYTE(l
, 2);
475 s
->conf
.macaddr
.a
[3] = VMXNET3_GET_BYTE(l
, 3);
476 s
->conf
.macaddr
.a
[4] = VMXNET3_GET_BYTE(h
, 0);
477 s
->conf
.macaddr
.a
[5] = VMXNET3_GET_BYTE(h
, 1);
479 VMW_CFPRN("Variable MAC: " MAC_FMT
, MAC_ARG(s
->conf
.macaddr
.a
));
481 qemu_format_nic_info_str(qemu_get_queue(s
->nic
), s
->conf
.macaddr
.a
);
484 static uint64_t vmxnet3_get_mac_low(MACAddr
*addr
)
486 return VMXNET3_MAKE_BYTE(0, addr
->a
[0]) |
487 VMXNET3_MAKE_BYTE(1, addr
->a
[1]) |
488 VMXNET3_MAKE_BYTE(2, addr
->a
[2]) |
489 VMXNET3_MAKE_BYTE(3, addr
->a
[3]);
492 static uint64_t vmxnet3_get_mac_high(MACAddr
*addr
)
494 return VMXNET3_MAKE_BYTE(0, addr
->a
[4]) |
495 VMXNET3_MAKE_BYTE(1, addr
->a
[5]);
499 vmxnet3_inc_tx_consumption_counter(VMXNET3State
*s
, int qidx
)
501 vmxnet3_ring_inc(&s
->txq_descr
[qidx
].tx_ring
);
505 vmxnet3_inc_rx_consumption_counter(VMXNET3State
*s
, int qidx
, int ridx
)
507 vmxnet3_ring_inc(&s
->rxq_descr
[qidx
].rx_ring
[ridx
]);
511 vmxnet3_inc_tx_completion_counter(VMXNET3State
*s
, int qidx
)
513 vmxnet3_ring_inc(&s
->txq_descr
[qidx
].comp_ring
);
517 vmxnet3_inc_rx_completion_counter(VMXNET3State
*s
, int qidx
)
519 vmxnet3_ring_inc(&s
->rxq_descr
[qidx
].comp_ring
);
523 vmxnet3_dec_rx_completion_counter(VMXNET3State
*s
, int qidx
)
525 vmxnet3_ring_dec(&s
->rxq_descr
[qidx
].comp_ring
);
528 static void vmxnet3_complete_packet(VMXNET3State
*s
, int qidx
, uint32_t tx_ridx
)
530 struct Vmxnet3_TxCompDesc txcq_descr
;
531 PCIDevice
*d
= PCI_DEVICE(s
);
533 VMXNET3_RING_DUMP(VMW_RIPRN
, "TXC", qidx
, &s
->txq_descr
[qidx
].comp_ring
);
535 memset(&txcq_descr
, 0, sizeof(txcq_descr
));
536 txcq_descr
.txdIdx
= tx_ridx
;
537 txcq_descr
.gen
= vmxnet3_ring_curr_gen(&s
->txq_descr
[qidx
].comp_ring
);
539 vmxnet3_ring_write_curr_cell(d
, &s
->txq_descr
[qidx
].comp_ring
, &txcq_descr
);
541 /* Flush changes in TX descriptor before changing the counter value */
544 vmxnet3_inc_tx_completion_counter(s
, qidx
);
545 vmxnet3_trigger_interrupt(s
, s
->txq_descr
[qidx
].intr_idx
);
549 vmxnet3_setup_tx_offloads(VMXNET3State
*s
)
551 switch (s
->offload_mode
) {
552 case VMXNET3_OM_NONE
:
553 net_tx_pkt_build_vheader(s
->tx_pkt
, false, false, 0);
556 case VMXNET3_OM_CSUM
:
557 net_tx_pkt_build_vheader(s
->tx_pkt
, false, true, 0);
558 VMW_PKPRN("L4 CSO requested\n");
562 net_tx_pkt_build_vheader(s
->tx_pkt
, true, true,
564 net_tx_pkt_update_ip_checksums(s
->tx_pkt
);
565 VMW_PKPRN("GSO offload requested.");
569 g_assert_not_reached();
577 vmxnet3_tx_retrieve_metadata(VMXNET3State
*s
,
578 const struct Vmxnet3_TxDesc
*txd
)
580 s
->offload_mode
= txd
->om
;
581 s
->cso_or_gso_size
= txd
->msscof
;
583 s
->needs_vlan
= txd
->ti
;
587 VMXNET3_PKT_STATUS_OK
,
588 VMXNET3_PKT_STATUS_ERROR
,
589 VMXNET3_PKT_STATUS_DISCARD
,/* only for tx */
590 VMXNET3_PKT_STATUS_OUT_OF_BUF
/* only for rx */
594 vmxnet3_on_tx_done_update_stats(VMXNET3State
*s
, int qidx
,
595 Vmxnet3PktStatus status
)
597 size_t tot_len
= net_tx_pkt_get_total_len(s
->tx_pkt
);
598 struct UPT1_TxStats
*stats
= &s
->txq_descr
[qidx
].txq_stats
;
601 case VMXNET3_PKT_STATUS_OK
:
602 switch (net_tx_pkt_get_packet_type(s
->tx_pkt
)) {
604 stats
->bcastPktsTxOK
++;
605 stats
->bcastBytesTxOK
+= tot_len
;
608 stats
->mcastPktsTxOK
++;
609 stats
->mcastBytesTxOK
+= tot_len
;
612 stats
->ucastPktsTxOK
++;
613 stats
->ucastBytesTxOK
+= tot_len
;
616 g_assert_not_reached();
619 if (s
->offload_mode
== VMXNET3_OM_TSO
) {
621 * According to VMWARE headers this statistic is a number
622 * of packets after segmentation but since we don't have
623 * this information in QEMU model, the best we can do is to
624 * provide number of non-segmented packets
626 stats
->TSOPktsTxOK
++;
627 stats
->TSOBytesTxOK
+= tot_len
;
631 case VMXNET3_PKT_STATUS_DISCARD
:
632 stats
->pktsTxDiscard
++;
635 case VMXNET3_PKT_STATUS_ERROR
:
636 stats
->pktsTxError
++;
640 g_assert_not_reached();
645 vmxnet3_on_rx_done_update_stats(VMXNET3State
*s
,
647 Vmxnet3PktStatus status
)
649 struct UPT1_RxStats
*stats
= &s
->rxq_descr
[qidx
].rxq_stats
;
650 size_t tot_len
= net_rx_pkt_get_total_len(s
->rx_pkt
);
653 case VMXNET3_PKT_STATUS_OUT_OF_BUF
:
654 stats
->pktsRxOutOfBuf
++;
657 case VMXNET3_PKT_STATUS_ERROR
:
658 stats
->pktsRxError
++;
660 case VMXNET3_PKT_STATUS_OK
:
661 switch (net_rx_pkt_get_packet_type(s
->rx_pkt
)) {
663 stats
->bcastPktsRxOK
++;
664 stats
->bcastBytesRxOK
+= tot_len
;
667 stats
->mcastPktsRxOK
++;
668 stats
->mcastBytesRxOK
+= tot_len
;
671 stats
->ucastPktsRxOK
++;
672 stats
->ucastBytesRxOK
+= tot_len
;
675 g_assert_not_reached();
678 if (tot_len
> s
->mtu
) {
679 stats
->LROPktsRxOK
++;
680 stats
->LROBytesRxOK
+= tot_len
;
684 g_assert_not_reached();
689 vmxnet3_pop_next_tx_descr(VMXNET3State
*s
,
691 struct Vmxnet3_TxDesc
*txd
,
694 Vmxnet3Ring
*ring
= &s
->txq_descr
[qidx
].tx_ring
;
695 PCIDevice
*d
= PCI_DEVICE(s
);
697 vmxnet3_ring_read_curr_cell(d
, ring
, txd
);
698 if (txd
->gen
== vmxnet3_ring_curr_gen(ring
)) {
699 /* Only read after generation field verification */
701 /* Re-read to be sure we got the latest version */
702 vmxnet3_ring_read_curr_cell(d
, ring
, txd
);
703 VMXNET3_RING_DUMP(VMW_RIPRN
, "TX", qidx
, ring
);
704 *descr_idx
= vmxnet3_ring_curr_cell_idx(ring
);
705 vmxnet3_inc_tx_consumption_counter(s
, qidx
);
713 vmxnet3_send_packet(VMXNET3State
*s
, uint32_t qidx
)
715 Vmxnet3PktStatus status
= VMXNET3_PKT_STATUS_OK
;
717 if (!vmxnet3_setup_tx_offloads(s
)) {
718 status
= VMXNET3_PKT_STATUS_ERROR
;
723 vmxnet3_dump_virt_hdr(net_tx_pkt_get_vhdr(s
->tx_pkt
));
724 net_tx_pkt_dump(s
->tx_pkt
);
726 if (!net_tx_pkt_send(s
->tx_pkt
, qemu_get_queue(s
->nic
))) {
727 status
= VMXNET3_PKT_STATUS_DISCARD
;
732 vmxnet3_on_tx_done_update_stats(s
, qidx
, status
);
733 return (status
== VMXNET3_PKT_STATUS_OK
);
736 static void vmxnet3_process_tx_queue(VMXNET3State
*s
, int qidx
)
738 struct Vmxnet3_TxDesc txd
;
744 if (!vmxnet3_pop_next_tx_descr(s
, qidx
, &txd
, &txd_idx
)) {
748 vmxnet3_dump_tx_descr(&txd
);
750 if (!s
->skip_current_tx_pkt
) {
751 data_len
= (txd
.len
> 0) ? txd
.len
: VMXNET3_MAX_TX_BUF_SIZE
;
752 data_pa
= le64_to_cpu(txd
.addr
);
754 if (!net_tx_pkt_add_raw_fragment(s
->tx_pkt
,
757 s
->skip_current_tx_pkt
= true;
762 vmxnet3_tx_retrieve_metadata(s
, &txd
);
767 if (!s
->skip_current_tx_pkt
&& net_tx_pkt_parse(s
->tx_pkt
)) {
769 net_tx_pkt_setup_vlan_header(s
->tx_pkt
, s
->tci
);
772 vmxnet3_send_packet(s
, qidx
);
774 vmxnet3_on_tx_done_update_stats(s
, qidx
,
775 VMXNET3_PKT_STATUS_ERROR
);
778 vmxnet3_complete_packet(s
, qidx
, txd_idx
);
780 s
->skip_current_tx_pkt
= false;
781 net_tx_pkt_reset(s
->tx_pkt
);
787 vmxnet3_read_next_rx_descr(VMXNET3State
*s
, int qidx
, int ridx
,
788 struct Vmxnet3_RxDesc
*dbuf
, uint32_t *didx
)
790 PCIDevice
*d
= PCI_DEVICE(s
);
792 Vmxnet3Ring
*ring
= &s
->rxq_descr
[qidx
].rx_ring
[ridx
];
793 *didx
= vmxnet3_ring_curr_cell_idx(ring
);
794 vmxnet3_ring_read_curr_cell(d
, ring
, dbuf
);
797 static inline uint8_t
798 vmxnet3_get_rx_ring_gen(VMXNET3State
*s
, int qidx
, int ridx
)
800 return s
->rxq_descr
[qidx
].rx_ring
[ridx
].gen
;
804 vmxnet3_pop_rxc_descr(VMXNET3State
*s
, int qidx
, uint32_t *descr_gen
)
807 struct Vmxnet3_RxCompDesc rxcd
;
810 vmxnet3_ring_curr_cell_pa(&s
->rxq_descr
[qidx
].comp_ring
);
812 pci_dma_read(PCI_DEVICE(s
),
813 daddr
, &rxcd
, sizeof(struct Vmxnet3_RxCompDesc
));
814 ring_gen
= vmxnet3_ring_curr_gen(&s
->rxq_descr
[qidx
].comp_ring
);
816 if (rxcd
.gen
!= ring_gen
) {
817 *descr_gen
= ring_gen
;
818 vmxnet3_inc_rx_completion_counter(s
, qidx
);
826 vmxnet3_revert_rxc_descr(VMXNET3State
*s
, int qidx
)
828 vmxnet3_dec_rx_completion_counter(s
, qidx
);
832 #define RX_HEAD_BODY_RING (0)
833 #define RX_BODY_ONLY_RING (1)
836 vmxnet3_get_next_head_rx_descr(VMXNET3State
*s
,
837 struct Vmxnet3_RxDesc
*descr_buf
,
843 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_HEAD_BODY_RING
,
844 descr_buf
, descr_idx
);
846 /* If no more free descriptors - return */
847 ring_gen
= vmxnet3_get_rx_ring_gen(s
, RXQ_IDX
, RX_HEAD_BODY_RING
);
848 if (descr_buf
->gen
!= ring_gen
) {
852 /* Only read after generation field verification */
854 /* Re-read to be sure we got the latest version */
855 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_HEAD_BODY_RING
,
856 descr_buf
, descr_idx
);
858 /* Mark current descriptor as used/skipped */
859 vmxnet3_inc_rx_consumption_counter(s
, RXQ_IDX
, RX_HEAD_BODY_RING
);
861 /* If this is what we are looking for - return */
862 if (descr_buf
->btype
== VMXNET3_RXD_BTYPE_HEAD
) {
863 *ridx
= RX_HEAD_BODY_RING
;
870 vmxnet3_get_next_body_rx_descr(VMXNET3State
*s
,
871 struct Vmxnet3_RxDesc
*d
,
875 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_HEAD_BODY_RING
, d
, didx
);
877 /* Try to find corresponding descriptor in head/body ring */
878 if (d
->gen
== vmxnet3_get_rx_ring_gen(s
, RXQ_IDX
, RX_HEAD_BODY_RING
)) {
879 /* Only read after generation field verification */
881 /* Re-read to be sure we got the latest version */
882 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_HEAD_BODY_RING
, d
, didx
);
883 if (d
->btype
== VMXNET3_RXD_BTYPE_BODY
) {
884 vmxnet3_inc_rx_consumption_counter(s
, RXQ_IDX
, RX_HEAD_BODY_RING
);
885 *ridx
= RX_HEAD_BODY_RING
;
891 * If there is no free descriptors on head/body ring or next free
892 * descriptor is a head descriptor switch to body only ring
894 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_BODY_ONLY_RING
, d
, didx
);
896 /* If no more free descriptors - return */
897 if (d
->gen
== vmxnet3_get_rx_ring_gen(s
, RXQ_IDX
, RX_BODY_ONLY_RING
)) {
898 /* Only read after generation field verification */
900 /* Re-read to be sure we got the latest version */
901 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_BODY_ONLY_RING
, d
, didx
);
902 assert(d
->btype
== VMXNET3_RXD_BTYPE_BODY
);
903 *ridx
= RX_BODY_ONLY_RING
;
904 vmxnet3_inc_rx_consumption_counter(s
, RXQ_IDX
, RX_BODY_ONLY_RING
);
912 vmxnet3_get_next_rx_descr(VMXNET3State
*s
, bool is_head
,
913 struct Vmxnet3_RxDesc
*descr_buf
,
917 if (is_head
|| !s
->rx_packets_compound
) {
918 return vmxnet3_get_next_head_rx_descr(s
, descr_buf
, descr_idx
, ridx
);
920 return vmxnet3_get_next_body_rx_descr(s
, descr_buf
, descr_idx
, ridx
);
924 /* In case packet was csum offloaded (either NEEDS_CSUM or DATA_VALID),
925 * the implementation always passes an RxCompDesc with a "Checksum
926 * calculated and found correct" to the OS (cnc=0 and tuc=1, see
927 * vmxnet3_rx_update_descr). This emulates the observed ESXi behavior.
929 * Therefore, if packet has the NEEDS_CSUM set, we must calculate
930 * and place a fully computed checksum into the tcp/udp header.
931 * Otherwise, the OS driver will receive a checksum-correct indication
932 * (CHECKSUM_UNNECESSARY), but with the actual tcp/udp checksum field
933 * having just the pseudo header csum value.
935 * While this is not a problem if packet is destined for local delivery,
936 * in the case the host OS performs forwarding, it will forward an
937 * incorrectly checksummed packet.
939 static void vmxnet3_rx_need_csum_calculate(struct NetRxPkt
*pkt
,
940 const void *pkt_data
,
943 struct virtio_net_hdr
*vhdr
;
944 bool isip4
, isip6
, istcp
, isudp
;
948 if (!net_rx_pkt_has_virt_hdr(pkt
)) {
952 vhdr
= net_rx_pkt_get_vhdr(pkt
);
953 if (!VMXNET_FLAG_IS_SET(vhdr
->flags
, VIRTIO_NET_HDR_F_NEEDS_CSUM
)) {
957 net_rx_pkt_get_protocols(pkt
, &isip4
, &isip6
, &isudp
, &istcp
);
958 if (!(isip4
|| isip6
) || !(istcp
|| isudp
)) {
962 vmxnet3_dump_virt_hdr(vhdr
);
964 /* Validate packet len: csum_start + scum_offset + length of csum field */
965 if (pkt_len
< (vhdr
->csum_start
+ vhdr
->csum_offset
+ 2)) {
966 VMW_PKPRN("packet len:%zu < csum_start(%d) + csum_offset(%d) + 2, "
967 "cannot calculate checksum",
968 pkt_len
, vhdr
->csum_start
, vhdr
->csum_offset
);
972 data
= (uint8_t *)pkt_data
+ vhdr
->csum_start
;
973 len
= pkt_len
- vhdr
->csum_start
;
974 /* Put the checksum obtained into the packet */
975 stw_be_p(data
+ vhdr
->csum_offset
,
976 net_checksum_finish_nozero(net_checksum_add(len
, data
)));
978 vhdr
->flags
&= ~VIRTIO_NET_HDR_F_NEEDS_CSUM
;
979 vhdr
->flags
|= VIRTIO_NET_HDR_F_DATA_VALID
;
982 static void vmxnet3_rx_update_descr(struct NetRxPkt
*pkt
,
983 struct Vmxnet3_RxCompDesc
*rxcd
)
986 bool isip4
, isip6
, istcp
, isudp
;
987 struct virtio_net_hdr
*vhdr
;
988 uint8_t offload_type
;
990 if (net_rx_pkt_is_vlan_stripped(pkt
)) {
992 rxcd
->tci
= net_rx_pkt_get_vlan_tag(pkt
);
995 if (!net_rx_pkt_has_virt_hdr(pkt
)) {
999 vhdr
= net_rx_pkt_get_vhdr(pkt
);
1001 * Checksum is valid when lower level tell so or when lower level
1002 * requires checksum offload telling that packet produced/bridged
1003 * locally and did travel over network after last checksum calculation
1006 csum_ok
= VMXNET_FLAG_IS_SET(vhdr
->flags
, VIRTIO_NET_HDR_F_DATA_VALID
) ||
1007 VMXNET_FLAG_IS_SET(vhdr
->flags
, VIRTIO_NET_HDR_F_NEEDS_CSUM
);
1009 offload_type
= vhdr
->gso_type
& ~VIRTIO_NET_HDR_GSO_ECN
;
1010 is_gso
= (offload_type
!= VIRTIO_NET_HDR_GSO_NONE
) ? 1 : 0;
1012 if (!csum_ok
&& !is_gso
) {
1016 net_rx_pkt_get_protocols(pkt
, &isip4
, &isip6
, &isudp
, &istcp
);
1017 if ((!istcp
&& !isudp
) || (!isip4
&& !isip6
)) {
1022 rxcd
->v4
= isip4
? 1 : 0;
1023 rxcd
->v6
= isip6
? 1 : 0;
1024 rxcd
->tcp
= istcp
? 1 : 0;
1025 rxcd
->udp
= isudp
? 1 : 0;
1026 rxcd
->fcs
= rxcd
->tuc
= rxcd
->ipc
= 1;
1035 vmxnet3_pci_dma_writev(PCIDevice
*pci_dev
,
1036 const struct iovec
*iov
,
1037 size_t start_iov_off
,
1039 size_t bytes_to_copy
)
1041 size_t curr_off
= 0;
1044 while (bytes_to_copy
) {
1045 if (start_iov_off
< (curr_off
+ iov
->iov_len
)) {
1047 MIN((curr_off
+ iov
->iov_len
) - start_iov_off
, bytes_to_copy
);
1049 pci_dma_write(pci_dev
, target_addr
+ copied
,
1050 iov
->iov_base
+ start_iov_off
- curr_off
,
1053 copied
+= chunk_len
;
1054 start_iov_off
+= chunk_len
;
1055 curr_off
= start_iov_off
;
1056 bytes_to_copy
-= chunk_len
;
1058 curr_off
+= iov
->iov_len
;
1065 vmxnet3_indicate_packet(VMXNET3State
*s
)
1067 struct Vmxnet3_RxDesc rxd
;
1068 PCIDevice
*d
= PCI_DEVICE(s
);
1069 bool is_head
= true;
1071 uint32_t rx_ridx
= 0;
1073 struct Vmxnet3_RxCompDesc rxcd
;
1074 uint32_t new_rxcd_gen
= VMXNET3_INIT_GEN
;
1075 hwaddr new_rxcd_pa
= 0;
1076 hwaddr ready_rxcd_pa
= 0;
1077 struct iovec
*data
= net_rx_pkt_get_iovec(s
->rx_pkt
);
1078 size_t bytes_copied
= 0;
1079 size_t bytes_left
= net_rx_pkt_get_total_len(s
->rx_pkt
);
1080 uint16_t num_frags
= 0;
1083 net_rx_pkt_dump(s
->rx_pkt
);
1085 while (bytes_left
> 0) {
1087 /* cannot add more frags to packet */
1088 if (num_frags
== s
->max_rx_frags
) {
1092 new_rxcd_pa
= vmxnet3_pop_rxc_descr(s
, RXQ_IDX
, &new_rxcd_gen
);
1097 if (!vmxnet3_get_next_rx_descr(s
, is_head
, &rxd
, &rxd_idx
, &rx_ridx
)) {
1101 chunk_size
= MIN(bytes_left
, rxd
.len
);
1102 vmxnet3_pci_dma_writev(d
, data
, bytes_copied
,
1103 le64_to_cpu(rxd
.addr
), chunk_size
);
1104 bytes_copied
+= chunk_size
;
1105 bytes_left
-= chunk_size
;
1107 vmxnet3_dump_rx_descr(&rxd
);
1109 if (ready_rxcd_pa
!= 0) {
1110 pci_dma_write(d
, ready_rxcd_pa
, &rxcd
, sizeof(rxcd
));
1113 memset(&rxcd
, 0, sizeof(struct Vmxnet3_RxCompDesc
));
1114 rxcd
.rxdIdx
= rxd_idx
;
1115 rxcd
.len
= chunk_size
;
1117 rxcd
.gen
= new_rxcd_gen
;
1118 rxcd
.rqID
= RXQ_IDX
+ rx_ridx
* s
->rxq_num
;
1120 if (bytes_left
== 0) {
1121 vmxnet3_rx_update_descr(s
->rx_pkt
, &rxcd
);
1124 VMW_RIPRN("RX Completion descriptor: rxRing: %lu rxIdx %lu len %lu "
1125 "sop %d csum_correct %lu",
1126 (unsigned long) rx_ridx
,
1127 (unsigned long) rxcd
.rxdIdx
,
1128 (unsigned long) rxcd
.len
,
1130 (unsigned long) rxcd
.tuc
);
1133 ready_rxcd_pa
= new_rxcd_pa
;
1138 if (ready_rxcd_pa
!= 0) {
1140 rxcd
.err
= (bytes_left
!= 0);
1142 pci_dma_write(d
, ready_rxcd_pa
, &rxcd
, sizeof(rxcd
));
1144 /* Flush RX descriptor changes */
1148 if (new_rxcd_pa
!= 0) {
1149 vmxnet3_revert_rxc_descr(s
, RXQ_IDX
);
1152 vmxnet3_trigger_interrupt(s
, s
->rxq_descr
[RXQ_IDX
].intr_idx
);
1154 if (bytes_left
== 0) {
1155 vmxnet3_on_rx_done_update_stats(s
, RXQ_IDX
, VMXNET3_PKT_STATUS_OK
);
1157 } else if (num_frags
== s
->max_rx_frags
) {
1158 vmxnet3_on_rx_done_update_stats(s
, RXQ_IDX
, VMXNET3_PKT_STATUS_ERROR
);
1161 vmxnet3_on_rx_done_update_stats(s
, RXQ_IDX
,
1162 VMXNET3_PKT_STATUS_OUT_OF_BUF
);
1168 vmxnet3_io_bar0_write(void *opaque
, hwaddr addr
,
1169 uint64_t val
, unsigned size
)
1171 VMXNET3State
*s
= opaque
;
1173 if (!s
->device_active
) {
1177 if (VMW_IS_MULTIREG_ADDR(addr
, VMXNET3_REG_TXPROD
,
1178 VMXNET3_DEVICE_MAX_TX_QUEUES
, VMXNET3_REG_ALIGN
)) {
1180 VMW_MULTIREG_IDX_BY_ADDR(addr
, VMXNET3_REG_TXPROD
,
1182 assert(tx_queue_idx
<= s
->txq_num
);
1183 vmxnet3_process_tx_queue(s
, tx_queue_idx
);
1187 if (VMW_IS_MULTIREG_ADDR(addr
, VMXNET3_REG_IMR
,
1188 VMXNET3_MAX_INTRS
, VMXNET3_REG_ALIGN
)) {
1189 int l
= VMW_MULTIREG_IDX_BY_ADDR(addr
, VMXNET3_REG_IMR
,
1192 VMW_CBPRN("Interrupt mask for line %d written: 0x%" PRIx64
, l
, val
);
1194 vmxnet3_on_interrupt_mask_changed(s
, l
, val
);
1198 if (VMW_IS_MULTIREG_ADDR(addr
, VMXNET3_REG_RXPROD
,
1199 VMXNET3_DEVICE_MAX_RX_QUEUES
, VMXNET3_REG_ALIGN
) ||
1200 VMW_IS_MULTIREG_ADDR(addr
, VMXNET3_REG_RXPROD2
,
1201 VMXNET3_DEVICE_MAX_RX_QUEUES
, VMXNET3_REG_ALIGN
)) {
1205 VMW_WRPRN("BAR0 unknown write [%" PRIx64
"] = %" PRIx64
", size %d",
1206 (uint64_t) addr
, val
, size
);
1210 vmxnet3_io_bar0_read(void *opaque
, hwaddr addr
, unsigned size
)
1212 VMXNET3State
*s
= opaque
;
1214 if (VMW_IS_MULTIREG_ADDR(addr
, VMXNET3_REG_IMR
,
1215 VMXNET3_MAX_INTRS
, VMXNET3_REG_ALIGN
)) {
1216 int l
= VMW_MULTIREG_IDX_BY_ADDR(addr
, VMXNET3_REG_IMR
,
1218 return s
->interrupt_states
[l
].is_masked
;
1221 VMW_CBPRN("BAR0 unknown read [%" PRIx64
"], size %d", addr
, size
);
1225 static void vmxnet3_reset_interrupt_states(VMXNET3State
*s
)
1228 for (i
= 0; i
< ARRAY_SIZE(s
->interrupt_states
); i
++) {
1229 s
->interrupt_states
[i
].is_asserted
= false;
1230 s
->interrupt_states
[i
].is_pending
= false;
1231 s
->interrupt_states
[i
].is_masked
= true;
1235 static void vmxnet3_reset_mac(VMXNET3State
*s
)
1237 memcpy(&s
->conf
.macaddr
.a
, &s
->perm_mac
.a
, sizeof(s
->perm_mac
.a
));
1238 VMW_CFPRN("MAC address set to: " MAC_FMT
, MAC_ARG(s
->conf
.macaddr
.a
));
1241 static void vmxnet3_deactivate_device(VMXNET3State
*s
)
1243 if (s
->device_active
) {
1244 VMW_CBPRN("Deactivating vmxnet3...");
1245 net_tx_pkt_reset(s
->tx_pkt
);
1246 net_tx_pkt_uninit(s
->tx_pkt
);
1247 net_rx_pkt_uninit(s
->rx_pkt
);
1248 s
->device_active
= false;
1252 static void vmxnet3_reset(VMXNET3State
*s
)
1254 VMW_CBPRN("Resetting vmxnet3...");
1256 vmxnet3_deactivate_device(s
);
1257 vmxnet3_reset_interrupt_states(s
);
1260 s
->skip_current_tx_pkt
= false;
1263 static void vmxnet3_update_rx_mode(VMXNET3State
*s
)
1265 PCIDevice
*d
= PCI_DEVICE(s
);
1267 s
->rx_mode
= VMXNET3_READ_DRV_SHARED32(d
, s
->drv_shmem
,
1268 devRead
.rxFilterConf
.rxMode
);
1269 VMW_CFPRN("RX mode: 0x%08X", s
->rx_mode
);
1272 static void vmxnet3_update_vlan_filters(VMXNET3State
*s
)
1275 PCIDevice
*d
= PCI_DEVICE(s
);
1277 /* Copy configuration from shared memory */
1278 VMXNET3_READ_DRV_SHARED(d
, s
->drv_shmem
,
1279 devRead
.rxFilterConf
.vfTable
,
1281 sizeof(s
->vlan_table
));
1283 /* Invert byte order when needed */
1284 for (i
= 0; i
< ARRAY_SIZE(s
->vlan_table
); i
++) {
1285 s
->vlan_table
[i
] = le32_to_cpu(s
->vlan_table
[i
]);
1288 /* Dump configuration for debugging purposes */
1289 VMW_CFPRN("Configured VLANs:");
1290 for (i
= 0; i
< sizeof(s
->vlan_table
) * 8; i
++) {
1291 if (VMXNET3_VFTABLE_ENTRY_IS_SET(s
->vlan_table
, i
)) {
1292 VMW_CFPRN("\tVLAN %d is present", i
);
1297 static void vmxnet3_update_mcast_filters(VMXNET3State
*s
)
1299 PCIDevice
*d
= PCI_DEVICE(s
);
1301 uint16_t list_bytes
=
1302 VMXNET3_READ_DRV_SHARED16(d
, s
->drv_shmem
,
1303 devRead
.rxFilterConf
.mfTableLen
);
1305 s
->mcast_list_len
= list_bytes
/ sizeof(s
->mcast_list
[0]);
1307 s
->mcast_list
= g_realloc(s
->mcast_list
, list_bytes
);
1308 if (!s
->mcast_list
) {
1309 if (s
->mcast_list_len
== 0) {
1310 VMW_CFPRN("Current multicast list is empty");
1312 VMW_ERPRN("Failed to allocate multicast list of %d elements",
1315 s
->mcast_list_len
= 0;
1318 hwaddr mcast_list_pa
=
1319 VMXNET3_READ_DRV_SHARED64(d
, s
->drv_shmem
,
1320 devRead
.rxFilterConf
.mfTablePA
);
1322 pci_dma_read(d
, mcast_list_pa
, s
->mcast_list
, list_bytes
);
1324 VMW_CFPRN("Current multicast list len is %d:", s
->mcast_list_len
);
1325 for (i
= 0; i
< s
->mcast_list_len
; i
++) {
1326 VMW_CFPRN("\t" MAC_FMT
, MAC_ARG(s
->mcast_list
[i
].a
));
1331 static void vmxnet3_setup_rx_filtering(VMXNET3State
*s
)
1333 vmxnet3_update_rx_mode(s
);
1334 vmxnet3_update_vlan_filters(s
);
1335 vmxnet3_update_mcast_filters(s
);
1338 static uint32_t vmxnet3_get_interrupt_config(VMXNET3State
*s
)
1340 uint32_t interrupt_mode
= VMXNET3_IT_AUTO
| (VMXNET3_IMM_AUTO
<< 2);
1341 VMW_CFPRN("Interrupt config is 0x%X", interrupt_mode
);
1342 return interrupt_mode
;
1345 static void vmxnet3_fill_stats(VMXNET3State
*s
)
1348 PCIDevice
*d
= PCI_DEVICE(s
);
1350 if (!s
->device_active
)
1353 for (i
= 0; i
< s
->txq_num
; i
++) {
1355 s
->txq_descr
[i
].tx_stats_pa
,
1356 &s
->txq_descr
[i
].txq_stats
,
1357 sizeof(s
->txq_descr
[i
].txq_stats
));
1360 for (i
= 0; i
< s
->rxq_num
; i
++) {
1362 s
->rxq_descr
[i
].rx_stats_pa
,
1363 &s
->rxq_descr
[i
].rxq_stats
,
1364 sizeof(s
->rxq_descr
[i
].rxq_stats
));
1368 static void vmxnet3_adjust_by_guest_type(VMXNET3State
*s
)
1370 struct Vmxnet3_GOSInfo gos
;
1371 PCIDevice
*d
= PCI_DEVICE(s
);
1373 VMXNET3_READ_DRV_SHARED(d
, s
->drv_shmem
, devRead
.misc
.driverInfo
.gos
,
1375 s
->rx_packets_compound
=
1376 (gos
.gosType
== VMXNET3_GOS_TYPE_WIN
) ? false : true;
1378 VMW_CFPRN("Guest type specifics: RXCOMPOUND: %d", s
->rx_packets_compound
);
1382 vmxnet3_dump_conf_descr(const char *name
,
1383 struct Vmxnet3_VariableLenConfDesc
*pm_descr
)
1385 VMW_CFPRN("%s descriptor dump: Version %u, Length %u",
1386 name
, pm_descr
->confVer
, pm_descr
->confLen
);
1390 static void vmxnet3_update_pm_state(VMXNET3State
*s
)
1392 struct Vmxnet3_VariableLenConfDesc pm_descr
;
1393 PCIDevice
*d
= PCI_DEVICE(s
);
1396 VMXNET3_READ_DRV_SHARED32(d
, s
->drv_shmem
, devRead
.pmConfDesc
.confLen
);
1398 VMXNET3_READ_DRV_SHARED32(d
, s
->drv_shmem
, devRead
.pmConfDesc
.confVer
);
1400 VMXNET3_READ_DRV_SHARED64(d
, s
->drv_shmem
, devRead
.pmConfDesc
.confPA
);
1402 vmxnet3_dump_conf_descr("PM State", &pm_descr
);
1405 static void vmxnet3_update_features(VMXNET3State
*s
)
1407 uint32_t guest_features
;
1408 int rxcso_supported
;
1409 PCIDevice
*d
= PCI_DEVICE(s
);
1411 guest_features
= VMXNET3_READ_DRV_SHARED32(d
, s
->drv_shmem
,
1412 devRead
.misc
.uptFeatures
);
1414 rxcso_supported
= VMXNET_FLAG_IS_SET(guest_features
, UPT1_F_RXCSUM
);
1415 s
->rx_vlan_stripping
= VMXNET_FLAG_IS_SET(guest_features
, UPT1_F_RXVLAN
);
1416 s
->lro_supported
= VMXNET_FLAG_IS_SET(guest_features
, UPT1_F_LRO
);
1418 VMW_CFPRN("Features configuration: LRO: %d, RXCSUM: %d, VLANSTRIP: %d",
1419 s
->lro_supported
, rxcso_supported
,
1420 s
->rx_vlan_stripping
);
1421 if (s
->peer_has_vhdr
) {
1422 qemu_set_offload(qemu_get_queue(s
->nic
)->peer
,
1431 static bool vmxnet3_verify_intx(VMXNET3State
*s
, int intx
)
1433 return s
->msix_used
|| msi_enabled(PCI_DEVICE(s
))
1434 || intx
== pci_get_byte(s
->parent_obj
.config
+ PCI_INTERRUPT_PIN
) - 1;
1437 static void vmxnet3_validate_interrupt_idx(bool is_msix
, int idx
)
1439 int max_ints
= is_msix
? VMXNET3_MAX_INTRS
: VMXNET3_MAX_NMSIX_INTRS
;
1440 if (idx
>= max_ints
) {
1441 hw_error("Bad interrupt index: %d\n", idx
);
1445 static void vmxnet3_validate_interrupts(VMXNET3State
*s
)
1449 VMW_CFPRN("Verifying event interrupt index (%d)", s
->event_int_idx
);
1450 vmxnet3_validate_interrupt_idx(s
->msix_used
, s
->event_int_idx
);
1452 for (i
= 0; i
< s
->txq_num
; i
++) {
1453 int idx
= s
->txq_descr
[i
].intr_idx
;
1454 VMW_CFPRN("Verifying TX queue %d interrupt index (%d)", i
, idx
);
1455 vmxnet3_validate_interrupt_idx(s
->msix_used
, idx
);
1458 for (i
= 0; i
< s
->rxq_num
; i
++) {
1459 int idx
= s
->rxq_descr
[i
].intr_idx
;
1460 VMW_CFPRN("Verifying RX queue %d interrupt index (%d)", i
, idx
);
1461 vmxnet3_validate_interrupt_idx(s
->msix_used
, idx
);
1465 static void vmxnet3_validate_queues(VMXNET3State
*s
)
1468 * txq_num and rxq_num are total number of queues
1469 * configured by guest. These numbers must not
1470 * exceed corresponding maximal values.
1473 if (s
->txq_num
> VMXNET3_DEVICE_MAX_TX_QUEUES
) {
1474 hw_error("Bad TX queues number: %d\n", s
->txq_num
);
1477 if (s
->rxq_num
> VMXNET3_DEVICE_MAX_RX_QUEUES
) {
1478 hw_error("Bad RX queues number: %d\n", s
->rxq_num
);
1482 static void vmxnet3_activate_device(VMXNET3State
*s
)
1485 static const uint32_t VMXNET3_DEF_TX_THRESHOLD
= 1;
1486 PCIDevice
*d
= PCI_DEVICE(s
);
1487 hwaddr qdescr_table_pa
;
1491 /* Verify configuration consistency */
1492 if (!vmxnet3_verify_driver_magic(d
, s
->drv_shmem
)) {
1493 VMW_ERPRN("Device configuration received from driver is invalid");
1497 /* Verify if device is active */
1498 if (s
->device_active
) {
1499 VMW_CFPRN("Vmxnet3 device is active");
1503 vmxnet3_adjust_by_guest_type(s
);
1504 vmxnet3_update_features(s
);
1505 vmxnet3_update_pm_state(s
);
1506 vmxnet3_setup_rx_filtering(s
);
1507 /* Cache fields from shared memory */
1508 s
->mtu
= VMXNET3_READ_DRV_SHARED32(d
, s
->drv_shmem
, devRead
.misc
.mtu
);
1509 VMW_CFPRN("MTU is %u", s
->mtu
);
1512 VMXNET3_READ_DRV_SHARED16(d
, s
->drv_shmem
, devRead
.misc
.maxNumRxSG
);
1514 if (s
->max_rx_frags
== 0) {
1515 s
->max_rx_frags
= 1;
1518 VMW_CFPRN("Max RX fragments is %u", s
->max_rx_frags
);
1521 VMXNET3_READ_DRV_SHARED8(d
, s
->drv_shmem
, devRead
.intrConf
.eventIntrIdx
);
1522 assert(vmxnet3_verify_intx(s
, s
->event_int_idx
));
1523 VMW_CFPRN("Events interrupt line is %u", s
->event_int_idx
);
1525 s
->auto_int_masking
=
1526 VMXNET3_READ_DRV_SHARED8(d
, s
->drv_shmem
, devRead
.intrConf
.autoMask
);
1527 VMW_CFPRN("Automatic interrupt masking is %d", (int)s
->auto_int_masking
);
1530 VMXNET3_READ_DRV_SHARED8(d
, s
->drv_shmem
, devRead
.misc
.numTxQueues
);
1532 VMXNET3_READ_DRV_SHARED8(d
, s
->drv_shmem
, devRead
.misc
.numRxQueues
);
1534 VMW_CFPRN("Number of TX/RX queues %u/%u", s
->txq_num
, s
->rxq_num
);
1535 vmxnet3_validate_queues(s
);
1538 VMXNET3_READ_DRV_SHARED64(d
, s
->drv_shmem
, devRead
.misc
.queueDescPA
);
1539 VMW_CFPRN("TX queues descriptors table is at 0x%" PRIx64
, qdescr_table_pa
);
1542 * Worst-case scenario is a packet that holds all TX rings space so
1543 * we calculate total size of all TX rings for max TX fragments number
1545 s
->max_tx_frags
= 0;
1548 for (i
= 0; i
< s
->txq_num
; i
++) {
1550 qdescr_table_pa
+ i
* sizeof(struct Vmxnet3_TxQueueDesc
);
1552 /* Read interrupt number for this TX queue */
1553 s
->txq_descr
[i
].intr_idx
=
1554 VMXNET3_READ_TX_QUEUE_DESCR8(d
, qdescr_pa
, conf
.intrIdx
);
1555 assert(vmxnet3_verify_intx(s
, s
->txq_descr
[i
].intr_idx
));
1557 VMW_CFPRN("TX Queue %d interrupt: %d", i
, s
->txq_descr
[i
].intr_idx
);
1559 /* Read rings memory locations for TX queues */
1560 pa
= VMXNET3_READ_TX_QUEUE_DESCR64(d
, qdescr_pa
, conf
.txRingBasePA
);
1561 size
= VMXNET3_READ_TX_QUEUE_DESCR32(d
, qdescr_pa
, conf
.txRingSize
);
1563 vmxnet3_ring_init(d
, &s
->txq_descr
[i
].tx_ring
, pa
, size
,
1564 sizeof(struct Vmxnet3_TxDesc
), false);
1565 VMXNET3_RING_DUMP(VMW_CFPRN
, "TX", i
, &s
->txq_descr
[i
].tx_ring
);
1567 s
->max_tx_frags
+= size
;
1570 pa
= VMXNET3_READ_TX_QUEUE_DESCR64(d
, qdescr_pa
, conf
.compRingBasePA
);
1571 size
= VMXNET3_READ_TX_QUEUE_DESCR32(d
, qdescr_pa
, conf
.compRingSize
);
1572 vmxnet3_ring_init(d
, &s
->txq_descr
[i
].comp_ring
, pa
, size
,
1573 sizeof(struct Vmxnet3_TxCompDesc
), true);
1574 VMXNET3_RING_DUMP(VMW_CFPRN
, "TXC", i
, &s
->txq_descr
[i
].comp_ring
);
1576 s
->txq_descr
[i
].tx_stats_pa
=
1577 qdescr_pa
+ offsetof(struct Vmxnet3_TxQueueDesc
, stats
);
1579 memset(&s
->txq_descr
[i
].txq_stats
, 0,
1580 sizeof(s
->txq_descr
[i
].txq_stats
));
1582 /* Fill device-managed parameters for queues */
1583 VMXNET3_WRITE_TX_QUEUE_DESCR32(d
, qdescr_pa
,
1585 VMXNET3_DEF_TX_THRESHOLD
);
1588 /* Preallocate TX packet wrapper */
1589 VMW_CFPRN("Max TX fragments is %u", s
->max_tx_frags
);
1590 net_tx_pkt_init(&s
->tx_pkt
, PCI_DEVICE(s
),
1591 s
->max_tx_frags
, s
->peer_has_vhdr
);
1592 net_rx_pkt_init(&s
->rx_pkt
, s
->peer_has_vhdr
);
1594 /* Read rings memory locations for RX queues */
1595 for (i
= 0; i
< s
->rxq_num
; i
++) {
1598 qdescr_table_pa
+ s
->txq_num
* sizeof(struct Vmxnet3_TxQueueDesc
) +
1599 i
* sizeof(struct Vmxnet3_RxQueueDesc
);
1601 /* Read interrupt number for this RX queue */
1602 s
->rxq_descr
[i
].intr_idx
=
1603 VMXNET3_READ_TX_QUEUE_DESCR8(d
, qd_pa
, conf
.intrIdx
);
1604 assert(vmxnet3_verify_intx(s
, s
->rxq_descr
[i
].intr_idx
));
1606 VMW_CFPRN("RX Queue %d interrupt: %d", i
, s
->rxq_descr
[i
].intr_idx
);
1608 /* Read rings memory locations */
1609 for (j
= 0; j
< VMXNET3_RX_RINGS_PER_QUEUE
; j
++) {
1611 pa
= VMXNET3_READ_RX_QUEUE_DESCR64(d
, qd_pa
, conf
.rxRingBasePA
[j
]);
1612 size
= VMXNET3_READ_RX_QUEUE_DESCR32(d
, qd_pa
, conf
.rxRingSize
[j
]);
1613 vmxnet3_ring_init(d
, &s
->rxq_descr
[i
].rx_ring
[j
], pa
, size
,
1614 sizeof(struct Vmxnet3_RxDesc
), false);
1615 VMW_CFPRN("RX queue %d:%d: Base: %" PRIx64
", Size: %d",
1620 pa
= VMXNET3_READ_RX_QUEUE_DESCR64(d
, qd_pa
, conf
.compRingBasePA
);
1621 size
= VMXNET3_READ_RX_QUEUE_DESCR32(d
, qd_pa
, conf
.compRingSize
);
1622 vmxnet3_ring_init(d
, &s
->rxq_descr
[i
].comp_ring
, pa
, size
,
1623 sizeof(struct Vmxnet3_RxCompDesc
), true);
1624 VMW_CFPRN("RXC queue %d: Base: %" PRIx64
", Size: %d", i
, pa
, size
);
1626 s
->rxq_descr
[i
].rx_stats_pa
=
1627 qd_pa
+ offsetof(struct Vmxnet3_RxQueueDesc
, stats
);
1628 memset(&s
->rxq_descr
[i
].rxq_stats
, 0,
1629 sizeof(s
->rxq_descr
[i
].rxq_stats
));
1632 vmxnet3_validate_interrupts(s
);
1634 /* Make sure everything is in place before device activation */
1637 vmxnet3_reset_mac(s
);
1639 s
->device_active
= true;
1642 static void vmxnet3_handle_command(VMXNET3State
*s
, uint64_t cmd
)
1644 s
->last_command
= cmd
;
1647 case VMXNET3_CMD_GET_PERM_MAC_HI
:
1648 VMW_CBPRN("Set: Get upper part of permanent MAC");
1651 case VMXNET3_CMD_GET_PERM_MAC_LO
:
1652 VMW_CBPRN("Set: Get lower part of permanent MAC");
1655 case VMXNET3_CMD_GET_STATS
:
1656 VMW_CBPRN("Set: Get device statistics");
1657 vmxnet3_fill_stats(s
);
1660 case VMXNET3_CMD_ACTIVATE_DEV
:
1661 VMW_CBPRN("Set: Activating vmxnet3 device");
1662 vmxnet3_activate_device(s
);
1665 case VMXNET3_CMD_UPDATE_RX_MODE
:
1666 VMW_CBPRN("Set: Update rx mode");
1667 vmxnet3_update_rx_mode(s
);
1670 case VMXNET3_CMD_UPDATE_VLAN_FILTERS
:
1671 VMW_CBPRN("Set: Update VLAN filters");
1672 vmxnet3_update_vlan_filters(s
);
1675 case VMXNET3_CMD_UPDATE_MAC_FILTERS
:
1676 VMW_CBPRN("Set: Update MAC filters");
1677 vmxnet3_update_mcast_filters(s
);
1680 case VMXNET3_CMD_UPDATE_FEATURE
:
1681 VMW_CBPRN("Set: Update features");
1682 vmxnet3_update_features(s
);
1685 case VMXNET3_CMD_UPDATE_PMCFG
:
1686 VMW_CBPRN("Set: Update power management config");
1687 vmxnet3_update_pm_state(s
);
1690 case VMXNET3_CMD_GET_LINK
:
1691 VMW_CBPRN("Set: Get link");
1694 case VMXNET3_CMD_RESET_DEV
:
1695 VMW_CBPRN("Set: Reset device");
1699 case VMXNET3_CMD_QUIESCE_DEV
:
1700 VMW_CBPRN("Set: VMXNET3_CMD_QUIESCE_DEV - deactivate the device");
1701 vmxnet3_deactivate_device(s
);
1704 case VMXNET3_CMD_GET_CONF_INTR
:
1705 VMW_CBPRN("Set: VMXNET3_CMD_GET_CONF_INTR - interrupt configuration");
1708 case VMXNET3_CMD_GET_ADAPTIVE_RING_INFO
:
1709 VMW_CBPRN("Set: VMXNET3_CMD_GET_ADAPTIVE_RING_INFO - "
1710 "adaptive ring info flags");
1713 case VMXNET3_CMD_GET_DID_LO
:
1714 VMW_CBPRN("Set: Get lower part of device ID");
1717 case VMXNET3_CMD_GET_DID_HI
:
1718 VMW_CBPRN("Set: Get upper part of device ID");
1721 case VMXNET3_CMD_GET_DEV_EXTRA_INFO
:
1722 VMW_CBPRN("Set: Get device extra info");
1726 VMW_CBPRN("Received unknown command: %" PRIx64
, cmd
);
1731 static uint64_t vmxnet3_get_command_status(VMXNET3State
*s
)
1735 switch (s
->last_command
) {
1736 case VMXNET3_CMD_ACTIVATE_DEV
:
1737 ret
= (s
->device_active
) ? 0 : 1;
1738 VMW_CFPRN("Device active: %" PRIx64
, ret
);
1741 case VMXNET3_CMD_RESET_DEV
:
1742 case VMXNET3_CMD_QUIESCE_DEV
:
1743 case VMXNET3_CMD_GET_QUEUE_STATUS
:
1744 case VMXNET3_CMD_GET_DEV_EXTRA_INFO
:
1748 case VMXNET3_CMD_GET_LINK
:
1749 ret
= s
->link_status_and_speed
;
1750 VMW_CFPRN("Link and speed: %" PRIx64
, ret
);
1753 case VMXNET3_CMD_GET_PERM_MAC_LO
:
1754 ret
= vmxnet3_get_mac_low(&s
->perm_mac
);
1757 case VMXNET3_CMD_GET_PERM_MAC_HI
:
1758 ret
= vmxnet3_get_mac_high(&s
->perm_mac
);
1761 case VMXNET3_CMD_GET_CONF_INTR
:
1762 ret
= vmxnet3_get_interrupt_config(s
);
1765 case VMXNET3_CMD_GET_ADAPTIVE_RING_INFO
:
1766 ret
= VMXNET3_DISABLE_ADAPTIVE_RING
;
1769 case VMXNET3_CMD_GET_DID_LO
:
1770 ret
= PCI_DEVICE_ID_VMWARE_VMXNET3
;
1773 case VMXNET3_CMD_GET_DID_HI
:
1774 ret
= VMXNET3_DEVICE_REVISION
;
1778 VMW_WRPRN("Received request for unknown command: %x", s
->last_command
);
1786 static void vmxnet3_set_events(VMXNET3State
*s
, uint32_t val
)
1789 PCIDevice
*d
= PCI_DEVICE(s
);
1791 VMW_CBPRN("Setting events: 0x%x", val
);
1792 events
= VMXNET3_READ_DRV_SHARED32(d
, s
->drv_shmem
, ecr
) | val
;
1793 VMXNET3_WRITE_DRV_SHARED32(d
, s
->drv_shmem
, ecr
, events
);
1796 static void vmxnet3_ack_events(VMXNET3State
*s
, uint32_t val
)
1798 PCIDevice
*d
= PCI_DEVICE(s
);
1801 VMW_CBPRN("Clearing events: 0x%x", val
);
1802 events
= VMXNET3_READ_DRV_SHARED32(d
, s
->drv_shmem
, ecr
) & ~val
;
1803 VMXNET3_WRITE_DRV_SHARED32(d
, s
->drv_shmem
, ecr
, events
);
1807 vmxnet3_io_bar1_write(void *opaque
,
1812 VMXNET3State
*s
= opaque
;
1815 /* Vmxnet3 Revision Report Selection */
1816 case VMXNET3_REG_VRRS
:
1817 VMW_CBPRN("Write BAR1 [VMXNET3_REG_VRRS] = %" PRIx64
", size %d",
1821 /* UPT Version Report Selection */
1822 case VMXNET3_REG_UVRS
:
1823 VMW_CBPRN("Write BAR1 [VMXNET3_REG_UVRS] = %" PRIx64
", size %d",
1827 /* Driver Shared Address Low */
1828 case VMXNET3_REG_DSAL
:
1829 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAL] = %" PRIx64
", size %d",
1832 * Guest driver will first write the low part of the shared
1833 * memory address. We save it to temp variable and set the
1834 * shared address only after we get the high part
1837 vmxnet3_deactivate_device(s
);
1839 s
->temp_shared_guest_driver_memory
= val
;
1843 /* Driver Shared Address High */
1844 case VMXNET3_REG_DSAH
:
1845 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAH] = %" PRIx64
", size %d",
1848 * Set the shared memory between guest driver and device.
1849 * We already should have low address part.
1851 s
->drv_shmem
= s
->temp_shared_guest_driver_memory
| (val
<< 32);
1855 case VMXNET3_REG_CMD
:
1856 VMW_CBPRN("Write BAR1 [VMXNET3_REG_CMD] = %" PRIx64
", size %d",
1858 vmxnet3_handle_command(s
, val
);
1861 /* MAC Address Low */
1862 case VMXNET3_REG_MACL
:
1863 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACL] = %" PRIx64
", size %d",
1868 /* MAC Address High */
1869 case VMXNET3_REG_MACH
:
1870 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACH] = %" PRIx64
", size %d",
1872 vmxnet3_set_variable_mac(s
, val
, s
->temp_mac
);
1875 /* Interrupt Cause Register */
1876 case VMXNET3_REG_ICR
:
1877 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ICR] = %" PRIx64
", size %d",
1879 g_assert_not_reached();
1882 /* Event Cause Register */
1883 case VMXNET3_REG_ECR
:
1884 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ECR] = %" PRIx64
", size %d",
1886 vmxnet3_ack_events(s
, val
);
1890 VMW_CBPRN("Unknown Write to BAR1 [%" PRIx64
"] = %" PRIx64
", size %d",
1897 vmxnet3_io_bar1_read(void *opaque
, hwaddr addr
, unsigned size
)
1899 VMXNET3State
*s
= opaque
;
1903 /* Vmxnet3 Revision Report Selection */
1904 case VMXNET3_REG_VRRS
:
1905 VMW_CBPRN("Read BAR1 [VMXNET3_REG_VRRS], size %d", size
);
1906 ret
= VMXNET3_DEVICE_REVISION
;
1909 /* UPT Version Report Selection */
1910 case VMXNET3_REG_UVRS
:
1911 VMW_CBPRN("Read BAR1 [VMXNET3_REG_UVRS], size %d", size
);
1912 ret
= VMXNET3_UPT_REVISION
;
1916 case VMXNET3_REG_CMD
:
1917 VMW_CBPRN("Read BAR1 [VMXNET3_REG_CMD], size %d", size
);
1918 ret
= vmxnet3_get_command_status(s
);
1921 /* MAC Address Low */
1922 case VMXNET3_REG_MACL
:
1923 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACL], size %d", size
);
1924 ret
= vmxnet3_get_mac_low(&s
->conf
.macaddr
);
1927 /* MAC Address High */
1928 case VMXNET3_REG_MACH
:
1929 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACH], size %d", size
);
1930 ret
= vmxnet3_get_mac_high(&s
->conf
.macaddr
);
1934 * Interrupt Cause Register
1935 * Used for legacy interrupts only so interrupt index always 0
1937 case VMXNET3_REG_ICR
:
1938 VMW_CBPRN("Read BAR1 [VMXNET3_REG_ICR], size %d", size
);
1939 if (vmxnet3_interrupt_asserted(s
, 0)) {
1940 vmxnet3_clear_interrupt(s
, 0);
1948 VMW_CBPRN("Unknow read BAR1[%" PRIx64
"], %d bytes", addr
, size
);
1956 vmxnet3_can_receive(NetClientState
*nc
)
1958 VMXNET3State
*s
= qemu_get_nic_opaque(nc
);
1959 return s
->device_active
&&
1960 VMXNET_FLAG_IS_SET(s
->link_status_and_speed
, VMXNET3_LINK_STATUS_UP
);
1964 vmxnet3_is_registered_vlan(VMXNET3State
*s
, const void *data
)
1966 uint16_t vlan_tag
= eth_get_pkt_tci(data
) & VLAN_VID_MASK
;
1967 if (IS_SPECIAL_VLAN_ID(vlan_tag
)) {
1971 return VMXNET3_VFTABLE_ENTRY_IS_SET(s
->vlan_table
, vlan_tag
);
1975 vmxnet3_is_allowed_mcast_group(VMXNET3State
*s
, const uint8_t *group_mac
)
1978 for (i
= 0; i
< s
->mcast_list_len
; i
++) {
1979 if (!memcmp(group_mac
, s
->mcast_list
[i
].a
, sizeof(s
->mcast_list
[i
]))) {
1987 vmxnet3_rx_filter_may_indicate(VMXNET3State
*s
, const void *data
,
1990 struct eth_header
*ehdr
= PKT_GET_ETH_HDR(data
);
1992 if (VMXNET_FLAG_IS_SET(s
->rx_mode
, VMXNET3_RXM_PROMISC
)) {
1996 if (!vmxnet3_is_registered_vlan(s
, data
)) {
2000 switch (net_rx_pkt_get_packet_type(s
->rx_pkt
)) {
2002 if (!VMXNET_FLAG_IS_SET(s
->rx_mode
, VMXNET3_RXM_UCAST
)) {
2005 if (memcmp(s
->conf
.macaddr
.a
, ehdr
->h_dest
, ETH_ALEN
)) {
2011 if (!VMXNET_FLAG_IS_SET(s
->rx_mode
, VMXNET3_RXM_BCAST
)) {
2017 if (VMXNET_FLAG_IS_SET(s
->rx_mode
, VMXNET3_RXM_ALL_MULTI
)) {
2020 if (!VMXNET_FLAG_IS_SET(s
->rx_mode
, VMXNET3_RXM_MCAST
)) {
2023 if (!vmxnet3_is_allowed_mcast_group(s
, ehdr
->h_dest
)) {
2029 g_assert_not_reached();
2036 vmxnet3_receive(NetClientState
*nc
, const uint8_t *buf
, size_t size
)
2038 VMXNET3State
*s
= qemu_get_nic_opaque(nc
);
2039 size_t bytes_indicated
;
2040 uint8_t min_buf
[MIN_BUF_SIZE
];
2042 if (!vmxnet3_can_receive(nc
)) {
2043 VMW_PKPRN("Cannot receive now");
2047 if (s
->peer_has_vhdr
) {
2048 net_rx_pkt_set_vhdr(s
->rx_pkt
, (struct virtio_net_hdr
*)buf
);
2049 buf
+= sizeof(struct virtio_net_hdr
);
2050 size
-= sizeof(struct virtio_net_hdr
);
2053 /* Pad to minimum Ethernet frame length */
2054 if (size
< sizeof(min_buf
)) {
2055 memcpy(min_buf
, buf
, size
);
2056 memset(&min_buf
[size
], 0, sizeof(min_buf
) - size
);
2058 size
= sizeof(min_buf
);
2061 net_rx_pkt_set_packet_type(s
->rx_pkt
,
2062 get_eth_packet_type(PKT_GET_ETH_HDR(buf
)));
2064 if (vmxnet3_rx_filter_may_indicate(s
, buf
, size
)) {
2065 net_rx_pkt_set_protocols(s
->rx_pkt
, buf
, size
);
2066 vmxnet3_rx_need_csum_calculate(s
->rx_pkt
, buf
, size
);
2067 net_rx_pkt_attach_data(s
->rx_pkt
, buf
, size
, s
->rx_vlan_stripping
);
2068 bytes_indicated
= vmxnet3_indicate_packet(s
) ? size
: -1;
2069 if (bytes_indicated
< size
) {
2070 VMW_PKPRN("RX: %zu of %zu bytes indicated", bytes_indicated
, size
);
2073 VMW_PKPRN("Packet dropped by RX filter");
2074 bytes_indicated
= size
;
2078 assert(bytes_indicated
!= 0);
2079 return bytes_indicated
;
2082 static void vmxnet3_set_link_status(NetClientState
*nc
)
2084 VMXNET3State
*s
= qemu_get_nic_opaque(nc
);
2086 if (nc
->link_down
) {
2087 s
->link_status_and_speed
&= ~VMXNET3_LINK_STATUS_UP
;
2089 s
->link_status_and_speed
|= VMXNET3_LINK_STATUS_UP
;
2092 vmxnet3_set_events(s
, VMXNET3_ECR_LINK
);
2093 vmxnet3_trigger_interrupt(s
, s
->event_int_idx
);
2096 static NetClientInfo net_vmxnet3_info
= {
2097 .type
= NET_CLIENT_DRIVER_NIC
,
2098 .size
= sizeof(NICState
),
2099 .receive
= vmxnet3_receive
,
2100 .link_status_changed
= vmxnet3_set_link_status
,
2103 static bool vmxnet3_peer_has_vnet_hdr(VMXNET3State
*s
)
2105 NetClientState
*nc
= qemu_get_queue(s
->nic
);
2107 if (qemu_has_vnet_hdr(nc
->peer
)) {
2114 static void vmxnet3_net_uninit(VMXNET3State
*s
)
2116 g_free(s
->mcast_list
);
2117 vmxnet3_deactivate_device(s
);
2118 qemu_del_nic(s
->nic
);
2121 static void vmxnet3_net_init(VMXNET3State
*s
)
2123 DeviceState
*d
= DEVICE(s
);
2125 VMW_CBPRN("vmxnet3_net_init called...");
2127 qemu_macaddr_default_if_unset(&s
->conf
.macaddr
);
2129 /* Windows guest will query the address that was set on init */
2130 memcpy(&s
->perm_mac
.a
, &s
->conf
.macaddr
.a
, sizeof(s
->perm_mac
.a
));
2132 s
->mcast_list
= NULL
;
2133 s
->mcast_list_len
= 0;
2135 s
->link_status_and_speed
= VMXNET3_LINK_SPEED
| VMXNET3_LINK_STATUS_UP
;
2137 VMW_CFPRN("Permanent MAC: " MAC_FMT
, MAC_ARG(s
->perm_mac
.a
));
2139 s
->nic
= qemu_new_nic(&net_vmxnet3_info
, &s
->conf
,
2140 object_get_typename(OBJECT(s
)),
2143 s
->peer_has_vhdr
= vmxnet3_peer_has_vnet_hdr(s
);
2145 s
->skip_current_tx_pkt
= false;
2148 s
->rx_vlan_stripping
= false;
2149 s
->lro_supported
= false;
2151 if (s
->peer_has_vhdr
) {
2152 qemu_set_vnet_hdr_len(qemu_get_queue(s
->nic
)->peer
,
2153 sizeof(struct virtio_net_hdr
));
2155 qemu_using_vnet_hdr(qemu_get_queue(s
->nic
)->peer
, 1);
2158 qemu_format_nic_info_str(qemu_get_queue(s
->nic
), s
->conf
.macaddr
.a
);
2162 vmxnet3_unuse_msix_vectors(VMXNET3State
*s
, int num_vectors
)
2164 PCIDevice
*d
= PCI_DEVICE(s
);
2166 for (i
= 0; i
< num_vectors
; i
++) {
2167 msix_vector_unuse(d
, i
);
2172 vmxnet3_use_msix_vectors(VMXNET3State
*s
, int num_vectors
)
2174 PCIDevice
*d
= PCI_DEVICE(s
);
2176 for (i
= 0; i
< num_vectors
; i
++) {
2177 int res
= msix_vector_use(d
, i
);
2179 VMW_WRPRN("Failed to use MSI-X vector %d, error %d", i
, res
);
2180 vmxnet3_unuse_msix_vectors(s
, i
);
2188 vmxnet3_init_msix(VMXNET3State
*s
)
2190 PCIDevice
*d
= PCI_DEVICE(s
);
2191 int res
= msix_init(d
, VMXNET3_MAX_INTRS
,
2193 VMXNET3_MSIX_BAR_IDX
, VMXNET3_OFF_MSIX_TABLE
,
2195 VMXNET3_MSIX_BAR_IDX
, VMXNET3_OFF_MSIX_PBA(s
),
2196 VMXNET3_MSIX_OFFSET(s
), NULL
);
2199 VMW_WRPRN("Failed to initialize MSI-X, error %d", res
);
2200 s
->msix_used
= false;
2202 if (!vmxnet3_use_msix_vectors(s
, VMXNET3_MAX_INTRS
)) {
2203 VMW_WRPRN("Failed to use MSI-X vectors, error %d", res
);
2204 msix_uninit(d
, &s
->msix_bar
, &s
->msix_bar
);
2205 s
->msix_used
= false;
2207 s
->msix_used
= true;
2210 return s
->msix_used
;
2214 vmxnet3_cleanup_msix(VMXNET3State
*s
)
2216 PCIDevice
*d
= PCI_DEVICE(s
);
2219 vmxnet3_unuse_msix_vectors(s
, VMXNET3_MAX_INTRS
);
2220 msix_uninit(d
, &s
->msix_bar
, &s
->msix_bar
);
2225 vmxnet3_cleanup_msi(VMXNET3State
*s
)
2227 PCIDevice
*d
= PCI_DEVICE(s
);
2233 vmxnet3_msix_save(QEMUFile
*f
, void *opaque
)
2235 PCIDevice
*d
= PCI_DEVICE(opaque
);
2240 vmxnet3_msix_load(QEMUFile
*f
, void *opaque
, int version_id
)
2242 PCIDevice
*d
= PCI_DEVICE(opaque
);
2247 static const MemoryRegionOps b0_ops
= {
2248 .read
= vmxnet3_io_bar0_read
,
2249 .write
= vmxnet3_io_bar0_write
,
2250 .endianness
= DEVICE_LITTLE_ENDIAN
,
2252 .min_access_size
= 4,
2253 .max_access_size
= 4,
2257 static const MemoryRegionOps b1_ops
= {
2258 .read
= vmxnet3_io_bar1_read
,
2259 .write
= vmxnet3_io_bar1_write
,
2260 .endianness
= DEVICE_LITTLE_ENDIAN
,
2262 .min_access_size
= 4,
2263 .max_access_size
= 4,
2267 static SaveVMHandlers savevm_vmxnet3_msix
= {
2268 .save_state
= vmxnet3_msix_save
,
2269 .load_state
= vmxnet3_msix_load
,
2272 static uint64_t vmxnet3_device_serial_num(VMXNET3State
*s
)
2274 uint64_t dsn_payload
;
2275 uint8_t *dsnp
= (uint8_t *)&dsn_payload
;
2278 dsnp
[1] = s
->conf
.macaddr
.a
[3];
2279 dsnp
[2] = s
->conf
.macaddr
.a
[4];
2280 dsnp
[3] = s
->conf
.macaddr
.a
[5];
2281 dsnp
[4] = s
->conf
.macaddr
.a
[0];
2282 dsnp
[5] = s
->conf
.macaddr
.a
[1];
2283 dsnp
[6] = s
->conf
.macaddr
.a
[2];
2289 #define VMXNET3_USE_64BIT (true)
2290 #define VMXNET3_PER_VECTOR_MASK (false)
2292 static void vmxnet3_pci_realize(PCIDevice
*pci_dev
, Error
**errp
)
2294 DeviceState
*dev
= DEVICE(pci_dev
);
2295 VMXNET3State
*s
= VMXNET3(pci_dev
);
2298 VMW_CBPRN("Starting init...");
2300 memory_region_init_io(&s
->bar0
, OBJECT(s
), &b0_ops
, s
,
2301 "vmxnet3-b0", VMXNET3_PT_REG_SIZE
);
2302 pci_register_bar(pci_dev
, VMXNET3_BAR0_IDX
,
2303 PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->bar0
);
2305 memory_region_init_io(&s
->bar1
, OBJECT(s
), &b1_ops
, s
,
2306 "vmxnet3-b1", VMXNET3_VD_REG_SIZE
);
2307 pci_register_bar(pci_dev
, VMXNET3_BAR1_IDX
,
2308 PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->bar1
);
2310 memory_region_init(&s
->msix_bar
, OBJECT(s
), "vmxnet3-msix-bar",
2311 VMXNET3_MSIX_BAR_SIZE
);
2312 pci_register_bar(pci_dev
, VMXNET3_MSIX_BAR_IDX
,
2313 PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->msix_bar
);
2315 vmxnet3_reset_interrupt_states(s
);
2317 /* Interrupt pin A */
2318 pci_dev
->config
[PCI_INTERRUPT_PIN
] = 0x01;
2320 ret
= msi_init(pci_dev
, VMXNET3_MSI_OFFSET(s
), VMXNET3_MAX_NMSIX_INTRS
,
2321 VMXNET3_USE_64BIT
, VMXNET3_PER_VECTOR_MASK
, NULL
);
2322 /* Any error other than -ENOTSUP(board's MSI support is broken)
2323 * is a programming error. Fall back to INTx silently on -ENOTSUP */
2324 assert(!ret
|| ret
== -ENOTSUP
);
2326 if (!vmxnet3_init_msix(s
)) {
2327 VMW_WRPRN("Failed to initialize MSI-X, configuration is inconsistent.");
2330 vmxnet3_net_init(s
);
2332 if (pci_is_express(pci_dev
)) {
2333 if (pci_bus_is_express(pci_dev
->bus
)) {
2334 pcie_endpoint_cap_init(pci_dev
, VMXNET3_EXP_EP_OFFSET
);
2337 pcie_dev_ser_num_init(pci_dev
, VMXNET3_DSN_OFFSET
,
2338 vmxnet3_device_serial_num(s
));
2341 register_savevm_live(dev
, "vmxnet3-msix", -1, 1, &savevm_vmxnet3_msix
, s
);
2344 static void vmxnet3_instance_init(Object
*obj
)
2346 VMXNET3State
*s
= VMXNET3(obj
);
2347 device_add_bootindex_property(obj
, &s
->conf
.bootindex
,
2348 "bootindex", "/ethernet-phy@0",
2352 static void vmxnet3_pci_uninit(PCIDevice
*pci_dev
)
2354 DeviceState
*dev
= DEVICE(pci_dev
);
2355 VMXNET3State
*s
= VMXNET3(pci_dev
);
2357 VMW_CBPRN("Starting uninit...");
2359 unregister_savevm(dev
, "vmxnet3-msix", s
);
2361 vmxnet3_net_uninit(s
);
2363 vmxnet3_cleanup_msix(s
);
2365 vmxnet3_cleanup_msi(s
);
2368 static void vmxnet3_qdev_reset(DeviceState
*dev
)
2370 PCIDevice
*d
= PCI_DEVICE(dev
);
2371 VMXNET3State
*s
= VMXNET3(d
);
2373 VMW_CBPRN("Starting QDEV reset...");
2377 static bool vmxnet3_mc_list_needed(void *opaque
)
2382 static int vmxnet3_mcast_list_pre_load(void *opaque
)
2384 VMXNET3State
*s
= opaque
;
2386 s
->mcast_list
= g_malloc(s
->mcast_list_buff_size
);
2392 static int vmxnet3_pre_save(void *opaque
)
2394 VMXNET3State
*s
= opaque
;
2396 s
->mcast_list_buff_size
= s
->mcast_list_len
* sizeof(MACAddr
);
2401 static const VMStateDescription vmxstate_vmxnet3_mcast_list
= {
2402 .name
= "vmxnet3/mcast_list",
2404 .minimum_version_id
= 1,
2405 .pre_load
= vmxnet3_mcast_list_pre_load
,
2406 .needed
= vmxnet3_mc_list_needed
,
2407 .fields
= (VMStateField
[]) {
2408 VMSTATE_VBUFFER_UINT32(mcast_list
, VMXNET3State
, 0, NULL
,
2409 mcast_list_buff_size
),
2410 VMSTATE_END_OF_LIST()
2414 static const VMStateDescription vmstate_vmxnet3_ring
= {
2415 .name
= "vmxnet3-ring",
2417 .fields
= (VMStateField
[]) {
2418 VMSTATE_UINT64(pa
, Vmxnet3Ring
),
2419 VMSTATE_UINT32(size
, Vmxnet3Ring
),
2420 VMSTATE_UINT32(cell_size
, Vmxnet3Ring
),
2421 VMSTATE_UINT32(next
, Vmxnet3Ring
),
2422 VMSTATE_UINT8(gen
, Vmxnet3Ring
),
2423 VMSTATE_END_OF_LIST()
2427 static const VMStateDescription vmstate_vmxnet3_tx_stats
= {
2428 .name
= "vmxnet3-tx-stats",
2430 .fields
= (VMStateField
[]) {
2431 VMSTATE_UINT64(TSOPktsTxOK
, struct UPT1_TxStats
),
2432 VMSTATE_UINT64(TSOBytesTxOK
, struct UPT1_TxStats
),
2433 VMSTATE_UINT64(ucastPktsTxOK
, struct UPT1_TxStats
),
2434 VMSTATE_UINT64(ucastBytesTxOK
, struct UPT1_TxStats
),
2435 VMSTATE_UINT64(mcastPktsTxOK
, struct UPT1_TxStats
),
2436 VMSTATE_UINT64(mcastBytesTxOK
, struct UPT1_TxStats
),
2437 VMSTATE_UINT64(bcastPktsTxOK
, struct UPT1_TxStats
),
2438 VMSTATE_UINT64(bcastBytesTxOK
, struct UPT1_TxStats
),
2439 VMSTATE_UINT64(pktsTxError
, struct UPT1_TxStats
),
2440 VMSTATE_UINT64(pktsTxDiscard
, struct UPT1_TxStats
),
2441 VMSTATE_END_OF_LIST()
2445 static const VMStateDescription vmstate_vmxnet3_txq_descr
= {
2446 .name
= "vmxnet3-txq-descr",
2448 .fields
= (VMStateField
[]) {
2449 VMSTATE_STRUCT(tx_ring
, Vmxnet3TxqDescr
, 0, vmstate_vmxnet3_ring
,
2451 VMSTATE_STRUCT(comp_ring
, Vmxnet3TxqDescr
, 0, vmstate_vmxnet3_ring
,
2453 VMSTATE_UINT8(intr_idx
, Vmxnet3TxqDescr
),
2454 VMSTATE_UINT64(tx_stats_pa
, Vmxnet3TxqDescr
),
2455 VMSTATE_STRUCT(txq_stats
, Vmxnet3TxqDescr
, 0, vmstate_vmxnet3_tx_stats
,
2456 struct UPT1_TxStats
),
2457 VMSTATE_END_OF_LIST()
2461 static const VMStateDescription vmstate_vmxnet3_rx_stats
= {
2462 .name
= "vmxnet3-rx-stats",
2464 .fields
= (VMStateField
[]) {
2465 VMSTATE_UINT64(LROPktsRxOK
, struct UPT1_RxStats
),
2466 VMSTATE_UINT64(LROBytesRxOK
, struct UPT1_RxStats
),
2467 VMSTATE_UINT64(ucastPktsRxOK
, struct UPT1_RxStats
),
2468 VMSTATE_UINT64(ucastBytesRxOK
, struct UPT1_RxStats
),
2469 VMSTATE_UINT64(mcastPktsRxOK
, struct UPT1_RxStats
),
2470 VMSTATE_UINT64(mcastBytesRxOK
, struct UPT1_RxStats
),
2471 VMSTATE_UINT64(bcastPktsRxOK
, struct UPT1_RxStats
),
2472 VMSTATE_UINT64(bcastBytesRxOK
, struct UPT1_RxStats
),
2473 VMSTATE_UINT64(pktsRxOutOfBuf
, struct UPT1_RxStats
),
2474 VMSTATE_UINT64(pktsRxError
, struct UPT1_RxStats
),
2475 VMSTATE_END_OF_LIST()
2479 static const VMStateDescription vmstate_vmxnet3_rxq_descr
= {
2480 .name
= "vmxnet3-rxq-descr",
2482 .fields
= (VMStateField
[]) {
2483 VMSTATE_STRUCT_ARRAY(rx_ring
, Vmxnet3RxqDescr
,
2484 VMXNET3_RX_RINGS_PER_QUEUE
, 0,
2485 vmstate_vmxnet3_ring
, Vmxnet3Ring
),
2486 VMSTATE_STRUCT(comp_ring
, Vmxnet3RxqDescr
, 0, vmstate_vmxnet3_ring
,
2488 VMSTATE_UINT8(intr_idx
, Vmxnet3RxqDescr
),
2489 VMSTATE_UINT64(rx_stats_pa
, Vmxnet3RxqDescr
),
2490 VMSTATE_STRUCT(rxq_stats
, Vmxnet3RxqDescr
, 0, vmstate_vmxnet3_rx_stats
,
2491 struct UPT1_RxStats
),
2492 VMSTATE_END_OF_LIST()
2496 static int vmxnet3_post_load(void *opaque
, int version_id
)
2498 VMXNET3State
*s
= opaque
;
2499 PCIDevice
*d
= PCI_DEVICE(s
);
2501 net_tx_pkt_init(&s
->tx_pkt
, PCI_DEVICE(s
),
2502 s
->max_tx_frags
, s
->peer_has_vhdr
);
2503 net_rx_pkt_init(&s
->rx_pkt
, s
->peer_has_vhdr
);
2506 if (!vmxnet3_use_msix_vectors(s
, VMXNET3_MAX_INTRS
)) {
2507 VMW_WRPRN("Failed to re-use MSI-X vectors");
2508 msix_uninit(d
, &s
->msix_bar
, &s
->msix_bar
);
2509 s
->msix_used
= false;
2514 vmxnet3_validate_queues(s
);
2515 vmxnet3_validate_interrupts(s
);
2520 static const VMStateDescription vmstate_vmxnet3_int_state
= {
2521 .name
= "vmxnet3-int-state",
2523 .fields
= (VMStateField
[]) {
2524 VMSTATE_BOOL(is_masked
, Vmxnet3IntState
),
2525 VMSTATE_BOOL(is_pending
, Vmxnet3IntState
),
2526 VMSTATE_BOOL(is_asserted
, Vmxnet3IntState
),
2527 VMSTATE_END_OF_LIST()
2531 static bool vmxnet3_vmstate_need_pcie_device(void *opaque
)
2533 VMXNET3State
*s
= VMXNET3(opaque
);
2535 return !(s
->compat_flags
& VMXNET3_COMPAT_FLAG_DISABLE_PCIE
);
2538 static bool vmxnet3_vmstate_test_pci_device(void *opaque
, int version_id
)
2540 return !vmxnet3_vmstate_need_pcie_device(opaque
);
2543 static const VMStateDescription vmstate_vmxnet3_pcie_device
= {
2544 .name
= "vmxnet3/pcie",
2546 .minimum_version_id
= 1,
2547 .needed
= vmxnet3_vmstate_need_pcie_device
,
2548 .fields
= (VMStateField
[]) {
2549 VMSTATE_PCI_DEVICE(parent_obj
, VMXNET3State
),
2550 VMSTATE_END_OF_LIST()
2554 static const VMStateDescription vmstate_vmxnet3
= {
2557 .minimum_version_id
= 1,
2558 .pre_save
= vmxnet3_pre_save
,
2559 .post_load
= vmxnet3_post_load
,
2560 .fields
= (VMStateField
[]) {
2561 VMSTATE_STRUCT_TEST(parent_obj
, VMXNET3State
,
2562 vmxnet3_vmstate_test_pci_device
, 0,
2563 vmstate_pci_device
, PCIDevice
),
2564 VMSTATE_BOOL(rx_packets_compound
, VMXNET3State
),
2565 VMSTATE_BOOL(rx_vlan_stripping
, VMXNET3State
),
2566 VMSTATE_BOOL(lro_supported
, VMXNET3State
),
2567 VMSTATE_UINT32(rx_mode
, VMXNET3State
),
2568 VMSTATE_UINT32(mcast_list_len
, VMXNET3State
),
2569 VMSTATE_UINT32(mcast_list_buff_size
, VMXNET3State
),
2570 VMSTATE_UINT32_ARRAY(vlan_table
, VMXNET3State
, VMXNET3_VFT_SIZE
),
2571 VMSTATE_UINT32(mtu
, VMXNET3State
),
2572 VMSTATE_UINT16(max_rx_frags
, VMXNET3State
),
2573 VMSTATE_UINT32(max_tx_frags
, VMXNET3State
),
2574 VMSTATE_UINT8(event_int_idx
, VMXNET3State
),
2575 VMSTATE_BOOL(auto_int_masking
, VMXNET3State
),
2576 VMSTATE_UINT8(txq_num
, VMXNET3State
),
2577 VMSTATE_UINT8(rxq_num
, VMXNET3State
),
2578 VMSTATE_UINT32(device_active
, VMXNET3State
),
2579 VMSTATE_UINT32(last_command
, VMXNET3State
),
2580 VMSTATE_UINT32(link_status_and_speed
, VMXNET3State
),
2581 VMSTATE_UINT32(temp_mac
, VMXNET3State
),
2582 VMSTATE_UINT64(drv_shmem
, VMXNET3State
),
2583 VMSTATE_UINT64(temp_shared_guest_driver_memory
, VMXNET3State
),
2585 VMSTATE_STRUCT_ARRAY(txq_descr
, VMXNET3State
,
2586 VMXNET3_DEVICE_MAX_TX_QUEUES
, 0, vmstate_vmxnet3_txq_descr
,
2588 VMSTATE_STRUCT_ARRAY(rxq_descr
, VMXNET3State
,
2589 VMXNET3_DEVICE_MAX_RX_QUEUES
, 0, vmstate_vmxnet3_rxq_descr
,
2591 VMSTATE_STRUCT_ARRAY(interrupt_states
, VMXNET3State
,
2592 VMXNET3_MAX_INTRS
, 0, vmstate_vmxnet3_int_state
,
2595 VMSTATE_END_OF_LIST()
2597 .subsections
= (const VMStateDescription
*[]) {
2598 &vmxstate_vmxnet3_mcast_list
,
2599 &vmstate_vmxnet3_pcie_device
,
2604 static Property vmxnet3_properties
[] = {
2605 DEFINE_NIC_PROPERTIES(VMXNET3State
, conf
),
2606 DEFINE_PROP_BIT("x-old-msi-offsets", VMXNET3State
, compat_flags
,
2607 VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT
, false),
2608 DEFINE_PROP_BIT("x-disable-pcie", VMXNET3State
, compat_flags
,
2609 VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT
, false),
2610 DEFINE_PROP_END_OF_LIST(),
2613 static void vmxnet3_realize(DeviceState
*qdev
, Error
**errp
)
2615 VMXNET3Class
*vc
= VMXNET3_DEVICE_GET_CLASS(qdev
);
2616 PCIDevice
*pci_dev
= PCI_DEVICE(qdev
);
2617 VMXNET3State
*s
= VMXNET3(qdev
);
2619 if (!(s
->compat_flags
& VMXNET3_COMPAT_FLAG_DISABLE_PCIE
)) {
2620 pci_dev
->cap_present
|= QEMU_PCI_CAP_EXPRESS
;
2623 vc
->parent_dc_realize(qdev
, errp
);
2626 static void vmxnet3_class_init(ObjectClass
*class, void *data
)
2628 DeviceClass
*dc
= DEVICE_CLASS(class);
2629 PCIDeviceClass
*c
= PCI_DEVICE_CLASS(class);
2630 VMXNET3Class
*vc
= VMXNET3_DEVICE_CLASS(class);
2632 c
->realize
= vmxnet3_pci_realize
;
2633 c
->exit
= vmxnet3_pci_uninit
;
2634 c
->vendor_id
= PCI_VENDOR_ID_VMWARE
;
2635 c
->device_id
= PCI_DEVICE_ID_VMWARE_VMXNET3
;
2636 c
->revision
= PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION
;
2637 c
->romfile
= "efi-vmxnet3.rom";
2638 c
->class_id
= PCI_CLASS_NETWORK_ETHERNET
;
2639 c
->subsystem_vendor_id
= PCI_VENDOR_ID_VMWARE
;
2640 c
->subsystem_id
= PCI_DEVICE_ID_VMWARE_VMXNET3
;
2641 vc
->parent_dc_realize
= dc
->realize
;
2642 dc
->realize
= vmxnet3_realize
;
2643 dc
->desc
= "VMWare Paravirtualized Ethernet v3";
2644 dc
->reset
= vmxnet3_qdev_reset
;
2645 dc
->vmsd
= &vmstate_vmxnet3
;
2646 dc
->props
= vmxnet3_properties
;
2647 set_bit(DEVICE_CATEGORY_NETWORK
, dc
->categories
);
2650 static const TypeInfo vmxnet3_info
= {
2651 .name
= TYPE_VMXNET3
,
2652 .parent
= TYPE_PCI_DEVICE
,
2653 .class_size
= sizeof(VMXNET3Class
),
2654 .instance_size
= sizeof(VMXNET3State
),
2655 .class_init
= vmxnet3_class_init
,
2656 .instance_init
= vmxnet3_instance_init
,
2657 .interfaces
= (InterfaceInfo
[]) {
2658 { INTERFACE_PCIE_DEVICE
},
2659 { INTERFACE_CONVENTIONAL_PCI_DEVICE
},
2664 static void vmxnet3_register_types(void)
2666 VMW_CBPRN("vmxnet3_register_types called...");
2667 type_register_static(&vmxnet3_info
);
2670 type_init(vmxnet3_register_types
)