2 * QEMU NVM Express Controller
4 * Copyright (c) 2012, Intel Corporation
6 * Written by Keith Busch <keith.busch@intel.com>
8 * This code is licensed under the GNU GPL v2 or later.
12 * Reference Specs: http://www.nvmexpress.org, 1.4, 1.3, 1.2, 1.1, 1.0e
14 * https://nvmexpress.org/developers/nvme-specification/
17 * Notes on coding style
18 * ---------------------
19 * While QEMU coding style prefers lowercase hexadecimals in constants, the
20 * NVMe subsystem use thes format from the NVMe specifications in the comments
21 * (i.e. 'h' suffix instead of '0x' prefix).
25 * See docs/system/nvme.rst for extensive documentation.
28 * -drive file=<file>,if=none,id=<drive_id>
29 * -device nvme-subsys,id=<subsys_id>,nqn=<nqn_id>
30 * -device nvme,serial=<serial>,id=<bus_name>, \
31 * cmb_size_mb=<cmb_size_mb[optional]>, \
32 * [pmrdev=<mem_backend_file_id>,] \
33 * max_ioqpairs=<N[optional]>, \
34 * aerl=<N[optional]>,aer_max_queued=<N[optional]>, \
35 * mdts=<N[optional]>,vsl=<N[optional]>, \
36 * zoned.zasl=<N[optional]>, \
38 * -device nvme-ns,drive=<drive_id>,bus=<bus_name>,nsid=<nsid>,\
39 * zoned=<true|false[optional]>, \
40 * subsys=<subsys_id>,detached=<true|false[optional]>
42 * Note cmb_size_mb denotes size of CMB in MB. CMB is assumed to be at
43 * offset 0 in BAR2 and supports only WDS, RDS and SQS for now. By default, the
44 * device will use the "v1.4 CMB scheme" - use the `legacy-cmb` parameter to
45 * always enable the CMBLOC and CMBSZ registers (v1.3 behavior).
47 * Enabling pmr emulation can be achieved by pointing to memory-backend-file.
49 * -object memory-backend-file,id=<mem_id>,share=on,mem-path=<file_path>, \
50 * size=<size> .... -device nvme,...,pmrdev=<mem_id>
52 * The PMR will use BAR 4/5 exclusively.
54 * To place controller(s) and namespace(s) to a subsystem, then provide
55 * nvme-subsys device as above.
57 * nvme subsystem device parameters
58 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
60 * This parameter provides the `<nqn_id>` part of the string
61 * `nqn.2019-08.org.qemu:<nqn_id>` which will be reported in the SUBNQN field
62 * of subsystem controllers. Note that `<nqn_id>` should be unique per
63 * subsystem, but this is not enforced by QEMU. If not specified, it will
64 * default to the value of the `id` parameter (`<subsys_id>`).
66 * nvme device parameters
67 * ~~~~~~~~~~~~~~~~~~~~~~
69 * Specifying this parameter attaches the controller to the subsystem and
70 * the SUBNQN field in the controller will report the NQN of the subsystem
71 * device. This also enables multi controller capability represented in
72 * Identify Controller data structure in CMIC (Controller Multi-path I/O and
73 * Namesapce Sharing Capabilities).
76 * The Asynchronous Event Request Limit (AERL). Indicates the maximum number
77 * of concurrently outstanding Asynchronous Event Request commands support
78 * by the controller. This is a 0's based value.
81 * This is the maximum number of events that the device will enqueue for
82 * completion when there are no outstanding AERs. When the maximum number of
83 * enqueued events are reached, subsequent events will be dropped.
86 * Indicates the maximum data transfer size for a command that transfers data
87 * between host-accessible memory and the controller. The value is specified
88 * as a power of two (2^n) and is in units of the minimum memory page size
89 * (CAP.MPSMIN). The default value is 7 (i.e. 512 KiB).
92 * Indicates the maximum data size limit for the Verify command. Like `mdts`,
93 * this value is specified as a power of two (2^n) and is in units of the
94 * minimum memory page size (CAP.MPSMIN). The default value is 7 (i.e. 512
98 * Indicates the maximum data transfer size for the Zone Append command. Like
99 * `mdts`, the value is specified as a power of two (2^n) and is in units of
100 * the minimum memory page size (CAP.MPSMIN). The default value is 0 (i.e.
101 * defaulting to the value of `mdts`).
103 * nvme namespace device parameters
104 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
106 * When the parent nvme device (as defined explicitly by the 'bus' parameter
107 * or implicitly by the most recently defined NvmeBus) is linked to an
108 * nvme-subsys device, the namespace will be attached to all controllers in
109 * the subsystem. If set to 'off' (the default), the namespace will remain a
110 * private namespace and may only be attached to a single controller at a
114 * This parameter is only valid together with the `subsys` parameter. If left
115 * at the default value (`false/off`), the namespace will be attached to all
116 * controllers in the NVMe subsystem at boot-up. If set to `true/on`, the
117 * namespace will be be available in the subsystem not not attached to any
120 * Setting `zoned` to true selects Zoned Command Set at the namespace.
121 * In this case, the following namespace properties are available to configure
123 * zoned.zone_size=<zone size in bytes, default: 128MiB>
124 * The number may be followed by K, M, G as in kilo-, mega- or giga-.
126 * zoned.zone_capacity=<zone capacity in bytes, default: zone size>
127 * The value 0 (default) forces zone capacity to be the same as zone
128 * size. The value of this property may not exceed zone size.
130 * zoned.descr_ext_size=<zone descriptor extension size, default 0>
131 * This value needs to be specified in 64B units. If it is zero,
132 * namespace(s) will not support zone descriptor extensions.
134 * zoned.max_active=<Maximum Active Resources (zones), default: 0>
135 * The default value means there is no limit to the number of
136 * concurrently active zones.
138 * zoned.max_open=<Maximum Open Resources (zones), default: 0>
139 * The default value means there is no limit to the number of
140 * concurrently open zones.
142 * zoned.cross_read=<enable RAZB, default: false>
143 * Setting this property to true enables Read Across Zone Boundaries.
146 #include "qemu/osdep.h"
147 #include "qemu/cutils.h"
148 #include "qemu/error-report.h"
149 #include "qemu/log.h"
150 #include "qemu/units.h"
151 #include "qapi/error.h"
152 #include "qapi/visitor.h"
153 #include "sysemu/sysemu.h"
154 #include "sysemu/block-backend.h"
155 #include "sysemu/hostmem.h"
156 #include "hw/pci/msix.h"
157 #include "migration/vmstate.h"
162 #define NVME_MAX_IOQPAIRS 0xffff
163 #define NVME_DB_SIZE 4
164 #define NVME_SPEC_VER 0x00010400
165 #define NVME_CMB_BIR 2
166 #define NVME_PMR_BIR 4
167 #define NVME_TEMPERATURE 0x143
168 #define NVME_TEMPERATURE_WARNING 0x157
169 #define NVME_TEMPERATURE_CRITICAL 0x175
170 #define NVME_NUM_FW_SLOTS 1
171 #define NVME_DEFAULT_MAX_ZA_SIZE (128 * KiB)
173 #define NVME_GUEST_ERR(trace, fmt, ...) \
175 (trace_##trace)(__VA_ARGS__); \
176 qemu_log_mask(LOG_GUEST_ERROR, #trace \
177 " in %s: " fmt "\n", __func__, ## __VA_ARGS__); \
180 static const bool nvme_feature_support
[NVME_FID_MAX
] = {
181 [NVME_ARBITRATION
] = true,
182 [NVME_POWER_MANAGEMENT
] = true,
183 [NVME_TEMPERATURE_THRESHOLD
] = true,
184 [NVME_ERROR_RECOVERY
] = true,
185 [NVME_VOLATILE_WRITE_CACHE
] = true,
186 [NVME_NUMBER_OF_QUEUES
] = true,
187 [NVME_INTERRUPT_COALESCING
] = true,
188 [NVME_INTERRUPT_VECTOR_CONF
] = true,
189 [NVME_WRITE_ATOMICITY
] = true,
190 [NVME_ASYNCHRONOUS_EVENT_CONF
] = true,
191 [NVME_TIMESTAMP
] = true,
192 [NVME_COMMAND_SET_PROFILE
] = true,
195 static const uint32_t nvme_feature_cap
[NVME_FID_MAX
] = {
196 [NVME_TEMPERATURE_THRESHOLD
] = NVME_FEAT_CAP_CHANGE
,
197 [NVME_ERROR_RECOVERY
] = NVME_FEAT_CAP_CHANGE
| NVME_FEAT_CAP_NS
,
198 [NVME_VOLATILE_WRITE_CACHE
] = NVME_FEAT_CAP_CHANGE
,
199 [NVME_NUMBER_OF_QUEUES
] = NVME_FEAT_CAP_CHANGE
,
200 [NVME_ASYNCHRONOUS_EVENT_CONF
] = NVME_FEAT_CAP_CHANGE
,
201 [NVME_TIMESTAMP
] = NVME_FEAT_CAP_CHANGE
,
202 [NVME_COMMAND_SET_PROFILE
] = NVME_FEAT_CAP_CHANGE
,
205 static const uint32_t nvme_cse_acs
[256] = {
206 [NVME_ADM_CMD_DELETE_SQ
] = NVME_CMD_EFF_CSUPP
,
207 [NVME_ADM_CMD_CREATE_SQ
] = NVME_CMD_EFF_CSUPP
,
208 [NVME_ADM_CMD_GET_LOG_PAGE
] = NVME_CMD_EFF_CSUPP
,
209 [NVME_ADM_CMD_DELETE_CQ
] = NVME_CMD_EFF_CSUPP
,
210 [NVME_ADM_CMD_CREATE_CQ
] = NVME_CMD_EFF_CSUPP
,
211 [NVME_ADM_CMD_IDENTIFY
] = NVME_CMD_EFF_CSUPP
,
212 [NVME_ADM_CMD_ABORT
] = NVME_CMD_EFF_CSUPP
,
213 [NVME_ADM_CMD_SET_FEATURES
] = NVME_CMD_EFF_CSUPP
,
214 [NVME_ADM_CMD_GET_FEATURES
] = NVME_CMD_EFF_CSUPP
,
215 [NVME_ADM_CMD_ASYNC_EV_REQ
] = NVME_CMD_EFF_CSUPP
,
216 [NVME_ADM_CMD_NS_ATTACHMENT
] = NVME_CMD_EFF_CSUPP
| NVME_CMD_EFF_NIC
,
217 [NVME_ADM_CMD_FORMAT_NVM
] = NVME_CMD_EFF_CSUPP
| NVME_CMD_EFF_LBCC
,
220 static const uint32_t nvme_cse_iocs_none
[256];
222 static const uint32_t nvme_cse_iocs_nvm
[256] = {
223 [NVME_CMD_FLUSH
] = NVME_CMD_EFF_CSUPP
| NVME_CMD_EFF_LBCC
,
224 [NVME_CMD_WRITE_ZEROES
] = NVME_CMD_EFF_CSUPP
| NVME_CMD_EFF_LBCC
,
225 [NVME_CMD_WRITE
] = NVME_CMD_EFF_CSUPP
| NVME_CMD_EFF_LBCC
,
226 [NVME_CMD_READ
] = NVME_CMD_EFF_CSUPP
,
227 [NVME_CMD_DSM
] = NVME_CMD_EFF_CSUPP
| NVME_CMD_EFF_LBCC
,
228 [NVME_CMD_VERIFY
] = NVME_CMD_EFF_CSUPP
,
229 [NVME_CMD_COPY
] = NVME_CMD_EFF_CSUPP
| NVME_CMD_EFF_LBCC
,
230 [NVME_CMD_COMPARE
] = NVME_CMD_EFF_CSUPP
,
233 static const uint32_t nvme_cse_iocs_zoned
[256] = {
234 [NVME_CMD_FLUSH
] = NVME_CMD_EFF_CSUPP
| NVME_CMD_EFF_LBCC
,
235 [NVME_CMD_WRITE_ZEROES
] = NVME_CMD_EFF_CSUPP
| NVME_CMD_EFF_LBCC
,
236 [NVME_CMD_WRITE
] = NVME_CMD_EFF_CSUPP
| NVME_CMD_EFF_LBCC
,
237 [NVME_CMD_READ
] = NVME_CMD_EFF_CSUPP
,
238 [NVME_CMD_DSM
] = NVME_CMD_EFF_CSUPP
| NVME_CMD_EFF_LBCC
,
239 [NVME_CMD_VERIFY
] = NVME_CMD_EFF_CSUPP
,
240 [NVME_CMD_COPY
] = NVME_CMD_EFF_CSUPP
| NVME_CMD_EFF_LBCC
,
241 [NVME_CMD_COMPARE
] = NVME_CMD_EFF_CSUPP
,
242 [NVME_CMD_ZONE_APPEND
] = NVME_CMD_EFF_CSUPP
| NVME_CMD_EFF_LBCC
,
243 [NVME_CMD_ZONE_MGMT_SEND
] = NVME_CMD_EFF_CSUPP
| NVME_CMD_EFF_LBCC
,
244 [NVME_CMD_ZONE_MGMT_RECV
] = NVME_CMD_EFF_CSUPP
,
247 static void nvme_process_sq(void *opaque
);
249 static uint16_t nvme_sqid(NvmeRequest
*req
)
251 return le16_to_cpu(req
->sq
->sqid
);
254 static void nvme_assign_zone_state(NvmeNamespace
*ns
, NvmeZone
*zone
,
257 if (QTAILQ_IN_USE(zone
, entry
)) {
258 switch (nvme_get_zone_state(zone
)) {
259 case NVME_ZONE_STATE_EXPLICITLY_OPEN
:
260 QTAILQ_REMOVE(&ns
->exp_open_zones
, zone
, entry
);
262 case NVME_ZONE_STATE_IMPLICITLY_OPEN
:
263 QTAILQ_REMOVE(&ns
->imp_open_zones
, zone
, entry
);
265 case NVME_ZONE_STATE_CLOSED
:
266 QTAILQ_REMOVE(&ns
->closed_zones
, zone
, entry
);
268 case NVME_ZONE_STATE_FULL
:
269 QTAILQ_REMOVE(&ns
->full_zones
, zone
, entry
);
275 nvme_set_zone_state(zone
, state
);
278 case NVME_ZONE_STATE_EXPLICITLY_OPEN
:
279 QTAILQ_INSERT_TAIL(&ns
->exp_open_zones
, zone
, entry
);
281 case NVME_ZONE_STATE_IMPLICITLY_OPEN
:
282 QTAILQ_INSERT_TAIL(&ns
->imp_open_zones
, zone
, entry
);
284 case NVME_ZONE_STATE_CLOSED
:
285 QTAILQ_INSERT_TAIL(&ns
->closed_zones
, zone
, entry
);
287 case NVME_ZONE_STATE_FULL
:
288 QTAILQ_INSERT_TAIL(&ns
->full_zones
, zone
, entry
);
289 case NVME_ZONE_STATE_READ_ONLY
:
297 * Check if we can open a zone without exceeding open/active limits.
298 * AOR stands for "Active and Open Resources" (see TP 4053 section 2.5).
300 static int nvme_aor_check(NvmeNamespace
*ns
, uint32_t act
, uint32_t opn
)
302 if (ns
->params
.max_active_zones
!= 0 &&
303 ns
->nr_active_zones
+ act
> ns
->params
.max_active_zones
) {
304 trace_pci_nvme_err_insuff_active_res(ns
->params
.max_active_zones
);
305 return NVME_ZONE_TOO_MANY_ACTIVE
| NVME_DNR
;
307 if (ns
->params
.max_open_zones
!= 0 &&
308 ns
->nr_open_zones
+ opn
> ns
->params
.max_open_zones
) {
309 trace_pci_nvme_err_insuff_open_res(ns
->params
.max_open_zones
);
310 return NVME_ZONE_TOO_MANY_OPEN
| NVME_DNR
;
316 static bool nvme_addr_is_cmb(NvmeCtrl
*n
, hwaddr addr
)
324 lo
= n
->params
.legacy_cmb
? n
->cmb
.mem
.addr
: n
->cmb
.cba
;
325 hi
= lo
+ int128_get64(n
->cmb
.mem
.size
);
327 return addr
>= lo
&& addr
< hi
;
330 static inline void *nvme_addr_to_cmb(NvmeCtrl
*n
, hwaddr addr
)
332 hwaddr base
= n
->params
.legacy_cmb
? n
->cmb
.mem
.addr
: n
->cmb
.cba
;
333 return &n
->cmb
.buf
[addr
- base
];
336 static bool nvme_addr_is_pmr(NvmeCtrl
*n
, hwaddr addr
)
344 hi
= n
->pmr
.cba
+ int128_get64(n
->pmr
.dev
->mr
.size
);
346 return addr
>= n
->pmr
.cba
&& addr
< hi
;
349 static inline void *nvme_addr_to_pmr(NvmeCtrl
*n
, hwaddr addr
)
351 return memory_region_get_ram_ptr(&n
->pmr
.dev
->mr
) + (addr
- n
->pmr
.cba
);
354 static int nvme_addr_read(NvmeCtrl
*n
, hwaddr addr
, void *buf
, int size
)
356 hwaddr hi
= addr
+ size
- 1;
361 if (n
->bar
.cmbsz
&& nvme_addr_is_cmb(n
, addr
) && nvme_addr_is_cmb(n
, hi
)) {
362 memcpy(buf
, nvme_addr_to_cmb(n
, addr
), size
);
366 if (nvme_addr_is_pmr(n
, addr
) && nvme_addr_is_pmr(n
, hi
)) {
367 memcpy(buf
, nvme_addr_to_pmr(n
, addr
), size
);
371 return pci_dma_read(&n
->parent_obj
, addr
, buf
, size
);
374 static int nvme_addr_write(NvmeCtrl
*n
, hwaddr addr
, void *buf
, int size
)
376 hwaddr hi
= addr
+ size
- 1;
381 if (n
->bar
.cmbsz
&& nvme_addr_is_cmb(n
, addr
) && nvme_addr_is_cmb(n
, hi
)) {
382 memcpy(nvme_addr_to_cmb(n
, addr
), buf
, size
);
386 if (nvme_addr_is_pmr(n
, addr
) && nvme_addr_is_pmr(n
, hi
)) {
387 memcpy(nvme_addr_to_pmr(n
, addr
), buf
, size
);
391 return pci_dma_write(&n
->parent_obj
, addr
, buf
, size
);
394 static bool nvme_nsid_valid(NvmeCtrl
*n
, uint32_t nsid
)
396 return nsid
&& (nsid
== NVME_NSID_BROADCAST
|| nsid
<= n
->num_namespaces
);
399 static int nvme_check_sqid(NvmeCtrl
*n
, uint16_t sqid
)
401 return sqid
< n
->params
.max_ioqpairs
+ 1 && n
->sq
[sqid
] != NULL
? 0 : -1;
404 static int nvme_check_cqid(NvmeCtrl
*n
, uint16_t cqid
)
406 return cqid
< n
->params
.max_ioqpairs
+ 1 && n
->cq
[cqid
] != NULL
? 0 : -1;
409 static void nvme_inc_cq_tail(NvmeCQueue
*cq
)
412 if (cq
->tail
>= cq
->size
) {
414 cq
->phase
= !cq
->phase
;
418 static void nvme_inc_sq_head(NvmeSQueue
*sq
)
420 sq
->head
= (sq
->head
+ 1) % sq
->size
;
423 static uint8_t nvme_cq_full(NvmeCQueue
*cq
)
425 return (cq
->tail
+ 1) % cq
->size
== cq
->head
;
428 static uint8_t nvme_sq_empty(NvmeSQueue
*sq
)
430 return sq
->head
== sq
->tail
;
433 static void nvme_irq_check(NvmeCtrl
*n
)
435 if (msix_enabled(&(n
->parent_obj
))) {
438 if (~n
->bar
.intms
& n
->irq_status
) {
439 pci_irq_assert(&n
->parent_obj
);
441 pci_irq_deassert(&n
->parent_obj
);
445 static void nvme_irq_assert(NvmeCtrl
*n
, NvmeCQueue
*cq
)
447 if (cq
->irq_enabled
) {
448 if (msix_enabled(&(n
->parent_obj
))) {
449 trace_pci_nvme_irq_msix(cq
->vector
);
450 msix_notify(&(n
->parent_obj
), cq
->vector
);
452 trace_pci_nvme_irq_pin();
453 assert(cq
->vector
< 32);
454 n
->irq_status
|= 1 << cq
->vector
;
458 trace_pci_nvme_irq_masked();
462 static void nvme_irq_deassert(NvmeCtrl
*n
, NvmeCQueue
*cq
)
464 if (cq
->irq_enabled
) {
465 if (msix_enabled(&(n
->parent_obj
))) {
468 assert(cq
->vector
< 32);
469 n
->irq_status
&= ~(1 << cq
->vector
);
475 static void nvme_req_clear(NvmeRequest
*req
)
480 memset(&req
->cqe
, 0x0, sizeof(req
->cqe
));
481 req
->status
= NVME_SUCCESS
;
484 static inline void nvme_sg_init(NvmeCtrl
*n
, NvmeSg
*sg
, bool dma
)
487 pci_dma_sglist_init(&sg
->qsg
, &n
->parent_obj
, 0);
488 sg
->flags
= NVME_SG_DMA
;
490 qemu_iovec_init(&sg
->iov
, 0);
493 sg
->flags
|= NVME_SG_ALLOC
;
496 static inline void nvme_sg_unmap(NvmeSg
*sg
)
498 if (!(sg
->flags
& NVME_SG_ALLOC
)) {
502 if (sg
->flags
& NVME_SG_DMA
) {
503 qemu_sglist_destroy(&sg
->qsg
);
505 qemu_iovec_destroy(&sg
->iov
);
508 memset(sg
, 0x0, sizeof(*sg
));
512 * When metadata is transfered as extended LBAs, the DPTR mapped into `sg`
513 * holds both data and metadata. This function splits the data and metadata
514 * into two separate QSG/IOVs.
516 static void nvme_sg_split(NvmeSg
*sg
, NvmeNamespace
*ns
, NvmeSg
*data
,
520 size_t size
= nvme_lsize(ns
);
521 size_t msize
= nvme_msize(ns
);
522 uint32_t trans_len
, count
= size
;
524 bool dma
= sg
->flags
& NVME_SG_DMA
;
526 size_t sg_len
= dma
? sg
->qsg
.size
: sg
->iov
.size
;
529 assert(sg
->flags
& NVME_SG_ALLOC
);
532 sge_len
= dma
? sg
->qsg
.sg
[sg_idx
].len
: sg
->iov
.iov
[sg_idx
].iov_len
;
534 trans_len
= MIN(sg_len
, count
);
535 trans_len
= MIN(trans_len
, sge_len
- offset
);
539 qemu_sglist_add(&dst
->qsg
, sg
->qsg
.sg
[sg_idx
].base
+ offset
,
542 qemu_iovec_add(&dst
->iov
,
543 sg
->iov
.iov
[sg_idx
].iov_base
+ offset
,
553 dst
= (dst
== data
) ? mdata
: data
;
554 count
= (dst
== data
) ? size
: msize
;
557 if (sge_len
== offset
) {
564 static uint16_t nvme_map_addr_cmb(NvmeCtrl
*n
, QEMUIOVector
*iov
, hwaddr addr
,
571 trace_pci_nvme_map_addr_cmb(addr
, len
);
573 if (!nvme_addr_is_cmb(n
, addr
) || !nvme_addr_is_cmb(n
, addr
+ len
- 1)) {
574 return NVME_DATA_TRAS_ERROR
;
577 qemu_iovec_add(iov
, nvme_addr_to_cmb(n
, addr
), len
);
582 static uint16_t nvme_map_addr_pmr(NvmeCtrl
*n
, QEMUIOVector
*iov
, hwaddr addr
,
589 if (!nvme_addr_is_pmr(n
, addr
) || !nvme_addr_is_pmr(n
, addr
+ len
- 1)) {
590 return NVME_DATA_TRAS_ERROR
;
593 qemu_iovec_add(iov
, nvme_addr_to_pmr(n
, addr
), len
);
598 static uint16_t nvme_map_addr(NvmeCtrl
*n
, NvmeSg
*sg
, hwaddr addr
, size_t len
)
600 bool cmb
= false, pmr
= false;
606 trace_pci_nvme_map_addr(addr
, len
);
608 if (nvme_addr_is_cmb(n
, addr
)) {
610 } else if (nvme_addr_is_pmr(n
, addr
)) {
615 if (sg
->flags
& NVME_SG_DMA
) {
616 return NVME_INVALID_USE_OF_CMB
| NVME_DNR
;
620 return nvme_map_addr_cmb(n
, &sg
->iov
, addr
, len
);
622 return nvme_map_addr_pmr(n
, &sg
->iov
, addr
, len
);
626 if (!(sg
->flags
& NVME_SG_DMA
)) {
627 return NVME_INVALID_USE_OF_CMB
| NVME_DNR
;
630 qemu_sglist_add(&sg
->qsg
, addr
, len
);
635 static inline bool nvme_addr_is_dma(NvmeCtrl
*n
, hwaddr addr
)
637 return !(nvme_addr_is_cmb(n
, addr
) || nvme_addr_is_pmr(n
, addr
));
640 static uint16_t nvme_map_prp(NvmeCtrl
*n
, NvmeSg
*sg
, uint64_t prp1
,
641 uint64_t prp2
, uint32_t len
)
643 hwaddr trans_len
= n
->page_size
- (prp1
% n
->page_size
);
644 trans_len
= MIN(len
, trans_len
);
645 int num_prps
= (len
>> n
->page_bits
) + 1;
649 trace_pci_nvme_map_prp(trans_len
, len
, prp1
, prp2
, num_prps
);
651 nvme_sg_init(n
, sg
, nvme_addr_is_dma(n
, prp1
));
653 status
= nvme_map_addr(n
, sg
, prp1
, trans_len
);
660 if (len
> n
->page_size
) {
661 uint64_t prp_list
[n
->max_prp_ents
];
662 uint32_t nents
, prp_trans
;
666 * The first PRP list entry, pointed to by PRP2 may contain offset.
667 * Hence, we need to calculate the number of entries in based on
670 nents
= (n
->page_size
- (prp2
& (n
->page_size
- 1))) >> 3;
671 prp_trans
= MIN(n
->max_prp_ents
, nents
) * sizeof(uint64_t);
672 ret
= nvme_addr_read(n
, prp2
, (void *)prp_list
, prp_trans
);
674 trace_pci_nvme_err_addr_read(prp2
);
675 status
= NVME_DATA_TRAS_ERROR
;
679 uint64_t prp_ent
= le64_to_cpu(prp_list
[i
]);
681 if (i
== nents
- 1 && len
> n
->page_size
) {
682 if (unlikely(prp_ent
& (n
->page_size
- 1))) {
683 trace_pci_nvme_err_invalid_prplist_ent(prp_ent
);
684 status
= NVME_INVALID_PRP_OFFSET
| NVME_DNR
;
689 nents
= (len
+ n
->page_size
- 1) >> n
->page_bits
;
690 nents
= MIN(nents
, n
->max_prp_ents
);
691 prp_trans
= nents
* sizeof(uint64_t);
692 ret
= nvme_addr_read(n
, prp_ent
, (void *)prp_list
,
695 trace_pci_nvme_err_addr_read(prp_ent
);
696 status
= NVME_DATA_TRAS_ERROR
;
699 prp_ent
= le64_to_cpu(prp_list
[i
]);
702 if (unlikely(prp_ent
& (n
->page_size
- 1))) {
703 trace_pci_nvme_err_invalid_prplist_ent(prp_ent
);
704 status
= NVME_INVALID_PRP_OFFSET
| NVME_DNR
;
708 trans_len
= MIN(len
, n
->page_size
);
709 status
= nvme_map_addr(n
, sg
, prp_ent
, trans_len
);
718 if (unlikely(prp2
& (n
->page_size
- 1))) {
719 trace_pci_nvme_err_invalid_prp2_align(prp2
);
720 status
= NVME_INVALID_PRP_OFFSET
| NVME_DNR
;
723 status
= nvme_map_addr(n
, sg
, prp2
, len
);
738 * Map 'nsgld' data descriptors from 'segment'. The function will subtract the
739 * number of bytes mapped in len.
741 static uint16_t nvme_map_sgl_data(NvmeCtrl
*n
, NvmeSg
*sg
,
742 NvmeSglDescriptor
*segment
, uint64_t nsgld
,
743 size_t *len
, NvmeCmd
*cmd
)
745 dma_addr_t addr
, trans_len
;
749 for (int i
= 0; i
< nsgld
; i
++) {
750 uint8_t type
= NVME_SGL_TYPE(segment
[i
].type
);
753 case NVME_SGL_DESCR_TYPE_BIT_BUCKET
:
754 if (cmd
->opcode
== NVME_CMD_WRITE
) {
757 case NVME_SGL_DESCR_TYPE_DATA_BLOCK
:
759 case NVME_SGL_DESCR_TYPE_SEGMENT
:
760 case NVME_SGL_DESCR_TYPE_LAST_SEGMENT
:
761 return NVME_INVALID_NUM_SGL_DESCRS
| NVME_DNR
;
763 return NVME_SGL_DESCR_TYPE_INVALID
| NVME_DNR
;
766 dlen
= le32_to_cpu(segment
[i
].len
);
774 * All data has been mapped, but the SGL contains additional
775 * segments and/or descriptors. The controller might accept
776 * ignoring the rest of the SGL.
778 uint32_t sgls
= le32_to_cpu(n
->id_ctrl
.sgls
);
779 if (sgls
& NVME_CTRL_SGLS_EXCESS_LENGTH
) {
783 trace_pci_nvme_err_invalid_sgl_excess_length(dlen
);
784 return NVME_DATA_SGL_LEN_INVALID
| NVME_DNR
;
787 trans_len
= MIN(*len
, dlen
);
789 if (type
== NVME_SGL_DESCR_TYPE_BIT_BUCKET
) {
793 addr
= le64_to_cpu(segment
[i
].addr
);
795 if (UINT64_MAX
- addr
< dlen
) {
796 return NVME_DATA_SGL_LEN_INVALID
| NVME_DNR
;
799 status
= nvme_map_addr(n
, sg
, addr
, trans_len
);
811 static uint16_t nvme_map_sgl(NvmeCtrl
*n
, NvmeSg
*sg
, NvmeSglDescriptor sgl
,
812 size_t len
, NvmeCmd
*cmd
)
815 * Read the segment in chunks of 256 descriptors (one 4k page) to avoid
816 * dynamically allocating a potentially huge SGL. The spec allows the SGL
817 * to be larger (as in number of bytes required to describe the SGL
818 * descriptors and segment chain) than the command transfer size, so it is
819 * not bounded by MDTS.
821 const int SEG_CHUNK_SIZE
= 256;
823 NvmeSglDescriptor segment
[SEG_CHUNK_SIZE
], *sgld
, *last_sgld
;
831 addr
= le64_to_cpu(sgl
.addr
);
833 trace_pci_nvme_map_sgl(NVME_SGL_TYPE(sgl
.type
), len
);
835 nvme_sg_init(n
, sg
, nvme_addr_is_dma(n
, addr
));
838 * If the entire transfer can be described with a single data block it can
839 * be mapped directly.
841 if (NVME_SGL_TYPE(sgl
.type
) == NVME_SGL_DESCR_TYPE_DATA_BLOCK
) {
842 status
= nvme_map_sgl_data(n
, sg
, sgld
, 1, &len
, cmd
);
851 switch (NVME_SGL_TYPE(sgld
->type
)) {
852 case NVME_SGL_DESCR_TYPE_SEGMENT
:
853 case NVME_SGL_DESCR_TYPE_LAST_SEGMENT
:
856 return NVME_INVALID_SGL_SEG_DESCR
| NVME_DNR
;
859 seg_len
= le32_to_cpu(sgld
->len
);
861 /* check the length of the (Last) Segment descriptor */
862 if ((!seg_len
|| seg_len
& 0xf) &&
863 (NVME_SGL_TYPE(sgld
->type
) != NVME_SGL_DESCR_TYPE_BIT_BUCKET
)) {
864 return NVME_INVALID_SGL_SEG_DESCR
| NVME_DNR
;
867 if (UINT64_MAX
- addr
< seg_len
) {
868 return NVME_DATA_SGL_LEN_INVALID
| NVME_DNR
;
871 nsgld
= seg_len
/ sizeof(NvmeSglDescriptor
);
873 while (nsgld
> SEG_CHUNK_SIZE
) {
874 if (nvme_addr_read(n
, addr
, segment
, sizeof(segment
))) {
875 trace_pci_nvme_err_addr_read(addr
);
876 status
= NVME_DATA_TRAS_ERROR
;
880 status
= nvme_map_sgl_data(n
, sg
, segment
, SEG_CHUNK_SIZE
,
886 nsgld
-= SEG_CHUNK_SIZE
;
887 addr
+= SEG_CHUNK_SIZE
* sizeof(NvmeSglDescriptor
);
890 ret
= nvme_addr_read(n
, addr
, segment
, nsgld
*
891 sizeof(NvmeSglDescriptor
));
893 trace_pci_nvme_err_addr_read(addr
);
894 status
= NVME_DATA_TRAS_ERROR
;
898 last_sgld
= &segment
[nsgld
- 1];
901 * If the segment ends with a Data Block or Bit Bucket Descriptor Type,
904 switch (NVME_SGL_TYPE(last_sgld
->type
)) {
905 case NVME_SGL_DESCR_TYPE_DATA_BLOCK
:
906 case NVME_SGL_DESCR_TYPE_BIT_BUCKET
:
907 status
= nvme_map_sgl_data(n
, sg
, segment
, nsgld
, &len
, cmd
);
919 * If the last descriptor was not a Data Block or Bit Bucket, then the
920 * current segment must not be a Last Segment.
922 if (NVME_SGL_TYPE(sgld
->type
) == NVME_SGL_DESCR_TYPE_LAST_SEGMENT
) {
923 status
= NVME_INVALID_SGL_SEG_DESCR
| NVME_DNR
;
928 addr
= le64_to_cpu(sgld
->addr
);
931 * Do not map the last descriptor; it will be a Segment or Last Segment
932 * descriptor and is handled by the next iteration.
934 status
= nvme_map_sgl_data(n
, sg
, segment
, nsgld
- 1, &len
, cmd
);
941 /* if there is any residual left in len, the SGL was too short */
943 status
= NVME_DATA_SGL_LEN_INVALID
| NVME_DNR
;
954 uint16_t nvme_map_dptr(NvmeCtrl
*n
, NvmeSg
*sg
, size_t len
,
959 switch (NVME_CMD_FLAGS_PSDT(cmd
->flags
)) {
961 prp1
= le64_to_cpu(cmd
->dptr
.prp1
);
962 prp2
= le64_to_cpu(cmd
->dptr
.prp2
);
964 return nvme_map_prp(n
, sg
, prp1
, prp2
, len
);
965 case NVME_PSDT_SGL_MPTR_CONTIGUOUS
:
966 case NVME_PSDT_SGL_MPTR_SGL
:
967 return nvme_map_sgl(n
, sg
, cmd
->dptr
.sgl
, len
, cmd
);
969 return NVME_INVALID_FIELD
;
973 static uint16_t nvme_map_mptr(NvmeCtrl
*n
, NvmeSg
*sg
, size_t len
,
976 int psdt
= NVME_CMD_FLAGS_PSDT(cmd
->flags
);
977 hwaddr mptr
= le64_to_cpu(cmd
->mptr
);
980 if (psdt
== NVME_PSDT_SGL_MPTR_SGL
) {
981 NvmeSglDescriptor sgl
;
983 if (nvme_addr_read(n
, mptr
, &sgl
, sizeof(sgl
))) {
984 return NVME_DATA_TRAS_ERROR
;
987 status
= nvme_map_sgl(n
, sg
, sgl
, len
, cmd
);
988 if (status
&& (status
& 0x7ff) == NVME_DATA_SGL_LEN_INVALID
) {
989 status
= NVME_MD_SGL_LEN_INVALID
| NVME_DNR
;
995 nvme_sg_init(n
, sg
, nvme_addr_is_dma(n
, mptr
));
996 status
= nvme_map_addr(n
, sg
, mptr
, len
);
1004 static uint16_t nvme_map_data(NvmeCtrl
*n
, uint32_t nlb
, NvmeRequest
*req
)
1006 NvmeNamespace
*ns
= req
->ns
;
1007 NvmeRwCmd
*rw
= (NvmeRwCmd
*)&req
->cmd
;
1008 uint16_t ctrl
= le16_to_cpu(rw
->control
);
1009 size_t len
= nvme_l2b(ns
, nlb
);
1012 if (NVME_ID_NS_DPS_TYPE(ns
->id_ns
.dps
) &&
1013 (ctrl
& NVME_RW_PRINFO_PRACT
&& nvme_msize(ns
) == 8)) {
1017 if (nvme_ns_ext(ns
)) {
1020 len
+= nvme_m2b(ns
, nlb
);
1022 status
= nvme_map_dptr(n
, &sg
, len
, &req
->cmd
);
1027 nvme_sg_init(n
, &req
->sg
, sg
.flags
& NVME_SG_DMA
);
1028 nvme_sg_split(&sg
, ns
, &req
->sg
, NULL
);
1031 return NVME_SUCCESS
;
1035 return nvme_map_dptr(n
, &req
->sg
, len
, &req
->cmd
);
1038 static uint16_t nvme_map_mdata(NvmeCtrl
*n
, uint32_t nlb
, NvmeRequest
*req
)
1040 NvmeNamespace
*ns
= req
->ns
;
1041 size_t len
= nvme_m2b(ns
, nlb
);
1044 if (nvme_ns_ext(ns
)) {
1047 len
+= nvme_l2b(ns
, nlb
);
1049 status
= nvme_map_dptr(n
, &sg
, len
, &req
->cmd
);
1054 nvme_sg_init(n
, &req
->sg
, sg
.flags
& NVME_SG_DMA
);
1055 nvme_sg_split(&sg
, ns
, NULL
, &req
->sg
);
1058 return NVME_SUCCESS
;
1061 return nvme_map_mptr(n
, &req
->sg
, len
, &req
->cmd
);
1064 static uint16_t nvme_tx_interleaved(NvmeCtrl
*n
, NvmeSg
*sg
, uint8_t *ptr
,
1065 uint32_t len
, uint32_t bytes
,
1066 int32_t skip_bytes
, int64_t offset
,
1067 NvmeTxDirection dir
)
1070 uint32_t trans_len
, count
= bytes
;
1071 bool dma
= sg
->flags
& NVME_SG_DMA
;
1076 assert(sg
->flags
& NVME_SG_ALLOC
);
1079 sge_len
= dma
? sg
->qsg
.sg
[sg_idx
].len
: sg
->iov
.iov
[sg_idx
].iov_len
;
1081 if (sge_len
- offset
< 0) {
1087 if (sge_len
== offset
) {
1093 trans_len
= MIN(len
, count
);
1094 trans_len
= MIN(trans_len
, sge_len
- offset
);
1097 addr
= sg
->qsg
.sg
[sg_idx
].base
+ offset
;
1099 addr
= (hwaddr
)(uintptr_t)sg
->iov
.iov
[sg_idx
].iov_base
+ offset
;
1102 if (dir
== NVME_TX_DIRECTION_TO_DEVICE
) {
1103 ret
= nvme_addr_read(n
, addr
, ptr
, trans_len
);
1105 ret
= nvme_addr_write(n
, addr
, ptr
, trans_len
);
1109 return NVME_DATA_TRAS_ERROR
;
1115 offset
+= trans_len
;
1119 offset
+= skip_bytes
;
1123 return NVME_SUCCESS
;
1126 static uint16_t nvme_tx(NvmeCtrl
*n
, NvmeSg
*sg
, uint8_t *ptr
, uint32_t len
,
1127 NvmeTxDirection dir
)
1129 assert(sg
->flags
& NVME_SG_ALLOC
);
1131 if (sg
->flags
& NVME_SG_DMA
) {
1134 if (dir
== NVME_TX_DIRECTION_TO_DEVICE
) {
1135 residual
= dma_buf_write(ptr
, len
, &sg
->qsg
);
1137 residual
= dma_buf_read(ptr
, len
, &sg
->qsg
);
1140 if (unlikely(residual
)) {
1141 trace_pci_nvme_err_invalid_dma();
1142 return NVME_INVALID_FIELD
| NVME_DNR
;
1147 if (dir
== NVME_TX_DIRECTION_TO_DEVICE
) {
1148 bytes
= qemu_iovec_to_buf(&sg
->iov
, 0, ptr
, len
);
1150 bytes
= qemu_iovec_from_buf(&sg
->iov
, 0, ptr
, len
);
1153 if (unlikely(bytes
!= len
)) {
1154 trace_pci_nvme_err_invalid_dma();
1155 return NVME_INVALID_FIELD
| NVME_DNR
;
1159 return NVME_SUCCESS
;
1162 static inline uint16_t nvme_c2h(NvmeCtrl
*n
, uint8_t *ptr
, uint32_t len
,
1167 status
= nvme_map_dptr(n
, &req
->sg
, len
, &req
->cmd
);
1172 return nvme_tx(n
, &req
->sg
, ptr
, len
, NVME_TX_DIRECTION_FROM_DEVICE
);
1175 static inline uint16_t nvme_h2c(NvmeCtrl
*n
, uint8_t *ptr
, uint32_t len
,
1180 status
= nvme_map_dptr(n
, &req
->sg
, len
, &req
->cmd
);
1185 return nvme_tx(n
, &req
->sg
, ptr
, len
, NVME_TX_DIRECTION_TO_DEVICE
);
1188 uint16_t nvme_bounce_data(NvmeCtrl
*n
, uint8_t *ptr
, uint32_t len
,
1189 NvmeTxDirection dir
, NvmeRequest
*req
)
1191 NvmeNamespace
*ns
= req
->ns
;
1192 NvmeRwCmd
*rw
= (NvmeRwCmd
*)&req
->cmd
;
1193 uint16_t ctrl
= le16_to_cpu(rw
->control
);
1195 if (nvme_ns_ext(ns
) &&
1196 !(ctrl
& NVME_RW_PRINFO_PRACT
&& nvme_msize(ns
) == 8)) {
1197 size_t lsize
= nvme_lsize(ns
);
1198 size_t msize
= nvme_msize(ns
);
1200 return nvme_tx_interleaved(n
, &req
->sg
, ptr
, len
, lsize
, msize
, 0,
1204 return nvme_tx(n
, &req
->sg
, ptr
, len
, dir
);
1207 uint16_t nvme_bounce_mdata(NvmeCtrl
*n
, uint8_t *ptr
, uint32_t len
,
1208 NvmeTxDirection dir
, NvmeRequest
*req
)
1210 NvmeNamespace
*ns
= req
->ns
;
1213 if (nvme_ns_ext(ns
)) {
1214 size_t lsize
= nvme_lsize(ns
);
1215 size_t msize
= nvme_msize(ns
);
1217 return nvme_tx_interleaved(n
, &req
->sg
, ptr
, len
, msize
, lsize
, lsize
,
1221 nvme_sg_unmap(&req
->sg
);
1223 status
= nvme_map_mptr(n
, &req
->sg
, len
, &req
->cmd
);
1228 return nvme_tx(n
, &req
->sg
, ptr
, len
, dir
);
1231 static inline void nvme_blk_read(BlockBackend
*blk
, int64_t offset
,
1232 BlockCompletionFunc
*cb
, NvmeRequest
*req
)
1234 assert(req
->sg
.flags
& NVME_SG_ALLOC
);
1236 if (req
->sg
.flags
& NVME_SG_DMA
) {
1237 req
->aiocb
= dma_blk_read(blk
, &req
->sg
.qsg
, offset
, BDRV_SECTOR_SIZE
,
1240 req
->aiocb
= blk_aio_preadv(blk
, offset
, &req
->sg
.iov
, 0, cb
, req
);
1244 static inline void nvme_blk_write(BlockBackend
*blk
, int64_t offset
,
1245 BlockCompletionFunc
*cb
, NvmeRequest
*req
)
1247 assert(req
->sg
.flags
& NVME_SG_ALLOC
);
1249 if (req
->sg
.flags
& NVME_SG_DMA
) {
1250 req
->aiocb
= dma_blk_write(blk
, &req
->sg
.qsg
, offset
, BDRV_SECTOR_SIZE
,
1253 req
->aiocb
= blk_aio_pwritev(blk
, offset
, &req
->sg
.iov
, 0, cb
, req
);
1257 static void nvme_post_cqes(void *opaque
)
1259 NvmeCQueue
*cq
= opaque
;
1260 NvmeCtrl
*n
= cq
->ctrl
;
1261 NvmeRequest
*req
, *next
;
1264 QTAILQ_FOREACH_SAFE(req
, &cq
->req_list
, entry
, next
) {
1268 if (nvme_cq_full(cq
)) {
1273 req
->cqe
.status
= cpu_to_le16((req
->status
<< 1) | cq
->phase
);
1274 req
->cqe
.sq_id
= cpu_to_le16(sq
->sqid
);
1275 req
->cqe
.sq_head
= cpu_to_le16(sq
->head
);
1276 addr
= cq
->dma_addr
+ cq
->tail
* n
->cqe_size
;
1277 ret
= pci_dma_write(&n
->parent_obj
, addr
, (void *)&req
->cqe
,
1280 trace_pci_nvme_err_addr_write(addr
);
1281 trace_pci_nvme_err_cfs();
1282 n
->bar
.csts
= NVME_CSTS_FAILED
;
1285 QTAILQ_REMOVE(&cq
->req_list
, req
, entry
);
1286 nvme_inc_cq_tail(cq
);
1287 nvme_sg_unmap(&req
->sg
);
1288 QTAILQ_INSERT_TAIL(&sq
->req_list
, req
, entry
);
1290 if (cq
->tail
!= cq
->head
) {
1291 nvme_irq_assert(n
, cq
);
1295 static void nvme_enqueue_req_completion(NvmeCQueue
*cq
, NvmeRequest
*req
)
1297 assert(cq
->cqid
== req
->sq
->cqid
);
1298 trace_pci_nvme_enqueue_req_completion(nvme_cid(req
), cq
->cqid
,
1302 trace_pci_nvme_err_req_status(nvme_cid(req
), nvme_nsid(req
->ns
),
1303 req
->status
, req
->cmd
.opcode
);
1306 QTAILQ_REMOVE(&req
->sq
->out_req_list
, req
, entry
);
1307 QTAILQ_INSERT_TAIL(&cq
->req_list
, req
, entry
);
1308 timer_mod(cq
->timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + 500);
1311 static void nvme_process_aers(void *opaque
)
1313 NvmeCtrl
*n
= opaque
;
1314 NvmeAsyncEvent
*event
, *next
;
1316 trace_pci_nvme_process_aers(n
->aer_queued
);
1318 QTAILQ_FOREACH_SAFE(event
, &n
->aer_queue
, entry
, next
) {
1320 NvmeAerResult
*result
;
1322 /* can't post cqe if there is nothing to complete */
1323 if (!n
->outstanding_aers
) {
1324 trace_pci_nvme_no_outstanding_aers();
1328 /* ignore if masked (cqe posted, but event not cleared) */
1329 if (n
->aer_mask
& (1 << event
->result
.event_type
)) {
1330 trace_pci_nvme_aer_masked(event
->result
.event_type
, n
->aer_mask
);
1334 QTAILQ_REMOVE(&n
->aer_queue
, event
, entry
);
1337 n
->aer_mask
|= 1 << event
->result
.event_type
;
1338 n
->outstanding_aers
--;
1340 req
= n
->aer_reqs
[n
->outstanding_aers
];
1342 result
= (NvmeAerResult
*) &req
->cqe
.result
;
1343 result
->event_type
= event
->result
.event_type
;
1344 result
->event_info
= event
->result
.event_info
;
1345 result
->log_page
= event
->result
.log_page
;
1348 trace_pci_nvme_aer_post_cqe(result
->event_type
, result
->event_info
,
1351 nvme_enqueue_req_completion(&n
->admin_cq
, req
);
1355 static void nvme_enqueue_event(NvmeCtrl
*n
, uint8_t event_type
,
1356 uint8_t event_info
, uint8_t log_page
)
1358 NvmeAsyncEvent
*event
;
1360 trace_pci_nvme_enqueue_event(event_type
, event_info
, log_page
);
1362 if (n
->aer_queued
== n
->params
.aer_max_queued
) {
1363 trace_pci_nvme_enqueue_event_noqueue(n
->aer_queued
);
1367 event
= g_new(NvmeAsyncEvent
, 1);
1368 event
->result
= (NvmeAerResult
) {
1369 .event_type
= event_type
,
1370 .event_info
= event_info
,
1371 .log_page
= log_page
,
1374 QTAILQ_INSERT_TAIL(&n
->aer_queue
, event
, entry
);
1377 nvme_process_aers(n
);
1380 static void nvme_smart_event(NvmeCtrl
*n
, uint8_t event
)
1384 /* Ref SPEC <Asynchronous Event Information 0x2013 SMART / Health Status> */
1385 if (!(NVME_AEC_SMART(n
->features
.async_config
) & event
)) {
1390 case NVME_SMART_SPARE
:
1391 aer_info
= NVME_AER_INFO_SMART_SPARE_THRESH
;
1393 case NVME_SMART_TEMPERATURE
:
1394 aer_info
= NVME_AER_INFO_SMART_TEMP_THRESH
;
1396 case NVME_SMART_RELIABILITY
:
1397 case NVME_SMART_MEDIA_READ_ONLY
:
1398 case NVME_SMART_FAILED_VOLATILE_MEDIA
:
1399 case NVME_SMART_PMR_UNRELIABLE
:
1400 aer_info
= NVME_AER_INFO_SMART_RELIABILITY
;
1406 nvme_enqueue_event(n
, NVME_AER_TYPE_SMART
, aer_info
, NVME_LOG_SMART_INFO
);
1409 static void nvme_clear_events(NvmeCtrl
*n
, uint8_t event_type
)
1411 n
->aer_mask
&= ~(1 << event_type
);
1412 if (!QTAILQ_EMPTY(&n
->aer_queue
)) {
1413 nvme_process_aers(n
);
1417 static inline uint16_t nvme_check_mdts(NvmeCtrl
*n
, size_t len
)
1419 uint8_t mdts
= n
->params
.mdts
;
1421 if (mdts
&& len
> n
->page_size
<< mdts
) {
1422 trace_pci_nvme_err_mdts(len
);
1423 return NVME_INVALID_FIELD
| NVME_DNR
;
1426 return NVME_SUCCESS
;
1429 static inline uint16_t nvme_check_bounds(NvmeNamespace
*ns
, uint64_t slba
,
1432 uint64_t nsze
= le64_to_cpu(ns
->id_ns
.nsze
);
1434 if (unlikely(UINT64_MAX
- slba
< nlb
|| slba
+ nlb
> nsze
)) {
1435 trace_pci_nvme_err_invalid_lba_range(slba
, nlb
, nsze
);
1436 return NVME_LBA_RANGE
| NVME_DNR
;
1439 return NVME_SUCCESS
;
1442 static uint16_t nvme_check_dulbe(NvmeNamespace
*ns
, uint64_t slba
,
1445 BlockDriverState
*bs
= blk_bs(ns
->blkconf
.blk
);
1447 int64_t pnum
= 0, bytes
= nvme_l2b(ns
, nlb
);
1448 int64_t offset
= nvme_l2b(ns
, slba
);
1452 Error
*local_err
= NULL
;
1455 * `pnum` holds the number of bytes after offset that shares the same
1456 * allocation status as the byte at offset. If `pnum` is different from
1457 * `bytes`, we should check the allocation status of the next range and
1458 * continue this until all bytes have been checked.
1463 ret
= bdrv_block_status(bs
, offset
, bytes
, &pnum
, NULL
, NULL
);
1465 error_setg_errno(&local_err
, -ret
, "unable to get block status");
1466 error_report_err(local_err
);
1468 return NVME_INTERNAL_DEV_ERROR
;
1471 zeroed
= !!(ret
& BDRV_BLOCK_ZERO
);
1473 trace_pci_nvme_block_status(offset
, bytes
, pnum
, ret
, zeroed
);
1480 } while (pnum
!= bytes
);
1482 return NVME_SUCCESS
;
1485 static void nvme_aio_err(NvmeRequest
*req
, int ret
)
1487 uint16_t status
= NVME_SUCCESS
;
1488 Error
*local_err
= NULL
;
1490 switch (req
->cmd
.opcode
) {
1492 status
= NVME_UNRECOVERED_READ
;
1494 case NVME_CMD_FLUSH
:
1495 case NVME_CMD_WRITE
:
1496 case NVME_CMD_WRITE_ZEROES
:
1497 case NVME_CMD_ZONE_APPEND
:
1498 status
= NVME_WRITE_FAULT
;
1501 status
= NVME_INTERNAL_DEV_ERROR
;
1505 trace_pci_nvme_err_aio(nvme_cid(req
), strerror(-ret
), status
);
1507 error_setg_errno(&local_err
, -ret
, "aio failed");
1508 error_report_err(local_err
);
1511 * Set the command status code to the first encountered error but allow a
1512 * subsequent Internal Device Error to trump it.
1514 if (req
->status
&& status
!= NVME_INTERNAL_DEV_ERROR
) {
1518 req
->status
= status
;
1521 static inline uint32_t nvme_zone_idx(NvmeNamespace
*ns
, uint64_t slba
)
1523 return ns
->zone_size_log2
> 0 ? slba
>> ns
->zone_size_log2
:
1524 slba
/ ns
->zone_size
;
1527 static inline NvmeZone
*nvme_get_zone_by_slba(NvmeNamespace
*ns
, uint64_t slba
)
1529 uint32_t zone_idx
= nvme_zone_idx(ns
, slba
);
1531 assert(zone_idx
< ns
->num_zones
);
1532 return &ns
->zone_array
[zone_idx
];
1535 static uint16_t nvme_check_zone_state_for_write(NvmeZone
*zone
)
1537 uint64_t zslba
= zone
->d
.zslba
;
1539 switch (nvme_get_zone_state(zone
)) {
1540 case NVME_ZONE_STATE_EMPTY
:
1541 case NVME_ZONE_STATE_IMPLICITLY_OPEN
:
1542 case NVME_ZONE_STATE_EXPLICITLY_OPEN
:
1543 case NVME_ZONE_STATE_CLOSED
:
1544 return NVME_SUCCESS
;
1545 case NVME_ZONE_STATE_FULL
:
1546 trace_pci_nvme_err_zone_is_full(zslba
);
1547 return NVME_ZONE_FULL
;
1548 case NVME_ZONE_STATE_OFFLINE
:
1549 trace_pci_nvme_err_zone_is_offline(zslba
);
1550 return NVME_ZONE_OFFLINE
;
1551 case NVME_ZONE_STATE_READ_ONLY
:
1552 trace_pci_nvme_err_zone_is_read_only(zslba
);
1553 return NVME_ZONE_READ_ONLY
;
1558 return NVME_INTERNAL_DEV_ERROR
;
1561 static uint16_t nvme_check_zone_write(NvmeNamespace
*ns
, NvmeZone
*zone
,
1562 uint64_t slba
, uint32_t nlb
)
1564 uint64_t zcap
= nvme_zone_wr_boundary(zone
);
1567 status
= nvme_check_zone_state_for_write(zone
);
1572 if (unlikely(slba
!= zone
->w_ptr
)) {
1573 trace_pci_nvme_err_write_not_at_wp(slba
, zone
->d
.zslba
, zone
->w_ptr
);
1574 return NVME_ZONE_INVALID_WRITE
;
1577 if (unlikely((slba
+ nlb
) > zcap
)) {
1578 trace_pci_nvme_err_zone_boundary(slba
, nlb
, zcap
);
1579 return NVME_ZONE_BOUNDARY_ERROR
;
1582 return NVME_SUCCESS
;
1585 static uint16_t nvme_check_zone_state_for_read(NvmeZone
*zone
)
1587 switch (nvme_get_zone_state(zone
)) {
1588 case NVME_ZONE_STATE_EMPTY
:
1589 case NVME_ZONE_STATE_IMPLICITLY_OPEN
:
1590 case NVME_ZONE_STATE_EXPLICITLY_OPEN
:
1591 case NVME_ZONE_STATE_FULL
:
1592 case NVME_ZONE_STATE_CLOSED
:
1593 case NVME_ZONE_STATE_READ_ONLY
:
1594 return NVME_SUCCESS
;
1595 case NVME_ZONE_STATE_OFFLINE
:
1596 trace_pci_nvme_err_zone_is_offline(zone
->d
.zslba
);
1597 return NVME_ZONE_OFFLINE
;
1602 return NVME_INTERNAL_DEV_ERROR
;
1605 static uint16_t nvme_check_zone_read(NvmeNamespace
*ns
, uint64_t slba
,
1608 NvmeZone
*zone
= nvme_get_zone_by_slba(ns
, slba
);
1609 uint64_t bndry
= nvme_zone_rd_boundary(ns
, zone
);
1610 uint64_t end
= slba
+ nlb
;
1613 status
= nvme_check_zone_state_for_read(zone
);
1616 } else if (unlikely(end
> bndry
)) {
1617 if (!ns
->params
.cross_zone_read
) {
1618 status
= NVME_ZONE_BOUNDARY_ERROR
;
1621 * Read across zone boundary - check that all subsequent
1622 * zones that are being read have an appropriate state.
1626 status
= nvme_check_zone_state_for_read(zone
);
1630 } while (end
> nvme_zone_rd_boundary(ns
, zone
));
1637 static uint16_t nvme_zrm_finish(NvmeNamespace
*ns
, NvmeZone
*zone
)
1639 switch (nvme_get_zone_state(zone
)) {
1640 case NVME_ZONE_STATE_FULL
:
1641 return NVME_SUCCESS
;
1643 case NVME_ZONE_STATE_IMPLICITLY_OPEN
:
1644 case NVME_ZONE_STATE_EXPLICITLY_OPEN
:
1645 nvme_aor_dec_open(ns
);
1647 case NVME_ZONE_STATE_CLOSED
:
1648 nvme_aor_dec_active(ns
);
1650 case NVME_ZONE_STATE_EMPTY
:
1651 nvme_assign_zone_state(ns
, zone
, NVME_ZONE_STATE_FULL
);
1652 return NVME_SUCCESS
;
1655 return NVME_ZONE_INVAL_TRANSITION
;
1659 static uint16_t nvme_zrm_close(NvmeNamespace
*ns
, NvmeZone
*zone
)
1661 switch (nvme_get_zone_state(zone
)) {
1662 case NVME_ZONE_STATE_EXPLICITLY_OPEN
:
1663 case NVME_ZONE_STATE_IMPLICITLY_OPEN
:
1664 nvme_aor_dec_open(ns
);
1665 nvme_assign_zone_state(ns
, zone
, NVME_ZONE_STATE_CLOSED
);
1667 case NVME_ZONE_STATE_CLOSED
:
1668 return NVME_SUCCESS
;
1671 return NVME_ZONE_INVAL_TRANSITION
;
1675 static void nvme_zrm_auto_transition_zone(NvmeNamespace
*ns
)
1679 if (ns
->params
.max_open_zones
&&
1680 ns
->nr_open_zones
== ns
->params
.max_open_zones
) {
1681 zone
= QTAILQ_FIRST(&ns
->imp_open_zones
);
1684 * Automatically close this implicitly open zone.
1686 QTAILQ_REMOVE(&ns
->imp_open_zones
, zone
, entry
);
1687 nvme_zrm_close(ns
, zone
);
1693 NVME_ZRM_AUTO
= 1 << 0,
1696 static uint16_t nvme_zrm_open_flags(NvmeNamespace
*ns
, NvmeZone
*zone
,
1702 switch (nvme_get_zone_state(zone
)) {
1703 case NVME_ZONE_STATE_EMPTY
:
1708 case NVME_ZONE_STATE_CLOSED
:
1709 nvme_zrm_auto_transition_zone(ns
);
1710 status
= nvme_aor_check(ns
, act
, 1);
1716 nvme_aor_inc_active(ns
);
1719 nvme_aor_inc_open(ns
);
1721 if (flags
& NVME_ZRM_AUTO
) {
1722 nvme_assign_zone_state(ns
, zone
, NVME_ZONE_STATE_IMPLICITLY_OPEN
);
1723 return NVME_SUCCESS
;
1728 case NVME_ZONE_STATE_IMPLICITLY_OPEN
:
1729 if (flags
& NVME_ZRM_AUTO
) {
1730 return NVME_SUCCESS
;
1733 nvme_assign_zone_state(ns
, zone
, NVME_ZONE_STATE_EXPLICITLY_OPEN
);
1737 case NVME_ZONE_STATE_EXPLICITLY_OPEN
:
1738 return NVME_SUCCESS
;
1741 return NVME_ZONE_INVAL_TRANSITION
;
1745 static inline uint16_t nvme_zrm_auto(NvmeNamespace
*ns
, NvmeZone
*zone
)
1747 return nvme_zrm_open_flags(ns
, zone
, NVME_ZRM_AUTO
);
1750 static inline uint16_t nvme_zrm_open(NvmeNamespace
*ns
, NvmeZone
*zone
)
1752 return nvme_zrm_open_flags(ns
, zone
, 0);
1755 static void nvme_advance_zone_wp(NvmeNamespace
*ns
, NvmeZone
*zone
,
1760 if (zone
->d
.wp
== nvme_zone_wr_boundary(zone
)) {
1761 nvme_zrm_finish(ns
, zone
);
1765 static void nvme_finalize_zoned_write(NvmeNamespace
*ns
, NvmeRequest
*req
)
1767 NvmeRwCmd
*rw
= (NvmeRwCmd
*)&req
->cmd
;
1772 slba
= le64_to_cpu(rw
->slba
);
1773 nlb
= le16_to_cpu(rw
->nlb
) + 1;
1774 zone
= nvme_get_zone_by_slba(ns
, slba
);
1776 nvme_advance_zone_wp(ns
, zone
, nlb
);
1779 static inline bool nvme_is_write(NvmeRequest
*req
)
1781 NvmeRwCmd
*rw
= (NvmeRwCmd
*)&req
->cmd
;
1783 return rw
->opcode
== NVME_CMD_WRITE
||
1784 rw
->opcode
== NVME_CMD_ZONE_APPEND
||
1785 rw
->opcode
== NVME_CMD_WRITE_ZEROES
;
1788 static void nvme_misc_cb(void *opaque
, int ret
)
1790 NvmeRequest
*req
= opaque
;
1791 NvmeNamespace
*ns
= req
->ns
;
1793 BlockBackend
*blk
= ns
->blkconf
.blk
;
1794 BlockAcctCookie
*acct
= &req
->acct
;
1795 BlockAcctStats
*stats
= blk_get_stats(blk
);
1797 trace_pci_nvme_misc_cb(nvme_cid(req
), blk_name(blk
));
1800 block_acct_failed(stats
, acct
);
1801 nvme_aio_err(req
, ret
);
1803 block_acct_done(stats
, acct
);
1806 nvme_enqueue_req_completion(nvme_cq(req
), req
);
1809 void nvme_rw_complete_cb(void *opaque
, int ret
)
1811 NvmeRequest
*req
= opaque
;
1812 NvmeNamespace
*ns
= req
->ns
;
1813 BlockBackend
*blk
= ns
->blkconf
.blk
;
1814 BlockAcctCookie
*acct
= &req
->acct
;
1815 BlockAcctStats
*stats
= blk_get_stats(blk
);
1817 trace_pci_nvme_rw_complete_cb(nvme_cid(req
), blk_name(blk
));
1820 block_acct_failed(stats
, acct
);
1821 nvme_aio_err(req
, ret
);
1823 block_acct_done(stats
, acct
);
1826 if (ns
->params
.zoned
&& nvme_is_write(req
)) {
1827 nvme_finalize_zoned_write(ns
, req
);
1830 nvme_enqueue_req_completion(nvme_cq(req
), req
);
1833 static void nvme_rw_cb(void *opaque
, int ret
)
1835 NvmeRequest
*req
= opaque
;
1836 NvmeNamespace
*ns
= req
->ns
;
1838 BlockBackend
*blk
= ns
->blkconf
.blk
;
1840 trace_pci_nvme_rw_cb(nvme_cid(req
), blk_name(blk
));
1846 if (nvme_msize(ns
)) {
1847 NvmeRwCmd
*rw
= (NvmeRwCmd
*)&req
->cmd
;
1848 uint64_t slba
= le64_to_cpu(rw
->slba
);
1849 uint32_t nlb
= (uint32_t)le16_to_cpu(rw
->nlb
) + 1;
1850 uint64_t offset
= ns
->mdata_offset
+ nvme_m2b(ns
, slba
);
1852 if (req
->cmd
.opcode
== NVME_CMD_WRITE_ZEROES
) {
1853 size_t mlen
= nvme_m2b(ns
, nlb
);
1855 req
->aiocb
= blk_aio_pwrite_zeroes(blk
, offset
, mlen
,
1857 nvme_rw_complete_cb
, req
);
1861 if (nvme_ns_ext(ns
) || req
->cmd
.mptr
) {
1864 nvme_sg_unmap(&req
->sg
);
1865 status
= nvme_map_mdata(nvme_ctrl(req
), nlb
, req
);
1871 if (req
->cmd
.opcode
== NVME_CMD_READ
) {
1872 return nvme_blk_read(blk
, offset
, nvme_rw_complete_cb
, req
);
1875 return nvme_blk_write(blk
, offset
, nvme_rw_complete_cb
, req
);
1880 nvme_rw_complete_cb(req
, ret
);
1883 struct nvme_aio_format_ctx
{
1887 /* number of outstanding write zeroes for this namespace */
1891 static void nvme_aio_format_cb(void *opaque
, int ret
)
1893 struct nvme_aio_format_ctx
*ctx
= opaque
;
1894 NvmeRequest
*req
= ctx
->req
;
1895 NvmeNamespace
*ns
= ctx
->ns
;
1896 uintptr_t *num_formats
= (uintptr_t *)&req
->opaque
;
1897 int *count
= ctx
->count
;
1902 nvme_aio_err(req
, ret
);
1912 if (--(*num_formats
)) {
1916 nvme_enqueue_req_completion(nvme_cq(req
), req
);
1919 struct nvme_aio_flush_ctx
{
1922 BlockAcctCookie acct
;
1925 static void nvme_aio_flush_cb(void *opaque
, int ret
)
1927 struct nvme_aio_flush_ctx
*ctx
= opaque
;
1928 NvmeRequest
*req
= ctx
->req
;
1929 uintptr_t *num_flushes
= (uintptr_t *)&req
->opaque
;
1931 BlockBackend
*blk
= ctx
->ns
->blkconf
.blk
;
1932 BlockAcctCookie
*acct
= &ctx
->acct
;
1933 BlockAcctStats
*stats
= blk_get_stats(blk
);
1935 trace_pci_nvme_aio_flush_cb(nvme_cid(req
), blk_name(blk
));
1938 block_acct_done(stats
, acct
);
1940 block_acct_failed(stats
, acct
);
1941 nvme_aio_err(req
, ret
);
1951 nvme_enqueue_req_completion(nvme_cq(req
), req
);
1954 static void nvme_verify_cb(void *opaque
, int ret
)
1956 NvmeBounceContext
*ctx
= opaque
;
1957 NvmeRequest
*req
= ctx
->req
;
1958 NvmeNamespace
*ns
= req
->ns
;
1959 BlockBackend
*blk
= ns
->blkconf
.blk
;
1960 BlockAcctCookie
*acct
= &req
->acct
;
1961 BlockAcctStats
*stats
= blk_get_stats(blk
);
1962 NvmeRwCmd
*rw
= (NvmeRwCmd
*)&req
->cmd
;
1963 uint64_t slba
= le64_to_cpu(rw
->slba
);
1964 uint16_t ctrl
= le16_to_cpu(rw
->control
);
1965 uint16_t apptag
= le16_to_cpu(rw
->apptag
);
1966 uint16_t appmask
= le16_to_cpu(rw
->appmask
);
1967 uint32_t reftag
= le32_to_cpu(rw
->reftag
);
1970 trace_pci_nvme_verify_cb(nvme_cid(req
), NVME_RW_PRINFO(ctrl
), apptag
,
1974 block_acct_failed(stats
, acct
);
1975 nvme_aio_err(req
, ret
);
1979 block_acct_done(stats
, acct
);
1981 if (NVME_ID_NS_DPS_TYPE(ns
->id_ns
.dps
)) {
1982 status
= nvme_dif_mangle_mdata(ns
, ctx
->mdata
.bounce
,
1983 ctx
->mdata
.iov
.size
, slba
);
1985 req
->status
= status
;
1989 req
->status
= nvme_dif_check(ns
, ctx
->data
.bounce
, ctx
->data
.iov
.size
,
1990 ctx
->mdata
.bounce
, ctx
->mdata
.iov
.size
,
1991 ctrl
, slba
, apptag
, appmask
, reftag
);
1995 qemu_iovec_destroy(&ctx
->data
.iov
);
1996 g_free(ctx
->data
.bounce
);
1998 qemu_iovec_destroy(&ctx
->mdata
.iov
);
1999 g_free(ctx
->mdata
.bounce
);
2003 nvme_enqueue_req_completion(nvme_cq(req
), req
);
2007 static void nvme_verify_mdata_in_cb(void *opaque
, int ret
)
2009 NvmeBounceContext
*ctx
= opaque
;
2010 NvmeRequest
*req
= ctx
->req
;
2011 NvmeNamespace
*ns
= req
->ns
;
2012 NvmeRwCmd
*rw
= (NvmeRwCmd
*)&req
->cmd
;
2013 uint64_t slba
= le64_to_cpu(rw
->slba
);
2014 uint32_t nlb
= le16_to_cpu(rw
->nlb
) + 1;
2015 size_t mlen
= nvme_m2b(ns
, nlb
);
2016 uint64_t offset
= ns
->mdata_offset
+ nvme_m2b(ns
, slba
);
2017 BlockBackend
*blk
= ns
->blkconf
.blk
;
2019 trace_pci_nvme_verify_mdata_in_cb(nvme_cid(req
), blk_name(blk
));
2025 ctx
->mdata
.bounce
= g_malloc(mlen
);
2027 qemu_iovec_reset(&ctx
->mdata
.iov
);
2028 qemu_iovec_add(&ctx
->mdata
.iov
, ctx
->mdata
.bounce
, mlen
);
2030 req
->aiocb
= blk_aio_preadv(blk
, offset
, &ctx
->mdata
.iov
, 0,
2031 nvme_verify_cb
, ctx
);
2035 nvme_verify_cb(ctx
, ret
);
2038 static void nvme_aio_discard_cb(void *opaque
, int ret
)
2040 NvmeRequest
*req
= opaque
;
2041 uintptr_t *discards
= (uintptr_t *)&req
->opaque
;
2043 trace_pci_nvme_aio_discard_cb(nvme_cid(req
));
2046 nvme_aio_err(req
, ret
);
2055 nvme_enqueue_req_completion(nvme_cq(req
), req
);
2058 struct nvme_zone_reset_ctx
{
2063 static void nvme_aio_zone_reset_complete_cb(void *opaque
, int ret
)
2065 struct nvme_zone_reset_ctx
*ctx
= opaque
;
2066 NvmeRequest
*req
= ctx
->req
;
2067 NvmeNamespace
*ns
= req
->ns
;
2068 NvmeZone
*zone
= ctx
->zone
;
2069 uintptr_t *resets
= (uintptr_t *)&req
->opaque
;
2072 nvme_aio_err(req
, ret
);
2076 switch (nvme_get_zone_state(zone
)) {
2077 case NVME_ZONE_STATE_EXPLICITLY_OPEN
:
2078 case NVME_ZONE_STATE_IMPLICITLY_OPEN
:
2079 nvme_aor_dec_open(ns
);
2081 case NVME_ZONE_STATE_CLOSED
:
2082 nvme_aor_dec_active(ns
);
2084 case NVME_ZONE_STATE_FULL
:
2085 zone
->w_ptr
= zone
->d
.zslba
;
2086 zone
->d
.wp
= zone
->w_ptr
;
2087 nvme_assign_zone_state(ns
, zone
, NVME_ZONE_STATE_EMPTY
);
2102 nvme_enqueue_req_completion(nvme_cq(req
), req
);
2105 static void nvme_aio_zone_reset_cb(void *opaque
, int ret
)
2107 struct nvme_zone_reset_ctx
*ctx
= opaque
;
2108 NvmeRequest
*req
= ctx
->req
;
2109 NvmeNamespace
*ns
= req
->ns
;
2110 NvmeZone
*zone
= ctx
->zone
;
2112 trace_pci_nvme_aio_zone_reset_cb(nvme_cid(req
), zone
->d
.zslba
);
2118 if (nvme_msize(ns
)) {
2119 int64_t offset
= ns
->mdata_offset
+ nvme_m2b(ns
, zone
->d
.zslba
);
2121 blk_aio_pwrite_zeroes(ns
->blkconf
.blk
, offset
,
2122 nvme_m2b(ns
, ns
->zone_size
), BDRV_REQ_MAY_UNMAP
,
2123 nvme_aio_zone_reset_complete_cb
, ctx
);
2128 nvme_aio_zone_reset_complete_cb(opaque
, ret
);
2131 struct nvme_copy_ctx
{
2136 NvmeCopySourceRange
*ranges
;
2139 struct nvme_copy_in_ctx
{
2142 NvmeCopySourceRange
*range
;
2145 static void nvme_copy_complete_cb(void *opaque
, int ret
)
2147 NvmeRequest
*req
= opaque
;
2148 NvmeNamespace
*ns
= req
->ns
;
2149 struct nvme_copy_ctx
*ctx
= req
->opaque
;
2152 block_acct_failed(blk_get_stats(ns
->blkconf
.blk
), &req
->acct
);
2153 nvme_aio_err(req
, ret
);
2157 block_acct_done(blk_get_stats(ns
->blkconf
.blk
), &req
->acct
);
2160 if (ns
->params
.zoned
) {
2161 NvmeCopyCmd
*copy
= (NvmeCopyCmd
*)&req
->cmd
;
2162 uint64_t sdlba
= le64_to_cpu(copy
->sdlba
);
2163 NvmeZone
*zone
= nvme_get_zone_by_slba(ns
, sdlba
);
2165 nvme_advance_zone_wp(ns
, zone
, ctx
->nlb
);
2168 g_free(ctx
->bounce
);
2169 g_free(ctx
->mbounce
);
2172 nvme_enqueue_req_completion(nvme_cq(req
), req
);
2175 static void nvme_copy_cb(void *opaque
, int ret
)
2177 NvmeRequest
*req
= opaque
;
2178 NvmeNamespace
*ns
= req
->ns
;
2179 struct nvme_copy_ctx
*ctx
= req
->opaque
;
2181 trace_pci_nvme_copy_cb(nvme_cid(req
));
2187 if (nvme_msize(ns
)) {
2188 NvmeCopyCmd
*copy
= (NvmeCopyCmd
*)&req
->cmd
;
2189 uint64_t sdlba
= le64_to_cpu(copy
->sdlba
);
2190 int64_t offset
= ns
->mdata_offset
+ nvme_m2b(ns
, sdlba
);
2192 qemu_iovec_reset(&req
->sg
.iov
);
2193 qemu_iovec_add(&req
->sg
.iov
, ctx
->mbounce
, nvme_m2b(ns
, ctx
->nlb
));
2195 req
->aiocb
= blk_aio_pwritev(ns
->blkconf
.blk
, offset
, &req
->sg
.iov
, 0,
2196 nvme_copy_complete_cb
, req
);
2201 nvme_copy_complete_cb(opaque
, ret
);
2204 static void nvme_copy_in_complete(NvmeRequest
*req
)
2206 NvmeNamespace
*ns
= req
->ns
;
2207 NvmeCopyCmd
*copy
= (NvmeCopyCmd
*)&req
->cmd
;
2208 struct nvme_copy_ctx
*ctx
= req
->opaque
;
2209 uint64_t sdlba
= le64_to_cpu(copy
->sdlba
);
2212 trace_pci_nvme_copy_in_complete(nvme_cid(req
));
2214 block_acct_done(blk_get_stats(ns
->blkconf
.blk
), &req
->acct
);
2216 if (NVME_ID_NS_DPS_TYPE(ns
->id_ns
.dps
)) {
2217 uint16_t prinfor
= (copy
->control
[0] >> 4) & 0xf;
2218 uint16_t prinfow
= (copy
->control
[2] >> 2) & 0xf;
2219 uint16_t nr
= copy
->nr
+ 1;
2220 NvmeCopySourceRange
*range
;
2223 uint16_t apptag
, appmask
;
2225 uint8_t *buf
= ctx
->bounce
, *mbuf
= ctx
->mbounce
;
2230 * The dif helpers expects prinfo to be similar to the control field of
2231 * the NvmeRwCmd, so shift by 10 to fake it.
2233 prinfor
= prinfor
<< 10;
2234 prinfow
= prinfow
<< 10;
2236 for (i
= 0; i
< nr
; i
++) {
2237 range
= &ctx
->ranges
[i
];
2238 slba
= le64_to_cpu(range
->slba
);
2239 nlb
= le16_to_cpu(range
->nlb
) + 1;
2240 len
= nvme_l2b(ns
, nlb
);
2241 mlen
= nvme_m2b(ns
, nlb
);
2242 apptag
= le16_to_cpu(range
->apptag
);
2243 appmask
= le16_to_cpu(range
->appmask
);
2244 reftag
= le32_to_cpu(range
->reftag
);
2246 status
= nvme_dif_check(ns
, buf
, len
, mbuf
, mlen
, prinfor
, slba
,
2247 apptag
, appmask
, reftag
);
2256 apptag
= le16_to_cpu(copy
->apptag
);
2257 appmask
= le16_to_cpu(copy
->appmask
);
2258 reftag
= le32_to_cpu(copy
->reftag
);
2260 if (prinfow
& NVME_RW_PRINFO_PRACT
) {
2261 size_t len
= nvme_l2b(ns
, ctx
->nlb
);
2262 size_t mlen
= nvme_m2b(ns
, ctx
->nlb
);
2264 status
= nvme_check_prinfo(ns
, prinfow
, sdlba
, reftag
);
2269 nvme_dif_pract_generate_dif(ns
, ctx
->bounce
, len
, ctx
->mbounce
,
2270 mlen
, apptag
, reftag
);
2272 status
= nvme_dif_check(ns
, ctx
->bounce
, len
, ctx
->mbounce
, mlen
,
2273 prinfow
, sdlba
, apptag
, appmask
, reftag
);
2280 status
= nvme_check_bounds(ns
, sdlba
, ctx
->nlb
);
2285 if (ns
->params
.zoned
) {
2286 NvmeZone
*zone
= nvme_get_zone_by_slba(ns
, sdlba
);
2288 status
= nvme_check_zone_write(ns
, zone
, sdlba
, ctx
->nlb
);
2293 status
= nvme_zrm_auto(ns
, zone
);
2298 zone
->w_ptr
+= ctx
->nlb
;
2301 qemu_iovec_init(&req
->sg
.iov
, 1);
2302 qemu_iovec_add(&req
->sg
.iov
, ctx
->bounce
, nvme_l2b(ns
, ctx
->nlb
));
2304 block_acct_start(blk_get_stats(ns
->blkconf
.blk
), &req
->acct
, 0,
2307 req
->aiocb
= blk_aio_pwritev(ns
->blkconf
.blk
, nvme_l2b(ns
, sdlba
),
2308 &req
->sg
.iov
, 0, nvme_copy_cb
, req
);
2313 req
->status
= status
;
2315 g_free(ctx
->bounce
);
2318 nvme_enqueue_req_completion(nvme_cq(req
), req
);
2321 static void nvme_aio_copy_in_cb(void *opaque
, int ret
)
2323 struct nvme_copy_in_ctx
*in_ctx
= opaque
;
2324 NvmeRequest
*req
= in_ctx
->req
;
2325 NvmeNamespace
*ns
= req
->ns
;
2326 struct nvme_copy_ctx
*ctx
= req
->opaque
;
2328 qemu_iovec_destroy(&in_ctx
->iov
);
2331 trace_pci_nvme_aio_copy_in_cb(nvme_cid(req
));
2334 nvme_aio_err(req
, ret
);
2344 block_acct_failed(blk_get_stats(ns
->blkconf
.blk
), &req
->acct
);
2346 g_free(ctx
->bounce
);
2347 g_free(ctx
->mbounce
);
2350 nvme_enqueue_req_completion(nvme_cq(req
), req
);
2355 nvme_copy_in_complete(req
);
2358 struct nvme_compare_ctx
{
2370 static void nvme_compare_mdata_cb(void *opaque
, int ret
)
2372 NvmeRequest
*req
= opaque
;
2373 NvmeNamespace
*ns
= req
->ns
;
2374 NvmeCtrl
*n
= nvme_ctrl(req
);
2375 NvmeRwCmd
*rw
= (NvmeRwCmd
*)&req
->cmd
;
2376 uint16_t ctrl
= le16_to_cpu(rw
->control
);
2377 uint16_t apptag
= le16_to_cpu(rw
->apptag
);
2378 uint16_t appmask
= le16_to_cpu(rw
->appmask
);
2379 uint32_t reftag
= le32_to_cpu(rw
->reftag
);
2380 struct nvme_compare_ctx
*ctx
= req
->opaque
;
2381 g_autofree
uint8_t *buf
= NULL
;
2382 BlockBackend
*blk
= ns
->blkconf
.blk
;
2383 BlockAcctCookie
*acct
= &req
->acct
;
2384 BlockAcctStats
*stats
= blk_get_stats(blk
);
2385 uint16_t status
= NVME_SUCCESS
;
2387 trace_pci_nvme_compare_mdata_cb(nvme_cid(req
));
2390 block_acct_failed(stats
, acct
);
2391 nvme_aio_err(req
, ret
);
2395 buf
= g_malloc(ctx
->mdata
.iov
.size
);
2397 status
= nvme_bounce_mdata(n
, buf
, ctx
->mdata
.iov
.size
,
2398 NVME_TX_DIRECTION_TO_DEVICE
, req
);
2400 req
->status
= status
;
2404 if (NVME_ID_NS_DPS_TYPE(ns
->id_ns
.dps
)) {
2405 uint64_t slba
= le64_to_cpu(rw
->slba
);
2407 uint8_t *mbufp
= ctx
->mdata
.bounce
;
2408 uint8_t *end
= mbufp
+ ctx
->mdata
.iov
.size
;
2409 size_t msize
= nvme_msize(ns
);
2412 status
= nvme_dif_check(ns
, ctx
->data
.bounce
, ctx
->data
.iov
.size
,
2413 ctx
->mdata
.bounce
, ctx
->mdata
.iov
.size
, ctrl
,
2414 slba
, apptag
, appmask
, reftag
);
2416 req
->status
= status
;
2421 * When formatted with protection information, do not compare the DIF
2424 if (!(ns
->id_ns
.dps
& NVME_ID_NS_DPS_FIRST_EIGHT
)) {
2425 pil
= nvme_msize(ns
) - sizeof(NvmeDifTuple
);
2428 for (bufp
= buf
; mbufp
< end
; bufp
+= msize
, mbufp
+= msize
) {
2429 if (memcmp(bufp
+ pil
, mbufp
+ pil
, msize
- pil
)) {
2430 req
->status
= NVME_CMP_FAILURE
;
2438 if (memcmp(buf
, ctx
->mdata
.bounce
, ctx
->mdata
.iov
.size
)) {
2439 req
->status
= NVME_CMP_FAILURE
;
2443 block_acct_done(stats
, acct
);
2446 qemu_iovec_destroy(&ctx
->data
.iov
);
2447 g_free(ctx
->data
.bounce
);
2449 qemu_iovec_destroy(&ctx
->mdata
.iov
);
2450 g_free(ctx
->mdata
.bounce
);
2454 nvme_enqueue_req_completion(nvme_cq(req
), req
);
2457 static void nvme_compare_data_cb(void *opaque
, int ret
)
2459 NvmeRequest
*req
= opaque
;
2460 NvmeCtrl
*n
= nvme_ctrl(req
);
2461 NvmeNamespace
*ns
= req
->ns
;
2462 BlockBackend
*blk
= ns
->blkconf
.blk
;
2463 BlockAcctCookie
*acct
= &req
->acct
;
2464 BlockAcctStats
*stats
= blk_get_stats(blk
);
2466 struct nvme_compare_ctx
*ctx
= req
->opaque
;
2467 g_autofree
uint8_t *buf
= NULL
;
2470 trace_pci_nvme_compare_data_cb(nvme_cid(req
));
2473 block_acct_failed(stats
, acct
);
2474 nvme_aio_err(req
, ret
);
2478 buf
= g_malloc(ctx
->data
.iov
.size
);
2480 status
= nvme_bounce_data(n
, buf
, ctx
->data
.iov
.size
,
2481 NVME_TX_DIRECTION_TO_DEVICE
, req
);
2483 req
->status
= status
;
2487 if (memcmp(buf
, ctx
->data
.bounce
, ctx
->data
.iov
.size
)) {
2488 req
->status
= NVME_CMP_FAILURE
;
2492 if (nvme_msize(ns
)) {
2493 NvmeRwCmd
*rw
= (NvmeRwCmd
*)&req
->cmd
;
2494 uint64_t slba
= le64_to_cpu(rw
->slba
);
2495 uint32_t nlb
= le16_to_cpu(rw
->nlb
) + 1;
2496 size_t mlen
= nvme_m2b(ns
, nlb
);
2497 uint64_t offset
= ns
->mdata_offset
+ nvme_m2b(ns
, slba
);
2499 ctx
->mdata
.bounce
= g_malloc(mlen
);
2501 qemu_iovec_init(&ctx
->mdata
.iov
, 1);
2502 qemu_iovec_add(&ctx
->mdata
.iov
, ctx
->mdata
.bounce
, mlen
);
2504 req
->aiocb
= blk_aio_preadv(blk
, offset
, &ctx
->mdata
.iov
, 0,
2505 nvme_compare_mdata_cb
, req
);
2509 block_acct_done(stats
, acct
);
2512 qemu_iovec_destroy(&ctx
->data
.iov
);
2513 g_free(ctx
->data
.bounce
);
2516 nvme_enqueue_req_completion(nvme_cq(req
), req
);
2519 static uint16_t nvme_dsm(NvmeCtrl
*n
, NvmeRequest
*req
)
2521 NvmeNamespace
*ns
= req
->ns
;
2522 NvmeDsmCmd
*dsm
= (NvmeDsmCmd
*) &req
->cmd
;
2524 uint32_t attr
= le32_to_cpu(dsm
->attributes
);
2525 uint32_t nr
= (le32_to_cpu(dsm
->nr
) & 0xff) + 1;
2527 uint16_t status
= NVME_SUCCESS
;
2529 trace_pci_nvme_dsm(nvme_cid(req
), nvme_nsid(ns
), nr
, attr
);
2531 if (attr
& NVME_DSMGMT_AD
) {
2534 NvmeDsmRange range
[nr
];
2535 uintptr_t *discards
= (uintptr_t *)&req
->opaque
;
2537 status
= nvme_h2c(n
, (uint8_t *)range
, sizeof(range
), req
);
2543 * AIO callbacks may be called immediately, so initialize discards to 1
2544 * to make sure the the callback does not complete the request before
2545 * all discards have been issued.
2549 for (int i
= 0; i
< nr
; i
++) {
2550 uint64_t slba
= le64_to_cpu(range
[i
].slba
);
2551 uint32_t nlb
= le32_to_cpu(range
[i
].nlb
);
2553 if (nvme_check_bounds(ns
, slba
, nlb
)) {
2557 trace_pci_nvme_dsm_deallocate(nvme_cid(req
), nvme_nsid(ns
), slba
,
2560 if (nlb
> n
->dmrsl
) {
2561 trace_pci_nvme_dsm_single_range_limit_exceeded(nlb
, n
->dmrsl
);
2564 offset
= nvme_l2b(ns
, slba
);
2565 len
= nvme_l2b(ns
, nlb
);
2568 size_t bytes
= MIN(BDRV_REQUEST_MAX_BYTES
, len
);
2572 blk_aio_pdiscard(ns
->blkconf
.blk
, offset
, bytes
,
2573 nvme_aio_discard_cb
, req
);
2580 /* account for the 1-initialization */
2584 status
= NVME_NO_COMPLETE
;
2586 status
= req
->status
;
2593 static uint16_t nvme_verify(NvmeCtrl
*n
, NvmeRequest
*req
)
2595 NvmeRwCmd
*rw
= (NvmeRwCmd
*)&req
->cmd
;
2596 NvmeNamespace
*ns
= req
->ns
;
2597 BlockBackend
*blk
= ns
->blkconf
.blk
;
2598 uint64_t slba
= le64_to_cpu(rw
->slba
);
2599 uint32_t nlb
= le16_to_cpu(rw
->nlb
) + 1;
2600 size_t len
= nvme_l2b(ns
, nlb
);
2601 int64_t offset
= nvme_l2b(ns
, slba
);
2602 uint16_t ctrl
= le16_to_cpu(rw
->control
);
2603 uint32_t reftag
= le32_to_cpu(rw
->reftag
);
2604 NvmeBounceContext
*ctx
= NULL
;
2607 trace_pci_nvme_verify(nvme_cid(req
), nvme_nsid(ns
), slba
, nlb
);
2609 if (NVME_ID_NS_DPS_TYPE(ns
->id_ns
.dps
)) {
2610 status
= nvme_check_prinfo(ns
, ctrl
, slba
, reftag
);
2615 if (ctrl
& NVME_RW_PRINFO_PRACT
) {
2616 return NVME_INVALID_PROT_INFO
| NVME_DNR
;
2620 if (len
> n
->page_size
<< n
->params
.vsl
) {
2621 return NVME_INVALID_FIELD
| NVME_DNR
;
2624 status
= nvme_check_bounds(ns
, slba
, nlb
);
2629 if (NVME_ERR_REC_DULBE(ns
->features
.err_rec
)) {
2630 status
= nvme_check_dulbe(ns
, slba
, nlb
);
2636 ctx
= g_new0(NvmeBounceContext
, 1);
2639 ctx
->data
.bounce
= g_malloc(len
);
2641 qemu_iovec_init(&ctx
->data
.iov
, 1);
2642 qemu_iovec_add(&ctx
->data
.iov
, ctx
->data
.bounce
, len
);
2644 block_acct_start(blk_get_stats(blk
), &req
->acct
, ctx
->data
.iov
.size
,
2647 req
->aiocb
= blk_aio_preadv(ns
->blkconf
.blk
, offset
, &ctx
->data
.iov
, 0,
2648 nvme_verify_mdata_in_cb
, ctx
);
2649 return NVME_NO_COMPLETE
;
2652 static uint16_t nvme_copy(NvmeCtrl
*n
, NvmeRequest
*req
)
2654 NvmeNamespace
*ns
= req
->ns
;
2655 NvmeCopyCmd
*copy
= (NvmeCopyCmd
*)&req
->cmd
;
2657 uint16_t nr
= copy
->nr
+ 1;
2658 uint8_t format
= copy
->control
[0] & 0xf;
2661 * Shift the PRINFOR/PRINFOW values by 10 to allow reusing the
2662 * NVME_RW_PRINFO constants.
2664 uint16_t prinfor
= ((copy
->control
[0] >> 4) & 0xf) << 10;
2665 uint16_t prinfow
= ((copy
->control
[2] >> 2) & 0xf) << 10;
2668 uint8_t *bounce
= NULL
, *bouncep
= NULL
;
2669 uint8_t *mbounce
= NULL
, *mbouncep
= NULL
;
2670 struct nvme_copy_ctx
*ctx
;
2674 trace_pci_nvme_copy(nvme_cid(req
), nvme_nsid(ns
), nr
, format
);
2676 if (NVME_ID_NS_DPS_TYPE(ns
->id_ns
.dps
) &&
2677 ((prinfor
& NVME_RW_PRINFO_PRACT
) != (prinfow
& NVME_RW_PRINFO_PRACT
))) {
2678 return NVME_INVALID_FIELD
| NVME_DNR
;
2681 if (!(n
->id_ctrl
.ocfs
& (1 << format
))) {
2682 trace_pci_nvme_err_copy_invalid_format(format
);
2683 return NVME_INVALID_FIELD
| NVME_DNR
;
2686 if (nr
> ns
->id_ns
.msrc
+ 1) {
2687 return NVME_CMD_SIZE_LIMIT
| NVME_DNR
;
2690 ctx
= g_new(struct nvme_copy_ctx
, 1);
2691 ctx
->ranges
= g_new(NvmeCopySourceRange
, nr
);
2693 status
= nvme_h2c(n
, (uint8_t *)ctx
->ranges
,
2694 nr
* sizeof(NvmeCopySourceRange
), req
);
2699 for (i
= 0; i
< nr
; i
++) {
2700 uint64_t slba
= le64_to_cpu(ctx
->ranges
[i
].slba
);
2701 uint32_t _nlb
= le16_to_cpu(ctx
->ranges
[i
].nlb
) + 1;
2703 if (_nlb
> le16_to_cpu(ns
->id_ns
.mssrl
)) {
2704 status
= NVME_CMD_SIZE_LIMIT
| NVME_DNR
;
2708 status
= nvme_check_bounds(ns
, slba
, _nlb
);
2713 if (NVME_ERR_REC_DULBE(ns
->features
.err_rec
)) {
2714 status
= nvme_check_dulbe(ns
, slba
, _nlb
);
2720 if (ns
->params
.zoned
) {
2721 status
= nvme_check_zone_read(ns
, slba
, _nlb
);
2730 if (nlb
> le32_to_cpu(ns
->id_ns
.mcl
)) {
2731 status
= NVME_CMD_SIZE_LIMIT
| NVME_DNR
;
2735 bounce
= bouncep
= g_malloc(nvme_l2b(ns
, nlb
));
2736 if (nvme_msize(ns
)) {
2737 mbounce
= mbouncep
= g_malloc(nvme_m2b(ns
, nlb
));
2740 block_acct_start(blk_get_stats(ns
->blkconf
.blk
), &req
->acct
, 0,
2743 ctx
->bounce
= bounce
;
2744 ctx
->mbounce
= mbounce
;
2750 for (i
= 0; i
< nr
; i
++) {
2751 uint64_t slba
= le64_to_cpu(ctx
->ranges
[i
].slba
);
2752 uint32_t nlb
= le16_to_cpu(ctx
->ranges
[i
].nlb
) + 1;
2754 size_t len
= nvme_l2b(ns
, nlb
);
2755 int64_t offset
= nvme_l2b(ns
, slba
);
2757 trace_pci_nvme_copy_source_range(slba
, nlb
);
2759 struct nvme_copy_in_ctx
*in_ctx
= g_new(struct nvme_copy_in_ctx
, 1);
2762 qemu_iovec_init(&in_ctx
->iov
, 1);
2763 qemu_iovec_add(&in_ctx
->iov
, bouncep
, len
);
2767 blk_aio_preadv(ns
->blkconf
.blk
, offset
, &in_ctx
->iov
, 0,
2768 nvme_aio_copy_in_cb
, in_ctx
);
2772 if (nvme_msize(ns
)) {
2773 len
= nvme_m2b(ns
, nlb
);
2774 offset
= ns
->mdata_offset
+ nvme_m2b(ns
, slba
);
2776 in_ctx
= g_new(struct nvme_copy_in_ctx
, 1);
2779 qemu_iovec_init(&in_ctx
->iov
, 1);
2780 qemu_iovec_add(&in_ctx
->iov
, mbouncep
, len
);
2784 blk_aio_preadv(ns
->blkconf
.blk
, offset
, &in_ctx
->iov
, 0,
2785 nvme_aio_copy_in_cb
, in_ctx
);
2791 /* account for the 1-initialization */
2795 nvme_copy_in_complete(req
);
2798 return NVME_NO_COMPLETE
;
2801 g_free(ctx
->ranges
);
2807 static uint16_t nvme_compare(NvmeCtrl
*n
, NvmeRequest
*req
)
2809 NvmeRwCmd
*rw
= (NvmeRwCmd
*)&req
->cmd
;
2810 NvmeNamespace
*ns
= req
->ns
;
2811 BlockBackend
*blk
= ns
->blkconf
.blk
;
2812 uint64_t slba
= le64_to_cpu(rw
->slba
);
2813 uint32_t nlb
= le16_to_cpu(rw
->nlb
) + 1;
2814 uint16_t ctrl
= le16_to_cpu(rw
->control
);
2815 size_t data_len
= nvme_l2b(ns
, nlb
);
2816 size_t len
= data_len
;
2817 int64_t offset
= nvme_l2b(ns
, slba
);
2818 struct nvme_compare_ctx
*ctx
= NULL
;
2821 trace_pci_nvme_compare(nvme_cid(req
), nvme_nsid(ns
), slba
, nlb
);
2823 if (NVME_ID_NS_DPS_TYPE(ns
->id_ns
.dps
) && (ctrl
& NVME_RW_PRINFO_PRACT
)) {
2824 return NVME_INVALID_PROT_INFO
| NVME_DNR
;
2827 if (nvme_ns_ext(ns
)) {
2828 len
+= nvme_m2b(ns
, nlb
);
2831 status
= nvme_check_mdts(n
, len
);
2836 status
= nvme_check_bounds(ns
, slba
, nlb
);
2841 if (NVME_ERR_REC_DULBE(ns
->features
.err_rec
)) {
2842 status
= nvme_check_dulbe(ns
, slba
, nlb
);
2848 status
= nvme_map_dptr(n
, &req
->sg
, len
, &req
->cmd
);
2853 ctx
= g_new(struct nvme_compare_ctx
, 1);
2854 ctx
->data
.bounce
= g_malloc(data_len
);
2858 qemu_iovec_init(&ctx
->data
.iov
, 1);
2859 qemu_iovec_add(&ctx
->data
.iov
, ctx
->data
.bounce
, data_len
);
2861 block_acct_start(blk_get_stats(blk
), &req
->acct
, data_len
,
2863 req
->aiocb
= blk_aio_preadv(blk
, offset
, &ctx
->data
.iov
, 0,
2864 nvme_compare_data_cb
, req
);
2866 return NVME_NO_COMPLETE
;
2869 static uint16_t nvme_flush(NvmeCtrl
*n
, NvmeRequest
*req
)
2871 uint32_t nsid
= le32_to_cpu(req
->cmd
.nsid
);
2872 uintptr_t *num_flushes
= (uintptr_t *)&req
->opaque
;
2874 struct nvme_aio_flush_ctx
*ctx
;
2877 trace_pci_nvme_flush(nvme_cid(req
), nsid
);
2879 if (nsid
!= NVME_NSID_BROADCAST
) {
2880 req
->ns
= nvme_ns(n
, nsid
);
2881 if (unlikely(!req
->ns
)) {
2882 return NVME_INVALID_FIELD
| NVME_DNR
;
2885 block_acct_start(blk_get_stats(req
->ns
->blkconf
.blk
), &req
->acct
, 0,
2887 req
->aiocb
= blk_aio_flush(req
->ns
->blkconf
.blk
, nvme_misc_cb
, req
);
2888 return NVME_NO_COMPLETE
;
2891 /* 1-initialize; see comment in nvme_dsm */
2894 for (int i
= 1; i
<= n
->num_namespaces
; i
++) {
2900 ctx
= g_new(struct nvme_aio_flush_ctx
, 1);
2906 block_acct_start(blk_get_stats(ns
->blkconf
.blk
), &ctx
->acct
, 0,
2908 blk_aio_flush(ns
->blkconf
.blk
, nvme_aio_flush_cb
, ctx
);
2911 /* account for the 1-initialization */
2915 status
= NVME_NO_COMPLETE
;
2917 status
= req
->status
;
2923 static uint16_t nvme_read(NvmeCtrl
*n
, NvmeRequest
*req
)
2925 NvmeRwCmd
*rw
= (NvmeRwCmd
*)&req
->cmd
;
2926 NvmeNamespace
*ns
= req
->ns
;
2927 uint64_t slba
= le64_to_cpu(rw
->slba
);
2928 uint32_t nlb
= (uint32_t)le16_to_cpu(rw
->nlb
) + 1;
2929 uint16_t ctrl
= le16_to_cpu(rw
->control
);
2930 uint64_t data_size
= nvme_l2b(ns
, nlb
);
2931 uint64_t mapped_size
= data_size
;
2932 uint64_t data_offset
;
2933 BlockBackend
*blk
= ns
->blkconf
.blk
;
2936 if (nvme_ns_ext(ns
)) {
2937 mapped_size
+= nvme_m2b(ns
, nlb
);
2939 if (NVME_ID_NS_DPS_TYPE(ns
->id_ns
.dps
)) {
2940 bool pract
= ctrl
& NVME_RW_PRINFO_PRACT
;
2942 if (pract
&& nvme_msize(ns
) == 8) {
2943 mapped_size
= data_size
;
2948 trace_pci_nvme_read(nvme_cid(req
), nvme_nsid(ns
), nlb
, mapped_size
, slba
);
2950 status
= nvme_check_mdts(n
, mapped_size
);
2955 status
= nvme_check_bounds(ns
, slba
, nlb
);
2960 if (ns
->params
.zoned
) {
2961 status
= nvme_check_zone_read(ns
, slba
, nlb
);
2963 trace_pci_nvme_err_zone_read_not_ok(slba
, nlb
, status
);
2968 if (NVME_ERR_REC_DULBE(ns
->features
.err_rec
)) {
2969 status
= nvme_check_dulbe(ns
, slba
, nlb
);
2975 if (NVME_ID_NS_DPS_TYPE(ns
->id_ns
.dps
)) {
2976 return nvme_dif_rw(n
, req
);
2979 status
= nvme_map_data(n
, nlb
, req
);
2984 data_offset
= nvme_l2b(ns
, slba
);
2986 block_acct_start(blk_get_stats(blk
), &req
->acct
, data_size
,
2988 nvme_blk_read(blk
, data_offset
, nvme_rw_cb
, req
);
2989 return NVME_NO_COMPLETE
;
2992 block_acct_invalid(blk_get_stats(blk
), BLOCK_ACCT_READ
);
2993 return status
| NVME_DNR
;
2996 static uint16_t nvme_do_write(NvmeCtrl
*n
, NvmeRequest
*req
, bool append
,
2999 NvmeRwCmd
*rw
= (NvmeRwCmd
*)&req
->cmd
;
3000 NvmeNamespace
*ns
= req
->ns
;
3001 uint64_t slba
= le64_to_cpu(rw
->slba
);
3002 uint32_t nlb
= (uint32_t)le16_to_cpu(rw
->nlb
) + 1;
3003 uint16_t ctrl
= le16_to_cpu(rw
->control
);
3004 uint64_t data_size
= nvme_l2b(ns
, nlb
);
3005 uint64_t mapped_size
= data_size
;
3006 uint64_t data_offset
;
3008 NvmeZonedResult
*res
= (NvmeZonedResult
*)&req
->cqe
;
3009 BlockBackend
*blk
= ns
->blkconf
.blk
;
3012 if (nvme_ns_ext(ns
)) {
3013 mapped_size
+= nvme_m2b(ns
, nlb
);
3015 if (NVME_ID_NS_DPS_TYPE(ns
->id_ns
.dps
)) {
3016 bool pract
= ctrl
& NVME_RW_PRINFO_PRACT
;
3018 if (pract
&& nvme_msize(ns
) == 8) {
3019 mapped_size
-= nvme_m2b(ns
, nlb
);
3024 trace_pci_nvme_write(nvme_cid(req
), nvme_io_opc_str(rw
->opcode
),
3025 nvme_nsid(ns
), nlb
, mapped_size
, slba
);
3028 status
= nvme_check_mdts(n
, mapped_size
);
3034 status
= nvme_check_bounds(ns
, slba
, nlb
);
3039 if (ns
->params
.zoned
) {
3040 zone
= nvme_get_zone_by_slba(ns
, slba
);
3043 bool piremap
= !!(ctrl
& NVME_RW_PIREMAP
);
3045 if (unlikely(slba
!= zone
->d
.zslba
)) {
3046 trace_pci_nvme_err_append_not_at_start(slba
, zone
->d
.zslba
);
3047 status
= NVME_INVALID_FIELD
;
3051 if (n
->params
.zasl
&&
3052 data_size
> (uint64_t)n
->page_size
<< n
->params
.zasl
) {
3053 trace_pci_nvme_err_zasl(data_size
);
3054 return NVME_INVALID_FIELD
| NVME_DNR
;
3058 rw
->slba
= cpu_to_le64(slba
);
3059 res
->slba
= cpu_to_le64(slba
);
3061 switch (NVME_ID_NS_DPS_TYPE(ns
->id_ns
.dps
)) {
3062 case NVME_ID_NS_DPS_TYPE_1
:
3064 return NVME_INVALID_PROT_INFO
| NVME_DNR
;
3069 case NVME_ID_NS_DPS_TYPE_2
:
3071 uint32_t reftag
= le32_to_cpu(rw
->reftag
);
3072 rw
->reftag
= cpu_to_le32(reftag
+ (slba
- zone
->d
.zslba
));
3077 case NVME_ID_NS_DPS_TYPE_3
:
3079 return NVME_INVALID_PROT_INFO
| NVME_DNR
;
3086 status
= nvme_check_zone_write(ns
, zone
, slba
, nlb
);
3091 status
= nvme_zrm_auto(ns
, zone
);
3099 data_offset
= nvme_l2b(ns
, slba
);
3101 if (NVME_ID_NS_DPS_TYPE(ns
->id_ns
.dps
)) {
3102 return nvme_dif_rw(n
, req
);
3106 status
= nvme_map_data(n
, nlb
, req
);
3111 block_acct_start(blk_get_stats(blk
), &req
->acct
, data_size
,
3113 nvme_blk_write(blk
, data_offset
, nvme_rw_cb
, req
);
3115 req
->aiocb
= blk_aio_pwrite_zeroes(blk
, data_offset
, data_size
,
3116 BDRV_REQ_MAY_UNMAP
, nvme_rw_cb
,
3120 return NVME_NO_COMPLETE
;
3123 block_acct_invalid(blk_get_stats(blk
), BLOCK_ACCT_WRITE
);
3124 return status
| NVME_DNR
;
3127 static inline uint16_t nvme_write(NvmeCtrl
*n
, NvmeRequest
*req
)
3129 return nvme_do_write(n
, req
, false, false);
3132 static inline uint16_t nvme_write_zeroes(NvmeCtrl
*n
, NvmeRequest
*req
)
3134 return nvme_do_write(n
, req
, false, true);
3137 static inline uint16_t nvme_zone_append(NvmeCtrl
*n
, NvmeRequest
*req
)
3139 return nvme_do_write(n
, req
, true, false);
3142 static uint16_t nvme_get_mgmt_zone_slba_idx(NvmeNamespace
*ns
, NvmeCmd
*c
,
3143 uint64_t *slba
, uint32_t *zone_idx
)
3145 uint32_t dw10
= le32_to_cpu(c
->cdw10
);
3146 uint32_t dw11
= le32_to_cpu(c
->cdw11
);
3148 if (!ns
->params
.zoned
) {
3149 trace_pci_nvme_err_invalid_opc(c
->opcode
);
3150 return NVME_INVALID_OPCODE
| NVME_DNR
;
3153 *slba
= ((uint64_t)dw11
) << 32 | dw10
;
3154 if (unlikely(*slba
>= ns
->id_ns
.nsze
)) {
3155 trace_pci_nvme_err_invalid_lba_range(*slba
, 0, ns
->id_ns
.nsze
);
3157 return NVME_LBA_RANGE
| NVME_DNR
;
3160 *zone_idx
= nvme_zone_idx(ns
, *slba
);
3161 assert(*zone_idx
< ns
->num_zones
);
3163 return NVME_SUCCESS
;
3166 typedef uint16_t (*op_handler_t
)(NvmeNamespace
*, NvmeZone
*, NvmeZoneState
,
3169 enum NvmeZoneProcessingMask
{
3170 NVME_PROC_CURRENT_ZONE
= 0,
3171 NVME_PROC_OPENED_ZONES
= 1 << 0,
3172 NVME_PROC_CLOSED_ZONES
= 1 << 1,
3173 NVME_PROC_READ_ONLY_ZONES
= 1 << 2,
3174 NVME_PROC_FULL_ZONES
= 1 << 3,
3177 static uint16_t nvme_open_zone(NvmeNamespace
*ns
, NvmeZone
*zone
,
3178 NvmeZoneState state
, NvmeRequest
*req
)
3180 return nvme_zrm_open(ns
, zone
);
3183 static uint16_t nvme_close_zone(NvmeNamespace
*ns
, NvmeZone
*zone
,
3184 NvmeZoneState state
, NvmeRequest
*req
)
3186 return nvme_zrm_close(ns
, zone
);
3189 static uint16_t nvme_finish_zone(NvmeNamespace
*ns
, NvmeZone
*zone
,
3190 NvmeZoneState state
, NvmeRequest
*req
)
3192 return nvme_zrm_finish(ns
, zone
);
3195 static uint16_t nvme_reset_zone(NvmeNamespace
*ns
, NvmeZone
*zone
,
3196 NvmeZoneState state
, NvmeRequest
*req
)
3198 uintptr_t *resets
= (uintptr_t *)&req
->opaque
;
3199 struct nvme_zone_reset_ctx
*ctx
;
3202 case NVME_ZONE_STATE_EMPTY
:
3203 return NVME_SUCCESS
;
3204 case NVME_ZONE_STATE_EXPLICITLY_OPEN
:
3205 case NVME_ZONE_STATE_IMPLICITLY_OPEN
:
3206 case NVME_ZONE_STATE_CLOSED
:
3207 case NVME_ZONE_STATE_FULL
:
3210 return NVME_ZONE_INVAL_TRANSITION
;
3214 * The zone reset aio callback needs to know the zone that is being reset
3215 * in order to transition the zone on completion.
3217 ctx
= g_new(struct nvme_zone_reset_ctx
, 1);
3223 blk_aio_pwrite_zeroes(ns
->blkconf
.blk
, nvme_l2b(ns
, zone
->d
.zslba
),
3224 nvme_l2b(ns
, ns
->zone_size
), BDRV_REQ_MAY_UNMAP
,
3225 nvme_aio_zone_reset_cb
, ctx
);
3227 return NVME_NO_COMPLETE
;
3230 static uint16_t nvme_offline_zone(NvmeNamespace
*ns
, NvmeZone
*zone
,
3231 NvmeZoneState state
, NvmeRequest
*req
)
3234 case NVME_ZONE_STATE_READ_ONLY
:
3235 nvme_assign_zone_state(ns
, zone
, NVME_ZONE_STATE_OFFLINE
);
3237 case NVME_ZONE_STATE_OFFLINE
:
3238 return NVME_SUCCESS
;
3240 return NVME_ZONE_INVAL_TRANSITION
;
3244 static uint16_t nvme_set_zd_ext(NvmeNamespace
*ns
, NvmeZone
*zone
)
3247 uint8_t state
= nvme_get_zone_state(zone
);
3249 if (state
== NVME_ZONE_STATE_EMPTY
) {
3250 status
= nvme_aor_check(ns
, 1, 0);
3254 nvme_aor_inc_active(ns
);
3255 zone
->d
.za
|= NVME_ZA_ZD_EXT_VALID
;
3256 nvme_assign_zone_state(ns
, zone
, NVME_ZONE_STATE_CLOSED
);
3257 return NVME_SUCCESS
;
3260 return NVME_ZONE_INVAL_TRANSITION
;
3263 static uint16_t nvme_bulk_proc_zone(NvmeNamespace
*ns
, NvmeZone
*zone
,
3264 enum NvmeZoneProcessingMask proc_mask
,
3265 op_handler_t op_hndlr
, NvmeRequest
*req
)
3267 uint16_t status
= NVME_SUCCESS
;
3268 NvmeZoneState zs
= nvme_get_zone_state(zone
);
3272 case NVME_ZONE_STATE_IMPLICITLY_OPEN
:
3273 case NVME_ZONE_STATE_EXPLICITLY_OPEN
:
3274 proc_zone
= proc_mask
& NVME_PROC_OPENED_ZONES
;
3276 case NVME_ZONE_STATE_CLOSED
:
3277 proc_zone
= proc_mask
& NVME_PROC_CLOSED_ZONES
;
3279 case NVME_ZONE_STATE_READ_ONLY
:
3280 proc_zone
= proc_mask
& NVME_PROC_READ_ONLY_ZONES
;
3282 case NVME_ZONE_STATE_FULL
:
3283 proc_zone
= proc_mask
& NVME_PROC_FULL_ZONES
;
3290 status
= op_hndlr(ns
, zone
, zs
, req
);
3296 static uint16_t nvme_do_zone_op(NvmeNamespace
*ns
, NvmeZone
*zone
,
3297 enum NvmeZoneProcessingMask proc_mask
,
3298 op_handler_t op_hndlr
, NvmeRequest
*req
)
3301 uint16_t status
= NVME_SUCCESS
;
3305 status
= op_hndlr(ns
, zone
, nvme_get_zone_state(zone
), req
);
3307 if (proc_mask
& NVME_PROC_CLOSED_ZONES
) {
3308 QTAILQ_FOREACH_SAFE(zone
, &ns
->closed_zones
, entry
, next
) {
3309 status
= nvme_bulk_proc_zone(ns
, zone
, proc_mask
, op_hndlr
,
3311 if (status
&& status
!= NVME_NO_COMPLETE
) {
3316 if (proc_mask
& NVME_PROC_OPENED_ZONES
) {
3317 QTAILQ_FOREACH_SAFE(zone
, &ns
->imp_open_zones
, entry
, next
) {
3318 status
= nvme_bulk_proc_zone(ns
, zone
, proc_mask
, op_hndlr
,
3320 if (status
&& status
!= NVME_NO_COMPLETE
) {
3325 QTAILQ_FOREACH_SAFE(zone
, &ns
->exp_open_zones
, entry
, next
) {
3326 status
= nvme_bulk_proc_zone(ns
, zone
, proc_mask
, op_hndlr
,
3328 if (status
&& status
!= NVME_NO_COMPLETE
) {
3333 if (proc_mask
& NVME_PROC_FULL_ZONES
) {
3334 QTAILQ_FOREACH_SAFE(zone
, &ns
->full_zones
, entry
, next
) {
3335 status
= nvme_bulk_proc_zone(ns
, zone
, proc_mask
, op_hndlr
,
3337 if (status
&& status
!= NVME_NO_COMPLETE
) {
3343 if (proc_mask
& NVME_PROC_READ_ONLY_ZONES
) {
3344 for (i
= 0; i
< ns
->num_zones
; i
++, zone
++) {
3345 status
= nvme_bulk_proc_zone(ns
, zone
, proc_mask
, op_hndlr
,
3347 if (status
&& status
!= NVME_NO_COMPLETE
) {
3358 static uint16_t nvme_zone_mgmt_send(NvmeCtrl
*n
, NvmeRequest
*req
)
3360 NvmeCmd
*cmd
= (NvmeCmd
*)&req
->cmd
;
3361 NvmeNamespace
*ns
= req
->ns
;
3365 uint32_t dw13
= le32_to_cpu(cmd
->cdw13
);
3367 uint32_t zone_idx
= 0;
3371 enum NvmeZoneProcessingMask proc_mask
= NVME_PROC_CURRENT_ZONE
;
3373 action
= dw13
& 0xff;
3376 req
->status
= NVME_SUCCESS
;
3379 status
= nvme_get_mgmt_zone_slba_idx(ns
, cmd
, &slba
, &zone_idx
);
3385 zone
= &ns
->zone_array
[zone_idx
];
3386 if (slba
!= zone
->d
.zslba
) {
3387 trace_pci_nvme_err_unaligned_zone_cmd(action
, slba
, zone
->d
.zslba
);
3388 return NVME_INVALID_FIELD
| NVME_DNR
;
3393 case NVME_ZONE_ACTION_OPEN
:
3395 proc_mask
= NVME_PROC_CLOSED_ZONES
;
3397 trace_pci_nvme_open_zone(slba
, zone_idx
, all
);
3398 status
= nvme_do_zone_op(ns
, zone
, proc_mask
, nvme_open_zone
, req
);
3401 case NVME_ZONE_ACTION_CLOSE
:
3403 proc_mask
= NVME_PROC_OPENED_ZONES
;
3405 trace_pci_nvme_close_zone(slba
, zone_idx
, all
);
3406 status
= nvme_do_zone_op(ns
, zone
, proc_mask
, nvme_close_zone
, req
);
3409 case NVME_ZONE_ACTION_FINISH
:
3411 proc_mask
= NVME_PROC_OPENED_ZONES
| NVME_PROC_CLOSED_ZONES
;
3413 trace_pci_nvme_finish_zone(slba
, zone_idx
, all
);
3414 status
= nvme_do_zone_op(ns
, zone
, proc_mask
, nvme_finish_zone
, req
);
3417 case NVME_ZONE_ACTION_RESET
:
3418 resets
= (uintptr_t *)&req
->opaque
;
3421 proc_mask
= NVME_PROC_OPENED_ZONES
| NVME_PROC_CLOSED_ZONES
|
3422 NVME_PROC_FULL_ZONES
;
3424 trace_pci_nvme_reset_zone(slba
, zone_idx
, all
);
3428 status
= nvme_do_zone_op(ns
, zone
, proc_mask
, nvme_reset_zone
, req
);
3432 return *resets
? NVME_NO_COMPLETE
: req
->status
;
3434 case NVME_ZONE_ACTION_OFFLINE
:
3436 proc_mask
= NVME_PROC_READ_ONLY_ZONES
;
3438 trace_pci_nvme_offline_zone(slba
, zone_idx
, all
);
3439 status
= nvme_do_zone_op(ns
, zone
, proc_mask
, nvme_offline_zone
, req
);
3442 case NVME_ZONE_ACTION_SET_ZD_EXT
:
3443 trace_pci_nvme_set_descriptor_extension(slba
, zone_idx
);
3444 if (all
|| !ns
->params
.zd_extension_size
) {
3445 return NVME_INVALID_FIELD
| NVME_DNR
;
3447 zd_ext
= nvme_get_zd_extension(ns
, zone_idx
);
3448 status
= nvme_h2c(n
, zd_ext
, ns
->params
.zd_extension_size
, req
);
3450 trace_pci_nvme_err_zd_extension_map_error(zone_idx
);
3454 status
= nvme_set_zd_ext(ns
, zone
);
3455 if (status
== NVME_SUCCESS
) {
3456 trace_pci_nvme_zd_extension_set(zone_idx
);
3462 trace_pci_nvme_err_invalid_mgmt_action(action
);
3463 status
= NVME_INVALID_FIELD
;
3466 if (status
== NVME_ZONE_INVAL_TRANSITION
) {
3467 trace_pci_nvme_err_invalid_zone_state_transition(action
, slba
,
3477 static bool nvme_zone_matches_filter(uint32_t zafs
, NvmeZone
*zl
)
3479 NvmeZoneState zs
= nvme_get_zone_state(zl
);
3482 case NVME_ZONE_REPORT_ALL
:
3484 case NVME_ZONE_REPORT_EMPTY
:
3485 return zs
== NVME_ZONE_STATE_EMPTY
;
3486 case NVME_ZONE_REPORT_IMPLICITLY_OPEN
:
3487 return zs
== NVME_ZONE_STATE_IMPLICITLY_OPEN
;
3488 case NVME_ZONE_REPORT_EXPLICITLY_OPEN
:
3489 return zs
== NVME_ZONE_STATE_EXPLICITLY_OPEN
;
3490 case NVME_ZONE_REPORT_CLOSED
:
3491 return zs
== NVME_ZONE_STATE_CLOSED
;
3492 case NVME_ZONE_REPORT_FULL
:
3493 return zs
== NVME_ZONE_STATE_FULL
;
3494 case NVME_ZONE_REPORT_READ_ONLY
:
3495 return zs
== NVME_ZONE_STATE_READ_ONLY
;
3496 case NVME_ZONE_REPORT_OFFLINE
:
3497 return zs
== NVME_ZONE_STATE_OFFLINE
;
3503 static uint16_t nvme_zone_mgmt_recv(NvmeCtrl
*n
, NvmeRequest
*req
)
3505 NvmeCmd
*cmd
= (NvmeCmd
*)&req
->cmd
;
3506 NvmeNamespace
*ns
= req
->ns
;
3507 /* cdw12 is zero-based number of dwords to return. Convert to bytes */
3508 uint32_t data_size
= (le32_to_cpu(cmd
->cdw12
) + 1) << 2;
3509 uint32_t dw13
= le32_to_cpu(cmd
->cdw13
);
3510 uint32_t zone_idx
, zra
, zrasf
, partial
;
3511 uint64_t max_zones
, nr_zones
= 0;
3516 NvmeZoneReportHeader
*header
;
3518 size_t zone_entry_sz
;
3521 req
->status
= NVME_SUCCESS
;
3523 status
= nvme_get_mgmt_zone_slba_idx(ns
, cmd
, &slba
, &zone_idx
);
3529 if (zra
!= NVME_ZONE_REPORT
&& zra
!= NVME_ZONE_REPORT_EXTENDED
) {
3530 return NVME_INVALID_FIELD
| NVME_DNR
;
3532 if (zra
== NVME_ZONE_REPORT_EXTENDED
&& !ns
->params
.zd_extension_size
) {
3533 return NVME_INVALID_FIELD
| NVME_DNR
;
3536 zrasf
= (dw13
>> 8) & 0xff;
3537 if (zrasf
> NVME_ZONE_REPORT_OFFLINE
) {
3538 return NVME_INVALID_FIELD
| NVME_DNR
;
3541 if (data_size
< sizeof(NvmeZoneReportHeader
)) {
3542 return NVME_INVALID_FIELD
| NVME_DNR
;
3545 status
= nvme_check_mdts(n
, data_size
);
3550 partial
= (dw13
>> 16) & 0x01;
3552 zone_entry_sz
= sizeof(NvmeZoneDescr
);
3553 if (zra
== NVME_ZONE_REPORT_EXTENDED
) {
3554 zone_entry_sz
+= ns
->params
.zd_extension_size
;
3557 max_zones
= (data_size
- sizeof(NvmeZoneReportHeader
)) / zone_entry_sz
;
3558 buf
= g_malloc0(data_size
);
3560 zone
= &ns
->zone_array
[zone_idx
];
3561 for (i
= zone_idx
; i
< ns
->num_zones
; i
++) {
3562 if (partial
&& nr_zones
>= max_zones
) {
3565 if (nvme_zone_matches_filter(zrasf
, zone
++)) {
3569 header
= (NvmeZoneReportHeader
*)buf
;
3570 header
->nr_zones
= cpu_to_le64(nr_zones
);
3572 buf_p
= buf
+ sizeof(NvmeZoneReportHeader
);
3573 for (; zone_idx
< ns
->num_zones
&& max_zones
> 0; zone_idx
++) {
3574 zone
= &ns
->zone_array
[zone_idx
];
3575 if (nvme_zone_matches_filter(zrasf
, zone
)) {
3576 z
= (NvmeZoneDescr
*)buf_p
;
3577 buf_p
+= sizeof(NvmeZoneDescr
);
3581 z
->zcap
= cpu_to_le64(zone
->d
.zcap
);
3582 z
->zslba
= cpu_to_le64(zone
->d
.zslba
);
3585 if (nvme_wp_is_valid(zone
)) {
3586 z
->wp
= cpu_to_le64(zone
->d
.wp
);
3588 z
->wp
= cpu_to_le64(~0ULL);
3591 if (zra
== NVME_ZONE_REPORT_EXTENDED
) {
3592 if (zone
->d
.za
& NVME_ZA_ZD_EXT_VALID
) {
3593 memcpy(buf_p
, nvme_get_zd_extension(ns
, zone_idx
),
3594 ns
->params
.zd_extension_size
);
3596 buf_p
+= ns
->params
.zd_extension_size
;
3603 status
= nvme_c2h(n
, (uint8_t *)buf
, data_size
, req
);
3610 static uint16_t nvme_io_cmd(NvmeCtrl
*n
, NvmeRequest
*req
)
3613 uint32_t nsid
= le32_to_cpu(req
->cmd
.nsid
);
3615 trace_pci_nvme_io_cmd(nvme_cid(req
), nsid
, nvme_sqid(req
),
3616 req
->cmd
.opcode
, nvme_io_opc_str(req
->cmd
.opcode
));
3618 if (!nvme_nsid_valid(n
, nsid
)) {
3619 return NVME_INVALID_NSID
| NVME_DNR
;
3623 * In the base NVM command set, Flush may apply to all namespaces
3624 * (indicated by NSID being set to FFFFFFFFh). But if that feature is used
3625 * along with TP 4056 (Namespace Types), it may be pretty screwed up.
3627 * If NSID is indeed set to FFFFFFFFh, we simply cannot associate the
3628 * opcode with a specific command since we cannot determine a unique I/O
3629 * command set. Opcode 0h could have any other meaning than something
3630 * equivalent to flushing and say it DOES have completely different
3631 * semantics in some other command set - does an NSID of FFFFFFFFh then
3632 * mean "for all namespaces, apply whatever command set specific command
3633 * that uses the 0h opcode?" Or does it mean "for all namespaces, apply
3634 * whatever command that uses the 0h opcode if, and only if, it allows NSID
3637 * Anyway (and luckily), for now, we do not care about this since the
3638 * device only supports namespace types that includes the NVM Flush command
3639 * (NVM and Zoned), so always do an NVM Flush.
3641 if (req
->cmd
.opcode
== NVME_CMD_FLUSH
) {
3642 return nvme_flush(n
, req
);
3645 ns
= nvme_ns(n
, nsid
);
3646 if (unlikely(!ns
)) {
3647 return NVME_INVALID_FIELD
| NVME_DNR
;
3650 if (!(ns
->iocs
[req
->cmd
.opcode
] & NVME_CMD_EFF_CSUPP
)) {
3651 trace_pci_nvme_err_invalid_opc(req
->cmd
.opcode
);
3652 return NVME_INVALID_OPCODE
| NVME_DNR
;
3661 switch (req
->cmd
.opcode
) {
3662 case NVME_CMD_WRITE_ZEROES
:
3663 return nvme_write_zeroes(n
, req
);
3664 case NVME_CMD_ZONE_APPEND
:
3665 return nvme_zone_append(n
, req
);
3666 case NVME_CMD_WRITE
:
3667 return nvme_write(n
, req
);
3669 return nvme_read(n
, req
);
3670 case NVME_CMD_COMPARE
:
3671 return nvme_compare(n
, req
);
3673 return nvme_dsm(n
, req
);
3674 case NVME_CMD_VERIFY
:
3675 return nvme_verify(n
, req
);
3677 return nvme_copy(n
, req
);
3678 case NVME_CMD_ZONE_MGMT_SEND
:
3679 return nvme_zone_mgmt_send(n
, req
);
3680 case NVME_CMD_ZONE_MGMT_RECV
:
3681 return nvme_zone_mgmt_recv(n
, req
);
3686 return NVME_INVALID_OPCODE
| NVME_DNR
;
3689 static void nvme_free_sq(NvmeSQueue
*sq
, NvmeCtrl
*n
)
3691 n
->sq
[sq
->sqid
] = NULL
;
3692 timer_free(sq
->timer
);
3699 static uint16_t nvme_del_sq(NvmeCtrl
*n
, NvmeRequest
*req
)
3701 NvmeDeleteQ
*c
= (NvmeDeleteQ
*)&req
->cmd
;
3702 NvmeRequest
*r
, *next
;
3705 uint16_t qid
= le16_to_cpu(c
->qid
);
3708 if (unlikely(!qid
|| nvme_check_sqid(n
, qid
))) {
3709 trace_pci_nvme_err_invalid_del_sq(qid
);
3710 return NVME_INVALID_QID
| NVME_DNR
;
3713 trace_pci_nvme_del_sq(qid
);
3716 while (!QTAILQ_EMPTY(&sq
->out_req_list
)) {
3717 r
= QTAILQ_FIRST(&sq
->out_req_list
);
3719 blk_aio_cancel(r
->aiocb
);
3724 * Drain all namespaces if there are still outstanding requests that we
3725 * could not cancel explicitly.
3727 if (!QTAILQ_EMPTY(&sq
->out_req_list
)) {
3728 for (nsid
= 1; nsid
<= NVME_MAX_NAMESPACES
; nsid
++) {
3729 NvmeNamespace
*ns
= nvme_ns(n
, nsid
);
3736 assert(QTAILQ_EMPTY(&sq
->out_req_list
));
3738 if (!nvme_check_cqid(n
, sq
->cqid
)) {
3739 cq
= n
->cq
[sq
->cqid
];
3740 QTAILQ_REMOVE(&cq
->sq_list
, sq
, entry
);
3743 QTAILQ_FOREACH_SAFE(r
, &cq
->req_list
, entry
, next
) {
3745 QTAILQ_REMOVE(&cq
->req_list
, r
, entry
);
3746 QTAILQ_INSERT_TAIL(&sq
->req_list
, r
, entry
);
3751 nvme_free_sq(sq
, n
);
3752 return NVME_SUCCESS
;
3755 static void nvme_init_sq(NvmeSQueue
*sq
, NvmeCtrl
*n
, uint64_t dma_addr
,
3756 uint16_t sqid
, uint16_t cqid
, uint16_t size
)
3762 sq
->dma_addr
= dma_addr
;
3766 sq
->head
= sq
->tail
= 0;
3767 sq
->io_req
= g_new0(NvmeRequest
, sq
->size
);
3769 QTAILQ_INIT(&sq
->req_list
);
3770 QTAILQ_INIT(&sq
->out_req_list
);
3771 for (i
= 0; i
< sq
->size
; i
++) {
3772 sq
->io_req
[i
].sq
= sq
;
3773 QTAILQ_INSERT_TAIL(&(sq
->req_list
), &sq
->io_req
[i
], entry
);
3775 sq
->timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, nvme_process_sq
, sq
);
3777 assert(n
->cq
[cqid
]);
3779 QTAILQ_INSERT_TAIL(&(cq
->sq_list
), sq
, entry
);
3783 static uint16_t nvme_create_sq(NvmeCtrl
*n
, NvmeRequest
*req
)
3786 NvmeCreateSq
*c
= (NvmeCreateSq
*)&req
->cmd
;
3788 uint16_t cqid
= le16_to_cpu(c
->cqid
);
3789 uint16_t sqid
= le16_to_cpu(c
->sqid
);
3790 uint16_t qsize
= le16_to_cpu(c
->qsize
);
3791 uint16_t qflags
= le16_to_cpu(c
->sq_flags
);
3792 uint64_t prp1
= le64_to_cpu(c
->prp1
);
3794 trace_pci_nvme_create_sq(prp1
, sqid
, cqid
, qsize
, qflags
);
3796 if (unlikely(!cqid
|| nvme_check_cqid(n
, cqid
))) {
3797 trace_pci_nvme_err_invalid_create_sq_cqid(cqid
);
3798 return NVME_INVALID_CQID
| NVME_DNR
;
3800 if (unlikely(!sqid
|| sqid
> n
->params
.max_ioqpairs
||
3801 n
->sq
[sqid
] != NULL
)) {
3802 trace_pci_nvme_err_invalid_create_sq_sqid(sqid
);
3803 return NVME_INVALID_QID
| NVME_DNR
;
3805 if (unlikely(!qsize
|| qsize
> NVME_CAP_MQES(n
->bar
.cap
))) {
3806 trace_pci_nvme_err_invalid_create_sq_size(qsize
);
3807 return NVME_MAX_QSIZE_EXCEEDED
| NVME_DNR
;
3809 if (unlikely(prp1
& (n
->page_size
- 1))) {
3810 trace_pci_nvme_err_invalid_create_sq_addr(prp1
);
3811 return NVME_INVALID_PRP_OFFSET
| NVME_DNR
;
3813 if (unlikely(!(NVME_SQ_FLAGS_PC(qflags
)))) {
3814 trace_pci_nvme_err_invalid_create_sq_qflags(NVME_SQ_FLAGS_PC(qflags
));
3815 return NVME_INVALID_FIELD
| NVME_DNR
;
3817 sq
= g_malloc0(sizeof(*sq
));
3818 nvme_init_sq(sq
, n
, prp1
, sqid
, cqid
, qsize
+ 1);
3819 return NVME_SUCCESS
;
3823 uint64_t units_read
;
3824 uint64_t units_written
;
3825 uint64_t read_commands
;
3826 uint64_t write_commands
;
3829 static void nvme_set_blk_stats(NvmeNamespace
*ns
, struct nvme_stats
*stats
)
3831 BlockAcctStats
*s
= blk_get_stats(ns
->blkconf
.blk
);
3833 stats
->units_read
+= s
->nr_bytes
[BLOCK_ACCT_READ
] >> BDRV_SECTOR_BITS
;
3834 stats
->units_written
+= s
->nr_bytes
[BLOCK_ACCT_WRITE
] >> BDRV_SECTOR_BITS
;
3835 stats
->read_commands
+= s
->nr_ops
[BLOCK_ACCT_READ
];
3836 stats
->write_commands
+= s
->nr_ops
[BLOCK_ACCT_WRITE
];
3839 static uint16_t nvme_smart_info(NvmeCtrl
*n
, uint8_t rae
, uint32_t buf_len
,
3840 uint64_t off
, NvmeRequest
*req
)
3842 uint32_t nsid
= le32_to_cpu(req
->cmd
.nsid
);
3843 struct nvme_stats stats
= { 0 };
3844 NvmeSmartLog smart
= { 0 };
3849 if (off
>= sizeof(smart
)) {
3850 return NVME_INVALID_FIELD
| NVME_DNR
;
3853 if (nsid
!= 0xffffffff) {
3854 ns
= nvme_ns(n
, nsid
);
3856 return NVME_INVALID_NSID
| NVME_DNR
;
3858 nvme_set_blk_stats(ns
, &stats
);
3862 for (i
= 1; i
<= n
->num_namespaces
; i
++) {
3867 nvme_set_blk_stats(ns
, &stats
);
3871 trans_len
= MIN(sizeof(smart
) - off
, buf_len
);
3872 smart
.critical_warning
= n
->smart_critical_warning
;
3874 smart
.data_units_read
[0] = cpu_to_le64(DIV_ROUND_UP(stats
.units_read
,
3876 smart
.data_units_written
[0] = cpu_to_le64(DIV_ROUND_UP(stats
.units_written
,
3878 smart
.host_read_commands
[0] = cpu_to_le64(stats
.read_commands
);
3879 smart
.host_write_commands
[0] = cpu_to_le64(stats
.write_commands
);
3881 smart
.temperature
= cpu_to_le16(n
->temperature
);
3883 if ((n
->temperature
>= n
->features
.temp_thresh_hi
) ||
3884 (n
->temperature
<= n
->features
.temp_thresh_low
)) {
3885 smart
.critical_warning
|= NVME_SMART_TEMPERATURE
;
3888 current_ms
= qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
);
3889 smart
.power_on_hours
[0] =
3890 cpu_to_le64((((current_ms
- n
->starttime_ms
) / 1000) / 60) / 60);
3893 nvme_clear_events(n
, NVME_AER_TYPE_SMART
);
3896 return nvme_c2h(n
, (uint8_t *) &smart
+ off
, trans_len
, req
);
3899 static uint16_t nvme_fw_log_info(NvmeCtrl
*n
, uint32_t buf_len
, uint64_t off
,
3903 NvmeFwSlotInfoLog fw_log
= {
3907 if (off
>= sizeof(fw_log
)) {
3908 return NVME_INVALID_FIELD
| NVME_DNR
;
3911 strpadcpy((char *)&fw_log
.frs1
, sizeof(fw_log
.frs1
), "1.0", ' ');
3912 trans_len
= MIN(sizeof(fw_log
) - off
, buf_len
);
3914 return nvme_c2h(n
, (uint8_t *) &fw_log
+ off
, trans_len
, req
);
3917 static uint16_t nvme_error_info(NvmeCtrl
*n
, uint8_t rae
, uint32_t buf_len
,
3918 uint64_t off
, NvmeRequest
*req
)
3921 NvmeErrorLog errlog
;
3923 if (off
>= sizeof(errlog
)) {
3924 return NVME_INVALID_FIELD
| NVME_DNR
;
3928 nvme_clear_events(n
, NVME_AER_TYPE_ERROR
);
3931 memset(&errlog
, 0x0, sizeof(errlog
));
3932 trans_len
= MIN(sizeof(errlog
) - off
, buf_len
);
3934 return nvme_c2h(n
, (uint8_t *)&errlog
, trans_len
, req
);
3937 static uint16_t nvme_changed_nslist(NvmeCtrl
*n
, uint8_t rae
, uint32_t buf_len
,
3938 uint64_t off
, NvmeRequest
*req
)
3940 uint32_t nslist
[1024];
3945 memset(nslist
, 0x0, sizeof(nslist
));
3946 trans_len
= MIN(sizeof(nslist
) - off
, buf_len
);
3948 while ((nsid
= find_first_bit(n
->changed_nsids
, NVME_CHANGED_NSID_SIZE
)) !=
3949 NVME_CHANGED_NSID_SIZE
) {
3951 * If more than 1024 namespaces, the first entry in the log page should
3952 * be set to FFFFFFFFh and the others to 0 as spec.
3954 if (i
== ARRAY_SIZE(nslist
)) {
3955 memset(nslist
, 0x0, sizeof(nslist
));
3956 nslist
[0] = 0xffffffff;
3961 clear_bit(nsid
, n
->changed_nsids
);
3965 * Remove all the remaining list entries in case returns directly due to
3966 * more than 1024 namespaces.
3968 if (nslist
[0] == 0xffffffff) {
3969 bitmap_zero(n
->changed_nsids
, NVME_CHANGED_NSID_SIZE
);
3973 nvme_clear_events(n
, NVME_AER_TYPE_NOTICE
);
3976 return nvme_c2h(n
, ((uint8_t *)nslist
) + off
, trans_len
, req
);
3979 static uint16_t nvme_cmd_effects(NvmeCtrl
*n
, uint8_t csi
, uint32_t buf_len
,
3980 uint64_t off
, NvmeRequest
*req
)
3982 NvmeEffectsLog log
= {};
3983 const uint32_t *src_iocs
= NULL
;
3986 if (off
>= sizeof(log
)) {
3987 trace_pci_nvme_err_invalid_log_page_offset(off
, sizeof(log
));
3988 return NVME_INVALID_FIELD
| NVME_DNR
;
3991 switch (NVME_CC_CSS(n
->bar
.cc
)) {
3992 case NVME_CC_CSS_NVM
:
3993 src_iocs
= nvme_cse_iocs_nvm
;
3995 case NVME_CC_CSS_ADMIN_ONLY
:
3997 case NVME_CC_CSS_CSI
:
4000 src_iocs
= nvme_cse_iocs_nvm
;
4002 case NVME_CSI_ZONED
:
4003 src_iocs
= nvme_cse_iocs_zoned
;
4008 memcpy(log
.acs
, nvme_cse_acs
, sizeof(nvme_cse_acs
));
4011 memcpy(log
.iocs
, src_iocs
, sizeof(log
.iocs
));
4014 trans_len
= MIN(sizeof(log
) - off
, buf_len
);
4016 return nvme_c2h(n
, ((uint8_t *)&log
) + off
, trans_len
, req
);
4019 static uint16_t nvme_get_log(NvmeCtrl
*n
, NvmeRequest
*req
)
4021 NvmeCmd
*cmd
= &req
->cmd
;
4023 uint32_t dw10
= le32_to_cpu(cmd
->cdw10
);
4024 uint32_t dw11
= le32_to_cpu(cmd
->cdw11
);
4025 uint32_t dw12
= le32_to_cpu(cmd
->cdw12
);
4026 uint32_t dw13
= le32_to_cpu(cmd
->cdw13
);
4027 uint8_t lid
= dw10
& 0xff;
4028 uint8_t lsp
= (dw10
>> 8) & 0xf;
4029 uint8_t rae
= (dw10
>> 15) & 0x1;
4030 uint8_t csi
= le32_to_cpu(cmd
->cdw14
) >> 24;
4031 uint32_t numdl
, numdu
;
4032 uint64_t off
, lpol
, lpou
;
4036 numdl
= (dw10
>> 16);
4037 numdu
= (dw11
& 0xffff);
4041 len
= (((numdu
<< 16) | numdl
) + 1) << 2;
4042 off
= (lpou
<< 32ULL) | lpol
;
4045 return NVME_INVALID_FIELD
| NVME_DNR
;
4048 trace_pci_nvme_get_log(nvme_cid(req
), lid
, lsp
, rae
, len
, off
);
4050 status
= nvme_check_mdts(n
, len
);
4056 case NVME_LOG_ERROR_INFO
:
4057 return nvme_error_info(n
, rae
, len
, off
, req
);
4058 case NVME_LOG_SMART_INFO
:
4059 return nvme_smart_info(n
, rae
, len
, off
, req
);
4060 case NVME_LOG_FW_SLOT_INFO
:
4061 return nvme_fw_log_info(n
, len
, off
, req
);
4062 case NVME_LOG_CHANGED_NSLIST
:
4063 return nvme_changed_nslist(n
, rae
, len
, off
, req
);
4064 case NVME_LOG_CMD_EFFECTS
:
4065 return nvme_cmd_effects(n
, csi
, len
, off
, req
);
4067 trace_pci_nvme_err_invalid_log_page(nvme_cid(req
), lid
);
4068 return NVME_INVALID_FIELD
| NVME_DNR
;
4072 static void nvme_free_cq(NvmeCQueue
*cq
, NvmeCtrl
*n
)
4074 n
->cq
[cq
->cqid
] = NULL
;
4075 timer_free(cq
->timer
);
4076 if (msix_enabled(&n
->parent_obj
)) {
4077 msix_vector_unuse(&n
->parent_obj
, cq
->vector
);
4084 static uint16_t nvme_del_cq(NvmeCtrl
*n
, NvmeRequest
*req
)
4086 NvmeDeleteQ
*c
= (NvmeDeleteQ
*)&req
->cmd
;
4088 uint16_t qid
= le16_to_cpu(c
->qid
);
4090 if (unlikely(!qid
|| nvme_check_cqid(n
, qid
))) {
4091 trace_pci_nvme_err_invalid_del_cq_cqid(qid
);
4092 return NVME_INVALID_CQID
| NVME_DNR
;
4096 if (unlikely(!QTAILQ_EMPTY(&cq
->sq_list
))) {
4097 trace_pci_nvme_err_invalid_del_cq_notempty(qid
);
4098 return NVME_INVALID_QUEUE_DEL
;
4100 nvme_irq_deassert(n
, cq
);
4101 trace_pci_nvme_del_cq(qid
);
4102 nvme_free_cq(cq
, n
);
4103 return NVME_SUCCESS
;
4106 static void nvme_init_cq(NvmeCQueue
*cq
, NvmeCtrl
*n
, uint64_t dma_addr
,
4107 uint16_t cqid
, uint16_t vector
, uint16_t size
,
4108 uint16_t irq_enabled
)
4112 if (msix_enabled(&n
->parent_obj
)) {
4113 ret
= msix_vector_use(&n
->parent_obj
, vector
);
4119 cq
->dma_addr
= dma_addr
;
4121 cq
->irq_enabled
= irq_enabled
;
4122 cq
->vector
= vector
;
4123 cq
->head
= cq
->tail
= 0;
4124 QTAILQ_INIT(&cq
->req_list
);
4125 QTAILQ_INIT(&cq
->sq_list
);
4127 cq
->timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, nvme_post_cqes
, cq
);
4130 static uint16_t nvme_create_cq(NvmeCtrl
*n
, NvmeRequest
*req
)
4133 NvmeCreateCq
*c
= (NvmeCreateCq
*)&req
->cmd
;
4134 uint16_t cqid
= le16_to_cpu(c
->cqid
);
4135 uint16_t vector
= le16_to_cpu(c
->irq_vector
);
4136 uint16_t qsize
= le16_to_cpu(c
->qsize
);
4137 uint16_t qflags
= le16_to_cpu(c
->cq_flags
);
4138 uint64_t prp1
= le64_to_cpu(c
->prp1
);
4140 trace_pci_nvme_create_cq(prp1
, cqid
, vector
, qsize
, qflags
,
4141 NVME_CQ_FLAGS_IEN(qflags
) != 0);
4143 if (unlikely(!cqid
|| cqid
> n
->params
.max_ioqpairs
||
4144 n
->cq
[cqid
] != NULL
)) {
4145 trace_pci_nvme_err_invalid_create_cq_cqid(cqid
);
4146 return NVME_INVALID_QID
| NVME_DNR
;
4148 if (unlikely(!qsize
|| qsize
> NVME_CAP_MQES(n
->bar
.cap
))) {
4149 trace_pci_nvme_err_invalid_create_cq_size(qsize
);
4150 return NVME_MAX_QSIZE_EXCEEDED
| NVME_DNR
;
4152 if (unlikely(prp1
& (n
->page_size
- 1))) {
4153 trace_pci_nvme_err_invalid_create_cq_addr(prp1
);
4154 return NVME_INVALID_PRP_OFFSET
| NVME_DNR
;
4156 if (unlikely(!msix_enabled(&n
->parent_obj
) && vector
)) {
4157 trace_pci_nvme_err_invalid_create_cq_vector(vector
);
4158 return NVME_INVALID_IRQ_VECTOR
| NVME_DNR
;
4160 if (unlikely(vector
>= n
->params
.msix_qsize
)) {
4161 trace_pci_nvme_err_invalid_create_cq_vector(vector
);
4162 return NVME_INVALID_IRQ_VECTOR
| NVME_DNR
;
4164 if (unlikely(!(NVME_CQ_FLAGS_PC(qflags
)))) {
4165 trace_pci_nvme_err_invalid_create_cq_qflags(NVME_CQ_FLAGS_PC(qflags
));
4166 return NVME_INVALID_FIELD
| NVME_DNR
;
4169 cq
= g_malloc0(sizeof(*cq
));
4170 nvme_init_cq(cq
, n
, prp1
, cqid
, vector
, qsize
+ 1,
4171 NVME_CQ_FLAGS_IEN(qflags
));
4174 * It is only required to set qs_created when creating a completion queue;
4175 * creating a submission queue without a matching completion queue will
4178 n
->qs_created
= true;
4179 return NVME_SUCCESS
;
4182 static uint16_t nvme_rpt_empty_id_struct(NvmeCtrl
*n
, NvmeRequest
*req
)
4184 uint8_t id
[NVME_IDENTIFY_DATA_SIZE
] = {};
4186 return nvme_c2h(n
, id
, sizeof(id
), req
);
4189 static inline bool nvme_csi_has_nvm_support(NvmeNamespace
*ns
)
4193 case NVME_CSI_ZONED
:
4199 static uint16_t nvme_identify_ctrl(NvmeCtrl
*n
, NvmeRequest
*req
)
4201 trace_pci_nvme_identify_ctrl();
4203 return nvme_c2h(n
, (uint8_t *)&n
->id_ctrl
, sizeof(n
->id_ctrl
), req
);
4206 static uint16_t nvme_identify_ctrl_csi(NvmeCtrl
*n
, NvmeRequest
*req
)
4208 NvmeIdentify
*c
= (NvmeIdentify
*)&req
->cmd
;
4209 uint8_t id
[NVME_IDENTIFY_DATA_SIZE
] = {};
4210 NvmeIdCtrlNvm
*id_nvm
= (NvmeIdCtrlNvm
*)&id
;
4212 trace_pci_nvme_identify_ctrl_csi(c
->csi
);
4216 id_nvm
->vsl
= n
->params
.vsl
;
4217 id_nvm
->dmrsl
= cpu_to_le32(n
->dmrsl
);
4220 case NVME_CSI_ZONED
:
4221 ((NvmeIdCtrlZoned
*)&id
)->zasl
= n
->params
.zasl
;
4225 return NVME_INVALID_FIELD
| NVME_DNR
;
4228 return nvme_c2h(n
, id
, sizeof(id
), req
);
4231 static uint16_t nvme_identify_ns(NvmeCtrl
*n
, NvmeRequest
*req
, bool active
)
4234 NvmeIdentify
*c
= (NvmeIdentify
*)&req
->cmd
;
4235 uint32_t nsid
= le32_to_cpu(c
->nsid
);
4237 trace_pci_nvme_identify_ns(nsid
);
4239 if (!nvme_nsid_valid(n
, nsid
) || nsid
== NVME_NSID_BROADCAST
) {
4240 return NVME_INVALID_NSID
| NVME_DNR
;
4243 ns
= nvme_ns(n
, nsid
);
4244 if (unlikely(!ns
)) {
4246 ns
= nvme_subsys_ns(n
->subsys
, nsid
);
4248 return nvme_rpt_empty_id_struct(n
, req
);
4251 return nvme_rpt_empty_id_struct(n
, req
);
4255 if (c
->csi
== NVME_CSI_NVM
&& nvme_csi_has_nvm_support(ns
)) {
4256 return nvme_c2h(n
, (uint8_t *)&ns
->id_ns
, sizeof(NvmeIdNs
), req
);
4259 return NVME_INVALID_CMD_SET
| NVME_DNR
;
4262 static uint16_t nvme_identify_ns_attached_list(NvmeCtrl
*n
, NvmeRequest
*req
)
4264 NvmeIdentify
*c
= (NvmeIdentify
*)&req
->cmd
;
4265 uint16_t min_id
= le16_to_cpu(c
->ctrlid
);
4266 uint16_t list
[NVME_CONTROLLER_LIST_SIZE
] = {};
4267 uint16_t *ids
= &list
[1];
4270 int cntlid
, nr_ids
= 0;
4272 trace_pci_nvme_identify_ns_attached_list(min_id
);
4274 if (c
->nsid
== NVME_NSID_BROADCAST
) {
4275 return NVME_INVALID_FIELD
| NVME_DNR
;
4278 ns
= nvme_subsys_ns(n
->subsys
, c
->nsid
);
4280 return NVME_INVALID_FIELD
| NVME_DNR
;
4283 for (cntlid
= min_id
; cntlid
< ARRAY_SIZE(n
->subsys
->ctrls
); cntlid
++) {
4284 ctrl
= nvme_subsys_ctrl(n
->subsys
, cntlid
);
4289 if (!nvme_ns(ctrl
, c
->nsid
)) {
4293 ids
[nr_ids
++] = cntlid
;
4298 return nvme_c2h(n
, (uint8_t *)list
, sizeof(list
), req
);
4301 static uint16_t nvme_identify_ns_csi(NvmeCtrl
*n
, NvmeRequest
*req
,
4305 NvmeIdentify
*c
= (NvmeIdentify
*)&req
->cmd
;
4306 uint32_t nsid
= le32_to_cpu(c
->nsid
);
4308 trace_pci_nvme_identify_ns_csi(nsid
, c
->csi
);
4310 if (!nvme_nsid_valid(n
, nsid
) || nsid
== NVME_NSID_BROADCAST
) {
4311 return NVME_INVALID_NSID
| NVME_DNR
;
4314 ns
= nvme_ns(n
, nsid
);
4315 if (unlikely(!ns
)) {
4317 ns
= nvme_subsys_ns(n
->subsys
, nsid
);
4319 return nvme_rpt_empty_id_struct(n
, req
);
4322 return nvme_rpt_empty_id_struct(n
, req
);
4326 if (c
->csi
== NVME_CSI_NVM
&& nvme_csi_has_nvm_support(ns
)) {
4327 return nvme_rpt_empty_id_struct(n
, req
);
4328 } else if (c
->csi
== NVME_CSI_ZONED
&& ns
->csi
== NVME_CSI_ZONED
) {
4329 return nvme_c2h(n
, (uint8_t *)ns
->id_ns_zoned
, sizeof(NvmeIdNsZoned
),
4333 return NVME_INVALID_FIELD
| NVME_DNR
;
4336 static uint16_t nvme_identify_nslist(NvmeCtrl
*n
, NvmeRequest
*req
,
4340 NvmeIdentify
*c
= (NvmeIdentify
*)&req
->cmd
;
4341 uint32_t min_nsid
= le32_to_cpu(c
->nsid
);
4342 uint8_t list
[NVME_IDENTIFY_DATA_SIZE
] = {};
4343 static const int data_len
= sizeof(list
);
4344 uint32_t *list_ptr
= (uint32_t *)list
;
4347 trace_pci_nvme_identify_nslist(min_nsid
);
4350 * Both FFFFFFFFh (NVME_NSID_BROADCAST) and FFFFFFFFEh are invalid values
4351 * since the Active Namespace ID List should return namespaces with ids
4352 * *higher* than the NSID specified in the command. This is also specified
4353 * in the spec (NVM Express v1.3d, Section 5.15.4).
4355 if (min_nsid
>= NVME_NSID_BROADCAST
- 1) {
4356 return NVME_INVALID_NSID
| NVME_DNR
;
4359 for (i
= 1; i
<= n
->num_namespaces
; i
++) {
4363 ns
= nvme_subsys_ns(n
->subsys
, i
);
4371 if (ns
->params
.nsid
<= min_nsid
) {
4374 list_ptr
[j
++] = cpu_to_le32(ns
->params
.nsid
);
4375 if (j
== data_len
/ sizeof(uint32_t)) {
4380 return nvme_c2h(n
, list
, data_len
, req
);
4383 static uint16_t nvme_identify_nslist_csi(NvmeCtrl
*n
, NvmeRequest
*req
,
4387 NvmeIdentify
*c
= (NvmeIdentify
*)&req
->cmd
;
4388 uint32_t min_nsid
= le32_to_cpu(c
->nsid
);
4389 uint8_t list
[NVME_IDENTIFY_DATA_SIZE
] = {};
4390 static const int data_len
= sizeof(list
);
4391 uint32_t *list_ptr
= (uint32_t *)list
;
4394 trace_pci_nvme_identify_nslist_csi(min_nsid
, c
->csi
);
4397 * Same as in nvme_identify_nslist(), FFFFFFFFh/FFFFFFFFEh are invalid.
4399 if (min_nsid
>= NVME_NSID_BROADCAST
- 1) {
4400 return NVME_INVALID_NSID
| NVME_DNR
;
4403 if (c
->csi
!= NVME_CSI_NVM
&& c
->csi
!= NVME_CSI_ZONED
) {
4404 return NVME_INVALID_FIELD
| NVME_DNR
;
4407 for (i
= 1; i
<= n
->num_namespaces
; i
++) {
4411 ns
= nvme_subsys_ns(n
->subsys
, i
);
4419 if (ns
->params
.nsid
<= min_nsid
|| c
->csi
!= ns
->csi
) {
4422 list_ptr
[j
++] = cpu_to_le32(ns
->params
.nsid
);
4423 if (j
== data_len
/ sizeof(uint32_t)) {
4428 return nvme_c2h(n
, list
, data_len
, req
);
4431 static uint16_t nvme_identify_ns_descr_list(NvmeCtrl
*n
, NvmeRequest
*req
)
4434 NvmeIdentify
*c
= (NvmeIdentify
*)&req
->cmd
;
4435 uint32_t nsid
= le32_to_cpu(c
->nsid
);
4436 uint8_t list
[NVME_IDENTIFY_DATA_SIZE
] = {};
4441 uint8_t v
[NVME_NIDL_UUID
];
4449 struct data
*ns_descrs
= (struct data
*)list
;
4451 trace_pci_nvme_identify_ns_descr_list(nsid
);
4453 if (!nvme_nsid_valid(n
, nsid
) || nsid
== NVME_NSID_BROADCAST
) {
4454 return NVME_INVALID_NSID
| NVME_DNR
;
4457 ns
= nvme_ns(n
, nsid
);
4458 if (unlikely(!ns
)) {
4459 return NVME_INVALID_FIELD
| NVME_DNR
;
4463 * Because the NGUID and EUI64 fields are 0 in the Identify Namespace data
4464 * structure, a Namespace UUID (nidt = 3h) must be reported in the
4465 * Namespace Identification Descriptor. Add the namespace UUID here.
4467 ns_descrs
->uuid
.hdr
.nidt
= NVME_NIDT_UUID
;
4468 ns_descrs
->uuid
.hdr
.nidl
= NVME_NIDL_UUID
;
4469 memcpy(&ns_descrs
->uuid
.v
, ns
->params
.uuid
.data
, NVME_NIDL_UUID
);
4471 ns_descrs
->csi
.hdr
.nidt
= NVME_NIDT_CSI
;
4472 ns_descrs
->csi
.hdr
.nidl
= NVME_NIDL_CSI
;
4473 ns_descrs
->csi
.v
= ns
->csi
;
4475 return nvme_c2h(n
, list
, sizeof(list
), req
);
4478 static uint16_t nvme_identify_cmd_set(NvmeCtrl
*n
, NvmeRequest
*req
)
4480 uint8_t list
[NVME_IDENTIFY_DATA_SIZE
] = {};
4481 static const int data_len
= sizeof(list
);
4483 trace_pci_nvme_identify_cmd_set();
4485 NVME_SET_CSI(*list
, NVME_CSI_NVM
);
4486 NVME_SET_CSI(*list
, NVME_CSI_ZONED
);
4488 return nvme_c2h(n
, list
, data_len
, req
);
4491 static uint16_t nvme_identify(NvmeCtrl
*n
, NvmeRequest
*req
)
4493 NvmeIdentify
*c
= (NvmeIdentify
*)&req
->cmd
;
4495 trace_pci_nvme_identify(nvme_cid(req
), c
->cns
, le16_to_cpu(c
->ctrlid
),
4499 case NVME_ID_CNS_NS
:
4500 return nvme_identify_ns(n
, req
, true);
4501 case NVME_ID_CNS_NS_PRESENT
:
4502 return nvme_identify_ns(n
, req
, false);
4503 case NVME_ID_CNS_NS_ATTACHED_CTRL_LIST
:
4504 return nvme_identify_ns_attached_list(n
, req
);
4505 case NVME_ID_CNS_CS_NS
:
4506 return nvme_identify_ns_csi(n
, req
, true);
4507 case NVME_ID_CNS_CS_NS_PRESENT
:
4508 return nvme_identify_ns_csi(n
, req
, false);
4509 case NVME_ID_CNS_CTRL
:
4510 return nvme_identify_ctrl(n
, req
);
4511 case NVME_ID_CNS_CS_CTRL
:
4512 return nvme_identify_ctrl_csi(n
, req
);
4513 case NVME_ID_CNS_NS_ACTIVE_LIST
:
4514 return nvme_identify_nslist(n
, req
, true);
4515 case NVME_ID_CNS_NS_PRESENT_LIST
:
4516 return nvme_identify_nslist(n
, req
, false);
4517 case NVME_ID_CNS_CS_NS_ACTIVE_LIST
:
4518 return nvme_identify_nslist_csi(n
, req
, true);
4519 case NVME_ID_CNS_CS_NS_PRESENT_LIST
:
4520 return nvme_identify_nslist_csi(n
, req
, false);
4521 case NVME_ID_CNS_NS_DESCR_LIST
:
4522 return nvme_identify_ns_descr_list(n
, req
);
4523 case NVME_ID_CNS_IO_COMMAND_SET
:
4524 return nvme_identify_cmd_set(n
, req
);
4526 trace_pci_nvme_err_invalid_identify_cns(le32_to_cpu(c
->cns
));
4527 return NVME_INVALID_FIELD
| NVME_DNR
;
4531 static uint16_t nvme_abort(NvmeCtrl
*n
, NvmeRequest
*req
)
4533 uint16_t sqid
= le32_to_cpu(req
->cmd
.cdw10
) & 0xffff;
4535 req
->cqe
.result
= 1;
4536 if (nvme_check_sqid(n
, sqid
)) {
4537 return NVME_INVALID_FIELD
| NVME_DNR
;
4540 return NVME_SUCCESS
;
4543 static inline void nvme_set_timestamp(NvmeCtrl
*n
, uint64_t ts
)
4545 trace_pci_nvme_setfeat_timestamp(ts
);
4547 n
->host_timestamp
= le64_to_cpu(ts
);
4548 n
->timestamp_set_qemu_clock_ms
= qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
);
4551 static inline uint64_t nvme_get_timestamp(const NvmeCtrl
*n
)
4553 uint64_t current_time
= qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
);
4554 uint64_t elapsed_time
= current_time
- n
->timestamp_set_qemu_clock_ms
;
4556 union nvme_timestamp
{
4558 uint64_t timestamp
:48;
4566 union nvme_timestamp ts
;
4568 ts
.timestamp
= n
->host_timestamp
+ elapsed_time
;
4570 /* If the host timestamp is non-zero, set the timestamp origin */
4571 ts
.origin
= n
->host_timestamp
? 0x01 : 0x00;
4573 trace_pci_nvme_getfeat_timestamp(ts
.all
);
4575 return cpu_to_le64(ts
.all
);
4578 static uint16_t nvme_get_feature_timestamp(NvmeCtrl
*n
, NvmeRequest
*req
)
4580 uint64_t timestamp
= nvme_get_timestamp(n
);
4582 return nvme_c2h(n
, (uint8_t *)×tamp
, sizeof(timestamp
), req
);
4585 static uint16_t nvme_get_feature(NvmeCtrl
*n
, NvmeRequest
*req
)
4587 NvmeCmd
*cmd
= &req
->cmd
;
4588 uint32_t dw10
= le32_to_cpu(cmd
->cdw10
);
4589 uint32_t dw11
= le32_to_cpu(cmd
->cdw11
);
4590 uint32_t nsid
= le32_to_cpu(cmd
->nsid
);
4592 uint8_t fid
= NVME_GETSETFEAT_FID(dw10
);
4593 NvmeGetFeatureSelect sel
= NVME_GETFEAT_SELECT(dw10
);
4598 static const uint32_t nvme_feature_default
[NVME_FID_MAX
] = {
4599 [NVME_ARBITRATION
] = NVME_ARB_AB_NOLIMIT
,
4602 trace_pci_nvme_getfeat(nvme_cid(req
), nsid
, fid
, sel
, dw11
);
4604 if (!nvme_feature_support
[fid
]) {
4605 return NVME_INVALID_FIELD
| NVME_DNR
;
4608 if (nvme_feature_cap
[fid
] & NVME_FEAT_CAP_NS
) {
4609 if (!nvme_nsid_valid(n
, nsid
) || nsid
== NVME_NSID_BROADCAST
) {
4611 * The Reservation Notification Mask and Reservation Persistence
4612 * features require a status code of Invalid Field in Command when
4613 * NSID is FFFFFFFFh. Since the device does not support those
4614 * features we can always return Invalid Namespace or Format as we
4615 * should do for all other features.
4617 return NVME_INVALID_NSID
| NVME_DNR
;
4620 if (!nvme_ns(n
, nsid
)) {
4621 return NVME_INVALID_FIELD
| NVME_DNR
;
4626 case NVME_GETFEAT_SELECT_CURRENT
:
4628 case NVME_GETFEAT_SELECT_SAVED
:
4629 /* no features are saveable by the controller; fallthrough */
4630 case NVME_GETFEAT_SELECT_DEFAULT
:
4632 case NVME_GETFEAT_SELECT_CAP
:
4633 result
= nvme_feature_cap
[fid
];
4638 case NVME_TEMPERATURE_THRESHOLD
:
4642 * The controller only implements the Composite Temperature sensor, so
4643 * return 0 for all other sensors.
4645 if (NVME_TEMP_TMPSEL(dw11
) != NVME_TEMP_TMPSEL_COMPOSITE
) {
4649 switch (NVME_TEMP_THSEL(dw11
)) {
4650 case NVME_TEMP_THSEL_OVER
:
4651 result
= n
->features
.temp_thresh_hi
;
4653 case NVME_TEMP_THSEL_UNDER
:
4654 result
= n
->features
.temp_thresh_low
;
4658 return NVME_INVALID_FIELD
| NVME_DNR
;
4659 case NVME_ERROR_RECOVERY
:
4660 if (!nvme_nsid_valid(n
, nsid
)) {
4661 return NVME_INVALID_NSID
| NVME_DNR
;
4664 ns
= nvme_ns(n
, nsid
);
4665 if (unlikely(!ns
)) {
4666 return NVME_INVALID_FIELD
| NVME_DNR
;
4669 result
= ns
->features
.err_rec
;
4671 case NVME_VOLATILE_WRITE_CACHE
:
4673 for (i
= 1; i
<= n
->num_namespaces
; i
++) {
4679 result
= blk_enable_write_cache(ns
->blkconf
.blk
);
4684 trace_pci_nvme_getfeat_vwcache(result
? "enabled" : "disabled");
4686 case NVME_ASYNCHRONOUS_EVENT_CONF
:
4687 result
= n
->features
.async_config
;
4689 case NVME_TIMESTAMP
:
4690 return nvme_get_feature_timestamp(n
, req
);
4697 case NVME_TEMPERATURE_THRESHOLD
:
4700 if (NVME_TEMP_TMPSEL(dw11
) != NVME_TEMP_TMPSEL_COMPOSITE
) {
4704 if (NVME_TEMP_THSEL(dw11
) == NVME_TEMP_THSEL_OVER
) {
4705 result
= NVME_TEMPERATURE_WARNING
;
4709 case NVME_NUMBER_OF_QUEUES
:
4710 result
= (n
->params
.max_ioqpairs
- 1) |
4711 ((n
->params
.max_ioqpairs
- 1) << 16);
4712 trace_pci_nvme_getfeat_numq(result
);
4714 case NVME_INTERRUPT_VECTOR_CONF
:
4716 if (iv
>= n
->params
.max_ioqpairs
+ 1) {
4717 return NVME_INVALID_FIELD
| NVME_DNR
;
4721 if (iv
== n
->admin_cq
.vector
) {
4722 result
|= NVME_INTVC_NOCOALESCING
;
4726 result
= nvme_feature_default
[fid
];
4731 req
->cqe
.result
= cpu_to_le32(result
);
4732 return NVME_SUCCESS
;
4735 static uint16_t nvme_set_feature_timestamp(NvmeCtrl
*n
, NvmeRequest
*req
)
4740 ret
= nvme_h2c(n
, (uint8_t *)×tamp
, sizeof(timestamp
), req
);
4745 nvme_set_timestamp(n
, timestamp
);
4747 return NVME_SUCCESS
;
4750 static uint16_t nvme_set_feature(NvmeCtrl
*n
, NvmeRequest
*req
)
4752 NvmeNamespace
*ns
= NULL
;
4754 NvmeCmd
*cmd
= &req
->cmd
;
4755 uint32_t dw10
= le32_to_cpu(cmd
->cdw10
);
4756 uint32_t dw11
= le32_to_cpu(cmd
->cdw11
);
4757 uint32_t nsid
= le32_to_cpu(cmd
->nsid
);
4758 uint8_t fid
= NVME_GETSETFEAT_FID(dw10
);
4759 uint8_t save
= NVME_SETFEAT_SAVE(dw10
);
4762 trace_pci_nvme_setfeat(nvme_cid(req
), nsid
, fid
, save
, dw11
);
4764 if (save
&& !(nvme_feature_cap
[fid
] & NVME_FEAT_CAP_SAVE
)) {
4765 return NVME_FID_NOT_SAVEABLE
| NVME_DNR
;
4768 if (!nvme_feature_support
[fid
]) {
4769 return NVME_INVALID_FIELD
| NVME_DNR
;
4772 if (nvme_feature_cap
[fid
] & NVME_FEAT_CAP_NS
) {
4773 if (nsid
!= NVME_NSID_BROADCAST
) {
4774 if (!nvme_nsid_valid(n
, nsid
)) {
4775 return NVME_INVALID_NSID
| NVME_DNR
;
4778 ns
= nvme_ns(n
, nsid
);
4779 if (unlikely(!ns
)) {
4780 return NVME_INVALID_FIELD
| NVME_DNR
;
4783 } else if (nsid
&& nsid
!= NVME_NSID_BROADCAST
) {
4784 if (!nvme_nsid_valid(n
, nsid
)) {
4785 return NVME_INVALID_NSID
| NVME_DNR
;
4788 return NVME_FEAT_NOT_NS_SPEC
| NVME_DNR
;
4791 if (!(nvme_feature_cap
[fid
] & NVME_FEAT_CAP_CHANGE
)) {
4792 return NVME_FEAT_NOT_CHANGEABLE
| NVME_DNR
;
4796 case NVME_TEMPERATURE_THRESHOLD
:
4797 if (NVME_TEMP_TMPSEL(dw11
) != NVME_TEMP_TMPSEL_COMPOSITE
) {
4801 switch (NVME_TEMP_THSEL(dw11
)) {
4802 case NVME_TEMP_THSEL_OVER
:
4803 n
->features
.temp_thresh_hi
= NVME_TEMP_TMPTH(dw11
);
4805 case NVME_TEMP_THSEL_UNDER
:
4806 n
->features
.temp_thresh_low
= NVME_TEMP_TMPTH(dw11
);
4809 return NVME_INVALID_FIELD
| NVME_DNR
;
4812 if ((n
->temperature
>= n
->features
.temp_thresh_hi
) ||
4813 (n
->temperature
<= n
->features
.temp_thresh_low
)) {
4814 nvme_smart_event(n
, NVME_AER_INFO_SMART_TEMP_THRESH
);
4818 case NVME_ERROR_RECOVERY
:
4819 if (nsid
== NVME_NSID_BROADCAST
) {
4820 for (i
= 1; i
<= n
->num_namespaces
; i
++) {
4827 if (NVME_ID_NS_NSFEAT_DULBE(ns
->id_ns
.nsfeat
)) {
4828 ns
->features
.err_rec
= dw11
;
4836 if (NVME_ID_NS_NSFEAT_DULBE(ns
->id_ns
.nsfeat
)) {
4837 ns
->features
.err_rec
= dw11
;
4840 case NVME_VOLATILE_WRITE_CACHE
:
4841 for (i
= 1; i
<= n
->num_namespaces
; i
++) {
4847 if (!(dw11
& 0x1) && blk_enable_write_cache(ns
->blkconf
.blk
)) {
4848 blk_flush(ns
->blkconf
.blk
);
4851 blk_set_enable_write_cache(ns
->blkconf
.blk
, dw11
& 1);
4856 case NVME_NUMBER_OF_QUEUES
:
4857 if (n
->qs_created
) {
4858 return NVME_CMD_SEQ_ERROR
| NVME_DNR
;
4862 * NVMe v1.3, Section 5.21.1.7: FFFFh is not an allowed value for NCQR
4865 if ((dw11
& 0xffff) == 0xffff || ((dw11
>> 16) & 0xffff) == 0xffff) {
4866 return NVME_INVALID_FIELD
| NVME_DNR
;
4869 trace_pci_nvme_setfeat_numq((dw11
& 0xffff) + 1,
4870 ((dw11
>> 16) & 0xffff) + 1,
4871 n
->params
.max_ioqpairs
,
4872 n
->params
.max_ioqpairs
);
4873 req
->cqe
.result
= cpu_to_le32((n
->params
.max_ioqpairs
- 1) |
4874 ((n
->params
.max_ioqpairs
- 1) << 16));
4876 case NVME_ASYNCHRONOUS_EVENT_CONF
:
4877 n
->features
.async_config
= dw11
;
4879 case NVME_TIMESTAMP
:
4880 return nvme_set_feature_timestamp(n
, req
);
4881 case NVME_COMMAND_SET_PROFILE
:
4883 trace_pci_nvme_err_invalid_iocsci(dw11
& 0x1ff);
4884 return NVME_CMD_SET_CMB_REJECTED
| NVME_DNR
;
4888 return NVME_FEAT_NOT_CHANGEABLE
| NVME_DNR
;
4890 return NVME_SUCCESS
;
4893 static uint16_t nvme_aer(NvmeCtrl
*n
, NvmeRequest
*req
)
4895 trace_pci_nvme_aer(nvme_cid(req
));
4897 if (n
->outstanding_aers
> n
->params
.aerl
) {
4898 trace_pci_nvme_aer_aerl_exceeded();
4899 return NVME_AER_LIMIT_EXCEEDED
;
4902 n
->aer_reqs
[n
->outstanding_aers
] = req
;
4903 n
->outstanding_aers
++;
4905 if (!QTAILQ_EMPTY(&n
->aer_queue
)) {
4906 nvme_process_aers(n
);
4909 return NVME_NO_COMPLETE
;
4912 static void nvme_update_dmrsl(NvmeCtrl
*n
)
4916 for (nsid
= 1; nsid
<= NVME_MAX_NAMESPACES
; nsid
++) {
4917 NvmeNamespace
*ns
= nvme_ns(n
, nsid
);
4922 n
->dmrsl
= MIN_NON_ZERO(n
->dmrsl
,
4923 BDRV_REQUEST_MAX_BYTES
/ nvme_l2b(ns
, 1));
4927 static void nvme_select_iocs_ns(NvmeCtrl
*n
, NvmeNamespace
*ns
)
4929 ns
->iocs
= nvme_cse_iocs_none
;
4932 if (NVME_CC_CSS(n
->bar
.cc
) != NVME_CC_CSS_ADMIN_ONLY
) {
4933 ns
->iocs
= nvme_cse_iocs_nvm
;
4936 case NVME_CSI_ZONED
:
4937 if (NVME_CC_CSS(n
->bar
.cc
) == NVME_CC_CSS_CSI
) {
4938 ns
->iocs
= nvme_cse_iocs_zoned
;
4939 } else if (NVME_CC_CSS(n
->bar
.cc
) == NVME_CC_CSS_NVM
) {
4940 ns
->iocs
= nvme_cse_iocs_nvm
;
4946 static uint16_t nvme_ns_attachment(NvmeCtrl
*n
, NvmeRequest
*req
)
4950 uint16_t list
[NVME_CONTROLLER_LIST_SIZE
] = {};
4951 uint32_t nsid
= le32_to_cpu(req
->cmd
.nsid
);
4952 uint32_t dw10
= le32_to_cpu(req
->cmd
.cdw10
);
4953 bool attach
= !(dw10
& 0xf);
4954 uint16_t *nr_ids
= &list
[0];
4955 uint16_t *ids
= &list
[1];
4959 trace_pci_nvme_ns_attachment(nvme_cid(req
), dw10
& 0xf);
4961 if (!nvme_nsid_valid(n
, nsid
)) {
4962 return NVME_INVALID_NSID
| NVME_DNR
;
4965 ns
= nvme_subsys_ns(n
->subsys
, nsid
);
4967 return NVME_INVALID_FIELD
| NVME_DNR
;
4970 ret
= nvme_h2c(n
, (uint8_t *)list
, 4096, req
);
4976 return NVME_NS_CTRL_LIST_INVALID
| NVME_DNR
;
4979 *nr_ids
= MIN(*nr_ids
, NVME_CONTROLLER_LIST_SIZE
- 1);
4980 for (i
= 0; i
< *nr_ids
; i
++) {
4981 ctrl
= nvme_subsys_ctrl(n
->subsys
, ids
[i
]);
4983 return NVME_NS_CTRL_LIST_INVALID
| NVME_DNR
;
4987 if (nvme_ns(ctrl
, nsid
)) {
4988 return NVME_NS_ALREADY_ATTACHED
| NVME_DNR
;
4991 if (ns
->attached
&& !ns
->params
.shared
) {
4992 return NVME_NS_PRIVATE
| NVME_DNR
;
4995 nvme_attach_ns(ctrl
, ns
);
4996 nvme_select_iocs_ns(ctrl
, ns
);
4998 if (!nvme_ns(ctrl
, nsid
)) {
4999 return NVME_NS_NOT_ATTACHED
| NVME_DNR
;
5002 ctrl
->namespaces
[nsid
- 1] = NULL
;
5005 nvme_update_dmrsl(ctrl
);
5009 * Add namespace id to the changed namespace id list for event clearing
5010 * via Get Log Page command.
5012 if (!test_and_set_bit(nsid
, ctrl
->changed_nsids
)) {
5013 nvme_enqueue_event(ctrl
, NVME_AER_TYPE_NOTICE
,
5014 NVME_AER_INFO_NOTICE_NS_ATTR_CHANGED
,
5015 NVME_LOG_CHANGED_NSLIST
);
5019 return NVME_SUCCESS
;
5022 static uint16_t nvme_format_ns(NvmeCtrl
*n
, NvmeNamespace
*ns
, uint8_t lbaf
,
5023 uint8_t mset
, uint8_t pi
, uint8_t pil
,
5026 int64_t len
, offset
;
5027 struct nvme_aio_format_ctx
*ctx
;
5028 BlockBackend
*blk
= ns
->blkconf
.blk
;
5030 uintptr_t *num_formats
= (uintptr_t *)&req
->opaque
;
5033 if (ns
->params
.zoned
) {
5034 return NVME_INVALID_FORMAT
| NVME_DNR
;
5037 trace_pci_nvme_format_ns(nvme_cid(req
), nvme_nsid(ns
), lbaf
, mset
, pi
, pil
);
5039 if (lbaf
> ns
->id_ns
.nlbaf
) {
5040 return NVME_INVALID_FORMAT
| NVME_DNR
;
5043 ms
= ns
->id_ns
.lbaf
[lbaf
].ms
;
5045 if (pi
&& (ms
< sizeof(NvmeDifTuple
))) {
5046 return NVME_INVALID_FORMAT
| NVME_DNR
;
5049 if (pi
&& pi
> NVME_ID_NS_DPS_TYPE_3
) {
5050 return NVME_INVALID_FIELD
| NVME_DNR
;
5054 nvme_ns_shutdown(ns
);
5055 nvme_ns_cleanup(ns
);
5057 ns
->id_ns
.dps
= (pil
<< 3) | pi
;
5058 ns
->id_ns
.flbas
= lbaf
| (mset
<< 4);
5060 nvme_ns_init_format(ns
);
5062 ns
->status
= NVME_FORMAT_IN_PROGRESS
;
5067 count
= g_new(int, 1);
5073 ctx
= g_new(struct nvme_aio_format_ctx
, 1);
5078 size_t bytes
= MIN(BDRV_REQUEST_MAX_BYTES
, len
);
5082 blk_aio_pwrite_zeroes(blk
, offset
, bytes
, BDRV_REQ_MAY_UNMAP
,
5083 nvme_aio_format_cb
, ctx
);
5091 return NVME_NO_COMPLETE
;
5098 return NVME_SUCCESS
;
5101 static uint16_t nvme_format(NvmeCtrl
*n
, NvmeRequest
*req
)
5104 uint32_t dw10
= le32_to_cpu(req
->cmd
.cdw10
);
5105 uint32_t nsid
= le32_to_cpu(req
->cmd
.nsid
);
5106 uint8_t lbaf
= dw10
& 0xf;
5107 uint8_t mset
= (dw10
>> 4) & 0x1;
5108 uint8_t pi
= (dw10
>> 5) & 0x7;
5109 uint8_t pil
= (dw10
>> 8) & 0x1;
5110 uintptr_t *num_formats
= (uintptr_t *)&req
->opaque
;
5114 trace_pci_nvme_format(nvme_cid(req
), nsid
, lbaf
, mset
, pi
, pil
);
5116 /* 1-initialize; see the comment in nvme_dsm */
5119 if (nsid
!= NVME_NSID_BROADCAST
) {
5120 if (!nvme_nsid_valid(n
, nsid
)) {
5121 return NVME_INVALID_NSID
| NVME_DNR
;
5124 ns
= nvme_ns(n
, nsid
);
5126 return NVME_INVALID_FIELD
| NVME_DNR
;
5129 status
= nvme_format_ns(n
, ns
, lbaf
, mset
, pi
, pil
, req
);
5130 if (status
&& status
!= NVME_NO_COMPLETE
) {
5131 req
->status
= status
;
5134 for (i
= 1; i
<= n
->num_namespaces
; i
++) {
5140 status
= nvme_format_ns(n
, ns
, lbaf
, mset
, pi
, pil
, req
);
5141 if (status
&& status
!= NVME_NO_COMPLETE
) {
5142 req
->status
= status
;
5148 /* account for the 1-initialization */
5149 if (--(*num_formats
)) {
5150 return NVME_NO_COMPLETE
;
5156 static uint16_t nvme_admin_cmd(NvmeCtrl
*n
, NvmeRequest
*req
)
5158 trace_pci_nvme_admin_cmd(nvme_cid(req
), nvme_sqid(req
), req
->cmd
.opcode
,
5159 nvme_adm_opc_str(req
->cmd
.opcode
));
5161 if (!(nvme_cse_acs
[req
->cmd
.opcode
] & NVME_CMD_EFF_CSUPP
)) {
5162 trace_pci_nvme_err_invalid_admin_opc(req
->cmd
.opcode
);
5163 return NVME_INVALID_OPCODE
| NVME_DNR
;
5166 /* SGLs shall not be used for Admin commands in NVMe over PCIe */
5167 if (NVME_CMD_FLAGS_PSDT(req
->cmd
.flags
) != NVME_PSDT_PRP
) {
5168 return NVME_INVALID_FIELD
| NVME_DNR
;
5171 switch (req
->cmd
.opcode
) {
5172 case NVME_ADM_CMD_DELETE_SQ
:
5173 return nvme_del_sq(n
, req
);
5174 case NVME_ADM_CMD_CREATE_SQ
:
5175 return nvme_create_sq(n
, req
);
5176 case NVME_ADM_CMD_GET_LOG_PAGE
:
5177 return nvme_get_log(n
, req
);
5178 case NVME_ADM_CMD_DELETE_CQ
:
5179 return nvme_del_cq(n
, req
);
5180 case NVME_ADM_CMD_CREATE_CQ
:
5181 return nvme_create_cq(n
, req
);
5182 case NVME_ADM_CMD_IDENTIFY
:
5183 return nvme_identify(n
, req
);
5184 case NVME_ADM_CMD_ABORT
:
5185 return nvme_abort(n
, req
);
5186 case NVME_ADM_CMD_SET_FEATURES
:
5187 return nvme_set_feature(n
, req
);
5188 case NVME_ADM_CMD_GET_FEATURES
:
5189 return nvme_get_feature(n
, req
);
5190 case NVME_ADM_CMD_ASYNC_EV_REQ
:
5191 return nvme_aer(n
, req
);
5192 case NVME_ADM_CMD_NS_ATTACHMENT
:
5193 return nvme_ns_attachment(n
, req
);
5194 case NVME_ADM_CMD_FORMAT_NVM
:
5195 return nvme_format(n
, req
);
5200 return NVME_INVALID_OPCODE
| NVME_DNR
;
5203 static void nvme_process_sq(void *opaque
)
5205 NvmeSQueue
*sq
= opaque
;
5206 NvmeCtrl
*n
= sq
->ctrl
;
5207 NvmeCQueue
*cq
= n
->cq
[sq
->cqid
];
5214 while (!(nvme_sq_empty(sq
) || QTAILQ_EMPTY(&sq
->req_list
))) {
5215 addr
= sq
->dma_addr
+ sq
->head
* n
->sqe_size
;
5216 if (nvme_addr_read(n
, addr
, (void *)&cmd
, sizeof(cmd
))) {
5217 trace_pci_nvme_err_addr_read(addr
);
5218 trace_pci_nvme_err_cfs();
5219 n
->bar
.csts
= NVME_CSTS_FAILED
;
5222 nvme_inc_sq_head(sq
);
5224 req
= QTAILQ_FIRST(&sq
->req_list
);
5225 QTAILQ_REMOVE(&sq
->req_list
, req
, entry
);
5226 QTAILQ_INSERT_TAIL(&sq
->out_req_list
, req
, entry
);
5227 nvme_req_clear(req
);
5228 req
->cqe
.cid
= cmd
.cid
;
5229 memcpy(&req
->cmd
, &cmd
, sizeof(NvmeCmd
));
5231 status
= sq
->sqid
? nvme_io_cmd(n
, req
) :
5232 nvme_admin_cmd(n
, req
);
5233 if (status
!= NVME_NO_COMPLETE
) {
5234 req
->status
= status
;
5235 nvme_enqueue_req_completion(cq
, req
);
5240 static void nvme_ctrl_reset(NvmeCtrl
*n
)
5245 for (i
= 1; i
<= n
->num_namespaces
; i
++) {
5254 for (i
= 0; i
< n
->params
.max_ioqpairs
+ 1; i
++) {
5255 if (n
->sq
[i
] != NULL
) {
5256 nvme_free_sq(n
->sq
[i
], n
);
5259 for (i
= 0; i
< n
->params
.max_ioqpairs
+ 1; i
++) {
5260 if (n
->cq
[i
] != NULL
) {
5261 nvme_free_cq(n
->cq
[i
], n
);
5265 while (!QTAILQ_EMPTY(&n
->aer_queue
)) {
5266 NvmeAsyncEvent
*event
= QTAILQ_FIRST(&n
->aer_queue
);
5267 QTAILQ_REMOVE(&n
->aer_queue
, event
, entry
);
5272 n
->outstanding_aers
= 0;
5273 n
->qs_created
= false;
5278 static void nvme_ctrl_shutdown(NvmeCtrl
*n
)
5284 memory_region_msync(&n
->pmr
.dev
->mr
, 0, n
->pmr
.dev
->size
);
5287 for (i
= 1; i
<= n
->num_namespaces
; i
++) {
5293 nvme_ns_shutdown(ns
);
5297 static void nvme_select_iocs(NvmeCtrl
*n
)
5302 for (i
= 1; i
<= n
->num_namespaces
; i
++) {
5308 nvme_select_iocs_ns(n
, ns
);
5312 static int nvme_start_ctrl(NvmeCtrl
*n
)
5314 uint32_t page_bits
= NVME_CC_MPS(n
->bar
.cc
) + 12;
5315 uint32_t page_size
= 1 << page_bits
;
5317 if (unlikely(n
->cq
[0])) {
5318 trace_pci_nvme_err_startfail_cq();
5321 if (unlikely(n
->sq
[0])) {
5322 trace_pci_nvme_err_startfail_sq();
5325 if (unlikely(!n
->bar
.asq
)) {
5326 trace_pci_nvme_err_startfail_nbarasq();
5329 if (unlikely(!n
->bar
.acq
)) {
5330 trace_pci_nvme_err_startfail_nbaracq();
5333 if (unlikely(n
->bar
.asq
& (page_size
- 1))) {
5334 trace_pci_nvme_err_startfail_asq_misaligned(n
->bar
.asq
);
5337 if (unlikely(n
->bar
.acq
& (page_size
- 1))) {
5338 trace_pci_nvme_err_startfail_acq_misaligned(n
->bar
.acq
);
5341 if (unlikely(!(NVME_CAP_CSS(n
->bar
.cap
) & (1 << NVME_CC_CSS(n
->bar
.cc
))))) {
5342 trace_pci_nvme_err_startfail_css(NVME_CC_CSS(n
->bar
.cc
));
5345 if (unlikely(NVME_CC_MPS(n
->bar
.cc
) <
5346 NVME_CAP_MPSMIN(n
->bar
.cap
))) {
5347 trace_pci_nvme_err_startfail_page_too_small(
5348 NVME_CC_MPS(n
->bar
.cc
),
5349 NVME_CAP_MPSMIN(n
->bar
.cap
));
5352 if (unlikely(NVME_CC_MPS(n
->bar
.cc
) >
5353 NVME_CAP_MPSMAX(n
->bar
.cap
))) {
5354 trace_pci_nvme_err_startfail_page_too_large(
5355 NVME_CC_MPS(n
->bar
.cc
),
5356 NVME_CAP_MPSMAX(n
->bar
.cap
));
5359 if (unlikely(NVME_CC_IOCQES(n
->bar
.cc
) <
5360 NVME_CTRL_CQES_MIN(n
->id_ctrl
.cqes
))) {
5361 trace_pci_nvme_err_startfail_cqent_too_small(
5362 NVME_CC_IOCQES(n
->bar
.cc
),
5363 NVME_CTRL_CQES_MIN(n
->bar
.cap
));
5366 if (unlikely(NVME_CC_IOCQES(n
->bar
.cc
) >
5367 NVME_CTRL_CQES_MAX(n
->id_ctrl
.cqes
))) {
5368 trace_pci_nvme_err_startfail_cqent_too_large(
5369 NVME_CC_IOCQES(n
->bar
.cc
),
5370 NVME_CTRL_CQES_MAX(n
->bar
.cap
));
5373 if (unlikely(NVME_CC_IOSQES(n
->bar
.cc
) <
5374 NVME_CTRL_SQES_MIN(n
->id_ctrl
.sqes
))) {
5375 trace_pci_nvme_err_startfail_sqent_too_small(
5376 NVME_CC_IOSQES(n
->bar
.cc
),
5377 NVME_CTRL_SQES_MIN(n
->bar
.cap
));
5380 if (unlikely(NVME_CC_IOSQES(n
->bar
.cc
) >
5381 NVME_CTRL_SQES_MAX(n
->id_ctrl
.sqes
))) {
5382 trace_pci_nvme_err_startfail_sqent_too_large(
5383 NVME_CC_IOSQES(n
->bar
.cc
),
5384 NVME_CTRL_SQES_MAX(n
->bar
.cap
));
5387 if (unlikely(!NVME_AQA_ASQS(n
->bar
.aqa
))) {
5388 trace_pci_nvme_err_startfail_asqent_sz_zero();
5391 if (unlikely(!NVME_AQA_ACQS(n
->bar
.aqa
))) {
5392 trace_pci_nvme_err_startfail_acqent_sz_zero();
5396 n
->page_bits
= page_bits
;
5397 n
->page_size
= page_size
;
5398 n
->max_prp_ents
= n
->page_size
/ sizeof(uint64_t);
5399 n
->cqe_size
= 1 << NVME_CC_IOCQES(n
->bar
.cc
);
5400 n
->sqe_size
= 1 << NVME_CC_IOSQES(n
->bar
.cc
);
5401 nvme_init_cq(&n
->admin_cq
, n
, n
->bar
.acq
, 0, 0,
5402 NVME_AQA_ACQS(n
->bar
.aqa
) + 1, 1);
5403 nvme_init_sq(&n
->admin_sq
, n
, n
->bar
.asq
, 0, 0,
5404 NVME_AQA_ASQS(n
->bar
.aqa
) + 1);
5406 nvme_set_timestamp(n
, 0ULL);
5408 QTAILQ_INIT(&n
->aer_queue
);
5410 nvme_select_iocs(n
);
5415 static void nvme_cmb_enable_regs(NvmeCtrl
*n
)
5417 NVME_CMBLOC_SET_CDPCILS(n
->bar
.cmbloc
, 1);
5418 NVME_CMBLOC_SET_CDPMLS(n
->bar
.cmbloc
, 1);
5419 NVME_CMBLOC_SET_BIR(n
->bar
.cmbloc
, NVME_CMB_BIR
);
5421 NVME_CMBSZ_SET_SQS(n
->bar
.cmbsz
, 1);
5422 NVME_CMBSZ_SET_CQS(n
->bar
.cmbsz
, 0);
5423 NVME_CMBSZ_SET_LISTS(n
->bar
.cmbsz
, 1);
5424 NVME_CMBSZ_SET_RDS(n
->bar
.cmbsz
, 1);
5425 NVME_CMBSZ_SET_WDS(n
->bar
.cmbsz
, 1);
5426 NVME_CMBSZ_SET_SZU(n
->bar
.cmbsz
, 2); /* MBs */
5427 NVME_CMBSZ_SET_SZ(n
->bar
.cmbsz
, n
->params
.cmb_size_mb
);
5430 static void nvme_write_bar(NvmeCtrl
*n
, hwaddr offset
, uint64_t data
,
5433 if (unlikely(offset
& (sizeof(uint32_t) - 1))) {
5434 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_misaligned32
,
5435 "MMIO write not 32-bit aligned,"
5436 " offset=0x%"PRIx64
"", offset
);
5437 /* should be ignored, fall through for now */
5440 if (unlikely(size
< sizeof(uint32_t))) {
5441 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_toosmall
,
5442 "MMIO write smaller than 32-bits,"
5443 " offset=0x%"PRIx64
", size=%u",
5445 /* should be ignored, fall through for now */
5449 case 0xc: /* INTMS */
5450 if (unlikely(msix_enabled(&(n
->parent_obj
)))) {
5451 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_intmask_with_msix
,
5452 "undefined access to interrupt mask set"
5453 " when MSI-X is enabled");
5454 /* should be ignored, fall through for now */
5456 n
->bar
.intms
|= data
& 0xffffffff;
5457 n
->bar
.intmc
= n
->bar
.intms
;
5458 trace_pci_nvme_mmio_intm_set(data
& 0xffffffff, n
->bar
.intmc
);
5461 case 0x10: /* INTMC */
5462 if (unlikely(msix_enabled(&(n
->parent_obj
)))) {
5463 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_intmask_with_msix
,
5464 "undefined access to interrupt mask clr"
5465 " when MSI-X is enabled");
5466 /* should be ignored, fall through for now */
5468 n
->bar
.intms
&= ~(data
& 0xffffffff);
5469 n
->bar
.intmc
= n
->bar
.intms
;
5470 trace_pci_nvme_mmio_intm_clr(data
& 0xffffffff, n
->bar
.intmc
);
5474 trace_pci_nvme_mmio_cfg(data
& 0xffffffff);
5475 /* Windows first sends data, then sends enable bit */
5476 if (!NVME_CC_EN(data
) && !NVME_CC_EN(n
->bar
.cc
) &&
5477 !NVME_CC_SHN(data
) && !NVME_CC_SHN(n
->bar
.cc
))
5482 if (NVME_CC_EN(data
) && !NVME_CC_EN(n
->bar
.cc
)) {
5484 if (unlikely(nvme_start_ctrl(n
))) {
5485 trace_pci_nvme_err_startfail();
5486 n
->bar
.csts
= NVME_CSTS_FAILED
;
5488 trace_pci_nvme_mmio_start_success();
5489 n
->bar
.csts
= NVME_CSTS_READY
;
5491 } else if (!NVME_CC_EN(data
) && NVME_CC_EN(n
->bar
.cc
)) {
5492 trace_pci_nvme_mmio_stopped();
5494 n
->bar
.csts
&= ~NVME_CSTS_READY
;
5496 if (NVME_CC_SHN(data
) && !(NVME_CC_SHN(n
->bar
.cc
))) {
5497 trace_pci_nvme_mmio_shutdown_set();
5498 nvme_ctrl_shutdown(n
);
5500 n
->bar
.csts
|= NVME_CSTS_SHST_COMPLETE
;
5501 } else if (!NVME_CC_SHN(data
) && NVME_CC_SHN(n
->bar
.cc
)) {
5502 trace_pci_nvme_mmio_shutdown_cleared();
5503 n
->bar
.csts
&= ~NVME_CSTS_SHST_COMPLETE
;
5507 case 0x1c: /* CSTS */
5508 if (data
& (1 << 4)) {
5509 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_ssreset_w1c_unsupported
,
5510 "attempted to W1C CSTS.NSSRO"
5511 " but CAP.NSSRS is zero (not supported)");
5512 } else if (data
!= 0) {
5513 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_ro_csts
,
5514 "attempted to set a read only bit"
5515 " of controller status");
5518 case 0x20: /* NSSR */
5519 if (data
== 0x4e564d65) {
5520 trace_pci_nvme_ub_mmiowr_ssreset_unsupported();
5522 /* The spec says that writes of other values have no effect */
5526 case 0x24: /* AQA */
5527 n
->bar
.aqa
= data
& 0xffffffff;
5528 trace_pci_nvme_mmio_aqattr(data
& 0xffffffff);
5530 case 0x28: /* ASQ */
5531 n
->bar
.asq
= size
== 8 ? data
:
5532 (n
->bar
.asq
& ~0xffffffffULL
) | (data
& 0xffffffff);
5533 trace_pci_nvme_mmio_asqaddr(data
);
5535 case 0x2c: /* ASQ hi */
5536 n
->bar
.asq
= (n
->bar
.asq
& 0xffffffff) | (data
<< 32);
5537 trace_pci_nvme_mmio_asqaddr_hi(data
, n
->bar
.asq
);
5539 case 0x30: /* ACQ */
5540 trace_pci_nvme_mmio_acqaddr(data
);
5541 n
->bar
.acq
= size
== 8 ? data
:
5542 (n
->bar
.acq
& ~0xffffffffULL
) | (data
& 0xffffffff);
5544 case 0x34: /* ACQ hi */
5545 n
->bar
.acq
= (n
->bar
.acq
& 0xffffffff) | (data
<< 32);
5546 trace_pci_nvme_mmio_acqaddr_hi(data
, n
->bar
.acq
);
5548 case 0x38: /* CMBLOC */
5549 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_cmbloc_reserved
,
5550 "invalid write to reserved CMBLOC"
5551 " when CMBSZ is zero, ignored");
5553 case 0x3C: /* CMBSZ */
5554 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_cmbsz_readonly
,
5555 "invalid write to read only CMBSZ, ignored");
5557 case 0x50: /* CMBMSC */
5558 if (!NVME_CAP_CMBS(n
->bar
.cap
)) {
5562 n
->bar
.cmbmsc
= size
== 8 ? data
:
5563 (n
->bar
.cmbmsc
& ~0xffffffff) | (data
& 0xffffffff);
5564 n
->cmb
.cmse
= false;
5566 if (NVME_CMBMSC_CRE(data
)) {
5567 nvme_cmb_enable_regs(n
);
5569 if (NVME_CMBMSC_CMSE(data
)) {
5570 hwaddr cba
= NVME_CMBMSC_CBA(data
) << CMBMSC_CBA_SHIFT
;
5571 if (cba
+ int128_get64(n
->cmb
.mem
.size
) < cba
) {
5572 NVME_CMBSTS_SET_CBAI(n
->bar
.cmbsts
, 1);
5585 case 0x54: /* CMBMSC hi */
5586 n
->bar
.cmbmsc
= (n
->bar
.cmbmsc
& 0xffffffff) | (data
<< 32);
5589 case 0xe00: /* PMRCAP */
5590 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrcap_readonly
,
5591 "invalid write to PMRCAP register, ignored");
5593 case 0xe04: /* PMRCTL */
5594 n
->bar
.pmrctl
= data
;
5595 if (NVME_PMRCTL_EN(data
)) {
5596 memory_region_set_enabled(&n
->pmr
.dev
->mr
, true);
5599 memory_region_set_enabled(&n
->pmr
.dev
->mr
, false);
5600 NVME_PMRSTS_SET_NRDY(n
->bar
.pmrsts
, 1);
5601 n
->pmr
.cmse
= false;
5604 case 0xe08: /* PMRSTS */
5605 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrsts_readonly
,
5606 "invalid write to PMRSTS register, ignored");
5608 case 0xe0C: /* PMREBS */
5609 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrebs_readonly
,
5610 "invalid write to PMREBS register, ignored");
5612 case 0xe10: /* PMRSWTP */
5613 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrswtp_readonly
,
5614 "invalid write to PMRSWTP register, ignored");
5616 case 0xe14: /* PMRMSCL */
5617 if (!NVME_CAP_PMRS(n
->bar
.cap
)) {
5621 n
->bar
.pmrmsc
= (n
->bar
.pmrmsc
& ~0xffffffff) | (data
& 0xffffffff);
5622 n
->pmr
.cmse
= false;
5624 if (NVME_PMRMSC_CMSE(n
->bar
.pmrmsc
)) {
5625 hwaddr cba
= NVME_PMRMSC_CBA(n
->bar
.pmrmsc
) << PMRMSC_CBA_SHIFT
;
5626 if (cba
+ int128_get64(n
->pmr
.dev
->mr
.size
) < cba
) {
5627 NVME_PMRSTS_SET_CBAI(n
->bar
.pmrsts
, 1);
5636 case 0xe18: /* PMRMSCU */
5637 if (!NVME_CAP_PMRS(n
->bar
.cap
)) {
5641 n
->bar
.pmrmsc
= (n
->bar
.pmrmsc
& 0xffffffff) | (data
<< 32);
5644 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_invalid
,
5645 "invalid MMIO write,"
5646 " offset=0x%"PRIx64
", data=%"PRIx64
"",
5652 static uint64_t nvme_mmio_read(void *opaque
, hwaddr addr
, unsigned size
)
5654 NvmeCtrl
*n
= (NvmeCtrl
*)opaque
;
5655 uint8_t *ptr
= (uint8_t *)&n
->bar
;
5658 trace_pci_nvme_mmio_read(addr
, size
);
5660 if (unlikely(addr
& (sizeof(uint32_t) - 1))) {
5661 NVME_GUEST_ERR(pci_nvme_ub_mmiord_misaligned32
,
5662 "MMIO read not 32-bit aligned,"
5663 " offset=0x%"PRIx64
"", addr
);
5664 /* should RAZ, fall through for now */
5665 } else if (unlikely(size
< sizeof(uint32_t))) {
5666 NVME_GUEST_ERR(pci_nvme_ub_mmiord_toosmall
,
5667 "MMIO read smaller than 32-bits,"
5668 " offset=0x%"PRIx64
"", addr
);
5669 /* should RAZ, fall through for now */
5672 if (addr
< sizeof(n
->bar
)) {
5674 * When PMRWBM bit 1 is set then read from
5675 * from PMRSTS should ensure prior writes
5676 * made it to persistent media
5678 if (addr
== 0xe08 &&
5679 (NVME_PMRCAP_PMRWBM(n
->bar
.pmrcap
) & 0x02)) {
5680 memory_region_msync(&n
->pmr
.dev
->mr
, 0, n
->pmr
.dev
->size
);
5682 memcpy(&val
, ptr
+ addr
, size
);
5684 NVME_GUEST_ERR(pci_nvme_ub_mmiord_invalid_ofs
,
5685 "MMIO read beyond last register,"
5686 " offset=0x%"PRIx64
", returning 0", addr
);
5692 static void nvme_process_db(NvmeCtrl
*n
, hwaddr addr
, int val
)
5696 if (unlikely(addr
& ((1 << 2) - 1))) {
5697 NVME_GUEST_ERR(pci_nvme_ub_db_wr_misaligned
,
5698 "doorbell write not 32-bit aligned,"
5699 " offset=0x%"PRIx64
", ignoring", addr
);
5703 if (((addr
- 0x1000) >> 2) & 1) {
5704 /* Completion queue doorbell write */
5706 uint16_t new_head
= val
& 0xffff;
5710 qid
= (addr
- (0x1000 + (1 << 2))) >> 3;
5711 if (unlikely(nvme_check_cqid(n
, qid
))) {
5712 NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_cq
,
5713 "completion queue doorbell write"
5714 " for nonexistent queue,"
5715 " sqid=%"PRIu32
", ignoring", qid
);
5718 * NVM Express v1.3d, Section 4.1 state: "If host software writes
5719 * an invalid value to the Submission Queue Tail Doorbell or
5720 * Completion Queue Head Doorbell regiter and an Asynchronous Event
5721 * Request command is outstanding, then an asynchronous event is
5722 * posted to the Admin Completion Queue with a status code of
5723 * Invalid Doorbell Write Value."
5725 * Also note that the spec includes the "Invalid Doorbell Register"
5726 * status code, but nowhere does it specify when to use it.
5727 * However, it seems reasonable to use it here in a similar
5730 if (n
->outstanding_aers
) {
5731 nvme_enqueue_event(n
, NVME_AER_TYPE_ERROR
,
5732 NVME_AER_INFO_ERR_INVALID_DB_REGISTER
,
5733 NVME_LOG_ERROR_INFO
);
5740 if (unlikely(new_head
>= cq
->size
)) {
5741 NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_cqhead
,
5742 "completion queue doorbell write value"
5743 " beyond queue size, sqid=%"PRIu32
","
5744 " new_head=%"PRIu16
", ignoring",
5747 if (n
->outstanding_aers
) {
5748 nvme_enqueue_event(n
, NVME_AER_TYPE_ERROR
,
5749 NVME_AER_INFO_ERR_INVALID_DB_VALUE
,
5750 NVME_LOG_ERROR_INFO
);
5756 trace_pci_nvme_mmio_doorbell_cq(cq
->cqid
, new_head
);
5758 start_sqs
= nvme_cq_full(cq
) ? 1 : 0;
5759 cq
->head
= new_head
;
5762 QTAILQ_FOREACH(sq
, &cq
->sq_list
, entry
) {
5763 timer_mod(sq
->timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + 500);
5765 timer_mod(cq
->timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + 500);
5768 if (cq
->tail
== cq
->head
) {
5769 nvme_irq_deassert(n
, cq
);
5772 /* Submission queue doorbell write */
5774 uint16_t new_tail
= val
& 0xffff;
5777 qid
= (addr
- 0x1000) >> 3;
5778 if (unlikely(nvme_check_sqid(n
, qid
))) {
5779 NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_sq
,
5780 "submission queue doorbell write"
5781 " for nonexistent queue,"
5782 " sqid=%"PRIu32
", ignoring", qid
);
5784 if (n
->outstanding_aers
) {
5785 nvme_enqueue_event(n
, NVME_AER_TYPE_ERROR
,
5786 NVME_AER_INFO_ERR_INVALID_DB_REGISTER
,
5787 NVME_LOG_ERROR_INFO
);
5794 if (unlikely(new_tail
>= sq
->size
)) {
5795 NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_sqtail
,
5796 "submission queue doorbell write value"
5797 " beyond queue size, sqid=%"PRIu32
","
5798 " new_tail=%"PRIu16
", ignoring",
5801 if (n
->outstanding_aers
) {
5802 nvme_enqueue_event(n
, NVME_AER_TYPE_ERROR
,
5803 NVME_AER_INFO_ERR_INVALID_DB_VALUE
,
5804 NVME_LOG_ERROR_INFO
);
5810 trace_pci_nvme_mmio_doorbell_sq(sq
->sqid
, new_tail
);
5812 sq
->tail
= new_tail
;
5813 timer_mod(sq
->timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + 500);
5817 static void nvme_mmio_write(void *opaque
, hwaddr addr
, uint64_t data
,
5820 NvmeCtrl
*n
= (NvmeCtrl
*)opaque
;
5822 trace_pci_nvme_mmio_write(addr
, data
, size
);
5824 if (addr
< sizeof(n
->bar
)) {
5825 nvme_write_bar(n
, addr
, data
, size
);
5827 nvme_process_db(n
, addr
, data
);
5831 static const MemoryRegionOps nvme_mmio_ops
= {
5832 .read
= nvme_mmio_read
,
5833 .write
= nvme_mmio_write
,
5834 .endianness
= DEVICE_LITTLE_ENDIAN
,
5836 .min_access_size
= 2,
5837 .max_access_size
= 8,
5841 static void nvme_cmb_write(void *opaque
, hwaddr addr
, uint64_t data
,
5844 NvmeCtrl
*n
= (NvmeCtrl
*)opaque
;
5845 stn_le_p(&n
->cmb
.buf
[addr
], size
, data
);
5848 static uint64_t nvme_cmb_read(void *opaque
, hwaddr addr
, unsigned size
)
5850 NvmeCtrl
*n
= (NvmeCtrl
*)opaque
;
5851 return ldn_le_p(&n
->cmb
.buf
[addr
], size
);
5854 static const MemoryRegionOps nvme_cmb_ops
= {
5855 .read
= nvme_cmb_read
,
5856 .write
= nvme_cmb_write
,
5857 .endianness
= DEVICE_LITTLE_ENDIAN
,
5859 .min_access_size
= 1,
5860 .max_access_size
= 8,
5864 static void nvme_check_constraints(NvmeCtrl
*n
, Error
**errp
)
5866 NvmeParams
*params
= &n
->params
;
5868 if (params
->num_queues
) {
5869 warn_report("num_queues is deprecated; please use max_ioqpairs "
5872 params
->max_ioqpairs
= params
->num_queues
- 1;
5875 if (n
->namespace.blkconf
.blk
&& n
->subsys
) {
5876 error_setg(errp
, "subsystem support is unavailable with legacy "
5877 "namespace ('drive' property)");
5881 if (params
->max_ioqpairs
< 1 ||
5882 params
->max_ioqpairs
> NVME_MAX_IOQPAIRS
) {
5883 error_setg(errp
, "max_ioqpairs must be between 1 and %d",
5888 if (params
->msix_qsize
< 1 ||
5889 params
->msix_qsize
> PCI_MSIX_FLAGS_QSIZE
+ 1) {
5890 error_setg(errp
, "msix_qsize must be between 1 and %d",
5891 PCI_MSIX_FLAGS_QSIZE
+ 1);
5895 if (!params
->serial
) {
5896 error_setg(errp
, "serial property not set");
5901 if (host_memory_backend_is_mapped(n
->pmr
.dev
)) {
5902 error_setg(errp
, "can't use already busy memdev: %s",
5903 object_get_canonical_path_component(OBJECT(n
->pmr
.dev
)));
5907 if (!is_power_of_2(n
->pmr
.dev
->size
)) {
5908 error_setg(errp
, "pmr backend size needs to be power of 2 in size");
5912 host_memory_backend_set_mapped(n
->pmr
.dev
, true);
5915 if (n
->params
.zasl
> n
->params
.mdts
) {
5916 error_setg(errp
, "zoned.zasl (Zone Append Size Limit) must be less "
5917 "than or equal to mdts (Maximum Data Transfer Size)");
5921 if (!n
->params
.vsl
) {
5922 error_setg(errp
, "vsl must be non-zero");
5927 static void nvme_init_state(NvmeCtrl
*n
)
5929 n
->num_namespaces
= NVME_MAX_NAMESPACES
;
5930 /* add one to max_ioqpairs to account for the admin queue pair */
5931 n
->reg_size
= pow2ceil(sizeof(NvmeBar
) +
5932 2 * (n
->params
.max_ioqpairs
+ 1) * NVME_DB_SIZE
);
5933 n
->sq
= g_new0(NvmeSQueue
*, n
->params
.max_ioqpairs
+ 1);
5934 n
->cq
= g_new0(NvmeCQueue
*, n
->params
.max_ioqpairs
+ 1);
5935 n
->temperature
= NVME_TEMPERATURE
;
5936 n
->features
.temp_thresh_hi
= NVME_TEMPERATURE_WARNING
;
5937 n
->starttime_ms
= qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
);
5938 n
->aer_reqs
= g_new0(NvmeRequest
*, n
->params
.aerl
+ 1);
5941 static void nvme_init_cmb(NvmeCtrl
*n
, PCIDevice
*pci_dev
)
5943 uint64_t cmb_size
= n
->params
.cmb_size_mb
* MiB
;
5945 n
->cmb
.buf
= g_malloc0(cmb_size
);
5946 memory_region_init_io(&n
->cmb
.mem
, OBJECT(n
), &nvme_cmb_ops
, n
,
5947 "nvme-cmb", cmb_size
);
5948 pci_register_bar(pci_dev
, NVME_CMB_BIR
,
5949 PCI_BASE_ADDRESS_SPACE_MEMORY
|
5950 PCI_BASE_ADDRESS_MEM_TYPE_64
|
5951 PCI_BASE_ADDRESS_MEM_PREFETCH
, &n
->cmb
.mem
);
5953 NVME_CAP_SET_CMBS(n
->bar
.cap
, 1);
5955 if (n
->params
.legacy_cmb
) {
5956 nvme_cmb_enable_regs(n
);
5961 static void nvme_init_pmr(NvmeCtrl
*n
, PCIDevice
*pci_dev
)
5963 NVME_PMRCAP_SET_RDS(n
->bar
.pmrcap
, 1);
5964 NVME_PMRCAP_SET_WDS(n
->bar
.pmrcap
, 1);
5965 NVME_PMRCAP_SET_BIR(n
->bar
.pmrcap
, NVME_PMR_BIR
);
5966 /* Turn on bit 1 support */
5967 NVME_PMRCAP_SET_PMRWBM(n
->bar
.pmrcap
, 0x02);
5968 NVME_PMRCAP_SET_CMSS(n
->bar
.pmrcap
, 1);
5970 pci_register_bar(pci_dev
, NVME_PMRCAP_BIR(n
->bar
.pmrcap
),
5971 PCI_BASE_ADDRESS_SPACE_MEMORY
|
5972 PCI_BASE_ADDRESS_MEM_TYPE_64
|
5973 PCI_BASE_ADDRESS_MEM_PREFETCH
, &n
->pmr
.dev
->mr
);
5975 memory_region_set_enabled(&n
->pmr
.dev
->mr
, false);
5978 static int nvme_init_pci(NvmeCtrl
*n
, PCIDevice
*pci_dev
, Error
**errp
)
5980 uint8_t *pci_conf
= pci_dev
->config
;
5981 uint64_t bar_size
, msix_table_size
, msix_pba_size
;
5982 unsigned msix_table_offset
, msix_pba_offset
;
5987 pci_conf
[PCI_INTERRUPT_PIN
] = 1;
5988 pci_config_set_prog_interface(pci_conf
, 0x2);
5990 if (n
->params
.use_intel_id
) {
5991 pci_config_set_vendor_id(pci_conf
, PCI_VENDOR_ID_INTEL
);
5992 pci_config_set_device_id(pci_conf
, 0x5845);
5994 pci_config_set_vendor_id(pci_conf
, PCI_VENDOR_ID_REDHAT
);
5995 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_REDHAT_NVME
);
5998 pci_config_set_class(pci_conf
, PCI_CLASS_STORAGE_EXPRESS
);
5999 pcie_endpoint_cap_init(pci_dev
, 0x80);
6001 bar_size
= QEMU_ALIGN_UP(n
->reg_size
, 4 * KiB
);
6002 msix_table_offset
= bar_size
;
6003 msix_table_size
= PCI_MSIX_ENTRY_SIZE
* n
->params
.msix_qsize
;
6005 bar_size
+= msix_table_size
;
6006 bar_size
= QEMU_ALIGN_UP(bar_size
, 4 * KiB
);
6007 msix_pba_offset
= bar_size
;
6008 msix_pba_size
= QEMU_ALIGN_UP(n
->params
.msix_qsize
, 64) / 8;
6010 bar_size
+= msix_pba_size
;
6011 bar_size
= pow2ceil(bar_size
);
6013 memory_region_init(&n
->bar0
, OBJECT(n
), "nvme-bar0", bar_size
);
6014 memory_region_init_io(&n
->iomem
, OBJECT(n
), &nvme_mmio_ops
, n
, "nvme",
6016 memory_region_add_subregion(&n
->bar0
, 0, &n
->iomem
);
6018 pci_register_bar(pci_dev
, 0, PCI_BASE_ADDRESS_SPACE_MEMORY
|
6019 PCI_BASE_ADDRESS_MEM_TYPE_64
, &n
->bar0
);
6020 ret
= msix_init(pci_dev
, n
->params
.msix_qsize
,
6021 &n
->bar0
, 0, msix_table_offset
,
6022 &n
->bar0
, 0, msix_pba_offset
, 0, &err
);
6024 if (ret
== -ENOTSUP
) {
6025 warn_report_err(err
);
6027 error_propagate(errp
, err
);
6032 if (n
->params
.cmb_size_mb
) {
6033 nvme_init_cmb(n
, pci_dev
);
6037 nvme_init_pmr(n
, pci_dev
);
6043 static void nvme_init_subnqn(NvmeCtrl
*n
)
6045 NvmeSubsystem
*subsys
= n
->subsys
;
6046 NvmeIdCtrl
*id
= &n
->id_ctrl
;
6049 snprintf((char *)id
->subnqn
, sizeof(id
->subnqn
),
6050 "nqn.2019-08.org.qemu:%s", n
->params
.serial
);
6052 pstrcpy((char *)id
->subnqn
, sizeof(id
->subnqn
), (char*)subsys
->subnqn
);
6056 static void nvme_init_ctrl(NvmeCtrl
*n
, PCIDevice
*pci_dev
)
6058 NvmeIdCtrl
*id
= &n
->id_ctrl
;
6059 uint8_t *pci_conf
= pci_dev
->config
;
6061 id
->vid
= cpu_to_le16(pci_get_word(pci_conf
+ PCI_VENDOR_ID
));
6062 id
->ssvid
= cpu_to_le16(pci_get_word(pci_conf
+ PCI_SUBSYSTEM_VENDOR_ID
));
6063 strpadcpy((char *)id
->mn
, sizeof(id
->mn
), "QEMU NVMe Ctrl", ' ');
6064 strpadcpy((char *)id
->fr
, sizeof(id
->fr
), "1.0", ' ');
6065 strpadcpy((char *)id
->sn
, sizeof(id
->sn
), n
->params
.serial
, ' ');
6067 id
->cntlid
= cpu_to_le16(n
->cntlid
);
6069 id
->oaes
= cpu_to_le32(NVME_OAES_NS_ATTR
);
6073 if (n
->params
.use_intel_id
) {
6083 id
->mdts
= n
->params
.mdts
;
6084 id
->ver
= cpu_to_le32(NVME_SPEC_VER
);
6085 id
->oacs
= cpu_to_le16(NVME_OACS_NS_MGMT
| NVME_OACS_FORMAT
);
6086 id
->cntrltype
= 0x1;
6089 * Because the controller always completes the Abort command immediately,
6090 * there can never be more than one concurrently executing Abort command,
6091 * so this value is never used for anything. Note that there can easily be
6092 * many Abort commands in the queues, but they are not considered
6093 * "executing" until processed by nvme_abort.
6095 * The specification recommends a value of 3 for Abort Command Limit (four
6096 * concurrently outstanding Abort commands), so lets use that though it is
6100 id
->aerl
= n
->params
.aerl
;
6101 id
->frmw
= (NVME_NUM_FW_SLOTS
<< 1) | NVME_FRMW_SLOT1_RO
;
6102 id
->lpa
= NVME_LPA_NS_SMART
| NVME_LPA_CSE
| NVME_LPA_EXTENDED
;
6104 /* recommended default value (~70 C) */
6105 id
->wctemp
= cpu_to_le16(NVME_TEMPERATURE_WARNING
);
6106 id
->cctemp
= cpu_to_le16(NVME_TEMPERATURE_CRITICAL
);
6108 id
->sqes
= (0x6 << 4) | 0x6;
6109 id
->cqes
= (0x4 << 4) | 0x4;
6110 id
->nn
= cpu_to_le32(n
->num_namespaces
);
6111 id
->oncs
= cpu_to_le16(NVME_ONCS_WRITE_ZEROES
| NVME_ONCS_TIMESTAMP
|
6112 NVME_ONCS_FEATURES
| NVME_ONCS_DSM
|
6113 NVME_ONCS_COMPARE
| NVME_ONCS_COPY
);
6116 * NOTE: If this device ever supports a command set that does NOT use 0x0
6117 * as a Flush-equivalent operation, support for the broadcast NSID in Flush
6118 * should probably be removed.
6120 * See comment in nvme_io_cmd.
6122 id
->vwc
= NVME_VWC_NSID_BROADCAST_SUPPORT
| NVME_VWC_PRESENT
;
6124 id
->ocfs
= cpu_to_le16(NVME_OCFS_COPY_FORMAT_0
);
6125 id
->sgls
= cpu_to_le32(NVME_CTRL_SGLS_SUPPORT_NO_ALIGN
|
6126 NVME_CTRL_SGLS_BITBUCKET
);
6128 nvme_init_subnqn(n
);
6130 id
->psd
[0].mp
= cpu_to_le16(0x9c4);
6131 id
->psd
[0].enlat
= cpu_to_le32(0x10);
6132 id
->psd
[0].exlat
= cpu_to_le32(0x4);
6135 id
->cmic
|= NVME_CMIC_MULTI_CTRL
;
6138 NVME_CAP_SET_MQES(n
->bar
.cap
, 0x7ff);
6139 NVME_CAP_SET_CQR(n
->bar
.cap
, 1);
6140 NVME_CAP_SET_TO(n
->bar
.cap
, 0xf);
6141 NVME_CAP_SET_CSS(n
->bar
.cap
, NVME_CAP_CSS_NVM
);
6142 NVME_CAP_SET_CSS(n
->bar
.cap
, NVME_CAP_CSS_CSI_SUPP
);
6143 NVME_CAP_SET_CSS(n
->bar
.cap
, NVME_CAP_CSS_ADMIN_ONLY
);
6144 NVME_CAP_SET_MPSMAX(n
->bar
.cap
, 4);
6145 NVME_CAP_SET_CMBS(n
->bar
.cap
, n
->params
.cmb_size_mb
? 1 : 0);
6146 NVME_CAP_SET_PMRS(n
->bar
.cap
, n
->pmr
.dev
? 1 : 0);
6148 n
->bar
.vs
= NVME_SPEC_VER
;
6149 n
->bar
.intmc
= n
->bar
.intms
= 0;
6152 static int nvme_init_subsys(NvmeCtrl
*n
, Error
**errp
)
6160 cntlid
= nvme_subsys_register_ctrl(n
, errp
);
6170 void nvme_attach_ns(NvmeCtrl
*n
, NvmeNamespace
*ns
)
6172 uint32_t nsid
= ns
->params
.nsid
;
6173 assert(nsid
&& nsid
<= NVME_MAX_NAMESPACES
);
6175 n
->namespaces
[nsid
- 1] = ns
;
6178 n
->dmrsl
= MIN_NON_ZERO(n
->dmrsl
,
6179 BDRV_REQUEST_MAX_BYTES
/ nvme_l2b(ns
, 1));
6182 static void nvme_realize(PCIDevice
*pci_dev
, Error
**errp
)
6184 NvmeCtrl
*n
= NVME(pci_dev
);
6186 Error
*local_err
= NULL
;
6188 nvme_check_constraints(n
, &local_err
);
6190 error_propagate(errp
, local_err
);
6194 qbus_create_inplace(&n
->bus
, sizeof(NvmeBus
), TYPE_NVME_BUS
,
6195 &pci_dev
->qdev
, n
->parent_obj
.qdev
.id
);
6198 if (nvme_init_pci(n
, pci_dev
, errp
)) {
6202 if (nvme_init_subsys(n
, errp
)) {
6203 error_propagate(errp
, local_err
);
6206 nvme_init_ctrl(n
, pci_dev
);
6208 /* setup a namespace if the controller drive property was given */
6209 if (n
->namespace.blkconf
.blk
) {
6211 ns
->params
.nsid
= 1;
6213 if (nvme_ns_setup(n
, ns
, errp
)) {
6217 nvme_attach_ns(n
, ns
);
6221 static void nvme_exit(PCIDevice
*pci_dev
)
6223 NvmeCtrl
*n
= NVME(pci_dev
);
6229 for (i
= 1; i
<= n
->num_namespaces
; i
++) {
6235 nvme_ns_cleanup(ns
);
6240 g_free(n
->aer_reqs
);
6242 if (n
->params
.cmb_size_mb
) {
6247 host_memory_backend_set_mapped(n
->pmr
.dev
, false);
6249 msix_uninit(pci_dev
, &n
->bar0
, &n
->bar0
);
6250 memory_region_del_subregion(&n
->bar0
, &n
->iomem
);
6253 static Property nvme_props
[] = {
6254 DEFINE_BLOCK_PROPERTIES(NvmeCtrl
, namespace.blkconf
),
6255 DEFINE_PROP_LINK("pmrdev", NvmeCtrl
, pmr
.dev
, TYPE_MEMORY_BACKEND
,
6256 HostMemoryBackend
*),
6257 DEFINE_PROP_LINK("subsys", NvmeCtrl
, subsys
, TYPE_NVME_SUBSYS
,
6259 DEFINE_PROP_STRING("serial", NvmeCtrl
, params
.serial
),
6260 DEFINE_PROP_UINT32("cmb_size_mb", NvmeCtrl
, params
.cmb_size_mb
, 0),
6261 DEFINE_PROP_UINT32("num_queues", NvmeCtrl
, params
.num_queues
, 0),
6262 DEFINE_PROP_UINT32("max_ioqpairs", NvmeCtrl
, params
.max_ioqpairs
, 64),
6263 DEFINE_PROP_UINT16("msix_qsize", NvmeCtrl
, params
.msix_qsize
, 65),
6264 DEFINE_PROP_UINT8("aerl", NvmeCtrl
, params
.aerl
, 3),
6265 DEFINE_PROP_UINT32("aer_max_queued", NvmeCtrl
, params
.aer_max_queued
, 64),
6266 DEFINE_PROP_UINT8("mdts", NvmeCtrl
, params
.mdts
, 7),
6267 DEFINE_PROP_UINT8("vsl", NvmeCtrl
, params
.vsl
, 7),
6268 DEFINE_PROP_BOOL("use-intel-id", NvmeCtrl
, params
.use_intel_id
, false),
6269 DEFINE_PROP_BOOL("legacy-cmb", NvmeCtrl
, params
.legacy_cmb
, false),
6270 DEFINE_PROP_UINT8("zoned.zasl", NvmeCtrl
, params
.zasl
, 0),
6271 DEFINE_PROP_END_OF_LIST(),
6274 static void nvme_get_smart_warning(Object
*obj
, Visitor
*v
, const char *name
,
6275 void *opaque
, Error
**errp
)
6277 NvmeCtrl
*n
= NVME(obj
);
6278 uint8_t value
= n
->smart_critical_warning
;
6280 visit_type_uint8(v
, name
, &value
, errp
);
6283 static void nvme_set_smart_warning(Object
*obj
, Visitor
*v
, const char *name
,
6284 void *opaque
, Error
**errp
)
6286 NvmeCtrl
*n
= NVME(obj
);
6287 uint8_t value
, old_value
, cap
= 0, index
, event
;
6289 if (!visit_type_uint8(v
, name
, &value
, errp
)) {
6293 cap
= NVME_SMART_SPARE
| NVME_SMART_TEMPERATURE
| NVME_SMART_RELIABILITY
6294 | NVME_SMART_MEDIA_READ_ONLY
| NVME_SMART_FAILED_VOLATILE_MEDIA
;
6295 if (NVME_CAP_PMRS(n
->bar
.cap
)) {
6296 cap
|= NVME_SMART_PMR_UNRELIABLE
;
6299 if ((value
& cap
) != value
) {
6300 error_setg(errp
, "unsupported smart critical warning bits: 0x%x",
6305 old_value
= n
->smart_critical_warning
;
6306 n
->smart_critical_warning
= value
;
6308 /* only inject new bits of smart critical warning */
6309 for (index
= 0; index
< NVME_SMART_WARN_MAX
; index
++) {
6311 if (value
& ~old_value
& event
)
6312 nvme_smart_event(n
, event
);
6316 static const VMStateDescription nvme_vmstate
= {
6321 static void nvme_class_init(ObjectClass
*oc
, void *data
)
6323 DeviceClass
*dc
= DEVICE_CLASS(oc
);
6324 PCIDeviceClass
*pc
= PCI_DEVICE_CLASS(oc
);
6326 pc
->realize
= nvme_realize
;
6327 pc
->exit
= nvme_exit
;
6328 pc
->class_id
= PCI_CLASS_STORAGE_EXPRESS
;
6331 set_bit(DEVICE_CATEGORY_STORAGE
, dc
->categories
);
6332 dc
->desc
= "Non-Volatile Memory Express";
6333 device_class_set_props(dc
, nvme_props
);
6334 dc
->vmsd
= &nvme_vmstate
;
6337 static void nvme_instance_init(Object
*obj
)
6339 NvmeCtrl
*n
= NVME(obj
);
6341 device_add_bootindex_property(obj
, &n
->namespace.blkconf
.bootindex
,
6342 "bootindex", "/namespace@1,0",
6345 object_property_add(obj
, "smart_critical_warning", "uint8",
6346 nvme_get_smart_warning
,
6347 nvme_set_smart_warning
, NULL
, NULL
);
6350 static const TypeInfo nvme_info
= {
6352 .parent
= TYPE_PCI_DEVICE
,
6353 .instance_size
= sizeof(NvmeCtrl
),
6354 .instance_init
= nvme_instance_init
,
6355 .class_init
= nvme_class_init
,
6356 .interfaces
= (InterfaceInfo
[]) {
6357 { INTERFACE_PCIE_DEVICE
},
6362 static const TypeInfo nvme_bus_info
= {
6363 .name
= TYPE_NVME_BUS
,
6365 .instance_size
= sizeof(NvmeBus
),
6368 static void nvme_register_types(void)
6370 type_register_static(&nvme_info
);
6371 type_register_static(&nvme_bus_info
);
6374 type_init(nvme_register_types
)